system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | # include <stdio.h>
# include <stdint.h>
# include "hip/hip_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
hipSetDevice(1);
measure_global();
hipDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 592*256*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
hipDeviceReset();
hipError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = hipMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != hipSuccess) {
printf("Error 1.0 is %s\n", hipGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// 16MB*33
for (i=0; i<33; i++){
h_a[i * 1024 * 256 * 16] = (i+1)*256*1024*16;
h_a[i * 1024 * 256 * 16+1] = (1+i) * 1024 * 256 * 16+1;
}
// 1MB*63
for (i=0; i<63 ; i++){
h_a[(528+i)*256*1024] = (529+i)*256*1024;
}
h_a[528*256*1024+1] = 528*256*1024+2;
h_a[528*256*1024+2] = 528*256*1024+3;
h_a[528*256*1024+3] = 528*256*1024+1;
h_a[591*256*1024 ] = 1;
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = hipMemcpy(d_a, h_a, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
if (error_id != hipSuccess) {
printf("Error 1.1 is %s\n", hipGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *duration;
error_id = hipMalloc ((void **) &duration, sizeof(unsigned int)*160);
if (error_id != hipSuccess) {
printf("Error 1.2 is %s\n", hipGetErrorString(error_id));
}
unsigned int *d_index;
error_id = hipMalloc( (void **) &d_index, sizeof(unsigned int)*160 );
if (error_id != hipSuccess) {
printf("Error 1.3 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
hipDeviceSynchronize ();
error_id = hipGetLastError();
if (error_id != hipSuccess) {
printf("Error kernel is %s\n", hipGetErrorString(error_id));
}
/* copy results from GPU to CPU */
hipDeviceSynchronize ();
error_id = hipMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.0 is %s\n", hipGetErrorString(error_id));
}
error_id = hipMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.1 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
for(i=0;i<160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
hipFree(d_a);
hipFree(d_index);
hipFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
hipDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[160];
__shared__ unsigned int s_index[160];
int k;
for(k=0; k<160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
// for (k = 0; k < iterations*256; k++)
// j = my_array[j];
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} | .text
.file "pattern_fermi.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x4082800000000000 # double 592
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1, %edi
callq hipSetDevice
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movl $155189248, %edi # imm = 0x9400000
movl $1, %esi
callq _Z25parametric_measure_globalii
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14measure_globalv
.LCPI1_0:
.quad 0x4082800000000000 # double 592
.text
.globl _Z14measure_globalv
.p2align 4, 0x90
.type _Z14measure_globalv,@function
_Z14measure_globalv: # @_Z14measure_globalv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movl $155189248, %edi # imm = 0x9400000
movl $1, %esi
callq _Z25parametric_measure_globalii
movl $.Lstr, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z14measure_globalv, .Lfunc_end1-_Z14measure_globalv
.cfi_endproc
# -- End function
.globl _Z25parametric_measure_globalii # -- Begin function _Z25parametric_measure_globalii
.p2align 4, 0x90
.type _Z25parametric_measure_globalii,@function
_Z25parametric_measure_globalii: # @_Z25parametric_measure_globalii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r12d
callq hipDeviceReset
movslq %r12d, %r14
leaq 8(,%r14,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_2:
testl %r12d, %r12d
jle .LBB2_3
# %bb.24: # %.lr.ph.preheader
movl %r12d, %edx
shlq $2, %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_3: # %.preheader79.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_4: # %.preheader79
# =>This Inner Loop Header: Depth=1
leaq 4194304(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
leal 4194305(%rax), %edx
movl %edx, 4(%rbx,%rax,4)
movq %rcx, %rax
cmpq $138412032, %rcx # imm = 0x8400000
jne .LBB2_4
# %bb.5: # %.preheader
movl $138412032, %eax # imm = 0x8400000
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
leaq 262144(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $154927104, %rcx # imm = 0x93C0000
jne .LBB2_6
# %bb.7:
movabsq $594475163836219394, %rax # imm = 0x840000308400002
movq %rax, 553648132(%rbx)
movl $138412033, 553648140(%rbx) # imm = 0x8400001
movl $1, 619708416(%rbx)
movq $0, (%rbx,%r14,4)
movq 24(%rsp), %rdi
shlq $2, %r14
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_9
# %bb.8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_9:
movl $640, %edi # imm = 0x280
callq malloc
movq %rax, %r14
movl $640, %edi # imm = 0x280
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $640, %esi # imm = 0x280
callq hipMalloc
testl %eax, %eax
je .LBB2_11
# %bb.10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_11:
leaq 8(%rsp), %rdi
movl $640, %esi # imm = 0x280
callq hipMalloc
testl %eax, %eax
je .LBB2_13
# %bb.12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_13:
callq hipDeviceSynchronize
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movl %r12d, 36(%rsp)
movl %ebp, 32(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14global_latencyPjiiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB2_17
# %bb.16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_17:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $640, %edx # imm = 0x280
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_19
# %bb.18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_19:
movq 8(%rsp), %rsi
movl $640, %edx # imm = 0x280
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_21
# %bb.20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_21:
callq hipDeviceSynchronize
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_22: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl (%r15,%r12,4), %edx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $160, %r12
jne .LBB2_22
# %bb.23:
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z25parametric_measure_globalii, .Lfunc_end2-_Z25parametric_measure_globalii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__global_latencyPjiiS_S_ # -- Begin function _Z29__device_stub__global_latencyPjiiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__global_latencyPjiiS_S_,@function
_Z29__device_stub__global_latencyPjiiS_S_: # @_Z29__device_stub__global_latencyPjiiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14global_latencyPjiiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z29__device_stub__global_latencyPjiiS_S_, .Lfunc_end3-_Z29__device_stub__global_latencyPjiiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14global_latencyPjiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n"
.size .L.str, 65
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error 1.0 is %s\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error 1.1 is %s\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error 1.2 is %s\n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error 1.3 is %s\n"
.size .L.str.5, 17
.type _Z14global_latencyPjiiS_S_,@object # @_Z14global_latencyPjiiS_S_
.section .rodata,"a",@progbits
.globl _Z14global_latencyPjiiS_S_
.p2align 3, 0x0
_Z14global_latencyPjiiS_S_:
.quad _Z29__device_stub__global_latencyPjiiS_S_
.size _Z14global_latencyPjiiS_S_, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Error kernel is %s\n"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error 2.0 is %s\n"
.size .L.str.7, 17
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error 2.1 is %s\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d\t %d\n"
.size .L.str.9, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14global_latencyPjiiS_S_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "===============================================\n"
.size .Lstr, 49
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__global_latencyPjiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14global_latencyPjiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ed11b_00000000-6_pattern_fermi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
.type _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_, @function
_Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14global_latencyPjiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_, .-_Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
.globl _Z14global_latencyPjiiS_S_
.type _Z14global_latencyPjiiS_S_, @function
_Z14global_latencyPjiiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14global_latencyPjiiS_S_, .-_Z14global_latencyPjiiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error 1.0 is %s\n"
.LC1:
.string "Error 1.1 is %s\n"
.LC2:
.string "Error 1.2 is %s\n"
.LC3:
.string "Error 1.3 is %s\n"
.LC4:
.string "Error kernel is %s\n"
.LC5:
.string "Error 2.0 is %s\n"
.LC6:
.string "Error 2.1 is %s\n"
.LC7:
.string "%d\t %d\n"
.text
.globl _Z25parametric_measure_globalii
.type _Z25parametric_measure_globalii, @function
_Z25parametric_measure_globalii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r12d
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaDeviceReset@PLT
leal 2(%r12), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
.L12:
testl %r12d, %r12d
jle .L13
movq %rbp, %rax
leaq -8(%rbp,%rbx), %rdx
.L14:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
.L13:
movq %rbp, %rdx
movl $4194305, %eax
.L15:
leal -1(%rax), %ecx
movl %ecx, (%rdx)
movl %eax, 4(%rdx)
addq $16777216, %rdx
addl $4194304, %eax
cmpl $142606337, %eax
jne .L15
leaq 553648128(%rbp), %rdx
movl $138674176, %eax
.L16:
movl %eax, (%rdx)
addl $262144, %eax
addq $1048576, %rdx
cmpl $155189248, %eax
jne .L16
movl $138412034, 553648132(%rbp)
movl $138412035, 553648136(%rbp)
movl $138412033, 553648140(%rbp)
movl $1, 619708416(%rbp)
leaq -8(%rbx), %rdx
movl $0, -8(%rbp,%rbx)
movl $0, -4(%rbp,%rbx)
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
.L17:
movl $640, %edi
call malloc@PLT
movq %rax, %r15
movl $640, %edi
call malloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $640, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
.L18:
leaq 24(%rsp), %rdi
movl $640, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
.L19:
call cudaThreadSynchronize@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L20:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
.L21:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $640, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
.L22:
movl $2, %ecx
movl $640, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
.L23:
call cudaThreadSynchronize@PLT
movl $0, %ebx
leaq .LC7(%rip), %r12
.L24:
movl (%r14,%rbx), %ecx
movl (%r15,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $640, %rbx
jne .L24
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L35:
movq 24(%rsp), %r8
movq 16(%rsp), %rcx
movl %r13d, %edx
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
jmp .L20
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z25parametric_measure_globalii, .-_Z25parametric_measure_globalii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n"
.align 8
.LC10:
.string "===============================================\n\n"
.text
.globl _Z14measure_globalv
.type _Z14measure_globalv, @function
_Z14measure_globalv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %esi
movl $155189248, %edi
call _Z25parametric_measure_globalii
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z14measure_globalv, .-_Z14measure_globalv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call cudaSetDevice@PLT
call _Z14measure_globalv
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z14global_latencyPjiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z14global_latencyPjiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1082294272
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pattern_fermi.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x4082800000000000 # double 592
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1, %edi
callq hipSetDevice
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movl $155189248, %edi # imm = 0x9400000
movl $1, %esi
callq _Z25parametric_measure_globalii
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14measure_globalv
.LCPI1_0:
.quad 0x4082800000000000 # double 592
.text
.globl _Z14measure_globalv
.p2align 4, 0x90
.type _Z14measure_globalv,@function
_Z14measure_globalv: # @_Z14measure_globalv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movl $155189248, %edi # imm = 0x9400000
movl $1, %esi
callq _Z25parametric_measure_globalii
movl $.Lstr, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z14measure_globalv, .Lfunc_end1-_Z14measure_globalv
.cfi_endproc
# -- End function
.globl _Z25parametric_measure_globalii # -- Begin function _Z25parametric_measure_globalii
.p2align 4, 0x90
.type _Z25parametric_measure_globalii,@function
_Z25parametric_measure_globalii: # @_Z25parametric_measure_globalii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r12d
callq hipDeviceReset
movslq %r12d, %r14
leaq 8(,%r14,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_2:
testl %r12d, %r12d
jle .LBB2_3
# %bb.24: # %.lr.ph.preheader
movl %r12d, %edx
shlq $2, %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_3: # %.preheader79.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_4: # %.preheader79
# =>This Inner Loop Header: Depth=1
leaq 4194304(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
leal 4194305(%rax), %edx
movl %edx, 4(%rbx,%rax,4)
movq %rcx, %rax
cmpq $138412032, %rcx # imm = 0x8400000
jne .LBB2_4
# %bb.5: # %.preheader
movl $138412032, %eax # imm = 0x8400000
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
leaq 262144(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $154927104, %rcx # imm = 0x93C0000
jne .LBB2_6
# %bb.7:
movabsq $594475163836219394, %rax # imm = 0x840000308400002
movq %rax, 553648132(%rbx)
movl $138412033, 553648140(%rbx) # imm = 0x8400001
movl $1, 619708416(%rbx)
movq $0, (%rbx,%r14,4)
movq 24(%rsp), %rdi
shlq $2, %r14
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_9
# %bb.8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_9:
movl $640, %edi # imm = 0x280
callq malloc
movq %rax, %r14
movl $640, %edi # imm = 0x280
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $640, %esi # imm = 0x280
callq hipMalloc
testl %eax, %eax
je .LBB2_11
# %bb.10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_11:
leaq 8(%rsp), %rdi
movl $640, %esi # imm = 0x280
callq hipMalloc
testl %eax, %eax
je .LBB2_13
# %bb.12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_13:
callq hipDeviceSynchronize
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movl %r12d, 36(%rsp)
movl %ebp, 32(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14global_latencyPjiiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB2_17
# %bb.16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_17:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $640, %edx # imm = 0x280
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_19
# %bb.18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_19:
movq 8(%rsp), %rsi
movl $640, %edx # imm = 0x280
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_21
# %bb.20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_21:
callq hipDeviceSynchronize
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_22: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl (%r15,%r12,4), %edx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $160, %r12
jne .LBB2_22
# %bb.23:
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z25parametric_measure_globalii, .Lfunc_end2-_Z25parametric_measure_globalii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__global_latencyPjiiS_S_ # -- Begin function _Z29__device_stub__global_latencyPjiiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__global_latencyPjiiS_S_,@function
_Z29__device_stub__global_latencyPjiiS_S_: # @_Z29__device_stub__global_latencyPjiiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14global_latencyPjiiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z29__device_stub__global_latencyPjiiS_S_, .Lfunc_end3-_Z29__device_stub__global_latencyPjiiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14global_latencyPjiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n"
.size .L.str, 65
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error 1.0 is %s\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error 1.1 is %s\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error 1.2 is %s\n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error 1.3 is %s\n"
.size .L.str.5, 17
.type _Z14global_latencyPjiiS_S_,@object # @_Z14global_latencyPjiiS_S_
.section .rodata,"a",@progbits
.globl _Z14global_latencyPjiiS_S_
.p2align 3, 0x0
_Z14global_latencyPjiiS_S_:
.quad _Z29__device_stub__global_latencyPjiiS_S_
.size _Z14global_latencyPjiiS_S_, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Error kernel is %s\n"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error 2.0 is %s\n"
.size .L.str.7, 17
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error 2.1 is %s\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d\t %d\n"
.size .L.str.9, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14global_latencyPjiiS_S_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "===============================================\n"
.size .Lstr, 49
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__global_latencyPjiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14global_latencyPjiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <sys/time.h>
inline double nowSec()
{
struct timeval t;
struct timezone tzp;
gettimeofday(&t, &tzp);
return t.tv_sec + t.tv_usec*1e-6;
}
__host__ void host_mmul (int *A, int *B, int *C, int N)
{
for(int i=0; i<N; i++)
{
for (int j=0; j<N; j++)
{
for(int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
}
}
__global__ void global_mmul (int *A, int *B, int *C, int N)
{
int i=blockIdx.y;
int j=blockIdx.x;
for (int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
#ifdef PRINT
void printMtx (int *m, int N)
{
for (int i=0; i<N*N; i++)
{
if (i>0 && i%N == 0)
fprintf(stderr, "\n");
fprintf(stderr, "%d\t",*m);
m++;
}
}
#endif
int main(int argc, char **argv)
{
if (argc != 2)
{
puts("Usage: Matrix_mult [N]\n");
return -1;
}
int N=atoi(argv[1]);
int NN=N*N;
int i;
int *A, *B, *C_host, *C_device;
int *ptrA, *ptrB;
cudaMallocManaged(&A, NN*sizeof(int));
cudaMallocManaged(&B, NN*sizeof(int));
cudaMallocManaged(&C_device, NN*sizeof(int));
cudaMallocManaged(&C_host, NN*sizeof(int));
cudaDeviceSynchronize(); //attende che la memoria sia allocata
for (i=0, ptrA=A, ptrB=B ; i<N; i++)
{
for (int j=0; j<N; j++)
{
*ptrA=i*N+j;
*ptrB=0;
if (i==j)
*ptrB=1;
ptrA++;
ptrB++;
}
}
#ifdef PRINT
fprintf(stderr,"A=\n");
printMtx(A, N);
fprintf(stderr,"\n\nB=\n");
printMtx(B, N);
fprintf(stderr,"\n\n");
#endif
double t_begin_cpu = nowSec();
host_mmul(A, B, C_host, N);
double t_end_cpu = nowSec();
dim3 blockPerGrid(N,N);
dim3 threadPerBlock(1,1);
double t_begin_gpu = nowSec();
global_mmul <<< blockPerGrid, threadPerBlock >>> (A,B,C_device,N);
cudaDeviceSynchronize();
double t_end_gpu = nowSec();
#ifdef PRINT
fprintf(stderr,"C_host=\n");
printMtx(C_host, N);
fprintf(stderr,"\n\nC_device=\n");
printMtx(C_device, N);
fprintf(stderr,"\n");
#endif
printf("Elapsed time CPU: %f sec\n", t_end_cpu - t_begin_cpu);
printf("Elapsed time GPU: %f sec\n", t_end_gpu - t_begin_gpu);
cudaFree(A);
cudaFree(B);
cudaFree(C_device);
cudaFree(C_host);
return 0;
} | code for sm_80
Function : _Z11global_mmulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0050*/ IADD3 R5, R0.reuse, -0x1, RZ ; /* 0xffffffff00057810 */
/* 0x040fe20007ffe0ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0080*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0090*/ LOP3.LUT R10, R0, 0x3, RZ, 0xc0, !PT ; /* 0x00000003000a7812 */
/* 0x000fe200078ec0ff */
/*00a0*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x001fe200078e02ff */
/*00b0*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x002fc80000011406 */
/*00c0*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fe40000011407 */
/*00d0*/ IADD3 R3, P0, R7, R6, RZ ; /* 0x0000000607037210 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R4, R8, R9, RZ, P0, !PT ; /* 0x0000000908047210 */
/* 0x000fe400007fe4ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*0100*/ LEA R2, P1, R3, c[0x0][0x170], 0x2 ; /* 0x00005c0003027a11 */
/* 0x000fc800078210ff */
/*0110*/ LEA.HI.X R3, R3, c[0x0][0x174], R4, 0x2, P1 ; /* 0x00005d0003037a11 */
/* 0x000fce00008f1404 */
/*0120*/ @!P0 BRA 0xc90 ; /* 0x00000b6000008947 */
/* 0x000fea0003800000 */
/*0130*/ LEA R4, P0, R7.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580007047a11 */
/* 0x040fe200078010ff */
/*0140*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000162000c1e1900 */
/*0150*/ IADD3 R11, -R10, c[0x0][0x178], RZ ; /* 0x00005e000a0b7a10 */
/* 0x000fe40007ffe1ff */
/*0160*/ LEA.HI.X R5, R7, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590007057a11 */
/* 0x000fe400000f1408 */
/*0170*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f04270 */
/*0180*/ LEA R14, P1, R6, c[0x0][0x168], 0x2 ; /* 0x00005a00060e7a11 */
/* 0x000fe400078210ff */
/*0190*/ IADD3 R4, P2, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fc40007f5e0ff */
/*01a0*/ LEA.HI.X R15, R6, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b00060f7a11 */
/* 0x000fe400008f1409 */
/*01b0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe400017fe4ff */
/*01c0*/ MOV R12, RZ ; /* 0x000000ff000c7202 */
/* 0x000fc60000000f00 */
/*01d0*/ @!P0 BRA 0xad0 ; /* 0x000008f000008947 */
/* 0x001fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x7a0 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x004ea8000c1e1900 */
/*0230*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD R13, R16, R17, R13 ; /* 0x00000011100d7224 */
/* 0x024fe400078e020d */
/*0250*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0260*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0270*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R19, [R4.64+-0x4] ; /* 0xfffffc0404137981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD R21, R18, R19, R13 ; /* 0x0000001312157224 */
/* 0x004fc400078e020d */
/*02a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*02b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02c0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0300*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x001ee2000c1e1900 */
/*0330*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0340*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x008fca00078e0217 */
/*0350*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0360*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000e64000c1e1900 */
/*0380*/ IMAD R21, R20, R18, R13 ; /* 0x0000001214157224 */
/* 0x002fc400078e020d */
/*0390*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*03a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03b0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*03f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R13, [R4.64+0x10] ; /* 0x00001004040d7981 */
/* 0x001ee2000c1e1900 */
/*0420*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0430*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x008fca00078e0217 */
/*0440*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0450*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0460*/ LDG.E R18, [R4.64+0x14] ; /* 0x0000140404127981 */
/* 0x000e64000c1e1900 */
/*0470*/ IMAD R21, R20, R18, R13 ; /* 0x0000001214157224 */
/* 0x002fc400078e020d */
/*0480*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0490*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04a0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*04d0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*04e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*04f0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x001ee2000c1e1900 */
/*0510*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0520*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x008fca00078e0217 */
/*0530*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0540*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0550*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000e64000c1e1900 */
/*0560*/ IMAD R21, R20, R18, R13 ; /* 0x0000001214157224 */
/* 0x002fc400078e020d */
/*0570*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0580*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0590*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R14, [R4.64+0x24] ; /* 0x00002404040e7981 */
/* 0x000ea4000c1e1900 */
/*05b0*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*05c0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*05d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R13, [R4.64+0x28] ; /* 0x00002804040d7981 */
/* 0x001ea2000c1e1900 */
/*0600*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0610*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x004fca00078e0217 */
/*0620*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0630*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R18, [R4.64+0x2c] ; /* 0x00002c0404127981 */
/* 0x000ea4000c1e1900 */
/*0650*/ IMAD R25, R20, R18, R13 ; /* 0x0000001214197224 */
/* 0x004fc400078e020d */
/*0660*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0670*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0680*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e68000c1e1900 */
/*0690*/ LDG.E R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x000e62000c1e1900 */
/*06a0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ IMAD R23, R20, R14, R25 ; /* 0x0000000e14177224 */
/* 0x002fc400078e0219 */
/*06c0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc600078e0212 */
/*06d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*06e0*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ee8000c1e1900 */
/*06f0*/ LDG.E R13, [R4.64+0x34] ; /* 0x00003404040d7981 */
/* 0x0010e2000c1e1900 */
/*0700*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*0710*/ IADD3 R16, P2, R4, 0x40, RZ ; /* 0x0000004004107810 */
/* 0x000fc40007f5e0ff */
/*0720*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fe40007ffe0ff */
/*0730*/ IADD3.X R17, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff117210 */
/* 0x000fe400017fe4ff */
/*0740*/ MOV R4, R16 ; /* 0x0000001000047202 */
/* 0x001fe40000000f00 */
/*0750*/ MOV R5, R17 ; /* 0x0000001100057202 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD R13, R14, R13, R23 ; /* 0x0000000d0e0d7224 */
/* 0x008fe400078e0217 */
/*0770*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0214 */
/*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e2000c101904 */
/*0790*/ @P1 BRA 0x220 ; /* 0xfffffa8000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xab0 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*07d0*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ee4000c1e1900 */
/*07e0*/ IMAD R13, R16, R17, R13 ; /* 0x00000011100d7224 */
/* 0x02cfe400078e020d */
/*07f0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0800*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0810*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0820*/ LDG.E R19, [R4.64+-0x4] ; /* 0xfffffc0404137981 */
/* 0x000ea4000c1e1900 */
/*0830*/ IMAD R21, R18, R19, R13 ; /* 0x0000001312157224 */
/* 0x004fc400078e020d */
/*0840*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0850*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0860*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea4000c1e1900 */
/*0880*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*0890*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*08a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08b0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*08c0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x001ee2000c1e1900 */
/*08d0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*08e0*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x008fca00078e0217 */
/*08f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0900*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0910*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000e64000c1e1900 */
/*0920*/ IMAD R21, R20, R18, R13 ; /* 0x0000001214157224 */
/* 0x002fc400078e020d */
/*0930*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0940*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0950*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x000ea4000c1e1900 */
/*0970*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*0980*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0990*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09a0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R13, [R4.64+0x10] ; /* 0x00001004040d7981 */
/* 0x001ea2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*09d0*/ IMAD R25, R20, R13, R23 ; /* 0x0000000d14197224 */
/* 0x004fca00078e0217 */
/*09e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*09f0*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea8000c1e1900 */
/*0a00*/ LDG.E R13, [R4.64+0x14] ; /* 0x00001404040d7981 */
/* 0x0000a2000c1e1900 */
/*0a10*/ IADD3 R18, P1, R4, 0x20, RZ ; /* 0x0000002004127810 */
/* 0x000fe20007f3e0ff */
/*0a20*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0210 */
/*0a30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a40*/ IADD3 R12, R12, 0x8, RZ ; /* 0x000000080c0c7810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.X R19, RZ, RZ, R5, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0605 */
/*0a60*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ MOV R4, R18 ; /* 0x0000001200047202 */
/* 0x001fe40000000f00 */
/*0a80*/ MOV R5, R19 ; /* 0x0000001300057202 */
/* 0x000fe20000000f00 */
/*0a90*/ IMAD R13, R20, R13, R25 ; /* 0x0000000d140d7224 */
/* 0x004fca00078e0219 */
/*0aa0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e4000c101904 */
/*0ab0*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0ac0*/ @!P0 BRA 0xc90 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0ae0*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ee4000c1e1900 */
/*0af0*/ IMAD R13, R16, R17, R13 ; /* 0x00000011100d7224 */
/* 0x02efe400078e020d */
/*0b00*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0b10*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0b20*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0b30*/ LDG.E R19, [R4.64+-0x4] ; /* 0xfffffc0404137981 */
/* 0x000ea4000c1e1900 */
/*0b40*/ IMAD R23, R18, R19, R13 ; /* 0x0000001312177224 */
/* 0x004fc400078e020d */
/*0b50*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0b60*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0b70*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea2000c1e1900 */
/*0b90*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ IMAD R25, R20, R14, R23 ; /* 0x0000000e14197224 */
/* 0x004fc400078e0217 */
/*0bb0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc600078e0212 */
/*0bc0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0bd0*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea8000c1e1900 */
/*0be0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x0010a2000c1e1900 */
/*0bf0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05270 */
/*0c00*/ IADD3 R16, P1, R4, 0x10, RZ ; /* 0x0000001004107810 */
/* 0x000fc40007f3e0ff */
/*0c10*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe0ff */
/*0c20*/ IADD3.X R17, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff117210 */
/* 0x000fe40000ffe4ff */
/*0c30*/ MOV R4, R16 ; /* 0x0000001000047202 */
/* 0x001fc60000000f00 */
/*0c40*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0011 */
/*0c50*/ IMAD R13, R14, R13, R25 ; /* 0x0000000d0e0d7224 */
/* 0x004fe400078e0219 */
/*0c60*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0214 */
/*0c70*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e4000c101904 */
/*0c80*/ @P0 BRA 0xad0 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0c90*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0ca0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cb0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0cc0*/ IMAD R4, R12, c[0x0][0x178], RZ ; /* 0x00005e000c047a24 */
/* 0x000fe200078e02ff */
/*0cd0*/ IADD3 R7, P2, R7, R12, RZ ; /* 0x0000000c07077210 */
/* 0x000fc80007f5e0ff */
/*0ce0*/ IADD3 R5, P0, R4, R6, RZ ; /* 0x0000000604057210 */
/* 0x000fe40007f1e0ff */
/*0cf0*/ LEA R13, P3, R7, c[0x0][0x160], 0x2 ; /* 0x00005800070d7a11 */
/* 0x026fe400078610ff */
/*0d00*/ LEA R6, P1, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005067a11 */
/* 0x000fe400078210ff */
/*0d10*/ LEA.HI.X.SX32 R12, R12, R8, 0x1, P2 ; /* 0x000000080c0c7211 */
/* 0x000fe400010f0eff */
/*0d20*/ LEA.HI.X.SX32 R4, R4, R9, 0x1, P0 ; /* 0x0000000904047211 */
/* 0x000fe400000f0eff */
/*0d30*/ LEA.HI.X R12, R7, c[0x0][0x164], R12, 0x2, P3 ; /* 0x00005900070c7a11 */
/* 0x000fc400018f140c */
/*0d40*/ LEA.HI.X R5, R5, c[0x0][0x16c], R4, 0x2, P1 ; /* 0x00005b0005057a11 */
/* 0x001fc800008f1404 */
/*0d50*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0d60*/ MOV R8, R13 ; /* 0x0000000d00087202 */
/* 0x000fe40000000f00 */
/*0d70*/ MOV R9, R12 ; /* 0x0000000c00097202 */
/* 0x000fe20000000f00 */
/*0d80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000ea8000c1e1900 */
/*0d90*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000ea2000c1e1900 */
/*0da0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0dc0*/ IADD3 R13, P1, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fc80007f3e0ff */
/*0dd0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*0de0*/ IMAD R11, R4, R5, R11 ; /* 0x00000005040b7224 */
/* 0x005fe400078e020b */
/*0df0*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc600078e0206 */
/*0e00*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101904 */
/*0e10*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*0e20*/ @P0 BRA 0xd50 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <sys/time.h>
inline double nowSec()
{
struct timeval t;
struct timezone tzp;
gettimeofday(&t, &tzp);
return t.tv_sec + t.tv_usec*1e-6;
}
__host__ void host_mmul (int *A, int *B, int *C, int N)
{
for(int i=0; i<N; i++)
{
for (int j=0; j<N; j++)
{
for(int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
}
}
__global__ void global_mmul (int *A, int *B, int *C, int N)
{
int i=blockIdx.y;
int j=blockIdx.x;
for (int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
#ifdef PRINT
void printMtx (int *m, int N)
{
for (int i=0; i<N*N; i++)
{
if (i>0 && i%N == 0)
fprintf(stderr, "\n");
fprintf(stderr, "%d\t",*m);
m++;
}
}
#endif
int main(int argc, char **argv)
{
if (argc != 2)
{
puts("Usage: Matrix_mult [N]\n");
return -1;
}
int N=atoi(argv[1]);
int NN=N*N;
int i;
int *A, *B, *C_host, *C_device;
int *ptrA, *ptrB;
cudaMallocManaged(&A, NN*sizeof(int));
cudaMallocManaged(&B, NN*sizeof(int));
cudaMallocManaged(&C_device, NN*sizeof(int));
cudaMallocManaged(&C_host, NN*sizeof(int));
cudaDeviceSynchronize(); //attende che la memoria sia allocata
for (i=0, ptrA=A, ptrB=B ; i<N; i++)
{
for (int j=0; j<N; j++)
{
*ptrA=i*N+j;
*ptrB=0;
if (i==j)
*ptrB=1;
ptrA++;
ptrB++;
}
}
#ifdef PRINT
fprintf(stderr,"A=\n");
printMtx(A, N);
fprintf(stderr,"\n\nB=\n");
printMtx(B, N);
fprintf(stderr,"\n\n");
#endif
double t_begin_cpu = nowSec();
host_mmul(A, B, C_host, N);
double t_end_cpu = nowSec();
dim3 blockPerGrid(N,N);
dim3 threadPerBlock(1,1);
double t_begin_gpu = nowSec();
global_mmul <<< blockPerGrid, threadPerBlock >>> (A,B,C_device,N);
cudaDeviceSynchronize();
double t_end_gpu = nowSec();
#ifdef PRINT
fprintf(stderr,"C_host=\n");
printMtx(C_host, N);
fprintf(stderr,"\n\nC_device=\n");
printMtx(C_device, N);
fprintf(stderr,"\n");
#endif
printf("Elapsed time CPU: %f sec\n", t_end_cpu - t_begin_cpu);
printf("Elapsed time GPU: %f sec\n", t_end_gpu - t_begin_gpu);
cudaFree(A);
cudaFree(B);
cudaFree(C_device);
cudaFree(C_host);
return 0;
} | .file "tmpxft_00121921_00000000-6_Matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._Z6nowSecv,"axG",@progbits,_Z6nowSecv,comdat
.weak _Z6nowSecv
.type _Z6nowSecv, @function
_Z6nowSecv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6nowSecv, .-_Z6nowSecv
.text
.globl _Z9host_mmulPiS_S_i
.type _Z9host_mmulPiS_S_i, @function
_Z9host_mmulPiS_S_i:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L15
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r8
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, %r13d
movslq %ecx, %rbx
leaq 0(,%rbx,4), %rdi
movq %r8, %r11
addq %rdi, %r8
movl $0, %r14d
.L9:
movq %r12, %r10
movq %rbp, %rsi
movl $0, %r9d
.L12:
movq %r10, %rcx
movq %r11, %rax
.L10:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, (%rsi)
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L10
addq $1, %r9
addq $4, %r10
addq $4, %rsi
cmpq %rbx, %r9
jne .L12
addl $1, %r14d
addq %rdi, %r11
addq %rdi, %r8
addq %rdi, %rbp
cmpl %r14d, %r13d
jne .L9
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2058:
.size _Z9host_mmulPiS_S_i, .-_Z9host_mmulPiS_S_i
.globl _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i
.type _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i, @function
_Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11global_mmulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i, .-_Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i
.globl _Z11global_mmulPiS_S_i
.type _Z11global_mmulPiS_S_i, @function
_Z11global_mmulPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11global_mmulPiS_S_i, .-_Z11global_mmulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Usage: Matrix_mult [N]\n"
.LC2:
.string "Elapsed time CPU: %f sec\n"
.LC3:
.string "Elapsed time GPU: %f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L36
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
movl %eax, %r12d
imull %eax, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 32(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
call cudaDeviceSynchronize@PLT
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
testl %ebx, %ebx
jle .L29
movl %ebx, %r11d
leal -1(%rbx), %r9d
leaq 4(,%r9,4), %r10
movl $0, %r8d
movl $0, %ecx
.L30:
movl $0, %eax
.L31:
leal (%r8,%rax), %edx
movl %edx, (%rsi,%rax,4)
cmpl %eax, %ecx
sete %dl
movzbl %dl, %edx
movl %edx, (%rdi,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %r9, %rdx
jne .L31
addq %r10, %rsi
addq %r10, %rdi
addl $1, %ecx
addl %r11d, %r8d
cmpl %ebp, %ecx
jne .L30
.L29:
call _Z6nowSecv
movsd %xmm0, (%rsp)
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z9host_mmulPiS_S_i
call _Z6nowSecv
movsd %xmm0, 8(%rsp)
movl %ebx, 64(%rsp)
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
call _Z6nowSecv
movsd %xmm0, 16(%rsp)
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L32:
call cudaDeviceSynchronize@PLT
call _Z6nowSecv
movsd %xmm0, 24(%rsp)
movsd 8(%rsp), %xmm1
subsd (%rsp), %xmm1
movapd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
subsd 16(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L26:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
leaq .LC1(%rip), %rdi
call puts@PLT
movl $-1, %eax
jmp .L26
.L37:
movl %ebp, %ecx
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i
jmp .L32
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11global_mmulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11global_mmulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <sys/time.h>
inline double nowSec()
{
struct timeval t;
struct timezone tzp;
gettimeofday(&t, &tzp);
return t.tv_sec + t.tv_usec*1e-6;
}
__host__ void host_mmul (int *A, int *B, int *C, int N)
{
for(int i=0; i<N; i++)
{
for (int j=0; j<N; j++)
{
for(int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
}
}
__global__ void global_mmul (int *A, int *B, int *C, int N)
{
int i=blockIdx.y;
int j=blockIdx.x;
for (int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
#ifdef PRINT
void printMtx (int *m, int N)
{
for (int i=0; i<N*N; i++)
{
if (i>0 && i%N == 0)
fprintf(stderr, "\n");
fprintf(stderr, "%d\t",*m);
m++;
}
}
#endif
int main(int argc, char **argv)
{
if (argc != 2)
{
puts("Usage: Matrix_mult [N]\n");
return -1;
}
int N=atoi(argv[1]);
int NN=N*N;
int i;
int *A, *B, *C_host, *C_device;
int *ptrA, *ptrB;
cudaMallocManaged(&A, NN*sizeof(int));
cudaMallocManaged(&B, NN*sizeof(int));
cudaMallocManaged(&C_device, NN*sizeof(int));
cudaMallocManaged(&C_host, NN*sizeof(int));
cudaDeviceSynchronize(); //attende che la memoria sia allocata
for (i=0, ptrA=A, ptrB=B ; i<N; i++)
{
for (int j=0; j<N; j++)
{
*ptrA=i*N+j;
*ptrB=0;
if (i==j)
*ptrB=1;
ptrA++;
ptrB++;
}
}
#ifdef PRINT
fprintf(stderr,"A=\n");
printMtx(A, N);
fprintf(stderr,"\n\nB=\n");
printMtx(B, N);
fprintf(stderr,"\n\n");
#endif
double t_begin_cpu = nowSec();
host_mmul(A, B, C_host, N);
double t_end_cpu = nowSec();
dim3 blockPerGrid(N,N);
dim3 threadPerBlock(1,1);
double t_begin_gpu = nowSec();
global_mmul <<< blockPerGrid, threadPerBlock >>> (A,B,C_device,N);
cudaDeviceSynchronize();
double t_end_gpu = nowSec();
#ifdef PRINT
fprintf(stderr,"C_host=\n");
printMtx(C_host, N);
fprintf(stderr,"\n\nC_device=\n");
printMtx(C_device, N);
fprintf(stderr,"\n");
#endif
printf("Elapsed time CPU: %f sec\n", t_end_cpu - t_begin_cpu);
printf("Elapsed time GPU: %f sec\n", t_end_gpu - t_begin_gpu);
cudaFree(A);
cudaFree(B);
cudaFree(C_device);
cudaFree(C_host);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
inline double nowSec()
{
struct timeval t;
struct timezone tzp;
gettimeofday(&t, &tzp);
return t.tv_sec + t.tv_usec*1e-6;
}
__host__ void host_mmul (int *A, int *B, int *C, int N)
{
for(int i=0; i<N; i++)
{
for (int j=0; j<N; j++)
{
for(int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
}
}
__global__ void global_mmul (int *A, int *B, int *C, int N)
{
int i=blockIdx.y;
int j=blockIdx.x;
for (int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
#ifdef PRINT
void printMtx (int *m, int N)
{
for (int i=0; i<N*N; i++)
{
if (i>0 && i%N == 0)
fprintf(stderr, "\n");
fprintf(stderr, "%d\t",*m);
m++;
}
}
#endif
int main(int argc, char **argv)
{
if (argc != 2)
{
puts("Usage: Matrix_mult [N]\n");
return -1;
}
int N=atoi(argv[1]);
int NN=N*N;
int i;
int *A, *B, *C_host, *C_device;
int *ptrA, *ptrB;
hipMallocManaged(&A, NN*sizeof(int));
hipMallocManaged(&B, NN*sizeof(int));
hipMallocManaged(&C_device, NN*sizeof(int));
hipMallocManaged(&C_host, NN*sizeof(int));
hipDeviceSynchronize(); //attende che la memoria sia allocata
for (i=0, ptrA=A, ptrB=B ; i<N; i++)
{
for (int j=0; j<N; j++)
{
*ptrA=i*N+j;
*ptrB=0;
if (i==j)
*ptrB=1;
ptrA++;
ptrB++;
}
}
#ifdef PRINT
fprintf(stderr,"A=\n");
printMtx(A, N);
fprintf(stderr,"\n\nB=\n");
printMtx(B, N);
fprintf(stderr,"\n\n");
#endif
double t_begin_cpu = nowSec();
host_mmul(A, B, C_host, N);
double t_end_cpu = nowSec();
dim3 blockPerGrid(N,N);
dim3 threadPerBlock(1,1);
double t_begin_gpu = nowSec();
global_mmul <<< blockPerGrid, threadPerBlock >>> (A,B,C_device,N);
hipDeviceSynchronize();
double t_end_gpu = nowSec();
#ifdef PRINT
fprintf(stderr,"C_host=\n");
printMtx(C_host, N);
fprintf(stderr,"\n\nC_device=\n");
printMtx(C_device, N);
fprintf(stderr,"\n");
#endif
printf("Elapsed time CPU: %f sec\n", t_end_cpu - t_begin_cpu);
printf("Elapsed time GPU: %f sec\n", t_end_gpu - t_begin_gpu);
hipFree(A);
hipFree(B);
hipFree(C_device);
hipFree(C_host);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
inline double nowSec()
{
struct timeval t;
struct timezone tzp;
gettimeofday(&t, &tzp);
return t.tv_sec + t.tv_usec*1e-6;
}
__host__ void host_mmul (int *A, int *B, int *C, int N)
{
for(int i=0; i<N; i++)
{
for (int j=0; j<N; j++)
{
for(int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
}
}
__global__ void global_mmul (int *A, int *B, int *C, int N)
{
int i=blockIdx.y;
int j=blockIdx.x;
for (int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
#ifdef PRINT
void printMtx (int *m, int N)
{
for (int i=0; i<N*N; i++)
{
if (i>0 && i%N == 0)
fprintf(stderr, "\n");
fprintf(stderr, "%d\t",*m);
m++;
}
}
#endif
int main(int argc, char **argv)
{
if (argc != 2)
{
puts("Usage: Matrix_mult [N]\n");
return -1;
}
int N=atoi(argv[1]);
int NN=N*N;
int i;
int *A, *B, *C_host, *C_device;
int *ptrA, *ptrB;
hipMallocManaged(&A, NN*sizeof(int));
hipMallocManaged(&B, NN*sizeof(int));
hipMallocManaged(&C_device, NN*sizeof(int));
hipMallocManaged(&C_host, NN*sizeof(int));
hipDeviceSynchronize(); //attende che la memoria sia allocata
for (i=0, ptrA=A, ptrB=B ; i<N; i++)
{
for (int j=0; j<N; j++)
{
*ptrA=i*N+j;
*ptrB=0;
if (i==j)
*ptrB=1;
ptrA++;
ptrB++;
}
}
#ifdef PRINT
fprintf(stderr,"A=\n");
printMtx(A, N);
fprintf(stderr,"\n\nB=\n");
printMtx(B, N);
fprintf(stderr,"\n\n");
#endif
double t_begin_cpu = nowSec();
host_mmul(A, B, C_host, N);
double t_end_cpu = nowSec();
dim3 blockPerGrid(N,N);
dim3 threadPerBlock(1,1);
double t_begin_gpu = nowSec();
global_mmul <<< blockPerGrid, threadPerBlock >>> (A,B,C_device,N);
hipDeviceSynchronize();
double t_end_gpu = nowSec();
#ifdef PRINT
fprintf(stderr,"C_host=\n");
printMtx(C_host, N);
fprintf(stderr,"\n\nC_device=\n");
printMtx(C_device, N);
fprintf(stderr,"\n");
#endif
printf("Elapsed time CPU: %f sec\n", t_end_cpu - t_begin_cpu);
printf("Elapsed time GPU: %f sec\n", t_end_gpu - t_begin_gpu);
hipFree(A);
hipFree(B);
hipFree(C_device);
hipFree(C_host);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11global_mmulPiS_S_i
.globl _Z11global_mmulPiS_S_i
.p2align 8
.type _Z11global_mmulPiS_S_i,@function
_Z11global_mmulPiS_S_i:
s_load_b32 s6, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mul_i32 s0, s15, s6
v_mov_b32_e32 v1, 0
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[0:1], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s8, s4
s_addc_u32 s1, s9, s5
s_ashr_i32 s15, s14, 31
s_mov_b32 s9, s6
s_lshl_b64 s[12:13], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s7, s10, s12
s_addc_u32 s8, s11, s13
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_add_u32 s2, s2, s12
s_addc_u32 s3, s3, s13
s_mov_b32 s5, 0
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
s_mov_b32 s4, s5
.p2align 6
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[4:5], 2
s_add_u32 s10, s7, s10
s_addc_u32 s11, s8, s11
s_clause 0x1
global_load_b32 v2, v1, s[0:1]
global_load_b32 v3, v1, s[10:11]
s_add_i32 s9, s9, -1
s_add_i32 s4, s4, s6
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s9, 0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
global_store_b32 v1, v0, s[2:3]
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11global_mmulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11global_mmulPiS_S_i, .Lfunc_end0-_Z11global_mmulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11global_mmulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z11global_mmulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
inline double nowSec()
{
struct timeval t;
struct timezone tzp;
gettimeofday(&t, &tzp);
return t.tv_sec + t.tv_usec*1e-6;
}
__host__ void host_mmul (int *A, int *B, int *C, int N)
{
for(int i=0; i<N; i++)
{
for (int j=0; j<N; j++)
{
for(int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
}
}
__global__ void global_mmul (int *A, int *B, int *C, int N)
{
int i=blockIdx.y;
int j=blockIdx.x;
for (int k=0; k<N; k++)
{
*(C+ i*N+j)+=*(A+i*N + k) * *(B+k*N+j);
}
}
#ifdef PRINT
void printMtx (int *m, int N)
{
for (int i=0; i<N*N; i++)
{
if (i>0 && i%N == 0)
fprintf(stderr, "\n");
fprintf(stderr, "%d\t",*m);
m++;
}
}
#endif
int main(int argc, char **argv)
{
if (argc != 2)
{
puts("Usage: Matrix_mult [N]\n");
return -1;
}
int N=atoi(argv[1]);
int NN=N*N;
int i;
int *A, *B, *C_host, *C_device;
int *ptrA, *ptrB;
hipMallocManaged(&A, NN*sizeof(int));
hipMallocManaged(&B, NN*sizeof(int));
hipMallocManaged(&C_device, NN*sizeof(int));
hipMallocManaged(&C_host, NN*sizeof(int));
hipDeviceSynchronize(); //attende che la memoria sia allocata
for (i=0, ptrA=A, ptrB=B ; i<N; i++)
{
for (int j=0; j<N; j++)
{
*ptrA=i*N+j;
*ptrB=0;
if (i==j)
*ptrB=1;
ptrA++;
ptrB++;
}
}
#ifdef PRINT
fprintf(stderr,"A=\n");
printMtx(A, N);
fprintf(stderr,"\n\nB=\n");
printMtx(B, N);
fprintf(stderr,"\n\n");
#endif
double t_begin_cpu = nowSec();
host_mmul(A, B, C_host, N);
double t_end_cpu = nowSec();
dim3 blockPerGrid(N,N);
dim3 threadPerBlock(1,1);
double t_begin_gpu = nowSec();
global_mmul <<< blockPerGrid, threadPerBlock >>> (A,B,C_device,N);
hipDeviceSynchronize();
double t_end_gpu = nowSec();
#ifdef PRINT
fprintf(stderr,"C_host=\n");
printMtx(C_host, N);
fprintf(stderr,"\n\nC_device=\n");
printMtx(C_device, N);
fprintf(stderr,"\n");
#endif
printf("Elapsed time CPU: %f sec\n", t_end_cpu - t_begin_cpu);
printf("Elapsed time GPU: %f sec\n", t_end_gpu - t_begin_gpu);
hipFree(A);
hipFree(B);
hipFree(C_device);
hipFree(C_host);
return 0;
} | .text
.file "Matrix_mult.hip"
.globl _Z9host_mmulPiS_S_i # -- Begin function _Z9host_mmulPiS_S_i
.p2align 4, 0x90
.type _Z9host_mmulPiS_S_i,@function
_Z9host_mmulPiS_S_i: # @_Z9host_mmulPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader23.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_2: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movq %r8, %r9
imulq %rax, %r9
leaq (%rdx,%r9,4), %r9
movq %rsi, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
movl (%r9,%r11,4), %ebx
movq %r10, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r14), %ebp
imull (%rdi,%r15,4), %ebp
addl %ebp, %ebx
movl %ebx, (%r9,%r11,4)
incq %r15
addq %rcx, %r14
cmpq %r15, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
incq %r11
addq $4, %r10
cmpq %rax, %r11
jne .LBB0_3
# %bb.6: # %._crit_edge26
# in Loop: Header=BB0_2 Depth=1
incq %r8
addq %rcx, %rdi
cmpq %rax, %r8
jne .LBB0_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_8: # %._crit_edge28
retq
.Lfunc_end0:
.size _Z9host_mmulPiS_S_i, .Lfunc_end0-_Z9host_mmulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__global_mmulPiS_S_i # -- Begin function _Z26__device_stub__global_mmulPiS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__global_mmulPiS_S_i,@function
_Z26__device_stub__global_mmulPiS_S_i: # @_Z26__device_stub__global_mmulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11global_mmulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z26__device_stub__global_mmulPiS_S_i, .Lfunc_end1-_Z26__device_stub__global_mmulPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %ebx, %r14d
imull %r14d, %r14d
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 88(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 96(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
callq hipDeviceSynchronize
testl %ebx, %ebx
jle .LBB2_7
# %bb.3: # %.preheader.lr.ph
movq (%rsp), %rax
movq 8(%rsp), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_4 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%r8), %r9d
movl %r9d, (%rcx,%r8,4)
xorl %r9d, %r9d
cmpl %r8d, %esi
sete %r9b
movl %r9d, (%rax,%r8,4)
incq %r8
addq $-4, %rdi
cmpl %r8d, %ebx
jne .LBB2_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB2_4 Depth=1
incq %rsi
subq %rdi, %rcx
subq %rdi, %rax
addq %rbx, %rdx
cmpl %ebx, %esi
jne .LBB2_4
.LBB2_7: # %._crit_edge54
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq 32(%rsp), %xmm0
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
testl %ebx, %ebx
jle .LBB2_14
# %bb.8: # %.preheader23.lr.ph.i
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 96(%rsp), %rdx
movl %ebx, %esi
leaq (,%rsi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_9: # %.preheader23.i
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
# Child Loop BB2_11 Depth 3
movq %r8, %r9
imulq %rsi, %r9
leaq (%rdx,%r9,4), %r9
movq %rcx, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_10: # %.preheader.i
# Parent Loop BB2_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_11 Depth 3
movl (%r9,%r11,4), %ebp
movq %r10, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_11: # Parent Loop BB2_9 Depth=1
# Parent Loop BB2_10 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r14), %r12d
imull (%rax,%r15), %r12d
addl %r12d, %ebp
movl %ebp, (%r9,%r11,4)
addq $4, %r15
addq %rdi, %r14
cmpq %r15, %rdi
jne .LBB2_11
# %bb.12: # %._crit_edge.i
# in Loop: Header=BB2_10 Depth=2
incq %r11
addq $4, %r10
cmpq %rsi, %r11
jne .LBB2_10
# %bb.13: # %._crit_edge26.i
# in Loop: Header=BB2_9 Depth=1
incq %r8
addq %rdi, %rax
cmpq %rsi, %r8
jne .LBB2_9
.LBB2_14: # %_Z9host_mmulPiS_S_i.exit
addsd %xmm0, %xmm1
movsd %xmm1, 104(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 112(%rsp) # 8-byte Spill
movl %ebx, %eax
movq %rbx, %r15
shlq $32, %r15
orq %rax, %r15
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movabsq $4294967297, %rdx # imm = 0x100000001
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %ebx, 84(%rsp)
leaq 168(%rsp), %rax
movq %rax, 32(%rsp)
leaq 160(%rsp), %rax
movq %rax, 40(%rsp)
leaq 152(%rsp), %rax
movq %rax, 48(%rsp)
leaq 84(%rsp), %rax
movq %rax, 56(%rsp)
leaq 16(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z11global_mmulPiS_S_i, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16:
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 72(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 72(%rsp) # 8-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 104(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
jmp .LBB2_17
.LBB2_1:
movl $.L.str, %edi
callq puts
movl $-1, %r14d
.LBB2_17:
movl %r14d, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11global_mmulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11global_mmulPiS_S_i,@object # @_Z11global_mmulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z11global_mmulPiS_S_i
.p2align 3, 0x0
_Z11global_mmulPiS_S_i:
.quad _Z26__device_stub__global_mmulPiS_S_i
.size _Z11global_mmulPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: Matrix_mult [N]\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Elapsed time CPU: %f sec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Elapsed time GPU: %f sec\n"
.size .L.str.2, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11global_mmulPiS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__global_mmulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11global_mmulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11global_mmulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0050*/ IADD3 R5, R0.reuse, -0x1, RZ ; /* 0xffffffff00057810 */
/* 0x040fe20007ffe0ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0080*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0090*/ LOP3.LUT R10, R0, 0x3, RZ, 0xc0, !PT ; /* 0x00000003000a7812 */
/* 0x000fe200078ec0ff */
/*00a0*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x001fe200078e02ff */
/*00b0*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x002fc80000011406 */
/*00c0*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fe40000011407 */
/*00d0*/ IADD3 R3, P0, R7, R6, RZ ; /* 0x0000000607037210 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R4, R8, R9, RZ, P0, !PT ; /* 0x0000000908047210 */
/* 0x000fe400007fe4ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*0100*/ LEA R2, P1, R3, c[0x0][0x170], 0x2 ; /* 0x00005c0003027a11 */
/* 0x000fc800078210ff */
/*0110*/ LEA.HI.X R3, R3, c[0x0][0x174], R4, 0x2, P1 ; /* 0x00005d0003037a11 */
/* 0x000fce00008f1404 */
/*0120*/ @!P0 BRA 0xc90 ; /* 0x00000b6000008947 */
/* 0x000fea0003800000 */
/*0130*/ LEA R4, P0, R7.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580007047a11 */
/* 0x040fe200078010ff */
/*0140*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000162000c1e1900 */
/*0150*/ IADD3 R11, -R10, c[0x0][0x178], RZ ; /* 0x00005e000a0b7a10 */
/* 0x000fe40007ffe1ff */
/*0160*/ LEA.HI.X R5, R7, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590007057a11 */
/* 0x000fe400000f1408 */
/*0170*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f04270 */
/*0180*/ LEA R14, P1, R6, c[0x0][0x168], 0x2 ; /* 0x00005a00060e7a11 */
/* 0x000fe400078210ff */
/*0190*/ IADD3 R4, P2, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fc40007f5e0ff */
/*01a0*/ LEA.HI.X R15, R6, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b00060f7a11 */
/* 0x000fe400008f1409 */
/*01b0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe400017fe4ff */
/*01c0*/ MOV R12, RZ ; /* 0x000000ff000c7202 */
/* 0x000fc60000000f00 */
/*01d0*/ @!P0 BRA 0xad0 ; /* 0x000008f000008947 */
/* 0x001fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x7a0 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x004ea8000c1e1900 */
/*0230*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD R13, R16, R17, R13 ; /* 0x00000011100d7224 */
/* 0x024fe400078e020d */
/*0250*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0260*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0270*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R19, [R4.64+-0x4] ; /* 0xfffffc0404137981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD R21, R18, R19, R13 ; /* 0x0000001312157224 */
/* 0x004fc400078e020d */
/*02a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*02b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02c0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0300*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x001ee2000c1e1900 */
/*0330*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0340*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x008fca00078e0217 */
/*0350*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0360*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000e64000c1e1900 */
/*0380*/ IMAD R21, R20, R18, R13 ; /* 0x0000001214157224 */
/* 0x002fc400078e020d */
/*0390*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*03a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03b0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*03f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R13, [R4.64+0x10] ; /* 0x00001004040d7981 */
/* 0x001ee2000c1e1900 */
/*0420*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0430*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x008fca00078e0217 */
/*0440*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0450*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0460*/ LDG.E R18, [R4.64+0x14] ; /* 0x0000140404127981 */
/* 0x000e64000c1e1900 */
/*0470*/ IMAD R21, R20, R18, R13 ; /* 0x0000001214157224 */
/* 0x002fc400078e020d */
/*0480*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0490*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04a0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*04d0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*04e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*04f0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x001ee2000c1e1900 */
/*0510*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0520*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x008fca00078e0217 */
/*0530*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0540*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0550*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000e64000c1e1900 */
/*0560*/ IMAD R21, R20, R18, R13 ; /* 0x0000001214157224 */
/* 0x002fc400078e020d */
/*0570*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0580*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0590*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R14, [R4.64+0x24] ; /* 0x00002404040e7981 */
/* 0x000ea4000c1e1900 */
/*05b0*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*05c0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*05d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R13, [R4.64+0x28] ; /* 0x00002804040d7981 */
/* 0x001ea2000c1e1900 */
/*0600*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0610*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x004fca00078e0217 */
/*0620*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0630*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R18, [R4.64+0x2c] ; /* 0x00002c0404127981 */
/* 0x000ea4000c1e1900 */
/*0650*/ IMAD R25, R20, R18, R13 ; /* 0x0000001214197224 */
/* 0x004fc400078e020d */
/*0660*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0670*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0680*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e68000c1e1900 */
/*0690*/ LDG.E R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x000e62000c1e1900 */
/*06a0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ IMAD R23, R20, R14, R25 ; /* 0x0000000e14177224 */
/* 0x002fc400078e0219 */
/*06c0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc600078e0212 */
/*06d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*06e0*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ee8000c1e1900 */
/*06f0*/ LDG.E R13, [R4.64+0x34] ; /* 0x00003404040d7981 */
/* 0x0010e2000c1e1900 */
/*0700*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*0710*/ IADD3 R16, P2, R4, 0x40, RZ ; /* 0x0000004004107810 */
/* 0x000fc40007f5e0ff */
/*0720*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fe40007ffe0ff */
/*0730*/ IADD3.X R17, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff117210 */
/* 0x000fe400017fe4ff */
/*0740*/ MOV R4, R16 ; /* 0x0000001000047202 */
/* 0x001fe40000000f00 */
/*0750*/ MOV R5, R17 ; /* 0x0000001100057202 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD R13, R14, R13, R23 ; /* 0x0000000d0e0d7224 */
/* 0x008fe400078e0217 */
/*0770*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0214 */
/*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e2000c101904 */
/*0790*/ @P1 BRA 0x220 ; /* 0xfffffa8000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xab0 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*07d0*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ee4000c1e1900 */
/*07e0*/ IMAD R13, R16, R17, R13 ; /* 0x00000011100d7224 */
/* 0x02cfe400078e020d */
/*07f0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0800*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0810*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0820*/ LDG.E R19, [R4.64+-0x4] ; /* 0xfffffc0404137981 */
/* 0x000ea4000c1e1900 */
/*0830*/ IMAD R21, R18, R19, R13 ; /* 0x0000001312157224 */
/* 0x004fc400078e020d */
/*0840*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0850*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0860*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea4000c1e1900 */
/*0880*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*0890*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*08a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08b0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*08c0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x001ee2000c1e1900 */
/*08d0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*08e0*/ IMAD R13, R20, R13, R23 ; /* 0x0000000d140d7224 */
/* 0x008fca00078e0217 */
/*08f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0900*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0910*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000e64000c1e1900 */
/*0920*/ IMAD R21, R20, R18, R13 ; /* 0x0000001214157224 */
/* 0x002fc400078e020d */
/*0930*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0940*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0950*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x000ea4000c1e1900 */
/*0970*/ IMAD R23, R20, R14, R21 ; /* 0x0000000e14177224 */
/* 0x004fc400078e0215 */
/*0980*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0990*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09a0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R13, [R4.64+0x10] ; /* 0x00001004040d7981 */
/* 0x001ea2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*09d0*/ IMAD R25, R20, R13, R23 ; /* 0x0000000d14197224 */
/* 0x004fca00078e0217 */
/*09e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*09f0*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea8000c1e1900 */
/*0a00*/ LDG.E R13, [R4.64+0x14] ; /* 0x00001404040d7981 */
/* 0x0000a2000c1e1900 */
/*0a10*/ IADD3 R18, P1, R4, 0x20, RZ ; /* 0x0000002004127810 */
/* 0x000fe20007f3e0ff */
/*0a20*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0210 */
/*0a30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a40*/ IADD3 R12, R12, 0x8, RZ ; /* 0x000000080c0c7810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.X R19, RZ, RZ, R5, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0605 */
/*0a60*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ MOV R4, R18 ; /* 0x0000001200047202 */
/* 0x001fe40000000f00 */
/*0a80*/ MOV R5, R19 ; /* 0x0000001300057202 */
/* 0x000fe20000000f00 */
/*0a90*/ IMAD R13, R20, R13, R25 ; /* 0x0000000d140d7224 */
/* 0x004fca00078e0219 */
/*0aa0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e4000c101904 */
/*0ab0*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0ac0*/ @!P0 BRA 0xc90 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0ae0*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ee4000c1e1900 */
/*0af0*/ IMAD R13, R16, R17, R13 ; /* 0x00000011100d7224 */
/* 0x02efe400078e020d */
/*0b00*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0b10*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0b20*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0b30*/ LDG.E R19, [R4.64+-0x4] ; /* 0xfffffc0404137981 */
/* 0x000ea4000c1e1900 */
/*0b40*/ IMAD R23, R18, R19, R13 ; /* 0x0000001312177224 */
/* 0x004fc400078e020d */
/*0b50*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0b60*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0b70*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea2000c1e1900 */
/*0b90*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ IMAD R25, R20, R14, R23 ; /* 0x0000000e14197224 */
/* 0x004fc400078e0217 */
/*0bb0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc600078e0212 */
/*0bc0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0bd0*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea8000c1e1900 */
/*0be0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x0010a2000c1e1900 */
/*0bf0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05270 */
/*0c00*/ IADD3 R16, P1, R4, 0x10, RZ ; /* 0x0000001004107810 */
/* 0x000fc40007f3e0ff */
/*0c10*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe0ff */
/*0c20*/ IADD3.X R17, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff117210 */
/* 0x000fe40000ffe4ff */
/*0c30*/ MOV R4, R16 ; /* 0x0000001000047202 */
/* 0x001fc60000000f00 */
/*0c40*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0011 */
/*0c50*/ IMAD R13, R14, R13, R25 ; /* 0x0000000d0e0d7224 */
/* 0x004fe400078e0219 */
/*0c60*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0214 */
/*0c70*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e4000c101904 */
/*0c80*/ @P0 BRA 0xad0 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0c90*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0ca0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cb0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0cc0*/ IMAD R4, R12, c[0x0][0x178], RZ ; /* 0x00005e000c047a24 */
/* 0x000fe200078e02ff */
/*0cd0*/ IADD3 R7, P2, R7, R12, RZ ; /* 0x0000000c07077210 */
/* 0x000fc80007f5e0ff */
/*0ce0*/ IADD3 R5, P0, R4, R6, RZ ; /* 0x0000000604057210 */
/* 0x000fe40007f1e0ff */
/*0cf0*/ LEA R13, P3, R7, c[0x0][0x160], 0x2 ; /* 0x00005800070d7a11 */
/* 0x026fe400078610ff */
/*0d00*/ LEA R6, P1, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005067a11 */
/* 0x000fe400078210ff */
/*0d10*/ LEA.HI.X.SX32 R12, R12, R8, 0x1, P2 ; /* 0x000000080c0c7211 */
/* 0x000fe400010f0eff */
/*0d20*/ LEA.HI.X.SX32 R4, R4, R9, 0x1, P0 ; /* 0x0000000904047211 */
/* 0x000fe400000f0eff */
/*0d30*/ LEA.HI.X R12, R7, c[0x0][0x164], R12, 0x2, P3 ; /* 0x00005900070c7a11 */
/* 0x000fc400018f140c */
/*0d40*/ LEA.HI.X R5, R5, c[0x0][0x16c], R4, 0x2, P1 ; /* 0x00005b0005057a11 */
/* 0x001fc800008f1404 */
/*0d50*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0d60*/ MOV R8, R13 ; /* 0x0000000d00087202 */
/* 0x000fe40000000f00 */
/*0d70*/ MOV R9, R12 ; /* 0x0000000c00097202 */
/* 0x000fe20000000f00 */
/*0d80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000ea8000c1e1900 */
/*0d90*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000ea2000c1e1900 */
/*0da0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0dc0*/ IADD3 R13, P1, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fc80007f3e0ff */
/*0dd0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*0de0*/ IMAD R11, R4, R5, R11 ; /* 0x00000005040b7224 */
/* 0x005fe400078e020b */
/*0df0*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc600078e0206 */
/*0e00*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101904 */
/*0e10*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*0e20*/ @P0 BRA 0xd50 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11global_mmulPiS_S_i
.globl _Z11global_mmulPiS_S_i
.p2align 8
.type _Z11global_mmulPiS_S_i,@function
_Z11global_mmulPiS_S_i:
s_load_b32 s6, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mul_i32 s0, s15, s6
v_mov_b32_e32 v1, 0
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[0:1], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s8, s4
s_addc_u32 s1, s9, s5
s_ashr_i32 s15, s14, 31
s_mov_b32 s9, s6
s_lshl_b64 s[12:13], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s7, s10, s12
s_addc_u32 s8, s11, s13
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_add_u32 s2, s2, s12
s_addc_u32 s3, s3, s13
s_mov_b32 s5, 0
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
s_mov_b32 s4, s5
.p2align 6
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[4:5], 2
s_add_u32 s10, s7, s10
s_addc_u32 s11, s8, s11
s_clause 0x1
global_load_b32 v2, v1, s[0:1]
global_load_b32 v3, v1, s[10:11]
s_add_i32 s9, s9, -1
s_add_i32 s4, s4, s6
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s9, 0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
global_store_b32 v1, v0, s[2:3]
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11global_mmulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11global_mmulPiS_S_i, .Lfunc_end0-_Z11global_mmulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11global_mmulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z11global_mmulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00121921_00000000-6_Matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._Z6nowSecv,"axG",@progbits,_Z6nowSecv,comdat
.weak _Z6nowSecv
.type _Z6nowSecv, @function
_Z6nowSecv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6nowSecv, .-_Z6nowSecv
.text
.globl _Z9host_mmulPiS_S_i
.type _Z9host_mmulPiS_S_i, @function
_Z9host_mmulPiS_S_i:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L15
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r8
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, %r13d
movslq %ecx, %rbx
leaq 0(,%rbx,4), %rdi
movq %r8, %r11
addq %rdi, %r8
movl $0, %r14d
.L9:
movq %r12, %r10
movq %rbp, %rsi
movl $0, %r9d
.L12:
movq %r10, %rcx
movq %r11, %rax
.L10:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, (%rsi)
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L10
addq $1, %r9
addq $4, %r10
addq $4, %rsi
cmpq %rbx, %r9
jne .L12
addl $1, %r14d
addq %rdi, %r11
addq %rdi, %r8
addq %rdi, %rbp
cmpl %r14d, %r13d
jne .L9
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2058:
.size _Z9host_mmulPiS_S_i, .-_Z9host_mmulPiS_S_i
.globl _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i
.type _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i, @function
_Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11global_mmulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i, .-_Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i
.globl _Z11global_mmulPiS_S_i
.type _Z11global_mmulPiS_S_i, @function
_Z11global_mmulPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11global_mmulPiS_S_i, .-_Z11global_mmulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Usage: Matrix_mult [N]\n"
.LC2:
.string "Elapsed time CPU: %f sec\n"
.LC3:
.string "Elapsed time GPU: %f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L36
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
movl %eax, %r12d
imull %eax, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 32(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
call cudaDeviceSynchronize@PLT
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
testl %ebx, %ebx
jle .L29
movl %ebx, %r11d
leal -1(%rbx), %r9d
leaq 4(,%r9,4), %r10
movl $0, %r8d
movl $0, %ecx
.L30:
movl $0, %eax
.L31:
leal (%r8,%rax), %edx
movl %edx, (%rsi,%rax,4)
cmpl %eax, %ecx
sete %dl
movzbl %dl, %edx
movl %edx, (%rdi,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %r9, %rdx
jne .L31
addq %r10, %rsi
addq %r10, %rdi
addl $1, %ecx
addl %r11d, %r8d
cmpl %ebp, %ecx
jne .L30
.L29:
call _Z6nowSecv
movsd %xmm0, (%rsp)
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z9host_mmulPiS_S_i
call _Z6nowSecv
movsd %xmm0, 8(%rsp)
movl %ebx, 64(%rsp)
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
call _Z6nowSecv
movsd %xmm0, 16(%rsp)
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L32:
call cudaDeviceSynchronize@PLT
call _Z6nowSecv
movsd %xmm0, 24(%rsp)
movsd 8(%rsp), %xmm1
subsd (%rsp), %xmm1
movapd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
subsd 16(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L26:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
leaq .LC1(%rip), %rdi
call puts@PLT
movl $-1, %eax
jmp .L26
.L37:
movl %ebp, %ecx
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z36__device_stub__Z11global_mmulPiS_S_iPiS_S_i
jmp .L32
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11global_mmulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11global_mmulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix_mult.hip"
.globl _Z9host_mmulPiS_S_i # -- Begin function _Z9host_mmulPiS_S_i
.p2align 4, 0x90
.type _Z9host_mmulPiS_S_i,@function
_Z9host_mmulPiS_S_i: # @_Z9host_mmulPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader23.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_2: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movq %r8, %r9
imulq %rax, %r9
leaq (%rdx,%r9,4), %r9
movq %rsi, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
movl (%r9,%r11,4), %ebx
movq %r10, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r14), %ebp
imull (%rdi,%r15,4), %ebp
addl %ebp, %ebx
movl %ebx, (%r9,%r11,4)
incq %r15
addq %rcx, %r14
cmpq %r15, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
incq %r11
addq $4, %r10
cmpq %rax, %r11
jne .LBB0_3
# %bb.6: # %._crit_edge26
# in Loop: Header=BB0_2 Depth=1
incq %r8
addq %rcx, %rdi
cmpq %rax, %r8
jne .LBB0_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_8: # %._crit_edge28
retq
.Lfunc_end0:
.size _Z9host_mmulPiS_S_i, .Lfunc_end0-_Z9host_mmulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__global_mmulPiS_S_i # -- Begin function _Z26__device_stub__global_mmulPiS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__global_mmulPiS_S_i,@function
_Z26__device_stub__global_mmulPiS_S_i: # @_Z26__device_stub__global_mmulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11global_mmulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z26__device_stub__global_mmulPiS_S_i, .Lfunc_end1-_Z26__device_stub__global_mmulPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %ebx, %r14d
imull %r14d, %r14d
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 88(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 96(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
callq hipDeviceSynchronize
testl %ebx, %ebx
jle .LBB2_7
# %bb.3: # %.preheader.lr.ph
movq (%rsp), %rax
movq 8(%rsp), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_4 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%r8), %r9d
movl %r9d, (%rcx,%r8,4)
xorl %r9d, %r9d
cmpl %r8d, %esi
sete %r9b
movl %r9d, (%rax,%r8,4)
incq %r8
addq $-4, %rdi
cmpl %r8d, %ebx
jne .LBB2_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB2_4 Depth=1
incq %rsi
subq %rdi, %rcx
subq %rdi, %rax
addq %rbx, %rdx
cmpl %ebx, %esi
jne .LBB2_4
.LBB2_7: # %._crit_edge54
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq 32(%rsp), %xmm0
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
testl %ebx, %ebx
jle .LBB2_14
# %bb.8: # %.preheader23.lr.ph.i
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 96(%rsp), %rdx
movl %ebx, %esi
leaq (,%rsi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_9: # %.preheader23.i
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
# Child Loop BB2_11 Depth 3
movq %r8, %r9
imulq %rsi, %r9
leaq (%rdx,%r9,4), %r9
movq %rcx, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_10: # %.preheader.i
# Parent Loop BB2_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_11 Depth 3
movl (%r9,%r11,4), %ebp
movq %r10, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_11: # Parent Loop BB2_9 Depth=1
# Parent Loop BB2_10 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r14), %r12d
imull (%rax,%r15), %r12d
addl %r12d, %ebp
movl %ebp, (%r9,%r11,4)
addq $4, %r15
addq %rdi, %r14
cmpq %r15, %rdi
jne .LBB2_11
# %bb.12: # %._crit_edge.i
# in Loop: Header=BB2_10 Depth=2
incq %r11
addq $4, %r10
cmpq %rsi, %r11
jne .LBB2_10
# %bb.13: # %._crit_edge26.i
# in Loop: Header=BB2_9 Depth=1
incq %r8
addq %rdi, %rax
cmpq %rsi, %r8
jne .LBB2_9
.LBB2_14: # %_Z9host_mmulPiS_S_i.exit
addsd %xmm0, %xmm1
movsd %xmm1, 104(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 112(%rsp) # 8-byte Spill
movl %ebx, %eax
movq %rbx, %r15
shlq $32, %r15
orq %rax, %r15
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movabsq $4294967297, %rdx # imm = 0x100000001
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %ebx, 84(%rsp)
leaq 168(%rsp), %rax
movq %rax, 32(%rsp)
leaq 160(%rsp), %rax
movq %rax, 40(%rsp)
leaq 152(%rsp), %rax
movq %rax, 48(%rsp)
leaq 84(%rsp), %rax
movq %rax, 56(%rsp)
leaq 16(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z11global_mmulPiS_S_i, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16:
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 72(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 72(%rsp) # 8-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 104(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
jmp .LBB2_17
.LBB2_1:
movl $.L.str, %edi
callq puts
movl $-1, %r14d
.LBB2_17:
movl %r14d, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11global_mmulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11global_mmulPiS_S_i,@object # @_Z11global_mmulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z11global_mmulPiS_S_i
.p2align 3, 0x0
_Z11global_mmulPiS_S_i:
.quad _Z26__device_stub__global_mmulPiS_S_i
.size _Z11global_mmulPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: Matrix_mult [N]\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Elapsed time CPU: %f sec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Elapsed time GPU: %f sec\n"
.size .L.str.2, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11global_mmulPiS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__global_mmulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11global_mmulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <string>
#include <cuda.h>
void printDesc(const std::string &label, const cudaChannelFormatDesc &desc) {
std::cout << label << " -----------" << std::endl;
std::cout << "x: " << desc.x << std::endl;
std::cout << "y: " << desc.y << std::endl;
std::cout << "z: " << desc.z << std::endl;
std::cout << "w: " << desc.w << std::endl;
}
int main(int argc, char const *argv[])
{
cudaChannelFormatDesc desc;
desc = cudaCreateChannelDesc<float4>();
printDesc("float4", desc);
desc = cudaCreateChannelDesc<float>();
printDesc("float", desc);
desc = cudaCreateChannelDesc<int>();
printDesc("int", desc);
desc = cudaCreateChannelDesc<char>();
printDesc("char", desc);
desc = cudaCreateChannelDesc<char4>();
printDesc("char4", desc);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <string>
#include <cuda.h>
void printDesc(const std::string &label, const cudaChannelFormatDesc &desc) {
std::cout << label << " -----------" << std::endl;
std::cout << "x: " << desc.x << std::endl;
std::cout << "y: " << desc.y << std::endl;
std::cout << "z: " << desc.z << std::endl;
std::cout << "w: " << desc.w << std::endl;
}
int main(int argc, char const *argv[])
{
cudaChannelFormatDesc desc;
desc = cudaCreateChannelDesc<float4>();
printDesc("float4", desc);
desc = cudaCreateChannelDesc<float>();
printDesc("float", desc);
desc = cudaCreateChannelDesc<int>();
printDesc("int", desc);
desc = cudaCreateChannelDesc<char>();
printDesc("char", desc);
desc = cudaCreateChannelDesc<char4>();
printDesc("char4", desc);
return 0;
} | .file "tmpxft_000e6986_00000000-6_cudaCreateChannelDesc_info.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " -----------"
.LC1:
.string "x: "
.LC2:
.string "y: "
.LC3:
.string "z: "
.LC4:
.string "w: "
.text
.globl _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.type _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc, @function
_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbp
movq 8(%rdi), %rdx
movq (%rdi), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
movl $12, %edx
leaq .LC0(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L20
cmpb $0, 56(%r12)
je .L5
movzbl 67(%r12), %esi
.L6:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $3, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%rbp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L21
cmpb $0, 56(%r12)
je .L8
movzbl 67(%r12), %esi
.L9:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $3, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rbp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L22
cmpb $0, 56(%r12)
je .L11
movzbl 67(%r12), %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $3, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 8(%rbp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L23
cmpb $0, 56(%r12)
je .L14
movzbl 67(%r12), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $3, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 12(%rbp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L24
cmpb $0, 56(%rbp)
je .L17
movzbl 67(%rbp), %esi
.L18:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.L21:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.L22:
call _ZSt16__throw_bad_castv@PLT
.L11:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L23:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L24:
call _ZSt16__throw_bad_castv@PLT
.L17:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.cfi_endproc
.LFE3669:
.size _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc, .-_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4001:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L36
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L37
cmpq $1, %rax
jne .L32
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L33:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L39
leaq .LC5(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L39:
call __stack_chk_fail@PLT
.L37:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L31:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L33
.L32:
testq %rax, %rax
je .L33
jmp .L31
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4001:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC6:
.string "float4"
.LC7:
.string "float"
.LC8:
.string "int"
.LC9:
.string "char"
.LC10:
.string "char4"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3670
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbp
movl $2, %r9d
movl $32, %r8d
movl $32, %ecx
movl $32, %edx
movl $32, %esi
movq %rbp, %rdi
.LEHB0:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm0
movaps %xmm0, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
leaq 64(%rsp), %rbx
movq %rbp, %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB1:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE1:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $2, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $32, %esi
movq %rbp, %rdi
.LEHB2:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm1
movaps %xmm1, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
movq %rbp, %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB3:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE3:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $32, %esi
movq %rbp, %rdi
.LEHB4:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm2
movaps %xmm2, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
movq %rbp, %rdx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB5:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE5:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $8, %esi
movq %rbp, %rdi
.LEHB6:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm3
movaps %xmm3, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
movq %rbp, %rdx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB7:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE7:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %r9d
movl $8, %r8d
movl $8, %ecx
movl $8, %edx
movl $8, %esi
movq %rbp, %rdi
.LEHB8:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm4
movaps %xmm4, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
movq %rbp, %rdx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE8:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB9:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE9:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
movq %rbx, %rdi
.LEHB10:
call _Unwind_Resume@PLT
.L53:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L44:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L54:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L46
call __stack_chk_fail@PLT
.L46:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L55:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L48:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L56:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L50:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE10:
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3670:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3670-.LLSDACSB3670
.LLSDACSB3670:
.uleb128 .LEHB0-.LFB3670
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3670
.uleb128 .LEHE1-.LEHB1
.uleb128 .L52-.LFB3670
.uleb128 0
.uleb128 .LEHB2-.LFB3670
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3670
.uleb128 .LEHE3-.LEHB3
.uleb128 .L53-.LFB3670
.uleb128 0
.uleb128 .LEHB4-.LFB3670
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3670
.uleb128 .LEHE5-.LEHB5
.uleb128 .L54-.LFB3670
.uleb128 0
.uleb128 .LEHB6-.LFB3670
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3670
.uleb128 .LEHE7-.LEHB7
.uleb128 .L55-.LFB3670
.uleb128 0
.uleb128 .LEHB8-.LFB3670
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB3670
.uleb128 .LEHE9-.LEHB9
.uleb128 .L56-.LFB3670
.uleb128 0
.uleb128 .LEHB10-.LFB3670
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.LLSDACSE3670:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <string>
#include <cuda.h>
void printDesc(const std::string &label, const cudaChannelFormatDesc &desc) {
std::cout << label << " -----------" << std::endl;
std::cout << "x: " << desc.x << std::endl;
std::cout << "y: " << desc.y << std::endl;
std::cout << "z: " << desc.z << std::endl;
std::cout << "w: " << desc.w << std::endl;
}
int main(int argc, char const *argv[])
{
cudaChannelFormatDesc desc;
desc = cudaCreateChannelDesc<float4>();
printDesc("float4", desc);
desc = cudaCreateChannelDesc<float>();
printDesc("float", desc);
desc = cudaCreateChannelDesc<int>();
printDesc("int", desc);
desc = cudaCreateChannelDesc<char>();
printDesc("char", desc);
desc = cudaCreateChannelDesc<char4>();
printDesc("char4", desc);
return 0;
} | #include <iostream>
#include <string>
#include <hip/hip_runtime.h>
void printDesc(const std::string &label, const hipChannelFormatDesc &desc) {
std::cout << label << " -----------" << std::endl;
std::cout << "x: " << desc.x << std::endl;
std::cout << "y: " << desc.y << std::endl;
std::cout << "z: " << desc.z << std::endl;
std::cout << "w: " << desc.w << std::endl;
}
int main(int argc, char const *argv[])
{
hipChannelFormatDesc desc;
desc = hipCreateChannelDesc<float4>();
printDesc("float4", desc);
desc = hipCreateChannelDesc<float>();
printDesc("float", desc);
desc = hipCreateChannelDesc<int>();
printDesc("int", desc);
desc = hipCreateChannelDesc<char>();
printDesc("char", desc);
desc = hipCreateChannelDesc<char4>();
printDesc("char4", desc);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <string>
#include <hip/hip_runtime.h>
void printDesc(const std::string &label, const hipChannelFormatDesc &desc) {
std::cout << label << " -----------" << std::endl;
std::cout << "x: " << desc.x << std::endl;
std::cout << "y: " << desc.y << std::endl;
std::cout << "z: " << desc.z << std::endl;
std::cout << "w: " << desc.w << std::endl;
}
int main(int argc, char const *argv[])
{
hipChannelFormatDesc desc;
desc = hipCreateChannelDesc<float4>();
printDesc("float4", desc);
desc = hipCreateChannelDesc<float>();
printDesc("float", desc);
desc = hipCreateChannelDesc<int>();
printDesc("int", desc);
desc = hipCreateChannelDesc<char>();
printDesc("char", desc);
desc = hipCreateChannelDesc<char4>();
printDesc("char4", desc);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <string>
#include <hip/hip_runtime.h>
void printDesc(const std::string &label, const hipChannelFormatDesc &desc) {
std::cout << label << " -----------" << std::endl;
std::cout << "x: " << desc.x << std::endl;
std::cout << "y: " << desc.y << std::endl;
std::cout << "z: " << desc.z << std::endl;
std::cout << "w: " << desc.w << std::endl;
}
int main(int argc, char const *argv[])
{
hipChannelFormatDesc desc;
desc = hipCreateChannelDesc<float4>();
printDesc("float4", desc);
desc = hipCreateChannelDesc<float>();
printDesc("float", desc);
desc = hipCreateChannelDesc<int>();
printDesc("int", desc);
desc = hipCreateChannelDesc<char>();
printDesc("char", desc);
desc = hipCreateChannelDesc<char4>();
printDesc("char4", desc);
return 0;
} | .text
.file "cudaCreateChannelDesc_info.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc # -- Begin function _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.p2align 4, 0x90
.type _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc,@function
_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc: # @_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq (%rdi), %rsi
movq 8(%rdi), %rdx
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r14
movl $.L.str, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB0_3
# %bb.2:
movzbl 67(%r15), %eax
jmp .LBB0_4
.LBB0_3:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_21
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i6
cmpb $0, 56(%r14)
je .LBB0_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB0_8
.LBB0_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit9
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_21
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%r14)
je .LBB0_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB0_12
.LBB0_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_21
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r14)
je .LBB0_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB0_16
.LBB0_15:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 12(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%rbx)
je .LBB0_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB0_20
.LBB0_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB0_21:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc, .Lfunc_end0-_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rbx
movq %rbx, %rdi
movl $32, %esi
movl $32, %edx
movl $32, %ecx
movl $32, %r8d
movl $2, %r9d
callq hipCreateChannelDesc
leaq 16(%rsp), %r14
movq %r14, (%rsp)
movl $1634692198, 16(%rsp) # imm = 0x616F6C66
movw $13428, 20(%rsp) # imm = 0x3474
movq $6, 8(%rsp)
movb $0, 22(%rsp)
.Ltmp0:
movq %rsp, %rdi
movq %rbx, %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp1:
# %bb.1:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_3
# %bb.2: # %.critedge.i.i
callq _ZdlPv
.LBB1_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %rsp, %rdi
movl $32, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
movl $2, %r9d
callq hipCreateChannelDesc
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 32(%rsp)
movq %r14, (%rsp)
movl $1634692198, 16(%rsp) # imm = 0x616F6C66
movw $116, 20(%rsp)
movq $5, 8(%rsp)
.Ltmp3:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp4:
# %bb.4:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_6
# %bb.5: # %.critedge.i.i26
callq _ZdlPv
.LBB1_6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit28
movq %rsp, %rdi
movl $32, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq hipCreateChannelDesc
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 32(%rsp)
movq %r14, (%rsp)
movl $7630441, 16(%rsp) # imm = 0x746E69
movq $3, 8(%rsp)
.Ltmp6:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp7:
# %bb.7:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_9
# %bb.8: # %.critedge.i.i36
callq _ZdlPv
.LBB1_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit38
movq %rsp, %rdi
movl $8, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq hipCreateChannelDesc
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 32(%rsp)
movq %r14, (%rsp)
movl $1918986339, 16(%rsp) # imm = 0x72616863
movq $4, 8(%rsp)
movb $0, 20(%rsp)
.Ltmp9:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp10:
# %bb.10:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_12
# %bb.11: # %.critedge.i.i46
callq _ZdlPv
.LBB1_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit48
movq %rsp, %rdi
movl $8, %esi
movl $8, %edx
movl $8, %ecx
movl $8, %r8d
xorl %r9d, %r9d
callq hipCreateChannelDesc
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 32(%rsp)
movq %r14, (%rsp)
movl $1918986339, 16(%rsp) # imm = 0x72616863
movw $52, 20(%rsp)
movq $5, 8(%rsp)
.Ltmp12:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp13:
# %bb.13:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_15
# %bb.14: # %.critedge.i.i56
callq _ZdlPv
.LBB1_15: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit58
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_20:
.cfi_def_cfa_offset 80
.Ltmp14:
jmp .LBB1_21
.LBB1_19:
.Ltmp11:
jmp .LBB1_21
.LBB1_18:
.Ltmp8:
jmp .LBB1_21
.LBB1_17:
.Ltmp5:
jmp .LBB1_21
.LBB1_16:
.Ltmp2:
.LBB1_21:
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_23
# %bb.22: # %.critedge.i.i71
callq _ZdlPv
.LBB1_23:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Lfunc_end1-.Ltmp13 # Call between .Ltmp13 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " -----------"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "x: "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "y: "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "z: "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "w: "
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "float4"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "float"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "int"
.size .L.str.7, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "char4"
.size .L.str.9, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e6986_00000000-6_cudaCreateChannelDesc_info.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " -----------"
.LC1:
.string "x: "
.LC2:
.string "y: "
.LC3:
.string "z: "
.LC4:
.string "w: "
.text
.globl _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.type _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc, @function
_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbp
movq 8(%rdi), %rdx
movq (%rdi), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
movl $12, %edx
leaq .LC0(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L20
cmpb $0, 56(%r12)
je .L5
movzbl 67(%r12), %esi
.L6:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $3, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%rbp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L21
cmpb $0, 56(%r12)
je .L8
movzbl 67(%r12), %esi
.L9:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $3, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rbp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L22
cmpb $0, 56(%r12)
je .L11
movzbl 67(%r12), %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $3, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 8(%rbp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L23
cmpb $0, 56(%r12)
je .L14
movzbl 67(%r12), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $3, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 12(%rbp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L24
cmpb $0, 56(%rbp)
je .L17
movzbl 67(%rbp), %esi
.L18:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.L21:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.L22:
call _ZSt16__throw_bad_castv@PLT
.L11:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L23:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L24:
call _ZSt16__throw_bad_castv@PLT
.L17:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.cfi_endproc
.LFE3669:
.size _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc, .-_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4001:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L36
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L37
cmpq $1, %rax
jne .L32
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L33:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L39
leaq .LC5(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L39:
call __stack_chk_fail@PLT
.L37:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L31:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L33
.L32:
testq %rax, %rax
je .L33
jmp .L31
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4001:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC6:
.string "float4"
.LC7:
.string "float"
.LC8:
.string "int"
.LC9:
.string "char"
.LC10:
.string "char4"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3670
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbp
movl $2, %r9d
movl $32, %r8d
movl $32, %ecx
movl $32, %edx
movl $32, %esi
movq %rbp, %rdi
.LEHB0:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm0
movaps %xmm0, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
leaq 64(%rsp), %rbx
movq %rbp, %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB1:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE1:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $2, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $32, %esi
movq %rbp, %rdi
.LEHB2:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm1
movaps %xmm1, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
movq %rbp, %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB3:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE3:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $32, %esi
movq %rbp, %rdi
.LEHB4:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm2
movaps %xmm2, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
movq %rbp, %rdx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB5:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE5:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $8, %esi
movq %rbp, %rdi
.LEHB6:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm3
movaps %xmm3, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
movq %rbp, %rdx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB7:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE7:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %r9d
movl $8, %r8d
movl $8, %ecx
movl $8, %edx
movl $8, %esi
movq %rbp, %rdi
.LEHB8:
call cudaCreateChannelDesc@PLT
movdqa 32(%rsp), %xmm4
movaps %xmm4, (%rsp)
movl 48(%rsp), %eax
movl %eax, 16(%rsp)
movq %rbp, %rdx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE8:
movq %rsp, %rsi
movq %rbx, %rdi
.LEHB9:
call _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK21cudaChannelFormatDesc
.LEHE9:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
movq %rbx, %rdi
.LEHB10:
call _Unwind_Resume@PLT
.L53:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L44:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L54:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L46
call __stack_chk_fail@PLT
.L46:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L55:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L48:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L56:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L50:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE10:
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3670:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3670-.LLSDACSB3670
.LLSDACSB3670:
.uleb128 .LEHB0-.LFB3670
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3670
.uleb128 .LEHE1-.LEHB1
.uleb128 .L52-.LFB3670
.uleb128 0
.uleb128 .LEHB2-.LFB3670
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3670
.uleb128 .LEHE3-.LEHB3
.uleb128 .L53-.LFB3670
.uleb128 0
.uleb128 .LEHB4-.LFB3670
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3670
.uleb128 .LEHE5-.LEHB5
.uleb128 .L54-.LFB3670
.uleb128 0
.uleb128 .LEHB6-.LFB3670
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3670
.uleb128 .LEHE7-.LEHB7
.uleb128 .L55-.LFB3670
.uleb128 0
.uleb128 .LEHB8-.LFB3670
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB3670
.uleb128 .LEHE9-.LEHB9
.uleb128 .L56-.LFB3670
.uleb128 0
.uleb128 .LEHB10-.LFB3670
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.LLSDACSE3670:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaCreateChannelDesc_info.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc # -- Begin function _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.p2align 4, 0x90
.type _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc,@function
_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc: # @_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq (%rdi), %rsi
movq 8(%rdi), %rdx
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r14
movl $.L.str, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB0_3
# %bb.2:
movzbl 67(%r15), %eax
jmp .LBB0_4
.LBB0_3:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_21
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i6
cmpb $0, 56(%r14)
je .LBB0_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB0_8
.LBB0_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit9
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_21
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%r14)
je .LBB0_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB0_12
.LBB0_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_21
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r14)
je .LBB0_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB0_16
.LBB0_15:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 12(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%rbx)
je .LBB0_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB0_20
.LBB0_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB0_21:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc, .Lfunc_end0-_Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rbx
movq %rbx, %rdi
movl $32, %esi
movl $32, %edx
movl $32, %ecx
movl $32, %r8d
movl $2, %r9d
callq hipCreateChannelDesc
leaq 16(%rsp), %r14
movq %r14, (%rsp)
movl $1634692198, 16(%rsp) # imm = 0x616F6C66
movw $13428, 20(%rsp) # imm = 0x3474
movq $6, 8(%rsp)
movb $0, 22(%rsp)
.Ltmp0:
movq %rsp, %rdi
movq %rbx, %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp1:
# %bb.1:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_3
# %bb.2: # %.critedge.i.i
callq _ZdlPv
.LBB1_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %rsp, %rdi
movl $32, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
movl $2, %r9d
callq hipCreateChannelDesc
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 32(%rsp)
movq %r14, (%rsp)
movl $1634692198, 16(%rsp) # imm = 0x616F6C66
movw $116, 20(%rsp)
movq $5, 8(%rsp)
.Ltmp3:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp4:
# %bb.4:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_6
# %bb.5: # %.critedge.i.i26
callq _ZdlPv
.LBB1_6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit28
movq %rsp, %rdi
movl $32, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq hipCreateChannelDesc
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 32(%rsp)
movq %r14, (%rsp)
movl $7630441, 16(%rsp) # imm = 0x746E69
movq $3, 8(%rsp)
.Ltmp6:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp7:
# %bb.7:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_9
# %bb.8: # %.critedge.i.i36
callq _ZdlPv
.LBB1_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit38
movq %rsp, %rdi
movl $8, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq hipCreateChannelDesc
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 32(%rsp)
movq %r14, (%rsp)
movl $1918986339, 16(%rsp) # imm = 0x72616863
movq $4, 8(%rsp)
movb $0, 20(%rsp)
.Ltmp9:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp10:
# %bb.10:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_12
# %bb.11: # %.critedge.i.i46
callq _ZdlPv
.LBB1_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit48
movq %rsp, %rdi
movl $8, %esi
movl $8, %edx
movl $8, %ecx
movl $8, %r8d
xorl %r9d, %r9d
callq hipCreateChannelDesc
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 32(%rsp)
movq %r14, (%rsp)
movl $1918986339, 16(%rsp) # imm = 0x72616863
movw $52, 20(%rsp)
movq $5, 8(%rsp)
.Ltmp12:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq _Z9printDescRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERK20hipChannelFormatDesc
.Ltmp13:
# %bb.13:
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_15
# %bb.14: # %.critedge.i.i56
callq _ZdlPv
.LBB1_15: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit58
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_20:
.cfi_def_cfa_offset 80
.Ltmp14:
jmp .LBB1_21
.LBB1_19:
.Ltmp11:
jmp .LBB1_21
.LBB1_18:
.Ltmp8:
jmp .LBB1_21
.LBB1_17:
.Ltmp5:
jmp .LBB1_21
.LBB1_16:
.Ltmp2:
.LBB1_21:
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_23
# %bb.22: # %.critedge.i.i71
callq _ZdlPv
.LBB1_23:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Lfunc_end1-.Ltmp13 # Call between .Ltmp13 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " -----------"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "x: "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "y: "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "z: "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "w: "
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "float4"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "float"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "int"
.size .L.str.7, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "char4"
.size .L.str.9, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
extern "C" {
void get_dev_mem(size_t& total, size_t& free)
{
cuMemGetInfo(&free, &total);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
extern "C" {
void get_dev_mem(size_t& total, size_t& free)
{
cuMemGetInfo(&free, &total);
}
} | .file "tmpxft_00081add_00000000-6_cuda_api.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl get_dev_mem
.type get_dev_mem, @function
get_dev_mem:
.LFB2027:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movq %rax, %rsi
call cuMemGetInfo_v2@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size get_dev_mem, .-get_dev_mem
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
extern "C" {
void get_dev_mem(size_t& total, size_t& free)
{
cuMemGetInfo(&free, &total);
}
} | #include <hip/hip_runtime.h>
extern "C" {
void get_dev_mem(size_t& total, size_t& free)
{
hipMemGetInfo(&free, &total);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" {
void get_dev_mem(size_t& total, size_t& free)
{
hipMemGetInfo(&free, &total);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" {
void get_dev_mem(size_t& total, size_t& free)
{
hipMemGetInfo(&free, &total);
}
} | .text
.file "cuda_api.hip"
.globl get_dev_mem # -- Begin function get_dev_mem
.p2align 4, 0x90
.type get_dev_mem,@function
get_dev_mem: # @get_dev_mem
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movq %rsi, %rdi
movq %rax, %rsi
jmp hipMemGetInfo # TAILCALL
.Lfunc_end0:
.size get_dev_mem, .Lfunc_end0-get_dev_mem
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00081add_00000000-6_cuda_api.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl get_dev_mem
.type get_dev_mem, @function
get_dev_mem:
.LFB2027:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movq %rax, %rsi
call cuMemGetInfo_v2@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size get_dev_mem, .-get_dev_mem
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_api.hip"
.globl get_dev_mem # -- Begin function get_dev_mem
.p2align 4, 0x90
.type get_dev_mem,@function
get_dev_mem: # @get_dev_mem
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movq %rsi, %rdi
movq %rax, %rsi
jmp hipMemGetInfo # TAILCALL
.Lfunc_end0:
.size get_dev_mem, .Lfunc_end0-get_dev_mem
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// main.cu
// CS 426 - Project 4
//
// Created by Muhammed Cavusoglu on 19.05.2019.
// Copyright © 2019 Muhammed Cavusoglu. All rights reserved.
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals);
// Parallel SpMV using CSR format
__global__ void spmv_csr(const int *row_ptr, const int *col_ind, const float *values, const int num_rows, const float *x, float *y) {
// Uses a grid-stride loop to perform dot product
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < num_rows; i += blockDim.x * gridDim.x) {
float dotProduct = 0;
const int row_start = row_ptr[i];
const int row_end = row_ptr[i + 1];
for (int j = row_start; j < row_end; j++) {
dotProduct += values[j] * x[col_ind[j]];
}
y[i] = dotProduct;
}
}
int main(int argc, const char * argv[]) {
if (argc != 5) {
fprintf(stdout, "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n");
exit(0);
}
int *row_ptr, *col_ind, num_rows, num_cols, num_vals, numSMs;;
float *values;
int num_thread = atoi(argv[1]);
int num_repeat = atoi(argv[2]);
int print_mode = atoi(argv[3]);
const char *filename = argv[4];
read_matrix(&row_ptr, &col_ind, &values, filename, &num_rows, &num_cols, &num_vals);
float *x = (float *) malloc(num_rows * sizeof(float));
float *y = (float *) malloc(num_rows * sizeof(float));
for (int i = 0; i < num_rows; i++) {
x[i] = 1.0;
y[i] = 0.0;
}
if (print_mode == 1) {
// Values Array
fprintf(stdout, "Values Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%.6f ", values[i]);
}
// Column Indices Array
fprintf(stdout, "\n\nColumn Indices Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%d ", col_ind[i]);
}
// Row Pointer Array
fprintf(stdout, "\n\nRow Pointer Array:\n");
for (int i = 0; i < (num_rows + 1); i++) {
fprintf(stdout, "%d ", row_ptr[i]);
}
fprintf(stdout, "\n\nInitial Vector:\n");
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.1f ", x[i]);
}
fprintf(stdout, "\n\nResulting Vector:\n");
}
// Allocate on device
int *d_row_ptr, *d_col_ind;
float *d_values, *d_x, *d_y;
cudaMalloc((void**)&d_row_ptr, (num_rows + 1) * sizeof(int));
cudaMalloc((void**)&d_col_ind, num_vals * sizeof(int));
cudaMalloc((void**)&d_values, num_vals * sizeof(float));
cudaMalloc((void**)&d_x, num_rows * sizeof(float));
cudaMalloc((void**)&d_y, num_rows * sizeof(float));
// Get number of SMs
cudaDeviceGetAttribute(&numSMs, cudaDevAttrMultiProcessorCount, 0);
// Copy from host to device
cudaMemcpy(d_row_ptr, row_ptr, (num_rows + 1) * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_col_ind, col_ind, num_vals * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_values, values, num_vals * sizeof(float), cudaMemcpyHostToDevice);
// Time the iterations
float elapsed_time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
for (int i = 0; i < num_repeat; i++) {
cudaMemcpy(d_x, x, num_rows * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, num_rows * sizeof(float), cudaMemcpyHostToDevice);
// Call kernel function
spmv_csr<<<32 * numSMs, num_thread>>>(d_row_ptr, d_col_ind, d_values, num_rows, d_x, d_y);
// Copy the result to x_{i} at the end of each iteration, and use it in iteration x_{i+1}
cudaMemcpy(y, d_y, num_rows * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < num_rows; i++) {
x[i] = y[i];
y[i] = 0.0;
}
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time, start, stop);
// Print resulting vector
if (print_mode == 1 || print_mode == 2) {
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.6f ", x[i]);
}
fprintf(stdout, "\n");
}
// Print elapsed time
// printf("\nParallel Running time: %.4f ms\n", elapsed_time);
// printf("Num SMs: %d\n", numSMs);
// Free
cudaFree(d_row_ptr);
cudaFree(d_col_ind);
cudaFree(d_values);
cudaFree(d_x);
cudaFree(d_y);
free(row_ptr);
free(col_ind);
free(values);
return 0;
}
// Reads a sparse matrix and represents it using CSR (Compressed Sparse Row) format
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals) {
FILE *file = fopen(filename, "r");
if (file == NULL) {
fprintf(stdout, "File cannot be opened!\n");
exit(0);
}
// Get number of rows, columns, and non-zero values
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int *row_ptr_t = (int *) malloc((*num_rows + 1) * sizeof(int));
int *col_ind_t = (int *) malloc(*num_vals * sizeof(int));
float *values_t = (float *) malloc(*num_vals * sizeof(float));
// Collect occurances of each row for determining the indices of row_ptr
int *row_occurances = (int *) malloc(*num_rows * sizeof(int));
for (int i = 0; i < *num_rows; i++) {
row_occurances[i] = 0;
}
int row, column;
float value;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
// Subtract 1 from row and column indices to match C format
row--;
column--;
row_occurances[row]++;
}
// Set row_ptr
int index = 0;
for (int i = 0; i < *num_rows; i++) {
row_ptr_t[i] = index;
index += row_occurances[i];
}
row_ptr_t[*num_rows] = *num_vals;
free(row_occurances);
// Set the file position to the beginning of the file
rewind(file);
// Read the file again, save column indices and values
for (int i = 0; i < *num_vals; i++) {
col_ind_t[i] = -1;
}
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int i = 0;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
row--;
column--;
// Find the correct index (i + row_ptr_t[row]) using both row information and an index i
while (col_ind_t[i + row_ptr_t[row]] != -1) {
i++;
}
col_ind_t[i + row_ptr_t[row]] = column;
values_t[i + row_ptr_t[row]] = value;
i = 0;
}
fclose(file);
*row_ptr = row_ptr_t;
*col_ind = col_ind_t;
*values = values_t;
} | code for sm_80
Function : _Z8spmv_csrPKiS0_PKfiS2_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R14, SR_CTAID.X ; /* 0x00000000000e7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R14, R14, c[0x0][0x0], R3 ; /* 0x000000000e0e7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ UMOV UR4, 0x8 ; /* 0x0000000800047882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0090*/ UIADD3 UR6, UP0, UR4, UR6, URZ ; /* 0x0000000604067290 */
/* 0x000fe4000ff1e03f */
/*00a0*/ UIADD3 UR4, UP1, UR4, UR8, URZ ; /* 0x0000000804047290 */
/* 0x000fe4000ff3e03f */
/*00b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc400087fe43f */
/*00c0*/ UIADD3.X UR5, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f057290 */
/* 0x000fc60008ffe43f */
/*00d0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*00e0*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fd400000001ff */
/*00f0*/ IMAD.WIDE R2, R14, R15, c[0x0][0x160] ; /* 0x000058000e027625 */
/* 0x000fca00078e020f */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000000802007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040802107981 */
/* 0x000ea2000c1e1900 */
/*0120*/ BSSY B0, 0xea0 ; /* 0x00000d7000007945 */
/* 0x000fe20003800000 */
/*0130*/ SHF.R.S32.HI R17, RZ, 0x1f, R14 ; /* 0x0000001fff117819 */
/* 0x000fe4000001140e */
/*0140*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0150*/ ISETP.GT.AND P0, PT, R16, R0, PT ; /* 0x000000001000720c */
/* 0x004fda0003f04270 */
/*0160*/ @!P0 BRA 0xe90 ; /* 0x00000d2000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R2, -R0, R16, RZ ; /* 0x0000001000027210 */
/* 0x000fe20007ffe1ff */
/*0180*/ BSSY B1, 0x380 ; /* 0x000001f000017945 */
/* 0x000fe20003800000 */
/*0190*/ LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff037212 */
/* 0x000fe400078e33ff */
/*01a0*/ LOP3.LUT P0, R10, R2, 0x3, RZ, 0xc0, !PT ; /* 0x00000003020a7812 */
/* 0x000fe4000780c0ff */
/*01b0*/ IADD3 R3, R16, R3, RZ ; /* 0x0000000310037210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fc40003f26070 */
/*01e0*/ MOV R19, R0 ; /* 0x0000000000137202 */
/* 0x000fca0000000f00 */
/*01f0*/ @!P0 BRA 0x370 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.WIDE R4, R0, R15, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e020f */
/*0210*/ LDG.E R6, [R4.64] ; /* 0x0000000804067981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IMAD.WIDE R2, R0, R15, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e020f */
/*0230*/ LDG.E R9, [R2.64] ; /* 0x0000000802097981 */
/* 0x000ee2000c1e1900 */
/*0240*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f05270 */
/*0250*/ IMAD.WIDE R6, R6, R15, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x004fcc00078e020f */
/*0260*/ LDG.E R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ee2000c1e1900 */
/*0270*/ IADD3 R19, R0, 0x1, RZ ; /* 0x0000000100137810 */
/* 0x000fe20007ffe0ff */
/*0280*/ FFMA R8, R6, R9, RZ ; /* 0x0000000906087223 */
/* 0x008fc800000000ff */
/*0290*/ @!P0 BRA 0x370 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.NE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe20003f05270 */
/*02b0*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040804067981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040802097981 */
/* 0x000ef0000c1e1900 */
/*02d0*/ @P0 LDG.E R10, [R4.64+0x8] ; /* 0x00000808040a0981 */
/* 0x000f28000c1e1900 */
/*02e0*/ @P0 LDG.E R12, [R2.64+0x8] ; /* 0x00000808020c0981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IMAD.WIDE R6, R6, R15, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x004fcc00078e020f */
/*0300*/ LDG.E R7, [R6.64] ; /* 0x0000000806077981 */
/* 0x000ee2000c1e1900 */
/*0310*/ @P0 IMAD.WIDE R10, R10, R15, c[0x0][0x180] ; /* 0x000060000a0a0625 */
/* 0x010fcc00078e020f */
/*0320*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000080a0b0981 */
/* 0x000f62000c1e1900 */
/*0330*/ IADD3 R19, R0.reuse, 0x2, RZ ; /* 0x0000000200137810 */
/* 0x040fe40007ffe0ff */
/*0340*/ @P0 IADD3 R19, R0, 0x3, RZ ; /* 0x0000000300130810 */
/* 0x000fe20007ffe0ff */
/*0350*/ FFMA R8, R7, R9, R8 ; /* 0x0000000907087223 */
/* 0x008fc80000000008 */
/*0360*/ @P0 FFMA R8, R11, R12, R8 ; /* 0x0000000c0b080223 */
/* 0x020fe40000000008 */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ @!P1 BRA 0xe90 ; /* 0x00000b0000009947 */
/* 0x000fea0003800000 */
/*0390*/ IADD3 R0, R16, -R19, RZ ; /* 0x8000001310007210 */
/* 0x000fe20007ffe0ff */
/*03a0*/ BSSY B1, 0x9f0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*03b0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe40008000f00 */
/*03c0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24270 */
/*03d0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe40008000f00 */
/*03e0*/ MOV R6, UR4 ; /* 0x0000000400067c02 */
/* 0x000fe40008000f00 */
/*03f0*/ MOV R7, UR5 ; /* 0x0000000500077c02 */
/* 0x000fe20008000f00 */
/*0400*/ IMAD.WIDE R4, R19, 0x4, R4 ; /* 0x0000000413047825 */
/* 0x000fe200078e0204 */
/*0410*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*0420*/ IMAD.WIDE R6, R19, 0x4, R6 ; /* 0x0000000413067825 */
/* 0x000fe400078e0206 */
/*0430*/ @!P1 BRA 0x9e0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0440*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0450*/ IADD3 R18, R16, -0xc, RZ ; /* 0xfffffff410127810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LDG.E R24, [R6.64+-0x8] ; /* 0xfffff80806187981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R10, [R6.64+-0x4] ; /* 0xfffffc08060a7981 */
/* 0x000ee8000c1e1900 */
/*0480*/ LDG.E R20, [R6.64] ; /* 0x0000000806147981 */
/* 0x000f28000c1e1900 */
/*0490*/ LDG.E R22, [R6.64+0x4] ; /* 0x0000040806167981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R26, [R6.64+0x8] ; /* 0x00000808061a7981 */
/* 0x000f68000c1e1900 */
/*04b0*/ LDG.E R3, [R4.64+-0x8] ; /* 0xfffff80804037981 */
/* 0x000f68000c1e1900 */
/*04c0*/ LDG.E R12, [R4.64+-0x4] ; /* 0xfffffc08040c7981 */
/* 0x000f68000c1e1900 */
/*04d0*/ LDG.E R13, [R6.64+0xc] ; /* 0x00000c08060d7981 */
/* 0x000f68000c1e1900 */
/*04e0*/ LDG.E R28, [R6.64+0x10] ; /* 0x00001008061c7981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R29, [R4.64] ; /* 0x00000008041d7981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R2, [R4.64+0x4] ; /* 0x0000040804027981 */
/* 0x000f62000c1e1900 */
/*0510*/ IMAD.WIDE R24, R24, R15, c[0x0][0x180] ; /* 0x0000600018187625 */
/* 0x004fc800078e020f */
/*0520*/ IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x088fe200078e020f */
/*0530*/ LDG.E R0, [R24.64] ; /* 0x0000000818007981 */
/* 0x0000a6000c1e1900 */
/*0540*/ IMAD.WIDE R20, R20, R15.reuse, c[0x0][0x180] ; /* 0x0000600014147625 */
/* 0x090fe200078e020f */
/*0550*/ LDG.E R9, [R10.64] ; /* 0x000000080a097981 */
/* 0x0002ea000c1e1900 */
/*0560*/ LDG.E R21, [R20.64] ; /* 0x0000000814157981 */
/* 0x0008e2000c1e1900 */
/*0570*/ IMAD.WIDE R22, R22, R15, c[0x0][0x180] ; /* 0x0000600016167625 */
/* 0x020fc600078e020f */
/*0580*/ LDG.E R24, [R6.64+0x18] ; /* 0x0000180806187981 */
/* 0x001f62000c1e1900 */
/*0590*/ IMAD.WIDE R26, R26, R15, c[0x0][0x180] ; /* 0x000060001a1a7625 */
/* 0x000fc600078e020f */
/*05a0*/ LDG.E R25, [R22.64] ; /* 0x0000000816197981 */
/* 0x000168000c1e1900 */
/*05b0*/ LDG.E R20, [R6.64+0x14] ; /* 0x0000140806147981 */
/* 0x010f28000c1e1900 */
/*05c0*/ LDG.E R10, [R26.64] ; /* 0x000000081a0a7981 */
/* 0x002328000c1e1900 */
/*05d0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000808040b7981 */
/* 0x000f68000c1e1900 */
/*05e0*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0804177981 */
/* 0x001f68000c1e1900 */
/*05f0*/ LDG.E R22, [R6.64+0x20] ; /* 0x0000200806167981 */
/* 0x000f68000c1e1900 */
/*0600*/ LDG.E R26, [R6.64+0x30] ; /* 0x00003008061a7981 */
/* 0x002f62000c1e1900 */
/*0610*/ FFMA R0, R0, R3, R8 ; /* 0x0000000300007223 */
/* 0x004fc60000000008 */
/*0620*/ LDG.E R3, [R4.64+0x14] ; /* 0x0000140804037981 */
/* 0x000ea2000c1e1900 */
/*0630*/ FFMA R0, R9, R12, R0 ; /* 0x0000000c09007223 */
/* 0x008fe40000000000 */
/*0640*/ IMAD.WIDE R12, R13, R15, c[0x0][0x180] ; /* 0x000060000d0c7625 */
/* 0x000fc800078e020f */
/*0650*/ IMAD.WIDE R8, R28, R15, c[0x0][0x180] ; /* 0x000060001c087625 */
/* 0x000fe400078e020f */
/*0660*/ LDG.E R28, [R4.64+0x18] ; /* 0x00001808041c7981 */
/* 0x000ee4000c1e1900 */
/*0670*/ FFMA R0, R21, R29, R0 ; /* 0x0000001d15007223 */
/* 0x000fe40000000000 */
/*0680*/ LDG.E R21, [R12.64] ; /* 0x000000080c157981 */
/* 0x0008a8000c1e1900 */
/*0690*/ LDG.E R29, [R6.64+0x1c] ; /* 0x00001c08061d7981 */
/* 0x000ee8000c1e1900 */
/*06a0*/ LDG.E R9, [R8.64] ; /* 0x0000000808097981 */
/* 0x0000e2000c1e1900 */
/*06b0*/ IMAD.WIDE R12, R20, R15, c[0x0][0x180] ; /* 0x00006000140c7625 */
/* 0x010fc600078e020f */
/*06c0*/ LDG.E R20, [R4.64+0x10] ; /* 0x0000100804147981 */
/* 0x000f22000c1e1900 */
/*06d0*/ FFMA R0, R25, R2, R0 ; /* 0x0000000219007223 */
/* 0x020fc60000000000 */
/*06e0*/ LDG.E R27, [R12.64] ; /* 0x000000080c1b7981 */
/* 0x000362000c1e1900 */
/*06f0*/ IMAD.WIDE R24, R24, R15, c[0x0][0x180] ; /* 0x0000600018187625 */
/* 0x000fc600078e020f */
/*0700*/ LDG.E R2, [R6.64+0x24] ; /* 0x0000240806027981 */
/* 0x000f68000c1e1900 */
/*0710*/ LDG.E R8, [R6.64+0x28] ; /* 0x0000280806087981 */
/* 0x001f62000c1e1900 */
/*0720*/ FFMA R12, R10, R11, R0 ; /* 0x0000000b0a0c7223 */
/* 0x002fc60000000000 */
/*0730*/ LDG.E R11, [R24.64] ; /* 0x00000008180b7981 */
/* 0x000168000c1e1900 */
/*0740*/ LDG.E R10, [R6.64+0x2c] ; /* 0x00002c08060a7981 */
/* 0x000f68000c1e1900 */
/*0750*/ LDG.E R0, [R6.64+0x34] ; /* 0x0000340806007981 */
/* 0x000f68000c1e1900 */
/*0760*/ LDG.E R24, [R4.64+0x20] ; /* 0x0000200804187981 */
/* 0x001168000c1e1900 */
/*0770*/ LDG.E R25, [R4.64+0x24] ; /* 0x0000240804197981 */
/* 0x000162000c1e1900 */
/*0780*/ FFMA R21, R21, R23, R12 ; /* 0x0000001715157223 */
/* 0x004fc6000000000c */
/*0790*/ LDG.E R23, [R4.64+0x1c] ; /* 0x00001c0804177981 */
/* 0x0000a2000c1e1900 */
/*07a0*/ IMAD.WIDE R12, R29, R15, c[0x0][0x180] ; /* 0x000060001d0c7625 */
/* 0x008fc600078e020f */
/*07b0*/ LDG.E R29, [R4.64+0x28] ; /* 0x00002808041d7981 */
/* 0x0000e2000c1e1900 */
/*07c0*/ FFMA R9, R9, R20, R21 ; /* 0x0000001409097223 */
/* 0x010fe40000000015 */
/*07d0*/ IMAD.WIDE R20, R22, R15, c[0x0][0x180] ; /* 0x0000600016147625 */
/* 0x000fe400078e020f */
/*07e0*/ LDG.E R22, [R12.64] ; /* 0x000000080c167981 */
/* 0x0002a4000c1e1900 */
/*07f0*/ FFMA R27, R27, R3, R9 ; /* 0x000000031b1b7223 */
/* 0x020fe40000000009 */
/*0800*/ IMAD.WIDE R2, R2, R15.reuse, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x080fe200078e020f */
/*0810*/ LDG.E R21, [R20.64] ; /* 0x0000000814157981 */
/* 0x000966000c1e1900 */
/*0820*/ IMAD.WIDE R8, R8, R15, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x000fc400078e020f */
/*0830*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x0000e4000c1e1900 */
/*0840*/ FFMA R28, R11, R28, R27 ; /* 0x0000001c0b1c7223 */
/* 0x000fe4000000001b */
/*0850*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x0000e2000c1e1900 */
/*0860*/ IMAD.WIDE R10, R10, R15, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x000fc600078e020f */
/*0870*/ LDG.E R20, [R4.64+0x2c] ; /* 0x00002c0804147981 */
/* 0x0108e2000c1e1900 */
/*0880*/ IMAD.WIDE R12, R26, R15, c[0x0][0x180] ; /* 0x000060001a0c7625 */
/* 0x002fc600078e020f */
/*0890*/ LDG.E R11, [R10.64] ; /* 0x000000080a0b7981 */
/* 0x000ee2000c1e1900 */
/*08a0*/ IMAD.WIDE R26, R0, R15, c[0x0][0x180] ; /* 0x00006000001a7625 */
/* 0x000fc600078e020f */
/*08b0*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000ee8000c1e1900 */
/*08c0*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300804007981 */
/* 0x0008e8000c1e1900 */
/*08d0*/ LDG.E R26, [R26.64] ; /* 0x000000081a1a7981 */
/* 0x000ee8000c1e1900 */
/*08e0*/ LDG.E R3, [R4.64+0x34] ; /* 0x0000340804037981 */
/* 0x0018e2000c1e1900 */
/*08f0*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fc80007ffe0ff */
/*0900*/ ISETP.GE.AND P1, PT, R19, R18, PT ; /* 0x000000121300720c */
/* 0x000fe40003f26270 */
/*0910*/ IADD3 R6, P3, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x000fe40007f7e0ff */
/*0920*/ IADD3 R9, P2, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe40007f5e0ff */
/*0930*/ IADD3.X R7, RZ, R7, RZ, P3, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40001ffe4ff */
/*0940*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x010fe400017fe4ff */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0960*/ FFMA R22, R22, R23, R28 ; /* 0x0000001716167223 */
/* 0x004fc8000000001c */
/*0970*/ FFMA R21, R21, R24, R22 ; /* 0x0000001815157223 */
/* 0x020fc80000000016 */
/*0980*/ FFMA R2, R2, R25, R21 ; /* 0x0000001902027223 */
/* 0x008fc80000000015 */
/*0990*/ FFMA R2, R8, R29, R2 ; /* 0x0000001d08027223 */
/* 0x000fc80000000002 */
/*09a0*/ FFMA R2, R11, R20, R2 ; /* 0x000000140b027223 */
/* 0x000fc80000000002 */
/*09b0*/ FFMA R0, R13, R0, R2 ; /* 0x000000000d007223 */
/* 0x000fc80000000002 */
/*09c0*/ FFMA R8, R26, R3, R0 ; /* 0x000000031a087223 */
/* 0x000fe20000000000 */
/*09d0*/ @!P1 BRA 0x460 ; /* 0xfffffa8000009947 */
/* 0x000fea000383ffff */
/*09e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09f0*/ IADD3 R0, R16, -R19, RZ ; /* 0x8000001310007210 */
/* 0x000fe20007ffe0ff */
/*0a00*/ BSSY B1, 0xd30 ; /* 0x0000032000017945 */
/* 0x000fe60003800000 */
/*0a10*/ ISETP.GT.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f24270 */
/*0a20*/ @!P1 BRA 0xd20 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0a30*/ LDG.E R22, [R6.64+-0x8] ; /* 0xfffff80806167981 */
/* 0x000ea8000c1e1900 */
/*0a40*/ LDG.E R28, [R6.64+-0x4] ; /* 0xfffffc08061c7981 */
/* 0x000ee8000c1e1900 */
/*0a50*/ LDG.E R2, [R6.64] ; /* 0x0000000806027981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R3, [R6.64+0x4] ; /* 0x0000040806037981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R10, [R6.64+0x8] ; /* 0x00000808060a7981 */
/* 0x000f68000c1e1900 */
/*0a80*/ LDG.E R12, [R6.64+0xc] ; /* 0x00000c08060c7981 */
/* 0x000f68000c1e1900 */
/*0a90*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100806147981 */
/* 0x000f68000c1e1900 */
/*0aa0*/ LDG.E R24, [R6.64+0x14] ; /* 0x0000140806187981 */
/* 0x000f68000c1e1900 */
/*0ab0*/ LDG.E R0, [R4.64+-0x8] ; /* 0xfffff80804007981 */
/* 0x000f68000c1e1900 */
/*0ac0*/ LDG.E R18, [R4.64+-0x4] ; /* 0xfffffc0804127981 */
/* 0x000f68000c1e1900 */
/*0ad0*/ LDG.E R27, [R4.64] ; /* 0x00000008041b7981 */
/* 0x000f62000c1e1900 */
/*0ae0*/ IMAD.WIDE R22, R22, R15, c[0x0][0x180] ; /* 0x0000600016167625 */
/* 0x004fc800078e020f */
/*0af0*/ IMAD.WIDE R28, R28, R15.reuse, c[0x0][0x180] ; /* 0x000060001c1c7625 */
/* 0x088fe200078e020f */
/*0b00*/ LDG.E R9, [R22.64] ; /* 0x0000000816097981 */
/* 0x0008a8000c1e1900 */
/*0b10*/ LDG.E R25, [R28.64] ; /* 0x000000081c197981 */
/* 0x0000e2000c1e1900 */
/*0b20*/ IMAD.WIDE R22, R2, R15, c[0x0][0x180] ; /* 0x0000600002167625 */
/* 0x010fc800078e020f */
/*0b30*/ IMAD.WIDE R2, R3, R15.reuse, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x0a0fe200078e020f */
/*0b40*/ LDG.E R26, [R22.64] ; /* 0x00000008161a7981 */
/* 0x000326000c1e1900 */
/*0b50*/ IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x080fe200078e020f */
/*0b60*/ LDG.E R29, [R4.64+0xc] ; /* 0x00000c08041d7981 */
/* 0x001f68000c1e1900 */
/*0b70*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000162000c1e1900 */
/*0b80*/ IMAD.WIDE R12, R12, R15, c[0x0][0x180] ; /* 0x000060000c0c7625 */
/* 0x000fc600078e020f */
/*0b90*/ LDG.E R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000362000c1e1900 */
/*0ba0*/ IMAD.WIDE R20, R20, R15, c[0x0][0x180] ; /* 0x0000600014147625 */
/* 0x000fc600078e020f */
/*0bb0*/ LDG.E R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000f68000c1e1900 */
/*0bc0*/ LDG.E R3, [R4.64+0x4] ; /* 0x0000040804037981 */
/* 0x001f68000c1e1900 */
/*0bd0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000808040b7981 */
/* 0x002f62000c1e1900 */
/*0be0*/ IMAD.WIDE R22, R24, R15, c[0x0][0x180] ; /* 0x0000600018167625 */
/* 0x000fc600078e020f */
/*0bf0*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000f68000c1e1900 */
/*0c00*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100804187981 */
/* 0x000f68000c1e1900 */
/*0c10*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000f68000c1e1900 */
/*0c20*/ LDG.E R28, [R4.64+0x14] ; /* 0x00001408041c7981 */
/* 0x000162000c1e1900 */
/*0c30*/ IADD3 R6, P2, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fc40007f5e0ff */
/*0c40*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0c50*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400017fe4ff */
/*0c60*/ IADD3 R19, R19, 0x8, RZ ; /* 0x0000000813137810 */
/* 0x000fe20007ffe0ff */
/*0c70*/ FFMA R0, R9, R0, R8 ; /* 0x0000000009007223 */
/* 0x004fc80000000008 */
/*0c80*/ FFMA R0, R25, R18, R0 ; /* 0x0000001219007223 */
/* 0x008fc80000000000 */
/*0c90*/ FFMA R0, R26, R27, R0 ; /* 0x0000001b1a007223 */
/* 0x010fc80000000000 */
/*0ca0*/ FFMA R0, R2, R3, R0 ; /* 0x0000000302007223 */
/* 0x020fc80000000000 */
/*0cb0*/ FFMA R0, R10, R11, R0 ; /* 0x0000000b0a007223 */
/* 0x000fc80000000000 */
/*0cc0*/ FFMA R29, R12, R29, R0 ; /* 0x0000001d0c1d7223 */
/* 0x000fe20000000000 */
/*0cd0*/ IADD3 R0, P1, R4, 0x20, RZ ; /* 0x0000002004007810 */
/* 0x000fc60007f3e0ff */
/*0ce0*/ FFMA R29, R20, R24, R29 ; /* 0x00000018141d7223 */
/* 0x000fe2000000001d */
/*0cf0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x001fe40000ffe4ff */
/*0d00*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*0d10*/ FFMA R8, R22, R28, R29 ; /* 0x0000001c16087223 */
/* 0x000fe4000000001d */
/*0d20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d30*/ ISETP.LT.OR P0, PT, R19, R16, P0 ; /* 0x000000101300720c */
/* 0x000fda0000701670 */
/*0d40*/ @!P0 BRA 0xe90 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0d50*/ LDG.E R2, [R6.64+-0x8] ; /* 0xfffff80806027981 */
/* 0x0000a8000c1e1900 */
/*0d60*/ LDG.E R10, [R6.64+-0x4] ; /* 0xfffffc08060a7981 */
/* 0x0000e8000c1e1900 */
/*0d70*/ LDG.E R12, [R6.64] ; /* 0x00000008060c7981 */
/* 0x000128000c1e1900 */
/*0d80*/ LDG.E R18, [R6.64+0x4] ; /* 0x0000040806127981 */
/* 0x000168000c1e1900 */
/*0d90*/ LDG.E R0, [R4.64+-0x8] ; /* 0xfffff80804007981 */
/* 0x000f68000c1e1900 */
/*0da0*/ LDG.E R9, [R4.64+-0x4] ; /* 0xfffffc0804097981 */
/* 0x000f68000c1e1900 */
/*0db0*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040804067981 */
/* 0x001f62000c1e1900 */
/*0dc0*/ IMAD.WIDE R2, R2, R15, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x004fc800078e020f */
/*0dd0*/ IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x088fe400078e020f */
/*0de0*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea4000c1e1900 */
/*0df0*/ IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x180] ; /* 0x000060000c0c7625 */
/* 0x090fe400078e020f */
/*0e00*/ LDG.E R11, [R10.64] ; /* 0x000000080a0b7981 */
/* 0x000ee4000c1e1900 */
/*0e10*/ IMAD.WIDE R18, R18, R15, c[0x0][0x180] ; /* 0x0000600012127625 */
/* 0x020fe400078e020f */
/*0e20*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000f28000c1e1900 */
/*0e30*/ LDG.E R15, [R4.64] ; /* 0x00000008040f7981 */
/* 0x000f28000c1e1900 */
/*0e40*/ LDG.E R19, [R18.64] ; /* 0x0000000812137981 */
/* 0x000f62000c1e1900 */
/*0e50*/ FFMA R0, R3, R0, R8 ; /* 0x0000000003007223 */
/* 0x004fc80000000008 */
/*0e60*/ FFMA R0, R11, R9, R0 ; /* 0x000000090b007223 */
/* 0x008fc80000000000 */
/*0e70*/ FFMA R0, R13, R15, R0 ; /* 0x0000000f0d007223 */
/* 0x010fc80000000000 */
/*0e80*/ FFMA R8, R19, R6, R0 ; /* 0x0000000613087223 */
/* 0x020fe40000000000 */
/*0e90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ea0*/ LEA R2, P0, R14.reuse, c[0x0][0x188], 0x2 ; /* 0x000062000e027a11 */
/* 0x040fe400078010ff */
/*0eb0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe40000000f00 */
/*0ec0*/ LEA.HI.X R3, R14, c[0x0][0x18c], R17, 0x2, P0 ; /* 0x000063000e037a11 */
/* 0x000fc600000f1411 */
/*0ed0*/ IMAD R14, R5, c[0x0][0xc], R14 ; /* 0x00000300050e7a24 */
/* 0x000fe400078e020e */
/*0ee0*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0001e6000c101908 */
/*0ef0*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fda0003f06270 */
/*0f00*/ @P0 CALL.REL.NOINC 0xf20 ; /* 0x0000001000000944 */
/* 0x001fe20003c00000 */
/*0f10*/ BRA 0xe0 ; /* 0xfffff1c000007947 */
/* 0x000fea000383ffff */
/*0f20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f30*/ BRA 0xf30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// main.cu
// CS 426 - Project 4
//
// Created by Muhammed Cavusoglu on 19.05.2019.
// Copyright © 2019 Muhammed Cavusoglu. All rights reserved.
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals);
// Parallel SpMV using CSR format
__global__ void spmv_csr(const int *row_ptr, const int *col_ind, const float *values, const int num_rows, const float *x, float *y) {
// Uses a grid-stride loop to perform dot product
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < num_rows; i += blockDim.x * gridDim.x) {
float dotProduct = 0;
const int row_start = row_ptr[i];
const int row_end = row_ptr[i + 1];
for (int j = row_start; j < row_end; j++) {
dotProduct += values[j] * x[col_ind[j]];
}
y[i] = dotProduct;
}
}
int main(int argc, const char * argv[]) {
if (argc != 5) {
fprintf(stdout, "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n");
exit(0);
}
int *row_ptr, *col_ind, num_rows, num_cols, num_vals, numSMs;;
float *values;
int num_thread = atoi(argv[1]);
int num_repeat = atoi(argv[2]);
int print_mode = atoi(argv[3]);
const char *filename = argv[4];
read_matrix(&row_ptr, &col_ind, &values, filename, &num_rows, &num_cols, &num_vals);
float *x = (float *) malloc(num_rows * sizeof(float));
float *y = (float *) malloc(num_rows * sizeof(float));
for (int i = 0; i < num_rows; i++) {
x[i] = 1.0;
y[i] = 0.0;
}
if (print_mode == 1) {
// Values Array
fprintf(stdout, "Values Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%.6f ", values[i]);
}
// Column Indices Array
fprintf(stdout, "\n\nColumn Indices Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%d ", col_ind[i]);
}
// Row Pointer Array
fprintf(stdout, "\n\nRow Pointer Array:\n");
for (int i = 0; i < (num_rows + 1); i++) {
fprintf(stdout, "%d ", row_ptr[i]);
}
fprintf(stdout, "\n\nInitial Vector:\n");
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.1f ", x[i]);
}
fprintf(stdout, "\n\nResulting Vector:\n");
}
// Allocate on device
int *d_row_ptr, *d_col_ind;
float *d_values, *d_x, *d_y;
cudaMalloc((void**)&d_row_ptr, (num_rows + 1) * sizeof(int));
cudaMalloc((void**)&d_col_ind, num_vals * sizeof(int));
cudaMalloc((void**)&d_values, num_vals * sizeof(float));
cudaMalloc((void**)&d_x, num_rows * sizeof(float));
cudaMalloc((void**)&d_y, num_rows * sizeof(float));
// Get number of SMs
cudaDeviceGetAttribute(&numSMs, cudaDevAttrMultiProcessorCount, 0);
// Copy from host to device
cudaMemcpy(d_row_ptr, row_ptr, (num_rows + 1) * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_col_ind, col_ind, num_vals * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_values, values, num_vals * sizeof(float), cudaMemcpyHostToDevice);
// Time the iterations
float elapsed_time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
for (int i = 0; i < num_repeat; i++) {
cudaMemcpy(d_x, x, num_rows * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, num_rows * sizeof(float), cudaMemcpyHostToDevice);
// Call kernel function
spmv_csr<<<32 * numSMs, num_thread>>>(d_row_ptr, d_col_ind, d_values, num_rows, d_x, d_y);
// Copy the result to x_{i} at the end of each iteration, and use it in iteration x_{i+1}
cudaMemcpy(y, d_y, num_rows * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < num_rows; i++) {
x[i] = y[i];
y[i] = 0.0;
}
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time, start, stop);
// Print resulting vector
if (print_mode == 1 || print_mode == 2) {
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.6f ", x[i]);
}
fprintf(stdout, "\n");
}
// Print elapsed time
// printf("\nParallel Running time: %.4f ms\n", elapsed_time);
// printf("Num SMs: %d\n", numSMs);
// Free
cudaFree(d_row_ptr);
cudaFree(d_col_ind);
cudaFree(d_values);
cudaFree(d_x);
cudaFree(d_y);
free(row_ptr);
free(col_ind);
free(values);
return 0;
}
// Reads a sparse matrix and represents it using CSR (Compressed Sparse Row) format
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals) {
FILE *file = fopen(filename, "r");
if (file == NULL) {
fprintf(stdout, "File cannot be opened!\n");
exit(0);
}
// Get number of rows, columns, and non-zero values
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int *row_ptr_t = (int *) malloc((*num_rows + 1) * sizeof(int));
int *col_ind_t = (int *) malloc(*num_vals * sizeof(int));
float *values_t = (float *) malloc(*num_vals * sizeof(float));
// Collect occurances of each row for determining the indices of row_ptr
int *row_occurances = (int *) malloc(*num_rows * sizeof(int));
for (int i = 0; i < *num_rows; i++) {
row_occurances[i] = 0;
}
int row, column;
float value;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
// Subtract 1 from row and column indices to match C format
row--;
column--;
row_occurances[row]++;
}
// Set row_ptr
int index = 0;
for (int i = 0; i < *num_rows; i++) {
row_ptr_t[i] = index;
index += row_occurances[i];
}
row_ptr_t[*num_rows] = *num_vals;
free(row_occurances);
// Set the file position to the beginning of the file
rewind(file);
// Read the file again, save column indices and values
for (int i = 0; i < *num_vals; i++) {
col_ind_t[i] = -1;
}
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int i = 0;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
row--;
column--;
// Find the correct index (i + row_ptr_t[row]) using both row information and an index i
while (col_ind_t[i + row_ptr_t[row]] != -1) {
i++;
}
col_ind_t[i + row_ptr_t[row]] = column;
values_t[i + row_ptr_t[row]] = value;
i = 0;
}
fclose(file);
*row_ptr = row_ptr_t;
*col_ind = col_ind_t;
*values = values_t;
} | .file "tmpxft_0008cc3b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "File cannot be opened!\n"
.LC2:
.string "%d %d %d\n"
.LC3:
.string "%d %d %f\n"
.text
.globl _Z11read_matrixPPiS0_PPfPKcS_S_S_
.type _Z11read_matrixPPiS0_PPfPKcS_S_S_, @function
_Z11read_matrixPPiS0_PPfPKcS_S_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, %rdi
movq %r8, 8(%rsp)
movq %r9, 16(%rsp)
movq 144(%rsp), %r15
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L23
movq %rax, %rbp
movq %r15, %r8
movq 16(%rsp), %rcx
movq 8(%rsp), %r14
movq %r14, %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl (%r14), %eax
movl %eax, 8(%rsp)
leal 1(%rax), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movslq (%r15), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbx
movslq (%r15), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
movq %r14, 8(%rsp)
movslq (%r14), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
movq 8(%rsp), %rax
movl (%rax), %edx
testl %edx, %edx
jle .L7
movq %r14, %rax
movslq %edx, %rdx
leaq (%r14,%rdx,4), %rdx
.L6:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L6
jmp .L7
.L23:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L8:
movl 60(%rsp), %eax
subl $1, %eax
movl %eax, 60(%rsp)
subl $1, 64(%rsp)
cltq
addl $1, (%r14,%rax,4)
.L7:
leaq 64(%rsp), %rcx
leaq 60(%rsp), %rdx
leaq 68(%rsp), %r8
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
jne .L8
movq 8(%rsp), %rax
movl (%rax), %esi
testl %esi, %esi
jle .L9
movslq %esi, %rcx
salq $2, %rcx
movl $0, %eax
movl $0, %edx
.L10:
movl %edx, (%r12,%rax)
addl (%r14,%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L10
.L9:
movslq %esi, %rsi
movl (%r15), %eax
movl %eax, (%r12,%rsi,4)
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call rewind@PLT
movl (%r15), %edx
testl %edx, %edx
jle .L11
movq %rbx, %rax
movslq %edx, %rdx
leaq (%rbx,%rdx,4), %rdx
.L12:
movl $-1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
.L11:
movq %r15, %r8
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq .LC3(%rip), %r14
jmp .L13
.L14:
movl %ecx, (%rax)
movss 68(%rsp), %xmm0
movss %xmm0, 0(%r13,%rdx)
.L13:
leaq 64(%rsp), %rcx
leaq 60(%rsp), %rdx
leaq 68(%rsp), %r8
movq %r14, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L24
movl 60(%rsp), %eax
subl $1, %eax
movl %eax, 60(%rsp)
movl 64(%rsp), %esi
leal -1(%rsi), %ecx
movl %ecx, 64(%rsp)
cltq
movslq (%r12,%rax,4), %rdx
salq $2, %rdx
leaq (%rbx,%rdx), %rax
cmpl $-1, (%rax)
je .L14
leaq 4(%rdx), %rax
.L15:
movq %rax, %rdx
addq $4, %rax
cmpl $-1, -4(%rbx,%rax)
jne .L15
leaq (%rbx,%rdx), %rax
jmp .L14
.L24:
movq %rbp, %rdi
call fclose@PLT
movq 24(%rsp), %rax
movq %r12, (%rax)
movq 32(%rsp), %rax
movq %rbx, (%rax)
movq 40(%rsp), %rax
movq %r13, (%rax)
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11read_matrixPPiS0_PPfPKcS_S_S_, .-_Z11read_matrixPPiS0_PPfPKcS_S_S_
.globl _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
.type _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf, @function
_Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8spmv_csrPKiS0_PKfiS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf, .-_Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
.globl _Z8spmv_csrPKiS0_PKfiS2_Pf
.type _Z8spmv_csrPKiS0_PKfiS2_Pf, @function
_Z8spmv_csrPKiS0_PKfiS2_Pf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8spmv_csrPKiS0_PKfiS2_Pf, .-_Z8spmv_csrPKiS0_PKfiS2_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n"
.section .rodata.str1.1
.LC7:
.string "Values Array:\n"
.LC8:
.string "%.6f "
.LC9:
.string "\n\nColumn Indices Array:\n"
.LC10:
.string "%d "
.LC11:
.string "\n\nRow Pointer Array:\n"
.LC12:
.string "\n\nInitial Vector:\n"
.LC13:
.string "%.1f "
.LC14:
.string "\n\nResulting Vector:\n"
.LC15:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
cmpl $5, %edi
je .L35
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L35:
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movl %eax, %r14d
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, (%rsp)
movq 32(%rbx), %rcx
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 232
leaq 48(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 240
leaq 52(%rsp), %r9
leaq 48(%rsp), %r8
call _Z11read_matrixPPiS0_PPfPKcS_S_S_
movl 48(%rsp), %r15d
movslq %r15d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 224
testl %r15d, %r15d
jle .L36
movl $0, %eax
movss .LC5(%rip), %xmm0
.L37:
movss %xmm0, 0(%rbp,%rax)
movl $0x00000000, (%rbx,%rax)
addq $4, %rax
cmpq %rax, %r12
jne .L37
.L36:
cmpl $1, (%rsp)
je .L61
.L38:
movl 32(%rsp), %eax
leal 1(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 40(%rsp), %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movslq 40(%rsp), %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movslq 32(%rsp), %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
movslq 32(%rsp), %rsi
salq $2, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
leaq 44(%rsp), %rdi
movl $0, %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
movq 48(%rsp), %r15
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rsi
movq %rsi, 8(%rsp)
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movq 64(%rsp), %rsi
movq %rsi, 16(%rsp)
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
call cudaEventCreate@PLT
leaq 120(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 112(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $0, 24(%rsp)
jle .L47
movl $0, %r12d
jmp .L51
.L61:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
leaq .LC8(%rip), %r15
jmp .L39
.L40:
movq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%r12,4), %xmm0
movq %r15, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %r12
.L39:
cmpl %r12d, 40(%rsp)
jg .L40
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
leaq .LC10(%rip), %r15
jmp .L41
.L42:
movq 56(%rsp), %rax
movl (%rax,%r12,4), %ecx
movq %r15, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %r12
.L41:
cmpl %r12d, 40(%rsp)
jg .L42
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
leaq .LC10(%rip), %r15
jmp .L43
.L44:
movq 48(%rsp), %rax
movl (%rax,%r12,4), %ecx
movq %r15, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %r12
.L43:
cmpl %r12d, 32(%rsp)
jge .L44
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
leaq .LC13(%rip), %r15
jmp .L45
.L46:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12,4), %xmm0
movq %r15, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %r12
.L45:
cmpl %r12d, 32(%rsp)
jg .L46
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L38
.L48:
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 104(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %edx
testl %edx, %edx
jle .L49
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L50:
movss (%rbx,%rax), %xmm0
movss %xmm0, 0(%rbp,%rax)
movl $0x00000000, (%rbx,%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L50
.L49:
addl $1, %r12d
cmpl %r14d, %r12d
je .L47
.L51:
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl 44(%rsp), %eax
sall $5, %eax
movl %eax, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movl 32(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
jmp .L48
.L47:
movl $0, %esi
movq 120(%rsp), %rdi
call cudaEventRecord@PLT
movq 120(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 140(%rsp), %rdi
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl (%rsp), %eax
subl $1, %eax
cmpl $1, %eax
jbe .L62
.L52:
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
cmpl $0, 32(%rsp)
jle .L53
movl $0, %ebx
leaq .LC8(%rip), %r12
.L54:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, 32(%rsp)
jg .L54
.L53:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L52
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z8spmv_csrPKiS0_PKfiS2_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8spmv_csrPKiS0_PKfiS2_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// main.cu
// CS 426 - Project 4
//
// Created by Muhammed Cavusoglu on 19.05.2019.
// Copyright © 2019 Muhammed Cavusoglu. All rights reserved.
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals);
// Parallel SpMV using CSR format
__global__ void spmv_csr(const int *row_ptr, const int *col_ind, const float *values, const int num_rows, const float *x, float *y) {
// Uses a grid-stride loop to perform dot product
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < num_rows; i += blockDim.x * gridDim.x) {
float dotProduct = 0;
const int row_start = row_ptr[i];
const int row_end = row_ptr[i + 1];
for (int j = row_start; j < row_end; j++) {
dotProduct += values[j] * x[col_ind[j]];
}
y[i] = dotProduct;
}
}
int main(int argc, const char * argv[]) {
if (argc != 5) {
fprintf(stdout, "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n");
exit(0);
}
int *row_ptr, *col_ind, num_rows, num_cols, num_vals, numSMs;;
float *values;
int num_thread = atoi(argv[1]);
int num_repeat = atoi(argv[2]);
int print_mode = atoi(argv[3]);
const char *filename = argv[4];
read_matrix(&row_ptr, &col_ind, &values, filename, &num_rows, &num_cols, &num_vals);
float *x = (float *) malloc(num_rows * sizeof(float));
float *y = (float *) malloc(num_rows * sizeof(float));
for (int i = 0; i < num_rows; i++) {
x[i] = 1.0;
y[i] = 0.0;
}
if (print_mode == 1) {
// Values Array
fprintf(stdout, "Values Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%.6f ", values[i]);
}
// Column Indices Array
fprintf(stdout, "\n\nColumn Indices Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%d ", col_ind[i]);
}
// Row Pointer Array
fprintf(stdout, "\n\nRow Pointer Array:\n");
for (int i = 0; i < (num_rows + 1); i++) {
fprintf(stdout, "%d ", row_ptr[i]);
}
fprintf(stdout, "\n\nInitial Vector:\n");
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.1f ", x[i]);
}
fprintf(stdout, "\n\nResulting Vector:\n");
}
// Allocate on device
int *d_row_ptr, *d_col_ind;
float *d_values, *d_x, *d_y;
cudaMalloc((void**)&d_row_ptr, (num_rows + 1) * sizeof(int));
cudaMalloc((void**)&d_col_ind, num_vals * sizeof(int));
cudaMalloc((void**)&d_values, num_vals * sizeof(float));
cudaMalloc((void**)&d_x, num_rows * sizeof(float));
cudaMalloc((void**)&d_y, num_rows * sizeof(float));
// Get number of SMs
cudaDeviceGetAttribute(&numSMs, cudaDevAttrMultiProcessorCount, 0);
// Copy from host to device
cudaMemcpy(d_row_ptr, row_ptr, (num_rows + 1) * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_col_ind, col_ind, num_vals * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_values, values, num_vals * sizeof(float), cudaMemcpyHostToDevice);
// Time the iterations
float elapsed_time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
for (int i = 0; i < num_repeat; i++) {
cudaMemcpy(d_x, x, num_rows * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, num_rows * sizeof(float), cudaMemcpyHostToDevice);
// Call kernel function
spmv_csr<<<32 * numSMs, num_thread>>>(d_row_ptr, d_col_ind, d_values, num_rows, d_x, d_y);
// Copy the result to x_{i} at the end of each iteration, and use it in iteration x_{i+1}
cudaMemcpy(y, d_y, num_rows * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < num_rows; i++) {
x[i] = y[i];
y[i] = 0.0;
}
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time, start, stop);
// Print resulting vector
if (print_mode == 1 || print_mode == 2) {
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.6f ", x[i]);
}
fprintf(stdout, "\n");
}
// Print elapsed time
// printf("\nParallel Running time: %.4f ms\n", elapsed_time);
// printf("Num SMs: %d\n", numSMs);
// Free
cudaFree(d_row_ptr);
cudaFree(d_col_ind);
cudaFree(d_values);
cudaFree(d_x);
cudaFree(d_y);
free(row_ptr);
free(col_ind);
free(values);
return 0;
}
// Reads a sparse matrix and represents it using CSR (Compressed Sparse Row) format
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals) {
FILE *file = fopen(filename, "r");
if (file == NULL) {
fprintf(stdout, "File cannot be opened!\n");
exit(0);
}
// Get number of rows, columns, and non-zero values
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int *row_ptr_t = (int *) malloc((*num_rows + 1) * sizeof(int));
int *col_ind_t = (int *) malloc(*num_vals * sizeof(int));
float *values_t = (float *) malloc(*num_vals * sizeof(float));
// Collect occurances of each row for determining the indices of row_ptr
int *row_occurances = (int *) malloc(*num_rows * sizeof(int));
for (int i = 0; i < *num_rows; i++) {
row_occurances[i] = 0;
}
int row, column;
float value;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
// Subtract 1 from row and column indices to match C format
row--;
column--;
row_occurances[row]++;
}
// Set row_ptr
int index = 0;
for (int i = 0; i < *num_rows; i++) {
row_ptr_t[i] = index;
index += row_occurances[i];
}
row_ptr_t[*num_rows] = *num_vals;
free(row_occurances);
// Set the file position to the beginning of the file
rewind(file);
// Read the file again, save column indices and values
for (int i = 0; i < *num_vals; i++) {
col_ind_t[i] = -1;
}
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int i = 0;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
row--;
column--;
// Find the correct index (i + row_ptr_t[row]) using both row information and an index i
while (col_ind_t[i + row_ptr_t[row]] != -1) {
i++;
}
col_ind_t[i + row_ptr_t[row]] = column;
values_t[i + row_ptr_t[row]] = value;
i = 0;
}
fclose(file);
*row_ptr = row_ptr_t;
*col_ind = col_ind_t;
*values = values_t;
} | //
// main.cu
// CS 426 - Project 4
//
// Created by Muhammed Cavusoglu on 19.05.2019.
// Copyright © 2019 Muhammed Cavusoglu. All rights reserved.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals);
// Parallel SpMV using CSR format
__global__ void spmv_csr(const int *row_ptr, const int *col_ind, const float *values, const int num_rows, const float *x, float *y) {
// Uses a grid-stride loop to perform dot product
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < num_rows; i += blockDim.x * gridDim.x) {
float dotProduct = 0;
const int row_start = row_ptr[i];
const int row_end = row_ptr[i + 1];
for (int j = row_start; j < row_end; j++) {
dotProduct += values[j] * x[col_ind[j]];
}
y[i] = dotProduct;
}
}
int main(int argc, const char * argv[]) {
if (argc != 5) {
fprintf(stdout, "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n");
exit(0);
}
int *row_ptr, *col_ind, num_rows, num_cols, num_vals, numSMs;;
float *values;
int num_thread = atoi(argv[1]);
int num_repeat = atoi(argv[2]);
int print_mode = atoi(argv[3]);
const char *filename = argv[4];
read_matrix(&row_ptr, &col_ind, &values, filename, &num_rows, &num_cols, &num_vals);
float *x = (float *) malloc(num_rows * sizeof(float));
float *y = (float *) malloc(num_rows * sizeof(float));
for (int i = 0; i < num_rows; i++) {
x[i] = 1.0;
y[i] = 0.0;
}
if (print_mode == 1) {
// Values Array
fprintf(stdout, "Values Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%.6f ", values[i]);
}
// Column Indices Array
fprintf(stdout, "\n\nColumn Indices Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%d ", col_ind[i]);
}
// Row Pointer Array
fprintf(stdout, "\n\nRow Pointer Array:\n");
for (int i = 0; i < (num_rows + 1); i++) {
fprintf(stdout, "%d ", row_ptr[i]);
}
fprintf(stdout, "\n\nInitial Vector:\n");
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.1f ", x[i]);
}
fprintf(stdout, "\n\nResulting Vector:\n");
}
// Allocate on device
int *d_row_ptr, *d_col_ind;
float *d_values, *d_x, *d_y;
hipMalloc((void**)&d_row_ptr, (num_rows + 1) * sizeof(int));
hipMalloc((void**)&d_col_ind, num_vals * sizeof(int));
hipMalloc((void**)&d_values, num_vals * sizeof(float));
hipMalloc((void**)&d_x, num_rows * sizeof(float));
hipMalloc((void**)&d_y, num_rows * sizeof(float));
// Get number of SMs
hipDeviceGetAttribute(&numSMs, hipDeviceAttributeMultiprocessorCount, 0);
// Copy from host to device
hipMemcpy(d_row_ptr, row_ptr, (num_rows + 1) * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_col_ind, col_ind, num_vals * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_values, values, num_vals * sizeof(float), hipMemcpyHostToDevice);
// Time the iterations
float elapsed_time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
for (int i = 0; i < num_repeat; i++) {
hipMemcpy(d_x, x, num_rows * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, num_rows * sizeof(float), hipMemcpyHostToDevice);
// Call kernel function
spmv_csr<<<32 * numSMs, num_thread>>>(d_row_ptr, d_col_ind, d_values, num_rows, d_x, d_y);
// Copy the result to x_{i} at the end of each iteration, and use it in iteration x_{i+1}
hipMemcpy(y, d_y, num_rows * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < num_rows; i++) {
x[i] = y[i];
y[i] = 0.0;
}
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time, start, stop);
// Print resulting vector
if (print_mode == 1 || print_mode == 2) {
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.6f ", x[i]);
}
fprintf(stdout, "\n");
}
// Print elapsed time
// printf("\nParallel Running time: %.4f ms\n", elapsed_time);
// printf("Num SMs: %d\n", numSMs);
// Free
hipFree(d_row_ptr);
hipFree(d_col_ind);
hipFree(d_values);
hipFree(d_x);
hipFree(d_y);
free(row_ptr);
free(col_ind);
free(values);
return 0;
}
// Reads a sparse matrix and represents it using CSR (Compressed Sparse Row) format
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals) {
FILE *file = fopen(filename, "r");
if (file == NULL) {
fprintf(stdout, "File cannot be opened!\n");
exit(0);
}
// Get number of rows, columns, and non-zero values
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int *row_ptr_t = (int *) malloc((*num_rows + 1) * sizeof(int));
int *col_ind_t = (int *) malloc(*num_vals * sizeof(int));
float *values_t = (float *) malloc(*num_vals * sizeof(float));
// Collect occurances of each row for determining the indices of row_ptr
int *row_occurances = (int *) malloc(*num_rows * sizeof(int));
for (int i = 0; i < *num_rows; i++) {
row_occurances[i] = 0;
}
int row, column;
float value;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
// Subtract 1 from row and column indices to match C format
row--;
column--;
row_occurances[row]++;
}
// Set row_ptr
int index = 0;
for (int i = 0; i < *num_rows; i++) {
row_ptr_t[i] = index;
index += row_occurances[i];
}
row_ptr_t[*num_rows] = *num_vals;
free(row_occurances);
// Set the file position to the beginning of the file
rewind(file);
// Read the file again, save column indices and values
for (int i = 0; i < *num_vals; i++) {
col_ind_t[i] = -1;
}
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int i = 0;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
row--;
column--;
// Find the correct index (i + row_ptr_t[row]) using both row information and an index i
while (col_ind_t[i + row_ptr_t[row]] != -1) {
i++;
}
col_ind_t[i + row_ptr_t[row]] = column;
values_t[i + row_ptr_t[row]] = value;
i = 0;
}
fclose(file);
*row_ptr = row_ptr_t;
*col_ind = col_ind_t;
*values = values_t;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// main.cu
// CS 426 - Project 4
//
// Created by Muhammed Cavusoglu on 19.05.2019.
// Copyright © 2019 Muhammed Cavusoglu. All rights reserved.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals);
// Parallel SpMV using CSR format
__global__ void spmv_csr(const int *row_ptr, const int *col_ind, const float *values, const int num_rows, const float *x, float *y) {
// Uses a grid-stride loop to perform dot product
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < num_rows; i += blockDim.x * gridDim.x) {
float dotProduct = 0;
const int row_start = row_ptr[i];
const int row_end = row_ptr[i + 1];
for (int j = row_start; j < row_end; j++) {
dotProduct += values[j] * x[col_ind[j]];
}
y[i] = dotProduct;
}
}
int main(int argc, const char * argv[]) {
if (argc != 5) {
fprintf(stdout, "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n");
exit(0);
}
int *row_ptr, *col_ind, num_rows, num_cols, num_vals, numSMs;;
float *values;
int num_thread = atoi(argv[1]);
int num_repeat = atoi(argv[2]);
int print_mode = atoi(argv[3]);
const char *filename = argv[4];
read_matrix(&row_ptr, &col_ind, &values, filename, &num_rows, &num_cols, &num_vals);
float *x = (float *) malloc(num_rows * sizeof(float));
float *y = (float *) malloc(num_rows * sizeof(float));
for (int i = 0; i < num_rows; i++) {
x[i] = 1.0;
y[i] = 0.0;
}
if (print_mode == 1) {
// Values Array
fprintf(stdout, "Values Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%.6f ", values[i]);
}
// Column Indices Array
fprintf(stdout, "\n\nColumn Indices Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%d ", col_ind[i]);
}
// Row Pointer Array
fprintf(stdout, "\n\nRow Pointer Array:\n");
for (int i = 0; i < (num_rows + 1); i++) {
fprintf(stdout, "%d ", row_ptr[i]);
}
fprintf(stdout, "\n\nInitial Vector:\n");
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.1f ", x[i]);
}
fprintf(stdout, "\n\nResulting Vector:\n");
}
// Allocate on device
int *d_row_ptr, *d_col_ind;
float *d_values, *d_x, *d_y;
hipMalloc((void**)&d_row_ptr, (num_rows + 1) * sizeof(int));
hipMalloc((void**)&d_col_ind, num_vals * sizeof(int));
hipMalloc((void**)&d_values, num_vals * sizeof(float));
hipMalloc((void**)&d_x, num_rows * sizeof(float));
hipMalloc((void**)&d_y, num_rows * sizeof(float));
// Get number of SMs
hipDeviceGetAttribute(&numSMs, hipDeviceAttributeMultiprocessorCount, 0);
// Copy from host to device
hipMemcpy(d_row_ptr, row_ptr, (num_rows + 1) * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_col_ind, col_ind, num_vals * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_values, values, num_vals * sizeof(float), hipMemcpyHostToDevice);
// Time the iterations
float elapsed_time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
for (int i = 0; i < num_repeat; i++) {
hipMemcpy(d_x, x, num_rows * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, num_rows * sizeof(float), hipMemcpyHostToDevice);
// Call kernel function
spmv_csr<<<32 * numSMs, num_thread>>>(d_row_ptr, d_col_ind, d_values, num_rows, d_x, d_y);
// Copy the result to x_{i} at the end of each iteration, and use it in iteration x_{i+1}
hipMemcpy(y, d_y, num_rows * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < num_rows; i++) {
x[i] = y[i];
y[i] = 0.0;
}
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time, start, stop);
// Print resulting vector
if (print_mode == 1 || print_mode == 2) {
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.6f ", x[i]);
}
fprintf(stdout, "\n");
}
// Print elapsed time
// printf("\nParallel Running time: %.4f ms\n", elapsed_time);
// printf("Num SMs: %d\n", numSMs);
// Free
hipFree(d_row_ptr);
hipFree(d_col_ind);
hipFree(d_values);
hipFree(d_x);
hipFree(d_y);
free(row_ptr);
free(col_ind);
free(values);
return 0;
}
// Reads a sparse matrix and represents it using CSR (Compressed Sparse Row) format
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals) {
FILE *file = fopen(filename, "r");
if (file == NULL) {
fprintf(stdout, "File cannot be opened!\n");
exit(0);
}
// Get number of rows, columns, and non-zero values
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int *row_ptr_t = (int *) malloc((*num_rows + 1) * sizeof(int));
int *col_ind_t = (int *) malloc(*num_vals * sizeof(int));
float *values_t = (float *) malloc(*num_vals * sizeof(float));
// Collect occurances of each row for determining the indices of row_ptr
int *row_occurances = (int *) malloc(*num_rows * sizeof(int));
for (int i = 0; i < *num_rows; i++) {
row_occurances[i] = 0;
}
int row, column;
float value;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
// Subtract 1 from row and column indices to match C format
row--;
column--;
row_occurances[row]++;
}
// Set row_ptr
int index = 0;
for (int i = 0; i < *num_rows; i++) {
row_ptr_t[i] = index;
index += row_occurances[i];
}
row_ptr_t[*num_rows] = *num_vals;
free(row_occurances);
// Set the file position to the beginning of the file
rewind(file);
// Read the file again, save column indices and values
for (int i = 0; i < *num_vals; i++) {
col_ind_t[i] = -1;
}
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int i = 0;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
row--;
column--;
// Find the correct index (i + row_ptr_t[row]) using both row information and an index i
while (col_ind_t[i + row_ptr_t[row]] != -1) {
i++;
}
col_ind_t[i + row_ptr_t[row]] = column;
values_t[i + row_ptr_t[row]] = value;
i = 0;
}
fclose(file);
*row_ptr = row_ptr_t;
*col_ind = col_ind_t;
*values = values_t;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8spmv_csrPKiS0_PKfiS2_Pf
.globl _Z8spmv_csrPKiS0_PKfiS2_Pf
.p2align 8
.type _Z8spmv_csrPKiS0_PKfiS2_Pf,@function
_Z8spmv_csrPKiS0_PKfiS2_Pf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_7
s_load_b32 s14, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s14, s13
s_mov_b32 s13, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v2, s0, s10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
v_cmp_le_i32_e32 vcc_lo, s12, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v4, v5
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v7, 31, v4
v_mov_b32_e32 v6, v4
v_mov_b32_e32 v0, 0
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
.p2align 6
.LBB0_5:
global_load_b32 v10, v[8:9], off
v_add_nc_u32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v4, v5
s_or_b32 s15, s0, s15
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s8, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_load_b32 v12, v[6:7], off
global_load_b32 v10, v[10:11], off
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v12, v10
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s15
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8spmv_csrPKiS0_PKfiS2_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8spmv_csrPKiS0_PKfiS2_Pf, .Lfunc_end0-_Z8spmv_csrPKiS0_PKfiS2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8spmv_csrPKiS0_PKfiS2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8spmv_csrPKiS0_PKfiS2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// main.cu
// CS 426 - Project 4
//
// Created by Muhammed Cavusoglu on 19.05.2019.
// Copyright © 2019 Muhammed Cavusoglu. All rights reserved.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals);
// Parallel SpMV using CSR format
__global__ void spmv_csr(const int *row_ptr, const int *col_ind, const float *values, const int num_rows, const float *x, float *y) {
// Uses a grid-stride loop to perform dot product
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < num_rows; i += blockDim.x * gridDim.x) {
float dotProduct = 0;
const int row_start = row_ptr[i];
const int row_end = row_ptr[i + 1];
for (int j = row_start; j < row_end; j++) {
dotProduct += values[j] * x[col_ind[j]];
}
y[i] = dotProduct;
}
}
int main(int argc, const char * argv[]) {
if (argc != 5) {
fprintf(stdout, "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n");
exit(0);
}
int *row_ptr, *col_ind, num_rows, num_cols, num_vals, numSMs;;
float *values;
int num_thread = atoi(argv[1]);
int num_repeat = atoi(argv[2]);
int print_mode = atoi(argv[3]);
const char *filename = argv[4];
read_matrix(&row_ptr, &col_ind, &values, filename, &num_rows, &num_cols, &num_vals);
float *x = (float *) malloc(num_rows * sizeof(float));
float *y = (float *) malloc(num_rows * sizeof(float));
for (int i = 0; i < num_rows; i++) {
x[i] = 1.0;
y[i] = 0.0;
}
if (print_mode == 1) {
// Values Array
fprintf(stdout, "Values Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%.6f ", values[i]);
}
// Column Indices Array
fprintf(stdout, "\n\nColumn Indices Array:\n");
for (int i = 0; i < num_vals; i++) {
fprintf(stdout, "%d ", col_ind[i]);
}
// Row Pointer Array
fprintf(stdout, "\n\nRow Pointer Array:\n");
for (int i = 0; i < (num_rows + 1); i++) {
fprintf(stdout, "%d ", row_ptr[i]);
}
fprintf(stdout, "\n\nInitial Vector:\n");
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.1f ", x[i]);
}
fprintf(stdout, "\n\nResulting Vector:\n");
}
// Allocate on device
int *d_row_ptr, *d_col_ind;
float *d_values, *d_x, *d_y;
hipMalloc((void**)&d_row_ptr, (num_rows + 1) * sizeof(int));
hipMalloc((void**)&d_col_ind, num_vals * sizeof(int));
hipMalloc((void**)&d_values, num_vals * sizeof(float));
hipMalloc((void**)&d_x, num_rows * sizeof(float));
hipMalloc((void**)&d_y, num_rows * sizeof(float));
// Get number of SMs
hipDeviceGetAttribute(&numSMs, hipDeviceAttributeMultiprocessorCount, 0);
// Copy from host to device
hipMemcpy(d_row_ptr, row_ptr, (num_rows + 1) * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_col_ind, col_ind, num_vals * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_values, values, num_vals * sizeof(float), hipMemcpyHostToDevice);
// Time the iterations
float elapsed_time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
for (int i = 0; i < num_repeat; i++) {
hipMemcpy(d_x, x, num_rows * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, num_rows * sizeof(float), hipMemcpyHostToDevice);
// Call kernel function
spmv_csr<<<32 * numSMs, num_thread>>>(d_row_ptr, d_col_ind, d_values, num_rows, d_x, d_y);
// Copy the result to x_{i} at the end of each iteration, and use it in iteration x_{i+1}
hipMemcpy(y, d_y, num_rows * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < num_rows; i++) {
x[i] = y[i];
y[i] = 0.0;
}
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time, start, stop);
// Print resulting vector
if (print_mode == 1 || print_mode == 2) {
for (int i = 0; i < num_rows; i++) {
fprintf(stdout, "%.6f ", x[i]);
}
fprintf(stdout, "\n");
}
// Print elapsed time
// printf("\nParallel Running time: %.4f ms\n", elapsed_time);
// printf("Num SMs: %d\n", numSMs);
// Free
hipFree(d_row_ptr);
hipFree(d_col_ind);
hipFree(d_values);
hipFree(d_x);
hipFree(d_y);
free(row_ptr);
free(col_ind);
free(values);
return 0;
}
// Reads a sparse matrix and represents it using CSR (Compressed Sparse Row) format
void read_matrix(int **row_ptr, int **col_ind, float **values, const char *filename, int *num_rows, int *num_cols, int *num_vals) {
FILE *file = fopen(filename, "r");
if (file == NULL) {
fprintf(stdout, "File cannot be opened!\n");
exit(0);
}
// Get number of rows, columns, and non-zero values
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int *row_ptr_t = (int *) malloc((*num_rows + 1) * sizeof(int));
int *col_ind_t = (int *) malloc(*num_vals * sizeof(int));
float *values_t = (float *) malloc(*num_vals * sizeof(float));
// Collect occurances of each row for determining the indices of row_ptr
int *row_occurances = (int *) malloc(*num_rows * sizeof(int));
for (int i = 0; i < *num_rows; i++) {
row_occurances[i] = 0;
}
int row, column;
float value;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
// Subtract 1 from row and column indices to match C format
row--;
column--;
row_occurances[row]++;
}
// Set row_ptr
int index = 0;
for (int i = 0; i < *num_rows; i++) {
row_ptr_t[i] = index;
index += row_occurances[i];
}
row_ptr_t[*num_rows] = *num_vals;
free(row_occurances);
// Set the file position to the beginning of the file
rewind(file);
// Read the file again, save column indices and values
for (int i = 0; i < *num_vals; i++) {
col_ind_t[i] = -1;
}
fscanf(file, "%d %d %d\n", num_rows, num_cols, num_vals);
int i = 0;
while (fscanf(file, "%d %d %f\n", &row, &column, &value) != EOF) {
row--;
column--;
// Find the correct index (i + row_ptr_t[row]) using both row information and an index i
while (col_ind_t[i + row_ptr_t[row]] != -1) {
i++;
}
col_ind_t[i + row_ptr_t[row]] = column;
values_t[i + row_ptr_t[row]] = value;
i = 0;
}
fclose(file);
*row_ptr = row_ptr_t;
*col_ind = col_ind_t;
*values = values_t;
} | .text
.file "main.hip"
.globl _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf # -- Begin function _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.p2align 4, 0x90
.type _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf,@function
_Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf: # @_Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8spmv_csrPKiS0_PKfiS2_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf, .Lfunc_end0-_Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB1_32
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 104(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 32(%rbx), %rcx
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 20(%rsp), %rax
leaq 104(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 16(%rsp), %r8
leaq 244(%rsp), %r9
pushq %rax
.cfi_adjust_cfa_offset 8
callq _Z11read_matrixPPiS0_PPfPKcS_S_S_
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movslq 8(%rsp), %r13
leaq (,%r13,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r12
testq %r13, %r13
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r13d, %r14d
leaq (,%r14,4), %rdx
xorl %r13d, %r13d
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%r13,4) # imm = 0x3F800000
incq %r13
cmpq %r13, %r14
jne .LBB1_3
.LBB1_4: # %._crit_edge
cmpl $1, %ebp
jne .LBB1_18
# %bb.5:
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $14, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, 12(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph65
movq 80(%rsp), %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_7
.LBB1_8: # %._crit_edge66
movq stdout(%rip), %rcx
movl $.L.str.3, %edi
movl $24, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, 12(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph69
movq 88(%rsp), %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movl (%r14,%r13,4), %edx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_10
.LBB1_11: # %._crit_edge70
movq stdout(%rip), %rcx
movl $.L.str.5, %edi
movl $21, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, 8(%rsp)
js .LBB1_14
# %bb.12: # %.lr.ph74
movq $-1, %r14
movq 96(%rsp), %r13
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movl 4(%r13,%r14,4), %edx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movslq 8(%rsp), %rax
incq %r14
cmpq %rax, %r14
jl .LBB1_13
.LBB1_14: # %._crit_edge75
movq stdout(%rip), %rcx
movl $.L.str.6, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, 8(%rsp)
jle .LBB1_17
# %bb.15: # %.lr.ph78.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_16: # %.lr.ph78
# =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movb $1, %al
callq fprintf
incq %r14
movslq 8(%rsp), %rax
cmpq %rax, %r14
jl .LBB1_16
.LBB1_17: # %._crit_edge79
movq stdout(%rip), %rcx
movl $.L.str.8, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
.LBB1_18:
movq %rbp, 136(%rsp) # 8-byte Spill
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
leaq 64(%rsp), %rdi
xorl %r14d, %r14d
movl $63, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
movq 56(%rsp), %rdi
movq 96(%rsp), %rsi
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rdx
movq %rsi, 128(%rsp) # 8-byte Spill
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 88(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq %rsi, 120(%rsp) # 8-byte Spill
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 80(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq %rsi, 112(%rsp) # 8-byte Spill
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %r15d, %r15d
jle .LBB1_26
# %bb.19: # %.lr.ph86
movabsq $4294967296, %r13 # imm = 0x100000000
movl 104(%rsp), %ebp # 4-byte Reload
orq %r13, %rbp
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_25: # %._crit_edge83
# in Loop: Header=BB1_20 Depth=1
incl %r14d
cmpl %r15d, %r14d
je .LBB1_26
.LBB1_20: # =>This Loop Header: Depth=1
# Child Loop BB1_24 Depth 2
movq 32(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl 64(%rsp), %edi
shll $5, %edi
orq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_22
# %bb.21: # in Loop: Header=BB1_20 Depth=1
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movl 8(%rsp), %esi
movq 32(%rsp), %rdi
movq 16(%rsp), %r8
movq %rax, 224(%rsp)
movq %rcx, 216(%rsp)
movq %rdx, 208(%rsp)
movl %esi, 68(%rsp)
movq %rdi, 200(%rsp)
movq %r8, 192(%rsp)
leaq 224(%rsp), %rax
movq %rax, 240(%rsp)
leaq 216(%rsp), %rax
movq %rax, 248(%rsp)
leaq 208(%rsp), %rax
movq %rax, 256(%rsp)
leaq 68(%rsp), %rax
movq %rax, 264(%rsp)
leaq 200(%rsp), %rax
movq %rax, 272(%rsp)
leaq 192(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z8spmv_csrPKiS0_PKfiS2_Pf, %edi
leaq 240(%rsp), %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_22: # in Loop: Header=BB1_20 Depth=1
movq 16(%rsp), %rsi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_25
# %bb.23: # %.lr.ph82.preheader
# in Loop: Header=BB1_20 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_24: # %.lr.ph82
# Parent Loop BB1_20 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx,%rcx,4)
movl $0, (%r12,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_24
jmp .LBB1_25
.LBB1_26: # %._crit_edge87
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
movq 136(%rsp), %rax # 8-byte Reload
decl %eax
cmpl $1, %eax
ja .LBB1_31
# %bb.27: # %.preheader
cmpl $0, 8(%rsp)
jle .LBB1_30
# %bb.28: # %.lr.ph89.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_29: # %.lr.ph89
# =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
incq %r14
movslq 8(%rsp), %rax
cmpq %rax, %r14
jl .LBB1_29
.LBB1_30: # %._crit_edge90
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
.LBB1_31:
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi # 8-byte Reload
callq free
movq 120(%rsp), %rdi # 8-byte Reload
callq free
movq 112(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_32:
.cfi_def_cfa_offset 352
movq stdout(%rip), %rcx
movl $.L.str, %edi
movl $113, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11read_matrixPPiS0_PPfPKcS_S_S_ # -- Begin function _Z11read_matrixPPiS0_PPfPKcS_S_S_
.p2align 4, 0x90
.type _Z11read_matrixPPiS0_PPfPKcS_S_S_,@function
_Z11read_matrixPPiS0_PPfPKcS_S_S_: # @_Z11read_matrixPPiS0_PPfPKcS_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r13
movq %r8, %rbp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl $.L.str.10, %esi
movq %rcx, %rdi
callq fopen
testq %rax, %rax
je .LBB2_17
# %bb.1:
movq %rax, %r12
movq %r15, 48(%rsp) # 8-byte Spill
movq %r14, 56(%rsp) # 8-byte Spill
movq %rbx, 64(%rsp) # 8-byte Spill
movq 128(%rsp), %rbx
movl $.L.str.12, %esi
movq %rax, %rdi
movq %rbp, %rdx
movq %r13, 40(%rsp) # 8-byte Spill
movq %r13, %rcx
movq %rbx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbp, 24(%rsp) # 8-byte Spill
movslq (%rbp), %r15
leaq 4(,%r15,4), %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movslq (%rbx), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
leaq (,%r15,4), %rdi
callq malloc
movq %rax, %r14
testq %r15, %r15
jle .LBB2_3
# %bb.2: # %.lr.ph.preheader
movl %r15d, %edx
shlq $2, %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_3: # %._crit_edge
leaq 4(%rsp), %rdx
leaq 8(%rsp), %rcx
leaq 12(%rsp), %r8
movl $.L.str.13, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB2_6
# %bb.4:
leaq 4(%rsp), %rbx
leaq 8(%rsp), %r15
leaq 12(%rsp), %r13
.p2align 4, 0x90
.LBB2_5: # %.lr.ph69
# =>This Inner Loop Header: Depth=1
movslq 4(%rsp), %rax
leaq -1(%rax), %rcx
decl 8(%rsp)
movl %ecx, 4(%rsp)
incl -4(%r14,%rax,4)
movl $.L.str.13, %esi
movq %r12, %rdi
movq %rbx, %rdx
movq %r15, %rcx
movq %r13, %r8
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB2_5
.LBB2_6: # %.preheader
movq 24(%rsp), %rax # 8-byte Reload
movl (%rax), %eax
testl %eax, %eax
movq 16(%rsp), %rsi # 8-byte Reload
jle .LBB2_9
# %bb.7: # %.lr.ph72.preheader
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_8: # %.lr.ph72
# =>This Inner Loop Header: Depth=1
movl %edx, (%rsi,%rcx,4)
addl (%r14,%rcx,4), %edx
incq %rcx
cmpq %rcx, %rax
jne .LBB2_8
.LBB2_9: # %._crit_edge73
movq 128(%rsp), %rbx
movl (%rbx), %ecx
cltq
movl %ecx, (%rsi,%rax,4)
movq %r14, %rdi
callq free
movq %r12, %rdi
callq rewind
movl (%rbx), %edx
testl %edx, %edx
movq 64(%rsp), %r13 # 8-byte Reload
jle .LBB2_11
# %bb.10: # %.lr.ph76.preheader
shlq $2, %rdx
movq %rbp, %rdi
movl $255, %esi
callq memset@PLT
.LBB2_11: # %._crit_edge77
movl $.L.str.12, %esi
movq %r12, %rdi
movq 24(%rsp), %rdx # 8-byte Reload
movq 40(%rsp), %rcx # 8-byte Reload
movq %rbx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
leaq 4(%rsp), %rdx
leaq 8(%rsp), %rcx
leaq 12(%rsp), %r8
movl $.L.str.13, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB2_16
# %bb.12: # %.lr.ph81.preheader
leaq 4(%rsp), %r14
leaq 8(%rsp), %r15
leaq 12(%rsp), %rbx
.p2align 4, 0x90
.LBB2_13: # %.lr.ph81
# =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
movslq 4(%rsp), %rcx
leaq -1(%rcx), %rax
movl %eax, 4(%rsp)
movl 8(%rsp), %eax
decl %eax
movl %eax, 8(%rsp)
movq 16(%rsp), %rdx # 8-byte Reload
movslq -4(%rdx,%rcx,4), %rcx
shlq $2, %rcx
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
cmpl $-1, (%rbp,%rcx)
leaq 4(%rcx), %rcx
jne .LBB2_14
# %bb.15: # in Loop: Header=BB2_13 Depth=1
movl %eax, -4(%rbp,%rcx)
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 32(%rsp), %rax # 8-byte Reload
movss %xmm0, -4(%rax,%rcx)
movl $.L.str.13, %esi
movq %r12, %rdi
movq %r14, %rdx
movq %r15, %rcx
movq %rbx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB2_13
.LBB2_16: # %._crit_edge82
movq %r12, %rdi
callq fclose
movq 48(%rsp), %rax # 8-byte Reload
movq 16(%rsp), %rcx # 8-byte Reload
movq %rcx, (%rax)
movq 56(%rsp), %rax # 8-byte Reload
movq %rbp, (%rax)
movq 32(%rsp), %rax # 8-byte Reload
movq %rax, (%r13)
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 128
movq stdout(%rip), %rcx
movl $.L.str.11, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size _Z11read_matrixPPiS0_PPfPKcS_S_S_, .Lfunc_end2-_Z11read_matrixPPiS0_PPfPKcS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8spmv_csrPKiS0_PKfiS2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8spmv_csrPKiS0_PKfiS2_Pf,@object # @_Z8spmv_csrPKiS0_PKfiS2_Pf
.section .rodata,"a",@progbits
.globl _Z8spmv_csrPKiS0_PKfiS2_Pf
.p2align 3, 0x0
_Z8spmv_csrPKiS0_PKfiS2_Pf:
.quad _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.size _Z8spmv_csrPKiS0_PKfiS2_Pf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n"
.size .L.str, 114
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Values Array:\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%.6f "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n\nColumn Indices Array:\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d "
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n\nRow Pointer Array:\n"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n\nInitial Vector:\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%.1f "
.size .L.str.7, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\n\nResulting Vector:\n"
.size .L.str.8, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "r"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "File cannot be opened!\n"
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d %d %d\n"
.size .L.str.12, 10
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%d %d %f\n"
.size .L.str.13, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8spmv_csrPKiS0_PKfiS2_Pf"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8spmv_csrPKiS0_PKfiS2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8spmv_csrPKiS0_PKfiS2_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R14, SR_CTAID.X ; /* 0x00000000000e7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R14, R14, c[0x0][0x0], R3 ; /* 0x000000000e0e7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ UMOV UR4, 0x8 ; /* 0x0000000800047882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0090*/ UIADD3 UR6, UP0, UR4, UR6, URZ ; /* 0x0000000604067290 */
/* 0x000fe4000ff1e03f */
/*00a0*/ UIADD3 UR4, UP1, UR4, UR8, URZ ; /* 0x0000000804047290 */
/* 0x000fe4000ff3e03f */
/*00b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc400087fe43f */
/*00c0*/ UIADD3.X UR5, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f057290 */
/* 0x000fc60008ffe43f */
/*00d0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*00e0*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fd400000001ff */
/*00f0*/ IMAD.WIDE R2, R14, R15, c[0x0][0x160] ; /* 0x000058000e027625 */
/* 0x000fca00078e020f */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000000802007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040802107981 */
/* 0x000ea2000c1e1900 */
/*0120*/ BSSY B0, 0xea0 ; /* 0x00000d7000007945 */
/* 0x000fe20003800000 */
/*0130*/ SHF.R.S32.HI R17, RZ, 0x1f, R14 ; /* 0x0000001fff117819 */
/* 0x000fe4000001140e */
/*0140*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0150*/ ISETP.GT.AND P0, PT, R16, R0, PT ; /* 0x000000001000720c */
/* 0x004fda0003f04270 */
/*0160*/ @!P0 BRA 0xe90 ; /* 0x00000d2000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R2, -R0, R16, RZ ; /* 0x0000001000027210 */
/* 0x000fe20007ffe1ff */
/*0180*/ BSSY B1, 0x380 ; /* 0x000001f000017945 */
/* 0x000fe20003800000 */
/*0190*/ LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff037212 */
/* 0x000fe400078e33ff */
/*01a0*/ LOP3.LUT P0, R10, R2, 0x3, RZ, 0xc0, !PT ; /* 0x00000003020a7812 */
/* 0x000fe4000780c0ff */
/*01b0*/ IADD3 R3, R16, R3, RZ ; /* 0x0000000310037210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fc40003f26070 */
/*01e0*/ MOV R19, R0 ; /* 0x0000000000137202 */
/* 0x000fca0000000f00 */
/*01f0*/ @!P0 BRA 0x370 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.WIDE R4, R0, R15, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e020f */
/*0210*/ LDG.E R6, [R4.64] ; /* 0x0000000804067981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IMAD.WIDE R2, R0, R15, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e020f */
/*0230*/ LDG.E R9, [R2.64] ; /* 0x0000000802097981 */
/* 0x000ee2000c1e1900 */
/*0240*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f05270 */
/*0250*/ IMAD.WIDE R6, R6, R15, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x004fcc00078e020f */
/*0260*/ LDG.E R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ee2000c1e1900 */
/*0270*/ IADD3 R19, R0, 0x1, RZ ; /* 0x0000000100137810 */
/* 0x000fe20007ffe0ff */
/*0280*/ FFMA R8, R6, R9, RZ ; /* 0x0000000906087223 */
/* 0x008fc800000000ff */
/*0290*/ @!P0 BRA 0x370 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.NE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe20003f05270 */
/*02b0*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040804067981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040802097981 */
/* 0x000ef0000c1e1900 */
/*02d0*/ @P0 LDG.E R10, [R4.64+0x8] ; /* 0x00000808040a0981 */
/* 0x000f28000c1e1900 */
/*02e0*/ @P0 LDG.E R12, [R2.64+0x8] ; /* 0x00000808020c0981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IMAD.WIDE R6, R6, R15, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x004fcc00078e020f */
/*0300*/ LDG.E R7, [R6.64] ; /* 0x0000000806077981 */
/* 0x000ee2000c1e1900 */
/*0310*/ @P0 IMAD.WIDE R10, R10, R15, c[0x0][0x180] ; /* 0x000060000a0a0625 */
/* 0x010fcc00078e020f */
/*0320*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000080a0b0981 */
/* 0x000f62000c1e1900 */
/*0330*/ IADD3 R19, R0.reuse, 0x2, RZ ; /* 0x0000000200137810 */
/* 0x040fe40007ffe0ff */
/*0340*/ @P0 IADD3 R19, R0, 0x3, RZ ; /* 0x0000000300130810 */
/* 0x000fe20007ffe0ff */
/*0350*/ FFMA R8, R7, R9, R8 ; /* 0x0000000907087223 */
/* 0x008fc80000000008 */
/*0360*/ @P0 FFMA R8, R11, R12, R8 ; /* 0x0000000c0b080223 */
/* 0x020fe40000000008 */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ @!P1 BRA 0xe90 ; /* 0x00000b0000009947 */
/* 0x000fea0003800000 */
/*0390*/ IADD3 R0, R16, -R19, RZ ; /* 0x8000001310007210 */
/* 0x000fe20007ffe0ff */
/*03a0*/ BSSY B1, 0x9f0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*03b0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe40008000f00 */
/*03c0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24270 */
/*03d0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe40008000f00 */
/*03e0*/ MOV R6, UR4 ; /* 0x0000000400067c02 */
/* 0x000fe40008000f00 */
/*03f0*/ MOV R7, UR5 ; /* 0x0000000500077c02 */
/* 0x000fe20008000f00 */
/*0400*/ IMAD.WIDE R4, R19, 0x4, R4 ; /* 0x0000000413047825 */
/* 0x000fe200078e0204 */
/*0410*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*0420*/ IMAD.WIDE R6, R19, 0x4, R6 ; /* 0x0000000413067825 */
/* 0x000fe400078e0206 */
/*0430*/ @!P1 BRA 0x9e0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0440*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0450*/ IADD3 R18, R16, -0xc, RZ ; /* 0xfffffff410127810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LDG.E R24, [R6.64+-0x8] ; /* 0xfffff80806187981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R10, [R6.64+-0x4] ; /* 0xfffffc08060a7981 */
/* 0x000ee8000c1e1900 */
/*0480*/ LDG.E R20, [R6.64] ; /* 0x0000000806147981 */
/* 0x000f28000c1e1900 */
/*0490*/ LDG.E R22, [R6.64+0x4] ; /* 0x0000040806167981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R26, [R6.64+0x8] ; /* 0x00000808061a7981 */
/* 0x000f68000c1e1900 */
/*04b0*/ LDG.E R3, [R4.64+-0x8] ; /* 0xfffff80804037981 */
/* 0x000f68000c1e1900 */
/*04c0*/ LDG.E R12, [R4.64+-0x4] ; /* 0xfffffc08040c7981 */
/* 0x000f68000c1e1900 */
/*04d0*/ LDG.E R13, [R6.64+0xc] ; /* 0x00000c08060d7981 */
/* 0x000f68000c1e1900 */
/*04e0*/ LDG.E R28, [R6.64+0x10] ; /* 0x00001008061c7981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R29, [R4.64] ; /* 0x00000008041d7981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R2, [R4.64+0x4] ; /* 0x0000040804027981 */
/* 0x000f62000c1e1900 */
/*0510*/ IMAD.WIDE R24, R24, R15, c[0x0][0x180] ; /* 0x0000600018187625 */
/* 0x004fc800078e020f */
/*0520*/ IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x088fe200078e020f */
/*0530*/ LDG.E R0, [R24.64] ; /* 0x0000000818007981 */
/* 0x0000a6000c1e1900 */
/*0540*/ IMAD.WIDE R20, R20, R15.reuse, c[0x0][0x180] ; /* 0x0000600014147625 */
/* 0x090fe200078e020f */
/*0550*/ LDG.E R9, [R10.64] ; /* 0x000000080a097981 */
/* 0x0002ea000c1e1900 */
/*0560*/ LDG.E R21, [R20.64] ; /* 0x0000000814157981 */
/* 0x0008e2000c1e1900 */
/*0570*/ IMAD.WIDE R22, R22, R15, c[0x0][0x180] ; /* 0x0000600016167625 */
/* 0x020fc600078e020f */
/*0580*/ LDG.E R24, [R6.64+0x18] ; /* 0x0000180806187981 */
/* 0x001f62000c1e1900 */
/*0590*/ IMAD.WIDE R26, R26, R15, c[0x0][0x180] ; /* 0x000060001a1a7625 */
/* 0x000fc600078e020f */
/*05a0*/ LDG.E R25, [R22.64] ; /* 0x0000000816197981 */
/* 0x000168000c1e1900 */
/*05b0*/ LDG.E R20, [R6.64+0x14] ; /* 0x0000140806147981 */
/* 0x010f28000c1e1900 */
/*05c0*/ LDG.E R10, [R26.64] ; /* 0x000000081a0a7981 */
/* 0x002328000c1e1900 */
/*05d0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000808040b7981 */
/* 0x000f68000c1e1900 */
/*05e0*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0804177981 */
/* 0x001f68000c1e1900 */
/*05f0*/ LDG.E R22, [R6.64+0x20] ; /* 0x0000200806167981 */
/* 0x000f68000c1e1900 */
/*0600*/ LDG.E R26, [R6.64+0x30] ; /* 0x00003008061a7981 */
/* 0x002f62000c1e1900 */
/*0610*/ FFMA R0, R0, R3, R8 ; /* 0x0000000300007223 */
/* 0x004fc60000000008 */
/*0620*/ LDG.E R3, [R4.64+0x14] ; /* 0x0000140804037981 */
/* 0x000ea2000c1e1900 */
/*0630*/ FFMA R0, R9, R12, R0 ; /* 0x0000000c09007223 */
/* 0x008fe40000000000 */
/*0640*/ IMAD.WIDE R12, R13, R15, c[0x0][0x180] ; /* 0x000060000d0c7625 */
/* 0x000fc800078e020f */
/*0650*/ IMAD.WIDE R8, R28, R15, c[0x0][0x180] ; /* 0x000060001c087625 */
/* 0x000fe400078e020f */
/*0660*/ LDG.E R28, [R4.64+0x18] ; /* 0x00001808041c7981 */
/* 0x000ee4000c1e1900 */
/*0670*/ FFMA R0, R21, R29, R0 ; /* 0x0000001d15007223 */
/* 0x000fe40000000000 */
/*0680*/ LDG.E R21, [R12.64] ; /* 0x000000080c157981 */
/* 0x0008a8000c1e1900 */
/*0690*/ LDG.E R29, [R6.64+0x1c] ; /* 0x00001c08061d7981 */
/* 0x000ee8000c1e1900 */
/*06a0*/ LDG.E R9, [R8.64] ; /* 0x0000000808097981 */
/* 0x0000e2000c1e1900 */
/*06b0*/ IMAD.WIDE R12, R20, R15, c[0x0][0x180] ; /* 0x00006000140c7625 */
/* 0x010fc600078e020f */
/*06c0*/ LDG.E R20, [R4.64+0x10] ; /* 0x0000100804147981 */
/* 0x000f22000c1e1900 */
/*06d0*/ FFMA R0, R25, R2, R0 ; /* 0x0000000219007223 */
/* 0x020fc60000000000 */
/*06e0*/ LDG.E R27, [R12.64] ; /* 0x000000080c1b7981 */
/* 0x000362000c1e1900 */
/*06f0*/ IMAD.WIDE R24, R24, R15, c[0x0][0x180] ; /* 0x0000600018187625 */
/* 0x000fc600078e020f */
/*0700*/ LDG.E R2, [R6.64+0x24] ; /* 0x0000240806027981 */
/* 0x000f68000c1e1900 */
/*0710*/ LDG.E R8, [R6.64+0x28] ; /* 0x0000280806087981 */
/* 0x001f62000c1e1900 */
/*0720*/ FFMA R12, R10, R11, R0 ; /* 0x0000000b0a0c7223 */
/* 0x002fc60000000000 */
/*0730*/ LDG.E R11, [R24.64] ; /* 0x00000008180b7981 */
/* 0x000168000c1e1900 */
/*0740*/ LDG.E R10, [R6.64+0x2c] ; /* 0x00002c08060a7981 */
/* 0x000f68000c1e1900 */
/*0750*/ LDG.E R0, [R6.64+0x34] ; /* 0x0000340806007981 */
/* 0x000f68000c1e1900 */
/*0760*/ LDG.E R24, [R4.64+0x20] ; /* 0x0000200804187981 */
/* 0x001168000c1e1900 */
/*0770*/ LDG.E R25, [R4.64+0x24] ; /* 0x0000240804197981 */
/* 0x000162000c1e1900 */
/*0780*/ FFMA R21, R21, R23, R12 ; /* 0x0000001715157223 */
/* 0x004fc6000000000c */
/*0790*/ LDG.E R23, [R4.64+0x1c] ; /* 0x00001c0804177981 */
/* 0x0000a2000c1e1900 */
/*07a0*/ IMAD.WIDE R12, R29, R15, c[0x0][0x180] ; /* 0x000060001d0c7625 */
/* 0x008fc600078e020f */
/*07b0*/ LDG.E R29, [R4.64+0x28] ; /* 0x00002808041d7981 */
/* 0x0000e2000c1e1900 */
/*07c0*/ FFMA R9, R9, R20, R21 ; /* 0x0000001409097223 */
/* 0x010fe40000000015 */
/*07d0*/ IMAD.WIDE R20, R22, R15, c[0x0][0x180] ; /* 0x0000600016147625 */
/* 0x000fe400078e020f */
/*07e0*/ LDG.E R22, [R12.64] ; /* 0x000000080c167981 */
/* 0x0002a4000c1e1900 */
/*07f0*/ FFMA R27, R27, R3, R9 ; /* 0x000000031b1b7223 */
/* 0x020fe40000000009 */
/*0800*/ IMAD.WIDE R2, R2, R15.reuse, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x080fe200078e020f */
/*0810*/ LDG.E R21, [R20.64] ; /* 0x0000000814157981 */
/* 0x000966000c1e1900 */
/*0820*/ IMAD.WIDE R8, R8, R15, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x000fc400078e020f */
/*0830*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x0000e4000c1e1900 */
/*0840*/ FFMA R28, R11, R28, R27 ; /* 0x0000001c0b1c7223 */
/* 0x000fe4000000001b */
/*0850*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x0000e2000c1e1900 */
/*0860*/ IMAD.WIDE R10, R10, R15, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x000fc600078e020f */
/*0870*/ LDG.E R20, [R4.64+0x2c] ; /* 0x00002c0804147981 */
/* 0x0108e2000c1e1900 */
/*0880*/ IMAD.WIDE R12, R26, R15, c[0x0][0x180] ; /* 0x000060001a0c7625 */
/* 0x002fc600078e020f */
/*0890*/ LDG.E R11, [R10.64] ; /* 0x000000080a0b7981 */
/* 0x000ee2000c1e1900 */
/*08a0*/ IMAD.WIDE R26, R0, R15, c[0x0][0x180] ; /* 0x00006000001a7625 */
/* 0x000fc600078e020f */
/*08b0*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000ee8000c1e1900 */
/*08c0*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300804007981 */
/* 0x0008e8000c1e1900 */
/*08d0*/ LDG.E R26, [R26.64] ; /* 0x000000081a1a7981 */
/* 0x000ee8000c1e1900 */
/*08e0*/ LDG.E R3, [R4.64+0x34] ; /* 0x0000340804037981 */
/* 0x0018e2000c1e1900 */
/*08f0*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fc80007ffe0ff */
/*0900*/ ISETP.GE.AND P1, PT, R19, R18, PT ; /* 0x000000121300720c */
/* 0x000fe40003f26270 */
/*0910*/ IADD3 R6, P3, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x000fe40007f7e0ff */
/*0920*/ IADD3 R9, P2, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe40007f5e0ff */
/*0930*/ IADD3.X R7, RZ, R7, RZ, P3, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40001ffe4ff */
/*0940*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x010fe400017fe4ff */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0960*/ FFMA R22, R22, R23, R28 ; /* 0x0000001716167223 */
/* 0x004fc8000000001c */
/*0970*/ FFMA R21, R21, R24, R22 ; /* 0x0000001815157223 */
/* 0x020fc80000000016 */
/*0980*/ FFMA R2, R2, R25, R21 ; /* 0x0000001902027223 */
/* 0x008fc80000000015 */
/*0990*/ FFMA R2, R8, R29, R2 ; /* 0x0000001d08027223 */
/* 0x000fc80000000002 */
/*09a0*/ FFMA R2, R11, R20, R2 ; /* 0x000000140b027223 */
/* 0x000fc80000000002 */
/*09b0*/ FFMA R0, R13, R0, R2 ; /* 0x000000000d007223 */
/* 0x000fc80000000002 */
/*09c0*/ FFMA R8, R26, R3, R0 ; /* 0x000000031a087223 */
/* 0x000fe20000000000 */
/*09d0*/ @!P1 BRA 0x460 ; /* 0xfffffa8000009947 */
/* 0x000fea000383ffff */
/*09e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09f0*/ IADD3 R0, R16, -R19, RZ ; /* 0x8000001310007210 */
/* 0x000fe20007ffe0ff */
/*0a00*/ BSSY B1, 0xd30 ; /* 0x0000032000017945 */
/* 0x000fe60003800000 */
/*0a10*/ ISETP.GT.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f24270 */
/*0a20*/ @!P1 BRA 0xd20 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0a30*/ LDG.E R22, [R6.64+-0x8] ; /* 0xfffff80806167981 */
/* 0x000ea8000c1e1900 */
/*0a40*/ LDG.E R28, [R6.64+-0x4] ; /* 0xfffffc08061c7981 */
/* 0x000ee8000c1e1900 */
/*0a50*/ LDG.E R2, [R6.64] ; /* 0x0000000806027981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R3, [R6.64+0x4] ; /* 0x0000040806037981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R10, [R6.64+0x8] ; /* 0x00000808060a7981 */
/* 0x000f68000c1e1900 */
/*0a80*/ LDG.E R12, [R6.64+0xc] ; /* 0x00000c08060c7981 */
/* 0x000f68000c1e1900 */
/*0a90*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100806147981 */
/* 0x000f68000c1e1900 */
/*0aa0*/ LDG.E R24, [R6.64+0x14] ; /* 0x0000140806187981 */
/* 0x000f68000c1e1900 */
/*0ab0*/ LDG.E R0, [R4.64+-0x8] ; /* 0xfffff80804007981 */
/* 0x000f68000c1e1900 */
/*0ac0*/ LDG.E R18, [R4.64+-0x4] ; /* 0xfffffc0804127981 */
/* 0x000f68000c1e1900 */
/*0ad0*/ LDG.E R27, [R4.64] ; /* 0x00000008041b7981 */
/* 0x000f62000c1e1900 */
/*0ae0*/ IMAD.WIDE R22, R22, R15, c[0x0][0x180] ; /* 0x0000600016167625 */
/* 0x004fc800078e020f */
/*0af0*/ IMAD.WIDE R28, R28, R15.reuse, c[0x0][0x180] ; /* 0x000060001c1c7625 */
/* 0x088fe200078e020f */
/*0b00*/ LDG.E R9, [R22.64] ; /* 0x0000000816097981 */
/* 0x0008a8000c1e1900 */
/*0b10*/ LDG.E R25, [R28.64] ; /* 0x000000081c197981 */
/* 0x0000e2000c1e1900 */
/*0b20*/ IMAD.WIDE R22, R2, R15, c[0x0][0x180] ; /* 0x0000600002167625 */
/* 0x010fc800078e020f */
/*0b30*/ IMAD.WIDE R2, R3, R15.reuse, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x0a0fe200078e020f */
/*0b40*/ LDG.E R26, [R22.64] ; /* 0x00000008161a7981 */
/* 0x000326000c1e1900 */
/*0b50*/ IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x080fe200078e020f */
/*0b60*/ LDG.E R29, [R4.64+0xc] ; /* 0x00000c08041d7981 */
/* 0x001f68000c1e1900 */
/*0b70*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000162000c1e1900 */
/*0b80*/ IMAD.WIDE R12, R12, R15, c[0x0][0x180] ; /* 0x000060000c0c7625 */
/* 0x000fc600078e020f */
/*0b90*/ LDG.E R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000362000c1e1900 */
/*0ba0*/ IMAD.WIDE R20, R20, R15, c[0x0][0x180] ; /* 0x0000600014147625 */
/* 0x000fc600078e020f */
/*0bb0*/ LDG.E R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000f68000c1e1900 */
/*0bc0*/ LDG.E R3, [R4.64+0x4] ; /* 0x0000040804037981 */
/* 0x001f68000c1e1900 */
/*0bd0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000808040b7981 */
/* 0x002f62000c1e1900 */
/*0be0*/ IMAD.WIDE R22, R24, R15, c[0x0][0x180] ; /* 0x0000600018167625 */
/* 0x000fc600078e020f */
/*0bf0*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000f68000c1e1900 */
/*0c00*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100804187981 */
/* 0x000f68000c1e1900 */
/*0c10*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000f68000c1e1900 */
/*0c20*/ LDG.E R28, [R4.64+0x14] ; /* 0x00001408041c7981 */
/* 0x000162000c1e1900 */
/*0c30*/ IADD3 R6, P2, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fc40007f5e0ff */
/*0c40*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0c50*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400017fe4ff */
/*0c60*/ IADD3 R19, R19, 0x8, RZ ; /* 0x0000000813137810 */
/* 0x000fe20007ffe0ff */
/*0c70*/ FFMA R0, R9, R0, R8 ; /* 0x0000000009007223 */
/* 0x004fc80000000008 */
/*0c80*/ FFMA R0, R25, R18, R0 ; /* 0x0000001219007223 */
/* 0x008fc80000000000 */
/*0c90*/ FFMA R0, R26, R27, R0 ; /* 0x0000001b1a007223 */
/* 0x010fc80000000000 */
/*0ca0*/ FFMA R0, R2, R3, R0 ; /* 0x0000000302007223 */
/* 0x020fc80000000000 */
/*0cb0*/ FFMA R0, R10, R11, R0 ; /* 0x0000000b0a007223 */
/* 0x000fc80000000000 */
/*0cc0*/ FFMA R29, R12, R29, R0 ; /* 0x0000001d0c1d7223 */
/* 0x000fe20000000000 */
/*0cd0*/ IADD3 R0, P1, R4, 0x20, RZ ; /* 0x0000002004007810 */
/* 0x000fc60007f3e0ff */
/*0ce0*/ FFMA R29, R20, R24, R29 ; /* 0x00000018141d7223 */
/* 0x000fe2000000001d */
/*0cf0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x001fe40000ffe4ff */
/*0d00*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*0d10*/ FFMA R8, R22, R28, R29 ; /* 0x0000001c16087223 */
/* 0x000fe4000000001d */
/*0d20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d30*/ ISETP.LT.OR P0, PT, R19, R16, P0 ; /* 0x000000101300720c */
/* 0x000fda0000701670 */
/*0d40*/ @!P0 BRA 0xe90 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0d50*/ LDG.E R2, [R6.64+-0x8] ; /* 0xfffff80806027981 */
/* 0x0000a8000c1e1900 */
/*0d60*/ LDG.E R10, [R6.64+-0x4] ; /* 0xfffffc08060a7981 */
/* 0x0000e8000c1e1900 */
/*0d70*/ LDG.E R12, [R6.64] ; /* 0x00000008060c7981 */
/* 0x000128000c1e1900 */
/*0d80*/ LDG.E R18, [R6.64+0x4] ; /* 0x0000040806127981 */
/* 0x000168000c1e1900 */
/*0d90*/ LDG.E R0, [R4.64+-0x8] ; /* 0xfffff80804007981 */
/* 0x000f68000c1e1900 */
/*0da0*/ LDG.E R9, [R4.64+-0x4] ; /* 0xfffffc0804097981 */
/* 0x000f68000c1e1900 */
/*0db0*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040804067981 */
/* 0x001f62000c1e1900 */
/*0dc0*/ IMAD.WIDE R2, R2, R15, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x004fc800078e020f */
/*0dd0*/ IMAD.WIDE R10, R10, R15.reuse, c[0x0][0x180] ; /* 0x000060000a0a7625 */
/* 0x088fe400078e020f */
/*0de0*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea4000c1e1900 */
/*0df0*/ IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x180] ; /* 0x000060000c0c7625 */
/* 0x090fe400078e020f */
/*0e00*/ LDG.E R11, [R10.64] ; /* 0x000000080a0b7981 */
/* 0x000ee4000c1e1900 */
/*0e10*/ IMAD.WIDE R18, R18, R15, c[0x0][0x180] ; /* 0x0000600012127625 */
/* 0x020fe400078e020f */
/*0e20*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000f28000c1e1900 */
/*0e30*/ LDG.E R15, [R4.64] ; /* 0x00000008040f7981 */
/* 0x000f28000c1e1900 */
/*0e40*/ LDG.E R19, [R18.64] ; /* 0x0000000812137981 */
/* 0x000f62000c1e1900 */
/*0e50*/ FFMA R0, R3, R0, R8 ; /* 0x0000000003007223 */
/* 0x004fc80000000008 */
/*0e60*/ FFMA R0, R11, R9, R0 ; /* 0x000000090b007223 */
/* 0x008fc80000000000 */
/*0e70*/ FFMA R0, R13, R15, R0 ; /* 0x0000000f0d007223 */
/* 0x010fc80000000000 */
/*0e80*/ FFMA R8, R19, R6, R0 ; /* 0x0000000613087223 */
/* 0x020fe40000000000 */
/*0e90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ea0*/ LEA R2, P0, R14.reuse, c[0x0][0x188], 0x2 ; /* 0x000062000e027a11 */
/* 0x040fe400078010ff */
/*0eb0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe40000000f00 */
/*0ec0*/ LEA.HI.X R3, R14, c[0x0][0x18c], R17, 0x2, P0 ; /* 0x000063000e037a11 */
/* 0x000fc600000f1411 */
/*0ed0*/ IMAD R14, R5, c[0x0][0xc], R14 ; /* 0x00000300050e7a24 */
/* 0x000fe400078e020e */
/*0ee0*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0001e6000c101908 */
/*0ef0*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fda0003f06270 */
/*0f00*/ @P0 CALL.REL.NOINC 0xf20 ; /* 0x0000001000000944 */
/* 0x001fe20003c00000 */
/*0f10*/ BRA 0xe0 ; /* 0xfffff1c000007947 */
/* 0x000fea000383ffff */
/*0f20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f30*/ BRA 0xf30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8spmv_csrPKiS0_PKfiS2_Pf
.globl _Z8spmv_csrPKiS0_PKfiS2_Pf
.p2align 8
.type _Z8spmv_csrPKiS0_PKfiS2_Pf,@function
_Z8spmv_csrPKiS0_PKfiS2_Pf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_7
s_load_b32 s14, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s14, s13
s_mov_b32 s13, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v2, s0, s10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
v_cmp_le_i32_e32 vcc_lo, s12, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v4, v5
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v7, 31, v4
v_mov_b32_e32 v6, v4
v_mov_b32_e32 v0, 0
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
.p2align 6
.LBB0_5:
global_load_b32 v10, v[8:9], off
v_add_nc_u32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v4, v5
s_or_b32 s15, s0, s15
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s8, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_load_b32 v12, v[6:7], off
global_load_b32 v10, v[10:11], off
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v12, v10
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s15
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8spmv_csrPKiS0_PKfiS2_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8spmv_csrPKiS0_PKfiS2_Pf, .Lfunc_end0-_Z8spmv_csrPKiS0_PKfiS2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8spmv_csrPKiS0_PKfiS2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8spmv_csrPKiS0_PKfiS2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008cc3b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "File cannot be opened!\n"
.LC2:
.string "%d %d %d\n"
.LC3:
.string "%d %d %f\n"
.text
.globl _Z11read_matrixPPiS0_PPfPKcS_S_S_
.type _Z11read_matrixPPiS0_PPfPKcS_S_S_, @function
_Z11read_matrixPPiS0_PPfPKcS_S_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, %rdi
movq %r8, 8(%rsp)
movq %r9, 16(%rsp)
movq 144(%rsp), %r15
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L23
movq %rax, %rbp
movq %r15, %r8
movq 16(%rsp), %rcx
movq 8(%rsp), %r14
movq %r14, %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl (%r14), %eax
movl %eax, 8(%rsp)
leal 1(%rax), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movslq (%r15), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbx
movslq (%r15), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
movq %r14, 8(%rsp)
movslq (%r14), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
movq 8(%rsp), %rax
movl (%rax), %edx
testl %edx, %edx
jle .L7
movq %r14, %rax
movslq %edx, %rdx
leaq (%r14,%rdx,4), %rdx
.L6:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L6
jmp .L7
.L23:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L8:
movl 60(%rsp), %eax
subl $1, %eax
movl %eax, 60(%rsp)
subl $1, 64(%rsp)
cltq
addl $1, (%r14,%rax,4)
.L7:
leaq 64(%rsp), %rcx
leaq 60(%rsp), %rdx
leaq 68(%rsp), %r8
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
jne .L8
movq 8(%rsp), %rax
movl (%rax), %esi
testl %esi, %esi
jle .L9
movslq %esi, %rcx
salq $2, %rcx
movl $0, %eax
movl $0, %edx
.L10:
movl %edx, (%r12,%rax)
addl (%r14,%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L10
.L9:
movslq %esi, %rsi
movl (%r15), %eax
movl %eax, (%r12,%rsi,4)
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call rewind@PLT
movl (%r15), %edx
testl %edx, %edx
jle .L11
movq %rbx, %rax
movslq %edx, %rdx
leaq (%rbx,%rdx,4), %rdx
.L12:
movl $-1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
.L11:
movq %r15, %r8
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq .LC3(%rip), %r14
jmp .L13
.L14:
movl %ecx, (%rax)
movss 68(%rsp), %xmm0
movss %xmm0, 0(%r13,%rdx)
.L13:
leaq 64(%rsp), %rcx
leaq 60(%rsp), %rdx
leaq 68(%rsp), %r8
movq %r14, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L24
movl 60(%rsp), %eax
subl $1, %eax
movl %eax, 60(%rsp)
movl 64(%rsp), %esi
leal -1(%rsi), %ecx
movl %ecx, 64(%rsp)
cltq
movslq (%r12,%rax,4), %rdx
salq $2, %rdx
leaq (%rbx,%rdx), %rax
cmpl $-1, (%rax)
je .L14
leaq 4(%rdx), %rax
.L15:
movq %rax, %rdx
addq $4, %rax
cmpl $-1, -4(%rbx,%rax)
jne .L15
leaq (%rbx,%rdx), %rax
jmp .L14
.L24:
movq %rbp, %rdi
call fclose@PLT
movq 24(%rsp), %rax
movq %r12, (%rax)
movq 32(%rsp), %rax
movq %rbx, (%rax)
movq 40(%rsp), %rax
movq %r13, (%rax)
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11read_matrixPPiS0_PPfPKcS_S_S_, .-_Z11read_matrixPPiS0_PPfPKcS_S_S_
.globl _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
.type _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf, @function
_Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8spmv_csrPKiS0_PKfiS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf, .-_Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
.globl _Z8spmv_csrPKiS0_PKfiS2_Pf
.type _Z8spmv_csrPKiS0_PKfiS2_Pf, @function
_Z8spmv_csrPKiS0_PKfiS2_Pf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8spmv_csrPKiS0_PKfiS2_Pf, .-_Z8spmv_csrPKiS0_PKfiS2_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n"
.section .rodata.str1.1
.LC7:
.string "Values Array:\n"
.LC8:
.string "%.6f "
.LC9:
.string "\n\nColumn Indices Array:\n"
.LC10:
.string "%d "
.LC11:
.string "\n\nRow Pointer Array:\n"
.LC12:
.string "\n\nInitial Vector:\n"
.LC13:
.string "%.1f "
.LC14:
.string "\n\nResulting Vector:\n"
.LC15:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
cmpl $5, %edi
je .L35
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L35:
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movl %eax, %r14d
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, (%rsp)
movq 32(%rbx), %rcx
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 232
leaq 48(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 240
leaq 52(%rsp), %r9
leaq 48(%rsp), %r8
call _Z11read_matrixPPiS0_PPfPKcS_S_S_
movl 48(%rsp), %r15d
movslq %r15d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 224
testl %r15d, %r15d
jle .L36
movl $0, %eax
movss .LC5(%rip), %xmm0
.L37:
movss %xmm0, 0(%rbp,%rax)
movl $0x00000000, (%rbx,%rax)
addq $4, %rax
cmpq %rax, %r12
jne .L37
.L36:
cmpl $1, (%rsp)
je .L61
.L38:
movl 32(%rsp), %eax
leal 1(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 40(%rsp), %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movslq 40(%rsp), %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movslq 32(%rsp), %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
movslq 32(%rsp), %rsi
salq $2, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
leaq 44(%rsp), %rdi
movl $0, %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
movq 48(%rsp), %r15
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rsi
movq %rsi, 8(%rsp)
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movq 64(%rsp), %rsi
movq %rsi, 16(%rsp)
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
call cudaEventCreate@PLT
leaq 120(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 112(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $0, 24(%rsp)
jle .L47
movl $0, %r12d
jmp .L51
.L61:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
leaq .LC8(%rip), %r15
jmp .L39
.L40:
movq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%r12,4), %xmm0
movq %r15, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %r12
.L39:
cmpl %r12d, 40(%rsp)
jg .L40
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
leaq .LC10(%rip), %r15
jmp .L41
.L42:
movq 56(%rsp), %rax
movl (%rax,%r12,4), %ecx
movq %r15, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %r12
.L41:
cmpl %r12d, 40(%rsp)
jg .L42
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
leaq .LC10(%rip), %r15
jmp .L43
.L44:
movq 48(%rsp), %rax
movl (%rax,%r12,4), %ecx
movq %r15, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %r12
.L43:
cmpl %r12d, 32(%rsp)
jge .L44
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
leaq .LC13(%rip), %r15
jmp .L45
.L46:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12,4), %xmm0
movq %r15, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %r12
.L45:
cmpl %r12d, 32(%rsp)
jg .L46
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L38
.L48:
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 104(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %edx
testl %edx, %edx
jle .L49
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L50:
movss (%rbx,%rax), %xmm0
movss %xmm0, 0(%rbp,%rax)
movl $0x00000000, (%rbx,%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L50
.L49:
addl $1, %r12d
cmpl %r14d, %r12d
je .L47
.L51:
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl 44(%rsp), %eax
sall $5, %eax
movl %eax, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movl 32(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z40__device_stub__Z8spmv_csrPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
jmp .L48
.L47:
movl $0, %esi
movq 120(%rsp), %rdi
call cudaEventRecord@PLT
movq 120(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 140(%rsp), %rdi
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl (%rsp), %eax
subl $1, %eax
cmpl $1, %eax
jbe .L62
.L52:
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
cmpl $0, 32(%rsp)
jle .L53
movl $0, %ebx
leaq .LC8(%rip), %r12
.L54:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, 32(%rsp)
jg .L54
.L53:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L52
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z8spmv_csrPKiS0_PKfiS2_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8spmv_csrPKiS0_PKfiS2_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf # -- Begin function _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.p2align 4, 0x90
.type _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf,@function
_Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf: # @_Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8spmv_csrPKiS0_PKfiS2_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf, .Lfunc_end0-_Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB1_32
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 104(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 32(%rbx), %rcx
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 20(%rsp), %rax
leaq 104(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 16(%rsp), %r8
leaq 244(%rsp), %r9
pushq %rax
.cfi_adjust_cfa_offset 8
callq _Z11read_matrixPPiS0_PPfPKcS_S_S_
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movslq 8(%rsp), %r13
leaq (,%r13,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r12
testq %r13, %r13
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r13d, %r14d
leaq (,%r14,4), %rdx
xorl %r13d, %r13d
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%r13,4) # imm = 0x3F800000
incq %r13
cmpq %r13, %r14
jne .LBB1_3
.LBB1_4: # %._crit_edge
cmpl $1, %ebp
jne .LBB1_18
# %bb.5:
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $14, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, 12(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph65
movq 80(%rsp), %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_7
.LBB1_8: # %._crit_edge66
movq stdout(%rip), %rcx
movl $.L.str.3, %edi
movl $24, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, 12(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph69
movq 88(%rsp), %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movl (%r14,%r13,4), %edx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_10
.LBB1_11: # %._crit_edge70
movq stdout(%rip), %rcx
movl $.L.str.5, %edi
movl $21, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, 8(%rsp)
js .LBB1_14
# %bb.12: # %.lr.ph74
movq $-1, %r14
movq 96(%rsp), %r13
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movl 4(%r13,%r14,4), %edx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movslq 8(%rsp), %rax
incq %r14
cmpq %rax, %r14
jl .LBB1_13
.LBB1_14: # %._crit_edge75
movq stdout(%rip), %rcx
movl $.L.str.6, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, 8(%rsp)
jle .LBB1_17
# %bb.15: # %.lr.ph78.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_16: # %.lr.ph78
# =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movb $1, %al
callq fprintf
incq %r14
movslq 8(%rsp), %rax
cmpq %rax, %r14
jl .LBB1_16
.LBB1_17: # %._crit_edge79
movq stdout(%rip), %rcx
movl $.L.str.8, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
.LBB1_18:
movq %rbp, 136(%rsp) # 8-byte Spill
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
leaq 64(%rsp), %rdi
xorl %r14d, %r14d
movl $63, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
movq 56(%rsp), %rdi
movq 96(%rsp), %rsi
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rdx
movq %rsi, 128(%rsp) # 8-byte Spill
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 88(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq %rsi, 120(%rsp) # 8-byte Spill
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 80(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq %rsi, 112(%rsp) # 8-byte Spill
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %r15d, %r15d
jle .LBB1_26
# %bb.19: # %.lr.ph86
movabsq $4294967296, %r13 # imm = 0x100000000
movl 104(%rsp), %ebp # 4-byte Reload
orq %r13, %rbp
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_25: # %._crit_edge83
# in Loop: Header=BB1_20 Depth=1
incl %r14d
cmpl %r15d, %r14d
je .LBB1_26
.LBB1_20: # =>This Loop Header: Depth=1
# Child Loop BB1_24 Depth 2
movq 32(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl 64(%rsp), %edi
shll $5, %edi
orq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_22
# %bb.21: # in Loop: Header=BB1_20 Depth=1
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movl 8(%rsp), %esi
movq 32(%rsp), %rdi
movq 16(%rsp), %r8
movq %rax, 224(%rsp)
movq %rcx, 216(%rsp)
movq %rdx, 208(%rsp)
movl %esi, 68(%rsp)
movq %rdi, 200(%rsp)
movq %r8, 192(%rsp)
leaq 224(%rsp), %rax
movq %rax, 240(%rsp)
leaq 216(%rsp), %rax
movq %rax, 248(%rsp)
leaq 208(%rsp), %rax
movq %rax, 256(%rsp)
leaq 68(%rsp), %rax
movq %rax, 264(%rsp)
leaq 200(%rsp), %rax
movq %rax, 272(%rsp)
leaq 192(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z8spmv_csrPKiS0_PKfiS2_Pf, %edi
leaq 240(%rsp), %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_22: # in Loop: Header=BB1_20 Depth=1
movq 16(%rsp), %rsi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_25
# %bb.23: # %.lr.ph82.preheader
# in Loop: Header=BB1_20 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_24: # %.lr.ph82
# Parent Loop BB1_20 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx,%rcx,4)
movl $0, (%r12,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_24
jmp .LBB1_25
.LBB1_26: # %._crit_edge87
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
movq 136(%rsp), %rax # 8-byte Reload
decl %eax
cmpl $1, %eax
ja .LBB1_31
# %bb.27: # %.preheader
cmpl $0, 8(%rsp)
jle .LBB1_30
# %bb.28: # %.lr.ph89.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_29: # %.lr.ph89
# =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
incq %r14
movslq 8(%rsp), %rax
cmpq %rax, %r14
jl .LBB1_29
.LBB1_30: # %._crit_edge90
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
.LBB1_31:
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi # 8-byte Reload
callq free
movq 120(%rsp), %rdi # 8-byte Reload
callq free
movq 112(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_32:
.cfi_def_cfa_offset 352
movq stdout(%rip), %rcx
movl $.L.str, %edi
movl $113, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11read_matrixPPiS0_PPfPKcS_S_S_ # -- Begin function _Z11read_matrixPPiS0_PPfPKcS_S_S_
.p2align 4, 0x90
.type _Z11read_matrixPPiS0_PPfPKcS_S_S_,@function
_Z11read_matrixPPiS0_PPfPKcS_S_S_: # @_Z11read_matrixPPiS0_PPfPKcS_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r13
movq %r8, %rbp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl $.L.str.10, %esi
movq %rcx, %rdi
callq fopen
testq %rax, %rax
je .LBB2_17
# %bb.1:
movq %rax, %r12
movq %r15, 48(%rsp) # 8-byte Spill
movq %r14, 56(%rsp) # 8-byte Spill
movq %rbx, 64(%rsp) # 8-byte Spill
movq 128(%rsp), %rbx
movl $.L.str.12, %esi
movq %rax, %rdi
movq %rbp, %rdx
movq %r13, 40(%rsp) # 8-byte Spill
movq %r13, %rcx
movq %rbx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbp, 24(%rsp) # 8-byte Spill
movslq (%rbp), %r15
leaq 4(,%r15,4), %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movslq (%rbx), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
leaq (,%r15,4), %rdi
callq malloc
movq %rax, %r14
testq %r15, %r15
jle .LBB2_3
# %bb.2: # %.lr.ph.preheader
movl %r15d, %edx
shlq $2, %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_3: # %._crit_edge
leaq 4(%rsp), %rdx
leaq 8(%rsp), %rcx
leaq 12(%rsp), %r8
movl $.L.str.13, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB2_6
# %bb.4:
leaq 4(%rsp), %rbx
leaq 8(%rsp), %r15
leaq 12(%rsp), %r13
.p2align 4, 0x90
.LBB2_5: # %.lr.ph69
# =>This Inner Loop Header: Depth=1
movslq 4(%rsp), %rax
leaq -1(%rax), %rcx
decl 8(%rsp)
movl %ecx, 4(%rsp)
incl -4(%r14,%rax,4)
movl $.L.str.13, %esi
movq %r12, %rdi
movq %rbx, %rdx
movq %r15, %rcx
movq %r13, %r8
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB2_5
.LBB2_6: # %.preheader
movq 24(%rsp), %rax # 8-byte Reload
movl (%rax), %eax
testl %eax, %eax
movq 16(%rsp), %rsi # 8-byte Reload
jle .LBB2_9
# %bb.7: # %.lr.ph72.preheader
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_8: # %.lr.ph72
# =>This Inner Loop Header: Depth=1
movl %edx, (%rsi,%rcx,4)
addl (%r14,%rcx,4), %edx
incq %rcx
cmpq %rcx, %rax
jne .LBB2_8
.LBB2_9: # %._crit_edge73
movq 128(%rsp), %rbx
movl (%rbx), %ecx
cltq
movl %ecx, (%rsi,%rax,4)
movq %r14, %rdi
callq free
movq %r12, %rdi
callq rewind
movl (%rbx), %edx
testl %edx, %edx
movq 64(%rsp), %r13 # 8-byte Reload
jle .LBB2_11
# %bb.10: # %.lr.ph76.preheader
shlq $2, %rdx
movq %rbp, %rdi
movl $255, %esi
callq memset@PLT
.LBB2_11: # %._crit_edge77
movl $.L.str.12, %esi
movq %r12, %rdi
movq 24(%rsp), %rdx # 8-byte Reload
movq 40(%rsp), %rcx # 8-byte Reload
movq %rbx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
leaq 4(%rsp), %rdx
leaq 8(%rsp), %rcx
leaq 12(%rsp), %r8
movl $.L.str.13, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB2_16
# %bb.12: # %.lr.ph81.preheader
leaq 4(%rsp), %r14
leaq 8(%rsp), %r15
leaq 12(%rsp), %rbx
.p2align 4, 0x90
.LBB2_13: # %.lr.ph81
# =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
movslq 4(%rsp), %rcx
leaq -1(%rcx), %rax
movl %eax, 4(%rsp)
movl 8(%rsp), %eax
decl %eax
movl %eax, 8(%rsp)
movq 16(%rsp), %rdx # 8-byte Reload
movslq -4(%rdx,%rcx,4), %rcx
shlq $2, %rcx
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
cmpl $-1, (%rbp,%rcx)
leaq 4(%rcx), %rcx
jne .LBB2_14
# %bb.15: # in Loop: Header=BB2_13 Depth=1
movl %eax, -4(%rbp,%rcx)
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 32(%rsp), %rax # 8-byte Reload
movss %xmm0, -4(%rax,%rcx)
movl $.L.str.13, %esi
movq %r12, %rdi
movq %r14, %rdx
movq %r15, %rcx
movq %rbx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB2_13
.LBB2_16: # %._crit_edge82
movq %r12, %rdi
callq fclose
movq 48(%rsp), %rax # 8-byte Reload
movq 16(%rsp), %rcx # 8-byte Reload
movq %rcx, (%rax)
movq 56(%rsp), %rax # 8-byte Reload
movq %rbp, (%rax)
movq 32(%rsp), %rax # 8-byte Reload
movq %rax, (%r13)
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 128
movq stdout(%rip), %rcx
movl $.L.str.11, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size _Z11read_matrixPPiS0_PPfPKcS_S_S_, .Lfunc_end2-_Z11read_matrixPPiS0_PPfPKcS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8spmv_csrPKiS0_PKfiS2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8spmv_csrPKiS0_PKfiS2_Pf,@object # @_Z8spmv_csrPKiS0_PKfiS2_Pf
.section .rodata,"a",@progbits
.globl _Z8spmv_csrPKiS0_PKfiS2_Pf
.p2align 3, 0x0
_Z8spmv_csrPKiS0_PKfiS2_Pf:
.quad _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.size _Z8spmv_csrPKiS0_PKfiS2_Pf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Invalid command, enter:\n1. number of threads, 2. number of repetitions, 3. print mode (1 or 2), 4. test filename\n"
.size .L.str, 114
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Values Array:\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%.6f "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n\nColumn Indices Array:\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d "
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n\nRow Pointer Array:\n"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n\nInitial Vector:\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%.1f "
.size .L.str.7, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\n\nResulting Vector:\n"
.size .L.str.8, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "r"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "File cannot be opened!\n"
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d %d %d\n"
.size .L.str.12, 10
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%d %d %f\n"
.size .L.str.13, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8spmv_csrPKiS0_PKfiS2_Pf"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__spmv_csrPKiS0_PKfiS2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8spmv_csrPKiS0_PKfiS2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void
exemple(void){
int identifiant_local = threadIdx.x;
int identifiant_global = blockIdx.x * blockDim.x + threadIdx.x;
}
int
main(){
exemple<<<512,512>>>();
return 0;
} | code for sm_80
Function : _Z7exemplev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void
exemple(void){
int identifiant_local = threadIdx.x;
int identifiant_global = blockIdx.x * blockDim.x + threadIdx.x;
}
int
main(){
exemple<<<512,512>>>();
return 0;
} | .file "tmpxft_00008cdd_00000000-6_exemple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7exemplevv
.type _Z25__device_stub__Z7exemplevv, @function
_Z25__device_stub__Z7exemplevv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7exemplev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z25__device_stub__Z7exemplevv, .-_Z25__device_stub__Z7exemplevv
.globl _Z7exemplev
.type _Z7exemplev, @function
_Z7exemplev:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7exemplevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7exemplev, .-_Z7exemplev
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z25__device_stub__Z7exemplevv
jmp .L12
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7exemplev"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7exemplev(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void
exemple(void){
int identifiant_local = threadIdx.x;
int identifiant_global = blockIdx.x * blockDim.x + threadIdx.x;
}
int
main(){
exemple<<<512,512>>>();
return 0;
} | #include <hip/hip_runtime.h>
__global__ void
exemple(void){
int identifiant_local = threadIdx.x;
int identifiant_global = blockIdx.x * blockDim.x + threadIdx.x;
}
int
main(){
exemple<<<512,512>>>();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void
exemple(void){
int identifiant_local = threadIdx.x;
int identifiant_global = blockIdx.x * blockDim.x + threadIdx.x;
}
int
main(){
exemple<<<512,512>>>();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7exemplev
.globl _Z7exemplev
.p2align 8
.type _Z7exemplev,@function
_Z7exemplev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7exemplev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7exemplev, .Lfunc_end0-_Z7exemplev
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7exemplev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7exemplev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
exemple(void){
int identifiant_local = threadIdx.x;
int identifiant_global = blockIdx.x * blockDim.x + threadIdx.x;
}
int
main(){
exemple<<<512,512>>>();
return 0;
} | .text
.file "exemple.hip"
.globl _Z22__device_stub__exemplev # -- Begin function _Z22__device_stub__exemplev
.p2align 4, 0x90
.type _Z22__device_stub__exemplev,@function
_Z22__device_stub__exemplev: # @_Z22__device_stub__exemplev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7exemplev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__exemplev, .Lfunc_end0-_Z22__device_stub__exemplev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967808, %rdi # imm = 0x100000200
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7exemplev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7exemplev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7exemplev,@object # @_Z7exemplev
.section .rodata,"a",@progbits
.globl _Z7exemplev
.p2align 3, 0x0
_Z7exemplev:
.quad _Z22__device_stub__exemplev
.size _Z7exemplev, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7exemplev"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__exemplev
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7exemplev
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7exemplev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7exemplev
.globl _Z7exemplev
.p2align 8
.type _Z7exemplev,@function
_Z7exemplev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7exemplev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7exemplev, .Lfunc_end0-_Z7exemplev
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7exemplev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7exemplev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00008cdd_00000000-6_exemple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7exemplevv
.type _Z25__device_stub__Z7exemplevv, @function
_Z25__device_stub__Z7exemplevv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7exemplev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z25__device_stub__Z7exemplevv, .-_Z25__device_stub__Z7exemplevv
.globl _Z7exemplev
.type _Z7exemplev, @function
_Z7exemplev:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7exemplevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7exemplev, .-_Z7exemplev
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z25__device_stub__Z7exemplevv
jmp .L12
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7exemplev"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7exemplev(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exemple.hip"
.globl _Z22__device_stub__exemplev # -- Begin function _Z22__device_stub__exemplev
.p2align 4, 0x90
.type _Z22__device_stub__exemplev,@function
_Z22__device_stub__exemplev: # @_Z22__device_stub__exemplev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7exemplev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__exemplev, .Lfunc_end0-_Z22__device_stub__exemplev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967808, %rdi # imm = 0x100000200
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7exemplev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7exemplev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7exemplev,@object # @_Z7exemplev
.section .rodata,"a",@progbits
.globl _Z7exemplev
.p2align 3, 0x0
_Z7exemplev:
.quad _Z22__device_stub__exemplev
.size _Z7exemplev, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7exemplev"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__exemplev
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7exemplev
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 1993-2006 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws.
*
* This software and the information contained herein is PROPRIETARY and
* CONFIDENTIAL to NVIDIA and is being provided under the terms and
* conditions of a Non-Disclosure Agreement. Any reproduction or
* disclosure to any third party without the express written consent of
* NVIDIA is prohibited.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*/
#ifdef _WIN32
# define NOMINMAX
#endif
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
// You can use any other block size you wish.
#define BLOCK_SIZE 256
#define DEFAULT_NUM_ELEMENTS 16777216
#define MAX_RAND 2
int LOG_BLOCK_SIZE;
void getLogBlockSize(int block_size) {
for(LOG_BLOCK_SIZE = 1;LOG_BLOCK_SIZE < 31; LOG_BLOCK_SIZE++) {
if((1<<LOG_BLOCK_SIZE) >= block_size)
return;
}
fprintf(stderr, "The size requested might be too large!\n");
exit(-1);
}
__global__ void kernel_reduction(float *inArray, int numElements, int stride, int numRest) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
__shared__ float idata[(BLOCK_SIZE << 1)+256];
int copyIdx = stride * ((idx << 1) + 1) - 1;
int copyToIdx = tid<<1;
copyToIdx += (copyToIdx>>4);
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx+1] = idata[copyToIdx] + inArray[copyIdx + stride];
__syncthreads();
int localStride = 2;
for(numRest>>=1;numRest > 1; numRest >>= 1, localStride <<= 1) {
if((tid<<1) < numRest) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
int idxTwo = idxOne - localStride;
idxOne += (idxOne >> 4);
idxTwo += (idxTwo >> 4);
idata[idxOne] += idata[idxTwo];
}
__syncthreads();
}
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+stride] = idata[copyToIdx+1];
}
__global__ void kernel_downtraverse(float *inArray, int numElements, int startStride, int LOG_BLOCK_SIZE) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
int finalStride = (startStride >> LOG_BLOCK_SIZE);
if(finalStride <= 0)
finalStride = 1;
if((startStride << 1) == numElements) {
__shared__ float idata[(BLOCK_SIZE<<1)+256];
int copyIdx = finalStride * ((idx << 1) + 1) - 1;
int copyToIdx = (tid<<1);
copyToIdx += (copyToIdx>>4);
if(copyIdx < numElements){
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx + 1] = inArray[copyIdx+finalStride];
}
__syncthreads();
int localStride = blockDim.x;
while(localStride >= 1) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
if(idxOne < (blockDim.x<<1)) {
int idxTwo = idxOne - localStride;
idxOne += (idxOne>>4);
idxTwo += (idxTwo>>4);
float tmp = idata[idxOne] + idata[idxTwo];
idata[idxTwo] = idata[idxOne];
idata[idxOne] = tmp;
}
localStride >>= 1;
__syncthreads();
}
if(copyIdx < numElements) {
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+finalStride] = idata[copyToIdx+1];
}
}
else {
int stride = startStride;
int idxOne = (stride << 1) * (idx + 1) - 1;
if(idxOne < numElements) {
int idxTwo = idxOne - stride;
float tmp = inArray[idxOne] + inArray[idxTwo];
inArray[idxTwo] = inArray[idxOne];
inArray[idxOne] = tmp;
}
}
}
// **===-------- Modify the body of this function -----------===**
// You may need to make multiple kernel calls.
void prescanArray(float *inArray, int numElements)
{
unsigned numRests = numElements;
int stride = 1;
while(numRests > 1) {
unsigned threads = numRests / 2;
unsigned gridX = 1, gridY = 1;
if(threads > BLOCK_SIZE) {
gridX = threads / BLOCK_SIZE;
threads = BLOCK_SIZE;
if(gridX > 32768) {
gridY = gridX / 32768;
gridX = 32768;
}
}
dim3 grids(gridX, gridY);
kernel_reduction<<<grids,threads>>>(inArray, numElements, stride, numRests > (2*BLOCK_SIZE)? (2*BLOCK_SIZE) : numRests);
stride <<= (LOG_BLOCK_SIZE + 1);
numRests >>= (LOG_BLOCK_SIZE + 1);
}
/*
cudaMemcpy(tmpArray, inArray, 10*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0;i<10;i++)
printf("%f\n", tmpArray[i]);
*/
float tmpNum = 0.0f;
cudaMemcpy(inArray + numElements - 1, &tmpNum, sizeof(float), cudaMemcpyHostToDevice);
unsigned threads = BLOCK_SIZE;
unsigned gridX = 1, gridY = 1;
if(threads >= (numElements>>1)) {
threads = (numElements>>1);
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, threads, LOG_BLOCK_SIZE);
}
else {
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, numElements>>1, LOG_BLOCK_SIZE);
int stride = numElements >> (LOG_BLOCK_SIZE + 2);
while(stride>0) {
gridX <<= 1;
if(gridX > 32768) {
gridX >>= 1;
gridY <<= 1;
}
dim3 grids2(gridX, gridY);
kernel_downtraverse<<<grids2, threads>>>(inArray, numElements, stride, LOG_BLOCK_SIZE);
stride>>=1;
}
}
}
// **===-----------------------------------------------------------===**
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
extern "C"
unsigned int compare( const float* reference, const float* data,
const unsigned int len);
extern "C"
void computeGold( float* reference, float* idata, const unsigned int len);
unsigned getSmallestPower2(unsigned);
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err);
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
runTest( argc, argv);
return EXIT_SUCCESS;
}
////////////////////////////////////////////////////////////////////////////////
// Get the power of 2 which is the least of the all powers that are not smaller
// than the given number
////////////////////////////////////////////////////////////////////////////////
int getSmallestPower2(int num) {
int result = 1;
while(result < num && result > 0)
result <<= 1;
if(result <= 0 || num <= 0) {
fprintf(stderr, "The size requested might be two large!\n");
exit(-1);
}
return result;
}
////////////////////////////////////////////////////////////////////////////////
//! Run a scan test for CUDA
////////////////////////////////////////////////////////////////////////////////
void
runTest( int argc, char** argv)
{
float device_time;
float host_time;
int num_elements = 0; // Must support large, non-power-of-2 arrays
int compare_size = 0;
// allocate host memory to store the input data
unsigned int mem_size = sizeof( float) * num_elements;
float* h_data = NULL;
// * No arguments: Randomly generate input data and compare against the
// host's result.
// * One argument: Randomly generate input data and write the result to
// file name specified by first argument
// * Two arguments: Read the first argument which indicates the size of the array,
// randomly generate input data and write the input data
// to the second argument. (for generating random input data)
// * Three arguments: Read the first file which indicate the size of the array,
// then input data from the file name specified by 2nd argument and write the
// SCAN output to file name specified by the 3rd argument.
switch(argc-1)
{
default: // No Arguments or one argument
// initialize the input data on the host to be integer values
// between 0 and 1000
// Use DEFAULT_NUM_ELEMENTS num_elements
if(argc <= 1)
compare_size = num_elements = DEFAULT_NUM_ELEMENTS;
else
compare_size = num_elements = atoi(argv[1]);
int tmp_size = num_elements;
num_elements = getSmallestPower2(num_elements);
// allocate host memory to store the input data
mem_size = sizeof( float) * num_elements;
//h_data = (float*) malloc( mem_size);
cudaMallocHost(&h_data, mem_size);
// initialize the input data on the host
for( unsigned int i = 0; i < num_elements; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = 0.0f;
}
for( unsigned int i = 0; i < tmp_size; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = (int)(rand() % MAX_RAND)*2 - 1;
}
break;
}
getLogBlockSize(BLOCK_SIZE);
cudaEvent_t time_start;
cudaEvent_t time_end;
cudaEventCreate(&time_start);
cudaEventCreate(&time_end);
// compute reference solution
float* reference = (float*) malloc( mem_size);
cudaEventRecord(time_start, 0);
computeGold( reference, h_data, num_elements);
cudaEventRecord(time_end, 0);
cudaEventSynchronize(time_end);
cudaEventElapsedTime(&host_time, time_start, time_end);
printf("\n\n**===-------------------------------------------------===**\n");
printf("Processing %d elements...\n", num_elements);
printf("Host CPU Processing time: %f (ms)\n", host_time);
// allocate device memory input and output arrays
float* d_idata = NULL;
float* d_odata = NULL;
cudaMalloc( (void**) &d_idata, mem_size);
cudaMalloc( (void**) &d_odata, mem_size);
// **===-------- Allocate data structure here -----------===**
// preallocBlockSums(num_elements);
// **===-----------------------------------------------------------===**
// Run just once to remove startup overhead for more accurate performance
// measurement
prescanArray(d_idata, 16);
// Run the prescan
cudaMemcpy( d_idata, h_data, mem_size, cudaMemcpyHostToDevice);
cudaEventRecord(time_start, 0);
// **===-------- Modify the body of this function -----------===**
prescanArray(d_idata, num_elements);
// **===-----------------------------------------------------------===**
cudaThreadSynchronize();
cudaEventRecord(time_end, 0);
cudaEventSynchronize(time_end);
cudaEventElapsedTime(&device_time, time_start, time_end);
// copy result from device to host
cudaMemcpy( h_data, d_idata, sizeof(float) * compare_size,
cudaMemcpyDeviceToHost);
printf("CUDA Processing time: %f (ms)\n", device_time);
printf("Speedup: %fX\n", host_time/device_time);
// **===-------- Deallocate data structure here -----------===**
// deallocBlockSums();
// **===-----------------------------------------------------------===**
// Check if the result is equivalent to the expected soluion
unsigned int result_regtest = cutComparef( reference, h_data, compare_size, 1e-6);
printf( "Test %s\n", (1 == result_regtest) ? "PASSED" : "FAILED");
// cleanup memory
cudaFreeHost(h_data);
free( reference);
cudaFree( d_odata);
cudaFree( d_idata);
printf("------------------------------------------------------\n\n");
}
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err) {
int i;
int diff_count = 0;
for (i = 0; i < num_elements; i++) {
float diff = fabs(reference[i] - h_data[i]);
float denominator = 1.f;
if (denominator < fabs(reference[i])) {
denominator = fabs(reference[i]);
}
if (i % 1000000 == 0) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
}
if (!(diff / denominator < err)) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
getchar();
diff_count ++;
}
}
if (diff_count > 0) {
printf("Number of difference: %d\n", diff_count);
return 0;
} else {
return 1;
}
} | code for sm_80
Function : _Z19kernel_downtraversePfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.SHL.U32 R3, R4, 0x2, RZ ; /* 0x0000000204037824 */
/* 0x000fc600078e00ff */
/*0070*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e640000002100 */
/*0080*/ ISETP.NE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f05270 */
/*0090*/ IMAD R2, R2, c[0x0][0xc], R5 ; /* 0x0000030002027a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x002fd000078e0207 */
/*00b0*/ @!P0 BRA 0x1b0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fca0007ffe0ff */
/*00d0*/ IMAD R2, R3, R2, RZ ; /* 0x0000000203027224 */
/* 0x000fca00078e02ff */
/*00e0*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f04270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0120*/ IADD3 R4, R2.reuse, -c[0x0][0x16c], RZ ; /* 0x80005b0002047a10 */
/* 0x040fe20007ffe0ff */
/*0130*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0150*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee8000c1e1900 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe2000c101904 */
/*0180*/ FADD R9, R0, R7 ; /* 0x0000000700097221 */
/* 0x008fca0000000000 */
/*0190*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ SHF.R.S32.HI R3, RZ, c[0x0][0x170], R4 ; /* 0x00005c00ff037a19 */
/* 0x000fe20000011404 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA R2, R2, 0x1, 0x1 ; /* 0x0000000102027811 */
/* 0x000fe400078e08ff */
/*01e0*/ IMNMX R5, R3, 0x1, !PT ; /* 0x0000000103057817 */
/* 0x000fca0007800200 */
/*01f0*/ IMAD R2, R5, R2, RZ ; /* 0x0000000205027224 */
/* 0x000fca00078e02ff */
/*0200*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*0210*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc60003f04270 */
/*0220*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0204 */
/*0230*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fc800078e0202 */
/*0240*/ @!P0 LDG.E R8, [R2.64] ; /* 0x0000000402088981 */
/* 0x000ea8000c1e1900 */
/*0250*/ @!P0 LDG.E R10, [R4.64] ; /* 0x00000004040a8981 */
/* 0x000ee2000c1e1900 */
/*0260*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD.SHL.U32 R6, R7, 0x2, RZ ; /* 0x0000000207067824 */
/* 0x000fc600078e00ff */
/*0280*/ ISETP.GE.AND P1, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe40003f26270 */
/*0290*/ LEA.HI.SX32 R7, R6, R6, 0x1c ; /* 0x0000000606077211 */
/* 0x000fca00078fe2ff */
/*02a0*/ @!P0 STS [R7.X4], R8 ; /* 0x0000000807008388 */
/* 0x0041e80000004800 */
/*02b0*/ @!P0 STS [R7.X4+0x4], R10 ; /* 0x0000040a07008388 */
/* 0x0081e80000004800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ @!P1 BRA 0x3e0 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R9, R6, 0x2, RZ ; /* 0x0000000206097810 */
/* 0x001fe20007ffe0ff */
/*02f0*/ IMAD.SHL.U32 R6, R11, 0x2, RZ ; /* 0x000000020b067824 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD R11, R9, R0, -0x1 ; /* 0xffffffff090b7424 */
/* 0x000fca00078e0200 */
/*0310*/ ISETP.GE.U32.AND P1, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x000fda0003f26070 */
/*0320*/ @!P1 IADD3 R8, R11.reuse, -R0, RZ ; /* 0x800000000b089210 */
/* 0x040fe40007ffe0ff */
/*0330*/ @!P1 LEA.HI.SX32 R10, R11, R11, 0x1c ; /* 0x0000000b0b0a9211 */
/* 0x000fe400078fe2ff */
/*0340*/ @!P1 LEA.HI.SX32 R8, R8, R8, 0x1c ; /* 0x0000000808089211 */
/* 0x000fe400078fe2ff */
/*0350*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011600 */
/*0360*/ @!P1 LDS R12, [R10.X4] ; /* 0x000000000a0c9984 */
/* 0x000e280000004800 */
/*0370*/ @!P1 LDS R11, [R8.X4] ; /* 0x00000000080b9984 */
/* 0x000e680000004800 */
/*0380*/ @!P1 STS [R8.X4], R12 ; /* 0x0000000c08009388 */
/* 0x0011e20000004800 */
/*0390*/ @!P1 FADD R11, R11, R12 ; /* 0x0000000c0b0b9221 */
/* 0x002fca0000000000 */
/*03a0*/ @!P1 STS [R10.X4], R11 ; /* 0x0000000b0a009388 */
/* 0x0001e80000004800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*03d0*/ @P1 BRA 0x300 ; /* 0xffffff2000001947 */
/* 0x001fea000383ffff */
/*03e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*03f0*/ LDS R9, [R7.X4] ; /* 0x0000000007097984 */
/* 0x000e280000004800 */
/*0400*/ LDS R11, [R7.X4+0x4] ; /* 0x00000400070b7984 */
/* 0x000e680000004800 */
/*0410*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x001fe8000c101904 */
/*0420*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x002fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16kernel_reductionPfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fe200078e0203 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0209 */
/*0090*/ LEA R0, R0, 0x1, 0x1 ; /* 0x0000000100007811 */
/* 0x000fca00078e08ff */
/*00a0*/ IMAD R0, R0, R5, -0x1 ; /* 0xffffffff00007424 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.SHL.U32 R0, R9, 0x2, RZ ; /* 0x0000000209007824 */
/* 0x000fca00078e00ff */
/*0100*/ LEA.HI.SX32 R6, R0, R0, 0x1c ; /* 0x0000000000067211 */
/* 0x000fe200078fe2ff */
/*0110*/ FADD R9, R7, R8 ; /* 0x0000000807097221 */
/* 0x004fe20000000000 */
/*0120*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fc80000000f00 */
/*0130*/ ISETP.GE.AND P0, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f06270 */
/*0140*/ STS [R6.X4], R7 ; /* 0x0000000706007388 */
/* 0x0001e80000004800 */
/*0150*/ STS [R6.X4+0x4], R9 ; /* 0x0000040906007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P0 BRA 0x2e0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x001fe200078e00ff */
/*0190*/ IADD3 R12, R0, 0x2, RZ ; /* 0x00000002000c7810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ UMOV UR4, 0x2 ; /* 0x0000000200047882 */
/* 0x000fc60000000000 */
/*01b0*/ SHF.R.S32.HI R11, RZ, 0x1, R7 ; /* 0x00000001ff0b7819 */
/* 0x000fe20000011407 */
/*01c0*/ BSSY B0, 0x290 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fda0003f06270 */
/*01e0*/ @P0 BRA 0x280 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*01f0*/ IMAD R8, R12, UR4, RZ ; /* 0x000000040c087c24 */
/* 0x000fca000f8e02ff */
/*0200*/ IADD3 R9, R8, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x000fc80007ffe0ff */
/*0210*/ IADD3 R10, R9.reuse, -UR4, RZ ; /* 0x80000004090a7c10 */
/* 0x040fe4000fffe0ff */
/*0220*/ LEA.HI.SX32 R8, R9, R8, 0x1c ; /* 0x0000000809087211 */
/* 0x000fe400078fe2ff */
/*0230*/ LEA.HI.SX32 R10, R10, R10, 0x1c ; /* 0x0000000a0a0a7211 */
/* 0x000fc600078fe2ff */
/*0240*/ LDS R9, [R8.X4+-0x4] ; /* 0xfffffc0008097984 */
/* 0x000fe80000004800 */
/*0250*/ LDS R10, [R10.X4] ; /* 0x000000000a0a7984 */
/* 0x000e240000004800 */
/*0260*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x001fca0000000000 */
/*0270*/ STS [R8.X4+-0x4], R9 ; /* 0xfffffc0908007388 */
/* 0x0001e40000004800 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GT.AND P0, PT, R7, 0x7, PT ; /* 0x000000070700780c */
/* 0x000fe20003f04270 */
/*02b0*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*02c0*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fd60000000f00 */
/*02d0*/ @P0 BRA 0x1b0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*02e0*/ LDS R7, [R6.X4] ; /* 0x0000000006077984 */
/* 0x001e280000004800 */
/*02f0*/ LDS R9, [R6.X4+0x4] ; /* 0x0000040006097984 */
/* 0x000e680000004800 */
/*0300*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101906 */
/*0310*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101906 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 1993-2006 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws.
*
* This software and the information contained herein is PROPRIETARY and
* CONFIDENTIAL to NVIDIA and is being provided under the terms and
* conditions of a Non-Disclosure Agreement. Any reproduction or
* disclosure to any third party without the express written consent of
* NVIDIA is prohibited.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*/
#ifdef _WIN32
# define NOMINMAX
#endif
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
// You can use any other block size you wish.
#define BLOCK_SIZE 256
#define DEFAULT_NUM_ELEMENTS 16777216
#define MAX_RAND 2
int LOG_BLOCK_SIZE;
void getLogBlockSize(int block_size) {
for(LOG_BLOCK_SIZE = 1;LOG_BLOCK_SIZE < 31; LOG_BLOCK_SIZE++) {
if((1<<LOG_BLOCK_SIZE) >= block_size)
return;
}
fprintf(stderr, "The size requested might be too large!\n");
exit(-1);
}
__global__ void kernel_reduction(float *inArray, int numElements, int stride, int numRest) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
__shared__ float idata[(BLOCK_SIZE << 1)+256];
int copyIdx = stride * ((idx << 1) + 1) - 1;
int copyToIdx = tid<<1;
copyToIdx += (copyToIdx>>4);
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx+1] = idata[copyToIdx] + inArray[copyIdx + stride];
__syncthreads();
int localStride = 2;
for(numRest>>=1;numRest > 1; numRest >>= 1, localStride <<= 1) {
if((tid<<1) < numRest) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
int idxTwo = idxOne - localStride;
idxOne += (idxOne >> 4);
idxTwo += (idxTwo >> 4);
idata[idxOne] += idata[idxTwo];
}
__syncthreads();
}
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+stride] = idata[copyToIdx+1];
}
__global__ void kernel_downtraverse(float *inArray, int numElements, int startStride, int LOG_BLOCK_SIZE) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
int finalStride = (startStride >> LOG_BLOCK_SIZE);
if(finalStride <= 0)
finalStride = 1;
if((startStride << 1) == numElements) {
__shared__ float idata[(BLOCK_SIZE<<1)+256];
int copyIdx = finalStride * ((idx << 1) + 1) - 1;
int copyToIdx = (tid<<1);
copyToIdx += (copyToIdx>>4);
if(copyIdx < numElements){
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx + 1] = inArray[copyIdx+finalStride];
}
__syncthreads();
int localStride = blockDim.x;
while(localStride >= 1) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
if(idxOne < (blockDim.x<<1)) {
int idxTwo = idxOne - localStride;
idxOne += (idxOne>>4);
idxTwo += (idxTwo>>4);
float tmp = idata[idxOne] + idata[idxTwo];
idata[idxTwo] = idata[idxOne];
idata[idxOne] = tmp;
}
localStride >>= 1;
__syncthreads();
}
if(copyIdx < numElements) {
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+finalStride] = idata[copyToIdx+1];
}
}
else {
int stride = startStride;
int idxOne = (stride << 1) * (idx + 1) - 1;
if(idxOne < numElements) {
int idxTwo = idxOne - stride;
float tmp = inArray[idxOne] + inArray[idxTwo];
inArray[idxTwo] = inArray[idxOne];
inArray[idxOne] = tmp;
}
}
}
// **===-------- Modify the body of this function -----------===**
// You may need to make multiple kernel calls.
void prescanArray(float *inArray, int numElements)
{
unsigned numRests = numElements;
int stride = 1;
while(numRests > 1) {
unsigned threads = numRests / 2;
unsigned gridX = 1, gridY = 1;
if(threads > BLOCK_SIZE) {
gridX = threads / BLOCK_SIZE;
threads = BLOCK_SIZE;
if(gridX > 32768) {
gridY = gridX / 32768;
gridX = 32768;
}
}
dim3 grids(gridX, gridY);
kernel_reduction<<<grids,threads>>>(inArray, numElements, stride, numRests > (2*BLOCK_SIZE)? (2*BLOCK_SIZE) : numRests);
stride <<= (LOG_BLOCK_SIZE + 1);
numRests >>= (LOG_BLOCK_SIZE + 1);
}
/*
cudaMemcpy(tmpArray, inArray, 10*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0;i<10;i++)
printf("%f\n", tmpArray[i]);
*/
float tmpNum = 0.0f;
cudaMemcpy(inArray + numElements - 1, &tmpNum, sizeof(float), cudaMemcpyHostToDevice);
unsigned threads = BLOCK_SIZE;
unsigned gridX = 1, gridY = 1;
if(threads >= (numElements>>1)) {
threads = (numElements>>1);
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, threads, LOG_BLOCK_SIZE);
}
else {
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, numElements>>1, LOG_BLOCK_SIZE);
int stride = numElements >> (LOG_BLOCK_SIZE + 2);
while(stride>0) {
gridX <<= 1;
if(gridX > 32768) {
gridX >>= 1;
gridY <<= 1;
}
dim3 grids2(gridX, gridY);
kernel_downtraverse<<<grids2, threads>>>(inArray, numElements, stride, LOG_BLOCK_SIZE);
stride>>=1;
}
}
}
// **===-----------------------------------------------------------===**
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
extern "C"
unsigned int compare( const float* reference, const float* data,
const unsigned int len);
extern "C"
void computeGold( float* reference, float* idata, const unsigned int len);
unsigned getSmallestPower2(unsigned);
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err);
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
runTest( argc, argv);
return EXIT_SUCCESS;
}
////////////////////////////////////////////////////////////////////////////////
// Get the power of 2 which is the least of the all powers that are not smaller
// than the given number
////////////////////////////////////////////////////////////////////////////////
int getSmallestPower2(int num) {
int result = 1;
while(result < num && result > 0)
result <<= 1;
if(result <= 0 || num <= 0) {
fprintf(stderr, "The size requested might be two large!\n");
exit(-1);
}
return result;
}
////////////////////////////////////////////////////////////////////////////////
//! Run a scan test for CUDA
////////////////////////////////////////////////////////////////////////////////
void
runTest( int argc, char** argv)
{
float device_time;
float host_time;
int num_elements = 0; // Must support large, non-power-of-2 arrays
int compare_size = 0;
// allocate host memory to store the input data
unsigned int mem_size = sizeof( float) * num_elements;
float* h_data = NULL;
// * No arguments: Randomly generate input data and compare against the
// host's result.
// * One argument: Randomly generate input data and write the result to
// file name specified by first argument
// * Two arguments: Read the first argument which indicates the size of the array,
// randomly generate input data and write the input data
// to the second argument. (for generating random input data)
// * Three arguments: Read the first file which indicate the size of the array,
// then input data from the file name specified by 2nd argument and write the
// SCAN output to file name specified by the 3rd argument.
switch(argc-1)
{
default: // No Arguments or one argument
// initialize the input data on the host to be integer values
// between 0 and 1000
// Use DEFAULT_NUM_ELEMENTS num_elements
if(argc <= 1)
compare_size = num_elements = DEFAULT_NUM_ELEMENTS;
else
compare_size = num_elements = atoi(argv[1]);
int tmp_size = num_elements;
num_elements = getSmallestPower2(num_elements);
// allocate host memory to store the input data
mem_size = sizeof( float) * num_elements;
//h_data = (float*) malloc( mem_size);
cudaMallocHost(&h_data, mem_size);
// initialize the input data on the host
for( unsigned int i = 0; i < num_elements; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = 0.0f;
}
for( unsigned int i = 0; i < tmp_size; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = (int)(rand() % MAX_RAND)*2 - 1;
}
break;
}
getLogBlockSize(BLOCK_SIZE);
cudaEvent_t time_start;
cudaEvent_t time_end;
cudaEventCreate(&time_start);
cudaEventCreate(&time_end);
// compute reference solution
float* reference = (float*) malloc( mem_size);
cudaEventRecord(time_start, 0);
computeGold( reference, h_data, num_elements);
cudaEventRecord(time_end, 0);
cudaEventSynchronize(time_end);
cudaEventElapsedTime(&host_time, time_start, time_end);
printf("\n\n**===-------------------------------------------------===**\n");
printf("Processing %d elements...\n", num_elements);
printf("Host CPU Processing time: %f (ms)\n", host_time);
// allocate device memory input and output arrays
float* d_idata = NULL;
float* d_odata = NULL;
cudaMalloc( (void**) &d_idata, mem_size);
cudaMalloc( (void**) &d_odata, mem_size);
// **===-------- Allocate data structure here -----------===**
// preallocBlockSums(num_elements);
// **===-----------------------------------------------------------===**
// Run just once to remove startup overhead for more accurate performance
// measurement
prescanArray(d_idata, 16);
// Run the prescan
cudaMemcpy( d_idata, h_data, mem_size, cudaMemcpyHostToDevice);
cudaEventRecord(time_start, 0);
// **===-------- Modify the body of this function -----------===**
prescanArray(d_idata, num_elements);
// **===-----------------------------------------------------------===**
cudaThreadSynchronize();
cudaEventRecord(time_end, 0);
cudaEventSynchronize(time_end);
cudaEventElapsedTime(&device_time, time_start, time_end);
// copy result from device to host
cudaMemcpy( h_data, d_idata, sizeof(float) * compare_size,
cudaMemcpyDeviceToHost);
printf("CUDA Processing time: %f (ms)\n", device_time);
printf("Speedup: %fX\n", host_time/device_time);
// **===-------- Deallocate data structure here -----------===**
// deallocBlockSums();
// **===-----------------------------------------------------------===**
// Check if the result is equivalent to the expected soluion
unsigned int result_regtest = cutComparef( reference, h_data, compare_size, 1e-6);
printf( "Test %s\n", (1 == result_regtest) ? "PASSED" : "FAILED");
// cleanup memory
cudaFreeHost(h_data);
free( reference);
cudaFree( d_odata);
cudaFree( d_idata);
printf("------------------------------------------------------\n\n");
}
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err) {
int i;
int diff_count = 0;
for (i = 0; i < num_elements; i++) {
float diff = fabs(reference[i] - h_data[i]);
float denominator = 1.f;
if (denominator < fabs(reference[i])) {
denominator = fabs(reference[i]);
}
if (i % 1000000 == 0) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
}
if (!(diff / denominator < err)) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
getchar();
diff_count ++;
}
}
if (diff_count > 0) {
printf("Number of difference: %d\n", diff_count);
return 0;
} else {
return 1;
}
} | .file "tmpxft_0001cf4e_00000000-6_scan_largearray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "The size requested might be too large!\n"
.text
.globl _Z15getLogBlockSizei
.type _Z15getLogBlockSizei, @function
_Z15getLogBlockSizei:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %esi
movl $1, %ecx
movl $1, %r8d
movl $1, %r9d
jmp .L7
.L8:
movl %ecx, %edx
.L7:
movl %r8d, %eax
sall %cl, %eax
cmpl %edi, %eax
jge .L13
addl $1, %ecx
movl %r9d, %esi
cmpl $31, %ecx
jne .L8
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $31, LOG_BLOCK_SIZE(%rip)
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L13:
.cfi_def_cfa_offset 8
testb %sil, %sil
movl $1, %eax
cmove %eax, %edx
movl %edx, LOG_BLOCK_SIZE(%rip)
ret
.cfi_endproc
.LFE2057:
.size _Z15getLogBlockSizei, .-_Z15getLogBlockSizei
.section .rodata.str1.8
.align 8
.LC1:
.string "The size requested might be two large!\n"
.text
.globl _Z17getSmallestPower2i
.type _Z17getSmallestPower2i, @function
_Z17getSmallestPower2i:
.LFB2060:
.cfi_startproc
endbr64
cmpl $1, %edi
jle .L20
movl $1, %eax
.L16:
addl %eax, %eax
cmpl %eax, %edi
jle .L15
testl %eax, %eax
jg .L16
.L15:
testl %eax, %eax
jle .L21
testl %edi, %edi
jle .L21
ret
.L20:
movl $1, %eax
jmp .L15
.L21:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z17getSmallestPower2i, .-_Z17getSmallestPower2i
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Number of difference: %d\n"
.text
.globl _Z11cutComparefPfS_if
.type _Z11cutComparefPfS_if, @function
_Z11cutComparefPfS_if:
.LFB2062:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movss %xmm0, 12(%rsp)
testl %edx, %edx
jle .L30
movq %rdi, %rbx
movq %rsi, %rbp
movslq %edx, %rdx
leaq (%rdi,%rdx,4), %r12
movl $0, %r13d
jmp .L29
.L28:
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
je .L34
.L29:
movss (%rbx), %xmm0
movaps %xmm0, %xmm1
subss 0(%rbp), %xmm1
andps .LC3(%rip), %xmm1
andps .LC3(%rip), %xmm0
movss .LC2(%rip), %xmm2
cmpltss %xmm0, %xmm2
andps %xmm2, %xmm0
movss .LC2(%rip), %xmm3
andnps %xmm3, %xmm2
orps %xmm2, %xmm0
divss %xmm0, %xmm1
movss 12(%rsp), %xmm4
comiss %xmm1, %xmm4
ja .L28
movq stdin(%rip), %rdi
call getc@PLT
addl $1, %r13d
jmp .L28
.L34:
movl $1, %eax
testl %r13d, %r13d
jg .L35
.L25:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %r13d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L25
.L30:
movl $1, %eax
jmp .L25
.cfi_endproc
.LFE2062:
.size _Z11cutComparefPfS_if, .-_Z11cutComparefPfS_if
.globl _Z39__device_stub__Z16kernel_reductionPfiiiPfiii
.type _Z39__device_stub__Z16kernel_reductionPfiiiPfiii, @function
_Z39__device_stub__Z16kernel_reductionPfiiiPfiii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16kernel_reductionPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z39__device_stub__Z16kernel_reductionPfiiiPfiii, .-_Z39__device_stub__Z16kernel_reductionPfiiiPfiii
.globl _Z16kernel_reductionPfiii
.type _Z16kernel_reductionPfiii, @function
_Z16kernel_reductionPfiii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16kernel_reductionPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z16kernel_reductionPfiii, .-_Z16kernel_reductionPfiii
.globl _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
.type _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii, @function
_Z42__device_stub__Z19kernel_downtraversePfiiiPfiii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19kernel_downtraversePfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii, .-_Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
.globl _Z19kernel_downtraversePfiii
.type _Z19kernel_downtraversePfiii, @function
_Z19kernel_downtraversePfiii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z19kernel_downtraversePfiii, .-_Z19kernel_downtraversePfiii
.globl _Z12prescanArrayPfi
.type _Z12prescanArrayPfi, @function
_Z12prescanArrayPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %esi
jbe .L53
movl %esi, %ebx
movl $1, %r12d
movl $1, %ebp
jmp .L58
.L54:
cmpl $16777727, %ebx
ja .L56
movl %ebx, %ecx
shrl $9, %ecx
movl %ebp, %edx
movl $256, %eax
.L55:
movl %ecx, 16(%rsp)
movl %edx, 20(%rsp)
movl %ebp, 24(%rsp)
movl %eax, 28(%rsp)
movl %ebp, 32(%rsp)
movl %ebp, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl %ebp, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L57:
movl LOG_BLOCK_SIZE(%rip), %eax
leal 1(%rax), %ecx
sall %cl, %r12d
shrl %cl, %ebx
cmpl $1, %ebx
jbe .L74
.L58:
cmpl $513, %ebx
ja .L54
movl %ebx, %eax
shrl %eax
movl %ebp, %edx
movl %ebp, %ecx
jmp .L55
.L56:
movl %ebx, %edx
shrl $24, %edx
movl $32768, %ecx
movl $256, %eax
jmp .L55
.L73:
movl $512, %ecx
cmpl %ecx, %ebx
cmovbe %ebx, %ecx
movl %r12d, %edx
movl %r13d, %esi
movq %r14, %rdi
call _Z39__device_stub__Z16kernel_reductionPfiiiPfiii
jmp .L57
.L74:
movl $0x00000000, (%rsp)
movq %rsp, %rsi
movslq %r13d, %rax
leaq -4(%r14,%rax,4), %rdi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movl %r13d, %ebx
sarl %ebx
movl %ebx, %eax
cmpl $256, %ebx
jbe .L67
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 4(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L62:
movl LOG_BLOCK_SIZE(%rip), %eax
leal 2(%rax), %ecx
movl %r13d, %ebx
sarl %cl, %ebx
testl %ebx, %ebx
jle .L52
movl $1, %r12d
movl $1, %ebp
jmp .L66
.L77:
movl LOG_BLOCK_SIZE(%rip), %ecx
movl %ebx, %edx
movl %r13d, %esi
movq %r14, %rdi
call _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
jmp .L52
.L75:
movl LOG_BLOCK_SIZE(%rip), %ecx
movl %ebx, %edx
movl %r13d, %esi
movq %r14, %rdi
call _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
jmp .L62
.L69:
movl %eax, %ebp
.L64:
movl %ebp, 16(%rsp)
movl %r12d, 20(%rsp)
movl $1, 24(%rsp)
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L76
.L65:
sarl %ebx
testl %ebx, %ebx
jle .L52
.L66:
leal (%rbp,%rbp), %eax
cmpl $32768, %eax
jbe .L69
addl %r12d, %r12d
jmp .L64
.L76:
movl LOG_BLOCK_SIZE(%rip), %ecx
movl %ebx, %edx
movl %r13d, %esi
movq %r14, %rdi
call _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
jmp .L65
.L53:
movl $0x00000000, (%rsp)
movq %rsp, %rsi
movslq %r13d, %rax
leaq -4(%rdi,%rax,4), %rdi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movl $0, %eax
movl $0, %ebx
.L67:
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L52:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12prescanArrayPfi, .-_Z12prescanArrayPfi
.section .rodata.str1.1
.LC6:
.string "PASSED"
.LC7:
.string "FAILED"
.section .rodata.str1.8
.align 8
.LC8:
.string "\n\n**===-------------------------------------------------===**\n"
.section .rodata.str1.1
.LC9:
.string "Processing %d elements...\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Host CPU Processing time: %f (ms)\n"
.align 8
.LC11:
.string "CUDA Processing time: %f (ms)\n"
.section .rodata.str1.1
.LC12:
.string "Speedup: %fX\n"
.LC14:
.string "Test %s\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "------------------------------------------------------\n\n"
.text
.globl _Z7runTestiPPc
.type _Z7runTestiPPc, @function
_Z7runTestiPPc:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
cmpl $1, %edi
jg .L95
movl $16777216, %edi
call _Z17getSmallestPower2i
movl %eax, %r12d
leal 0(,%r12,4), %r14d
leaq 16(%rsp), %rdi
movl $0, %edx
movq %r14, %rsi
call cudaHostAlloc@PLT
movl %r12d, %r15d
movl $16777216, %r13d
movl $16777216, %ebp
testl %r12d, %r12d
je .L87
.L86:
movl %r15d, %ecx
salq $2, %rcx
movl $0, %eax
.L82:
movq 16(%rsp), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L82
.L81:
movl %r13d, %ebp
testl %r13d, %r13d
je .L83
.L87:
movl %ebp, %ebp
salq $2, %rbp
movl $0, %ebx
.L84:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
leal -1(%rax,%rax), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L84
.L83:
movl $256, %edi
call _Z15getLogBlockSizei
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call computeGold@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq $0, 40(%rsp)
movq $0, 48(%rsp)
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $16, %esi
movq 40(%rsp), %rdi
call _Z12prescanArrayPfi
movl $1, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %r12d, %esi
movq 40(%rsp), %rdi
call _Z12prescanArrayPfi
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movslq %r13d, %rdx
salq $2, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
divss 8(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC13(%rip), %xmm0
movl %r13d, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call _Z11cutComparefPfS_if
cmpl $1, %eax
leaq .LC7(%rip), %rdx
leaq .LC6(%rip), %rax
cmove %rax, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
movl %eax, %edi
call _Z17getSmallestPower2i
movl %eax, %r12d
leal 0(,%r12,4), %r14d
leaq 16(%rsp), %rdi
movl $0, %edx
movq %r14, %rsi
call cudaHostAlloc@PLT
movl %r12d, %r15d
testl %r12d, %r12d
jne .L86
jmp .L81
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z7runTestiPPc, .-_Z7runTestiPPc
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z7runTestiPPc
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z19kernel_downtraversePfiii"
.LC17:
.string "_Z16kernel_reductionPfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z19kernel_downtraversePfiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernel_reductionPfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl LOG_BLOCK_SIZE
.bss
.align 4
.type LOG_BLOCK_SIZE, @object
.size LOG_BLOCK_SIZE, 4
LOG_BLOCK_SIZE:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC13:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 1993-2006 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws.
*
* This software and the information contained herein is PROPRIETARY and
* CONFIDENTIAL to NVIDIA and is being provided under the terms and
* conditions of a Non-Disclosure Agreement. Any reproduction or
* disclosure to any third party without the express written consent of
* NVIDIA is prohibited.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*/
#ifdef _WIN32
# define NOMINMAX
#endif
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
// You can use any other block size you wish.
#define BLOCK_SIZE 256
#define DEFAULT_NUM_ELEMENTS 16777216
#define MAX_RAND 2
int LOG_BLOCK_SIZE;
void getLogBlockSize(int block_size) {
for(LOG_BLOCK_SIZE = 1;LOG_BLOCK_SIZE < 31; LOG_BLOCK_SIZE++) {
if((1<<LOG_BLOCK_SIZE) >= block_size)
return;
}
fprintf(stderr, "The size requested might be too large!\n");
exit(-1);
}
__global__ void kernel_reduction(float *inArray, int numElements, int stride, int numRest) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
__shared__ float idata[(BLOCK_SIZE << 1)+256];
int copyIdx = stride * ((idx << 1) + 1) - 1;
int copyToIdx = tid<<1;
copyToIdx += (copyToIdx>>4);
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx+1] = idata[copyToIdx] + inArray[copyIdx + stride];
__syncthreads();
int localStride = 2;
for(numRest>>=1;numRest > 1; numRest >>= 1, localStride <<= 1) {
if((tid<<1) < numRest) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
int idxTwo = idxOne - localStride;
idxOne += (idxOne >> 4);
idxTwo += (idxTwo >> 4);
idata[idxOne] += idata[idxTwo];
}
__syncthreads();
}
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+stride] = idata[copyToIdx+1];
}
__global__ void kernel_downtraverse(float *inArray, int numElements, int startStride, int LOG_BLOCK_SIZE) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
int finalStride = (startStride >> LOG_BLOCK_SIZE);
if(finalStride <= 0)
finalStride = 1;
if((startStride << 1) == numElements) {
__shared__ float idata[(BLOCK_SIZE<<1)+256];
int copyIdx = finalStride * ((idx << 1) + 1) - 1;
int copyToIdx = (tid<<1);
copyToIdx += (copyToIdx>>4);
if(copyIdx < numElements){
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx + 1] = inArray[copyIdx+finalStride];
}
__syncthreads();
int localStride = blockDim.x;
while(localStride >= 1) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
if(idxOne < (blockDim.x<<1)) {
int idxTwo = idxOne - localStride;
idxOne += (idxOne>>4);
idxTwo += (idxTwo>>4);
float tmp = idata[idxOne] + idata[idxTwo];
idata[idxTwo] = idata[idxOne];
idata[idxOne] = tmp;
}
localStride >>= 1;
__syncthreads();
}
if(copyIdx < numElements) {
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+finalStride] = idata[copyToIdx+1];
}
}
else {
int stride = startStride;
int idxOne = (stride << 1) * (idx + 1) - 1;
if(idxOne < numElements) {
int idxTwo = idxOne - stride;
float tmp = inArray[idxOne] + inArray[idxTwo];
inArray[idxTwo] = inArray[idxOne];
inArray[idxOne] = tmp;
}
}
}
// **===-------- Modify the body of this function -----------===**
// You may need to make multiple kernel calls.
void prescanArray(float *inArray, int numElements)
{
unsigned numRests = numElements;
int stride = 1;
while(numRests > 1) {
unsigned threads = numRests / 2;
unsigned gridX = 1, gridY = 1;
if(threads > BLOCK_SIZE) {
gridX = threads / BLOCK_SIZE;
threads = BLOCK_SIZE;
if(gridX > 32768) {
gridY = gridX / 32768;
gridX = 32768;
}
}
dim3 grids(gridX, gridY);
kernel_reduction<<<grids,threads>>>(inArray, numElements, stride, numRests > (2*BLOCK_SIZE)? (2*BLOCK_SIZE) : numRests);
stride <<= (LOG_BLOCK_SIZE + 1);
numRests >>= (LOG_BLOCK_SIZE + 1);
}
/*
cudaMemcpy(tmpArray, inArray, 10*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0;i<10;i++)
printf("%f\n", tmpArray[i]);
*/
float tmpNum = 0.0f;
cudaMemcpy(inArray + numElements - 1, &tmpNum, sizeof(float), cudaMemcpyHostToDevice);
unsigned threads = BLOCK_SIZE;
unsigned gridX = 1, gridY = 1;
if(threads >= (numElements>>1)) {
threads = (numElements>>1);
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, threads, LOG_BLOCK_SIZE);
}
else {
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, numElements>>1, LOG_BLOCK_SIZE);
int stride = numElements >> (LOG_BLOCK_SIZE + 2);
while(stride>0) {
gridX <<= 1;
if(gridX > 32768) {
gridX >>= 1;
gridY <<= 1;
}
dim3 grids2(gridX, gridY);
kernel_downtraverse<<<grids2, threads>>>(inArray, numElements, stride, LOG_BLOCK_SIZE);
stride>>=1;
}
}
}
// **===-----------------------------------------------------------===**
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
extern "C"
unsigned int compare( const float* reference, const float* data,
const unsigned int len);
extern "C"
void computeGold( float* reference, float* idata, const unsigned int len);
unsigned getSmallestPower2(unsigned);
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err);
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
runTest( argc, argv);
return EXIT_SUCCESS;
}
////////////////////////////////////////////////////////////////////////////////
// Get the power of 2 which is the least of the all powers that are not smaller
// than the given number
////////////////////////////////////////////////////////////////////////////////
int getSmallestPower2(int num) {
int result = 1;
while(result < num && result > 0)
result <<= 1;
if(result <= 0 || num <= 0) {
fprintf(stderr, "The size requested might be two large!\n");
exit(-1);
}
return result;
}
////////////////////////////////////////////////////////////////////////////////
//! Run a scan test for CUDA
////////////////////////////////////////////////////////////////////////////////
void
runTest( int argc, char** argv)
{
float device_time;
float host_time;
int num_elements = 0; // Must support large, non-power-of-2 arrays
int compare_size = 0;
// allocate host memory to store the input data
unsigned int mem_size = sizeof( float) * num_elements;
float* h_data = NULL;
// * No arguments: Randomly generate input data and compare against the
// host's result.
// * One argument: Randomly generate input data and write the result to
// file name specified by first argument
// * Two arguments: Read the first argument which indicates the size of the array,
// randomly generate input data and write the input data
// to the second argument. (for generating random input data)
// * Three arguments: Read the first file which indicate the size of the array,
// then input data from the file name specified by 2nd argument and write the
// SCAN output to file name specified by the 3rd argument.
switch(argc-1)
{
default: // No Arguments or one argument
// initialize the input data on the host to be integer values
// between 0 and 1000
// Use DEFAULT_NUM_ELEMENTS num_elements
if(argc <= 1)
compare_size = num_elements = DEFAULT_NUM_ELEMENTS;
else
compare_size = num_elements = atoi(argv[1]);
int tmp_size = num_elements;
num_elements = getSmallestPower2(num_elements);
// allocate host memory to store the input data
mem_size = sizeof( float) * num_elements;
//h_data = (float*) malloc( mem_size);
cudaMallocHost(&h_data, mem_size);
// initialize the input data on the host
for( unsigned int i = 0; i < num_elements; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = 0.0f;
}
for( unsigned int i = 0; i < tmp_size; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = (int)(rand() % MAX_RAND)*2 - 1;
}
break;
}
getLogBlockSize(BLOCK_SIZE);
cudaEvent_t time_start;
cudaEvent_t time_end;
cudaEventCreate(&time_start);
cudaEventCreate(&time_end);
// compute reference solution
float* reference = (float*) malloc( mem_size);
cudaEventRecord(time_start, 0);
computeGold( reference, h_data, num_elements);
cudaEventRecord(time_end, 0);
cudaEventSynchronize(time_end);
cudaEventElapsedTime(&host_time, time_start, time_end);
printf("\n\n**===-------------------------------------------------===**\n");
printf("Processing %d elements...\n", num_elements);
printf("Host CPU Processing time: %f (ms)\n", host_time);
// allocate device memory input and output arrays
float* d_idata = NULL;
float* d_odata = NULL;
cudaMalloc( (void**) &d_idata, mem_size);
cudaMalloc( (void**) &d_odata, mem_size);
// **===-------- Allocate data structure here -----------===**
// preallocBlockSums(num_elements);
// **===-----------------------------------------------------------===**
// Run just once to remove startup overhead for more accurate performance
// measurement
prescanArray(d_idata, 16);
// Run the prescan
cudaMemcpy( d_idata, h_data, mem_size, cudaMemcpyHostToDevice);
cudaEventRecord(time_start, 0);
// **===-------- Modify the body of this function -----------===**
prescanArray(d_idata, num_elements);
// **===-----------------------------------------------------------===**
cudaThreadSynchronize();
cudaEventRecord(time_end, 0);
cudaEventSynchronize(time_end);
cudaEventElapsedTime(&device_time, time_start, time_end);
// copy result from device to host
cudaMemcpy( h_data, d_idata, sizeof(float) * compare_size,
cudaMemcpyDeviceToHost);
printf("CUDA Processing time: %f (ms)\n", device_time);
printf("Speedup: %fX\n", host_time/device_time);
// **===-------- Deallocate data structure here -----------===**
// deallocBlockSums();
// **===-----------------------------------------------------------===**
// Check if the result is equivalent to the expected soluion
unsigned int result_regtest = cutComparef( reference, h_data, compare_size, 1e-6);
printf( "Test %s\n", (1 == result_regtest) ? "PASSED" : "FAILED");
// cleanup memory
cudaFreeHost(h_data);
free( reference);
cudaFree( d_odata);
cudaFree( d_idata);
printf("------------------------------------------------------\n\n");
}
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err) {
int i;
int diff_count = 0;
for (i = 0; i < num_elements; i++) {
float diff = fabs(reference[i] - h_data[i]);
float denominator = 1.f;
if (denominator < fabs(reference[i])) {
denominator = fabs(reference[i]);
}
if (i % 1000000 == 0) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
}
if (!(diff / denominator < err)) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
getchar();
diff_count ++;
}
}
if (diff_count > 0) {
printf("Number of difference: %d\n", diff_count);
return 0;
} else {
return 1;
}
} | /*
* Copyright 1993-2006 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws.
*
* This software and the information contained herein is PROPRIETARY and
* CONFIDENTIAL to NVIDIA and is being provided under the terms and
* conditions of a Non-Disclosure Agreement. Any reproduction or
* disclosure to any third party without the express written consent of
* NVIDIA is prohibited.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*/
#ifdef _WIN32
# define NOMINMAX
#endif
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
// You can use any other block size you wish.
#define BLOCK_SIZE 256
#define DEFAULT_NUM_ELEMENTS 16777216
#define MAX_RAND 2
int LOG_BLOCK_SIZE;
void getLogBlockSize(int block_size) {
for(LOG_BLOCK_SIZE = 1;LOG_BLOCK_SIZE < 31; LOG_BLOCK_SIZE++) {
if((1<<LOG_BLOCK_SIZE) >= block_size)
return;
}
fprintf(stderr, "The size requested might be too large!\n");
exit(-1);
}
__global__ void kernel_reduction(float *inArray, int numElements, int stride, int numRest) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
__shared__ float idata[(BLOCK_SIZE << 1)+256];
int copyIdx = stride * ((idx << 1) + 1) - 1;
int copyToIdx = tid<<1;
copyToIdx += (copyToIdx>>4);
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx+1] = idata[copyToIdx] + inArray[copyIdx + stride];
__syncthreads();
int localStride = 2;
for(numRest>>=1;numRest > 1; numRest >>= 1, localStride <<= 1) {
if((tid<<1) < numRest) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
int idxTwo = idxOne - localStride;
idxOne += (idxOne >> 4);
idxTwo += (idxTwo >> 4);
idata[idxOne] += idata[idxTwo];
}
__syncthreads();
}
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+stride] = idata[copyToIdx+1];
}
__global__ void kernel_downtraverse(float *inArray, int numElements, int startStride, int LOG_BLOCK_SIZE) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
int finalStride = (startStride >> LOG_BLOCK_SIZE);
if(finalStride <= 0)
finalStride = 1;
if((startStride << 1) == numElements) {
__shared__ float idata[(BLOCK_SIZE<<1)+256];
int copyIdx = finalStride * ((idx << 1) + 1) - 1;
int copyToIdx = (tid<<1);
copyToIdx += (copyToIdx>>4);
if(copyIdx < numElements){
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx + 1] = inArray[copyIdx+finalStride];
}
__syncthreads();
int localStride = blockDim.x;
while(localStride >= 1) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
if(idxOne < (blockDim.x<<1)) {
int idxTwo = idxOne - localStride;
idxOne += (idxOne>>4);
idxTwo += (idxTwo>>4);
float tmp = idata[idxOne] + idata[idxTwo];
idata[idxTwo] = idata[idxOne];
idata[idxOne] = tmp;
}
localStride >>= 1;
__syncthreads();
}
if(copyIdx < numElements) {
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+finalStride] = idata[copyToIdx+1];
}
}
else {
int stride = startStride;
int idxOne = (stride << 1) * (idx + 1) - 1;
if(idxOne < numElements) {
int idxTwo = idxOne - stride;
float tmp = inArray[idxOne] + inArray[idxTwo];
inArray[idxTwo] = inArray[idxOne];
inArray[idxOne] = tmp;
}
}
}
// **===-------- Modify the body of this function -----------===**
// You may need to make multiple kernel calls.
void prescanArray(float *inArray, int numElements)
{
unsigned numRests = numElements;
int stride = 1;
while(numRests > 1) {
unsigned threads = numRests / 2;
unsigned gridX = 1, gridY = 1;
if(threads > BLOCK_SIZE) {
gridX = threads / BLOCK_SIZE;
threads = BLOCK_SIZE;
if(gridX > 32768) {
gridY = gridX / 32768;
gridX = 32768;
}
}
dim3 grids(gridX, gridY);
kernel_reduction<<<grids,threads>>>(inArray, numElements, stride, numRests > (2*BLOCK_SIZE)? (2*BLOCK_SIZE) : numRests);
stride <<= (LOG_BLOCK_SIZE + 1);
numRests >>= (LOG_BLOCK_SIZE + 1);
}
/*
cudaMemcpy(tmpArray, inArray, 10*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0;i<10;i++)
printf("%f\n", tmpArray[i]);
*/
float tmpNum = 0.0f;
hipMemcpy(inArray + numElements - 1, &tmpNum, sizeof(float), hipMemcpyHostToDevice);
unsigned threads = BLOCK_SIZE;
unsigned gridX = 1, gridY = 1;
if(threads >= (numElements>>1)) {
threads = (numElements>>1);
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, threads, LOG_BLOCK_SIZE);
}
else {
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, numElements>>1, LOG_BLOCK_SIZE);
int stride = numElements >> (LOG_BLOCK_SIZE + 2);
while(stride>0) {
gridX <<= 1;
if(gridX > 32768) {
gridX >>= 1;
gridY <<= 1;
}
dim3 grids2(gridX, gridY);
kernel_downtraverse<<<grids2, threads>>>(inArray, numElements, stride, LOG_BLOCK_SIZE);
stride>>=1;
}
}
}
// **===-----------------------------------------------------------===**
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
extern "C"
unsigned int compare( const float* reference, const float* data,
const unsigned int len);
extern "C"
void computeGold( float* reference, float* idata, const unsigned int len);
unsigned getSmallestPower2(unsigned);
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err);
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
runTest( argc, argv);
return EXIT_SUCCESS;
}
////////////////////////////////////////////////////////////////////////////////
// Get the power of 2 which is the least of the all powers that are not smaller
// than the given number
////////////////////////////////////////////////////////////////////////////////
int getSmallestPower2(int num) {
int result = 1;
while(result < num && result > 0)
result <<= 1;
if(result <= 0 || num <= 0) {
fprintf(stderr, "The size requested might be two large!\n");
exit(-1);
}
return result;
}
////////////////////////////////////////////////////////////////////////////////
//! Run a scan test for CUDA
////////////////////////////////////////////////////////////////////////////////
void
runTest( int argc, char** argv)
{
float device_time;
float host_time;
int num_elements = 0; // Must support large, non-power-of-2 arrays
int compare_size = 0;
// allocate host memory to store the input data
unsigned int mem_size = sizeof( float) * num_elements;
float* h_data = NULL;
// * No arguments: Randomly generate input data and compare against the
// host's result.
// * One argument: Randomly generate input data and write the result to
// file name specified by first argument
// * Two arguments: Read the first argument which indicates the size of the array,
// randomly generate input data and write the input data
// to the second argument. (for generating random input data)
// * Three arguments: Read the first file which indicate the size of the array,
// then input data from the file name specified by 2nd argument and write the
// SCAN output to file name specified by the 3rd argument.
switch(argc-1)
{
default: // No Arguments or one argument
// initialize the input data on the host to be integer values
// between 0 and 1000
// Use DEFAULT_NUM_ELEMENTS num_elements
if(argc <= 1)
compare_size = num_elements = DEFAULT_NUM_ELEMENTS;
else
compare_size = num_elements = atoi(argv[1]);
int tmp_size = num_elements;
num_elements = getSmallestPower2(num_elements);
// allocate host memory to store the input data
mem_size = sizeof( float) * num_elements;
//h_data = (float*) malloc( mem_size);
hipHostMalloc(&h_data, mem_size, hipHostMallocDefault);
// initialize the input data on the host
for( unsigned int i = 0; i < num_elements; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = 0.0f;
}
for( unsigned int i = 0; i < tmp_size; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = (int)(rand() % MAX_RAND)*2 - 1;
}
break;
}
getLogBlockSize(BLOCK_SIZE);
hipEvent_t time_start;
hipEvent_t time_end;
hipEventCreate(&time_start);
hipEventCreate(&time_end);
// compute reference solution
float* reference = (float*) malloc( mem_size);
hipEventRecord(time_start, 0);
computeGold( reference, h_data, num_elements);
hipEventRecord(time_end, 0);
hipEventSynchronize(time_end);
hipEventElapsedTime(&host_time, time_start, time_end);
printf("\n\n**===-------------------------------------------------===**\n");
printf("Processing %d elements...\n", num_elements);
printf("Host CPU Processing time: %f (ms)\n", host_time);
// allocate device memory input and output arrays
float* d_idata = NULL;
float* d_odata = NULL;
hipMalloc( (void**) &d_idata, mem_size);
hipMalloc( (void**) &d_odata, mem_size);
// **===-------- Allocate data structure here -----------===**
// preallocBlockSums(num_elements);
// **===-----------------------------------------------------------===**
// Run just once to remove startup overhead for more accurate performance
// measurement
prescanArray(d_idata, 16);
// Run the prescan
hipMemcpy( d_idata, h_data, mem_size, hipMemcpyHostToDevice);
hipEventRecord(time_start, 0);
// **===-------- Modify the body of this function -----------===**
prescanArray(d_idata, num_elements);
// **===-----------------------------------------------------------===**
hipDeviceSynchronize();
hipEventRecord(time_end, 0);
hipEventSynchronize(time_end);
hipEventElapsedTime(&device_time, time_start, time_end);
// copy result from device to host
hipMemcpy( h_data, d_idata, sizeof(float) * compare_size,
hipMemcpyDeviceToHost);
printf("CUDA Processing time: %f (ms)\n", device_time);
printf("Speedup: %fX\n", host_time/device_time);
// **===-------- Deallocate data structure here -----------===**
// deallocBlockSums();
// **===-----------------------------------------------------------===**
// Check if the result is equivalent to the expected soluion
unsigned int result_regtest = cutComparef( reference, h_data, compare_size, 1e-6);
printf( "Test %s\n", (1 == result_regtest) ? "PASSED" : "FAILED");
// cleanup memory
hipHostFree(h_data);
free( reference);
hipFree( d_odata);
hipFree( d_idata);
printf("------------------------------------------------------\n\n");
}
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err) {
int i;
int diff_count = 0;
for (i = 0; i < num_elements; i++) {
float diff = fabs(reference[i] - h_data[i]);
float denominator = 1.f;
if (denominator < fabs(reference[i])) {
denominator = fabs(reference[i]);
}
if (i % 1000000 == 0) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
}
if (!(diff / denominator < err)) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
getchar();
diff_count ++;
}
}
if (diff_count > 0) {
printf("Number of difference: %d\n", diff_count);
return 0;
} else {
return 1;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright 1993-2006 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws.
*
* This software and the information contained herein is PROPRIETARY and
* CONFIDENTIAL to NVIDIA and is being provided under the terms and
* conditions of a Non-Disclosure Agreement. Any reproduction or
* disclosure to any third party without the express written consent of
* NVIDIA is prohibited.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*/
#ifdef _WIN32
# define NOMINMAX
#endif
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
// You can use any other block size you wish.
#define BLOCK_SIZE 256
#define DEFAULT_NUM_ELEMENTS 16777216
#define MAX_RAND 2
int LOG_BLOCK_SIZE;
void getLogBlockSize(int block_size) {
for(LOG_BLOCK_SIZE = 1;LOG_BLOCK_SIZE < 31; LOG_BLOCK_SIZE++) {
if((1<<LOG_BLOCK_SIZE) >= block_size)
return;
}
fprintf(stderr, "The size requested might be too large!\n");
exit(-1);
}
__global__ void kernel_reduction(float *inArray, int numElements, int stride, int numRest) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
__shared__ float idata[(BLOCK_SIZE << 1)+256];
int copyIdx = stride * ((idx << 1) + 1) - 1;
int copyToIdx = tid<<1;
copyToIdx += (copyToIdx>>4);
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx+1] = idata[copyToIdx] + inArray[copyIdx + stride];
__syncthreads();
int localStride = 2;
for(numRest>>=1;numRest > 1; numRest >>= 1, localStride <<= 1) {
if((tid<<1) < numRest) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
int idxTwo = idxOne - localStride;
idxOne += (idxOne >> 4);
idxTwo += (idxTwo >> 4);
idata[idxOne] += idata[idxTwo];
}
__syncthreads();
}
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+stride] = idata[copyToIdx+1];
}
__global__ void kernel_downtraverse(float *inArray, int numElements, int startStride, int LOG_BLOCK_SIZE) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
int finalStride = (startStride >> LOG_BLOCK_SIZE);
if(finalStride <= 0)
finalStride = 1;
if((startStride << 1) == numElements) {
__shared__ float idata[(BLOCK_SIZE<<1)+256];
int copyIdx = finalStride * ((idx << 1) + 1) - 1;
int copyToIdx = (tid<<1);
copyToIdx += (copyToIdx>>4);
if(copyIdx < numElements){
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx + 1] = inArray[copyIdx+finalStride];
}
__syncthreads();
int localStride = blockDim.x;
while(localStride >= 1) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
if(idxOne < (blockDim.x<<1)) {
int idxTwo = idxOne - localStride;
idxOne += (idxOne>>4);
idxTwo += (idxTwo>>4);
float tmp = idata[idxOne] + idata[idxTwo];
idata[idxTwo] = idata[idxOne];
idata[idxOne] = tmp;
}
localStride >>= 1;
__syncthreads();
}
if(copyIdx < numElements) {
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+finalStride] = idata[copyToIdx+1];
}
}
else {
int stride = startStride;
int idxOne = (stride << 1) * (idx + 1) - 1;
if(idxOne < numElements) {
int idxTwo = idxOne - stride;
float tmp = inArray[idxOne] + inArray[idxTwo];
inArray[idxTwo] = inArray[idxOne];
inArray[idxOne] = tmp;
}
}
}
// **===-------- Modify the body of this function -----------===**
// You may need to make multiple kernel calls.
void prescanArray(float *inArray, int numElements)
{
unsigned numRests = numElements;
int stride = 1;
while(numRests > 1) {
unsigned threads = numRests / 2;
unsigned gridX = 1, gridY = 1;
if(threads > BLOCK_SIZE) {
gridX = threads / BLOCK_SIZE;
threads = BLOCK_SIZE;
if(gridX > 32768) {
gridY = gridX / 32768;
gridX = 32768;
}
}
dim3 grids(gridX, gridY);
kernel_reduction<<<grids,threads>>>(inArray, numElements, stride, numRests > (2*BLOCK_SIZE)? (2*BLOCK_SIZE) : numRests);
stride <<= (LOG_BLOCK_SIZE + 1);
numRests >>= (LOG_BLOCK_SIZE + 1);
}
/*
cudaMemcpy(tmpArray, inArray, 10*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0;i<10;i++)
printf("%f\n", tmpArray[i]);
*/
float tmpNum = 0.0f;
hipMemcpy(inArray + numElements - 1, &tmpNum, sizeof(float), hipMemcpyHostToDevice);
unsigned threads = BLOCK_SIZE;
unsigned gridX = 1, gridY = 1;
if(threads >= (numElements>>1)) {
threads = (numElements>>1);
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, threads, LOG_BLOCK_SIZE);
}
else {
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, numElements>>1, LOG_BLOCK_SIZE);
int stride = numElements >> (LOG_BLOCK_SIZE + 2);
while(stride>0) {
gridX <<= 1;
if(gridX > 32768) {
gridX >>= 1;
gridY <<= 1;
}
dim3 grids2(gridX, gridY);
kernel_downtraverse<<<grids2, threads>>>(inArray, numElements, stride, LOG_BLOCK_SIZE);
stride>>=1;
}
}
}
// **===-----------------------------------------------------------===**
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
extern "C"
unsigned int compare( const float* reference, const float* data,
const unsigned int len);
extern "C"
void computeGold( float* reference, float* idata, const unsigned int len);
unsigned getSmallestPower2(unsigned);
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err);
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
runTest( argc, argv);
return EXIT_SUCCESS;
}
////////////////////////////////////////////////////////////////////////////////
// Get the power of 2 which is the least of the all powers that are not smaller
// than the given number
////////////////////////////////////////////////////////////////////////////////
int getSmallestPower2(int num) {
int result = 1;
while(result < num && result > 0)
result <<= 1;
if(result <= 0 || num <= 0) {
fprintf(stderr, "The size requested might be two large!\n");
exit(-1);
}
return result;
}
////////////////////////////////////////////////////////////////////////////////
//! Run a scan test for CUDA
////////////////////////////////////////////////////////////////////////////////
void
runTest( int argc, char** argv)
{
float device_time;
float host_time;
int num_elements = 0; // Must support large, non-power-of-2 arrays
int compare_size = 0;
// allocate host memory to store the input data
unsigned int mem_size = sizeof( float) * num_elements;
float* h_data = NULL;
// * No arguments: Randomly generate input data and compare against the
// host's result.
// * One argument: Randomly generate input data and write the result to
// file name specified by first argument
// * Two arguments: Read the first argument which indicates the size of the array,
// randomly generate input data and write the input data
// to the second argument. (for generating random input data)
// * Three arguments: Read the first file which indicate the size of the array,
// then input data from the file name specified by 2nd argument and write the
// SCAN output to file name specified by the 3rd argument.
switch(argc-1)
{
default: // No Arguments or one argument
// initialize the input data on the host to be integer values
// between 0 and 1000
// Use DEFAULT_NUM_ELEMENTS num_elements
if(argc <= 1)
compare_size = num_elements = DEFAULT_NUM_ELEMENTS;
else
compare_size = num_elements = atoi(argv[1]);
int tmp_size = num_elements;
num_elements = getSmallestPower2(num_elements);
// allocate host memory to store the input data
mem_size = sizeof( float) * num_elements;
//h_data = (float*) malloc( mem_size);
hipHostMalloc(&h_data, mem_size, hipHostMallocDefault);
// initialize the input data on the host
for( unsigned int i = 0; i < num_elements; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = 0.0f;
}
for( unsigned int i = 0; i < tmp_size; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = (int)(rand() % MAX_RAND)*2 - 1;
}
break;
}
getLogBlockSize(BLOCK_SIZE);
hipEvent_t time_start;
hipEvent_t time_end;
hipEventCreate(&time_start);
hipEventCreate(&time_end);
// compute reference solution
float* reference = (float*) malloc( mem_size);
hipEventRecord(time_start, 0);
computeGold( reference, h_data, num_elements);
hipEventRecord(time_end, 0);
hipEventSynchronize(time_end);
hipEventElapsedTime(&host_time, time_start, time_end);
printf("\n\n**===-------------------------------------------------===**\n");
printf("Processing %d elements...\n", num_elements);
printf("Host CPU Processing time: %f (ms)\n", host_time);
// allocate device memory input and output arrays
float* d_idata = NULL;
float* d_odata = NULL;
hipMalloc( (void**) &d_idata, mem_size);
hipMalloc( (void**) &d_odata, mem_size);
// **===-------- Allocate data structure here -----------===**
// preallocBlockSums(num_elements);
// **===-----------------------------------------------------------===**
// Run just once to remove startup overhead for more accurate performance
// measurement
prescanArray(d_idata, 16);
// Run the prescan
hipMemcpy( d_idata, h_data, mem_size, hipMemcpyHostToDevice);
hipEventRecord(time_start, 0);
// **===-------- Modify the body of this function -----------===**
prescanArray(d_idata, num_elements);
// **===-----------------------------------------------------------===**
hipDeviceSynchronize();
hipEventRecord(time_end, 0);
hipEventSynchronize(time_end);
hipEventElapsedTime(&device_time, time_start, time_end);
// copy result from device to host
hipMemcpy( h_data, d_idata, sizeof(float) * compare_size,
hipMemcpyDeviceToHost);
printf("CUDA Processing time: %f (ms)\n", device_time);
printf("Speedup: %fX\n", host_time/device_time);
// **===-------- Deallocate data structure here -----------===**
// deallocBlockSums();
// **===-----------------------------------------------------------===**
// Check if the result is equivalent to the expected soluion
unsigned int result_regtest = cutComparef( reference, h_data, compare_size, 1e-6);
printf( "Test %s\n", (1 == result_regtest) ? "PASSED" : "FAILED");
// cleanup memory
hipHostFree(h_data);
free( reference);
hipFree( d_odata);
hipFree( d_idata);
printf("------------------------------------------------------\n\n");
}
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err) {
int i;
int diff_count = 0;
for (i = 0; i < num_elements; i++) {
float diff = fabs(reference[i] - h_data[i]);
float denominator = 1.f;
if (denominator < fabs(reference[i])) {
denominator = fabs(reference[i]);
}
if (i % 1000000 == 0) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
}
if (!(diff / denominator < err)) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
getchar();
diff_count ++;
}
}
if (diff_count > 0) {
printf("Number of difference: %d\n", diff_count);
return 0;
} else {
return 1;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kernel_reductionPfiii
.globl _Z16kernel_reductionPfiii
.p2align 8
.type _Z16kernel_reductionPfiii,@function
_Z16kernel_reductionPfiii:
s_clause 0x3
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
v_lshrrev_b32_e32 v5, 3, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_lshl_or_b32 v3, v1, 1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s2, -1
v_add_nc_u32_e32 v3, s2, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_ashr_i32 s1, s3, 1
s_mov_b32 s0, 2
s_clause 0x1
global_load_b32 v8, v[1:2], off
global_load_b32 v7, v[3:4], off
v_lshlrev_b32_e32 v6, 1, v0
s_cmp_lt_i32 s1, 2
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v5, v6, v5, 2
v_add_nc_u32_e32 v7, 4, v5
ds_store_2addr_b32 v5, v8, v9 offset1:1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
v_lshl_add_u32 v0, v0, 1, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_lshr_b32 s2, s1, 1
s_lshl_b32 s0, s0, 1
s_cmp_gt_u32 s1, 3
s_mov_b32 s1, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s1, v6
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[8:9], null, v0, s0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s0, v8
v_ashrrev_i32_e32 v11, 4, v8
v_ashrrev_i32_e32 v10, 4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_lshl_u32 v8, v11, v8, 2
v_add_lshl_u32 v9, v10, v9, 2
ds_load_b32 v9, v9
ds_load_b32 v10, v8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v9, v9, v10
ds_store_b32 v8, v9
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v0, v5
ds_load_b32 v5, v7
s_waitcnt lgkmcnt(1)
global_store_b32 v[1:2], v0, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kernel_reductionPfiii
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16kernel_reductionPfiii, .Lfunc_end0-_Z16kernel_reductionPfiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19kernel_downtraversePfiii
.globl _Z19kernel_downtraversePfiii
.p2align 8
.type _Z19kernel_downtraversePfiii,@function
_Z19kernel_downtraversePfiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s8, -1
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_lshl_b32 s2, s7, 1
s_cmp_lg_u32 s2, s6
s_cbranch_scc0 .LBB1_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, v1, s[2:3]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s6, v2
s_cbranch_execz .LBB1_3
v_add_nc_u32_e32 v2, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s7, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v6, v7
s_clause 0x1
global_store_b32 v[4:5], v6, off
global_store_b32 v[2:3], v7, off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s8, 0
.LBB1_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB1_14
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshl_or_b32 v1, v1, 1, 1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s0, s7, s0
s_max_i32 s1, s0, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v1, s1
v_lshrrev_b32_e32 v1, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v3, v0, 1, v1
v_add_nc_u32_e32 v1, -1, v2
v_cmp_ge_i32_e32 vcc_lo, s6, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s1, v1
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v4
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
s_clause 0x1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v3
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v5, v2, v4 offset1:1
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_eq_u32 s3, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_12
v_lshl_add_u32 v0, v0, 1, 2
s_lshl_b32 s2, s3, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_10
.p2align 6
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s6
s_lshr_b32 s0, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_12
.LBB1_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v0, s3, -1
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB1_9
v_subrev_nc_u32_e32 v4, s3, v2
v_lshrrev_b32_e32 v5, 4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 4, v4
v_add_lshl_u32 v2, v5, v2, 2
s_delay_alu instid0(VALU_DEP_2)
v_add_lshl_u32 v4, v6, v4, 2
ds_load_b32 v5, v2
ds_load_b32 v6, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v5, v6
ds_store_b32 v4, v5
ds_store_b32 v2, v6
s_branch .LBB1_9
.LBB1_12:
s_set_inst_prefetch_distance 0x2
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_14
v_lshlrev_b32_e32 v0, 2, v3
v_add_nc_u32_e32 v3, s1, v1
v_ashrrev_i32_e32 v2, 31, v1
ds_load_2addr_b32 v[5:6], v0 offset1:1
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v6, off
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19kernel_downtraversePfiii
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19kernel_downtraversePfiii, .Lfunc_end1-_Z19kernel_downtraversePfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kernel_reductionPfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16kernel_reductionPfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19kernel_downtraversePfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19kernel_downtraversePfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 1993-2006 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws.
*
* This software and the information contained herein is PROPRIETARY and
* CONFIDENTIAL to NVIDIA and is being provided under the terms and
* conditions of a Non-Disclosure Agreement. Any reproduction or
* disclosure to any third party without the express written consent of
* NVIDIA is prohibited.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*/
#ifdef _WIN32
# define NOMINMAX
#endif
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
// You can use any other block size you wish.
#define BLOCK_SIZE 256
#define DEFAULT_NUM_ELEMENTS 16777216
#define MAX_RAND 2
int LOG_BLOCK_SIZE;
void getLogBlockSize(int block_size) {
for(LOG_BLOCK_SIZE = 1;LOG_BLOCK_SIZE < 31; LOG_BLOCK_SIZE++) {
if((1<<LOG_BLOCK_SIZE) >= block_size)
return;
}
fprintf(stderr, "The size requested might be too large!\n");
exit(-1);
}
__global__ void kernel_reduction(float *inArray, int numElements, int stride, int numRest) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
__shared__ float idata[(BLOCK_SIZE << 1)+256];
int copyIdx = stride * ((idx << 1) + 1) - 1;
int copyToIdx = tid<<1;
copyToIdx += (copyToIdx>>4);
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx+1] = idata[copyToIdx] + inArray[copyIdx + stride];
__syncthreads();
int localStride = 2;
for(numRest>>=1;numRest > 1; numRest >>= 1, localStride <<= 1) {
if((tid<<1) < numRest) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
int idxTwo = idxOne - localStride;
idxOne += (idxOne >> 4);
idxTwo += (idxTwo >> 4);
idata[idxOne] += idata[idxTwo];
}
__syncthreads();
}
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+stride] = idata[copyToIdx+1];
}
__global__ void kernel_downtraverse(float *inArray, int numElements, int startStride, int LOG_BLOCK_SIZE) {
int tid = threadIdx.x;
int bidx = blockIdx.x, bidy = blockIdx.y;
int idx = tid + blockDim.x * bidx + blockDim.x * gridDim.x * bidy;
int finalStride = (startStride >> LOG_BLOCK_SIZE);
if(finalStride <= 0)
finalStride = 1;
if((startStride << 1) == numElements) {
__shared__ float idata[(BLOCK_SIZE<<1)+256];
int copyIdx = finalStride * ((idx << 1) + 1) - 1;
int copyToIdx = (tid<<1);
copyToIdx += (copyToIdx>>4);
if(copyIdx < numElements){
idata[copyToIdx] = inArray[copyIdx];
idata[copyToIdx + 1] = inArray[copyIdx+finalStride];
}
__syncthreads();
int localStride = blockDim.x;
while(localStride >= 1) {
int idxOne = (localStride << 1) * (tid + 1) - 1;
if(idxOne < (blockDim.x<<1)) {
int idxTwo = idxOne - localStride;
idxOne += (idxOne>>4);
idxTwo += (idxTwo>>4);
float tmp = idata[idxOne] + idata[idxTwo];
idata[idxTwo] = idata[idxOne];
idata[idxOne] = tmp;
}
localStride >>= 1;
__syncthreads();
}
if(copyIdx < numElements) {
inArray[copyIdx] = idata[copyToIdx];
inArray[copyIdx+finalStride] = idata[copyToIdx+1];
}
}
else {
int stride = startStride;
int idxOne = (stride << 1) * (idx + 1) - 1;
if(idxOne < numElements) {
int idxTwo = idxOne - stride;
float tmp = inArray[idxOne] + inArray[idxTwo];
inArray[idxTwo] = inArray[idxOne];
inArray[idxOne] = tmp;
}
}
}
// **===-------- Modify the body of this function -----------===**
// You may need to make multiple kernel calls.
void prescanArray(float *inArray, int numElements)
{
unsigned numRests = numElements;
int stride = 1;
while(numRests > 1) {
unsigned threads = numRests / 2;
unsigned gridX = 1, gridY = 1;
if(threads > BLOCK_SIZE) {
gridX = threads / BLOCK_SIZE;
threads = BLOCK_SIZE;
if(gridX > 32768) {
gridY = gridX / 32768;
gridX = 32768;
}
}
dim3 grids(gridX, gridY);
kernel_reduction<<<grids,threads>>>(inArray, numElements, stride, numRests > (2*BLOCK_SIZE)? (2*BLOCK_SIZE) : numRests);
stride <<= (LOG_BLOCK_SIZE + 1);
numRests >>= (LOG_BLOCK_SIZE + 1);
}
/*
cudaMemcpy(tmpArray, inArray, 10*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0;i<10;i++)
printf("%f\n", tmpArray[i]);
*/
float tmpNum = 0.0f;
hipMemcpy(inArray + numElements - 1, &tmpNum, sizeof(float), hipMemcpyHostToDevice);
unsigned threads = BLOCK_SIZE;
unsigned gridX = 1, gridY = 1;
if(threads >= (numElements>>1)) {
threads = (numElements>>1);
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, threads, LOG_BLOCK_SIZE);
}
else {
dim3 grids(gridX, gridY);
kernel_downtraverse<<<grids, threads>>>(inArray, numElements, numElements>>1, LOG_BLOCK_SIZE);
int stride = numElements >> (LOG_BLOCK_SIZE + 2);
while(stride>0) {
gridX <<= 1;
if(gridX > 32768) {
gridX >>= 1;
gridY <<= 1;
}
dim3 grids2(gridX, gridY);
kernel_downtraverse<<<grids2, threads>>>(inArray, numElements, stride, LOG_BLOCK_SIZE);
stride>>=1;
}
}
}
// **===-----------------------------------------------------------===**
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
extern "C"
unsigned int compare( const float* reference, const float* data,
const unsigned int len);
extern "C"
void computeGold( float* reference, float* idata, const unsigned int len);
unsigned getSmallestPower2(unsigned);
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err);
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
runTest( argc, argv);
return EXIT_SUCCESS;
}
////////////////////////////////////////////////////////////////////////////////
// Get the power of 2 which is the least of the all powers that are not smaller
// than the given number
////////////////////////////////////////////////////////////////////////////////
int getSmallestPower2(int num) {
int result = 1;
while(result < num && result > 0)
result <<= 1;
if(result <= 0 || num <= 0) {
fprintf(stderr, "The size requested might be two large!\n");
exit(-1);
}
return result;
}
////////////////////////////////////////////////////////////////////////////////
//! Run a scan test for CUDA
////////////////////////////////////////////////////////////////////////////////
void
runTest( int argc, char** argv)
{
float device_time;
float host_time;
int num_elements = 0; // Must support large, non-power-of-2 arrays
int compare_size = 0;
// allocate host memory to store the input data
unsigned int mem_size = sizeof( float) * num_elements;
float* h_data = NULL;
// * No arguments: Randomly generate input data and compare against the
// host's result.
// * One argument: Randomly generate input data and write the result to
// file name specified by first argument
// * Two arguments: Read the first argument which indicates the size of the array,
// randomly generate input data and write the input data
// to the second argument. (for generating random input data)
// * Three arguments: Read the first file which indicate the size of the array,
// then input data from the file name specified by 2nd argument and write the
// SCAN output to file name specified by the 3rd argument.
switch(argc-1)
{
default: // No Arguments or one argument
// initialize the input data on the host to be integer values
// between 0 and 1000
// Use DEFAULT_NUM_ELEMENTS num_elements
if(argc <= 1)
compare_size = num_elements = DEFAULT_NUM_ELEMENTS;
else
compare_size = num_elements = atoi(argv[1]);
int tmp_size = num_elements;
num_elements = getSmallestPower2(num_elements);
// allocate host memory to store the input data
mem_size = sizeof( float) * num_elements;
//h_data = (float*) malloc( mem_size);
hipHostMalloc(&h_data, mem_size, hipHostMallocDefault);
// initialize the input data on the host
for( unsigned int i = 0; i < num_elements; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = 0.0f;
}
for( unsigned int i = 0; i < tmp_size; ++i)
{
// h_data[i] = 1.0f;
h_data[i] = (int)(rand() % MAX_RAND)*2 - 1;
}
break;
}
getLogBlockSize(BLOCK_SIZE);
hipEvent_t time_start;
hipEvent_t time_end;
hipEventCreate(&time_start);
hipEventCreate(&time_end);
// compute reference solution
float* reference = (float*) malloc( mem_size);
hipEventRecord(time_start, 0);
computeGold( reference, h_data, num_elements);
hipEventRecord(time_end, 0);
hipEventSynchronize(time_end);
hipEventElapsedTime(&host_time, time_start, time_end);
printf("\n\n**===-------------------------------------------------===**\n");
printf("Processing %d elements...\n", num_elements);
printf("Host CPU Processing time: %f (ms)\n", host_time);
// allocate device memory input and output arrays
float* d_idata = NULL;
float* d_odata = NULL;
hipMalloc( (void**) &d_idata, mem_size);
hipMalloc( (void**) &d_odata, mem_size);
// **===-------- Allocate data structure here -----------===**
// preallocBlockSums(num_elements);
// **===-----------------------------------------------------------===**
// Run just once to remove startup overhead for more accurate performance
// measurement
prescanArray(d_idata, 16);
// Run the prescan
hipMemcpy( d_idata, h_data, mem_size, hipMemcpyHostToDevice);
hipEventRecord(time_start, 0);
// **===-------- Modify the body of this function -----------===**
prescanArray(d_idata, num_elements);
// **===-----------------------------------------------------------===**
hipDeviceSynchronize();
hipEventRecord(time_end, 0);
hipEventSynchronize(time_end);
hipEventElapsedTime(&device_time, time_start, time_end);
// copy result from device to host
hipMemcpy( h_data, d_idata, sizeof(float) * compare_size,
hipMemcpyDeviceToHost);
printf("CUDA Processing time: %f (ms)\n", device_time);
printf("Speedup: %fX\n", host_time/device_time);
// **===-------- Deallocate data structure here -----------===**
// deallocBlockSums();
// **===-----------------------------------------------------------===**
// Check if the result is equivalent to the expected soluion
unsigned int result_regtest = cutComparef( reference, h_data, compare_size, 1e-6);
printf( "Test %s\n", (1 == result_regtest) ? "PASSED" : "FAILED");
// cleanup memory
hipHostFree(h_data);
free( reference);
hipFree( d_odata);
hipFree( d_idata);
printf("------------------------------------------------------\n\n");
}
unsigned int cutComparef( float *reference, float *h_data, int num_elements, float err) {
int i;
int diff_count = 0;
for (i = 0; i < num_elements; i++) {
float diff = fabs(reference[i] - h_data[i]);
float denominator = 1.f;
if (denominator < fabs(reference[i])) {
denominator = fabs(reference[i]);
}
if (i % 1000000 == 0) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
}
if (!(diff / denominator < err)) {
//printf("Diff at %d: %g %g\n", i, diff, diff / denominator);
getchar();
diff_count ++;
}
}
if (diff_count > 0) {
printf("Number of difference: %d\n", diff_count);
return 0;
} else {
return 1;
}
} | .text
.file "scan_largearray.hip"
.globl _Z15getLogBlockSizei # -- Begin function _Z15getLogBlockSizei
.p2align 4, 0x90
.type _Z15getLogBlockSizei,@function
_Z15getLogBlockSizei: # @_Z15getLogBlockSizei
.cfi_startproc
# %bb.0:
movl $1, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1, %eax
shll %cl, %eax
cmpl %edi, %eax
jge .LBB0_4
# %bb.2: # in Loop: Header=BB0_1 Depth=1
incl %ecx
cmpl $31, %ecx
jne .LBB0_1
# %bb.3:
pushq %rax
.cfi_def_cfa_offset 16
movl $31, LOG_BLOCK_SIZE(%rip)
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $39, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.LBB0_4:
.cfi_def_cfa_offset 8
movl %ecx, LOG_BLOCK_SIZE(%rip)
retq
.Lfunc_end0:
.size _Z15getLogBlockSizei, .Lfunc_end0-_Z15getLogBlockSizei
.cfi_endproc
# -- End function
.globl _Z31__device_stub__kernel_reductionPfiii # -- Begin function _Z31__device_stub__kernel_reductionPfiii
.p2align 4, 0x90
.type _Z31__device_stub__kernel_reductionPfiii,@function
_Z31__device_stub__kernel_reductionPfiii: # @_Z31__device_stub__kernel_reductionPfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16kernel_reductionPfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z31__device_stub__kernel_reductionPfiii, .Lfunc_end1-_Z31__device_stub__kernel_reductionPfiii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__kernel_downtraversePfiii # -- Begin function _Z34__device_stub__kernel_downtraversePfiii
.p2align 4, 0x90
.type _Z34__device_stub__kernel_downtraversePfiii,@function
_Z34__device_stub__kernel_downtraversePfiii: # @_Z34__device_stub__kernel_downtraversePfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19kernel_downtraversePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z34__device_stub__kernel_downtraversePfiii, .Lfunc_end2-_Z34__device_stub__kernel_downtraversePfiii
.cfi_endproc
# -- End function
.globl _Z12prescanArrayPfi # -- Begin function _Z12prescanArrayPfi
.p2align 4, 0x90
.type _Z12prescanArrayPfi,@function
_Z12prescanArrayPfi: # @_Z12prescanArrayPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r12d
movq %rdi, %r14
movabsq $4294967296, %r15 # imm = 0x100000000
cmpl $2, %esi
jb .LBB3_8
# %bb.1: # %.lr.ph
movl $32768, %r13d # imm = 0x8000
movl %r12d, %ebx
movl $1, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # in Loop: Header=BB3_2 Depth=1
movzbl LOG_BLOCK_SIZE(%rip), %ecx
incb %cl
shll %cl, %ebp
shrl %cl, %ebx
cmpl $1, %ebx
jbe .LBB3_8
.LBB3_2: # =>This Inner Loop Header: Depth=1
cmpl $514, %ebx # imm = 0x202
jb .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=1
movl %ebx, %ecx
shrl $9, %ecx
movl %ebx, %edi
shrl $24, %edi
cmpl $16777728, %ebx # imm = 0x1000200
movl $1, %eax
cmovbl %eax, %edi
cmovael %r13d, %ecx
movl $256, %eax # imm = 0x100
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_3: # in Loop: Header=BB3_2 Depth=1
movl %ebx, %eax
shrl %eax
movl $1, %edi
movl $1, %ecx
.LBB3_5: # in Loop: Header=BB3_2 Depth=1
movl %ecx, %ecx
shlq $32, %rdi
orq %rcx, %rdi
movl %eax, %edx
orq %r15, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6: # in Loop: Header=BB3_2 Depth=1
cmpl $512, %ebx # imm = 0x200
movl $512, %eax # imm = 0x200
cmovbl %ebx, %eax
movq %r14, 72(%rsp)
movl %r12d, 20(%rsp)
movl %ebp, 16(%rsp)
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z16kernel_reductionPfiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_7
.LBB3_8: # %._crit_edge
movl $0, 116(%rsp)
movslq %r12d, %rax
leaq (%r14,%rax,4), %rdi
addq $-4, %rdi
leaq 116(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %ebx
sarl %ebx
cmpl $256, %ebx # imm = 0x100
ja .LBB3_11
# %bb.9:
movl %ebx, %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_18
# %bb.10:
movl LOG_BLOCK_SIZE(%rip), %eax
movq %r14, 72(%rsp)
movl %r12d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19kernel_downtraversePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_18
.LBB3_11:
leaq 1(%r15), %rdi
addq $256, %r15 # imm = 0x100
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12:
movl LOG_BLOCK_SIZE(%rip), %eax
movq %r14, 72(%rsp)
movl %r12d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19kernel_downtraversePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13:
movzbl LOG_BLOCK_SIZE(%rip), %ecx
addb $2, %cl
movl %r12d, %r13d
sarl %cl, %r13d
testl %r13d, %r13d
jle .LBB3_18
# %bb.14: # %.lr.ph128
movl $1, %ebp
movl $1, %ebx
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_15 Depth=1
movl %r13d, %eax
shrl %eax
cmpl $1, %r13d
movl %eax, %r13d
jbe .LBB3_18
.LBB3_15: # =>This Inner Loop Header: Depth=1
leal (,%rbp,2), %eax
andl $2147483647, %ebp # imm = 0x7FFFFFFF
cmpl $32769, %eax # imm = 0x8001
setae %cl
cmovbl %eax, %ebp
shll %cl, %ebx
movq %rbx, %rdi
shlq $32, %rdi
orq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_15 Depth=1
movl LOG_BLOCK_SIZE(%rip), %eax
movq %r14, 72(%rsp)
movl %r12d, 20(%rsp)
movl %r13d, 16(%rsp)
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z19kernel_downtraversePfiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_17
.LBB3_18: # %.loopexit
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12prescanArrayPfi, .Lfunc_end3-_Z12prescanArrayPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z7runTestiPPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z7runTestiPPc
.LCPI5_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_1:
.long 0x3f800000 # float 1
.LCPI5_2:
.long 0x358637bd # float 9.99999997E-7
.text
.globl _Z7runTestiPPc
.p2align 4, 0x90
.type _Z7runTestiPPc,@function
_Z7runTestiPPc: # @_Z7runTestiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 8(%rsp)
movl $16777216, %ebx # imm = 0x1000000
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB5_2:
movl $1, %eax
.p2align 4, 0x90
.LBB5_3: # =>This Inner Loop Header: Depth=1
movl %eax, %r12d
cmpl %ebx, %eax
jge .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=1
leal (%r12,%r12), %eax
testl %r12d, %r12d
jg .LBB5_3
.LBB5_5:
testl %ebx, %ebx
jle .LBB5_18
# %bb.6:
testl %r12d, %r12d
jle .LBB5_18
# %bb.7: # %_Z17getSmallestPower2i.exit
leal (,%r12,4), %r13d
leaq 8(%rsp), %rdi
xorl %r14d, %r14d
movq %r13, %rsi
xorl %edx, %edx
callq hipHostMalloc
movq 8(%rsp), %rdi
movl %r12d, %edx
shlq $2, %rdx
xorl %esi, %esi
callq memset@PLT
movl %ebx, %ebp
.p2align 4, 0x90
.LBB5_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $2147483646, %ecx # imm = 0x7FFFFFFE
subl %ecx, %eax
leal -1(,%rax,2), %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB5_8
# %bb.9: # %_Z15getLogBlockSizei.exit
movl $8, LOG_BLOCK_SIZE(%rip)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq 40(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movq %r14, %rdi
movl %r12d, %edx
callq computeGold
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq $0, 16(%rsp)
movq $0, 48(%rsp)
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movl $16, %esi
callq _Z12prescanArrayPfi
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
movl %r12d, %esi
callq _Z12prescanArrayPfi
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movslq %ebx, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 36(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
testl %ebx, %ebx
jle .LBB5_14
# %bb.10: # %.lr.ph.preheader.i
movq 8(%rsp), %rbx
xorl %r12d, %r12d
movaps .LCPI5_0(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movss .LCPI5_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI5_2(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
xorl %r15d, %r15d
jmp .LBB5_11
.p2align 4, 0x90
.LBB5_13: # in Loop: Header=BB5_11 Depth=1
incq %r12
cmpq %r12, %rbp
je .LBB5_14
.LBB5_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss (%rbx,%r12,4), %xmm1
andps %xmm2, %xmm1
andps %xmm2, %xmm0
maxss %xmm3, %xmm0
divss %xmm0, %xmm1
ucomiss %xmm1, %xmm4
ja .LBB5_13
# %bb.12: # in Loop: Header=BB5_11 Depth=1
movq stdin(%rip), %rdi
callq getc
movss .LCPI5_2(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI5_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps .LCPI5_0(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
incl %r15d
jmp .LBB5_13
.LBB5_14: # %._crit_edge.i
testl %r15d, %r15d
jle .LBB5_15
# %bb.16:
movl $.L.str.11, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.9, %esi
jmp .LBB5_17
.LBB5_15:
movl $.L.str.8, %esi
.LBB5_17: # %_Z11cutComparefPfS_if.exit
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipHostFree
movq %r14, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_18:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $39, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end5:
.size _Z7runTestiPPc, .Lfunc_end5-_Z7runTestiPPc
.cfi_endproc
# -- End function
.globl _Z17getSmallestPower2i # -- Begin function _Z17getSmallestPower2i
.p2align 4, 0x90
.type _Z17getSmallestPower2i,@function
_Z17getSmallestPower2i: # @_Z17getSmallestPower2i
.cfi_startproc
# %bb.0:
movl $1, %ecx
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
movl %ecx, %eax
cmpl %edi, %ecx
jge .LBB6_3
# %bb.2: # in Loop: Header=BB6_1 Depth=1
leal (%rax,%rax), %ecx
testl %eax, %eax
jg .LBB6_1
.LBB6_3:
testl %edi, %edi
jle .LBB6_6
# %bb.4:
testl %eax, %eax
jle .LBB6_6
# %bb.5:
# kill: def $eax killed $eax killed $rax
retq
.LBB6_6:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $39, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end6:
.size _Z17getSmallestPower2i, .Lfunc_end6-_Z17getSmallestPower2i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11cutComparefPfS_if
.LCPI7_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI7_1:
.long 0x3f800000 # float 1
.text
.globl _Z11cutComparefPfS_if
.p2align 4, 0x90
.type _Z11cutComparefPfS_if,@function
_Z11cutComparefPfS_if: # @_Z11cutComparefPfS_if
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edx, %edx
jle .LBB7_1
# %bb.2: # %.lr.ph.preheader
movq %rsi, %r14
movq %rdi, %r15
movl %edx, %r12d
xorl %r13d, %r13d
movaps .LCPI7_0(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI7_1(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
xorl %ebx, %ebx
movss %xmm0, 4(%rsp) # 4-byte Spill
jmp .LBB7_3
.p2align 4, 0x90
.LBB7_5: # in Loop: Header=BB7_3 Depth=1
incq %r13
cmpq %r13, %r12
je .LBB7_6
.LBB7_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm1
subss (%r14,%r13,4), %xmm1
andps %xmm3, %xmm1
andps %xmm3, %xmm2
maxss %xmm4, %xmm2
divss %xmm2, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB7_5
# %bb.4: # in Loop: Header=BB7_3 Depth=1
movq stdin(%rip), %rdi
callq getc
movss .LCPI7_1(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movaps .LCPI7_0(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
incl %ebx
jmp .LBB7_5
.LBB7_1:
xorl %ebx, %ebx
.LBB7_6: # %._crit_edge
testl %ebx, %ebx
jle .LBB7_7
# %bb.8:
xorl %ebp, %ebp
movl $.L.str.11, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
jmp .LBB7_9
.LBB7_7:
movl $1, %ebp
.LBB7_9:
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z11cutComparefPfS_if, .Lfunc_end7-_Z11cutComparefPfS_if
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernel_reductionPfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19kernel_downtraversePfiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type LOG_BLOCK_SIZE,@object # @LOG_BLOCK_SIZE
.bss
.globl LOG_BLOCK_SIZE
.p2align 2, 0x0
LOG_BLOCK_SIZE:
.long 0 # 0x0
.size LOG_BLOCK_SIZE, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The size requested might be too large!\n"
.size .L.str, 40
.type _Z16kernel_reductionPfiii,@object # @_Z16kernel_reductionPfiii
.section .rodata,"a",@progbits
.globl _Z16kernel_reductionPfiii
.p2align 3, 0x0
_Z16kernel_reductionPfiii:
.quad _Z31__device_stub__kernel_reductionPfiii
.size _Z16kernel_reductionPfiii, 8
.type _Z19kernel_downtraversePfiii,@object # @_Z19kernel_downtraversePfiii
.globl _Z19kernel_downtraversePfiii
.p2align 3, 0x0
_Z19kernel_downtraversePfiii:
.quad _Z34__device_stub__kernel_downtraversePfiii
.size _Z19kernel_downtraversePfiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "The size requested might be two large!\n"
.size .L.str.1, 40
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Processing %d elements...\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Host CPU Processing time: %f (ms)\n"
.size .L.str.4, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA Processing time: %f (ms)\n"
.size .L.str.5, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Speedup: %fX\n"
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Test %s\n"
.size .L.str.7, 9
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "PASSED"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "FAILED"
.size .L.str.9, 7
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Number of difference: %d\n"
.size .L.str.11, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16kernel_reductionPfiii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19kernel_downtraversePfiii"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\n**===-------------------------------------------------===**"
.size .Lstr, 62
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "------------------------------------------------------\n"
.size .Lstr.1, 56
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kernel_reductionPfiii
.addrsig_sym _Z34__device_stub__kernel_downtraversePfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kernel_reductionPfiii
.addrsig_sym _Z19kernel_downtraversePfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19kernel_downtraversePfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.SHL.U32 R3, R4, 0x2, RZ ; /* 0x0000000204037824 */
/* 0x000fc600078e00ff */
/*0070*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e640000002100 */
/*0080*/ ISETP.NE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f05270 */
/*0090*/ IMAD R2, R2, c[0x0][0xc], R5 ; /* 0x0000030002027a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x002fd000078e0207 */
/*00b0*/ @!P0 BRA 0x1b0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fca0007ffe0ff */
/*00d0*/ IMAD R2, R3, R2, RZ ; /* 0x0000000203027224 */
/* 0x000fca00078e02ff */
/*00e0*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f04270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0120*/ IADD3 R4, R2.reuse, -c[0x0][0x16c], RZ ; /* 0x80005b0002047a10 */
/* 0x040fe20007ffe0ff */
/*0130*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0150*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee8000c1e1900 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe2000c101904 */
/*0180*/ FADD R9, R0, R7 ; /* 0x0000000700097221 */
/* 0x008fca0000000000 */
/*0190*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ SHF.R.S32.HI R3, RZ, c[0x0][0x170], R4 ; /* 0x00005c00ff037a19 */
/* 0x000fe20000011404 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA R2, R2, 0x1, 0x1 ; /* 0x0000000102027811 */
/* 0x000fe400078e08ff */
/*01e0*/ IMNMX R5, R3, 0x1, !PT ; /* 0x0000000103057817 */
/* 0x000fca0007800200 */
/*01f0*/ IMAD R2, R5, R2, RZ ; /* 0x0000000205027224 */
/* 0x000fca00078e02ff */
/*0200*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*0210*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc60003f04270 */
/*0220*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0204 */
/*0230*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fc800078e0202 */
/*0240*/ @!P0 LDG.E R8, [R2.64] ; /* 0x0000000402088981 */
/* 0x000ea8000c1e1900 */
/*0250*/ @!P0 LDG.E R10, [R4.64] ; /* 0x00000004040a8981 */
/* 0x000ee2000c1e1900 */
/*0260*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD.SHL.U32 R6, R7, 0x2, RZ ; /* 0x0000000207067824 */
/* 0x000fc600078e00ff */
/*0280*/ ISETP.GE.AND P1, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe40003f26270 */
/*0290*/ LEA.HI.SX32 R7, R6, R6, 0x1c ; /* 0x0000000606077211 */
/* 0x000fca00078fe2ff */
/*02a0*/ @!P0 STS [R7.X4], R8 ; /* 0x0000000807008388 */
/* 0x0041e80000004800 */
/*02b0*/ @!P0 STS [R7.X4+0x4], R10 ; /* 0x0000040a07008388 */
/* 0x0081e80000004800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ @!P1 BRA 0x3e0 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R9, R6, 0x2, RZ ; /* 0x0000000206097810 */
/* 0x001fe20007ffe0ff */
/*02f0*/ IMAD.SHL.U32 R6, R11, 0x2, RZ ; /* 0x000000020b067824 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD R11, R9, R0, -0x1 ; /* 0xffffffff090b7424 */
/* 0x000fca00078e0200 */
/*0310*/ ISETP.GE.U32.AND P1, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x000fda0003f26070 */
/*0320*/ @!P1 IADD3 R8, R11.reuse, -R0, RZ ; /* 0x800000000b089210 */
/* 0x040fe40007ffe0ff */
/*0330*/ @!P1 LEA.HI.SX32 R10, R11, R11, 0x1c ; /* 0x0000000b0b0a9211 */
/* 0x000fe400078fe2ff */
/*0340*/ @!P1 LEA.HI.SX32 R8, R8, R8, 0x1c ; /* 0x0000000808089211 */
/* 0x000fe400078fe2ff */
/*0350*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011600 */
/*0360*/ @!P1 LDS R12, [R10.X4] ; /* 0x000000000a0c9984 */
/* 0x000e280000004800 */
/*0370*/ @!P1 LDS R11, [R8.X4] ; /* 0x00000000080b9984 */
/* 0x000e680000004800 */
/*0380*/ @!P1 STS [R8.X4], R12 ; /* 0x0000000c08009388 */
/* 0x0011e20000004800 */
/*0390*/ @!P1 FADD R11, R11, R12 ; /* 0x0000000c0b0b9221 */
/* 0x002fca0000000000 */
/*03a0*/ @!P1 STS [R10.X4], R11 ; /* 0x0000000b0a009388 */
/* 0x0001e80000004800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*03d0*/ @P1 BRA 0x300 ; /* 0xffffff2000001947 */
/* 0x001fea000383ffff */
/*03e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*03f0*/ LDS R9, [R7.X4] ; /* 0x0000000007097984 */
/* 0x000e280000004800 */
/*0400*/ LDS R11, [R7.X4+0x4] ; /* 0x00000400070b7984 */
/* 0x000e680000004800 */
/*0410*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x001fe8000c101904 */
/*0420*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x002fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16kernel_reductionPfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fe200078e0203 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0209 */
/*0090*/ LEA R0, R0, 0x1, 0x1 ; /* 0x0000000100007811 */
/* 0x000fca00078e08ff */
/*00a0*/ IMAD R0, R0, R5, -0x1 ; /* 0xffffffff00007424 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.SHL.U32 R0, R9, 0x2, RZ ; /* 0x0000000209007824 */
/* 0x000fca00078e00ff */
/*0100*/ LEA.HI.SX32 R6, R0, R0, 0x1c ; /* 0x0000000000067211 */
/* 0x000fe200078fe2ff */
/*0110*/ FADD R9, R7, R8 ; /* 0x0000000807097221 */
/* 0x004fe20000000000 */
/*0120*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fc80000000f00 */
/*0130*/ ISETP.GE.AND P0, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f06270 */
/*0140*/ STS [R6.X4], R7 ; /* 0x0000000706007388 */
/* 0x0001e80000004800 */
/*0150*/ STS [R6.X4+0x4], R9 ; /* 0x0000040906007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P0 BRA 0x2e0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x001fe200078e00ff */
/*0190*/ IADD3 R12, R0, 0x2, RZ ; /* 0x00000002000c7810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ UMOV UR4, 0x2 ; /* 0x0000000200047882 */
/* 0x000fc60000000000 */
/*01b0*/ SHF.R.S32.HI R11, RZ, 0x1, R7 ; /* 0x00000001ff0b7819 */
/* 0x000fe20000011407 */
/*01c0*/ BSSY B0, 0x290 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fda0003f06270 */
/*01e0*/ @P0 BRA 0x280 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*01f0*/ IMAD R8, R12, UR4, RZ ; /* 0x000000040c087c24 */
/* 0x000fca000f8e02ff */
/*0200*/ IADD3 R9, R8, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x000fc80007ffe0ff */
/*0210*/ IADD3 R10, R9.reuse, -UR4, RZ ; /* 0x80000004090a7c10 */
/* 0x040fe4000fffe0ff */
/*0220*/ LEA.HI.SX32 R8, R9, R8, 0x1c ; /* 0x0000000809087211 */
/* 0x000fe400078fe2ff */
/*0230*/ LEA.HI.SX32 R10, R10, R10, 0x1c ; /* 0x0000000a0a0a7211 */
/* 0x000fc600078fe2ff */
/*0240*/ LDS R9, [R8.X4+-0x4] ; /* 0xfffffc0008097984 */
/* 0x000fe80000004800 */
/*0250*/ LDS R10, [R10.X4] ; /* 0x000000000a0a7984 */
/* 0x000e240000004800 */
/*0260*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x001fca0000000000 */
/*0270*/ STS [R8.X4+-0x4], R9 ; /* 0xfffffc0908007388 */
/* 0x0001e40000004800 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GT.AND P0, PT, R7, 0x7, PT ; /* 0x000000070700780c */
/* 0x000fe20003f04270 */
/*02b0*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*02c0*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fd60000000f00 */
/*02d0*/ @P0 BRA 0x1b0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*02e0*/ LDS R7, [R6.X4] ; /* 0x0000000006077984 */
/* 0x001e280000004800 */
/*02f0*/ LDS R9, [R6.X4+0x4] ; /* 0x0000040006097984 */
/* 0x000e680000004800 */
/*0300*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101906 */
/*0310*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101906 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kernel_reductionPfiii
.globl _Z16kernel_reductionPfiii
.p2align 8
.type _Z16kernel_reductionPfiii,@function
_Z16kernel_reductionPfiii:
s_clause 0x3
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
v_lshrrev_b32_e32 v5, 3, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_lshl_or_b32 v3, v1, 1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s2, -1
v_add_nc_u32_e32 v3, s2, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_ashr_i32 s1, s3, 1
s_mov_b32 s0, 2
s_clause 0x1
global_load_b32 v8, v[1:2], off
global_load_b32 v7, v[3:4], off
v_lshlrev_b32_e32 v6, 1, v0
s_cmp_lt_i32 s1, 2
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v5, v6, v5, 2
v_add_nc_u32_e32 v7, 4, v5
ds_store_2addr_b32 v5, v8, v9 offset1:1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
v_lshl_add_u32 v0, v0, 1, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_lshr_b32 s2, s1, 1
s_lshl_b32 s0, s0, 1
s_cmp_gt_u32 s1, 3
s_mov_b32 s1, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s1, v6
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[8:9], null, v0, s0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s0, v8
v_ashrrev_i32_e32 v11, 4, v8
v_ashrrev_i32_e32 v10, 4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_lshl_u32 v8, v11, v8, 2
v_add_lshl_u32 v9, v10, v9, 2
ds_load_b32 v9, v9
ds_load_b32 v10, v8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v9, v9, v10
ds_store_b32 v8, v9
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v0, v5
ds_load_b32 v5, v7
s_waitcnt lgkmcnt(1)
global_store_b32 v[1:2], v0, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kernel_reductionPfiii
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16kernel_reductionPfiii, .Lfunc_end0-_Z16kernel_reductionPfiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19kernel_downtraversePfiii
.globl _Z19kernel_downtraversePfiii
.p2align 8
.type _Z19kernel_downtraversePfiii,@function
_Z19kernel_downtraversePfiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s8, -1
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_lshl_b32 s2, s7, 1
s_cmp_lg_u32 s2, s6
s_cbranch_scc0 .LBB1_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, v1, s[2:3]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s6, v2
s_cbranch_execz .LBB1_3
v_add_nc_u32_e32 v2, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s7, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v6, v7
s_clause 0x1
global_store_b32 v[4:5], v6, off
global_store_b32 v[2:3], v7, off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s8, 0
.LBB1_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB1_14
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshl_or_b32 v1, v1, 1, 1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s0, s7, s0
s_max_i32 s1, s0, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v1, s1
v_lshrrev_b32_e32 v1, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v3, v0, 1, v1
v_add_nc_u32_e32 v1, -1, v2
v_cmp_ge_i32_e32 vcc_lo, s6, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s1, v1
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v4
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
s_clause 0x1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v3
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v5, v2, v4 offset1:1
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_eq_u32 s3, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_12
v_lshl_add_u32 v0, v0, 1, 2
s_lshl_b32 s2, s3, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_10
.p2align 6
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s6
s_lshr_b32 s0, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_12
.LBB1_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v0, s3, -1
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB1_9
v_subrev_nc_u32_e32 v4, s3, v2
v_lshrrev_b32_e32 v5, 4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 4, v4
v_add_lshl_u32 v2, v5, v2, 2
s_delay_alu instid0(VALU_DEP_2)
v_add_lshl_u32 v4, v6, v4, 2
ds_load_b32 v5, v2
ds_load_b32 v6, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v5, v6
ds_store_b32 v4, v5
ds_store_b32 v2, v6
s_branch .LBB1_9
.LBB1_12:
s_set_inst_prefetch_distance 0x2
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_14
v_lshlrev_b32_e32 v0, 2, v3
v_add_nc_u32_e32 v3, s1, v1
v_ashrrev_i32_e32 v2, 31, v1
ds_load_2addr_b32 v[5:6], v0 offset1:1
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v6, off
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19kernel_downtraversePfiii
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19kernel_downtraversePfiii, .Lfunc_end1-_Z19kernel_downtraversePfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kernel_reductionPfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16kernel_reductionPfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19kernel_downtraversePfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19kernel_downtraversePfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001cf4e_00000000-6_scan_largearray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "The size requested might be too large!\n"
.text
.globl _Z15getLogBlockSizei
.type _Z15getLogBlockSizei, @function
_Z15getLogBlockSizei:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %esi
movl $1, %ecx
movl $1, %r8d
movl $1, %r9d
jmp .L7
.L8:
movl %ecx, %edx
.L7:
movl %r8d, %eax
sall %cl, %eax
cmpl %edi, %eax
jge .L13
addl $1, %ecx
movl %r9d, %esi
cmpl $31, %ecx
jne .L8
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $31, LOG_BLOCK_SIZE(%rip)
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L13:
.cfi_def_cfa_offset 8
testb %sil, %sil
movl $1, %eax
cmove %eax, %edx
movl %edx, LOG_BLOCK_SIZE(%rip)
ret
.cfi_endproc
.LFE2057:
.size _Z15getLogBlockSizei, .-_Z15getLogBlockSizei
.section .rodata.str1.8
.align 8
.LC1:
.string "The size requested might be two large!\n"
.text
.globl _Z17getSmallestPower2i
.type _Z17getSmallestPower2i, @function
_Z17getSmallestPower2i:
.LFB2060:
.cfi_startproc
endbr64
cmpl $1, %edi
jle .L20
movl $1, %eax
.L16:
addl %eax, %eax
cmpl %eax, %edi
jle .L15
testl %eax, %eax
jg .L16
.L15:
testl %eax, %eax
jle .L21
testl %edi, %edi
jle .L21
ret
.L20:
movl $1, %eax
jmp .L15
.L21:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z17getSmallestPower2i, .-_Z17getSmallestPower2i
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Number of difference: %d\n"
.text
.globl _Z11cutComparefPfS_if
.type _Z11cutComparefPfS_if, @function
_Z11cutComparefPfS_if:
.LFB2062:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movss %xmm0, 12(%rsp)
testl %edx, %edx
jle .L30
movq %rdi, %rbx
movq %rsi, %rbp
movslq %edx, %rdx
leaq (%rdi,%rdx,4), %r12
movl $0, %r13d
jmp .L29
.L28:
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
je .L34
.L29:
movss (%rbx), %xmm0
movaps %xmm0, %xmm1
subss 0(%rbp), %xmm1
andps .LC3(%rip), %xmm1
andps .LC3(%rip), %xmm0
movss .LC2(%rip), %xmm2
cmpltss %xmm0, %xmm2
andps %xmm2, %xmm0
movss .LC2(%rip), %xmm3
andnps %xmm3, %xmm2
orps %xmm2, %xmm0
divss %xmm0, %xmm1
movss 12(%rsp), %xmm4
comiss %xmm1, %xmm4
ja .L28
movq stdin(%rip), %rdi
call getc@PLT
addl $1, %r13d
jmp .L28
.L34:
movl $1, %eax
testl %r13d, %r13d
jg .L35
.L25:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %r13d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L25
.L30:
movl $1, %eax
jmp .L25
.cfi_endproc
.LFE2062:
.size _Z11cutComparefPfS_if, .-_Z11cutComparefPfS_if
.globl _Z39__device_stub__Z16kernel_reductionPfiiiPfiii
.type _Z39__device_stub__Z16kernel_reductionPfiiiPfiii, @function
_Z39__device_stub__Z16kernel_reductionPfiiiPfiii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16kernel_reductionPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z39__device_stub__Z16kernel_reductionPfiiiPfiii, .-_Z39__device_stub__Z16kernel_reductionPfiiiPfiii
.globl _Z16kernel_reductionPfiii
.type _Z16kernel_reductionPfiii, @function
_Z16kernel_reductionPfiii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16kernel_reductionPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z16kernel_reductionPfiii, .-_Z16kernel_reductionPfiii
.globl _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
.type _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii, @function
_Z42__device_stub__Z19kernel_downtraversePfiiiPfiii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19kernel_downtraversePfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii, .-_Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
.globl _Z19kernel_downtraversePfiii
.type _Z19kernel_downtraversePfiii, @function
_Z19kernel_downtraversePfiii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z19kernel_downtraversePfiii, .-_Z19kernel_downtraversePfiii
.globl _Z12prescanArrayPfi
.type _Z12prescanArrayPfi, @function
_Z12prescanArrayPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %esi
jbe .L53
movl %esi, %ebx
movl $1, %r12d
movl $1, %ebp
jmp .L58
.L54:
cmpl $16777727, %ebx
ja .L56
movl %ebx, %ecx
shrl $9, %ecx
movl %ebp, %edx
movl $256, %eax
.L55:
movl %ecx, 16(%rsp)
movl %edx, 20(%rsp)
movl %ebp, 24(%rsp)
movl %eax, 28(%rsp)
movl %ebp, 32(%rsp)
movl %ebp, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl %ebp, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L57:
movl LOG_BLOCK_SIZE(%rip), %eax
leal 1(%rax), %ecx
sall %cl, %r12d
shrl %cl, %ebx
cmpl $1, %ebx
jbe .L74
.L58:
cmpl $513, %ebx
ja .L54
movl %ebx, %eax
shrl %eax
movl %ebp, %edx
movl %ebp, %ecx
jmp .L55
.L56:
movl %ebx, %edx
shrl $24, %edx
movl $32768, %ecx
movl $256, %eax
jmp .L55
.L73:
movl $512, %ecx
cmpl %ecx, %ebx
cmovbe %ebx, %ecx
movl %r12d, %edx
movl %r13d, %esi
movq %r14, %rdi
call _Z39__device_stub__Z16kernel_reductionPfiiiPfiii
jmp .L57
.L74:
movl $0x00000000, (%rsp)
movq %rsp, %rsi
movslq %r13d, %rax
leaq -4(%r14,%rax,4), %rdi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movl %r13d, %ebx
sarl %ebx
movl %ebx, %eax
cmpl $256, %ebx
jbe .L67
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 4(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L62:
movl LOG_BLOCK_SIZE(%rip), %eax
leal 2(%rax), %ecx
movl %r13d, %ebx
sarl %cl, %ebx
testl %ebx, %ebx
jle .L52
movl $1, %r12d
movl $1, %ebp
jmp .L66
.L77:
movl LOG_BLOCK_SIZE(%rip), %ecx
movl %ebx, %edx
movl %r13d, %esi
movq %r14, %rdi
call _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
jmp .L52
.L75:
movl LOG_BLOCK_SIZE(%rip), %ecx
movl %ebx, %edx
movl %r13d, %esi
movq %r14, %rdi
call _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
jmp .L62
.L69:
movl %eax, %ebp
.L64:
movl %ebp, 16(%rsp)
movl %r12d, 20(%rsp)
movl $1, 24(%rsp)
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L76
.L65:
sarl %ebx
testl %ebx, %ebx
jle .L52
.L66:
leal (%rbp,%rbp), %eax
cmpl $32768, %eax
jbe .L69
addl %r12d, %r12d
jmp .L64
.L76:
movl LOG_BLOCK_SIZE(%rip), %ecx
movl %ebx, %edx
movl %r13d, %esi
movq %r14, %rdi
call _Z42__device_stub__Z19kernel_downtraversePfiiiPfiii
jmp .L65
.L53:
movl $0x00000000, (%rsp)
movq %rsp, %rsi
movslq %r13d, %rax
leaq -4(%rdi,%rax,4), %rdi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movl $0, %eax
movl $0, %ebx
.L67:
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L52:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12prescanArrayPfi, .-_Z12prescanArrayPfi
.section .rodata.str1.1
.LC6:
.string "PASSED"
.LC7:
.string "FAILED"
.section .rodata.str1.8
.align 8
.LC8:
.string "\n\n**===-------------------------------------------------===**\n"
.section .rodata.str1.1
.LC9:
.string "Processing %d elements...\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Host CPU Processing time: %f (ms)\n"
.align 8
.LC11:
.string "CUDA Processing time: %f (ms)\n"
.section .rodata.str1.1
.LC12:
.string "Speedup: %fX\n"
.LC14:
.string "Test %s\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "------------------------------------------------------\n\n"
.text
.globl _Z7runTestiPPc
.type _Z7runTestiPPc, @function
_Z7runTestiPPc:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
cmpl $1, %edi
jg .L95
movl $16777216, %edi
call _Z17getSmallestPower2i
movl %eax, %r12d
leal 0(,%r12,4), %r14d
leaq 16(%rsp), %rdi
movl $0, %edx
movq %r14, %rsi
call cudaHostAlloc@PLT
movl %r12d, %r15d
movl $16777216, %r13d
movl $16777216, %ebp
testl %r12d, %r12d
je .L87
.L86:
movl %r15d, %ecx
salq $2, %rcx
movl $0, %eax
.L82:
movq 16(%rsp), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L82
.L81:
movl %r13d, %ebp
testl %r13d, %r13d
je .L83
.L87:
movl %ebp, %ebp
salq $2, %rbp
movl $0, %ebx
.L84:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
leal -1(%rax,%rax), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L84
.L83:
movl $256, %edi
call _Z15getLogBlockSizei
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call computeGold@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq $0, 40(%rsp)
movq $0, 48(%rsp)
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $16, %esi
movq 40(%rsp), %rdi
call _Z12prescanArrayPfi
movl $1, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %r12d, %esi
movq 40(%rsp), %rdi
call _Z12prescanArrayPfi
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movslq %r13d, %rdx
salq $2, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
divss 8(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC13(%rip), %xmm0
movl %r13d, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call _Z11cutComparefPfS_if
cmpl $1, %eax
leaq .LC7(%rip), %rdx
leaq .LC6(%rip), %rax
cmove %rax, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
movl %eax, %edi
call _Z17getSmallestPower2i
movl %eax, %r12d
leal 0(,%r12,4), %r14d
leaq 16(%rsp), %rdi
movl $0, %edx
movq %r14, %rsi
call cudaHostAlloc@PLT
movl %r12d, %r15d
testl %r12d, %r12d
jne .L86
jmp .L81
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z7runTestiPPc, .-_Z7runTestiPPc
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z7runTestiPPc
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z19kernel_downtraversePfiii"
.LC17:
.string "_Z16kernel_reductionPfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z19kernel_downtraversePfiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernel_reductionPfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl LOG_BLOCK_SIZE
.bss
.align 4
.type LOG_BLOCK_SIZE, @object
.size LOG_BLOCK_SIZE, 4
LOG_BLOCK_SIZE:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC13:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan_largearray.hip"
.globl _Z15getLogBlockSizei # -- Begin function _Z15getLogBlockSizei
.p2align 4, 0x90
.type _Z15getLogBlockSizei,@function
_Z15getLogBlockSizei: # @_Z15getLogBlockSizei
.cfi_startproc
# %bb.0:
movl $1, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1, %eax
shll %cl, %eax
cmpl %edi, %eax
jge .LBB0_4
# %bb.2: # in Loop: Header=BB0_1 Depth=1
incl %ecx
cmpl $31, %ecx
jne .LBB0_1
# %bb.3:
pushq %rax
.cfi_def_cfa_offset 16
movl $31, LOG_BLOCK_SIZE(%rip)
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $39, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.LBB0_4:
.cfi_def_cfa_offset 8
movl %ecx, LOG_BLOCK_SIZE(%rip)
retq
.Lfunc_end0:
.size _Z15getLogBlockSizei, .Lfunc_end0-_Z15getLogBlockSizei
.cfi_endproc
# -- End function
.globl _Z31__device_stub__kernel_reductionPfiii # -- Begin function _Z31__device_stub__kernel_reductionPfiii
.p2align 4, 0x90
.type _Z31__device_stub__kernel_reductionPfiii,@function
_Z31__device_stub__kernel_reductionPfiii: # @_Z31__device_stub__kernel_reductionPfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16kernel_reductionPfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z31__device_stub__kernel_reductionPfiii, .Lfunc_end1-_Z31__device_stub__kernel_reductionPfiii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__kernel_downtraversePfiii # -- Begin function _Z34__device_stub__kernel_downtraversePfiii
.p2align 4, 0x90
.type _Z34__device_stub__kernel_downtraversePfiii,@function
_Z34__device_stub__kernel_downtraversePfiii: # @_Z34__device_stub__kernel_downtraversePfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19kernel_downtraversePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z34__device_stub__kernel_downtraversePfiii, .Lfunc_end2-_Z34__device_stub__kernel_downtraversePfiii
.cfi_endproc
# -- End function
.globl _Z12prescanArrayPfi # -- Begin function _Z12prescanArrayPfi
.p2align 4, 0x90
.type _Z12prescanArrayPfi,@function
_Z12prescanArrayPfi: # @_Z12prescanArrayPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r12d
movq %rdi, %r14
movabsq $4294967296, %r15 # imm = 0x100000000
cmpl $2, %esi
jb .LBB3_8
# %bb.1: # %.lr.ph
movl $32768, %r13d # imm = 0x8000
movl %r12d, %ebx
movl $1, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # in Loop: Header=BB3_2 Depth=1
movzbl LOG_BLOCK_SIZE(%rip), %ecx
incb %cl
shll %cl, %ebp
shrl %cl, %ebx
cmpl $1, %ebx
jbe .LBB3_8
.LBB3_2: # =>This Inner Loop Header: Depth=1
cmpl $514, %ebx # imm = 0x202
jb .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=1
movl %ebx, %ecx
shrl $9, %ecx
movl %ebx, %edi
shrl $24, %edi
cmpl $16777728, %ebx # imm = 0x1000200
movl $1, %eax
cmovbl %eax, %edi
cmovael %r13d, %ecx
movl $256, %eax # imm = 0x100
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_3: # in Loop: Header=BB3_2 Depth=1
movl %ebx, %eax
shrl %eax
movl $1, %edi
movl $1, %ecx
.LBB3_5: # in Loop: Header=BB3_2 Depth=1
movl %ecx, %ecx
shlq $32, %rdi
orq %rcx, %rdi
movl %eax, %edx
orq %r15, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6: # in Loop: Header=BB3_2 Depth=1
cmpl $512, %ebx # imm = 0x200
movl $512, %eax # imm = 0x200
cmovbl %ebx, %eax
movq %r14, 72(%rsp)
movl %r12d, 20(%rsp)
movl %ebp, 16(%rsp)
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z16kernel_reductionPfiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_7
.LBB3_8: # %._crit_edge
movl $0, 116(%rsp)
movslq %r12d, %rax
leaq (%r14,%rax,4), %rdi
addq $-4, %rdi
leaq 116(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %ebx
sarl %ebx
cmpl $256, %ebx # imm = 0x100
ja .LBB3_11
# %bb.9:
movl %ebx, %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_18
# %bb.10:
movl LOG_BLOCK_SIZE(%rip), %eax
movq %r14, 72(%rsp)
movl %r12d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19kernel_downtraversePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_18
.LBB3_11:
leaq 1(%r15), %rdi
addq $256, %r15 # imm = 0x100
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12:
movl LOG_BLOCK_SIZE(%rip), %eax
movq %r14, 72(%rsp)
movl %r12d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19kernel_downtraversePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13:
movzbl LOG_BLOCK_SIZE(%rip), %ecx
addb $2, %cl
movl %r12d, %r13d
sarl %cl, %r13d
testl %r13d, %r13d
jle .LBB3_18
# %bb.14: # %.lr.ph128
movl $1, %ebp
movl $1, %ebx
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_15 Depth=1
movl %r13d, %eax
shrl %eax
cmpl $1, %r13d
movl %eax, %r13d
jbe .LBB3_18
.LBB3_15: # =>This Inner Loop Header: Depth=1
leal (,%rbp,2), %eax
andl $2147483647, %ebp # imm = 0x7FFFFFFF
cmpl $32769, %eax # imm = 0x8001
setae %cl
cmovbl %eax, %ebp
shll %cl, %ebx
movq %rbx, %rdi
shlq $32, %rdi
orq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_15 Depth=1
movl LOG_BLOCK_SIZE(%rip), %eax
movq %r14, 72(%rsp)
movl %r12d, 20(%rsp)
movl %r13d, 16(%rsp)
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z19kernel_downtraversePfiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_17
.LBB3_18: # %.loopexit
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12prescanArrayPfi, .Lfunc_end3-_Z12prescanArrayPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z7runTestiPPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z7runTestiPPc
.LCPI5_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_1:
.long 0x3f800000 # float 1
.LCPI5_2:
.long 0x358637bd # float 9.99999997E-7
.text
.globl _Z7runTestiPPc
.p2align 4, 0x90
.type _Z7runTestiPPc,@function
_Z7runTestiPPc: # @_Z7runTestiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 8(%rsp)
movl $16777216, %ebx # imm = 0x1000000
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB5_2:
movl $1, %eax
.p2align 4, 0x90
.LBB5_3: # =>This Inner Loop Header: Depth=1
movl %eax, %r12d
cmpl %ebx, %eax
jge .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=1
leal (%r12,%r12), %eax
testl %r12d, %r12d
jg .LBB5_3
.LBB5_5:
testl %ebx, %ebx
jle .LBB5_18
# %bb.6:
testl %r12d, %r12d
jle .LBB5_18
# %bb.7: # %_Z17getSmallestPower2i.exit
leal (,%r12,4), %r13d
leaq 8(%rsp), %rdi
xorl %r14d, %r14d
movq %r13, %rsi
xorl %edx, %edx
callq hipHostMalloc
movq 8(%rsp), %rdi
movl %r12d, %edx
shlq $2, %rdx
xorl %esi, %esi
callq memset@PLT
movl %ebx, %ebp
.p2align 4, 0x90
.LBB5_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $2147483646, %ecx # imm = 0x7FFFFFFE
subl %ecx, %eax
leal -1(,%rax,2), %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB5_8
# %bb.9: # %_Z15getLogBlockSizei.exit
movl $8, LOG_BLOCK_SIZE(%rip)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq 40(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movq %r14, %rdi
movl %r12d, %edx
callq computeGold
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq $0, 16(%rsp)
movq $0, 48(%rsp)
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movl $16, %esi
callq _Z12prescanArrayPfi
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
movl %r12d, %esi
callq _Z12prescanArrayPfi
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movslq %ebx, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 36(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
testl %ebx, %ebx
jle .LBB5_14
# %bb.10: # %.lr.ph.preheader.i
movq 8(%rsp), %rbx
xorl %r12d, %r12d
movaps .LCPI5_0(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movss .LCPI5_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI5_2(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
xorl %r15d, %r15d
jmp .LBB5_11
.p2align 4, 0x90
.LBB5_13: # in Loop: Header=BB5_11 Depth=1
incq %r12
cmpq %r12, %rbp
je .LBB5_14
.LBB5_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss (%rbx,%r12,4), %xmm1
andps %xmm2, %xmm1
andps %xmm2, %xmm0
maxss %xmm3, %xmm0
divss %xmm0, %xmm1
ucomiss %xmm1, %xmm4
ja .LBB5_13
# %bb.12: # in Loop: Header=BB5_11 Depth=1
movq stdin(%rip), %rdi
callq getc
movss .LCPI5_2(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI5_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps .LCPI5_0(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
incl %r15d
jmp .LBB5_13
.LBB5_14: # %._crit_edge.i
testl %r15d, %r15d
jle .LBB5_15
# %bb.16:
movl $.L.str.11, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.9, %esi
jmp .LBB5_17
.LBB5_15:
movl $.L.str.8, %esi
.LBB5_17: # %_Z11cutComparefPfS_if.exit
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipHostFree
movq %r14, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_18:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $39, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end5:
.size _Z7runTestiPPc, .Lfunc_end5-_Z7runTestiPPc
.cfi_endproc
# -- End function
.globl _Z17getSmallestPower2i # -- Begin function _Z17getSmallestPower2i
.p2align 4, 0x90
.type _Z17getSmallestPower2i,@function
_Z17getSmallestPower2i: # @_Z17getSmallestPower2i
.cfi_startproc
# %bb.0:
movl $1, %ecx
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
movl %ecx, %eax
cmpl %edi, %ecx
jge .LBB6_3
# %bb.2: # in Loop: Header=BB6_1 Depth=1
leal (%rax,%rax), %ecx
testl %eax, %eax
jg .LBB6_1
.LBB6_3:
testl %edi, %edi
jle .LBB6_6
# %bb.4:
testl %eax, %eax
jle .LBB6_6
# %bb.5:
# kill: def $eax killed $eax killed $rax
retq
.LBB6_6:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $39, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end6:
.size _Z17getSmallestPower2i, .Lfunc_end6-_Z17getSmallestPower2i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11cutComparefPfS_if
.LCPI7_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI7_1:
.long 0x3f800000 # float 1
.text
.globl _Z11cutComparefPfS_if
.p2align 4, 0x90
.type _Z11cutComparefPfS_if,@function
_Z11cutComparefPfS_if: # @_Z11cutComparefPfS_if
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edx, %edx
jle .LBB7_1
# %bb.2: # %.lr.ph.preheader
movq %rsi, %r14
movq %rdi, %r15
movl %edx, %r12d
xorl %r13d, %r13d
movaps .LCPI7_0(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI7_1(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
xorl %ebx, %ebx
movss %xmm0, 4(%rsp) # 4-byte Spill
jmp .LBB7_3
.p2align 4, 0x90
.LBB7_5: # in Loop: Header=BB7_3 Depth=1
incq %r13
cmpq %r13, %r12
je .LBB7_6
.LBB7_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm1
subss (%r14,%r13,4), %xmm1
andps %xmm3, %xmm1
andps %xmm3, %xmm2
maxss %xmm4, %xmm2
divss %xmm2, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB7_5
# %bb.4: # in Loop: Header=BB7_3 Depth=1
movq stdin(%rip), %rdi
callq getc
movss .LCPI7_1(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movaps .LCPI7_0(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
incl %ebx
jmp .LBB7_5
.LBB7_1:
xorl %ebx, %ebx
.LBB7_6: # %._crit_edge
testl %ebx, %ebx
jle .LBB7_7
# %bb.8:
xorl %ebp, %ebp
movl $.L.str.11, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
jmp .LBB7_9
.LBB7_7:
movl $1, %ebp
.LBB7_9:
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z11cutComparefPfS_if, .Lfunc_end7-_Z11cutComparefPfS_if
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernel_reductionPfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19kernel_downtraversePfiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type LOG_BLOCK_SIZE,@object # @LOG_BLOCK_SIZE
.bss
.globl LOG_BLOCK_SIZE
.p2align 2, 0x0
LOG_BLOCK_SIZE:
.long 0 # 0x0
.size LOG_BLOCK_SIZE, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The size requested might be too large!\n"
.size .L.str, 40
.type _Z16kernel_reductionPfiii,@object # @_Z16kernel_reductionPfiii
.section .rodata,"a",@progbits
.globl _Z16kernel_reductionPfiii
.p2align 3, 0x0
_Z16kernel_reductionPfiii:
.quad _Z31__device_stub__kernel_reductionPfiii
.size _Z16kernel_reductionPfiii, 8
.type _Z19kernel_downtraversePfiii,@object # @_Z19kernel_downtraversePfiii
.globl _Z19kernel_downtraversePfiii
.p2align 3, 0x0
_Z19kernel_downtraversePfiii:
.quad _Z34__device_stub__kernel_downtraversePfiii
.size _Z19kernel_downtraversePfiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "The size requested might be two large!\n"
.size .L.str.1, 40
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Processing %d elements...\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Host CPU Processing time: %f (ms)\n"
.size .L.str.4, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA Processing time: %f (ms)\n"
.size .L.str.5, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Speedup: %fX\n"
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Test %s\n"
.size .L.str.7, 9
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "PASSED"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "FAILED"
.size .L.str.9, 7
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Number of difference: %d\n"
.size .L.str.11, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16kernel_reductionPfiii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19kernel_downtraversePfiii"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\n**===-------------------------------------------------===**"
.size .Lstr, 62
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "------------------------------------------------------\n"
.size .Lstr.1, 56
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kernel_reductionPfiii
.addrsig_sym _Z34__device_stub__kernel_downtraversePfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kernel_reductionPfiii
.addrsig_sym _Z19kernel_downtraversePfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void K(int *p) {
*p = 0;
printf("%d\n", *p);
}
int main() {
int *x, *y;
cudaMalloc(&x, sizeof(int));
K<<<2, 10>>>(x);
cudaDeviceSynchronize();
y = x;
cudaFree(y);
K<<<2, 10>>>(x);
cudaDeviceSynchronize();
//cudaError_t err = cudaGetLastError();
//printf("error=%d, %s, %s\n", err, cudaGetErrorName(err), cudaGetErrorString(err));
return 0;
} | code for sm_80
Function : _Z1KPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fca00078e00ff */
/*0010*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ STL [R1], RZ ; /* 0x000000ff01007387 */
/* 0x0001e20000100800 */
/*0070*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0080*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc400078e00ff */
/*00c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*00d0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fcc0000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0130*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0140*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void K(int *p) {
*p = 0;
printf("%d\n", *p);
}
int main() {
int *x, *y;
cudaMalloc(&x, sizeof(int));
K<<<2, 10>>>(x);
cudaDeviceSynchronize();
y = x;
cudaFree(y);
K<<<2, 10>>>(x);
cudaDeviceSynchronize();
//cudaError_t err = cudaGetLastError();
//printf("error=%d, %s, %s\n", err, cudaGetErrorName(err), cudaGetErrorString(err));
return 0;
} | .file "tmpxft_000b67b7_00000000-6_gdb3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z1KPiPi
.type _Z20__device_stub__Z1KPiPi, @function
_Z20__device_stub__Z1KPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1KPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z20__device_stub__Z1KPiPi, .-_Z20__device_stub__Z1KPiPi
.globl _Z1KPi
.type _Z1KPi, @function
_Z1KPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z1KPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z1KPi, .-_Z1KPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z20__device_stub__Z1KPiPi
jmp .L12
.L17:
movq 8(%rsp), %rdi
call _Z20__device_stub__Z1KPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1KPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1KPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
__global__ void K(int *p) {
*p = 0;
printf("%d\n", *p);
}
int main() {
int *x, *y;
cudaMalloc(&x, sizeof(int));
K<<<2, 10>>>(x);
cudaDeviceSynchronize();
y = x;
cudaFree(y);
K<<<2, 10>>>(x);
cudaDeviceSynchronize();
//cudaError_t err = cudaGetLastError();
//printf("error=%d, %s, %s\n", err, cudaGetErrorName(err), cudaGetErrorString(err));
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void K(int *p) {
*p = 0;
printf("%d\n", *p);
}
int main() {
int *x, *y;
hipMalloc(&x, sizeof(int));
K<<<2, 10>>>(x);
hipDeviceSynchronize();
y = x;
hipFree(y);
K<<<2, 10>>>(x);
hipDeviceSynchronize();
//cudaError_t err = cudaGetLastError();
//printf("error=%d, %s, %s\n", err, cudaGetErrorName(err), cudaGetErrorString(err));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void K(int *p) {
*p = 0;
printf("%d\n", *p);
}
int main() {
int *x, *y;
hipMalloc(&x, sizeof(int));
K<<<2, 10>>>(x);
hipDeviceSynchronize();
y = x;
hipFree(y);
K<<<2, 10>>>(x);
hipDeviceSynchronize();
//cudaError_t err = cudaGetLastError();
//printf("error=%d, %s, %s\n", err, cudaGetErrorName(err), cudaGetErrorString(err));
return 0;
} | .text
.file "gdb3.hip"
.globl _Z16__device_stub__KPi # -- Begin function _Z16__device_stub__KPi
.p2align 4, 0x90
.type _Z16__device_stub__KPi,@function
_Z16__device_stub__KPi: # @_Z16__device_stub__KPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z16__device_stub__KPi, .Lfunc_end0-_Z16__device_stub__KPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movabsq $4294967298, %rbx # imm = 0x100000002
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
leaq 8(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1KPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1KPi,@object # @_Z1KPi
.section .rodata,"a",@progbits
.globl _Z1KPi
.p2align 3, 0x0
_Z1KPi:
.quad _Z16__device_stub__KPi
.size _Z1KPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1KPi"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__KPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1KPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b67b7_00000000-6_gdb3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z1KPiPi
.type _Z20__device_stub__Z1KPiPi, @function
_Z20__device_stub__Z1KPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1KPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z20__device_stub__Z1KPiPi, .-_Z20__device_stub__Z1KPiPi
.globl _Z1KPi
.type _Z1KPi, @function
_Z1KPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z1KPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z1KPi, .-_Z1KPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z20__device_stub__Z1KPiPi
jmp .L12
.L17:
movq 8(%rsp), %rdi
call _Z20__device_stub__Z1KPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1KPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1KPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gdb3.hip"
.globl _Z16__device_stub__KPi # -- Begin function _Z16__device_stub__KPi
.p2align 4, 0x90
.type _Z16__device_stub__KPi,@function
_Z16__device_stub__KPi: # @_Z16__device_stub__KPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z16__device_stub__KPi, .Lfunc_end0-_Z16__device_stub__KPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movabsq $4294967298, %rbx # imm = 0x100000002
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
leaq 8(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1KPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1KPi,@object # @_Z1KPi
.section .rodata,"a",@progbits
.globl _Z1KPi
.p2align 3, 0x0
_Z1KPi:
.quad _Z16__device_stub__KPi
.size _Z1KPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1KPi"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__KPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1KPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <math.h>
#include <stdio.h>
#include <cuda_runtime.h>
#define PI 3.141592
/*
* Return number of hyperparameters
*/
__device__ int retNumParams(){
return 4;
}
/*
* Compute the covariance matrix in column oriented vector format using X
* The output matrix is upper triangular
* Output matrix formula k(x,z) = sf^2 * exp( -2*sin^2( pi*||x-z||/p )/ell^2 )
*/
__device__ void covMat(double *X, int nX, double *cM, double *lh){
double l = exp(lh[0]);
double sf2 = exp(2 * lh[1]);
double p = exp(lh[2]);
double sn2 = exp(2 * lh[3]);
int i, j;
for(i = 0; i < nX; i++){
for(j = i; j < nX; j++){
double _int = fabs(X[i] - X[j]);
cM[i + j * nX] = sf2 * exp(-2 * pow(sin((PI * _int) / p), 2) / pow(l, 2));
if(j == i) cM[i + j * nX] += sn2;
}
}
}
/*
* Compute the covariance matrix in column oriented vector format using X
* The output matrix is upper triangular
* Output matrix formula k(x,z) = sf^2 * exp( -2*sin^2( pi*||x-z||/p )/ell^2 )
* same as above except doesn't add sn2 to main diagonal
* Divides all elements by sn2 (when noise is high) and then adds an identity matrix
*/
__device__ void covMatSp(double *X, int nX, double *cM, double *lh){
double l = exp(lh[0]);
double sf2 = exp(2 * lh[1]);
double p = exp(lh[2]);
double sn2 = exp(2 * lh[3]);
for(int i = 0; i < nX; i++)
{
for(int j = i; j < nX; j++)
{
double _int = fabs(X[i] - X[j]);
cM[i + j * nX] = sf2 * exp(-2 * pow(sin((PI * _int) / p), 2) / pow(l, 2)) / sn2;
if (j == i)
{
cM[i + j * nX] += 1;
}
}
}
}
/*
* Compute the derivative of the covariance matrix in column oriented vector format using X with respect to hyperparameter #n
* The output matrix is upper triangular
*/
__device__ void dcovMat(double *X, int nX, double *dcM, double *lh, int n){
double l = exp(lh[0]);
double sf2 = exp(2*lh[1]);
double p = exp(lh[2]);
double sn2 = exp(2*lh[3]);
int i, j;
double tmp100;
for(i = 0; i < nX; i++)
{
for(j = i; j < nX; j++)
{
double _int = fabs(X[i]-X[j]);
switch(n){
case 1://log(l)
dcM[i+j*nX] = (sf2*exp(-2*pow(sin((PI*_int)/p),2)/pow(l,2)))*4*(pow(sin((PI*_int)/p),2)/pow(l,2));
break;
case 2://log(sf)
dcM[i+j*nX] = 2*sf2*exp(-2*pow(sin((PI*_int)/p),2)/pow(l,2));
break;
case 3://log(p)
// dcM[i+j*nX] = sf2*exp(-2*pow(sin((PI*_int)/p),2)/pow(l,2))*(4*sin((PI*_int)/p))*((PI*_int)/(pow(p,2)*pow(l,2)))*(cos((PI*_int)/p));
tmp100 = (PI*_int)/p;
dcM[i+j*nX]= ((sf2*4*tmp100)/(pow(l,2)))*exp((-2*pow(sin(tmp100),2))/pow(l,2))*sin(tmp100)*cos(tmp100);
break;
case 4://log(sn)
if(i == j)
dcM[i+j*nX] = 2*sn2;
else
dcM[i+j*nX] = 0;
break;
default:
return;
}
}
}
}
/*
* Compute element wise cross-covariance matrix between a vector of training observations, X and a vector test observations, Y.
* The output matrix cM is a nX x nY matrix in column oriented format
*/
__device__ void covMatCross(double *X, double *Y, int nX, int nY, double *cM, double *lh){
double l = exp(lh[0]);
double sf2 = exp(2 * lh[1]);
double p = exp(lh[2]);
int i, j;
for(j = 0; j < nY; j++)
{
for(i = 0; i < nX; i++)
{
double _int = fabs(X[i] - Y[j]);
cM[i + j * nX] = sf2 * exp(-2 * pow(sin((PI * _int) / p), 2) / pow(l, 2));
}
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <stdio.h>
#include <cuda_runtime.h>
#define PI 3.141592
/*
* Return number of hyperparameters
*/
__device__ int retNumParams(){
return 4;
}
/*
* Compute the covariance matrix in column oriented vector format using X
* The output matrix is upper triangular
* Output matrix formula k(x,z) = sf^2 * exp( -2*sin^2( pi*||x-z||/p )/ell^2 )
*/
__device__ void covMat(double *X, int nX, double *cM, double *lh){
double l = exp(lh[0]);
double sf2 = exp(2 * lh[1]);
double p = exp(lh[2]);
double sn2 = exp(2 * lh[3]);
int i, j;
for(i = 0; i < nX; i++){
for(j = i; j < nX; j++){
double _int = fabs(X[i] - X[j]);
cM[i + j * nX] = sf2 * exp(-2 * pow(sin((PI * _int) / p), 2) / pow(l, 2));
if(j == i) cM[i + j * nX] += sn2;
}
}
}
/*
* Compute the covariance matrix in column oriented vector format using X
* The output matrix is upper triangular
* Output matrix formula k(x,z) = sf^2 * exp( -2*sin^2( pi*||x-z||/p )/ell^2 )
* same as above except doesn't add sn2 to main diagonal
* Divides all elements by sn2 (when noise is high) and then adds an identity matrix
*/
__device__ void covMatSp(double *X, int nX, double *cM, double *lh){
double l = exp(lh[0]);
double sf2 = exp(2 * lh[1]);
double p = exp(lh[2]);
double sn2 = exp(2 * lh[3]);
for(int i = 0; i < nX; i++)
{
for(int j = i; j < nX; j++)
{
double _int = fabs(X[i] - X[j]);
cM[i + j * nX] = sf2 * exp(-2 * pow(sin((PI * _int) / p), 2) / pow(l, 2)) / sn2;
if (j == i)
{
cM[i + j * nX] += 1;
}
}
}
}
/*
* Compute the derivative of the covariance matrix in column oriented vector format using X with respect to hyperparameter #n
* The output matrix is upper triangular
*/
__device__ void dcovMat(double *X, int nX, double *dcM, double *lh, int n){
double l = exp(lh[0]);
double sf2 = exp(2*lh[1]);
double p = exp(lh[2]);
double sn2 = exp(2*lh[3]);
int i, j;
double tmp100;
for(i = 0; i < nX; i++)
{
for(j = i; j < nX; j++)
{
double _int = fabs(X[i]-X[j]);
switch(n){
case 1://log(l)
dcM[i+j*nX] = (sf2*exp(-2*pow(sin((PI*_int)/p),2)/pow(l,2)))*4*(pow(sin((PI*_int)/p),2)/pow(l,2));
break;
case 2://log(sf)
dcM[i+j*nX] = 2*sf2*exp(-2*pow(sin((PI*_int)/p),2)/pow(l,2));
break;
case 3://log(p)
// dcM[i+j*nX] = sf2*exp(-2*pow(sin((PI*_int)/p),2)/pow(l,2))*(4*sin((PI*_int)/p))*((PI*_int)/(pow(p,2)*pow(l,2)))*(cos((PI*_int)/p));
tmp100 = (PI*_int)/p;
dcM[i+j*nX]= ((sf2*4*tmp100)/(pow(l,2)))*exp((-2*pow(sin(tmp100),2))/pow(l,2))*sin(tmp100)*cos(tmp100);
break;
case 4://log(sn)
if(i == j)
dcM[i+j*nX] = 2*sn2;
else
dcM[i+j*nX] = 0;
break;
default:
return;
}
}
}
}
/*
* Compute element wise cross-covariance matrix between a vector of training observations, X and a vector test observations, Y.
* The output matrix cM is a nX x nY matrix in column oriented format
*/
__device__ void covMatCross(double *X, double *Y, int nX, int nY, double *cM, double *lh){
double l = exp(lh[0]);
double sf2 = exp(2 * lh[1]);
double p = exp(lh[2]);
int i, j;
for(j = 0; j < nY; j++)
{
for(i = 0; i < nX; i++)
{
double _int = fabs(X[i] - Y[j]);
cM[i + j * nX] = sf2 * exp(-2 * pow(sin((PI * _int) / p), 2) / pow(l, 2));
}
}
} | .file "tmpxft_0018386c_00000000-6_covPNoise.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12retNumParamsv
.type _Z12retNumParamsv, @function
_Z12retNumParamsv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z12retNumParamsv, .-_Z12retNumParamsv
.globl _Z6covMatPdiS_S_
.type _Z6covMatPdiS_S_, @function
_Z6covMatPdiS_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z6covMatPdiS_S_, .-_Z6covMatPdiS_S_
.globl _Z8covMatSpPdiS_S_
.type _Z8covMatSpPdiS_S_, @function
_Z8covMatSpPdiS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z8covMatSpPdiS_S_, .-_Z8covMatSpPdiS_S_
.globl _Z7dcovMatPdiS_S_i
.type _Z7dcovMatPdiS_S_i, @function
_Z7dcovMatPdiS_S_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z7dcovMatPdiS_S_i, .-_Z7dcovMatPdiS_S_i
.globl _Z11covMatCrossPdS_iiS_S_
.type _Z11covMatCrossPdS_iiS_S_, @function
_Z11covMatCrossPdS_iiS_S_:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z11covMatCrossPdS_iiS_S_, .-_Z11covMatCrossPdS_iiS_S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdio.h>
#include <cuda_runtime.h>
#define PI 3.141592
/*
* Return number of hyperparameters
*/
__device__ int retNumParams(){
return 4;
}
/*
* Compute the covariance matrix in column oriented vector format using X
* The output matrix is upper triangular
* Output matrix formula k(x,z) = sf^2 * exp( -2*sin^2( pi*||x-z||/p )/ell^2 )
*/
__device__ void covMat(double *X, int nX, double *cM, double *lh){
double l = exp(lh[0]);
double sf2 = exp(2 * lh[1]);
double p = exp(lh[2]);
double sn2 = exp(2 * lh[3]);
int i, j;
for(i = 0; i < nX; i++){
for(j = i; j < nX; j++){
double _int = fabs(X[i] - X[j]);
cM[i + j * nX] = sf2 * exp(-2 * pow(sin((PI * _int) / p), 2) / pow(l, 2));
if(j == i) cM[i + j * nX] += sn2;
}
}
}
/*
* Compute the covariance matrix in column oriented vector format using X
* The output matrix is upper triangular
* Output matrix formula k(x,z) = sf^2 * exp( -2*sin^2( pi*||x-z||/p )/ell^2 )
* same as above except doesn't add sn2 to main diagonal
* Divides all elements by sn2 (when noise is high) and then adds an identity matrix
*/
__device__ void covMatSp(double *X, int nX, double *cM, double *lh){
double l = exp(lh[0]);
double sf2 = exp(2 * lh[1]);
double p = exp(lh[2]);
double sn2 = exp(2 * lh[3]);
for(int i = 0; i < nX; i++)
{
for(int j = i; j < nX; j++)
{
double _int = fabs(X[i] - X[j]);
cM[i + j * nX] = sf2 * exp(-2 * pow(sin((PI * _int) / p), 2) / pow(l, 2)) / sn2;
if (j == i)
{
cM[i + j * nX] += 1;
}
}
}
}
/*
* Compute the derivative of the covariance matrix in column oriented vector format using X with respect to hyperparameter #n
* The output matrix is upper triangular
*/
__device__ void dcovMat(double *X, int nX, double *dcM, double *lh, int n){
double l = exp(lh[0]);
double sf2 = exp(2*lh[1]);
double p = exp(lh[2]);
double sn2 = exp(2*lh[3]);
int i, j;
double tmp100;
for(i = 0; i < nX; i++)
{
for(j = i; j < nX; j++)
{
double _int = fabs(X[i]-X[j]);
switch(n){
case 1://log(l)
dcM[i+j*nX] = (sf2*exp(-2*pow(sin((PI*_int)/p),2)/pow(l,2)))*4*(pow(sin((PI*_int)/p),2)/pow(l,2));
break;
case 2://log(sf)
dcM[i+j*nX] = 2*sf2*exp(-2*pow(sin((PI*_int)/p),2)/pow(l,2));
break;
case 3://log(p)
// dcM[i+j*nX] = sf2*exp(-2*pow(sin((PI*_int)/p),2)/pow(l,2))*(4*sin((PI*_int)/p))*((PI*_int)/(pow(p,2)*pow(l,2)))*(cos((PI*_int)/p));
tmp100 = (PI*_int)/p;
dcM[i+j*nX]= ((sf2*4*tmp100)/(pow(l,2)))*exp((-2*pow(sin(tmp100),2))/pow(l,2))*sin(tmp100)*cos(tmp100);
break;
case 4://log(sn)
if(i == j)
dcM[i+j*nX] = 2*sn2;
else
dcM[i+j*nX] = 0;
break;
default:
return;
}
}
}
}
/*
* Compute element wise cross-covariance matrix between a vector of training observations, X and a vector test observations, Y.
* The output matrix cM is a nX x nY matrix in column oriented format
*/
__device__ void covMatCross(double *X, double *Y, int nX, int nY, double *cM, double *lh){
double l = exp(lh[0]);
double sf2 = exp(2 * lh[1]);
double p = exp(lh[2]);
int i, j;
for(j = 0; j < nY; j++)
{
for(i = 0; i < nX; i++)
{
double _int = fabs(X[i] - Y[j]);
cM[i + j * nX] = sf2 * exp(-2 * pow(sin((PI * _int) / p), 2) / pow(l, 2));
}
}
} | #ifndef COVPNOISE_CUH
#define COVPNOISE_CUH
/* covariance function related routines */
__device__ int retNumParams();
__device__ void covVec(double *X, int nX, double *cV, double *lh);
__device__ void dcovVec(double *X, int nX, double *dcV, double *lh, int n);
__device__ void covMat(double *X, int nX, double *cM, double *lh);
__device__ void covMatSp(double *X, int nX, double *cM, double *lh);
__device__ void dcovMat(double *X, int nX, double *dcM, double *lh, int n);
__device__ void covMatCross(double *X, double *Y, int nX, int nY, double *cM, double *lh);
__device__ void dcovMatCross(double *X, double *Y, int nX, int nY, double *dcM, double *lh, int n);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef COVPNOISE_CUH
#define COVPNOISE_CUH
/* covariance function related routines */
__device__ int retNumParams();
__device__ void covVec(double *X, int nX, double *cV, double *lh);
__device__ void dcovVec(double *X, int nX, double *dcV, double *lh, int n);
__device__ void covMat(double *X, int nX, double *cM, double *lh);
__device__ void covMatSp(double *X, int nX, double *cM, double *lh);
__device__ void dcovMat(double *X, int nX, double *dcM, double *lh, int n);
__device__ void covMatCross(double *X, double *Y, int nX, int nY, double *cM, double *lh);
__device__ void dcovMatCross(double *X, double *Y, int nX, int nY, double *dcM, double *lh, int n);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef COVPNOISE_CUH
#define COVPNOISE_CUH
/* covariance function related routines */
__device__ int retNumParams();
__device__ void covVec(double *X, int nX, double *cV, double *lh);
__device__ void dcovVec(double *X, int nX, double *dcV, double *lh, int n);
__device__ void covMat(double *X, int nX, double *cM, double *lh);
__device__ void covMatSp(double *X, int nX, double *cM, double *lh);
__device__ void dcovMat(double *X, int nX, double *dcM, double *lh, int n);
__device__ void covMatCross(double *X, double *Y, int nX, int nY, double *cM, double *lh);
__device__ void dcovMatCross(double *X, double *Y, int nX, int nY, double *dcM, double *lh, int n);
#endif | .text
.file "covPNoise.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018386c_00000000-6_covPNoise.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12retNumParamsv
.type _Z12retNumParamsv, @function
_Z12retNumParamsv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z12retNumParamsv, .-_Z12retNumParamsv
.globl _Z6covMatPdiS_S_
.type _Z6covMatPdiS_S_, @function
_Z6covMatPdiS_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z6covMatPdiS_S_, .-_Z6covMatPdiS_S_
.globl _Z8covMatSpPdiS_S_
.type _Z8covMatSpPdiS_S_, @function
_Z8covMatSpPdiS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z8covMatSpPdiS_S_, .-_Z8covMatSpPdiS_S_
.globl _Z7dcovMatPdiS_S_i
.type _Z7dcovMatPdiS_S_i, @function
_Z7dcovMatPdiS_S_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z7dcovMatPdiS_S_i, .-_Z7dcovMatPdiS_S_i
.globl _Z11covMatCrossPdS_iiS_S_
.type _Z11covMatCrossPdS_iiS_S_, @function
_Z11covMatCrossPdS_iiS_S_:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z11covMatCrossPdS_iiS_S_, .-_Z11covMatCrossPdS_iiS_S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "covPNoise.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kLogregCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, const int numCases, const int numOut) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
/*
* Compute the probability of guessing the correct case if you take the most-probable label.
*
* This is done like this:
*
* - If the most probable label is not equal to the true label, then the probability is zero.
* - Otherwise, the probability is 1 / (number of labels whose probability is equal to the maximum).
*
* This is certainly overkill -- in practice, it's just about impossible for two labels to get assigned
* maximum probability. But it's a safety measure to prevent over-estimating your accuracy.
* Though it could never happen in reality. Well it could. But it wouldn't. Cool?
*/
if (labelp != maxp) {
correctProbs[tx] = 0;
} else {
int numMax = 0;
for (int i = 0; i < numOut; i++) {
numMax += probs[i * numCases + tx] == maxp;
}
correctProbs[tx] = 1.0f / float(numMax);
}
}
} | code for sm_80
Function : _Z11kLogregCostPfS_S_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R9, R0, 0x80, R3 ; /* 0x0000008000097824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x188], PT ; /* 0x0000620009007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R6, R9, R2, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x000fcc00078e0202 */
/*0090*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ F2I.TRUNC.NTZ R4, R6 ; /* 0x0000000600047305 */
/* 0x004e24000020f100 */
/*00b0*/ IMAD R11, R4, c[0x0][0x188], R9 ; /* 0x00006200040b7a24 */
/* 0x001fc800078e0209 */
/*00c0*/ IMAD.WIDE R10, R11, R2, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fcc00078e0202 */
/*00d0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R4, R9, R2, c[0x0][0x170] ; /* 0x00005c0009047625 */
/* 0x000fcc00078e0202 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*0100*/ IMAD.WIDE R6, R9, R2, c[0x0][0x178] ; /* 0x00005e0009067625 */
/* 0x000fc800078e0202 */
/*0110*/ IMAD.WIDE R16, R9, R2, c[0x0][0x180] ; /* 0x0000600009107625 */
/* 0x000fc800078e0202 */
/*0120*/ FMUL R8, R11.reuse, 16777216 ; /* 0x4b8000000b087820 */
/* 0x044fe20000400000 */
/*0130*/ FSETP.GEU.AND P0, PT, |R11|, 1.175494350822287508e-38, PT ; /* 0x008000000b00780b */
/* 0x000fc80003f0e200 */
/*0140*/ FSEL R8, R8, R11, !P0 ; /* 0x0000000b08087208 */
/* 0x000fc80004000000 */
/*0150*/ MUFU.LG2 R12, R8 ; /* 0x00000008000c7308 */
/* 0x000e2a0000000c00 */
/*0160*/ @!P0 FADD R12, R12, -24 ; /* 0xc1c000000c0c8421 */
/* 0x001fe20000000000 */
/*0170*/ FSETP.NEU.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720b */
/* 0x008fc60003f0d000 */
/*0180*/ FMUL R13, R12, 0.69314718246459960938 ; /* 0x3f3172180c0d7820 */
/* 0x000fca0000400000 */
/*0190*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001ea000c101904 */
/*01a0*/ @P0 BRA 0xea0 ; /* 0x00000cf000000947 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x001fc600078e00ff */
/*01d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 BRA 0xda0 ; /* 0x00000bb000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R6, R5.reuse, -0x1, RZ ; /* 0xffffffff05067810 */
/* 0x040fe20007ffe0ff */
/*0200*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0210*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe200078ec0ff */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0230*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fda0003f06070 */
/*0240*/ @!P0 BRA 0xcb0 ; /* 0x00000a6000008947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R6, -R5, c[0x0][0x18c], RZ ; /* 0x0000630005067a10 */
/* 0x000fe40007ffe1ff */
/*0260*/ SHF.R.S32.HI R8, RZ, 0x1f, R9 ; /* 0x0000001fff087819 */
/* 0x000fe40000011409 */
/*0270*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0280*/ LEA R18, P1, R9, c[0x0][0x160], 0x2 ; /* 0x0000580009127a11 */
/* 0x000fc800078210ff */
/*0290*/ LEA.HI.X R19, R9, c[0x0][0x164], R8, 0x2, P1 ; /* 0x0000590009137a11 */
/* 0x000fe200008f1408 */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*02b0*/ @!P0 BRA 0xb30 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02e0*/ @!P1 BRA 0x840 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0000a2000c1e1900 */
/*0310*/ IMAD.WIDE R22, R2, c[0x0][0x188], R18 ; /* 0x0000620002167a25 */
/* 0x000fca00078e0212 */
/*0320*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x0002e4000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2, c[0x0][0x188], R22 ; /* 0x0000620002167a25 */
/* 0x002fca00078e0216 */
/*0340*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000322000c1e1900 */
/*0350*/ IMAD.WIDE R26, R2, c[0x0][0x188], R22 ; /* 0x00006200021a7a25 */
/* 0x000fca00078e0216 */
/*0360*/ LDG.E R13, [R26.64] ; /* 0x000000041a0d7981 */
/* 0x000b24000c1e1900 */
/*0370*/ IMAD.WIDE R26, R2, c[0x0][0x188], R26 ; /* 0x00006200021a7a25 */
/* 0x020fca00078e021a */
/*0380*/ LDG.E R15, [R26.64] ; /* 0x000000041a0f7981 */
/* 0x000b22000c1e1900 */
/*0390*/ IMAD.WIDE R20, R2, c[0x0][0x188], R26 ; /* 0x0000620002147a25 */
/* 0x000fca00078e021a */
/*03a0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x000322000c1e1900 */
/*03b0*/ IMAD.WIDE R18, R2, c[0x0][0x188], R20 ; /* 0x0000620002127a25 */
/* 0x001fca00078e0214 */
/*03c0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000124000c1e1900 */
/*03d0*/ IMAD.WIDE R18, R2, c[0x0][0x188], R18 ; /* 0x0000620002127a25 */
/* 0x001fca00078e0212 */
/*03e0*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000122000c1e1900 */
/*03f0*/ IMAD.WIDE R20, R2, c[0x0][0x188], R18 ; /* 0x0000620002147a25 */
/* 0x002fca00078e0212 */
/*0400*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000322000c1e1900 */
/*0410*/ IMAD.WIDE R22, R2, c[0x0][0x188], R20 ; /* 0x0000620002167a25 */
/* 0x000fca00078e0214 */
/*0420*/ LDG.E R29, [R22.64] ; /* 0x00000004161d7981 */
/* 0x000124000c1e1900 */
/*0430*/ IMAD.WIDE R22, R2, c[0x0][0x188], R22 ; /* 0x0000620002167a25 */
/* 0x001fca00078e0216 */
/*0440*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x020162000c1e1900 */
/*0450*/ IMAD.WIDE R20, R2, c[0x0][0x188], R22 ; /* 0x0000620002147a25 */
/* 0x002fca00078e0216 */
/*0460*/ LDG.E R25, [R20.64] ; /* 0x0000000414197981 */
/* 0x000362000c1e1900 */
/*0470*/ IMAD.WIDE R18, R2, c[0x0][0x188], R20 ; /* 0x0000620002127a25 */
/* 0x000fca00078e0214 */
/*0480*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000164000c1e1900 */
/*0490*/ IMAD.WIDE R18, R2, c[0x0][0x188], R18 ; /* 0x0000620002127a25 */
/* 0x001fcc00078e0212 */
/*04a0*/ IMAD.WIDE R20, R2, c[0x0][0x188], R18 ; /* 0x0000620002147a25 */
/* 0x002fcc00078e0212 */
/*04b0*/ IMAD.WIDE R22, R2, c[0x0][0x188], R20 ; /* 0x0000620002167a25 */
/* 0x000fe200078e0214 */
/*04c0*/ FSETP.NEU.AND P1, PT, R28, R4, PT ; /* 0x000000041c00720b */
/* 0x004fe40003f2d000 */
/*04d0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0000a4000c1e1900 */
/*04e0*/ IADD3 R18, R7, 0x1, RZ ; /* 0x0000000107127810 */
/* 0x001fd20007ffe0ff */
/*04f0*/ @P1 IMAD.MOV R18, RZ, RZ, R7 ; /* 0x000000ffff121224 */
/* 0x000fe400078e0207 */
/*0500*/ LDG.E R7, [R20.64] ; /* 0x0000000414077981 */
/* 0x000ea2000c1e1900 */
/*0510*/ FSETP.NEU.AND P2, PT, R9, R4, PT ; /* 0x000000040900720b */
/* 0x008fc60003f4d000 */
/*0520*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x000ee2000c1e1900 */
/*0530*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe40007ffe0ff */
/*0540*/ FSETP.NEU.AND P1, PT, R11, R4, PT ; /* 0x000000040b00720b */
/* 0x010fe40003f2d000 */
/*0550*/ IADD3 R11, R18, 0x1, RZ ; /* 0x00000001120b7810 */
/* 0x000fe40007ffe0ff */
/*0560*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc60007ffe0ff */
/*0570*/ @P2 IMAD.MOV R11, RZ, RZ, R18 ; /* 0x000000ffff0b2224 */
/* 0x000fe200078e0212 */
/*0580*/ FSETP.NEU.AND P2, PT, R13, R4, PT ; /* 0x000000040d00720b */
/* 0x000fe20003f4d000 */
/*0590*/ IMAD.WIDE R18, R2, c[0x0][0x188], R22 ; /* 0x0000620002127a25 */
/* 0x000fc600078e0216 */
/*05a0*/ IADD3 R13, R11, 0x1, RZ ; /* 0x000000010b0d7810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ @P1 IMAD.MOV R13, RZ, RZ, R11 ; /* 0x000000ffff0d1224 */
/* 0x000fca00078e020b */
/*05c0*/ IADD3 R11, R13, 0x1, RZ ; /* 0x000000010d0b7810 */
/* 0x000fe40007ffe0ff */
/*05d0*/ FSETP.NEU.AND P1, PT, R15, R4.reuse, PT ; /* 0x000000040f00720b */
/* 0x080fe20003f2d000 */
/*05e0*/ @P2 IMAD.MOV R11, RZ, RZ, R13 ; /* 0x000000ffff0b2224 */
/* 0x000fe200078e020d */
/*05f0*/ FSETP.NEU.AND P2, PT, R24, R4, PT ; /* 0x000000041800720b */
/* 0x000fc80003f4d000 */
/*0600*/ IADD3 R13, R11, 0x1, RZ ; /* 0x000000010b0d7810 */
/* 0x000fce0007ffe0ff */
/*0610*/ @P1 IMAD.MOV R13, RZ, RZ, R11 ; /* 0x000000ffff0d1224 */
/* 0x000fe200078e020b */
/*0620*/ FSETP.NEU.AND P1, PT, R14, R4, PT ; /* 0x000000040e00720b */
/* 0x000fc80003f2d000 */
/*0630*/ IADD3 R11, R13, 0x1, RZ ; /* 0x000000010d0b7810 */
/* 0x000fe20007ffe0ff */
/*0640*/ @P2 IMAD.MOV R11, RZ, RZ, R13 ; /* 0x000000ffff0b2224 */
/* 0x000fe200078e020d */
/*0650*/ FSETP.NEU.AND P2, PT, R12, R4, PT ; /* 0x000000040c00720b */
/* 0x000fc80003f4d000 */
/*0660*/ IADD3 R12, R11, 0x1, RZ ; /* 0x000000010b0c7810 */
/* 0x000fc60007ffe0ff */
/*0670*/ @P1 IMAD.MOV R12, RZ, RZ, R11 ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e020b */
/*0680*/ FSETP.NEU.AND P1, PT, R10, R4, PT ; /* 0x000000040a00720b */
/* 0x000fc80003f2d000 */
/*0690*/ IADD3 R10, R12, 0x1, RZ ; /* 0x000000010c0a7810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ @P2 IMAD.MOV R10, RZ, RZ, R12 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e020c */
/*06b0*/ FSETP.NEU.AND P2, PT, R29, R4, PT ; /* 0x000000041d00720b */
/* 0x000fc80003f4d000 */
/*06c0*/ IADD3 R11, R10, 0x1, RZ ; /* 0x000000010a0b7810 */
/* 0x000fc60007ffe0ff */
/*06d0*/ @P1 IMAD.MOV R11, RZ, RZ, R10 ; /* 0x000000ffff0b1224 */
/* 0x000fca00078e020a */
/*06e0*/ IADD3 R10, R11, 0x1, RZ ; /* 0x000000010b0a7810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ FSETP.NEU.AND P1, PT, R27, R4.reuse, PT ; /* 0x000000041b00720b */
/* 0x0a0fe20003f2d000 */
/*0700*/ @P2 IMAD.MOV R10, RZ, RZ, R11 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e020b */
/*0710*/ FSETP.NEU.AND P2, PT, R25, R4, PT ; /* 0x000000041900720b */
/* 0x000fc80003f4d000 */
/*0720*/ IADD3 R11, R10, 0x1, RZ ; /* 0x000000010a0b7810 */
/* 0x000fce0007ffe0ff */
/*0730*/ @P1 IMAD.MOV R11, RZ, RZ, R10 ; /* 0x000000ffff0b1224 */
/* 0x000fe200078e020a */
/*0740*/ FSETP.NEU.AND P1, PT, R26, R4, PT ; /* 0x000000041a00720b */
/* 0x000fc80003f2d000 */
/*0750*/ IADD3 R10, R11, 0x1, RZ ; /* 0x000000010b0a7810 */
/* 0x000fe20007ffe0ff */
/*0760*/ @P2 IMAD.MOV R10, RZ, RZ, R11 ; /* 0x000000ffff0a2224 */
/* 0x000fca00078e020b */
/*0770*/ IADD3 R11, R10, 0x1, RZ ; /* 0x000000010a0b7810 */
/* 0x000fc60007ffe0ff */
/*0780*/ @P1 IMAD.MOV R11, RZ, RZ, R10 ; /* 0x000000ffff0b1224 */
/* 0x000fe200078e020a */
/*0790*/ FSETP.NEU.AND P2, PT, R28, R4.reuse, PT ; /* 0x000000041c00720b */
/* 0x084fe40003f4d000 */
/*07a0*/ FSETP.NEU.AND P1, PT, R7, R4, PT ; /* 0x000000040700720b */
/* 0x000fe40003f2d000 */
/*07b0*/ IADD3 R7, R11, 0x1, RZ ; /* 0x000000010b077810 */
/* 0x000fd20007ffe0ff */
/*07c0*/ @P2 IMAD.MOV R7, RZ, RZ, R11 ; /* 0x000000ffff072224 */
/* 0x000fe200078e020b */
/*07d0*/ FSETP.NEU.AND P2, PT, R9, R4, PT ; /* 0x000000040900720b */
/* 0x008fc80003f4d000 */
/*07e0*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ @P1 IMAD.MOV R9, RZ, RZ, R7 ; /* 0x000000ffff091224 */
/* 0x000fe200078e0207 */
/*0800*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc80003f24270 */
/*0810*/ IADD3 R7, R9, 0x1, RZ ; /* 0x0000000109077810 */
/* 0x000fc60007ffe0ff */
/*0820*/ @P2 IMAD.MOV R7, RZ, RZ, R9 ; /* 0x000000ffff072224 */
/* 0x000fcc00078e0209 */
/*0830*/ @P1 BRA 0x300 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*0840*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0850*/ @!P1 BRA 0xb10 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0860*/ LDG.E R9, [R18.64] ; /* 0x0000000412097981 */
/* 0x0000a2000c1e1900 */
/*0870*/ IMAD.WIDE R10, R2, c[0x0][0x188], R18 ; /* 0x00006200020a7a25 */
/* 0x000fca00078e0212 */
/*0880*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x0002e2000c1e1900 */
/*0890*/ IMAD.WIDE R26, R2, c[0x0][0x188], R10 ; /* 0x00006200021a7a25 */
/* 0x000fca00078e020a */
/*08a0*/ LDG.E R23, [R26.64] ; /* 0x000000041a177981 */
/* 0x000f22000c1e1900 */
/*08b0*/ IMAD.WIDE R28, R2, c[0x0][0x188], R26 ; /* 0x00006200021c7a25 */
/* 0x000fca00078e021a */
/*08c0*/ LDG.E R25, [R28.64] ; /* 0x000000041c197981 */
/* 0x000f62000c1e1900 */
/*08d0*/ IMAD.WIDE R12, R2, c[0x0][0x188], R28 ; /* 0x00006200020c7a25 */
/* 0x000fca00078e021c */
/*08e0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000362000c1e1900 */
/*08f0*/ IMAD.WIDE R14, R2, c[0x0][0x188], R12 ; /* 0x00006200020e7a25 */
/* 0x000fca00078e020c */
/*0900*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f62000c1e1900 */
/*0910*/ IMAD.WIDE R18, R2, c[0x0][0x188], R14 ; /* 0x0000620002127a25 */
/* 0x001fca00078e020e */
/*0920*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000162000c1e1900 */
/*0930*/ IMAD.WIDE R10, R2, c[0x0][0x188], R18 ; /* 0x00006200020a7a25 */
/* 0x002fca00078e0212 */
/*0940*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */
/* 0x000f62000c1e1900 */
/*0950*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007ffe0ff */
/*0960*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0970*/ IMAD.WIDE R18, R2, c[0x0][0x188], R10 ; /* 0x0000620002127a25 */
/* 0x001fe200078e020a */
/*0980*/ FSETP.NEU.AND P0, PT, R9, R4.reuse, PT ; /* 0x000000040900720b */
/* 0x084fe40003f0d000 */
/*0990*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ FSETP.NEU.AND P1, PT, R21, R4, PT ; /* 0x000000041500720b */
/* 0x008fd20003f2d000 */
/*09b0*/ @P0 IMAD.MOV R9, RZ, RZ, R7 ; /* 0x000000ffff090224 */
/* 0x000fe200078e0207 */
/*09c0*/ FSETP.NEU.AND P0, PT, R23, R4, PT ; /* 0x000000041700720b */
/* 0x010fc80003f0d000 */
/*09d0*/ IADD3 R7, R9, 0x1, RZ ; /* 0x0000000109077810 */
/* 0x000fe20007ffe0ff */
/*09e0*/ @P1 IMAD.MOV R7, RZ, RZ, R9 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0209 */
/*09f0*/ FSETP.NEU.AND P1, PT, R25, R4, PT ; /* 0x000000041900720b */
/* 0x020fc80003f2d000 */
/*0a00*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fc60007ffe0ff */
/*0a10*/ @P0 IMAD.MOV R9, RZ, RZ, R7 ; /* 0x000000ffff090224 */
/* 0x000fe200078e0207 */
/*0a20*/ FSETP.NEU.AND P0, PT, R20, R4, PT ; /* 0x000000041400720b */
/* 0x000fc80003f0d000 */
/*0a30*/ IADD3 R7, R9, 0x1, RZ ; /* 0x0000000109077810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ @P1 IMAD.MOV R7, RZ, RZ, R9 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0209 */
/*0a50*/ FSETP.NEU.AND P1, PT, R22, R4, PT ; /* 0x000000041600720b */
/* 0x000fc80003f2d000 */
/*0a60*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fc60007ffe0ff */
/*0a70*/ @P0 IMAD.MOV R9, RZ, RZ, R7 ; /* 0x000000ffff090224 */
/* 0x000fe200078e0207 */
/*0a80*/ FSETP.NEU.AND P0, PT, R24, R4, PT ; /* 0x000000041800720b */
/* 0x000fc80003f0d000 */
/*0a90*/ IADD3 R7, R9, 0x1, RZ ; /* 0x0000000109077810 */
/* 0x000fe20007ffe0ff */
/*0aa0*/ @P1 IMAD.MOV R7, RZ, RZ, R9 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0209 */
/*0ab0*/ FSETP.NEU.AND P1, PT, R13, R4, PT ; /* 0x000000040d00720b */
/* 0x000fc80003f2d000 */
/*0ac0*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fc60007ffe0ff */
/*0ad0*/ @P0 IMAD.MOV R9, RZ, RZ, R7 ; /* 0x000000ffff090224 */
/* 0x000fe200078e0207 */
/*0ae0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0af0*/ IADD3 R7, R9, 0x1, RZ ; /* 0x0000000109077810 */
/* 0x000fe20007ffe0ff */
/*0b00*/ @P1 IMAD.MOV R7, RZ, RZ, R9 ; /* 0x000000ffff071224 */
/* 0x000fe400078e0209 */
/*0b10*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0b20*/ @!P0 BRA 0xcb0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0b30*/ LDG.E R9, [R18.64] ; /* 0x0000000412097981 */
/* 0x0000a2000c1e1900 */
/*0b40*/ IMAD.WIDE R12, R2, c[0x0][0x188], R18 ; /* 0x00006200020c7a25 */
/* 0x000fca00078e0212 */
/*0b50*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ee2000c1e1900 */
/*0b60*/ IMAD.WIDE R14, R2, c[0x0][0x188], R12 ; /* 0x00006200020e7a25 */
/* 0x000fca00078e020c */
/*0b70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f22000c1e1900 */
/*0b80*/ IMAD.WIDE R10, R2, c[0x0][0x188], R14 ; /* 0x00006200020a7a25 */
/* 0x000fca00078e020e */
/*0b90*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000f62000c1e1900 */
/*0ba0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0bb0*/ IMAD.WIDE R18, R2, c[0x0][0x188], R10 ; /* 0x0000620002127a25 */
/* 0x001fe200078e020a */
/*0bc0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ FSETP.NEU.AND P0, PT, R9, R4.reuse, PT ; /* 0x000000040900720b */
/* 0x084fe40003f0d000 */
/*0be0*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ FSETP.NEU.AND P1, PT, R21, R4, PT ; /* 0x000000041500720b */
/* 0x008fd20003f2d000 */
/*0c00*/ @P0 IMAD.MOV R9, RZ, RZ, R7 ; /* 0x000000ffff090224 */
/* 0x000fe200078e0207 */
/*0c10*/ FSETP.NEU.AND P0, PT, R23, R4, PT ; /* 0x000000041700720b */
/* 0x010fc80003f0d000 */
/*0c20*/ IADD3 R7, R9, 0x1, RZ ; /* 0x0000000109077810 */
/* 0x000fe20007ffe0ff */
/*0c30*/ @P1 IMAD.MOV R7, RZ, RZ, R9 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0209 */
/*0c40*/ FSETP.NEU.AND P1, PT, R25, R4, PT ; /* 0x000000041900720b */
/* 0x020fc80003f2d000 */
/*0c50*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ @P0 IMAD.MOV R9, RZ, RZ, R7 ; /* 0x000000ffff090224 */
/* 0x000fe200078e0207 */
/*0c70*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*0c80*/ IADD3 R7, R9, 0x1, RZ ; /* 0x0000000109077810 */
/* 0x000fe20007ffe0ff */
/*0c90*/ @P1 IMAD.MOV R7, RZ, RZ, R9 ; /* 0x000000ffff071224 */
/* 0x000fd000078e0209 */
/*0ca0*/ @P0 BRA 0xb30 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 BRA 0xd90 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0cd0*/ IMAD R3, R8, c[0x0][0x188], R3 ; /* 0x0000620008037a24 */
/* 0x000fc800078e0203 */
/*0ce0*/ IMAD R3, R0, 0x80, R3 ; /* 0x0000008000037824 */
/* 0x000fc800078e0203 */
/*0cf0*/ IMAD.WIDE R8, R3, R2, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fca00078e0202 */
/*0d00*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000a2000c1e1900 */
/*0d10*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0d20*/ IADD3 R0, R7, 0x1, RZ ; /* 0x0000000107007810 */
/* 0x000fe40007ffe0ff */
/*0d30*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f25270 */
/*0d40*/ IMAD.WIDE R8, R2, c[0x0][0x188], R8 ; /* 0x0000620002087a25 */
/* 0x001fe200078e0208 */
/*0d50*/ FSETP.NEU.AND P0, PT, R3, R4, PT ; /* 0x000000040300720b */
/* 0x004fda0003f0d000 */
/*0d60*/ @P0 IMAD.MOV R0, RZ, RZ, R7 ; /* 0x000000ffff000224 */
/* 0x000fc800078e0207 */
/*0d70*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0d80*/ @P1 BRA 0xd00 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*0d90*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000e240000201400 */
/*0da0*/ IADD3 R0, R7, 0x1800000, RZ ; /* 0x0180000007007810 */
/* 0x001fe20007ffe0ff */
/*0db0*/ BSSY B0, 0xe80 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*0dc0*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0dd0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*0de0*/ @P0 BRA 0xe30 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0df0*/ MOV R0, 0xe10 ; /* 0x00000e1000007802 */
/* 0x000fe40000000f00 */
/*0e00*/ CALL.REL.NOINC 0xec0 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0e10*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0004 */
/*0e20*/ BRA 0xe70 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0e30*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x000e240000001000 */
/*0e40*/ FFMA R2, R0, R7, -1 ; /* 0xbf80000000027423 */
/* 0x001fc80000000007 */
/*0e50*/ FADD.FTZ R3, -R2, -RZ ; /* 0x800000ff02037221 */
/* 0x000fc80000010100 */
/*0e60*/ FFMA R3, R0, R3, R0 ; /* 0x0000000300037223 */
/* 0x000fe40000000000 */
/*0e70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e80*/ STG.E [R16.64], R3 ; /* 0x0000000310007986 */
/* 0x000fe2000c101904 */
/*0e90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ea0*/ STG.E [R16.64], RZ ; /* 0x000000ff10007986 */
/* 0x000fe2000c101904 */
/*0eb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ec0*/ IMAD.SHL.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027824 */
/* 0x000fe200078e00ff */
/*0ed0*/ BSSY B1, 0x11e0 ; /* 0x0000030000017945 */
/* 0x000fe80003800000 */
/*0ee0*/ SHF.R.U32.HI R8, RZ, 0x18, R2 ; /* 0x00000018ff087819 */
/* 0x000fc80000011602 */
/*0ef0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05070 */
/*0f00*/ @P0 BRA 0xfb0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0f10*/ IMAD.SHL.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027824 */
/* 0x000fca00078e00ff */
/*0f20*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0f30*/ @P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007030823 */
/* 0x000fe200000000ff */
/*0f40*/ @!P0 MUFU.RCP R2, R7 ; /* 0x0000000700028308 */
/* 0x000ff00000001000 */
/*0f50*/ @P0 MUFU.RCP R4, R3 ; /* 0x0000000300040308 */
/* 0x000e240000001000 */
/*0f60*/ @P0 FFMA R5, R3, R4, -1 ; /* 0xbf80000003050423 */
/* 0x001fc80000000004 */
/*0f70*/ @P0 FADD.FTZ R5, -R5, -RZ ; /* 0x800000ff05050221 */
/* 0x000fc80000010100 */
/*0f80*/ @P0 FFMA R5, R4, R5, R4 ; /* 0x0000000504050223 */
/* 0x000fc80000000004 */
/*0f90*/ @P0 FFMA R2, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005020823 */
/* 0x000fe200000000ff */
/*0fa0*/ BRA 0x11d0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ IADD3 R9, R8, -0xfd, RZ ; /* 0xffffff0308097810 */
/* 0x000fc80007ffe0ff */
/*0fc0*/ ISETP.GT.U32.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f04070 */
/*0fd0*/ @P0 BRA 0x11c0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0fe0*/ LOP3.LUT R2, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07027812 */
/* 0x000fe200078ec0ff */
/*0ff0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x3 ; /* 0x00000003ff067424 */
/* 0x000fc600078e00ff */
/*1000*/ LOP3.LUT R2, R2, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000002027812 */
/* 0x000fe400078efcff */
/*1010*/ SHF.L.U32 R6, R6, R9, RZ ; /* 0x0000000906067219 */
/* 0x000fe400000006ff */
/*1020*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x000e240000001000 */
/*1030*/ FFMA R4, R2, R3, -1 ; /* 0xbf80000002047423 */
/* 0x001fc80000000003 */
/*1040*/ FADD.FTZ R4, -R4, -RZ ; /* 0x800000ff04047221 */
/* 0x000fc80000010100 */
/*1050*/ FFMA.RM R5, R3.reuse, R4.reuse, R3.reuse ; /* 0x0000000403057223 */
/* 0x1c0fe40000004003 */
/*1060*/ FFMA.RP R4, R3, R4, R3 ; /* 0x0000000403047223 */
/* 0x000fc60000008003 */
/*1070*/ LOP3.LUT R3, R5.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05037812 */
/* 0x040fe400078ec0ff */
/*1080*/ FSETP.NEU.FTZ.AND P0, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x000fe40003f1d000 */
/*1090*/ LOP3.LUT R3, R3, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000003037812 */
/* 0x000fe400078efcff */
/*10a0*/ SEL R4, RZ, 0xffffffff, !P0 ; /* 0xffffffffff047807 */
/* 0x000fe40004000000 */
/*10b0*/ LOP3.LUT R6, R6, R3, RZ, 0xc0, !PT ; /* 0x0000000306067212 */
/* 0x000fc600078ec0ff */
/*10c0*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0a04 */
/*10d0*/ SHF.R.U32.HI R6, RZ, R9, R6 ; /* 0x00000009ff067219 */
/* 0x000fc80000011606 */
/*10e0*/ LOP3.LUT P1, RZ, R4, R9, R3, 0xf8, !PT ; /* 0x0000000904ff7212 */
/* 0x000fe4000782f803 */
/*10f0*/ LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */
/* 0x040fe4000780c0ff */
/*1100*/ LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */
/* 0x000fc8000784c0ff */
/*1110*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*1120*/ LOP3.LUT P1, RZ, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07ff7812 */
/* 0x000fe4000782c0ff */
/*1130*/ SEL R2, RZ, 0x1, !P0 ; /* 0x00000001ff027807 */
/* 0x000fca0004000000 */
/*1140*/ IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0a02 */
/*1150*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f06270 */
/*1160*/ IADD3 R2, R8, -0xfc, RZ ; /* 0xffffff0408027810 */
/* 0x000fc80007ffe0ff */
/*1170*/ SHF.R.U32.HI R2, RZ, R2, R3 ; /* 0x00000002ff027219 */
/* 0x000fce0000011603 */
/*1180*/ @!P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102028810 */
/* 0x000fca0007ffe0ff */
/*1190*/ @!P1 IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202029824 */
/* 0x000fca00078e00ff */
/*11a0*/ LOP3.LUT R2, R2, 0x80000000, R7, 0xf8, !PT ; /* 0x8000000002027812 */
/* 0x000fe200078ef807 */
/*11b0*/ BRA 0x11d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*11c0*/ MUFU.RCP R2, R7 ; /* 0x0000000700027308 */
/* 0x0000640000001000 */
/*11d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*11e0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0002 */
/*11f0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*1200*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*1210*/ RET.REL.NODEC R2 0x0 ; /* 0xffffede002007950 */
/* 0x000fea0003c3ffff */
/*1220*/ BRA 0x1220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kLogregCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, const int numCases, const int numOut) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
/*
* Compute the probability of guessing the correct case if you take the most-probable label.
*
* This is done like this:
*
* - If the most probable label is not equal to the true label, then the probability is zero.
* - Otherwise, the probability is 1 / (number of labels whose probability is equal to the maximum).
*
* This is certainly overkill -- in practice, it's just about impossible for two labels to get assigned
* maximum probability. But it's a safety measure to prevent over-estimating your accuracy.
* Though it could never happen in reality. Well it could. But it wouldn't. Cool?
*/
if (labelp != maxp) {
correctProbs[tx] = 0;
} else {
int numMax = 0;
for (int i = 0; i < numOut; i++) {
numMax += probs[i * numCases + tx] == maxp;
}
correctProbs[tx] = 1.0f / float(numMax);
}
}
} | .file "tmpxft_00016f81_00000000-6_kLogregCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii
.type _Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii, @function
_Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11kLogregCostPfS_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii, .-_Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii
.globl _Z11kLogregCostPfS_S_S_S_ii
.type _Z11kLogregCostPfS_S_S_S_ii, @function
_Z11kLogregCostPfS_S_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kLogregCostPfS_S_S_S_ii, .-_Z11kLogregCostPfS_S_S_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kLogregCostPfS_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kLogregCostPfS_S_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kLogregCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, const int numCases, const int numOut) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
/*
* Compute the probability of guessing the correct case if you take the most-probable label.
*
* This is done like this:
*
* - If the most probable label is not equal to the true label, then the probability is zero.
* - Otherwise, the probability is 1 / (number of labels whose probability is equal to the maximum).
*
* This is certainly overkill -- in practice, it's just about impossible for two labels to get assigned
* maximum probability. But it's a safety measure to prevent over-estimating your accuracy.
* Though it could never happen in reality. Well it could. But it wouldn't. Cool?
*/
if (labelp != maxp) {
correctProbs[tx] = 0;
} else {
int numMax = 0;
for (int i = 0; i < numOut; i++) {
numMax += probs[i * numCases + tx] == maxp;
}
correctProbs[tx] = 1.0f / float(numMax);
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kLogregCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, const int numCases, const int numOut) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
/*
* Compute the probability of guessing the correct case if you take the most-probable label.
*
* This is done like this:
*
* - If the most probable label is not equal to the true label, then the probability is zero.
* - Otherwise, the probability is 1 / (number of labels whose probability is equal to the maximum).
*
* This is certainly overkill -- in practice, it's just about impossible for two labels to get assigned
* maximum probability. But it's a safety measure to prevent over-estimating your accuracy.
* Though it could never happen in reality. Well it could. But it wouldn't. Cool?
*/
if (labelp != maxp) {
correctProbs[tx] = 0;
} else {
int numMax = 0;
for (int i = 0; i < numOut; i++) {
numMax += probs[i * numCases + tx] == maxp;
}
correctProbs[tx] = 1.0f / float(numMax);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kLogregCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, const int numCases, const int numOut) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
/*
* Compute the probability of guessing the correct case if you take the most-probable label.
*
* This is done like this:
*
* - If the most probable label is not equal to the true label, then the probability is zero.
* - Otherwise, the probability is 1 / (number of labels whose probability is equal to the maximum).
*
* This is certainly overkill -- in practice, it's just about impossible for two labels to get assigned
* maximum probability. But it's a safety measure to prevent over-estimating your accuracy.
* Though it could never happen in reality. Well it could. But it wouldn't. Cool?
*/
if (labelp != maxp) {
correctProbs[tx] = 0;
} else {
int numMax = 0;
for (int i = 0; i < numOut; i++) {
numMax += probs[i * numCases + tx] == maxp;
}
correctProbs[tx] = 1.0f / float(numMax);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kLogregCostPfS_S_S_S_ii
.globl _Z11kLogregCostPfS_S_S_S_ii
.p2align 8
.type _Z11kLogregCostPfS_S_S_S_ii,@function
_Z11kLogregCostPfS_S_S_S_ii:
s_load_b32 s2, s[0:1], 0x28
v_lshl_add_u32 v0, s15, 7, v0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_9
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v6, v4
v_mad_u64_u32 v[4:5], null, v6, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v7, v[4:5], off
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(1)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v7
v_cndmask_b32_e64 v5, 1.0, 0x4f800000, vcc_lo
v_cndmask_b32_e64 v8, 0, 0x41b17218, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v7, v5
v_log_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x3f317217, v5
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v5|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v5, 0x3f317217, -v6
v_fmamk_f32 v6, v5, 0x3377d1cf, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, 0x3f317217, v5
v_cndmask_b32_e32 v9, v5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_sub_f32 v3, v9, v8 :: v_dual_mov_b32 v2, 0
global_store_b32 v[5:6], v3, off
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 v7, v4
s_cbranch_execz .LBB0_8
s_load_b32 s6, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_6
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v2, v0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s6, s6, -1
s_cmp_eq_u32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, v3, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc0 .LBB0_4
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v5
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v2, 0
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v2, v2, 1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, 1.0, v2, 1.0
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v2, 1.0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x20
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kLogregCostPfS_S_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kLogregCostPfS_S_S_S_ii, .Lfunc_end0-_Z11kLogregCostPfS_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kLogregCostPfS_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kLogregCostPfS_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kLogregCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, const int numCases, const int numOut) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
/*
* Compute the probability of guessing the correct case if you take the most-probable label.
*
* This is done like this:
*
* - If the most probable label is not equal to the true label, then the probability is zero.
* - Otherwise, the probability is 1 / (number of labels whose probability is equal to the maximum).
*
* This is certainly overkill -- in practice, it's just about impossible for two labels to get assigned
* maximum probability. But it's a safety measure to prevent over-estimating your accuracy.
* Though it could never happen in reality. Well it could. But it wouldn't. Cool?
*/
if (labelp != maxp) {
correctProbs[tx] = 0;
} else {
int numMax = 0;
for (int i = 0; i < numOut; i++) {
numMax += probs[i * numCases + tx] == maxp;
}
correctProbs[tx] = 1.0f / float(numMax);
}
}
} | .text
.file "kLogregCost.hip"
.globl _Z26__device_stub__kLogregCostPfS_S_S_S_ii # -- Begin function _Z26__device_stub__kLogregCostPfS_S_S_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__kLogregCostPfS_S_S_S_ii,@function
_Z26__device_stub__kLogregCostPfS_S_S_S_ii: # @_Z26__device_stub__kLogregCostPfS_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11kLogregCostPfS_S_S_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__kLogregCostPfS_S_S_S_ii, .Lfunc_end0-_Z26__device_stub__kLogregCostPfS_S_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kLogregCostPfS_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kLogregCostPfS_S_S_S_ii,@object # @_Z11kLogregCostPfS_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z11kLogregCostPfS_S_S_S_ii
.p2align 3, 0x0
_Z11kLogregCostPfS_S_S_S_ii:
.quad _Z26__device_stub__kLogregCostPfS_S_S_S_ii
.size _Z11kLogregCostPfS_S_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kLogregCostPfS_S_S_S_ii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kLogregCostPfS_S_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kLogregCostPfS_S_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00016f81_00000000-6_kLogregCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii
.type _Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii, @function
_Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11kLogregCostPfS_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii, .-_Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii
.globl _Z11kLogregCostPfS_S_S_S_ii
.type _Z11kLogregCostPfS_S_S_S_ii, @function
_Z11kLogregCostPfS_S_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z11kLogregCostPfS_S_S_S_iiPfS_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kLogregCostPfS_S_S_S_ii, .-_Z11kLogregCostPfS_S_S_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kLogregCostPfS_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kLogregCostPfS_S_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kLogregCost.hip"
.globl _Z26__device_stub__kLogregCostPfS_S_S_S_ii # -- Begin function _Z26__device_stub__kLogregCostPfS_S_S_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__kLogregCostPfS_S_S_S_ii,@function
_Z26__device_stub__kLogregCostPfS_S_S_S_ii: # @_Z26__device_stub__kLogregCostPfS_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11kLogregCostPfS_S_S_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__kLogregCostPfS_S_S_S_ii, .Lfunc_end0-_Z26__device_stub__kLogregCostPfS_S_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kLogregCostPfS_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kLogregCostPfS_S_S_S_ii,@object # @_Z11kLogregCostPfS_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z11kLogregCostPfS_S_S_S_ii
.p2align 3, 0x0
_Z11kLogregCostPfS_S_S_S_ii:
.quad _Z26__device_stub__kLogregCostPfS_S_S_S_ii
.size _Z11kLogregCostPfS_S_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kLogregCostPfS_S_S_S_ii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kLogregCostPfS_S_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kLogregCostPfS_S_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define N 10
__host__ __device__ void fun(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
++arr[ii];
}
__global__ void dfun(int *arr) {
fun(arr);
}
__host__ __device__ void print(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
printf("%d, ", arr[ii]);
printf("\n");
}
__global__ void dprint(int *arr) {
print(arr);
}
int main() {
int arr[N], *darr;
cudaMalloc(&darr, N * sizeof(int));
for (unsigned ii = 0; ii < N; ++ii)
arr[ii] = ii;
cudaMemcpy(darr, arr, N * sizeof(int), cudaMemcpyHostToDevice);
fun(arr);
dfun<<<1, 1>>>(darr);
cudaDeviceSynchronize();
print(arr);
dprint<<<1, 1>>>(darr);
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z6dprintPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0050*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ MOV R19, 0x0 ; /* 0x0000000000137802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R18, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001127a10 */
/* 0x000fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000660000000a00 */
/*00b0*/ IMAD.X R2, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff027624 */
/* 0x000fe400000e06ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*00e0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*00f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*0100*/ MOV R3, 0x170 ; /* 0x0000017000037802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R20, 0xf0 ; /* 0x000000f000147802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0140*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0150*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0160*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0170*/ LDG.E R0, [R16.64+0x4] ; /* 0x0000042410007981 */
/* 0x000ea2000c1e1900 */
/*0180*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*01d0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*01e0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*01f0*/ MOV R3, 0x260 ; /* 0x0000026000037802 */
/* 0x000fe40000000f00 */
/*0200*/ MOV R20, 0x1e0 ; /* 0x000001e000147802 */
/* 0x000fc40000000f00 */
/*0210*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0230*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0240*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0250*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0260*/ LDG.E R0, [R16.64+0x8] ; /* 0x0000082410007981 */
/* 0x000ea2000c1e1900 */
/*0270*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0280*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*02c0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*02d0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*02e0*/ MOV R3, 0x350 ; /* 0x0000035000037802 */
/* 0x000fe40000000f00 */
/*02f0*/ MOV R20, 0x2d0 ; /* 0x000002d000147802 */
/* 0x000fc40000000f00 */
/*0300*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0310*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0320*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0330*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0340*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0350*/ LDG.E R0, [R16.64+0xc] ; /* 0x00000c2410007981 */
/* 0x000ea2000c1e1900 */
/*0360*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0380*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0390*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*03a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*03b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*03c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*03d0*/ MOV R3, 0x440 ; /* 0x0000044000037802 */
/* 0x000fe40000000f00 */
/*03e0*/ MOV R20, 0x3c0 ; /* 0x000003c000147802 */
/* 0x000fc40000000f00 */
/*03f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0400*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0410*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0420*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0430*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0440*/ LDG.E R0, [R16.64+0x10] ; /* 0x0000102410007981 */
/* 0x000ea2000c1e1900 */
/*0450*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0460*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0470*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*04a0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*04b0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*04c0*/ MOV R3, 0x530 ; /* 0x0000053000037802 */
/* 0x000fe40000000f00 */
/*04d0*/ MOV R20, 0x4b0 ; /* 0x000004b000147802 */
/* 0x000fc40000000f00 */
/*04e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*04f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0500*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0510*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0520*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0530*/ LDG.E R0, [R16.64+0x14] ; /* 0x0000142410007981 */
/* 0x000ea2000c1e1900 */
/*0540*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0580*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0590*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*05a0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*05b0*/ MOV R3, 0x620 ; /* 0x0000062000037802 */
/* 0x000fe40000000f00 */
/*05c0*/ MOV R20, 0x5a0 ; /* 0x000005a000147802 */
/* 0x000fc40000000f00 */
/*05d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*05e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*05f0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0600*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0610*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0620*/ LDG.E R0, [R16.64+0x18] ; /* 0x0000182410007981 */
/* 0x000ea2000c1e1900 */
/*0630*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0640*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0660*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0670*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0680*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*0690*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*06a0*/ MOV R3, 0x710 ; /* 0x0000071000037802 */
/* 0x000fe40000000f00 */
/*06b0*/ MOV R20, 0x690 ; /* 0x0000069000147802 */
/* 0x000fc40000000f00 */
/*06c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*06d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*06e0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*06f0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0700*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0710*/ LDG.E R0, [R16.64+0x1c] ; /* 0x00001c2410007981 */
/* 0x000ea2000c1e1900 */
/*0720*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0730*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0740*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0750*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0760*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0770*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*0780*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*0790*/ MOV R3, 0x800 ; /* 0x0000080000037802 */
/* 0x000fe40000000f00 */
/*07a0*/ MOV R20, 0x780 ; /* 0x0000078000147802 */
/* 0x000fc40000000f00 */
/*07b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*07c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*07d0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*07e0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*07f0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0800*/ LDG.E R0, [R16.64+0x20] ; /* 0x0000202410007981 */
/* 0x000ea2000c1e1900 */
/*0810*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0820*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0830*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0840*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0850*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0860*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*0870*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*0880*/ MOV R3, 0x8f0 ; /* 0x000008f000037802 */
/* 0x000fe40000000f00 */
/*0890*/ MOV R20, 0x870 ; /* 0x0000087000147802 */
/* 0x000fc40000000f00 */
/*08a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*08b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*08c0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*08d0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*08e0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*08f0*/ LDG.E R16, [R16.64+0x24] ; /* 0x0000242410107981 */
/* 0x000ea2000c1e1900 */
/*0900*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0910*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0920*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0930*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0940*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0950*/ STL [R1], R16 ; /* 0x0000001001007387 */
/* 0x0041e80000100800 */
/*0960*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fe40000000000 */
/*0970*/ MOV R11, 0x9e0 ; /* 0x000009e0000b7802 */
/* 0x000fe40000000f00 */
/*0980*/ MOV R20, 0x960 ; /* 0x0000096000147802 */
/* 0x000fc40000000f00 */
/*0990*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*09a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*09b0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*09c0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*09d0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*09e0*/ LDC.64 R2, c[0x4][R19] ; /* 0x0100000013027b82 */
/* 0x0000620000000a00 */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0a00*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0a10*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fca00078e00ff */
/*0a20*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0a30*/ MOV R11, 0xaa0 ; /* 0x00000aa0000b7802 */
/* 0x000fe40000000f00 */
/*0a40*/ MOV R20, 0xa20 ; /* 0x00000a2000147802 */
/* 0x000fe40000000f00 */
/*0a50*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0a60*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0a70*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0a80*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0a90*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x003fea0003c00000 */
/*0aa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ab0*/ BRA 0xab0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4dfunPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0050*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ee8000c1e1900 */
/*0060*/ LDG.E R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000f28000c1e1900 */
/*0070*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0402087981 */
/* 0x000f68000c1e1900 */
/*0080*/ LDG.E R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000f68000c1e1900 */
/*0090*/ LDG.E R12, [R2.64+0x14] ; /* 0x00001404020c7981 */
/* 0x000f68000c1e1900 */
/*00a0*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000f68000c1e1900 */
/*00b0*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000f68000c1e1900 */
/*00c0*/ LDG.E R18, [R2.64+0x20] ; /* 0x0000200402127981 */
/* 0x000f68000c1e1900 */
/*00d0*/ LDG.E R20, [R2.64+0x24] ; /* 0x0000240402147981 */
/* 0x000f62000c1e1900 */
/*00e0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fc40007ffe0ff */
/*00f0*/ IADD3 R7, R4, 0x1, RZ ; /* 0x0000000104077810 */
/* 0x008fc60007ffe0ff */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x010fc60007ffe0ff */
/*0120*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101904 */
/*0130*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x020fc60007ffe0ff */
/*0140*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe2000c101904 */
/*0150*/ IADD3 R13, R10, 0x1, RZ ; /* 0x000000010a0d7810 */
/* 0x000fc60007ffe0ff */
/*0160*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x000fe2000c101904 */
/*0170*/ IADD3 R15, R12, 0x1, RZ ; /* 0x000000010c0f7810 */
/* 0x000fc60007ffe0ff */
/*0180*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe2000c101904 */
/*0190*/ IADD3 R17, R14, 0x1, RZ ; /* 0x000000010e117810 */
/* 0x000fc60007ffe0ff */
/*01a0*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x000fe2000c101904 */
/*01b0*/ IADD3 R19, R16, 0x1, RZ ; /* 0x0000000110137810 */
/* 0x000fc60007ffe0ff */
/*01c0*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x000fe2000c101904 */
/*01d0*/ IADD3 R21, R18, 0x1, RZ ; /* 0x0000000112157810 */
/* 0x000fc60007ffe0ff */
/*01e0*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x000fe2000c101904 */
/*01f0*/ IADD3 R23, R20, 0x1, RZ ; /* 0x0000000114177810 */
/* 0x000fc60007ffe0ff */
/*0200*/ STG.E [R2.64+0x20], R21 ; /* 0x0000201502007986 */
/* 0x000fe8000c101904 */
/*0210*/ STG.E [R2.64+0x24], R23 ; /* 0x0000241702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define N 10
__host__ __device__ void fun(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
++arr[ii];
}
__global__ void dfun(int *arr) {
fun(arr);
}
__host__ __device__ void print(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
printf("%d, ", arr[ii]);
printf("\n");
}
__global__ void dprint(int *arr) {
print(arr);
}
int main() {
int arr[N], *darr;
cudaMalloc(&darr, N * sizeof(int));
for (unsigned ii = 0; ii < N; ++ii)
arr[ii] = ii;
cudaMemcpy(darr, arr, N * sizeof(int), cudaMemcpyHostToDevice);
fun(arr);
dfun<<<1, 1>>>(darr);
cudaDeviceSynchronize();
print(arr);
dprint<<<1, 1>>>(darr);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000a7ca0_00000000-6_functions3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3funPi
.type _Z3funPi, @function
_Z3funPi:
.LFB2057:
.cfi_startproc
endbr64
leaq 40(%rdi), %rax
.L4:
addl $1, (%rdi)
addq $4, %rdi
cmpq %rax, %rdi
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z3funPi, .-_Z3funPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d, "
.LC1:
.string "\n"
.text
.globl _Z5printPi
.type _Z5printPi, @function
_Z5printPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 40(%rdi), %r12
leaq .LC0(%rip), %rbp
.L7:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L7
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5printPi, .-_Z5printPi
.globl _Z23__device_stub__Z4dfunPiPi
.type _Z23__device_stub__Z4dfunPiPi, @function
_Z23__device_stub__Z4dfunPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4dfunPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z23__device_stub__Z4dfunPiPi, .-_Z23__device_stub__Z4dfunPiPi
.globl _Z4dfunPi
.type _Z4dfunPi, @function
_Z4dfunPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4dfunPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4dfunPi, .-_Z4dfunPi
.globl _Z25__device_stub__Z6dprintPiPi
.type _Z25__device_stub__Z6dprintPiPi, @function
_Z25__device_stub__Z6dprintPiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6dprintPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z25__device_stub__Z6dprintPiPi, .-_Z25__device_stub__Z6dprintPiPi
.globl _Z6dprintPi
.type _Z6dprintPi, @function
_Z6dprintPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6dprintPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6dprintPi, .-_Z6dprintPi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L27:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L27
leaq 32(%rsp), %rbx
movl $1, %ecx
movl $40, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call _Z3funPi
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
call cudaDeviceSynchronize@PLT
leaq 32(%rsp), %rdi
call _Z5printPi
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
call cudaDeviceSynchronize@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq (%rsp), %rdi
call _Z23__device_stub__Z4dfunPiPi
jmp .L28
.L34:
movq (%rsp), %rdi
call _Z25__device_stub__Z6dprintPiPi
jmp .L29
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6dprintPi"
.LC3:
.string "_Z4dfunPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6dprintPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z4dfunPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define N 10
__host__ __device__ void fun(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
++arr[ii];
}
__global__ void dfun(int *arr) {
fun(arr);
}
__host__ __device__ void print(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
printf("%d, ", arr[ii]);
printf("\n");
}
__global__ void dprint(int *arr) {
print(arr);
}
int main() {
int arr[N], *darr;
cudaMalloc(&darr, N * sizeof(int));
for (unsigned ii = 0; ii < N; ++ii)
arr[ii] = ii;
cudaMemcpy(darr, arr, N * sizeof(int), cudaMemcpyHostToDevice);
fun(arr);
dfun<<<1, 1>>>(darr);
cudaDeviceSynchronize();
print(arr);
dprint<<<1, 1>>>(darr);
cudaDeviceSynchronize();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 10
__host__ __device__ void fun(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
++arr[ii];
}
__global__ void dfun(int *arr) {
fun(arr);
}
__host__ __device__ void print(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
printf("%d, ", arr[ii]);
printf("\n");
}
__global__ void dprint(int *arr) {
print(arr);
}
int main() {
int arr[N], *darr;
hipMalloc(&darr, N * sizeof(int));
for (unsigned ii = 0; ii < N; ++ii)
arr[ii] = ii;
hipMemcpy(darr, arr, N * sizeof(int), hipMemcpyHostToDevice);
fun(arr);
dfun<<<1, 1>>>(darr);
hipDeviceSynchronize();
print(arr);
dprint<<<1, 1>>>(darr);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 10
__host__ __device__ void fun(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
++arr[ii];
}
__global__ void dfun(int *arr) {
fun(arr);
}
__host__ __device__ void print(int *arr) {
for (unsigned ii = 0; ii < N; ++ii)
printf("%d, ", arr[ii]);
printf("\n");
}
__global__ void dprint(int *arr) {
print(arr);
}
int main() {
int arr[N], *darr;
hipMalloc(&darr, N * sizeof(int));
for (unsigned ii = 0; ii < N; ++ii)
arr[ii] = ii;
hipMemcpy(darr, arr, N * sizeof(int), hipMemcpyHostToDevice);
fun(arr);
dfun<<<1, 1>>>(darr);
hipDeviceSynchronize();
print(arr);
dprint<<<1, 1>>>(darr);
hipDeviceSynchronize();
return 0;
} | .text
.file "functions3.hip"
.globl _Z3funPi # -- Begin function _Z3funPi
.p2align 4, 0x90
.type _Z3funPi,@function
_Z3funPi: # @_Z3funPi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
incl (%rdi,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB0_1
# %bb.2:
retq
.Lfunc_end0:
.size _Z3funPi, .Lfunc_end0-_Z3funPi
.cfi_endproc
# -- End function
.globl _Z19__device_stub__dfunPi # -- Begin function _Z19__device_stub__dfunPi
.p2align 4, 0x90
.type _Z19__device_stub__dfunPi,@function
_Z19__device_stub__dfunPi: # @_Z19__device_stub__dfunPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4dfunPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z19__device_stub__dfunPi, .Lfunc_end1-_Z19__device_stub__dfunPi
.cfi_endproc
# -- End function
.globl _Z5printPi # -- Begin function _Z5printPi
.p2align 4, 0x90
.type _Z5printPi,@function
_Z5printPi: # @_Z5printPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_1
# %bb.2:
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z5printPi, .Lfunc_end2-_Z5printPi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__dprintPi # -- Begin function _Z21__device_stub__dprintPi
.p2align 4, 0x90
.type _Z21__device_stub__dprintPi,@function
_Z21__device_stub__dprintPi: # @_Z21__device_stub__dprintPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6dprintPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z21__device_stub__dprintPi, .Lfunc_end3-_Z21__device_stub__dprintPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl %eax, 80(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB4_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
incl 80(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB4_3
# %bb.4: # %_Z3funPi.exit
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z4dfunPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipDeviceSynchronize
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_7: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB4_7
# %bb.8: # %_Z5printPi.exit
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z6dprintPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4dfunPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6dprintPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4dfunPi,@object # @_Z4dfunPi
.section .rodata,"a",@progbits
.globl _Z4dfunPi
.p2align 3, 0x0
_Z4dfunPi:
.quad _Z19__device_stub__dfunPi
.size _Z4dfunPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, "
.size .L.str, 5
.type _Z6dprintPi,@object # @_Z6dprintPi
.section .rodata,"a",@progbits
.globl _Z6dprintPi
.p2align 3, 0x0
_Z6dprintPi:
.quad _Z21__device_stub__dprintPi
.size _Z6dprintPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4dfunPi"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6dprintPi"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__dfunPi
.addrsig_sym _Z21__device_stub__dprintPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4dfunPi
.addrsig_sym _Z6dprintPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a7ca0_00000000-6_functions3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3funPi
.type _Z3funPi, @function
_Z3funPi:
.LFB2057:
.cfi_startproc
endbr64
leaq 40(%rdi), %rax
.L4:
addl $1, (%rdi)
addq $4, %rdi
cmpq %rax, %rdi
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z3funPi, .-_Z3funPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d, "
.LC1:
.string "\n"
.text
.globl _Z5printPi
.type _Z5printPi, @function
_Z5printPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 40(%rdi), %r12
leaq .LC0(%rip), %rbp
.L7:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L7
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5printPi, .-_Z5printPi
.globl _Z23__device_stub__Z4dfunPiPi
.type _Z23__device_stub__Z4dfunPiPi, @function
_Z23__device_stub__Z4dfunPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4dfunPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z23__device_stub__Z4dfunPiPi, .-_Z23__device_stub__Z4dfunPiPi
.globl _Z4dfunPi
.type _Z4dfunPi, @function
_Z4dfunPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4dfunPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4dfunPi, .-_Z4dfunPi
.globl _Z25__device_stub__Z6dprintPiPi
.type _Z25__device_stub__Z6dprintPiPi, @function
_Z25__device_stub__Z6dprintPiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6dprintPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z25__device_stub__Z6dprintPiPi, .-_Z25__device_stub__Z6dprintPiPi
.globl _Z6dprintPi
.type _Z6dprintPi, @function
_Z6dprintPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6dprintPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6dprintPi, .-_Z6dprintPi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L27:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L27
leaq 32(%rsp), %rbx
movl $1, %ecx
movl $40, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call _Z3funPi
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
call cudaDeviceSynchronize@PLT
leaq 32(%rsp), %rdi
call _Z5printPi
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
call cudaDeviceSynchronize@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq (%rsp), %rdi
call _Z23__device_stub__Z4dfunPiPi
jmp .L28
.L34:
movq (%rsp), %rdi
call _Z25__device_stub__Z6dprintPiPi
jmp .L29
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6dprintPi"
.LC3:
.string "_Z4dfunPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6dprintPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z4dfunPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "functions3.hip"
.globl _Z3funPi # -- Begin function _Z3funPi
.p2align 4, 0x90
.type _Z3funPi,@function
_Z3funPi: # @_Z3funPi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
incl (%rdi,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB0_1
# %bb.2:
retq
.Lfunc_end0:
.size _Z3funPi, .Lfunc_end0-_Z3funPi
.cfi_endproc
# -- End function
.globl _Z19__device_stub__dfunPi # -- Begin function _Z19__device_stub__dfunPi
.p2align 4, 0x90
.type _Z19__device_stub__dfunPi,@function
_Z19__device_stub__dfunPi: # @_Z19__device_stub__dfunPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4dfunPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z19__device_stub__dfunPi, .Lfunc_end1-_Z19__device_stub__dfunPi
.cfi_endproc
# -- End function
.globl _Z5printPi # -- Begin function _Z5printPi
.p2align 4, 0x90
.type _Z5printPi,@function
_Z5printPi: # @_Z5printPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_1
# %bb.2:
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z5printPi, .Lfunc_end2-_Z5printPi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__dprintPi # -- Begin function _Z21__device_stub__dprintPi
.p2align 4, 0x90
.type _Z21__device_stub__dprintPi,@function
_Z21__device_stub__dprintPi: # @_Z21__device_stub__dprintPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6dprintPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z21__device_stub__dprintPi, .Lfunc_end3-_Z21__device_stub__dprintPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl %eax, 80(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB4_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
incl 80(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB4_3
# %bb.4: # %_Z3funPi.exit
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z4dfunPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipDeviceSynchronize
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_7: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB4_7
# %bb.8: # %_Z5printPi.exit
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, (%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movq %rsp, %r9
movl $_Z6dprintPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4dfunPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6dprintPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4dfunPi,@object # @_Z4dfunPi
.section .rodata,"a",@progbits
.globl _Z4dfunPi
.p2align 3, 0x0
_Z4dfunPi:
.quad _Z19__device_stub__dfunPi
.size _Z4dfunPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, "
.size .L.str, 5
.type _Z6dprintPi,@object # @_Z6dprintPi
.section .rodata,"a",@progbits
.globl _Z6dprintPi
.p2align 3, 0x0
_Z6dprintPi:
.quad _Z21__device_stub__dprintPi
.size _Z6dprintPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4dfunPi"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6dprintPi"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__dfunPi
.addrsig_sym _Z21__device_stub__dprintPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4dfunPi
.addrsig_sym _Z6dprintPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void marix_multiply_by_const(const float *d_input, float *d_output, float val, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
d_output[index] = d_input[index] * val;
}
} | code for sm_80
Function : _Z23marix_multiply_by_constPKfPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FMUL R7, R2, c[0x0][0x170] ; /* 0x00005c0002077a20 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void marix_multiply_by_const(const float *d_input, float *d_output, float val, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
d_output[index] = d_input[index] * val;
}
} | .file "tmpxft_001bb946_00000000-6_marix_multiply_by_const.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi
.type _Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi, @function
_Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23marix_multiply_by_constPKfPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi, .-_Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi
.globl _Z23marix_multiply_by_constPKfPffi
.type _Z23marix_multiply_by_constPKfPffi, @function
_Z23marix_multiply_by_constPKfPffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23marix_multiply_by_constPKfPffi, .-_Z23marix_multiply_by_constPKfPffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23marix_multiply_by_constPKfPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23marix_multiply_by_constPKfPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void marix_multiply_by_const(const float *d_input, float *d_output, float val, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
d_output[index] = d_input[index] * val;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void marix_multiply_by_const(const float *d_input, float *d_output, float val, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
d_output[index] = d_input[index] * val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void marix_multiply_by_const(const float *d_input, float *d_output, float val, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
d_output[index] = d_input[index] * val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23marix_multiply_by_constPKfPffi
.globl _Z23marix_multiply_by_constPKfPffi
.p2align 8
.type _Z23marix_multiply_by_constPKfPffi,@function
_Z23marix_multiply_by_constPKfPffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23marix_multiply_by_constPKfPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23marix_multiply_by_constPKfPffi, .Lfunc_end0-_Z23marix_multiply_by_constPKfPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23marix_multiply_by_constPKfPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23marix_multiply_by_constPKfPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void marix_multiply_by_const(const float *d_input, float *d_output, float val, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
d_output[index] = d_input[index] * val;
}
} | .text
.file "marix_multiply_by_const.hip"
.globl _Z38__device_stub__marix_multiply_by_constPKfPffi # -- Begin function _Z38__device_stub__marix_multiply_by_constPKfPffi
.p2align 4, 0x90
.type _Z38__device_stub__marix_multiply_by_constPKfPffi,@function
_Z38__device_stub__marix_multiply_by_constPKfPffi: # @_Z38__device_stub__marix_multiply_by_constPKfPffi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23marix_multiply_by_constPKfPffi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__marix_multiply_by_constPKfPffi, .Lfunc_end0-_Z38__device_stub__marix_multiply_by_constPKfPffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23marix_multiply_by_constPKfPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23marix_multiply_by_constPKfPffi,@object # @_Z23marix_multiply_by_constPKfPffi
.section .rodata,"a",@progbits
.globl _Z23marix_multiply_by_constPKfPffi
.p2align 3, 0x0
_Z23marix_multiply_by_constPKfPffi:
.quad _Z38__device_stub__marix_multiply_by_constPKfPffi
.size _Z23marix_multiply_by_constPKfPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23marix_multiply_by_constPKfPffi"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__marix_multiply_by_constPKfPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23marix_multiply_by_constPKfPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23marix_multiply_by_constPKfPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FMUL R7, R2, c[0x0][0x170] ; /* 0x00005c0002077a20 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23marix_multiply_by_constPKfPffi
.globl _Z23marix_multiply_by_constPKfPffi
.p2align 8
.type _Z23marix_multiply_by_constPKfPffi,@function
_Z23marix_multiply_by_constPKfPffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23marix_multiply_by_constPKfPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23marix_multiply_by_constPKfPffi, .Lfunc_end0-_Z23marix_multiply_by_constPKfPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23marix_multiply_by_constPKfPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23marix_multiply_by_constPKfPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bb946_00000000-6_marix_multiply_by_const.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi
.type _Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi, @function
_Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23marix_multiply_by_constPKfPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi, .-_Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi
.globl _Z23marix_multiply_by_constPKfPffi
.type _Z23marix_multiply_by_constPKfPffi, @function
_Z23marix_multiply_by_constPKfPffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23marix_multiply_by_constPKfPffiPKfPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23marix_multiply_by_constPKfPffi, .-_Z23marix_multiply_by_constPKfPffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23marix_multiply_by_constPKfPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23marix_multiply_by_constPKfPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "marix_multiply_by_const.hip"
.globl _Z38__device_stub__marix_multiply_by_constPKfPffi # -- Begin function _Z38__device_stub__marix_multiply_by_constPKfPffi
.p2align 4, 0x90
.type _Z38__device_stub__marix_multiply_by_constPKfPffi,@function
_Z38__device_stub__marix_multiply_by_constPKfPffi: # @_Z38__device_stub__marix_multiply_by_constPKfPffi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23marix_multiply_by_constPKfPffi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__marix_multiply_by_constPKfPffi, .Lfunc_end0-_Z38__device_stub__marix_multiply_by_constPKfPffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23marix_multiply_by_constPKfPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23marix_multiply_by_constPKfPffi,@object # @_Z23marix_multiply_by_constPKfPffi
.section .rodata,"a",@progbits
.globl _Z23marix_multiply_by_constPKfPffi
.p2align 3, 0x0
_Z23marix_multiply_by_constPKfPffi:
.quad _Z38__device_stub__marix_multiply_by_constPKfPffi
.size _Z23marix_multiply_by_constPKfPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23marix_multiply_by_constPKfPffi"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__marix_multiply_by_constPKfPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23marix_multiply_by_constPKfPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void add(int* a, int* b, int* c)
{
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Put count random integers into integer [array] pointed to by p
void random_ints(int *p, int count)
{
for (int i=0; i < count; i++) {
p[i] = rand() % 32768; // limit random numbers to [0, 32768]
}
}
#define N 512
int main(void)
{
int *a, *b, *c; // host copies of data
int *d_a, *d_b, *d_c; // devices copies of data
int size = N * sizeof(int); // Number of bytes for N integers
printf("Total integer space size is %d bytes\n", size);
// Allocate space for device copies of data
cudaMalloc((void**) &d_a, size);
cudaMalloc((void**) &d_b, size);
cudaMalloc((void**) &d_c, size);
// Allocate space for host copies of input values (a, b, c arrays)
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
// Setup integers
random_ints(a, N);
random_ints(b, N);
// Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Launch add() on device
add<<<N,1>>>(d_a, d_b, d_c);
// Copy result to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Print out results
printf("\nResults of parallel GPU addition across %d elements:\n", N);
for (int i=0; i < N; i++) {
int sum = a[i] + b[i];
if (c[i] == sum) {
printf("%4d: %6d + %6d = %6d\n", i, a[i], b[i], c[i]);
}
else {
printf("%4d: %6d + %6d != %6d ERROR, should be %d", i, a[i], b[i], c[i], sum);
}
}
// Cleanup
free(a); free(b); free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void add(int* a, int* b, int* c)
{
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Put count random integers into integer [array] pointed to by p
void random_ints(int *p, int count)
{
for (int i=0; i < count; i++) {
p[i] = rand() % 32768; // limit random numbers to [0, 32768]
}
}
#define N 512
int main(void)
{
int *a, *b, *c; // host copies of data
int *d_a, *d_b, *d_c; // devices copies of data
int size = N * sizeof(int); // Number of bytes for N integers
printf("Total integer space size is %d bytes\n", size);
// Allocate space for device copies of data
cudaMalloc((void**) &d_a, size);
cudaMalloc((void**) &d_b, size);
cudaMalloc((void**) &d_c, size);
// Allocate space for host copies of input values (a, b, c arrays)
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
// Setup integers
random_ints(a, N);
random_ints(b, N);
// Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Launch add() on device
add<<<N,1>>>(d_a, d_b, d_c);
// Copy result to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Print out results
printf("\nResults of parallel GPU addition across %d elements:\n", N);
for (int i=0; i < N; i++) {
int sum = a[i] + b[i];
if (c[i] == sum) {
printf("%4d: %6d + %6d = %6d\n", i, a[i], b[i], c[i]);
}
else {
printf("%4d: %6d + %6d != %6d ERROR, should be %d", i, a[i], b[i], c[i], sum);
}
}
// Cleanup
free(a); free(b); free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_00140419_00000000-6_vectoradd_par.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
cltd
shrl $17, %edx
addl %edx, %eax
andl $32767, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Total integer space size is %d bytes\n"
.align 8
.LC1:
.string "\nResults of parallel GPU addition across %d elements:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%4d: %6d + %6d = %6d\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "%4d: %6d + %6d != %6d ERROR, should be %d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2048, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $512, %esi
movq %r12, %rdi
call _Z11random_intsPii
movl $512, %esi
movq %rbp, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $2048, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L20:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $512, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r14
leaq .LC2(%rip), %r15
jmp .L23
.L27:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L29:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
addq $1, %rbx
cmpq $512, %rbx
je .L28
.L23:
movl %ebx, %edx
movl (%r12,%rbx,4), %ecx
movl 0(%rbp,%rbx,4), %r8d
leal (%rcx,%r8), %eax
movl 0(%r13,%rbx,4), %r9d
cmpl %eax, %r9d
je .L29
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L28:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void add(int* a, int* b, int* c)
{
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Put count random integers into integer [array] pointed to by p
void random_ints(int *p, int count)
{
for (int i=0; i < count; i++) {
p[i] = rand() % 32768; // limit random numbers to [0, 32768]
}
}
#define N 512
int main(void)
{
int *a, *b, *c; // host copies of data
int *d_a, *d_b, *d_c; // devices copies of data
int size = N * sizeof(int); // Number of bytes for N integers
printf("Total integer space size is %d bytes\n", size);
// Allocate space for device copies of data
cudaMalloc((void**) &d_a, size);
cudaMalloc((void**) &d_b, size);
cudaMalloc((void**) &d_c, size);
// Allocate space for host copies of input values (a, b, c arrays)
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
// Setup integers
random_ints(a, N);
random_ints(b, N);
// Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Launch add() on device
add<<<N,1>>>(d_a, d_b, d_c);
// Copy result to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Print out results
printf("\nResults of parallel GPU addition across %d elements:\n", N);
for (int i=0; i < N; i++) {
int sum = a[i] + b[i];
if (c[i] == sum) {
printf("%4d: %6d + %6d = %6d\n", i, a[i], b[i], c[i]);
}
else {
printf("%4d: %6d + %6d != %6d ERROR, should be %d", i, a[i], b[i], c[i], sum);
}
}
// Cleanup
free(a); free(b); free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int* a, int* b, int* c)
{
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Put count random integers into integer [array] pointed to by p
void random_ints(int *p, int count)
{
for (int i=0; i < count; i++) {
p[i] = rand() % 32768; // limit random numbers to [0, 32768]
}
}
#define N 512
int main(void)
{
int *a, *b, *c; // host copies of data
int *d_a, *d_b, *d_c; // devices copies of data
int size = N * sizeof(int); // Number of bytes for N integers
printf("Total integer space size is %d bytes\n", size);
// Allocate space for device copies of data
hipMalloc((void**) &d_a, size);
hipMalloc((void**) &d_b, size);
hipMalloc((void**) &d_c, size);
// Allocate space for host copies of input values (a, b, c arrays)
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
// Setup integers
random_ints(a, N);
random_ints(b, N);
// Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Launch add() on device
add<<<N,1>>>(d_a, d_b, d_c);
// Copy result to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Print out results
printf("\nResults of parallel GPU addition across %d elements:\n", N);
for (int i=0; i < N; i++) {
int sum = a[i] + b[i];
if (c[i] == sum) {
printf("%4d: %6d + %6d = %6d\n", i, a[i], b[i], c[i]);
}
else {
printf("%4d: %6d + %6d != %6d ERROR, should be %d", i, a[i], b[i], c[i], sum);
}
}
// Cleanup
free(a); free(b); free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int* a, int* b, int* c)
{
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Put count random integers into integer [array] pointed to by p
void random_ints(int *p, int count)
{
for (int i=0; i < count; i++) {
p[i] = rand() % 32768; // limit random numbers to [0, 32768]
}
}
#define N 512
int main(void)
{
int *a, *b, *c; // host copies of data
int *d_a, *d_b, *d_c; // devices copies of data
int size = N * sizeof(int); // Number of bytes for N integers
printf("Total integer space size is %d bytes\n", size);
// Allocate space for device copies of data
hipMalloc((void**) &d_a, size);
hipMalloc((void**) &d_b, size);
hipMalloc((void**) &d_c, size);
// Allocate space for host copies of input values (a, b, c arrays)
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
// Setup integers
random_ints(a, N);
random_ints(b, N);
// Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Launch add() on device
add<<<N,1>>>(d_a, d_b, d_c);
// Copy result to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Print out results
printf("\nResults of parallel GPU addition across %d elements:\n", N);
for (int i=0; i < N; i++) {
int sum = a[i] + b[i];
if (c[i] == sum) {
printf("%4d: %6d + %6d = %6d\n", i, a[i], b[i], c[i]);
}
else {
printf("%4d: %6d + %6d != %6d ERROR, should be %d", i, a[i], b[i], c[i], sum);
}
}
// Cleanup
free(a); free(b); free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int* a, int* b, int* c)
{
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Put count random integers into integer [array] pointed to by p
void random_ints(int *p, int count)
{
for (int i=0; i < count; i++) {
p[i] = rand() % 32768; // limit random numbers to [0, 32768]
}
}
#define N 512
int main(void)
{
int *a, *b, *c; // host copies of data
int *d_a, *d_b, *d_c; // devices copies of data
int size = N * sizeof(int); // Number of bytes for N integers
printf("Total integer space size is %d bytes\n", size);
// Allocate space for device copies of data
hipMalloc((void**) &d_a, size);
hipMalloc((void**) &d_b, size);
hipMalloc((void**) &d_c, size);
// Allocate space for host copies of input values (a, b, c arrays)
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
// Setup integers
random_ints(a, N);
random_ints(b, N);
// Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Launch add() on device
add<<<N,1>>>(d_a, d_b, d_c);
// Copy result to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Print out results
printf("\nResults of parallel GPU addition across %d elements:\n", N);
for (int i=0; i < N; i++) {
int sum = a[i] + b[i];
if (c[i] == sum) {
printf("%4d: %6d + %6d = %6d\n", i, a[i], b[i], c[i]);
}
else {
printf("%4d: %6d + %6d != %6d ERROR, should be %d", i, a[i], b[i], c[i], sum);
}
}
// Cleanup
free(a); free(b); free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "vectoradd_par.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 32767(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-32768, %ecx # imm = 0x8000
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r12d, %r12d
movl $.L.str, %edi
movl $2048, %esi # imm = 0x800
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 32767(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-32768, %ecx # imm = 0x8000
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_1
# %bb.2: # %.lr.ph.i45.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i45
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 32767(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-32768, %ecx # imm = 0x8000
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit49
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 511(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
movl $512, %esi # imm = 0x200
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
movl $.L.str.3, %edi
movl %r12d, %esi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
.LBB2_10: # in Loop: Header=BB2_7 Depth=1
incq %r12
cmpq $512, %r12 # imm = 0x200
je .LBB2_11
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %ecx
leal (%rcx,%rdx), %r9d
movl (%r15,%r12,4), %r8d
cmpl %r9d, %r8d
jne .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movl $.L.str.2, %edi
movl %r12d, %esi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
jmp .LBB2_10
.LBB2_11:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Total integer space size is %d bytes\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nResults of parallel GPU addition across %d elements:\n"
.size .L.str.1, 55
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4d: %6d + %6d = %6d\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%4d: %6d + %6d != %6d ERROR, should be %d"
.size .L.str.3, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00140419_00000000-6_vectoradd_par.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
cltd
shrl $17, %edx
addl %edx, %eax
andl $32767, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Total integer space size is %d bytes\n"
.align 8
.LC1:
.string "\nResults of parallel GPU addition across %d elements:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%4d: %6d + %6d = %6d\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "%4d: %6d + %6d != %6d ERROR, should be %d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2048, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $512, %esi
movq %r12, %rdi
call _Z11random_intsPii
movl $512, %esi
movq %rbp, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $2048, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L20:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $512, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r14
leaq .LC2(%rip), %r15
jmp .L23
.L27:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L29:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
addq $1, %rbx
cmpq $512, %rbx
je .L28
.L23:
movl %ebx, %edx
movl (%r12,%rbx,4), %ecx
movl 0(%rbp,%rbx,4), %r8d
leal (%rcx,%r8), %eax
movl 0(%r13,%rbx,4), %r9d
cmpl %eax, %r9d
je .L29
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L28:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectoradd_par.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 32767(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-32768, %ecx # imm = 0x8000
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r12d, %r12d
movl $.L.str, %edi
movl $2048, %esi # imm = 0x800
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 32767(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-32768, %ecx # imm = 0x8000
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_1
# %bb.2: # %.lr.ph.i45.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i45
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 32767(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-32768, %ecx # imm = 0x8000
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit49
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 511(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
movl $512, %esi # imm = 0x200
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
movl $.L.str.3, %edi
movl %r12d, %esi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
.LBB2_10: # in Loop: Header=BB2_7 Depth=1
incq %r12
cmpq $512, %r12 # imm = 0x200
je .LBB2_11
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %ecx
leal (%rcx,%rdx), %r9d
movl (%r15,%r12,4), %r8d
cmpl %r9d, %r8d
jne .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movl $.L.str.2, %edi
movl %r12d, %esi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
jmp .LBB2_10
.LBB2_11:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Total integer space size is %d bytes\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nResults of parallel GPU addition across %d elements:\n"
.size .L.str.1, 55
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4d: %6d + %6d = %6d\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%4d: %6d + %6d != %6d ERROR, should be %d"
.size .L.str.3, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define O_CHANNELS 5
void __global__ sconv_packed_fwd_row_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *src_base = v_src+z*w*h;
float *inp = _inp + (ty+tz*by)*(w+2);
inp[x+1] = src_base[x+y*w];
inp[0] = 0.f;
inp[w+1] = 0.f;
__syncthreads();
float *dst_base = v_dst+z*O_CHANNELS*w*h;
dst_base[x+y*w] = inp[x+2] - inp[x];
dst_base[x+(y+h)*w] = inp[x+2]+2*inp[x+1]+inp[x];
}
void __global__ sconv_packed_fwd_col_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp = _inp + (tx+tz*bx)*2*(h+2);
float *inp2 = inp+h+2;
float *dst_base = v_dst+z*O_CHANNELS*w*h;
inp[y+1] = dst_base[x+y*h];
inp2[y+1]= dst_base[x+(y+w)*h];
inp[0] = 0.f;
inp2[0] = 0.f;
inp[h+1] = 0.f;
inp2[h+1] = 0.f;
__syncthreads();
dst_base[x+y*w] = v_src[x+(y+z*h)*w];
dst_base[x+(y+h)*w] = inp[y+2]-inp[y];
dst_base[x+(y+h*3)*w] = inp2[y+2]-inp2[y];
dst_base[x+(y+h*2)*w] = inp[y+2]+inp[y+1]*2+inp[y];
dst_base[x+(y+h*4)*w] = inp2[y+2]+inp2[y+1]*2+inp2[y]; }
void __global__ sconv_packed_bwd_col_f32_ker(
float *v_dedx, float *v_tmp, float *v_dedy, int w, int h, int bsize) {
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp0 = _inp + (tx+tz*bx)*4*(h+2);
float *inp1 = inp0+h+2;
float *inp2 = inp0+2*(h+2);
float *inp3 = inp0+3*(h+2);
float *dedy_base = v_dedy+z*O_CHANNELS*w*h;
v_dedx[x+(y+z*h)*w] = dedy_base[x+y*h];
inp0[y+1]= dedy_base[x+(y+w)*h];
inp1[y+1]= dedy_base[x+(y+w*2)*h];
inp2[y+1]= dedy_base[x+(y+w*3)*h];
inp3[y+1]= dedy_base[x+(y+w*4)*h];
inp0[0] = 0.f; inp0[h+1]=0.f;
inp1[0] = 0.f; inp1[h+1]=0.f;
inp2[0] = 0.f; inp2[h+1]=0.f;
inp3[0] = 0.f; inp3[h+1]=0.f;
__syncthreads();
float *tmp_base = v_tmp+z*h*w*2;
tmp_base[x+y*w] = inp0[y]-inp0[y+2]+inp1[y+2]+inp1[y+1]*2+inp1[y];
tmp_base[x+(y+h)*w] = inp2[y]-inp2[y+2]+inp3[y+2]+inp3[y+1]*2+inp3[y];
}
void __global__ sconv_packed_bwd_row_f32_ker(
float *v_dedx, float *v_tmp, int w, int h, int bsize) {
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *tmp_base = v_tmp+z*w*h*2;
float *inp0 = _inp + (ty+tz*by)*2*(w+2);
float *inp1 = inp0 + w+2;
inp0[x+1] = tmp_base[x+y*w];
inp1[x+1] = tmp_base[x+(y+h)*w];
inp0[0] = 0.f;
inp0[w+1] = 0.f;
inp1[0] = 0.f;
inp1[w+1] = 0.f;
__syncthreads();
v_dedx[x+(y+z*h)*w] +=
inp0[x]-inp0[x+2]+inp1[x+2]+inp1[x+1]*2+inp1[x];
} | .file "tmpxft_0003c71b_00000000-6_simple_conv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii
.type _Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii, @function
_Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28sconv_packed_fwd_row_f32_kerPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii, .-_Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii
.globl _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.type _Z28sconv_packed_fwd_row_f32_kerPfS_iii, @function
_Z28sconv_packed_fwd_row_f32_kerPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28sconv_packed_fwd_row_f32_kerPfS_iii, .-_Z28sconv_packed_fwd_row_f32_kerPfS_iii
.globl _Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii
.type _Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii, @function
_Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28sconv_packed_fwd_col_f32_kerPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii, .-_Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii
.globl _Z28sconv_packed_fwd_col_f32_kerPfS_iii
.type _Z28sconv_packed_fwd_col_f32_kerPfS_iii, @function
_Z28sconv_packed_fwd_col_f32_kerPfS_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z28sconv_packed_fwd_col_f32_kerPfS_iii, .-_Z28sconv_packed_fwd_col_f32_kerPfS_iii
.globl _Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii
.type _Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii, @function
_Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii, .-_Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii
.globl _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.type _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, @function
_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, .-_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.globl _Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii
.type _Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii, @function
_Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28sconv_packed_bwd_row_f32_kerPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii, .-_Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii
.globl _Z28sconv_packed_bwd_row_f32_kerPfS_iii
.type _Z28sconv_packed_bwd_row_f32_kerPfS_iii, @function
_Z28sconv_packed_bwd_row_f32_kerPfS_iii:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z28sconv_packed_bwd_row_f32_kerPfS_iii, .-_Z28sconv_packed_bwd_row_f32_kerPfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28sconv_packed_bwd_row_f32_kerPfS_iii"
.align 8
.LC1:
.string "_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii"
.align 8
.LC2:
.string "_Z28sconv_packed_fwd_col_f32_kerPfS_iii"
.align 8
.LC3:
.string "_Z28sconv_packed_fwd_row_f32_kerPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28sconv_packed_bwd_row_f32_kerPfS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z28sconv_packed_fwd_col_f32_kerPfS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z28sconv_packed_fwd_row_f32_kerPfS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define O_CHANNELS 5
void __global__ sconv_packed_fwd_row_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *src_base = v_src+z*w*h;
float *inp = _inp + (ty+tz*by)*(w+2);
inp[x+1] = src_base[x+y*w];
inp[0] = 0.f;
inp[w+1] = 0.f;
__syncthreads();
float *dst_base = v_dst+z*O_CHANNELS*w*h;
dst_base[x+y*w] = inp[x+2] - inp[x];
dst_base[x+(y+h)*w] = inp[x+2]+2*inp[x+1]+inp[x];
}
void __global__ sconv_packed_fwd_col_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp = _inp + (tx+tz*bx)*2*(h+2);
float *inp2 = inp+h+2;
float *dst_base = v_dst+z*O_CHANNELS*w*h;
inp[y+1] = dst_base[x+y*h];
inp2[y+1]= dst_base[x+(y+w)*h];
inp[0] = 0.f;
inp2[0] = 0.f;
inp[h+1] = 0.f;
inp2[h+1] = 0.f;
__syncthreads();
dst_base[x+y*w] = v_src[x+(y+z*h)*w];
dst_base[x+(y+h)*w] = inp[y+2]-inp[y];
dst_base[x+(y+h*3)*w] = inp2[y+2]-inp2[y];
dst_base[x+(y+h*2)*w] = inp[y+2]+inp[y+1]*2+inp[y];
dst_base[x+(y+h*4)*w] = inp2[y+2]+inp2[y+1]*2+inp2[y]; }
void __global__ sconv_packed_bwd_col_f32_ker(
float *v_dedx, float *v_tmp, float *v_dedy, int w, int h, int bsize) {
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp0 = _inp + (tx+tz*bx)*4*(h+2);
float *inp1 = inp0+h+2;
float *inp2 = inp0+2*(h+2);
float *inp3 = inp0+3*(h+2);
float *dedy_base = v_dedy+z*O_CHANNELS*w*h;
v_dedx[x+(y+z*h)*w] = dedy_base[x+y*h];
inp0[y+1]= dedy_base[x+(y+w)*h];
inp1[y+1]= dedy_base[x+(y+w*2)*h];
inp2[y+1]= dedy_base[x+(y+w*3)*h];
inp3[y+1]= dedy_base[x+(y+w*4)*h];
inp0[0] = 0.f; inp0[h+1]=0.f;
inp1[0] = 0.f; inp1[h+1]=0.f;
inp2[0] = 0.f; inp2[h+1]=0.f;
inp3[0] = 0.f; inp3[h+1]=0.f;
__syncthreads();
float *tmp_base = v_tmp+z*h*w*2;
tmp_base[x+y*w] = inp0[y]-inp0[y+2]+inp1[y+2]+inp1[y+1]*2+inp1[y];
tmp_base[x+(y+h)*w] = inp2[y]-inp2[y+2]+inp3[y+2]+inp3[y+1]*2+inp3[y];
}
void __global__ sconv_packed_bwd_row_f32_ker(
float *v_dedx, float *v_tmp, int w, int h, int bsize) {
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *tmp_base = v_tmp+z*w*h*2;
float *inp0 = _inp + (ty+tz*by)*2*(w+2);
float *inp1 = inp0 + w+2;
inp0[x+1] = tmp_base[x+y*w];
inp1[x+1] = tmp_base[x+(y+h)*w];
inp0[0] = 0.f;
inp0[w+1] = 0.f;
inp1[0] = 0.f;
inp1[w+1] = 0.f;
__syncthreads();
v_dedx[x+(y+z*h)*w] +=
inp0[x]-inp0[x+2]+inp1[x+2]+inp1[x+1]*2+inp1[x];
} | #include <hip/hip_runtime.h>
#define O_CHANNELS 5
void __global__ sconv_packed_fwd_row_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *src_base = v_src+z*w*h;
float *inp = _inp + (ty+tz*by)*(w+2);
inp[x+1] = src_base[x+y*w];
inp[0] = 0.f;
inp[w+1] = 0.f;
__syncthreads();
float *dst_base = v_dst+z*O_CHANNELS*w*h;
dst_base[x+y*w] = inp[x+2] - inp[x];
dst_base[x+(y+h)*w] = inp[x+2]+2*inp[x+1]+inp[x];
}
void __global__ sconv_packed_fwd_col_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp = _inp + (tx+tz*bx)*2*(h+2);
float *inp2 = inp+h+2;
float *dst_base = v_dst+z*O_CHANNELS*w*h;
inp[y+1] = dst_base[x+y*h];
inp2[y+1]= dst_base[x+(y+w)*h];
inp[0] = 0.f;
inp2[0] = 0.f;
inp[h+1] = 0.f;
inp2[h+1] = 0.f;
__syncthreads();
dst_base[x+y*w] = v_src[x+(y+z*h)*w];
dst_base[x+(y+h)*w] = inp[y+2]-inp[y];
dst_base[x+(y+h*3)*w] = inp2[y+2]-inp2[y];
dst_base[x+(y+h*2)*w] = inp[y+2]+inp[y+1]*2+inp[y];
dst_base[x+(y+h*4)*w] = inp2[y+2]+inp2[y+1]*2+inp2[y]; }
void __global__ sconv_packed_bwd_col_f32_ker(
float *v_dedx, float *v_tmp, float *v_dedy, int w, int h, int bsize) {
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp0 = _inp + (tx+tz*bx)*4*(h+2);
float *inp1 = inp0+h+2;
float *inp2 = inp0+2*(h+2);
float *inp3 = inp0+3*(h+2);
float *dedy_base = v_dedy+z*O_CHANNELS*w*h;
v_dedx[x+(y+z*h)*w] = dedy_base[x+y*h];
inp0[y+1]= dedy_base[x+(y+w)*h];
inp1[y+1]= dedy_base[x+(y+w*2)*h];
inp2[y+1]= dedy_base[x+(y+w*3)*h];
inp3[y+1]= dedy_base[x+(y+w*4)*h];
inp0[0] = 0.f; inp0[h+1]=0.f;
inp1[0] = 0.f; inp1[h+1]=0.f;
inp2[0] = 0.f; inp2[h+1]=0.f;
inp3[0] = 0.f; inp3[h+1]=0.f;
__syncthreads();
float *tmp_base = v_tmp+z*h*w*2;
tmp_base[x+y*w] = inp0[y]-inp0[y+2]+inp1[y+2]+inp1[y+1]*2+inp1[y];
tmp_base[x+(y+h)*w] = inp2[y]-inp2[y+2]+inp3[y+2]+inp3[y+1]*2+inp3[y];
}
void __global__ sconv_packed_bwd_row_f32_ker(
float *v_dedx, float *v_tmp, int w, int h, int bsize) {
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *tmp_base = v_tmp+z*w*h*2;
float *inp0 = _inp + (ty+tz*by)*2*(w+2);
float *inp1 = inp0 + w+2;
inp0[x+1] = tmp_base[x+y*w];
inp1[x+1] = tmp_base[x+(y+h)*w];
inp0[0] = 0.f;
inp0[w+1] = 0.f;
inp1[0] = 0.f;
inp1[w+1] = 0.f;
__syncthreads();
v_dedx[x+(y+z*h)*w] +=
inp0[x]-inp0[x+2]+inp1[x+2]+inp1[x+1]*2+inp1[x];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define O_CHANNELS 5
void __global__ sconv_packed_fwd_row_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *src_base = v_src+z*w*h;
float *inp = _inp + (ty+tz*by)*(w+2);
inp[x+1] = src_base[x+y*w];
inp[0] = 0.f;
inp[w+1] = 0.f;
__syncthreads();
float *dst_base = v_dst+z*O_CHANNELS*w*h;
dst_base[x+y*w] = inp[x+2] - inp[x];
dst_base[x+(y+h)*w] = inp[x+2]+2*inp[x+1]+inp[x];
}
void __global__ sconv_packed_fwd_col_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp = _inp + (tx+tz*bx)*2*(h+2);
float *inp2 = inp+h+2;
float *dst_base = v_dst+z*O_CHANNELS*w*h;
inp[y+1] = dst_base[x+y*h];
inp2[y+1]= dst_base[x+(y+w)*h];
inp[0] = 0.f;
inp2[0] = 0.f;
inp[h+1] = 0.f;
inp2[h+1] = 0.f;
__syncthreads();
dst_base[x+y*w] = v_src[x+(y+z*h)*w];
dst_base[x+(y+h)*w] = inp[y+2]-inp[y];
dst_base[x+(y+h*3)*w] = inp2[y+2]-inp2[y];
dst_base[x+(y+h*2)*w] = inp[y+2]+inp[y+1]*2+inp[y];
dst_base[x+(y+h*4)*w] = inp2[y+2]+inp2[y+1]*2+inp2[y]; }
void __global__ sconv_packed_bwd_col_f32_ker(
float *v_dedx, float *v_tmp, float *v_dedy, int w, int h, int bsize) {
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp0 = _inp + (tx+tz*bx)*4*(h+2);
float *inp1 = inp0+h+2;
float *inp2 = inp0+2*(h+2);
float *inp3 = inp0+3*(h+2);
float *dedy_base = v_dedy+z*O_CHANNELS*w*h;
v_dedx[x+(y+z*h)*w] = dedy_base[x+y*h];
inp0[y+1]= dedy_base[x+(y+w)*h];
inp1[y+1]= dedy_base[x+(y+w*2)*h];
inp2[y+1]= dedy_base[x+(y+w*3)*h];
inp3[y+1]= dedy_base[x+(y+w*4)*h];
inp0[0] = 0.f; inp0[h+1]=0.f;
inp1[0] = 0.f; inp1[h+1]=0.f;
inp2[0] = 0.f; inp2[h+1]=0.f;
inp3[0] = 0.f; inp3[h+1]=0.f;
__syncthreads();
float *tmp_base = v_tmp+z*h*w*2;
tmp_base[x+y*w] = inp0[y]-inp0[y+2]+inp1[y+2]+inp1[y+1]*2+inp1[y];
tmp_base[x+(y+h)*w] = inp2[y]-inp2[y+2]+inp3[y+2]+inp3[y+1]*2+inp3[y];
}
void __global__ sconv_packed_bwd_row_f32_ker(
float *v_dedx, float *v_tmp, int w, int h, int bsize) {
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *tmp_base = v_tmp+z*w*h*2;
float *inp0 = _inp + (ty+tz*by)*2*(w+2);
float *inp1 = inp0 + w+2;
inp0[x+1] = tmp_base[x+y*w];
inp1[x+1] = tmp_base[x+(y+h)*w];
inp0[0] = 0.f;
inp0[w+1] = 0.f;
inp1[0] = 0.f;
inp1[w+1] = 0.f;
__syncthreads();
v_dedx[x+(y+z*h)*w] +=
inp0[x]-inp0[x+2]+inp1[x+2]+inp1[x+1]*2+inp1[x];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.globl _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.p2align 8
.type _Z28sconv_packed_fwd_row_f32_kerPfS_iii,@function
_Z28sconv_packed_fwd_row_f32_kerPfS_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s2, 16
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s14, s6, v[5:6]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s5, v2
v_cmp_gt_i32_e64 s3, s7, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_mul_i32 s7, s5, s4
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v6, s7, v3
v_mad_u64_u32 v[8:9], null, v2, s4, v[1:2]
v_mad_u32_u24 v0, v0, s6, v5
s_mul_i32 s7, s7, 5
v_add_nc_u32_e32 v11, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_add_i32 s2, s4, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v4, v8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
v_mul_lo_u32 v0, v0, s2
global_load_b32 v4, v[6:7], off
v_mov_b32_e32 v6, 0
v_lshl_add_u32 v5, v0, 2, 0
v_mul_lo_u32 v0, s7, v3
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v7, v1, 2, v5
v_lshl_add_u32 v10, s4, 2, v5
s_waitcnt vmcnt(0)
ds_store_b32 v7, v4 offset:4
ds_store_b32 v5, v6
ds_store_b32 v10, v6 offset:4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v7 offset1:1
ds_load_b32 v6, v7 offset:8
s_waitcnt lgkmcnt(1)
v_mad_u64_u32 v[4:5], null, v11, s4, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v11, v6, v2 :: v_dual_fmac_f32 v6, 2.0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v6, v2, v6
v_add_co_u32 v7, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, v10, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, v7, v4
v_add_co_ci_u32_e32 v3, vcc_lo, v10, v5, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v11, off
global_store_b32 v[2:3], v6, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28sconv_packed_fwd_row_f32_kerPfS_iii, .Lfunc_end0-_Z28sconv_packed_fwd_row_f32_kerPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z28sconv_packed_fwd_col_f32_kerPfS_iii
.globl _Z28sconv_packed_fwd_col_f32_kerPfS_iii
.p2align 8
.type _Z28sconv_packed_fwd_col_f32_kerPfS_iii,@function
_Z28sconv_packed_fwd_col_f32_kerPfS_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x18
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 20, 10
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[1:2], null, s14, s6, v[3:4]
v_mad_u64_u32 v[5:6], null, s15, s2, v[4:5]
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
v_cmp_gt_i32_e64 s3, s7, v5
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
v_mul_lo_u32 v2, v5, s5
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u32_u24 v3, v4, s6, v3
v_lshlrev_b32_e32 v15, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v2, s4
v_mad_u64_u32 v[7:8], null, v0, s5, v[1:2]
v_add_nc_u32_e32 v8, s4, v0
v_add_nc_u32_e32 v4, v2, v0
v_mad_u64_u32 v[9:10], null, v8, s5, v[1:2]
v_lshl_add_u32 v5, v5, 2, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v6, vcc_lo
v_lshlrev_b64 v[5:6], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, v13, v7
v_add_co_ci_u32_e32 v8, vcc_lo, v14, v8, vcc_lo
s_lshl_b32 s0, s5, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, v13, v5
v_add_co_ci_u32_e32 v6, vcc_lo, v14, v6, vcc_lo
s_clause 0x1
global_load_b32 v7, v[7:8], off
global_load_b32 v5, v[5:6], off
s_add_i32 s1, s0, 4
v_mov_b32_e32 v9, 0
v_mul_lo_u32 v6, s1, v3
v_mad_u64_u32 v[2:3], null, v4, s4, v[1:2]
s_lshl_b32 s1, s5, 2
v_mov_b32_e32 v4, 0
v_add_nc_u32_e32 v8, 4, v15
s_add_i32 s6, s1, 4
v_add_nc_u32_e32 v21, 8, v15
v_lshl_add_u32 v16, v6, 2, 0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v17, v16, s1, 8
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_nc_u32_e32 v18, v16, v8
v_mov_b32_e32 v6, 0
v_add_nc_u32_e32 v10, s6, v16
v_add_nc_u32_e32 v19, v17, v8
v_add_nc_u32_e32 v8, s6, v17
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_nc_u32_e32 v22, v16, v21
s_waitcnt vmcnt(1)
ds_store_b32 v18, v7
s_waitcnt vmcnt(0)
ds_store_b32 v19, v5
ds_store_b32 v16, v4
ds_store_2addr_b32 v10, v6, v9 offset1:1
ds_store_b32 v8, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v20, v[2:3], off
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
v_add_nc_u32_e32 v3, s5, v0
v_mad_u64_u32 v[4:5], null, s5, 3, v[0:1]
v_add_nc_u32_e32 v9, s0, v0
v_add_nc_u32_e32 v0, s1, v0
v_add_nc_u32_e32 v16, v16, v15
v_mad_u64_u32 v[5:6], null, v3, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[7:8], null, v9, s4, v[1:2]
v_mad_u64_u32 v[9:10], null, v0, s4, v[1:2]
v_mad_u64_u32 v[11:12], null, v4, s4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v15, v17, v15
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[2:3], 2, v[5:6]
v_lshlrev_b64 v[4:5], 2, v[7:8]
v_lshlrev_b64 v[6:7], 2, v[9:10]
v_add_nc_u32_e32 v10, v17, v21
v_lshlrev_b64 v[8:9], 2, v[11:12]
ds_load_b32 v11, v22
ds_load_b32 v12, v16
ds_load_b32 v10, v10
ds_load_b32 v15, v15
ds_load_b32 v16, v18
ds_load_b32 v17, v19
v_add_co_u32 v0, vcc_lo, v13, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v14, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v13, v2
v_add_co_ci_u32_e32 v3, vcc_lo, v14, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, v13, v8
v_add_co_ci_u32_e32 v9, vcc_lo, v14, v9, vcc_lo
v_add_co_u32 v4, vcc_lo, v13, v4
v_add_co_ci_u32_e32 v5, vcc_lo, v14, v5, vcc_lo
s_waitcnt lgkmcnt(2)
v_dual_sub_f32 v18, v11, v12 :: v_dual_sub_f32 v19, v10, v15
s_waitcnt lgkmcnt(0)
v_dual_fmac_f32 v11, 2.0, v16 :: v_dual_fmac_f32 v10, 2.0, v17
v_add_co_u32 v6, vcc_lo, v13, v6
v_add_co_ci_u32_e32 v7, vcc_lo, v14, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_add_f32 v10, v15, v10 :: v_dual_add_f32 v11, v12, v11
s_waitcnt vmcnt(0)
s_clause 0x4
global_store_b32 v[0:1], v20, off
global_store_b32 v[2:3], v18, off
global_store_b32 v[8:9], v19, off
global_store_b32 v[4:5], v11, off
global_store_b32 v[6:7], v10, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28sconv_packed_fwd_col_f32_kerPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z28sconv_packed_fwd_col_f32_kerPfS_iii, .Lfunc_end1-_Z28sconv_packed_fwd_col_f32_kerPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.globl _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.p2align 8
.type _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii,@function
_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s7, s[0:1], 0x20
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 20, 10
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[1:2], null, s14, s6, v[3:4]
v_mad_u64_u32 v[5:6], null, s15, s2, v[4:5]
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
v_cmp_gt_i32_e64 s3, s7, v5
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
v_mul_lo_u32 v16, v5, s5
s_load_b64 s[2:3], s[0:1], 0x10
v_lshl_add_u32 v10, s4, 2, v0
s_lshl_b32 s7, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v14, s7, v0
v_mul_lo_u32 v2, v16, s4
v_add_nc_u32_e32 v12, v16, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, v2, 2, v2
v_mad_u64_u32 v[7:8], null, v0, s5, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v6, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
v_add_co_u32 v5, vcc_lo, v2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, v17, v8, vcc_lo
v_add_nc_u32_e32 v8, s4, v0
global_load_b32 v18, v[5:6], off
v_mad_u64_u32 v[5:6], null, s4, 3, v[0:1]
v_mad_u64_u32 v[6:7], null, v8, s5, v[1:2]
v_mad_u64_u32 v[8:9], null, v10, s5, v[1:2]
v_mad_u64_u32 v[10:11], null, v12, s4, v[1:2]
v_mad_u64_u32 v[12:13], null, v14, s5, v[1:2]
v_mad_u64_u32 v[14:15], null, v5, s5, v[1:2]
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 2, v[6:7]
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_lshlrev_b64 v[7:8], 2, v[8:9]
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v11, vcc_lo
v_add_co_u32 v5, vcc_lo, v2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, v17, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, v2, v12
v_add_co_ci_u32_e32 v12, vcc_lo, v17, v13, vcc_lo
v_add_co_u32 v13, vcc_lo, v2, v14
v_add_co_ci_u32_e32 v14, vcc_lo, v17, v15, vcc_lo
v_add_co_u32 v7, vcc_lo, v2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, v17, v8, vcc_lo
v_mad_u32_u24 v2, v4, s6, v3
s_add_i32 s0, s5, 2
s_lshl_b32 s1, s5, 2
v_mov_b32_e32 v15, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v4, s0, v2
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
v_add_nc_u32_e32 v3, s5, v0
s_add_i32 s5, s1, 4
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v18, off
s_clause 0x3
global_load_b32 v9, v[5:6], off
global_load_b32 v10, v[11:12], off
global_load_b32 v11, v[13:14], off
global_load_b32 v8, v[7:8], off
v_dual_mov_b32 v13, 0 :: v_dual_lshlrev_b32 v12, 2, v0
v_mov_b32_e32 v14, 0
v_lshl_add_u32 v0, v4, 4, 0
v_mad_u64_u32 v[4:5], null, v3, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v17, 4, v12
v_add_nc_u32_e32 v18, 8, v12
v_add3_u32 v1, v0, s1, 8
v_lshl_add_u32 v3, s0, 3, v0
v_add_nc_u32_e32 v19, v0, v12
v_add_nc_u32_e32 v5, v0, v17
v_add_nc_u32_e32 v20, v0, v18
v_mad_u64_u32 v[6:7], null, s0, 12, v[0:1]
v_add_nc_u32_e32 v21, v1, v17
v_add_nc_u32_e32 v22, v3, v17
v_add_nc_u32_e32 v26, v3, v12
v_add_nc_u32_e32 v27, v3, v18
v_add_nc_u32_e32 v7, s5, v0
v_add_nc_u32_e32 v23, s5, v1
v_add_nc_u32_e32 v17, v6, v17
v_add_nc_u32_e32 v24, s5, v3
v_add_nc_u32_e32 v25, v1, v18
v_add_nc_u32_e32 v28, s5, v6
v_add_nc_u32_e32 v1, v1, v12
s_waitcnt vmcnt(3)
ds_store_b32 v5, v9
s_waitcnt vmcnt(2)
ds_store_b32 v21, v10
s_waitcnt vmcnt(1)
ds_store_b32 v22, v11
s_waitcnt vmcnt(0)
ds_store_b32 v17, v8
ds_store_b32 v0, v13
ds_store_2addr_b32 v7, v14, v15 offset1:1
ds_store_b32 v23, v13
ds_store_b32 v3, v13
ds_store_b32 v24, v13
ds_store_b32 v6, v13
ds_store_b32 v28, v13
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v7, v19
ds_load_b32 v8, v20
ds_load_b32 v9, v26
ds_load_b32 v10, v27
v_add_nc_u32_e32 v3, v6, v18
ds_load_b32 v11, v25
ds_load_b32 v13, v3
ds_load_b32 v14, v1
v_mul_lo_u32 v0, s7, v16
ds_load_b32 v15, v21
ds_load_b32 v16, v17
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(7)
v_sub_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(4)
v_dual_sub_f32 v8, v9, v10 :: v_dual_add_f32 v7, v7, v11
s_waitcnt lgkmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v8, v8, v13
v_add_co_u32 v9, vcc_lo, s2, v0
s_waitcnt lgkmcnt(1)
v_dual_fmac_f32 v7, 2.0, v15 :: v_dual_add_nc_u32 v6, v6, v12
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v9, v2
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(1)
v_fmac_f32_e32 v8, 2.0, v16
v_add_co_ci_u32_e32 v1, vcc_lo, v10, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v9, v4
v_add_f32_e32 v4, v14, v7
v_add_co_ci_u32_e32 v3, vcc_lo, v10, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v8
s_clause 0x1
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v5, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 29
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, .Lfunc_end2-_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z28sconv_packed_bwd_row_f32_kerPfS_iii
.globl _Z28sconv_packed_bwd_row_f32_kerPfS_iii
.p2align 8
.type _Z28sconv_packed_bwd_row_f32_kerPfS_iii,@function
_Z28sconv_packed_bwd_row_f32_kerPfS_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x18
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s2, 16
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s14, s6, v[4:5]
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s5, v2
v_cmp_gt_i32_e64 s3, s7, v5
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB3_2
v_mul_lo_u32 v3, v5, s5
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[7:8], null, v2, s4, v[1:2]
v_add_nc_u32_e32 v8, s5, v2
v_mad_u32_u24 v0, v0, s6, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v5, v3, s4
v_mad_u64_u32 v[9:10], null, v8, s4, v[1:2]
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b32_e32 v5, 1, v5
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[5:6], 2, v[9:10]
v_add_co_u32 v7, vcc_lo, v11, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, v12, v8, vcc_lo
s_lshl_b32 s2, s4, 1
v_add_co_u32 v5, vcc_lo, v11, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, v12, v6, vcc_lo
s_clause 0x1
global_load_b32 v7, v[7:8], off
global_load_b32 v5, v[5:6], off
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v11, 0
v_mad_u64_u32 v[2:3], null, v4, s4, v[1:2]
s_add_i32 s2, s2, 4
v_lshlrev_b32_e32 v4, 2, v1
v_mul_lo_u32 v0, s2, v0
s_lshl_b32 s2, s4, 2
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v10, 4, v4
v_lshl_add_u32 v8, v0, 2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add3_u32 v12, v8, s2, 8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, v8, v10
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_i32 s2, s2, 4
v_add_nc_u32_e32 v10, v12, v10
v_add_nc_u32_e32 v3, s2, v8
v_add_nc_u32_e32 v13, s2, v12
s_waitcnt vmcnt(1)
ds_store_b32 v2, v7
s_waitcnt vmcnt(0)
ds_store_b32 v10, v5
ds_store_b32 v8, v6
ds_store_2addr_b32 v3, v9, v11 offset1:1
ds_store_b32 v13, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v2, v[0:1], off
v_add_nc_u32_e32 v3, 8, v4
v_add_nc_u32_e32 v5, v8, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v6, v8, v3
ds_load_b32 v5, v5
ds_load_b32 v6, v6
v_add_nc_u32_e32 v3, v12, v3
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v5, v5, v6 :: v_dual_add_nc_u32 v4, v12, v4
ds_load_b32 v3, v3
ds_load_b32 v4, v4
ds_load_b32 v7, v10
s_waitcnt lgkmcnt(2)
v_add_f32_e32 v3, v5, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, 2.0, v7
v_add_f32_e32 v3, v4, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28sconv_packed_bwd_row_f32_kerPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z28sconv_packed_bwd_row_f32_kerPfS_iii, .Lfunc_end3-_Z28sconv_packed_bwd_row_f32_kerPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28sconv_packed_fwd_row_f32_kerPfS_iii.kd
.uniform_work_group_size: 1
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amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define O_CHANNELS 5
void __global__ sconv_packed_fwd_row_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *src_base = v_src+z*w*h;
float *inp = _inp + (ty+tz*by)*(w+2);
inp[x+1] = src_base[x+y*w];
inp[0] = 0.f;
inp[w+1] = 0.f;
__syncthreads();
float *dst_base = v_dst+z*O_CHANNELS*w*h;
dst_base[x+y*w] = inp[x+2] - inp[x];
dst_base[x+(y+h)*w] = inp[x+2]+2*inp[x+1]+inp[x];
}
void __global__ sconv_packed_fwd_col_f32_ker(
float *v_dst, float *v_src, int w, int h, int bsize) {
/*
ALWAYS ASSUME:
w,h both less or equal than 512 and is power of 2
*/
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp = _inp + (tx+tz*bx)*2*(h+2);
float *inp2 = inp+h+2;
float *dst_base = v_dst+z*O_CHANNELS*w*h;
inp[y+1] = dst_base[x+y*h];
inp2[y+1]= dst_base[x+(y+w)*h];
inp[0] = 0.f;
inp2[0] = 0.f;
inp[h+1] = 0.f;
inp2[h+1] = 0.f;
__syncthreads();
dst_base[x+y*w] = v_src[x+(y+z*h)*w];
dst_base[x+(y+h)*w] = inp[y+2]-inp[y];
dst_base[x+(y+h*3)*w] = inp2[y+2]-inp2[y];
dst_base[x+(y+h*2)*w] = inp[y+2]+inp[y+1]*2+inp[y];
dst_base[x+(y+h*4)*w] = inp2[y+2]+inp2[y+1]*2+inp2[y]; }
void __global__ sconv_packed_bwd_col_f32_ker(
float *v_dedx, float *v_tmp, float *v_dedy, int w, int h, int bsize) {
const int x = threadIdx.x + blockIdx.x*blockDim.x;
const int y = threadIdx.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int bx = blockDim.x;
const int tx = threadIdx.x;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *inp0 = _inp + (tx+tz*bx)*4*(h+2);
float *inp1 = inp0+h+2;
float *inp2 = inp0+2*(h+2);
float *inp3 = inp0+3*(h+2);
float *dedy_base = v_dedy+z*O_CHANNELS*w*h;
v_dedx[x+(y+z*h)*w] = dedy_base[x+y*h];
inp0[y+1]= dedy_base[x+(y+w)*h];
inp1[y+1]= dedy_base[x+(y+w*2)*h];
inp2[y+1]= dedy_base[x+(y+w*3)*h];
inp3[y+1]= dedy_base[x+(y+w*4)*h];
inp0[0] = 0.f; inp0[h+1]=0.f;
inp1[0] = 0.f; inp1[h+1]=0.f;
inp2[0] = 0.f; inp2[h+1]=0.f;
inp3[0] = 0.f; inp3[h+1]=0.f;
__syncthreads();
float *tmp_base = v_tmp+z*h*w*2;
tmp_base[x+y*w] = inp0[y]-inp0[y+2]+inp1[y+2]+inp1[y+1]*2+inp1[y];
tmp_base[x+(y+h)*w] = inp2[y]-inp2[y+2]+inp3[y+2]+inp3[y+1]*2+inp3[y];
}
void __global__ sconv_packed_bwd_row_f32_ker(
float *v_dedx, float *v_tmp, int w, int h, int bsize) {
const int x = threadIdx.x;
const int y = threadIdx.y + blockIdx.y*blockDim.y;
const int z = threadIdx.z + blockIdx.z*blockDim.z;
const int by = blockDim.y;
const int ty = threadIdx.y;
const int tz = threadIdx.z;
if(x>=w) return;
if(y>=h) return;
if(z>=bsize) return;
extern __shared__ float _inp[];
float *tmp_base = v_tmp+z*w*h*2;
float *inp0 = _inp + (ty+tz*by)*2*(w+2);
float *inp1 = inp0 + w+2;
inp0[x+1] = tmp_base[x+y*w];
inp1[x+1] = tmp_base[x+(y+h)*w];
inp0[0] = 0.f;
inp0[w+1] = 0.f;
inp1[0] = 0.f;
inp1[w+1] = 0.f;
__syncthreads();
v_dedx[x+(y+z*h)*w] +=
inp0[x]-inp0[x+2]+inp1[x+2]+inp1[x+1]*2+inp1[x];
} | .text
.file "simple_conv.hip"
.globl _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii # -- Begin function _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.p2align 4, 0x90
.type _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii,@function
_Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii: # @_Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28sconv_packed_fwd_row_f32_kerPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii, .Lfunc_end0-_Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii # -- Begin function _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.p2align 4, 0x90
.type _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii,@function
_Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii: # @_Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28sconv_packed_fwd_col_f32_kerPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii, .Lfunc_end1-_Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii # -- Begin function _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.p2align 4, 0x90
.type _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii,@function
_Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii: # @_Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii, .Lfunc_end2-_Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii # -- Begin function _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.p2align 4, 0x90
.type _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii,@function
_Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii: # @_Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28sconv_packed_bwd_row_f32_kerPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii, .Lfunc_end3-_Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28sconv_packed_fwd_row_f32_kerPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28sconv_packed_fwd_col_f32_kerPfS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28sconv_packed_bwd_row_f32_kerPfS_iii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28sconv_packed_fwd_row_f32_kerPfS_iii,@object # @_Z28sconv_packed_fwd_row_f32_kerPfS_iii
.section .rodata,"a",@progbits
.globl _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.p2align 3, 0x0
_Z28sconv_packed_fwd_row_f32_kerPfS_iii:
.quad _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.size _Z28sconv_packed_fwd_row_f32_kerPfS_iii, 8
.type _Z28sconv_packed_fwd_col_f32_kerPfS_iii,@object # @_Z28sconv_packed_fwd_col_f32_kerPfS_iii
.globl _Z28sconv_packed_fwd_col_f32_kerPfS_iii
.p2align 3, 0x0
_Z28sconv_packed_fwd_col_f32_kerPfS_iii:
.quad _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.size _Z28sconv_packed_fwd_col_f32_kerPfS_iii, 8
.type _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii,@object # @_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.globl _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.p2align 3, 0x0
_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii:
.quad _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.size _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, 8
.type _Z28sconv_packed_bwd_row_f32_kerPfS_iii,@object # @_Z28sconv_packed_bwd_row_f32_kerPfS_iii
.globl _Z28sconv_packed_bwd_row_f32_kerPfS_iii
.p2align 3, 0x0
_Z28sconv_packed_bwd_row_f32_kerPfS_iii:
.quad _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.size _Z28sconv_packed_bwd_row_f32_kerPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28sconv_packed_fwd_row_f32_kerPfS_iii"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z28sconv_packed_fwd_col_f32_kerPfS_iii"
.size .L__unnamed_2, 40
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii"
.size .L__unnamed_3, 42
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z28sconv_packed_bwd_row_f32_kerPfS_iii"
.size .L__unnamed_4, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.addrsig_sym _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.addrsig_sym _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.addrsig_sym _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.addrsig_sym _Z28sconv_packed_fwd_col_f32_kerPfS_iii
.addrsig_sym _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.addrsig_sym _Z28sconv_packed_bwd_row_f32_kerPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003c71b_00000000-6_simple_conv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii
.type _Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii, @function
_Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28sconv_packed_fwd_row_f32_kerPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii, .-_Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii
.globl _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.type _Z28sconv_packed_fwd_row_f32_kerPfS_iii, @function
_Z28sconv_packed_fwd_row_f32_kerPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z28sconv_packed_fwd_row_f32_kerPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28sconv_packed_fwd_row_f32_kerPfS_iii, .-_Z28sconv_packed_fwd_row_f32_kerPfS_iii
.globl _Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii
.type _Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii, @function
_Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28sconv_packed_fwd_col_f32_kerPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii, .-_Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii
.globl _Z28sconv_packed_fwd_col_f32_kerPfS_iii
.type _Z28sconv_packed_fwd_col_f32_kerPfS_iii, @function
_Z28sconv_packed_fwd_col_f32_kerPfS_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z28sconv_packed_fwd_col_f32_kerPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z28sconv_packed_fwd_col_f32_kerPfS_iii, .-_Z28sconv_packed_fwd_col_f32_kerPfS_iii
.globl _Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii
.type _Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii, @function
_Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii, .-_Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii
.globl _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.type _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, @function
_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z28sconv_packed_bwd_col_f32_kerPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, .-_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.globl _Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii
.type _Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii, @function
_Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28sconv_packed_bwd_row_f32_kerPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii, .-_Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii
.globl _Z28sconv_packed_bwd_row_f32_kerPfS_iii
.type _Z28sconv_packed_bwd_row_f32_kerPfS_iii, @function
_Z28sconv_packed_bwd_row_f32_kerPfS_iii:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z28sconv_packed_bwd_row_f32_kerPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z28sconv_packed_bwd_row_f32_kerPfS_iii, .-_Z28sconv_packed_bwd_row_f32_kerPfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28sconv_packed_bwd_row_f32_kerPfS_iii"
.align 8
.LC1:
.string "_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii"
.align 8
.LC2:
.string "_Z28sconv_packed_fwd_col_f32_kerPfS_iii"
.align 8
.LC3:
.string "_Z28sconv_packed_fwd_row_f32_kerPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28sconv_packed_bwd_row_f32_kerPfS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z28sconv_packed_fwd_col_f32_kerPfS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z28sconv_packed_fwd_row_f32_kerPfS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple_conv.hip"
.globl _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii # -- Begin function _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.p2align 4, 0x90
.type _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii,@function
_Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii: # @_Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28sconv_packed_fwd_row_f32_kerPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii, .Lfunc_end0-_Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii # -- Begin function _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.p2align 4, 0x90
.type _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii,@function
_Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii: # @_Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28sconv_packed_fwd_col_f32_kerPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii, .Lfunc_end1-_Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii # -- Begin function _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.p2align 4, 0x90
.type _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii,@function
_Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii: # @_Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii, .Lfunc_end2-_Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii # -- Begin function _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.p2align 4, 0x90
.type _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii,@function
_Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii: # @_Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28sconv_packed_bwd_row_f32_kerPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii, .Lfunc_end3-_Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28sconv_packed_fwd_row_f32_kerPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28sconv_packed_fwd_col_f32_kerPfS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28sconv_packed_bwd_row_f32_kerPfS_iii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28sconv_packed_fwd_row_f32_kerPfS_iii,@object # @_Z28sconv_packed_fwd_row_f32_kerPfS_iii
.section .rodata,"a",@progbits
.globl _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.p2align 3, 0x0
_Z28sconv_packed_fwd_row_f32_kerPfS_iii:
.quad _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.size _Z28sconv_packed_fwd_row_f32_kerPfS_iii, 8
.type _Z28sconv_packed_fwd_col_f32_kerPfS_iii,@object # @_Z28sconv_packed_fwd_col_f32_kerPfS_iii
.globl _Z28sconv_packed_fwd_col_f32_kerPfS_iii
.p2align 3, 0x0
_Z28sconv_packed_fwd_col_f32_kerPfS_iii:
.quad _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.size _Z28sconv_packed_fwd_col_f32_kerPfS_iii, 8
.type _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii,@object # @_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.globl _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.p2align 3, 0x0
_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii:
.quad _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.size _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii, 8
.type _Z28sconv_packed_bwd_row_f32_kerPfS_iii,@object # @_Z28sconv_packed_bwd_row_f32_kerPfS_iii
.globl _Z28sconv_packed_bwd_row_f32_kerPfS_iii
.p2align 3, 0x0
_Z28sconv_packed_bwd_row_f32_kerPfS_iii:
.quad _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.size _Z28sconv_packed_bwd_row_f32_kerPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28sconv_packed_fwd_row_f32_kerPfS_iii"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z28sconv_packed_fwd_col_f32_kerPfS_iii"
.size .L__unnamed_2, 40
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z28sconv_packed_bwd_col_f32_kerPfS_S_iii"
.size .L__unnamed_3, 42
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z28sconv_packed_bwd_row_f32_kerPfS_iii"
.size .L__unnamed_4, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__sconv_packed_fwd_row_f32_kerPfS_iii
.addrsig_sym _Z43__device_stub__sconv_packed_fwd_col_f32_kerPfS_iii
.addrsig_sym _Z43__device_stub__sconv_packed_bwd_col_f32_kerPfS_S_iii
.addrsig_sym _Z43__device_stub__sconv_packed_bwd_row_f32_kerPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28sconv_packed_fwd_row_f32_kerPfS_iii
.addrsig_sym _Z28sconv_packed_fwd_col_f32_kerPfS_iii
.addrsig_sym _Z28sconv_packed_bwd_col_f32_kerPfS_S_iii
.addrsig_sym _Z28sconv_packed_bwd_row_f32_kerPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "operators.cuh"
namespace NKernel {
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "operators.cuh"
namespace NKernel {
} | .file "tmpxft_000c0364_00000000-6_operators.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "operators.cuh"
namespace NKernel {
} | #include <hip/hip_runtime.h>
#include "operators.cuh"
namespace NKernel {
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "operators.cuh"
namespace NKernel {
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "operators.cuh"
namespace NKernel {
} | .text
.file "operators.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c0364_00000000-6_operators.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "operators.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void test(float *A, const int N){
int i = threadIdx.x;
float x = A[i+1];
if (i < N){
A[i] = x; // DR
}
} | code for sm_80
Function : _Z4testPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void test(float *A, const int N){
int i = threadIdx.x;
float x = A[i+1];
if (i < N){
A[i] = x; // DR
}
} | .file "tmpxft_0015dd55_00000000-6_DR-2-oneMainPath.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4testPfiPfi
.type _Z24__device_stub__Z4testPfiPfi, @function
_Z24__device_stub__Z4testPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z4testPfiPfi, .-_Z24__device_stub__Z4testPfiPfi
.globl _Z4testPfi
.type _Z4testPfi, @function
_Z4testPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4testPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4testPfi, .-_Z4testPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4testPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void test(float *A, const int N){
int i = threadIdx.x;
float x = A[i+1];
if (i < N){
A[i] = x; // DR
}
} | #include <hip/hip_runtime.h>
__global__ void test(float *A, const int N){
int i = threadIdx.x;
float x = A[i+1];
if (i < N){
A[i] = x; // DR
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void test(float *A, const int N){
int i = threadIdx.x;
float x = A[i+1];
if (i < N){
A[i] = x; // DR
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPfi
.globl _Z4testPfi
.p2align 8
.type _Z4testPfi,@function
_Z4testPfi:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testPfi, .Lfunc_end0-_Z4testPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testPfi
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z4testPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void test(float *A, const int N){
int i = threadIdx.x;
float x = A[i+1];
if (i < N){
A[i] = x; // DR
}
} | .text
.file "DR-2-oneMainPath.hip"
.globl _Z19__device_stub__testPfi # -- Begin function _Z19__device_stub__testPfi
.p2align 4, 0x90
.type _Z19__device_stub__testPfi,@function
_Z19__device_stub__testPfi: # @_Z19__device_stub__testPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4testPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__testPfi, .Lfunc_end0-_Z19__device_stub__testPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testPfi,@object # @_Z4testPfi
.section .rodata,"a",@progbits
.globl _Z4testPfi
.p2align 3, 0x0
_Z4testPfi:
.quad _Z19__device_stub__testPfi
.size _Z4testPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4testPfi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPfi
.globl _Z4testPfi
.p2align 8
.type _Z4testPfi,@function
_Z4testPfi:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testPfi, .Lfunc_end0-_Z4testPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testPfi
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z4testPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015dd55_00000000-6_DR-2-oneMainPath.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4testPfiPfi
.type _Z24__device_stub__Z4testPfiPfi, @function
_Z24__device_stub__Z4testPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z4testPfiPfi, .-_Z24__device_stub__Z4testPfiPfi
.globl _Z4testPfi
.type _Z4testPfi, @function
_Z4testPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4testPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4testPfi, .-_Z4testPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4testPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DR-2-oneMainPath.hip"
.globl _Z19__device_stub__testPfi # -- Begin function _Z19__device_stub__testPfi
.p2align 4, 0x90
.type _Z19__device_stub__testPfi,@function
_Z19__device_stub__testPfi: # @_Z19__device_stub__testPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4testPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__testPfi, .Lfunc_end0-_Z19__device_stub__testPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testPfi,@object # @_Z4testPfi
.section .rodata,"a",@progbits
.globl _Z4testPfi
.p2align 3, 0x0
_Z4testPfi:
.quad _Z19__device_stub__testPfi
.size _Z4testPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4testPfi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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