system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7upscalePfS_liiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0050*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe400078e0200 */
/*00a0*/ IMAD R3, R2, UR4, R5 ; /* 0x0000000402037c24 */
/* 0x002fca000f8e0205 */
/*00b0*/ IADD3 R0, P1, R0, R3, RZ ; /* 0x0000000300007210 */
/* 0x000fc80007f3e0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*00d0*/ IMAD.X R5, RZ, RZ, RZ, P1 ; /* 0x000000ffff057224 */
/* 0x000fca00008e06ff */
/*00e0*/ ISETP.GE.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06300 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IABS R4, c[0x0][0x18c] ; /* 0x0000630000047a13 */
/* 0x000fe20000000000 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*0130*/ I2F.RP R7, R4 ; /* 0x0000000400077306 */
/* 0x000e220000209400 */
/*0140*/ IABS R6, c[0x0][0x188] ; /* 0x0000620000067a13 */
/* 0x000fce0000000000 */
/*0150*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0160*/ IADD3 R2, R7, 0xffffffe, RZ ; /* 0x0ffffffe07027810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a03 */
/*01a0*/ IMAD R9, R9, R4, RZ ; /* 0x0000000409097224 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fe200078e0002 */
/*01c0*/ LOP3.LUT R2, R0, c[0x0][0x18c], RZ, 0x3c, !PT ; /* 0x0000630000027a12 */
/* 0x000fc600078e3cff */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0008 */
/*01e0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*01f0*/ I2F.RP R8, R6 ; /* 0x0000000600087306 */
/* 0x000e220000209400 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.HI.U32 R7, R3, R9, RZ ; /* 0x0000000903077227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*0230*/ IMAD R3, R4.reuse, R3, R9 ; /* 0x0000000304037224 */
/* 0x040fe200078e0209 */
/*0240*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e280000001000 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f24070 */
/*0260*/ @!P1 IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a04 */
/*0270*/ @!P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107079810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3 R9, R8, 0xffffffe, RZ ; /* 0x0ffffffe08097810 */
/* 0x001fe40007ffe0ff */
/*0290*/ ISETP.GE.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fe40003f06070 */
/*02a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R9 ; /* 0x0000000900037305 */
/* 0x000e22000021f000 */
/*02b0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fe40003f25270 */
/*02c0*/ IABS R8, c[0x0][0x184] ; /* 0x0000610000087a13 */
/* 0x000fd00000000000 */
/*02d0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD.MOV R11, RZ, RZ, -R3 ; /* 0x000000ffff0b7224 */
/* 0x001fc800078e0a03 */
/*02f0*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0300*/ @!P1 LOP3.LUT R7, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff079a12 */
/* 0x000fe200078e33ff */
/*0310*/ IMAD R9, R11, R6, RZ ; /* 0x000000060b097224 */
/* 0x000fe200078e02ff */
/*0320*/ IABS R11, c[0x0][0x178] ; /* 0x00005e00000b7a13 */
/* 0x000fe40000000000 */
/*0330*/ IABS R10, R7 ; /* 0x00000007000a7213 */
/* 0x000fe20000000000 */
/*0340*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fe200078e0002 */
/*0350*/ I2F.RP R16, R11 ; /* 0x0000000b00107306 */
/* 0x000e260000209400 */
/*0360*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fc800078e000a */
/*0370*/ IMAD.HI.U32 R14, R2, R3, RZ ; /* 0x00000003020e7227 */
/* 0x000fe200078e00ff */
/*0380*/ I2F.RP R9, R8 ; /* 0x0000000800097306 */
/* 0x000e660000209400 */
/*0390*/ IMAD.MOV R2, RZ, RZ, -R14 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a0e */
/*03a0*/ IMAD R3, R6.reuse, R2, R3 ; /* 0x0000000206037224 */
/* 0x040fe200078e0203 */
/*03b0*/ LOP3.LUT R2, R7, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x0000620007027a12 */
/* 0x000fe200078e3cff */
/*03c0*/ MUFU.RCP R16, R16 ; /* 0x0000001000107308 */
/* 0x001e260000001000 */
/*03d0*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe40003f24070 */
/*03e0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*03f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0400*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x002e700000001000 */
/*0410*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a06 */
/*0420*/ @!P1 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e9810 */
/* 0x000fc40007ffe0ff */
/*0430*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fe40003f25270 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f06070 */
/*0450*/ IADD3 R12, R16, 0xffffffe, RZ ; /* 0x0ffffffe100c7810 */
/* 0x001fe40007ffe0ff */
/*0460*/ IADD3 R10, R9, 0xffffffe, RZ ; /* 0x0ffffffe090a7810 */
/* 0x002fe40007ffe0ff */
/*0470*/ F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; /* 0x0000000c000d7305 */
/* 0x00006e000021f000 */
/*0480*/ @P0 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e0810 */
/* 0x000fe20007ffe0ff */
/*0490*/ F2I.FTZ.U32.TRUNC.NTZ R3, R10 ; /* 0x0000000a00037305 */
/* 0x0004e2000021f000 */
/*04a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x001fc600078e00ff */
/*04b0*/ @!P2 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0ea224 */
/* 0x000fe200078e0a0e */
/*04c0*/ @!P1 LOP3.LUT R14, RZ, c[0x0][0x188], RZ, 0x33, !PT ; /* 0x00006200ff0e9a12 */
/* 0x000fe200078e33ff */
/*04d0*/ IMAD.MOV R16, RZ, RZ, -R13 ; /* 0x000000ffff107224 */
/* 0x002fc600078e0a0d */
/*04e0*/ IABS R10, R14 ; /* 0x0000000e000a7213 */
/* 0x004fe20000000000 */
/*04f0*/ IMAD R17, R16, R11, RZ ; /* 0x0000000b10117224 */
/* 0x000fe400078e02ff */
/*0500*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x008fe400078e0a03 */
/*0510*/ IMAD.HI.U32 R13, R13, R17, R12 ; /* 0x000000110d0d7227 */
/* 0x000fc800078e000c */
/*0520*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0530*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fe200078e0002 */
/*0540*/ IABS R9, c[0x0][0x17c] ; /* 0x00005f0000097a13 */
/* 0x000fc60000000000 */
/*0550*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0560*/ I2F.RP R15, R9 ; /* 0x00000009000f7306 */
/* 0x000e260000209400 */
/*0570*/ IMAD.HI.U32 R10, R2, R3, RZ ; /* 0x00000003020a7227 */
/* 0x000fc800078e00ff */
/*0580*/ IMAD.MOV R2, RZ, RZ, -R10 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a0a */
/*0590*/ IMAD R3, R8, R2, R3 ; /* 0x0000000208037224 */
/* 0x000fe200078e0203 */
/*05a0*/ LOP3.LUT R2, R14, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x000061000e027a12 */
/* 0x000fc800078e3cff */
/*05b0*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fe20003f24070 */
/*05c0*/ MUFU.RCP R15, R15 ; /* 0x0000000f000f7308 */
/* 0x001e220000001000 */
/*05d0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f46270 */
/*05e0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a08 */
/*05f0*/ @!P1 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a9810 */
/* 0x000fe40007ffe0ff */
/*0600*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fe40003f25270 */
/*0610*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*0620*/ IADD3 R2, R15, 0xffffffe, RZ ; /* 0x0ffffffe0f027810 */
/* 0x001fc80007ffe0ff */
/*0630*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000e2e000021f000 */
/*0640*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fca0007ffe0ff */
/*0650*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*0660*/ @!P1 LOP3.LUT R10, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff0a9a12 */
/* 0x000fe200078e33ff */
/*0670*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x001fc800078e0a03 */
/*0680*/ IMAD.MOV R15, RZ, RZ, -R10 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0a0a */
/*0690*/ IMAD R17, R2, R9, RZ ; /* 0x0000000902117224 */
/* 0x000fe400078e02ff */
/*06a0*/ IMAD R15, R15, c[0x0][0x184], R14.reuse ; /* 0x000061000f0f7a24 */
/* 0x100fe400078e020e */
/*06b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*06c0*/ IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0e */
/*06d0*/ IABS R18, R15 ; /* 0x0000000f00127213 */
/* 0x000fe20000000000 */
/*06e0*/ IMAD.HI.U32 R17, R3, R17, R2 ; /* 0x0000001103117227 */
/* 0x000fe200078e0002 */
/*06f0*/ LOP3.LUT R15, R15, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e000f0f7a12 */
/* 0x000fc600078e3cff */
/*0700*/ IMAD.HI.U32 R12, R13, R18, RZ ; /* 0x000000120d0c7227 */
/* 0x000fe200078e00ff */
/*0710*/ ISETP.GE.AND P6, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003fc6270 */
/*0720*/ IMAD.MOV R16, RZ, RZ, -R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0a0c */
/*0730*/ IMAD.HI.U32 R13, R13, R8, RZ ; /* 0x000000080d0d7227 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD R18, R11, R16, R18 ; /* 0x000000100b127224 */
/* 0x000fe400078e0212 */
/*0750*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a0d */
/*0760*/ IMAD.HI.U32 R2, R17, R6, RZ ; /* 0x0000000611027227 */
/* 0x000fe200078e00ff */
/*0770*/ ISETP.GT.U32.AND P0, PT, R11, R18, PT ; /* 0x000000120b00720c */
/* 0x000fc60003f04070 */
/*0780*/ IMAD R16, R11.reuse, R3, R8 ; /* 0x000000030b107224 */
/* 0x040fe400078e0208 */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe400078e00ff */
/*07a0*/ IMAD R8, R14, c[0x0][0x188], R7.reuse ; /* 0x000062000e087a24 */
/* 0x100fe200078e0207 */
/*07b0*/ ISETP.GT.U32.AND P2, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f44070 */
/*07c0*/ IMAD.MOV R20, RZ, RZ, -R2 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0a02 */
/*07d0*/ LOP3.LUT R3, R3, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0003037a12 */
/* 0x000fe200078e3cff */
/*07e0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*07f0*/ IABS R24, R8 ; /* 0x0000000800187213 */
/* 0x000fe20000000000 */
/*0800*/ @!P0 IMAD.IADD R18, R18, 0x1, -R11 ; /* 0x0000000112128824 */
/* 0x000fe200078e0a0b */
/*0810*/ ISETP.GE.AND P3, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f66270 */
/*0820*/ IMAD R20, R9, R20, R6 ; /* 0x0000001409147224 */
/* 0x000fe200078e0206 */
/*0830*/ @!P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c8810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD R7, R7, c[0x0][0x18c], R0 ; /* 0x0000630007077a24 */
/* 0x000fe200078e0200 */
/*0850*/ ISETP.GE.U32.AND P4, PT, R18, R11, PT ; /* 0x0000000b1200720c */
/* 0x000fe20003f86070 */
/*0860*/ IMAD.HI.U32 R3, R17, R4, RZ ; /* 0x0000000411037227 */
/* 0x000fe200078e00ff */
/*0870*/ ISETP.GT.U32.AND P5, PT, R9, R20, PT ; /* 0x000000140900720c */
/* 0x000fc40003fa4070 */
/*0880*/ IABS R22, R7 ; /* 0x0000000700167213 */
/* 0x000fe20000000000 */
/*0890*/ IMAD.HI.U32 R6, R17, R24, RZ ; /* 0x0000001811067227 */
/* 0x000fe200078e00ff */
/*08a0*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ LOP3.LUT R8, R8, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0008087a12 */
/* 0x000fe200078e3cff */
/*08c0*/ @!P2 IMAD.IADD R16, R16, 0x1, -R11 ; /* 0x000000011010a824 */
/* 0x000fe200078e0a0b */
/*08d0*/ LOP3.LUT R7, R7, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0007077a12 */
/* 0x000fe200078e3cff */
/*08e0*/ IMAD.MOV R14, RZ, RZ, -R3 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0a03 */
/*08f0*/ IMAD.MOV R18, RZ, RZ, -R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0a06 */
/*0900*/ ISETP.GE.U32.AND P1, PT, R16, R11, PT ; /* 0x0000000b1000720c */
/* 0x000fe20003f26070 */
/*0910*/ IMAD R14, R9.reuse, R14, R4 ; /* 0x0000000e090e7224 */
/* 0x040fe200078e0204 */
/*0920*/ @P4 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c4810 */
/* 0x000fe20007ffe0ff */
/*0930*/ IMAD R18, R9, R18, R24 ; /* 0x0000001209127224 */
/* 0x000fe200078e0218 */
/*0940*/ LOP3.LUT R11, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff0b7a12 */
/* 0x000fe200078e33ff */
/*0950*/ IMAD.HI.U32 R4, R17, R22, RZ ; /* 0x0000001611047227 */
/* 0x000fe200078e00ff */
/*0960*/ ISETP.GT.U32.AND P2, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fc40003f44070 */
/*0970*/ ISETP.GT.U32.AND P4, PT, R9.reuse, R18, PT ; /* 0x000000120900720c */
/* 0x040fe20003f84070 */
/*0980*/ IMAD.MOV R16, RZ, RZ, -R4 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0a04 */
/*0990*/ @!P5 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202d810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0f7624 */
/* 0x000fe400078e00ff */
/*09b0*/ IMAD R16, R9, R16, R22 ; /* 0x0000001009107224 */
/* 0x000fe200078e0216 */
/*09c0*/ @P1 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d1810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ @!P6 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0ce224 */
/* 0x000fe200078e0a0c */
/*09e0*/ LOP3.LUT R15, R15, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f000f0f7a12 */
/* 0x000fe200078e3cff */
/*09f0*/ @!P5 IMAD.IADD R20, R20, 0x1, -R9 ; /* 0x000000011414d824 */
/* 0x000fe200078e0a09 */
/*0a00*/ ISETP.GT.U32.AND P1, PT, R9, R16, PT ; /* 0x000000100900720c */
/* 0x000fe20003f24070 */
/*0a10*/ @!P3 IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0db224 */
/* 0x000fe200078e0a0d */
/*0a20*/ ISETP.NE.AND P6, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003fc5270 */
/*0a30*/ @!P4 IMAD.IADD R18, R18, 0x1, -R9.reuse ; /* 0x000000011212c824 */
/* 0x100fe200078e0a09 */
/*0a40*/ ISETP.GE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f66270 */
/*0a50*/ @!P2 IMAD.IADD R14, R14, 0x1, -R9 ; /* 0x000000010e0ea824 */
/* 0x000fe200078e0a09 */
/*0a60*/ SEL R15, R11.reuse, R12, !P6 ; /* 0x0000000c0b0f7207 */
/* 0x040fe20007000000 */
/*0a70*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0c7624 */
/* 0x000fe200078e00ff */
/*0a80*/ SEL R11, R11, R13, !P6 ; /* 0x0000000d0b0b7207 */
/* 0x000fc40007000000 */
/*0a90*/ ISETP.GE.U32.AND P0, PT, R20, R9.reuse, PT ; /* 0x000000091400720c */
/* 0x080fe40003f06070 */
/*0aa0*/ ISETP.GE.U32.AND P6, PT, R18, R9, PT ; /* 0x000000091200720c */
/* 0x000fe20003fc6070 */
/*0ab0*/ @!P1 IMAD.IADD R16, R16, 0x1, -R9 ; /* 0x0000000110109824 */
/* 0x000fe200078e0a09 */
/*0ac0*/ @!P4 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606c810 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ IMAD R11, R10, R11, R15 ; /* 0x0000000b0a0b7224 */
/* 0x000fe200078e020f */
/*0ae0*/ ISETP.GE.U32.AND P4, PT, R14, R9.reuse, PT ; /* 0x000000090e00720c */
/* 0x080fe40003f86070 */
/*0af0*/ ISETP.GE.U32.AND P5, PT, R16, R9, PT ; /* 0x000000091000720c */
/* 0x000fe40003fa6070 */
/*0b00*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fc40007ffe0ff */
/*0b10*/ LOP3.LUT R12, R12, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f000c0c7a12 */
/* 0x000fe400078e3cff */
/*0b20*/ ISETP.GE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f26270 */
/*0b30*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0b40*/ @P6 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106066810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f06270 */
/*0b60*/ @!P3 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02b224 */
/* 0x000fe200078e0a02 */
/*0b70*/ ISETP.GE.AND P6, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc40003fc6270 */
/*0b80*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ @P5 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104045810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ @!P1 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0a06 */
/*0bb0*/ @P4 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103034810 */
/* 0x000fe40007ffe0ff */
/*0bc0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*0bd0*/ LOP3.LUT R7, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff077a12 */
/* 0x000fe200078e33ff */
/*0be0*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0a03 */
/*0bf0*/ @!P6 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04e224 */
/* 0x000fe200078e0a04 */
/*0c00*/ SEL R2, R7, R2, !P2 ; /* 0x0000000207027207 */
/* 0x000fc40005000000 */
/*0c10*/ SEL R9, R7.reuse, R6, !P2 ; /* 0x0000000607097207 */
/* 0x040fe40005000000 */
/*0c20*/ SEL R3, R7.reuse, R3, !P2 ; /* 0x0000000307037207 */
/* 0x040fe40005000000 */
/*0c30*/ SEL R4, R7, R4, !P2 ; /* 0x0000000407047207 */
/* 0x000fe20005000000 */
/*0c40*/ IMAD R9, R11, R2, R9 ; /* 0x000000020b097224 */
/* 0x000fe400078e0209 */
/*0c50*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0c60*/ IMAD R3, R9, R3, R4 ; /* 0x0000000309037224 */
/* 0x000fc800078e0204 */
/*0c70*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*0c80*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0c90*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0ca0*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f1405 */
/*0cb0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0cc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7upscalePfS_liiiiii
.globl _Z7upscalePfS_liiiiii
.p2align 8
.type _Z7upscalePfS_liiiiii,@function
_Z7upscalePfS_liiiiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s5, s[0:1], 0x30
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_mul_i32 s5, s5, s15
s_lshr_b32 s4, s4, 16
s_mul_i32 s5, s5, s6
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
v_mad_u64_u32 v[3:4], null, s5, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s4, v3, v2
v_add_co_ci_u32_e64 v1, null, 0, 0, s4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s6, s[0:1], 0x2c
v_ashrrev_i32_e32 v4, 31, v0
s_load_b64 s[10:11], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v0, v4
v_xor_b32_e32 v5, v5, v4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s6, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s6, s4
v_xor_b32_e32 v4, s4, v4
s_xor_b32 s5, s2, s4
s_ashr_i32 s14, s10, 31
v_cvt_f32_u32_e32 v2, s5
s_sub_i32 s2, 0, s5
s_add_i32 s10, s10, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s10, s10, s14
v_rcp_iflag_f32_e32 v2, v2
v_cvt_f32_u32_e32 v9, s10
s_sub_i32 s19, 0, s10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, s2, v2
s_load_b64 s[2:3], s[0:1], 0x24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_hi_u32 v2, v5, v2
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s3, 31
s_ashr_i32 s12, s2, 31
s_add_i32 s8, s3, s7
s_xor_b32 s15, s12, s14
s_xor_b32 s8, s8, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v6, s8
v_mul_lo_u32 v3, v2, s5
s_sub_i32 s9, 0, s8
v_rcp_iflag_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v2
v_subrev_nc_u32_e32 v7, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x4f7ffffe, v6
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 1, v2
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v3, v6
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v5, s9, v3
s_add_i32 s9, s2, s12
s_xor_b32 s13, s9, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v4
v_cvt_f32_u32_e32 v7, s13
s_sub_i32 s9, 0, s13
v_mul_hi_u32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v2, v2, v4
v_rcp_iflag_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v2
v_add_nc_u32_e32 v3, v3, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v7, 0x4f7ffffe, v7 :: v_dual_add_nc_u32 v6, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v6, v4
v_xor_b32_e32 v4, s7, v4
v_mul_hi_u32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v3, s8
v_sub_nc_u32_e32 v5, v5, v6
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v8, s8, v5
v_cmp_le_u32_e32 vcc_lo, s8, v5
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v5, v8 :: v_dual_add_nc_u32 v6, 1, v3
v_cmp_le_u32_e32 vcc_lo, s8, v5
v_cvt_u32_f32_e32 v5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_mul_lo_u32 v6, s9, v5
s_ashr_i32 s9, s11, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s11, s11, s9
v_xor_b32_e32 v3, v3, v4
s_xor_b32 s11, s11, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v8, s11
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v4
s_sub_i32 s16, 0, s11
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v5, v6
v_add_nc_u32_e32 v7, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v7, v4
v_rcp_iflag_f32_e32 v7, v8
v_rcp_iflag_f32_e32 v8, v9
v_xor_b32_e32 v4, s12, v4
v_mul_hi_u32 v5, v6, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v7, 0x4f7ffffe, v7 :: v_dual_mul_f32 v8, 0x4f7ffffe, v8
v_mul_lo_u32 v9, v5, s13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v7, v7
v_cvt_u32_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v6, v6, v9
v_add_nc_u32_e32 v9, 1, v5
v_readfirstlane_b32 s17, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_readfirstlane_b32 s18, v8
v_subrev_nc_u32_e32 v7, s13, v6
v_cmp_le_u32_e32 vcc_lo, s13, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
s_mul_i32 s16, s16, s17
s_mul_i32 s19, s19, s18
s_mul_hi_u32 s16, s17, s16
s_mul_hi_u32 s19, s18, s19
v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v6, v6, v7
s_add_i32 s18, s18, s19
s_add_i32 s17, s17, s16
s_mul_hi_u32 s12, s13, s18
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, 1, v5
v_cmp_le_u32_e32 vcc_lo, s13, v6
v_mul_lo_u32 v6, v3, s3
s_mul_i32 s20, s12, s10
s_add_i32 s21, s12, 1
s_sub_i32 s13, s13, s20
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
s_sub_i32 s20, s13, s10
s_cmp_ge_u32 s13, s10
s_mul_hi_u32 s16, s8, s17
s_cselect_b32 s12, s21, s12
v_xor_b32_e32 v5, v5, v4
s_mul_i32 s22, s16, s11
s_mul_hi_u32 s19, s5, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v4
v_mul_lo_u32 v4, v5, s2
s_cselect_b32 s2, s20, s13
s_add_i32 s13, s12, 1
s_cmp_ge_u32 s2, s10
s_mul_i32 s2, s19, s11
s_cselect_b32 s12, s13, s12
s_sub_i32 s3, s8, s22
s_xor_b32 s8, s12, s15
v_sub_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v4, v2, s6
v_sub_nc_u32_e32 v2, v2, v6
s_xor_b32 s7, s7, s9
s_add_i32 s6, s16, 1
v_ashrrev_i32_e32 v7, 31, v3
s_sub_i32 s12, s3, s11
v_ashrrev_i32_e32 v6, 31, v2
s_sub_i32 s8, s8, s15
v_sub_nc_u32_e32 v4, v0, v4
v_add_nc_u32_e32 v3, v3, v7
s_cmp_ge_u32 s3, s11
v_add_nc_u32_e32 v2, v2, v6
s_cselect_b32 s6, s6, s16
v_ashrrev_i32_e32 v8, 31, v4
v_xor_b32_e32 v3, v3, v7
s_cselect_b32 s3, s12, s3
v_xor_b32_e32 v2, v2, v6
s_add_i32 s12, s6, 1
v_add_nc_u32_e32 v4, v4, v8
v_mul_hi_u32 v9, v3, s18
s_cmp_ge_u32 s3, s11
v_mul_hi_u32 v10, v2, s17
s_cselect_b32 s3, s12, s6
v_xor_b32_e32 v4, v4, v8
s_sub_i32 s5, s5, s2
s_xor_b32 s3, s3, s7
s_xor_b32 s4, s4, s9
v_add_nc_u32_e32 v14, 1, v9
v_mul_lo_u32 v11, v9, s10
v_mul_hi_u32 v12, v4, s17
v_mul_lo_u32 v13, v10, s11
s_add_i32 s2, s19, 1
s_sub_i32 s6, s5, s11
s_sub_i32 s3, s3, s7
s_cmp_ge_u32 s5, s11
v_xor_b32_e32 v7, s14, v7
v_sub_nc_u32_e32 v3, v3, v11
v_mul_lo_u32 v11, v12, s11
v_sub_nc_u32_e32 v2, v2, v13
v_add_nc_u32_e32 v13, 1, v10
s_cselect_b32 s7, s2, s19
v_subrev_nc_u32_e32 v16, s10, v3
v_cmp_le_u32_e32 vcc_lo, s10, v3
v_add_nc_u32_e32 v15, 1, v12
v_xor_b32_e32 v6, s9, v6
v_sub_nc_u32_e32 v4, v4, v11
v_xor_b32_e32 v8, s9, v8
v_cndmask_b32_e32 v9, v9, v14, vcc_lo
v_cndmask_b32_e32 v3, v3, v16, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v11, 1, v9
v_cmp_le_u32_e64 s2, s10, v3
v_cndmask_b32_e32 v10, v10, v13, vcc_lo
v_subrev_nc_u32_e32 v13, s11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v9, v11, s2
v_cmp_le_u32_e64 s2, s11, v4
v_dual_cndmask_b32 v2, v2, v13 :: v_dual_add_nc_u32 v11, 1, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v3, v7
v_cndmask_b32_e64 v9, v12, v15, s2
v_subrev_nc_u32_e32 v12, s11, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s11, v2
v_sub_nc_u32_e32 v2, v3, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v4, v12, s2
v_dual_cndmask_b32 v10, v10, v11 :: v_dual_add_nc_u32 v11, 1, v9
v_mad_u64_u32 v[3:4], null, s8, v5, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s11, v7
v_xor_b32_e32 v10, v10, v6
s_cselect_b32 s2, s6, s5
s_add_i32 s5, s7, 1
s_cmp_ge_u32 s2, s11
v_cndmask_b32_e32 v4, v9, v11, vcc_lo
v_sub_nc_u32_e32 v2, v10, v6
s_cselect_b32 s2, s5, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_xor_b32 s5, s2, s4
v_xor_b32_e32 v6, v4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v3, s3, v[2:3]
s_sub_i32 s4, s5, s4
s_load_b128 s[0:3], s[0:1], 0x0
v_sub_nc_u32_e32 v2, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v4, s4, v[2:3]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7upscalePfS_liiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7upscalePfS_liiiiii, .Lfunc_end0-_Z7upscalePfS_liiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7upscalePfS_liiiiii
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z7upscalePfS_liiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00070969_00000000-6_upscale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13translate_idxiiiiiii
.type _Z13translate_idxiiiiiii, @function
_Z13translate_idxiiiiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13translate_idxiiiiiii, .-_Z13translate_idxiiiiiii
.globl _Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii
.type _Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii, @function
_Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7upscalePfS_liiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii, .-_Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii
.globl _Z7upscalePfS_liiiiii
.type _Z7upscalePfS_liiiiii, @function
_Z7upscalePfS_liiiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7upscalePfS_liiiiii, .-_Z7upscalePfS_liiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7upscalePfS_liiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7upscalePfS_liiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "upscale.hip"
.globl _Z22__device_stub__upscalePfS_liiiiii # -- Begin function _Z22__device_stub__upscalePfS_liiiiii
.p2align 4, 0x90
.type _Z22__device_stub__upscalePfS_liiiiii,@function
_Z22__device_stub__upscalePfS_liiiiii: # @_Z22__device_stub__upscalePfS_liiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7upscalePfS_liiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z22__device_stub__upscalePfS_liiiiii, .Lfunc_end0-_Z22__device_stub__upscalePfS_liiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7upscalePfS_liiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7upscalePfS_liiiiii,@object # @_Z7upscalePfS_liiiiii
.section .rodata,"a",@progbits
.globl _Z7upscalePfS_liiiiii
.p2align 3, 0x0
_Z7upscalePfS_liiiiii:
.quad _Z22__device_stub__upscalePfS_liiiiii
.size _Z7upscalePfS_liiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7upscalePfS_liiiiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__upscalePfS_liiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7upscalePfS_liiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
void vectorAdd(double* A, double* B,double* C,int n);
__global__ void vecAddKernel(double* A, double* B, double* C, int n);
int main() {
double *h_A, *h_B, *h_C;
int i;
long N=10000;
int size=N*sizeof(double);
h_A=(double*)malloc(size);
h_B=(double*)malloc(size);
h_C=(double*)malloc(size);
if(h_A==NULL||h_B==NULL||h_C==NULL) {
printf("malloc failed!");
exit(1);
}
for(i=0;i<N;i++) {
h_A[i]=i*2;
h_B[i]=i*3;
}
vectorAdd(h_A,h_B,h_C,N);
for(i=0;i<10;i++) {
printf("h_C[%d] is %f,should be %f\n",i,h_C[i],h_A[i]+h_B[i]);
}
return 0;
}
void vectorAdd(double* A, double* B,double* C,int n) {
double *d_A=NULL, *d_B=NULL, *d_C=NULL;
int size=sizeof(double)*n;
cudaMalloc((void**)&d_A,size);
cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_B,size);
cudaMemcpy(d_B,B,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_C,size);
if(d_A==NULL||d_B==NULL||d_C==NULL){
printf("device allocate memory failed!\n");
}
// dim3 dimGrid(65537,65537,65537);//test grid,block size
// dim3 dimBlock(1026,1024,64);
vecAddKernel<<<ceil(n/1024.0),1024>>>(d_A,d_B,d_C,n);
cudaMemcpy(C,d_C,size,cudaMemcpyDeviceToHost);
cudaFree(d_A);cudaFree(d_B);cudaFree(d_C);
}
__global__ void vecAddKernel(double* A, double* B, double* C, int n) {
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) {
C[i]=A[i]+B[i];
}
}
//add nvcc -arch compute_13 to enable double
/*
Device 0: "Quadro K600"
CUDA Driver Version / Runtime Version 5.5 / 5.5
CUDA Capability Major/Minor version number: 3.0
Total amount of global memory: 1024 MBytes (1073414144 bytes)
( 1) Multiprocessors, (192) CUDA Cores/MP: 192 CUDA Cores
GPU Clock rate: 876 MHz (0.88 GHz)
Memory Clock rate: 891 Mhz
Memory Bus Width: 128-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 65536
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device PCI Bus ID / PCI location ID: 5 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.5, CUDA Runtime Version = 5.5, NumDevs = 1, Device0 = Quadro K600
Result = PASS
*/ | code for sm_80
Function : _Z12vecAddKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
void vectorAdd(double* A, double* B,double* C,int n);
__global__ void vecAddKernel(double* A, double* B, double* C, int n);
int main() {
double *h_A, *h_B, *h_C;
int i;
long N=10000;
int size=N*sizeof(double);
h_A=(double*)malloc(size);
h_B=(double*)malloc(size);
h_C=(double*)malloc(size);
if(h_A==NULL||h_B==NULL||h_C==NULL) {
printf("malloc failed!");
exit(1);
}
for(i=0;i<N;i++) {
h_A[i]=i*2;
h_B[i]=i*3;
}
vectorAdd(h_A,h_B,h_C,N);
for(i=0;i<10;i++) {
printf("h_C[%d] is %f,should be %f\n",i,h_C[i],h_A[i]+h_B[i]);
}
return 0;
}
void vectorAdd(double* A, double* B,double* C,int n) {
double *d_A=NULL, *d_B=NULL, *d_C=NULL;
int size=sizeof(double)*n;
cudaMalloc((void**)&d_A,size);
cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_B,size);
cudaMemcpy(d_B,B,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_C,size);
if(d_A==NULL||d_B==NULL||d_C==NULL){
printf("device allocate memory failed!\n");
}
// dim3 dimGrid(65537,65537,65537);//test grid,block size
// dim3 dimBlock(1026,1024,64);
vecAddKernel<<<ceil(n/1024.0),1024>>>(d_A,d_B,d_C,n);
cudaMemcpy(C,d_C,size,cudaMemcpyDeviceToHost);
cudaFree(d_A);cudaFree(d_B);cudaFree(d_C);
}
__global__ void vecAddKernel(double* A, double* B, double* C, int n) {
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) {
C[i]=A[i]+B[i];
}
}
//add nvcc -arch compute_13 to enable double
/*
Device 0: "Quadro K600"
CUDA Driver Version / Runtime Version 5.5 / 5.5
CUDA Capability Major/Minor version number: 3.0
Total amount of global memory: 1024 MBytes (1073414144 bytes)
( 1) Multiprocessors, (192) CUDA Cores/MP: 192 CUDA Cores
GPU Clock rate: 876 MHz (0.88 GHz)
Memory Clock rate: 891 Mhz
Memory Bus Width: 128-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 65536
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device PCI Bus ID / PCI location ID: 5 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.5, CUDA Runtime Version = 5.5, NumDevs = 1, Device0 = Quadro K600
Result = PASS
*/ | .file "tmpxft_00062858_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
.type _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i, .-_Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
.globl _Z12vecAddKernelPdS_S_i
.type _Z12vecAddKernelPdS_S_i, @function
_Z12vecAddKernelPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12vecAddKernelPdS_S_i, .-_Z12vecAddKernelPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "device allocate memory failed!\n"
.text
.globl _Z9vectorAddPdS_S_i
.type _Z9vectorAddPdS_S_i, @function
_Z9vectorAddPdS_S_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leal 0(,%rcx,8), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
cmpq $0, 8(%rsp)
je .L12
cmpq $0, 16(%rsp)
je .L12
cmpq $0, 24(%rsp)
jne .L13
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L13:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC1(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC5(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC2(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC4(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L15:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
jmp .L15
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9vectorAddPdS_S_i, .-_Z9vectorAddPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "malloc failed!"
.LC7:
.string "h_C[%d] is %f,should be %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $80000, %edi
call malloc@PLT
movq %rax, %rbx
movl $80000, %edi
call malloc@PLT
movq %rax, %rbp
movl $80000, %edi
call malloc@PLT
movq %rax, %r12
testq %rbx, %rbx
sete %al
testq %rbp, %rbp
sete %dl
orb %dl, %al
jne .L25
testq %r12, %r12
je .L25
movl $0, %eax
.L21:
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
addq $1, %rax
cmpq $10000, %rax
jne .L21
movl $10000, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z9vectorAddPdS_S_i
movl $0, %r13d
leaq .LC7(%rip), %r14
.L23:
movsd (%rbx,%r13,8), %xmm1
movsd (%r12,%r13,8), %xmm0
addsd 0(%rbp,%r13,8), %xmm1
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $10, %r13
jne .L23
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z12vecAddKernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1062207488
.align 8
.LC2:
.long 0
.long 1127219200
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC5:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
void vectorAdd(double* A, double* B,double* C,int n);
__global__ void vecAddKernel(double* A, double* B, double* C, int n);
int main() {
double *h_A, *h_B, *h_C;
int i;
long N=10000;
int size=N*sizeof(double);
h_A=(double*)malloc(size);
h_B=(double*)malloc(size);
h_C=(double*)malloc(size);
if(h_A==NULL||h_B==NULL||h_C==NULL) {
printf("malloc failed!");
exit(1);
}
for(i=0;i<N;i++) {
h_A[i]=i*2;
h_B[i]=i*3;
}
vectorAdd(h_A,h_B,h_C,N);
for(i=0;i<10;i++) {
printf("h_C[%d] is %f,should be %f\n",i,h_C[i],h_A[i]+h_B[i]);
}
return 0;
}
void vectorAdd(double* A, double* B,double* C,int n) {
double *d_A=NULL, *d_B=NULL, *d_C=NULL;
int size=sizeof(double)*n;
cudaMalloc((void**)&d_A,size);
cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_B,size);
cudaMemcpy(d_B,B,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_C,size);
if(d_A==NULL||d_B==NULL||d_C==NULL){
printf("device allocate memory failed!\n");
}
// dim3 dimGrid(65537,65537,65537);//test grid,block size
// dim3 dimBlock(1026,1024,64);
vecAddKernel<<<ceil(n/1024.0),1024>>>(d_A,d_B,d_C,n);
cudaMemcpy(C,d_C,size,cudaMemcpyDeviceToHost);
cudaFree(d_A);cudaFree(d_B);cudaFree(d_C);
}
__global__ void vecAddKernel(double* A, double* B, double* C, int n) {
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) {
C[i]=A[i]+B[i];
}
}
//add nvcc -arch compute_13 to enable double
/*
Device 0: "Quadro K600"
CUDA Driver Version / Runtime Version 5.5 / 5.5
CUDA Capability Major/Minor version number: 3.0
Total amount of global memory: 1024 MBytes (1073414144 bytes)
( 1) Multiprocessors, (192) CUDA Cores/MP: 192 CUDA Cores
GPU Clock rate: 876 MHz (0.88 GHz)
Memory Clock rate: 891 Mhz
Memory Bus Width: 128-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 65536
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device PCI Bus ID / PCI location ID: 5 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.5, CUDA Runtime Version = 5.5, NumDevs = 1, Device0 = Quadro K600
Result = PASS
*/ | #include <stdio.h>
#include <hip/hip_runtime.h>
void vectorAdd(double* A, double* B,double* C,int n);
__global__ void vecAddKernel(double* A, double* B, double* C, int n);
int main() {
double *h_A, *h_B, *h_C;
int i;
long N=10000;
int size=N*sizeof(double);
h_A=(double*)malloc(size);
h_B=(double*)malloc(size);
h_C=(double*)malloc(size);
if(h_A==NULL||h_B==NULL||h_C==NULL) {
printf("malloc failed!");
exit(1);
}
for(i=0;i<N;i++) {
h_A[i]=i*2;
h_B[i]=i*3;
}
vectorAdd(h_A,h_B,h_C,N);
for(i=0;i<10;i++) {
printf("h_C[%d] is %f,should be %f\n",i,h_C[i],h_A[i]+h_B[i]);
}
return 0;
}
void vectorAdd(double* A, double* B,double* C,int n) {
double *d_A=NULL, *d_B=NULL, *d_C=NULL;
int size=sizeof(double)*n;
hipMalloc((void**)&d_A,size);
hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_B,size);
hipMemcpy(d_B,B,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_C,size);
if(d_A==NULL||d_B==NULL||d_C==NULL){
printf("device allocate memory failed!\n");
}
// dim3 dimGrid(65537,65537,65537);//test grid,block size
// dim3 dimBlock(1026,1024,64);
vecAddKernel<<<ceil(n/1024.0),1024>>>(d_A,d_B,d_C,n);
hipMemcpy(C,d_C,size,hipMemcpyDeviceToHost);
hipFree(d_A);hipFree(d_B);hipFree(d_C);
}
__global__ void vecAddKernel(double* A, double* B, double* C, int n) {
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) {
C[i]=A[i]+B[i];
}
}
//add nvcc -arch compute_13 to enable double
/*
Device 0: "Quadro K600"
CUDA Driver Version / Runtime Version 5.5 / 5.5
CUDA Capability Major/Minor version number: 3.0
Total amount of global memory: 1024 MBytes (1073414144 bytes)
( 1) Multiprocessors, (192) CUDA Cores/MP: 192 CUDA Cores
GPU Clock rate: 876 MHz (0.88 GHz)
Memory Clock rate: 891 Mhz
Memory Bus Width: 128-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 65536
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device PCI Bus ID / PCI location ID: 5 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.5, CUDA Runtime Version = 5.5, NumDevs = 1, Device0 = Quadro K600
Result = PASS
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
void vectorAdd(double* A, double* B,double* C,int n);
__global__ void vecAddKernel(double* A, double* B, double* C, int n);
int main() {
double *h_A, *h_B, *h_C;
int i;
long N=10000;
int size=N*sizeof(double);
h_A=(double*)malloc(size);
h_B=(double*)malloc(size);
h_C=(double*)malloc(size);
if(h_A==NULL||h_B==NULL||h_C==NULL) {
printf("malloc failed!");
exit(1);
}
for(i=0;i<N;i++) {
h_A[i]=i*2;
h_B[i]=i*3;
}
vectorAdd(h_A,h_B,h_C,N);
for(i=0;i<10;i++) {
printf("h_C[%d] is %f,should be %f\n",i,h_C[i],h_A[i]+h_B[i]);
}
return 0;
}
void vectorAdd(double* A, double* B,double* C,int n) {
double *d_A=NULL, *d_B=NULL, *d_C=NULL;
int size=sizeof(double)*n;
hipMalloc((void**)&d_A,size);
hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_B,size);
hipMemcpy(d_B,B,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_C,size);
if(d_A==NULL||d_B==NULL||d_C==NULL){
printf("device allocate memory failed!\n");
}
// dim3 dimGrid(65537,65537,65537);//test grid,block size
// dim3 dimBlock(1026,1024,64);
vecAddKernel<<<ceil(n/1024.0),1024>>>(d_A,d_B,d_C,n);
hipMemcpy(C,d_C,size,hipMemcpyDeviceToHost);
hipFree(d_A);hipFree(d_B);hipFree(d_C);
}
__global__ void vecAddKernel(double* A, double* B, double* C, int n) {
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) {
C[i]=A[i]+B[i];
}
}
//add nvcc -arch compute_13 to enable double
/*
Device 0: "Quadro K600"
CUDA Driver Version / Runtime Version 5.5 / 5.5
CUDA Capability Major/Minor version number: 3.0
Total amount of global memory: 1024 MBytes (1073414144 bytes)
( 1) Multiprocessors, (192) CUDA Cores/MP: 192 CUDA Cores
GPU Clock rate: 876 MHz (0.88 GHz)
Memory Clock rate: 891 Mhz
Memory Bus Width: 128-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 65536
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device PCI Bus ID / PCI location ID: 5 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.5, CUDA Runtime Version = 5.5, NumDevs = 1, Device0 = Quadro K600
Result = PASS
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPdS_S_i
.globl _Z12vecAddKernelPdS_S_i
.p2align 8
.type _Z12vecAddKernelPdS_S_i,@function
_Z12vecAddKernelPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPdS_S_i, .Lfunc_end0-_Z12vecAddKernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
void vectorAdd(double* A, double* B,double* C,int n);
__global__ void vecAddKernel(double* A, double* B, double* C, int n);
int main() {
double *h_A, *h_B, *h_C;
int i;
long N=10000;
int size=N*sizeof(double);
h_A=(double*)malloc(size);
h_B=(double*)malloc(size);
h_C=(double*)malloc(size);
if(h_A==NULL||h_B==NULL||h_C==NULL) {
printf("malloc failed!");
exit(1);
}
for(i=0;i<N;i++) {
h_A[i]=i*2;
h_B[i]=i*3;
}
vectorAdd(h_A,h_B,h_C,N);
for(i=0;i<10;i++) {
printf("h_C[%d] is %f,should be %f\n",i,h_C[i],h_A[i]+h_B[i]);
}
return 0;
}
void vectorAdd(double* A, double* B,double* C,int n) {
double *d_A=NULL, *d_B=NULL, *d_C=NULL;
int size=sizeof(double)*n;
hipMalloc((void**)&d_A,size);
hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_B,size);
hipMemcpy(d_B,B,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_C,size);
if(d_A==NULL||d_B==NULL||d_C==NULL){
printf("device allocate memory failed!\n");
}
// dim3 dimGrid(65537,65537,65537);//test grid,block size
// dim3 dimBlock(1026,1024,64);
vecAddKernel<<<ceil(n/1024.0),1024>>>(d_A,d_B,d_C,n);
hipMemcpy(C,d_C,size,hipMemcpyDeviceToHost);
hipFree(d_A);hipFree(d_B);hipFree(d_C);
}
__global__ void vecAddKernel(double* A, double* B, double* C, int n) {
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) {
C[i]=A[i]+B[i];
}
}
//add nvcc -arch compute_13 to enable double
/*
Device 0: "Quadro K600"
CUDA Driver Version / Runtime Version 5.5 / 5.5
CUDA Capability Major/Minor version number: 3.0
Total amount of global memory: 1024 MBytes (1073414144 bytes)
( 1) Multiprocessors, (192) CUDA Cores/MP: 192 CUDA Cores
GPU Clock rate: 876 MHz (0.88 GHz)
Memory Clock rate: 891 Mhz
Memory Bus Width: 128-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 65536
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device PCI Bus ID / PCI location ID: 5 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.5, CUDA Runtime Version = 5.5, NumDevs = 1, Device0 = Quadro K600
Result = PASS
*/ | .text
.file "vectorAdd.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %rbx
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %r14
movl $80000, %edi # imm = 0x13880
callq malloc
testq %rbx, %rbx
je .LBB0_8
# %bb.1:
testq %r14, %r14
je .LBB0_8
# %bb.2:
movq %rax, %r15
testq %rax, %rax
je .LBB0_8
# %bb.3: # %.preheader.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_4: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%rax,4)
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%r14,%rax,4)
addl $3, %ecx
addq $2, %rax
cmpq $20000, %rax # imm = 0x4E20
jne .LBB0_4
# %bb.5:
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $10000, %ecx # imm = 0x2710
callq _Z9vectorAddPdS_S_i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd (%rbx,%r12,8), %xmm1 # xmm1 = mem[0],zero
addsd (%r14,%r12,8), %xmm1
movl $.L.str.1, %edi
movl %r12d, %esi
movb $2, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB0_6
# %bb.7:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 48
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9vectorAddPdS_S_i
.LCPI1_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl _Z9vectorAddPdS_S_i
.p2align 4, 0x90
.type _Z9vectorAddPdS_S_i,@function
_Z9vectorAddPdS_S_i: # @_Z9vectorAddPdS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
leal (,%r15,8), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
cmpq $0, 24(%rsp)
je .LBB1_3
# %bb.1:
cmpq $0, 16(%rsp)
je .LBB1_3
# %bb.2:
cmpq $0, 8(%rsp)
jne .LBB1_4
.LBB1_3:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_4:
cvtsi2sd %r15d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9vectorAddPdS_S_i, .Lfunc_end1-_Z9vectorAddPdS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vecAddKernelPdS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPdS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPdS_S_i,@function
_Z27__device_stub__vecAddKernelPdS_S_i: # @_Z27__device_stub__vecAddKernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z27__device_stub__vecAddKernelPdS_S_i, .Lfunc_end2-_Z27__device_stub__vecAddKernelPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "malloc failed!"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "h_C[%d] is %f,should be %f\n"
.size .L.str.1, 28
.type _Z12vecAddKernelPdS_S_i,@object # @_Z12vecAddKernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPdS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPdS_S_i:
.quad _Z27__device_stub__vecAddKernelPdS_S_i
.size _Z12vecAddKernelPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12vecAddKernelPdS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "device allocate memory failed!"
.size .Lstr, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12vecAddKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPdS_S_i
.globl _Z12vecAddKernelPdS_S_i
.p2align 8
.type _Z12vecAddKernelPdS_S_i,@function
_Z12vecAddKernelPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPdS_S_i, .Lfunc_end0-_Z12vecAddKernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00062858_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
.type _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i, .-_Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
.globl _Z12vecAddKernelPdS_S_i
.type _Z12vecAddKernelPdS_S_i, @function
_Z12vecAddKernelPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12vecAddKernelPdS_S_i, .-_Z12vecAddKernelPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "device allocate memory failed!\n"
.text
.globl _Z9vectorAddPdS_S_i
.type _Z9vectorAddPdS_S_i, @function
_Z9vectorAddPdS_S_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leal 0(,%rcx,8), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
cmpq $0, 8(%rsp)
je .L12
cmpq $0, 16(%rsp)
je .L12
cmpq $0, 24(%rsp)
jne .L13
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L13:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC1(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC5(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC2(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC4(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L15:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
jmp .L15
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9vectorAddPdS_S_i, .-_Z9vectorAddPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "malloc failed!"
.LC7:
.string "h_C[%d] is %f,should be %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $80000, %edi
call malloc@PLT
movq %rax, %rbx
movl $80000, %edi
call malloc@PLT
movq %rax, %rbp
movl $80000, %edi
call malloc@PLT
movq %rax, %r12
testq %rbx, %rbx
sete %al
testq %rbp, %rbp
sete %dl
orb %dl, %al
jne .L25
testq %r12, %r12
je .L25
movl $0, %eax
.L21:
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
addq $1, %rax
cmpq $10000, %rax
jne .L21
movl $10000, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z9vectorAddPdS_S_i
movl $0, %r13d
leaq .LC7(%rip), %r14
.L23:
movsd (%rbx,%r13,8), %xmm1
movsd (%r12,%r13,8), %xmm0
addsd 0(%rbp,%r13,8), %xmm1
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $10, %r13
jne .L23
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z12vecAddKernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1062207488
.align 8
.LC2:
.long 0
.long 1127219200
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC5:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %rbx
movl $80000, %edi # imm = 0x13880
callq malloc
movq %rax, %r14
movl $80000, %edi # imm = 0x13880
callq malloc
testq %rbx, %rbx
je .LBB0_8
# %bb.1:
testq %r14, %r14
je .LBB0_8
# %bb.2:
movq %rax, %r15
testq %rax, %rax
je .LBB0_8
# %bb.3: # %.preheader.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_4: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%rax,4)
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%r14,%rax,4)
addl $3, %ecx
addq $2, %rax
cmpq $20000, %rax # imm = 0x4E20
jne .LBB0_4
# %bb.5:
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $10000, %ecx # imm = 0x2710
callq _Z9vectorAddPdS_S_i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd (%rbx,%r12,8), %xmm1 # xmm1 = mem[0],zero
addsd (%r14,%r12,8), %xmm1
movl $.L.str.1, %edi
movl %r12d, %esi
movb $2, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB0_6
# %bb.7:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 48
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9vectorAddPdS_S_i
.LCPI1_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl _Z9vectorAddPdS_S_i
.p2align 4, 0x90
.type _Z9vectorAddPdS_S_i,@function
_Z9vectorAddPdS_S_i: # @_Z9vectorAddPdS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
leal (,%r15,8), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
cmpq $0, 24(%rsp)
je .LBB1_3
# %bb.1:
cmpq $0, 16(%rsp)
je .LBB1_3
# %bb.2:
cmpq $0, 8(%rsp)
jne .LBB1_4
.LBB1_3:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_4:
cvtsi2sd %r15d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9vectorAddPdS_S_i, .Lfunc_end1-_Z9vectorAddPdS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vecAddKernelPdS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPdS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPdS_S_i,@function
_Z27__device_stub__vecAddKernelPdS_S_i: # @_Z27__device_stub__vecAddKernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z27__device_stub__vecAddKernelPdS_S_i, .Lfunc_end2-_Z27__device_stub__vecAddKernelPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "malloc failed!"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "h_C[%d] is %f,should be %f\n"
.size .L.str.1, 28
.type _Z12vecAddKernelPdS_S_i,@object # @_Z12vecAddKernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPdS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPdS_S_i:
.quad _Z27__device_stub__vecAddKernelPdS_S_i
.size _Z12vecAddKernelPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12vecAddKernelPdS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "device allocate memory failed!"
.size .Lstr, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // File: cudaGetDeviceProperties.cu
//
// Compiler Command:
// $ nvcc cudaGetDeviceProperties.cu -o cudaGetDeviceProperties
// Head files
#include <stdio.h>
#include <cuda_runtime.h>
// main function
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
int deviceCount = 0;
cudaError_t error_id = cudaGetDeviceCount(&deviceCount);
if (error_id != cudaSuccess) {
printf("cudaGetDeviceCount returned %d\n-> %s\n",
(int)error_id, cudaGetErrorString(error_id));
printf("Result = FAIL\n");
exit(EXIT_FAILURE);
}
if (deviceCount == 0) {
printf("There are no available device(s) that support CUDA\n");
} else {
printf("Detected %d CUDA Capable device(s)\n", deviceCount);
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev =0;
cudaSetDevice(dev);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("Device %d: \"%s\"\n", dev, deviceProp.name);
cudaDriverGetVersion(&driverVersion);
cudaRuntimeGetVersion(&runtimeVersion);
printf(" CUDA Driver Version / Runtime Version %d.%d / %d.%d\n",driverVersion/1000, (driverVersion%100)/10,runtimeVersion/1000, (runtimeVersion%100)/10);
printf(" CUDA Capability Major/Minor version number: %d.%d\n",deviceProp.major, deviceProp.minor);
printf(" Total amount of global memory: %.2f MBytes (%llu bytes)\n",(float)deviceProp.totalGlobalMem/(pow(1024.0,3)),(unsigned long long) deviceProp.totalGlobalMem);
printf(" GPU Clock rate: %.0f MHz (%0.2f GHz)\n",deviceProp.clockRate * 1e-3f, deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.0f Mhz\n",deviceProp.memoryClockRate * 1e-3f);
printf(" Memory Bus Width: %d-bit\n",deviceProp.memoryBusWidth);
if (deviceProp.l2CacheSize) {
printf(" L2 Cache Size: %d bytes\n",
deviceProp.l2CacheSize);
}
printf(" Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n",
deviceProp.maxTexture1D , deviceProp.maxTexture2D[0],
deviceProp.maxTexture2D[1],
deviceProp.maxTexture3D[0], deviceProp.maxTexture3D[1],
deviceProp.maxTexture3D[2]);
printf(" Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n",
deviceProp.maxTexture1DLayered[0], deviceProp.maxTexture1DLayered[1],
deviceProp.maxTexture2DLayered[0], deviceProp.maxTexture2DLayered[1],
deviceProp.maxTexture2DLayered[2]);
printf(" Total amount of constant memory: %lu bytes\n",deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %lu bytes\n",deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",deviceProp.regsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Maximum number of threads per multiprocessor: %d\n",deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %lu bytes\n", deviceProp.memPitch);
exit(EXIT_SUCCESS);
}
// For a system with multiple GPUs, it's necessary to choose one of these GPUs as our device.
// The stratage is that: the GPU with best performance must has the largest number of SMs.
// Implementation code listed below:
// int numDevices = 0;
// cudaGetDeviceCount(&numDevices);
// if (numDevices > 1) {
// int maxMultiprocessors = 0, maxDevice = 0;
// for (int device=0; device<numDevices; device++) {
// cudaDeviceProp props;
// cudaGetDeviceProperties(&props, device);
// if (maxMultiprocessors < props.multiProcessorCount) {
// maxMultiprocessors = props.multiProcessorCount;
// maxDevice = device;
// }
// }
// cudaSetDevice(maxDevice);
// }
// Runnning result
// yangyang@yangyang-XPS-8900:~/Desktop/cudaCodeDebug/CodeDebug2$ ./cudaGetDeviceProperties
// ./cudaGetDeviceProperties Starting...
// Detected 1 CUDA Capable device(s)
// Device 0: "GeForce GTX 750 Ti"
// CUDA Driver Version / Runtime Version 9.1 / 9.1
// CUDA Capability Major/Minor version number: 5.0
// Total amount of global memory: 1.95 MBytes (2090598400 bytes)
// GPU Clock rate: 1084 MHz (1.08 GHz)
// Memory Clock rate: 2700 Mhz
// Memory Bus Width: 128-bit
// L2 Cache Size: 2097152 bytes
// Max Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536,65536), 3D=(4096,4096,4096)
// Max Layered Texture Size (dim) x layers 1D=(16384) x 2048, 2D=(16384,16384) x 2048
// Total amount of constant memory: 65536 bytes
// Total amount of shared memory per block: 49152 bytes
// Total number of registers available per block: 65536
// Warp size: 32
// Maximum number of threads per multiprocessor: 2048
// Maximum number of threads per block: 1024
// Maximum sizes of each dimension of a block: 1024 x 1024 x 64
// Maximum sizes of each dimension of a grid: 2147483647 x 65535 x 65535
// Maximum memory pitch: 2147483647 bytes | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // File: cudaGetDeviceProperties.cu
//
// Compiler Command:
// $ nvcc cudaGetDeviceProperties.cu -o cudaGetDeviceProperties
// Head files
#include <stdio.h>
#include <cuda_runtime.h>
// main function
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
int deviceCount = 0;
cudaError_t error_id = cudaGetDeviceCount(&deviceCount);
if (error_id != cudaSuccess) {
printf("cudaGetDeviceCount returned %d\n-> %s\n",
(int)error_id, cudaGetErrorString(error_id));
printf("Result = FAIL\n");
exit(EXIT_FAILURE);
}
if (deviceCount == 0) {
printf("There are no available device(s) that support CUDA\n");
} else {
printf("Detected %d CUDA Capable device(s)\n", deviceCount);
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev =0;
cudaSetDevice(dev);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("Device %d: \"%s\"\n", dev, deviceProp.name);
cudaDriverGetVersion(&driverVersion);
cudaRuntimeGetVersion(&runtimeVersion);
printf(" CUDA Driver Version / Runtime Version %d.%d / %d.%d\n",driverVersion/1000, (driverVersion%100)/10,runtimeVersion/1000, (runtimeVersion%100)/10);
printf(" CUDA Capability Major/Minor version number: %d.%d\n",deviceProp.major, deviceProp.minor);
printf(" Total amount of global memory: %.2f MBytes (%llu bytes)\n",(float)deviceProp.totalGlobalMem/(pow(1024.0,3)),(unsigned long long) deviceProp.totalGlobalMem);
printf(" GPU Clock rate: %.0f MHz (%0.2f GHz)\n",deviceProp.clockRate * 1e-3f, deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.0f Mhz\n",deviceProp.memoryClockRate * 1e-3f);
printf(" Memory Bus Width: %d-bit\n",deviceProp.memoryBusWidth);
if (deviceProp.l2CacheSize) {
printf(" L2 Cache Size: %d bytes\n",
deviceProp.l2CacheSize);
}
printf(" Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n",
deviceProp.maxTexture1D , deviceProp.maxTexture2D[0],
deviceProp.maxTexture2D[1],
deviceProp.maxTexture3D[0], deviceProp.maxTexture3D[1],
deviceProp.maxTexture3D[2]);
printf(" Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n",
deviceProp.maxTexture1DLayered[0], deviceProp.maxTexture1DLayered[1],
deviceProp.maxTexture2DLayered[0], deviceProp.maxTexture2DLayered[1],
deviceProp.maxTexture2DLayered[2]);
printf(" Total amount of constant memory: %lu bytes\n",deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %lu bytes\n",deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",deviceProp.regsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Maximum number of threads per multiprocessor: %d\n",deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %lu bytes\n", deviceProp.memPitch);
exit(EXIT_SUCCESS);
}
// For a system with multiple GPUs, it's necessary to choose one of these GPUs as our device.
// The stratage is that: the GPU with best performance must has the largest number of SMs.
// Implementation code listed below:
// int numDevices = 0;
// cudaGetDeviceCount(&numDevices);
// if (numDevices > 1) {
// int maxMultiprocessors = 0, maxDevice = 0;
// for (int device=0; device<numDevices; device++) {
// cudaDeviceProp props;
// cudaGetDeviceProperties(&props, device);
// if (maxMultiprocessors < props.multiProcessorCount) {
// maxMultiprocessors = props.multiProcessorCount;
// maxDevice = device;
// }
// }
// cudaSetDevice(maxDevice);
// }
// Runnning result
// yangyang@yangyang-XPS-8900:~/Desktop/cudaCodeDebug/CodeDebug2$ ./cudaGetDeviceProperties
// ./cudaGetDeviceProperties Starting...
// Detected 1 CUDA Capable device(s)
// Device 0: "GeForce GTX 750 Ti"
// CUDA Driver Version / Runtime Version 9.1 / 9.1
// CUDA Capability Major/Minor version number: 5.0
// Total amount of global memory: 1.95 MBytes (2090598400 bytes)
// GPU Clock rate: 1084 MHz (1.08 GHz)
// Memory Clock rate: 2700 Mhz
// Memory Bus Width: 128-bit
// L2 Cache Size: 2097152 bytes
// Max Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536,65536), 3D=(4096,4096,4096)
// Max Layered Texture Size (dim) x layers 1D=(16384) x 2048, 2D=(16384,16384) x 2048
// Total amount of constant memory: 65536 bytes
// Total amount of shared memory per block: 49152 bytes
// Total number of registers available per block: 65536
// Warp size: 32
// Maximum number of threads per multiprocessor: 2048
// Maximum number of threads per block: 1024
// Maximum sizes of each dimension of a block: 1024 x 1024 x 64
// Maximum sizes of each dimension of a grid: 2147483647 x 65535 x 65535
// Maximum memory pitch: 2147483647 bytes | .file "tmpxft_0013c40f_00000000-6_cudaGetDeviceProperties.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s Starting...\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaGetDeviceCount returned %d\n-> %s\n"
.section .rodata.str1.1
.LC2:
.string "Result = FAIL\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "There are no available device(s) that support CUDA\n"
.align 8
.LC4:
.string "Detected %d CUDA Capable device(s)\n"
.section .rodata.str1.1
.LC5:
.string "Device %d: \"%s\"\n"
.section .rodata.str1.8
.align 8
.LC6:
.string " CUDA Driver Version / Runtime Version %d.%d / %d.%d\n"
.align 8
.LC7:
.string " CUDA Capability Major/Minor version number: %d.%d\n"
.align 8
.LC9:
.string " Total amount of global memory: %.2f MBytes (%llu bytes)\n"
.align 8
.LC12:
.string " GPU Clock rate: %.0f MHz (%0.2f GHz)\n"
.section .rodata.str1.1
.LC13:
.string " Memory Clock rate: %.0f Mhz\n"
.LC14:
.string " Memory Bus Width: %d-bit\n"
.LC15:
.string " L2 Cache Size: %d bytes\n"
.section .rodata.str1.8
.align 8
.LC16:
.string " Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n"
.align 8
.LC17:
.string " Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n"
.align 8
.LC18:
.string " Total amount of constant memory: %lu bytes\n"
.align 8
.LC19:
.string " Total amount of shared memory per block: %lu bytes\n"
.align 8
.LC20:
.string " Total number of registers available per block: %d\n"
.section .rodata.str1.1
.LC21:
.string " Warp size: %d\n"
.section .rodata.str1.8
.align 8
.LC22:
.string " Maximum number of threads per multiprocessor: %d\n"
.align 8
.LC23:
.string " Maximum number of threads per block: %d\n"
.align 8
.LC24:
.string " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.align 8
.LC25:
.string " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.align 8
.LC26:
.string " Maximum memory pitch: %lu bytes\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl 4(%rsp), %edx
testl %edx, %edx
jne .L5
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movl $0, 8(%rsp)
movl $0, 12(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq 12(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
movl 12(%rsp), %eax
movl 8(%rsp), %ecx
movslq %eax, %r8
imulq $1374389535, %r8, %rdx
sarq $37, %rdx
movl %eax, %edi
sarl $31, %edi
subl %edi, %edx
imull $100, %edx, %edx
subl %edx, %eax
movslq %eax, %r9
imulq $1717986919, %r9, %r9
sarq $34, %r9
sarl $31, %eax
imulq $274877907, %r8, %r8
sarq $38, %r8
movslq %ecx, %rdx
imulq $1374389535, %rdx, %rsi
sarq $37, %rsi
movl %ecx, %r10d
sarl $31, %r10d
subl %r10d, %esi
imull $100, %esi, %esi
subl %esi, %ecx
movslq %ecx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %ecx
subl %ecx, %esi
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
subl %r10d, %edx
subl %eax, %r9d
subl %edi, %r8d
movl %esi, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
testq %rdx, %rdx
js .L7
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
.L8:
cvtss2sd %xmm0, %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
movaps %xmm0, %xmm1
mulss .LC10(%rip), %xmm1
mulss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 628(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 632(%rsp), %edx
testl %edx, %edx
jne .L13
.L9:
movl 480(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1080
movl 484(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1088
movl 488(%rsp), %r9d
movl 456(%rsp), %r8d
movl 452(%rsp), %ecx
movl 440(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 532(%rsp), %eax
movl %eax, (%rsp)
movl 528(%rsp), %r9d
movl 524(%rsp), %r8d
movl 520(%rsp), %ecx
movl 516(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1072
movq 368(%rsp), %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L5:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L7:
movq %rdx, %rax
shrq %rax
movq %rdx, %rcx
andl $1, %ecx
orq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L8
.L13:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1041235968
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 897988541
.align 4
.LC11:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // File: cudaGetDeviceProperties.cu
//
// Compiler Command:
// $ nvcc cudaGetDeviceProperties.cu -o cudaGetDeviceProperties
// Head files
#include <stdio.h>
#include <cuda_runtime.h>
// main function
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
int deviceCount = 0;
cudaError_t error_id = cudaGetDeviceCount(&deviceCount);
if (error_id != cudaSuccess) {
printf("cudaGetDeviceCount returned %d\n-> %s\n",
(int)error_id, cudaGetErrorString(error_id));
printf("Result = FAIL\n");
exit(EXIT_FAILURE);
}
if (deviceCount == 0) {
printf("There are no available device(s) that support CUDA\n");
} else {
printf("Detected %d CUDA Capable device(s)\n", deviceCount);
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev =0;
cudaSetDevice(dev);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("Device %d: \"%s\"\n", dev, deviceProp.name);
cudaDriverGetVersion(&driverVersion);
cudaRuntimeGetVersion(&runtimeVersion);
printf(" CUDA Driver Version / Runtime Version %d.%d / %d.%d\n",driverVersion/1000, (driverVersion%100)/10,runtimeVersion/1000, (runtimeVersion%100)/10);
printf(" CUDA Capability Major/Minor version number: %d.%d\n",deviceProp.major, deviceProp.minor);
printf(" Total amount of global memory: %.2f MBytes (%llu bytes)\n",(float)deviceProp.totalGlobalMem/(pow(1024.0,3)),(unsigned long long) deviceProp.totalGlobalMem);
printf(" GPU Clock rate: %.0f MHz (%0.2f GHz)\n",deviceProp.clockRate * 1e-3f, deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.0f Mhz\n",deviceProp.memoryClockRate * 1e-3f);
printf(" Memory Bus Width: %d-bit\n",deviceProp.memoryBusWidth);
if (deviceProp.l2CacheSize) {
printf(" L2 Cache Size: %d bytes\n",
deviceProp.l2CacheSize);
}
printf(" Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n",
deviceProp.maxTexture1D , deviceProp.maxTexture2D[0],
deviceProp.maxTexture2D[1],
deviceProp.maxTexture3D[0], deviceProp.maxTexture3D[1],
deviceProp.maxTexture3D[2]);
printf(" Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n",
deviceProp.maxTexture1DLayered[0], deviceProp.maxTexture1DLayered[1],
deviceProp.maxTexture2DLayered[0], deviceProp.maxTexture2DLayered[1],
deviceProp.maxTexture2DLayered[2]);
printf(" Total amount of constant memory: %lu bytes\n",deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %lu bytes\n",deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",deviceProp.regsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Maximum number of threads per multiprocessor: %d\n",deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %lu bytes\n", deviceProp.memPitch);
exit(EXIT_SUCCESS);
}
// For a system with multiple GPUs, it's necessary to choose one of these GPUs as our device.
// The stratage is that: the GPU with best performance must has the largest number of SMs.
// Implementation code listed below:
// int numDevices = 0;
// cudaGetDeviceCount(&numDevices);
// if (numDevices > 1) {
// int maxMultiprocessors = 0, maxDevice = 0;
// for (int device=0; device<numDevices; device++) {
// cudaDeviceProp props;
// cudaGetDeviceProperties(&props, device);
// if (maxMultiprocessors < props.multiProcessorCount) {
// maxMultiprocessors = props.multiProcessorCount;
// maxDevice = device;
// }
// }
// cudaSetDevice(maxDevice);
// }
// Runnning result
// yangyang@yangyang-XPS-8900:~/Desktop/cudaCodeDebug/CodeDebug2$ ./cudaGetDeviceProperties
// ./cudaGetDeviceProperties Starting...
// Detected 1 CUDA Capable device(s)
// Device 0: "GeForce GTX 750 Ti"
// CUDA Driver Version / Runtime Version 9.1 / 9.1
// CUDA Capability Major/Minor version number: 5.0
// Total amount of global memory: 1.95 MBytes (2090598400 bytes)
// GPU Clock rate: 1084 MHz (1.08 GHz)
// Memory Clock rate: 2700 Mhz
// Memory Bus Width: 128-bit
// L2 Cache Size: 2097152 bytes
// Max Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536,65536), 3D=(4096,4096,4096)
// Max Layered Texture Size (dim) x layers 1D=(16384) x 2048, 2D=(16384,16384) x 2048
// Total amount of constant memory: 65536 bytes
// Total amount of shared memory per block: 49152 bytes
// Total number of registers available per block: 65536
// Warp size: 32
// Maximum number of threads per multiprocessor: 2048
// Maximum number of threads per block: 1024
// Maximum sizes of each dimension of a block: 1024 x 1024 x 64
// Maximum sizes of each dimension of a grid: 2147483647 x 65535 x 65535
// Maximum memory pitch: 2147483647 bytes | // File: cudaGetDeviceProperties.cu
//
// Compiler Command:
// $ nvcc cudaGetDeviceProperties.cu -o cudaGetDeviceProperties
// Head files
#include <stdio.h>
#include <hip/hip_runtime.h>
// main function
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
int deviceCount = 0;
hipError_t error_id = hipGetDeviceCount(&deviceCount);
if (error_id != hipSuccess) {
printf("hipGetDeviceCount returned %d\n-> %s\n",
(int)error_id, hipGetErrorString(error_id));
printf("Result = FAIL\n");
exit(EXIT_FAILURE);
}
if (deviceCount == 0) {
printf("There are no available device(s) that support CUDA\n");
} else {
printf("Detected %d CUDA Capable device(s)\n", deviceCount);
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev =0;
hipSetDevice(dev);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("Device %d: \"%s\"\n", dev, deviceProp.name);
hipDriverGetVersion(&driverVersion);
hipRuntimeGetVersion(&runtimeVersion);
printf(" CUDA Driver Version / Runtime Version %d.%d / %d.%d\n",driverVersion/1000, (driverVersion%100)/10,runtimeVersion/1000, (runtimeVersion%100)/10);
printf(" CUDA Capability Major/Minor version number: %d.%d\n",deviceProp.major, deviceProp.minor);
printf(" Total amount of global memory: %.2f MBytes (%llu bytes)\n",(float)deviceProp.totalGlobalMem/(pow(1024.0,3)),(unsigned long long) deviceProp.totalGlobalMem);
printf(" GPU Clock rate: %.0f MHz (%0.2f GHz)\n",deviceProp.clockRate * 1e-3f, deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.0f Mhz\n",deviceProp.memoryClockRate * 1e-3f);
printf(" Memory Bus Width: %d-bit\n",deviceProp.memoryBusWidth);
if (deviceProp.l2CacheSize) {
printf(" L2 Cache Size: %d bytes\n",
deviceProp.l2CacheSize);
}
printf(" Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n",
deviceProp.maxTexture1D , deviceProp.maxTexture2D[0],
deviceProp.maxTexture2D[1],
deviceProp.maxTexture3D[0], deviceProp.maxTexture3D[1],
deviceProp.maxTexture3D[2]);
printf(" Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n",
deviceProp.maxTexture1DLayered[0], deviceProp.maxTexture1DLayered[1],
deviceProp.maxTexture2DLayered[0], deviceProp.maxTexture2DLayered[1],
deviceProp.maxTexture2DLayered[2]);
printf(" Total amount of constant memory: %lu bytes\n",deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %lu bytes\n",deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",deviceProp.regsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Maximum number of threads per multiprocessor: %d\n",deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %lu bytes\n", deviceProp.memPitch);
exit(EXIT_SUCCESS);
}
// For a system with multiple GPUs, it's necessary to choose one of these GPUs as our device.
// The stratage is that: the GPU with best performance must has the largest number of SMs.
// Implementation code listed below:
// int numDevices = 0;
// cudaGetDeviceCount(&numDevices);
// if (numDevices > 1) {
// int maxMultiprocessors = 0, maxDevice = 0;
// for (int device=0; device<numDevices; device++) {
// cudaDeviceProp props;
// cudaGetDeviceProperties(&props, device);
// if (maxMultiprocessors < props.multiProcessorCount) {
// maxMultiprocessors = props.multiProcessorCount;
// maxDevice = device;
// }
// }
// cudaSetDevice(maxDevice);
// }
// Runnning result
// yangyang@yangyang-XPS-8900:~/Desktop/cudaCodeDebug/CodeDebug2$ ./cudaGetDeviceProperties
// ./cudaGetDeviceProperties Starting...
// Detected 1 CUDA Capable device(s)
// Device 0: "GeForce GTX 750 Ti"
// CUDA Driver Version / Runtime Version 9.1 / 9.1
// CUDA Capability Major/Minor version number: 5.0
// Total amount of global memory: 1.95 MBytes (2090598400 bytes)
// GPU Clock rate: 1084 MHz (1.08 GHz)
// Memory Clock rate: 2700 Mhz
// Memory Bus Width: 128-bit
// L2 Cache Size: 2097152 bytes
// Max Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536,65536), 3D=(4096,4096,4096)
// Max Layered Texture Size (dim) x layers 1D=(16384) x 2048, 2D=(16384,16384) x 2048
// Total amount of constant memory: 65536 bytes
// Total amount of shared memory per block: 49152 bytes
// Total number of registers available per block: 65536
// Warp size: 32
// Maximum number of threads per multiprocessor: 2048
// Maximum number of threads per block: 1024
// Maximum sizes of each dimension of a block: 1024 x 1024 x 64
// Maximum sizes of each dimension of a grid: 2147483647 x 65535 x 65535
// Maximum memory pitch: 2147483647 bytes |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // File: cudaGetDeviceProperties.cu
//
// Compiler Command:
// $ nvcc cudaGetDeviceProperties.cu -o cudaGetDeviceProperties
// Head files
#include <stdio.h>
#include <hip/hip_runtime.h>
// main function
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
int deviceCount = 0;
hipError_t error_id = hipGetDeviceCount(&deviceCount);
if (error_id != hipSuccess) {
printf("hipGetDeviceCount returned %d\n-> %s\n",
(int)error_id, hipGetErrorString(error_id));
printf("Result = FAIL\n");
exit(EXIT_FAILURE);
}
if (deviceCount == 0) {
printf("There are no available device(s) that support CUDA\n");
} else {
printf("Detected %d CUDA Capable device(s)\n", deviceCount);
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev =0;
hipSetDevice(dev);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("Device %d: \"%s\"\n", dev, deviceProp.name);
hipDriverGetVersion(&driverVersion);
hipRuntimeGetVersion(&runtimeVersion);
printf(" CUDA Driver Version / Runtime Version %d.%d / %d.%d\n",driverVersion/1000, (driverVersion%100)/10,runtimeVersion/1000, (runtimeVersion%100)/10);
printf(" CUDA Capability Major/Minor version number: %d.%d\n",deviceProp.major, deviceProp.minor);
printf(" Total amount of global memory: %.2f MBytes (%llu bytes)\n",(float)deviceProp.totalGlobalMem/(pow(1024.0,3)),(unsigned long long) deviceProp.totalGlobalMem);
printf(" GPU Clock rate: %.0f MHz (%0.2f GHz)\n",deviceProp.clockRate * 1e-3f, deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.0f Mhz\n",deviceProp.memoryClockRate * 1e-3f);
printf(" Memory Bus Width: %d-bit\n",deviceProp.memoryBusWidth);
if (deviceProp.l2CacheSize) {
printf(" L2 Cache Size: %d bytes\n",
deviceProp.l2CacheSize);
}
printf(" Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n",
deviceProp.maxTexture1D , deviceProp.maxTexture2D[0],
deviceProp.maxTexture2D[1],
deviceProp.maxTexture3D[0], deviceProp.maxTexture3D[1],
deviceProp.maxTexture3D[2]);
printf(" Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n",
deviceProp.maxTexture1DLayered[0], deviceProp.maxTexture1DLayered[1],
deviceProp.maxTexture2DLayered[0], deviceProp.maxTexture2DLayered[1],
deviceProp.maxTexture2DLayered[2]);
printf(" Total amount of constant memory: %lu bytes\n",deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %lu bytes\n",deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",deviceProp.regsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Maximum number of threads per multiprocessor: %d\n",deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %lu bytes\n", deviceProp.memPitch);
exit(EXIT_SUCCESS);
}
// For a system with multiple GPUs, it's necessary to choose one of these GPUs as our device.
// The stratage is that: the GPU with best performance must has the largest number of SMs.
// Implementation code listed below:
// int numDevices = 0;
// cudaGetDeviceCount(&numDevices);
// if (numDevices > 1) {
// int maxMultiprocessors = 0, maxDevice = 0;
// for (int device=0; device<numDevices; device++) {
// cudaDeviceProp props;
// cudaGetDeviceProperties(&props, device);
// if (maxMultiprocessors < props.multiProcessorCount) {
// maxMultiprocessors = props.multiProcessorCount;
// maxDevice = device;
// }
// }
// cudaSetDevice(maxDevice);
// }
// Runnning result
// yangyang@yangyang-XPS-8900:~/Desktop/cudaCodeDebug/CodeDebug2$ ./cudaGetDeviceProperties
// ./cudaGetDeviceProperties Starting...
// Detected 1 CUDA Capable device(s)
// Device 0: "GeForce GTX 750 Ti"
// CUDA Driver Version / Runtime Version 9.1 / 9.1
// CUDA Capability Major/Minor version number: 5.0
// Total amount of global memory: 1.95 MBytes (2090598400 bytes)
// GPU Clock rate: 1084 MHz (1.08 GHz)
// Memory Clock rate: 2700 Mhz
// Memory Bus Width: 128-bit
// L2 Cache Size: 2097152 bytes
// Max Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536,65536), 3D=(4096,4096,4096)
// Max Layered Texture Size (dim) x layers 1D=(16384) x 2048, 2D=(16384,16384) x 2048
// Total amount of constant memory: 65536 bytes
// Total amount of shared memory per block: 49152 bytes
// Total number of registers available per block: 65536
// Warp size: 32
// Maximum number of threads per multiprocessor: 2048
// Maximum number of threads per block: 1024
// Maximum sizes of each dimension of a block: 1024 x 1024 x 64
// Maximum sizes of each dimension of a grid: 2147483647 x 65535 x 65535
// Maximum memory pitch: 2147483647 bytes | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // File: cudaGetDeviceProperties.cu
//
// Compiler Command:
// $ nvcc cudaGetDeviceProperties.cu -o cudaGetDeviceProperties
// Head files
#include <stdio.h>
#include <hip/hip_runtime.h>
// main function
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
int deviceCount = 0;
hipError_t error_id = hipGetDeviceCount(&deviceCount);
if (error_id != hipSuccess) {
printf("hipGetDeviceCount returned %d\n-> %s\n",
(int)error_id, hipGetErrorString(error_id));
printf("Result = FAIL\n");
exit(EXIT_FAILURE);
}
if (deviceCount == 0) {
printf("There are no available device(s) that support CUDA\n");
} else {
printf("Detected %d CUDA Capable device(s)\n", deviceCount);
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev =0;
hipSetDevice(dev);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("Device %d: \"%s\"\n", dev, deviceProp.name);
hipDriverGetVersion(&driverVersion);
hipRuntimeGetVersion(&runtimeVersion);
printf(" CUDA Driver Version / Runtime Version %d.%d / %d.%d\n",driverVersion/1000, (driverVersion%100)/10,runtimeVersion/1000, (runtimeVersion%100)/10);
printf(" CUDA Capability Major/Minor version number: %d.%d\n",deviceProp.major, deviceProp.minor);
printf(" Total amount of global memory: %.2f MBytes (%llu bytes)\n",(float)deviceProp.totalGlobalMem/(pow(1024.0,3)),(unsigned long long) deviceProp.totalGlobalMem);
printf(" GPU Clock rate: %.0f MHz (%0.2f GHz)\n",deviceProp.clockRate * 1e-3f, deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.0f Mhz\n",deviceProp.memoryClockRate * 1e-3f);
printf(" Memory Bus Width: %d-bit\n",deviceProp.memoryBusWidth);
if (deviceProp.l2CacheSize) {
printf(" L2 Cache Size: %d bytes\n",
deviceProp.l2CacheSize);
}
printf(" Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n",
deviceProp.maxTexture1D , deviceProp.maxTexture2D[0],
deviceProp.maxTexture2D[1],
deviceProp.maxTexture3D[0], deviceProp.maxTexture3D[1],
deviceProp.maxTexture3D[2]);
printf(" Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n",
deviceProp.maxTexture1DLayered[0], deviceProp.maxTexture1DLayered[1],
deviceProp.maxTexture2DLayered[0], deviceProp.maxTexture2DLayered[1],
deviceProp.maxTexture2DLayered[2]);
printf(" Total amount of constant memory: %lu bytes\n",deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %lu bytes\n",deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",deviceProp.regsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Maximum number of threads per multiprocessor: %d\n",deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %lu bytes\n", deviceProp.memPitch);
exit(EXIT_SUCCESS);
}
// For a system with multiple GPUs, it's necessary to choose one of these GPUs as our device.
// The stratage is that: the GPU with best performance must has the largest number of SMs.
// Implementation code listed below:
// int numDevices = 0;
// cudaGetDeviceCount(&numDevices);
// if (numDevices > 1) {
// int maxMultiprocessors = 0, maxDevice = 0;
// for (int device=0; device<numDevices; device++) {
// cudaDeviceProp props;
// cudaGetDeviceProperties(&props, device);
// if (maxMultiprocessors < props.multiProcessorCount) {
// maxMultiprocessors = props.multiProcessorCount;
// maxDevice = device;
// }
// }
// cudaSetDevice(maxDevice);
// }
// Runnning result
// yangyang@yangyang-XPS-8900:~/Desktop/cudaCodeDebug/CodeDebug2$ ./cudaGetDeviceProperties
// ./cudaGetDeviceProperties Starting...
// Detected 1 CUDA Capable device(s)
// Device 0: "GeForce GTX 750 Ti"
// CUDA Driver Version / Runtime Version 9.1 / 9.1
// CUDA Capability Major/Minor version number: 5.0
// Total amount of global memory: 1.95 MBytes (2090598400 bytes)
// GPU Clock rate: 1084 MHz (1.08 GHz)
// Memory Clock rate: 2700 Mhz
// Memory Bus Width: 128-bit
// L2 Cache Size: 2097152 bytes
// Max Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536,65536), 3D=(4096,4096,4096)
// Max Layered Texture Size (dim) x layers 1D=(16384) x 2048, 2D=(16384,16384) x 2048
// Total amount of constant memory: 65536 bytes
// Total amount of shared memory per block: 49152 bytes
// Total number of registers available per block: 65536
// Warp size: 32
// Maximum number of threads per multiprocessor: 2048
// Maximum number of threads per block: 1024
// Maximum sizes of each dimension of a block: 1024 x 1024 x 64
// Maximum sizes of each dimension of a grid: 2147483647 x 65535 x 65535
// Maximum memory pitch: 2147483647 bytes | .text
.file "cudaGetDeviceProperties.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_1:
.long 0x3a83126f # float 0.00100000005
.LCPI0_2:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1504, %rsp # imm = 0x5E0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -16
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $0, 28(%rsp)
leaq 28(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_10
# %bb.1:
movl 28(%rsp), %esi
testl %esi, %esi
jne .LBB0_3
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB0_4
.LBB0_10:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.1, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB0_3:
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
.LBB0_4:
movl $0, 24(%rsp)
movl $0, 20(%rsp)
xorl %edi, %edi
callq hipSetDevice
leaq 32(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.5, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
callq hipDriverGetVersion
leaq 20(%rsp), %rdi
callq hipRuntimeGetVersion
movslq 24(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movslq 20(%rsp), %rax
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdi
shrq $63, %rdi
sarq $38, %rcx
addl %edi, %ecx
imulq $1374389535, %rax, %rdi # imm = 0x51EB851F
movq %rdi, %r8
shrq $63, %r8
sarq $37, %rdi
addl %r8d, %edi
imull $100, %edi, %edi
subl %edi, %eax
cltq
imulq $1717986919, %rax, %r8 # imm = 0x66666667
movq %r8, %rax
shrq $63, %rax
sarq $34, %r8
addl %eax, %r8d
movl $.L.str.6, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
# kill: def $r8d killed $r8d killed $r8
xorl %eax, %eax
callq printf
movl 392(%rsp), %esi
movl 396(%rsp), %edx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
testq %rsi, %rsi
js .LBB0_5
# %bb.6:
cvtsi2ss %rsi, %xmm0
jmp .LBB0_7
.LBB0_5:
movq %rsi, %rax
shrq %rax
movl %esi, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB0_7:
cvtss2sd %xmm0, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
cvtsi2ssl 380(%rsp), %xmm1
movaps %xmm1, %xmm0
mulss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulss .LCPI0_2(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.9, %edi
movb $2, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 640(%rsp), %xmm0
mulss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movl 644(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 648(%rsp), %esi
testl %esi, %esi
je .LBB0_9
# %bb.8:
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
.LBB0_9:
movl 440(%rsp), %esi
movl 452(%rsp), %edx
movl 456(%rsp), %ecx
movl 488(%rsp), %r8d
movl 492(%rsp), %r9d
movl 496(%rsp), %eax
movl %eax, (%rsp)
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 516(%rsp), %esi
movl 520(%rsp), %edx
movl 524(%rsp), %ecx
movl 528(%rsp), %r8d
movl 532(%rsp), %r9d
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
movl 656(%rsp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl 360(%rsp), %edx
movl 364(%rsp), %ecx
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl 376(%rsp), %ecx
movl $.L.str.22, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s Starting...\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipGetDeviceCount returned %d\n-> %s\n"
.size .L.str.1, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Detected %d CUDA Capable device(s)\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Device %d: \"%s\"\n"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " CUDA Driver Version / Runtime Version %d.%d / %d.%d\n"
.size .L.str.6, 54
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " CUDA Capability Major/Minor version number: %d.%d\n"
.size .L.str.7, 52
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Total amount of global memory: %.2f MBytes (%llu bytes)\n"
.size .L.str.8, 58
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " GPU Clock rate: %.0f MHz (%0.2f GHz)\n"
.size .L.str.9, 39
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Memory Clock rate: %.0f Mhz\n"
.size .L.str.10, 30
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Memory Bus Width: %d-bit\n"
.size .L.str.11, 27
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " L2 Cache Size: %d bytes\n"
.size .L.str.12, 26
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n"
.size .L.str.13, 72
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n"
.size .L.str.14, 72
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " Total amount of constant memory: %lu bytes\n"
.size .L.str.15, 45
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " Total amount of shared memory per block: %lu bytes\n"
.size .L.str.16, 53
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " Total number of registers available per block: %d\n"
.size .L.str.17, 52
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " Warp size: %d\n"
.size .L.str.18, 16
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " Maximum number of threads per multiprocessor: %d\n"
.size .L.str.19, 51
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " Maximum number of threads per block: %d\n"
.size .L.str.20, 42
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.size .L.str.21, 59
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.size .L.str.22, 58
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz " Maximum memory pitch: %lu bytes\n"
.size .L.str.23, 34
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There are no available device(s) that support CUDA"
.size .Lstr, 51
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Result = FAIL"
.size .Lstr.1, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013c40f_00000000-6_cudaGetDeviceProperties.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s Starting...\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaGetDeviceCount returned %d\n-> %s\n"
.section .rodata.str1.1
.LC2:
.string "Result = FAIL\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "There are no available device(s) that support CUDA\n"
.align 8
.LC4:
.string "Detected %d CUDA Capable device(s)\n"
.section .rodata.str1.1
.LC5:
.string "Device %d: \"%s\"\n"
.section .rodata.str1.8
.align 8
.LC6:
.string " CUDA Driver Version / Runtime Version %d.%d / %d.%d\n"
.align 8
.LC7:
.string " CUDA Capability Major/Minor version number: %d.%d\n"
.align 8
.LC9:
.string " Total amount of global memory: %.2f MBytes (%llu bytes)\n"
.align 8
.LC12:
.string " GPU Clock rate: %.0f MHz (%0.2f GHz)\n"
.section .rodata.str1.1
.LC13:
.string " Memory Clock rate: %.0f Mhz\n"
.LC14:
.string " Memory Bus Width: %d-bit\n"
.LC15:
.string " L2 Cache Size: %d bytes\n"
.section .rodata.str1.8
.align 8
.LC16:
.string " Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n"
.align 8
.LC17:
.string " Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n"
.align 8
.LC18:
.string " Total amount of constant memory: %lu bytes\n"
.align 8
.LC19:
.string " Total amount of shared memory per block: %lu bytes\n"
.align 8
.LC20:
.string " Total number of registers available per block: %d\n"
.section .rodata.str1.1
.LC21:
.string " Warp size: %d\n"
.section .rodata.str1.8
.align 8
.LC22:
.string " Maximum number of threads per multiprocessor: %d\n"
.align 8
.LC23:
.string " Maximum number of threads per block: %d\n"
.align 8
.LC24:
.string " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.align 8
.LC25:
.string " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.align 8
.LC26:
.string " Maximum memory pitch: %lu bytes\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl 4(%rsp), %edx
testl %edx, %edx
jne .L5
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movl $0, 8(%rsp)
movl $0, 12(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq 12(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
movl 12(%rsp), %eax
movl 8(%rsp), %ecx
movslq %eax, %r8
imulq $1374389535, %r8, %rdx
sarq $37, %rdx
movl %eax, %edi
sarl $31, %edi
subl %edi, %edx
imull $100, %edx, %edx
subl %edx, %eax
movslq %eax, %r9
imulq $1717986919, %r9, %r9
sarq $34, %r9
sarl $31, %eax
imulq $274877907, %r8, %r8
sarq $38, %r8
movslq %ecx, %rdx
imulq $1374389535, %rdx, %rsi
sarq $37, %rsi
movl %ecx, %r10d
sarl $31, %r10d
subl %r10d, %esi
imull $100, %esi, %esi
subl %esi, %ecx
movslq %ecx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %ecx
subl %ecx, %esi
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
subl %r10d, %edx
subl %eax, %r9d
subl %edi, %r8d
movl %esi, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
testq %rdx, %rdx
js .L7
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
.L8:
cvtss2sd %xmm0, %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
movaps %xmm0, %xmm1
mulss .LC10(%rip), %xmm1
mulss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 628(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 632(%rsp), %edx
testl %edx, %edx
jne .L13
.L9:
movl 480(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1080
movl 484(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1088
movl 488(%rsp), %r9d
movl 456(%rsp), %r8d
movl 452(%rsp), %ecx
movl 440(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 532(%rsp), %eax
movl %eax, (%rsp)
movl 528(%rsp), %r9d
movl 524(%rsp), %r8d
movl 520(%rsp), %ecx
movl 516(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1072
movq 368(%rsp), %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L5:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L7:
movq %rdx, %rax
shrq %rax
movq %rdx, %rcx
andl $1, %ecx
orq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L8
.L13:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1041235968
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 897988541
.align 4
.LC11:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaGetDeviceProperties.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_1:
.long 0x3a83126f # float 0.00100000005
.LCPI0_2:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1504, %rsp # imm = 0x5E0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -16
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $0, 28(%rsp)
leaq 28(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_10
# %bb.1:
movl 28(%rsp), %esi
testl %esi, %esi
jne .LBB0_3
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB0_4
.LBB0_10:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.1, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB0_3:
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
.LBB0_4:
movl $0, 24(%rsp)
movl $0, 20(%rsp)
xorl %edi, %edi
callq hipSetDevice
leaq 32(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.5, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
callq hipDriverGetVersion
leaq 20(%rsp), %rdi
callq hipRuntimeGetVersion
movslq 24(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movslq 20(%rsp), %rax
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdi
shrq $63, %rdi
sarq $38, %rcx
addl %edi, %ecx
imulq $1374389535, %rax, %rdi # imm = 0x51EB851F
movq %rdi, %r8
shrq $63, %r8
sarq $37, %rdi
addl %r8d, %edi
imull $100, %edi, %edi
subl %edi, %eax
cltq
imulq $1717986919, %rax, %r8 # imm = 0x66666667
movq %r8, %rax
shrq $63, %rax
sarq $34, %r8
addl %eax, %r8d
movl $.L.str.6, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
# kill: def $r8d killed $r8d killed $r8
xorl %eax, %eax
callq printf
movl 392(%rsp), %esi
movl 396(%rsp), %edx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
testq %rsi, %rsi
js .LBB0_5
# %bb.6:
cvtsi2ss %rsi, %xmm0
jmp .LBB0_7
.LBB0_5:
movq %rsi, %rax
shrq %rax
movl %esi, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB0_7:
cvtss2sd %xmm0, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
cvtsi2ssl 380(%rsp), %xmm1
movaps %xmm1, %xmm0
mulss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulss .LCPI0_2(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.9, %edi
movb $2, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 640(%rsp), %xmm0
mulss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movl 644(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 648(%rsp), %esi
testl %esi, %esi
je .LBB0_9
# %bb.8:
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
.LBB0_9:
movl 440(%rsp), %esi
movl 452(%rsp), %edx
movl 456(%rsp), %ecx
movl 488(%rsp), %r8d
movl 492(%rsp), %r9d
movl 496(%rsp), %eax
movl %eax, (%rsp)
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 516(%rsp), %esi
movl 520(%rsp), %edx
movl 524(%rsp), %ecx
movl 528(%rsp), %r8d
movl 532(%rsp), %r9d
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
movl 656(%rsp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl 360(%rsp), %edx
movl 364(%rsp), %ecx
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl 376(%rsp), %ecx
movl $.L.str.22, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s Starting...\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipGetDeviceCount returned %d\n-> %s\n"
.size .L.str.1, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Detected %d CUDA Capable device(s)\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Device %d: \"%s\"\n"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " CUDA Driver Version / Runtime Version %d.%d / %d.%d\n"
.size .L.str.6, 54
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " CUDA Capability Major/Minor version number: %d.%d\n"
.size .L.str.7, 52
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Total amount of global memory: %.2f MBytes (%llu bytes)\n"
.size .L.str.8, 58
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " GPU Clock rate: %.0f MHz (%0.2f GHz)\n"
.size .L.str.9, 39
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Memory Clock rate: %.0f Mhz\n"
.size .L.str.10, 30
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Memory Bus Width: %d-bit\n"
.size .L.str.11, 27
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " L2 Cache Size: %d bytes\n"
.size .L.str.12, 26
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Max Texture Dimension Size (x,y,z) 1D=(%d), 2D=(%d,%d), 3D=(%d,%d,%d)\n"
.size .L.str.13, 72
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Max Layered Texture Size (dim) x layers 1D=(%d) x %d, 2D=(%d,%d) x %d\n"
.size .L.str.14, 72
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " Total amount of constant memory: %lu bytes\n"
.size .L.str.15, 45
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " Total amount of shared memory per block: %lu bytes\n"
.size .L.str.16, 53
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " Total number of registers available per block: %d\n"
.size .L.str.17, 52
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " Warp size: %d\n"
.size .L.str.18, 16
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " Maximum number of threads per multiprocessor: %d\n"
.size .L.str.19, 51
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " Maximum number of threads per block: %d\n"
.size .L.str.20, 42
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.size .L.str.21, 59
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.size .L.str.22, 58
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz " Maximum memory pitch: %lu bytes\n"
.size .L.str.23, 34
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There are no available device(s) that support CUDA"
.size .Lstr, 51
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Result = FAIL"
.size .Lstr.1, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call.
// this is a No-op in release builds.
// inline suggests to the compiler to define this function in
// a way that it can be replaceable. This can speed up execution.
// this presents the compiler from going through the normal function
// overhead when it is called. It isn't looked up. It is compiled so
// that the instructions are just right there. This is used when the
// function has a small number of instructions.
inline cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n",
cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
// Copies the data between the device and the host. It also takes
// performance measurements.
// If the transfers are small, then it would be better in a real
// application to do them batched transfers. You can do this by
// using a temporary array, preferably pinned, and packing all
// of the data that needs to be transferred into it. Transfer
// it when ready.
// this method can be used: (there is also a 3D version)
// cudaMemcpy2D(dest, dest_pitch, src, src_pitch, w, h, cudaMemcpyHostToDevice)
void profileCopies(float* h_a, float* h_b, float* d, unsigned int n, char* desc) {
printf("\n%s transfers\n", desc);
unsigned int bytes = n * sizeof(float);
//events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda(cudaEventCreate(&startEvent));
checkCuda(cudaEventCreate(&stopEvent));
// record the time it takes for the host to copy the
// data over to the device.
// Note, it's better to do this kind of analysis with
// nvprof or Nsight rather than instrument the code.
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(d, h_a, bytes, cudaMemcpyHostToDevice));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
// print result
float time;
checkCuda(cudaEventElapsedTime(&time, startEvent, stopEvent));
printf(" Host to Deice bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
// Do the same thing from the device back to the host.
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(h_b, d, bytes, cudaMemcpyDeviceToHost));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&time, startEvent, stopEvent));
printf(" Device to Host bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
for (int i = 0; i < n; i++) {
if (h_a[i] != h_b[i]) {
printf("*** %s transfers failed *** \n", desc);
break;
}
}
// clean up events
checkCuda(cudaEventDestroy(startEvent));
checkCuda(cudaEventDestroy(stopEvent));
}
int main()
{
unsigned int nElements = 4 * 1024 * 1024;
const unsigned int bytes = nElements * sizeof(float);
//host arrays
float *h_aPageable, *h_bPageable;
float *h_aPinned, *h_bPinned;
// device array
float *d_a;
// allocate and initialize
h_aPageable = (float*)malloc(bytes); // host pageable
h_bPageable = (float*)malloc(bytes); // host pageable
checkCuda(cudaMallocHost((void**)&h_aPinned, bytes)); // host pinned
checkCuda(cudaMallocHost((void**)&h_bPinned, bytes)); // host pinned
checkCuda(cudaMalloc((void**)&d_a, bytes)); // device
for (int i = 0; i < nElements; ++i) {
h_aPageable[i] = i;
}
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPageable, 0, bytes);
// output device info and transfer size
cudaDeviceProp prop;
checkCuda(cudaGetDeviceProperties(&prop, 0));
printf("\nDevice: %s\n", prop.name);
printf("Transfer size (MB): %d\n", bytes / (1024 * 1024));
// perform copies and report bandwidth
profileCopies(h_aPageable, h_bPageable, d_a, nElements, "Pageable");
profileCopies(h_aPinned, h_bPinned, d_a, nElements, "Pinned");
printf("\n");
// cleanup
cudaFree(d_a);
cudaFreeHost(h_aPinned);
cudaFreeHost(h_bPinned);
free(h_aPageable);
free(h_bPageable);
// On my machine the pinned memory is over 3 times faster.
// This is all device dependent, however.
// Do not overuse Pinned Memory though. It limits the memory
// available to the operating system, etc. So, test to make
// sure the application is working suitably.
// Ultimately, take care to minimize the number of transfers
// and to optomize them when they must happen. This is the
// bottleneck of hybrid CPU/GPU computing.
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call.
// this is a No-op in release builds.
// inline suggests to the compiler to define this function in
// a way that it can be replaceable. This can speed up execution.
// this presents the compiler from going through the normal function
// overhead when it is called. It isn't looked up. It is compiled so
// that the instructions are just right there. This is used when the
// function has a small number of instructions.
inline cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n",
cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
// Copies the data between the device and the host. It also takes
// performance measurements.
// If the transfers are small, then it would be better in a real
// application to do them batched transfers. You can do this by
// using a temporary array, preferably pinned, and packing all
// of the data that needs to be transferred into it. Transfer
// it when ready.
// this method can be used: (there is also a 3D version)
// cudaMemcpy2D(dest, dest_pitch, src, src_pitch, w, h, cudaMemcpyHostToDevice)
void profileCopies(float* h_a, float* h_b, float* d, unsigned int n, char* desc) {
printf("\n%s transfers\n", desc);
unsigned int bytes = n * sizeof(float);
//events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda(cudaEventCreate(&startEvent));
checkCuda(cudaEventCreate(&stopEvent));
// record the time it takes for the host to copy the
// data over to the device.
// Note, it's better to do this kind of analysis with
// nvprof or Nsight rather than instrument the code.
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(d, h_a, bytes, cudaMemcpyHostToDevice));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
// print result
float time;
checkCuda(cudaEventElapsedTime(&time, startEvent, stopEvent));
printf(" Host to Deice bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
// Do the same thing from the device back to the host.
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(h_b, d, bytes, cudaMemcpyDeviceToHost));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&time, startEvent, stopEvent));
printf(" Device to Host bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
for (int i = 0; i < n; i++) {
if (h_a[i] != h_b[i]) {
printf("*** %s transfers failed *** \n", desc);
break;
}
}
// clean up events
checkCuda(cudaEventDestroy(startEvent));
checkCuda(cudaEventDestroy(stopEvent));
}
int main()
{
unsigned int nElements = 4 * 1024 * 1024;
const unsigned int bytes = nElements * sizeof(float);
//host arrays
float *h_aPageable, *h_bPageable;
float *h_aPinned, *h_bPinned;
// device array
float *d_a;
// allocate and initialize
h_aPageable = (float*)malloc(bytes); // host pageable
h_bPageable = (float*)malloc(bytes); // host pageable
checkCuda(cudaMallocHost((void**)&h_aPinned, bytes)); // host pinned
checkCuda(cudaMallocHost((void**)&h_bPinned, bytes)); // host pinned
checkCuda(cudaMalloc((void**)&d_a, bytes)); // device
for (int i = 0; i < nElements; ++i) {
h_aPageable[i] = i;
}
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPageable, 0, bytes);
// output device info and transfer size
cudaDeviceProp prop;
checkCuda(cudaGetDeviceProperties(&prop, 0));
printf("\nDevice: %s\n", prop.name);
printf("Transfer size (MB): %d\n", bytes / (1024 * 1024));
// perform copies and report bandwidth
profileCopies(h_aPageable, h_bPageable, d_a, nElements, "Pageable");
profileCopies(h_aPinned, h_bPinned, d_a, nElements, "Pinned");
printf("\n");
// cleanup
cudaFree(d_a);
cudaFreeHost(h_aPinned);
cudaFreeHost(h_bPinned);
free(h_aPageable);
free(h_bPageable);
// On my machine the pinned memory is over 3 times faster.
// This is all device dependent, however.
// Do not overuse Pinned Memory though. It limits the memory
// available to the operating system, etc. So, test to make
// sure the application is working suitably.
// Ultimately, take care to minimize the number of transfers
// and to optomize them when they must happen. This is the
// bottleneck of hybrid CPU/GPU computing.
return 0;
} | .file "tmpxft_0019a053_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n%s transfers\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string " Host to Deice bandwidth (GB/s): %f\n"
.align 8
.LC3:
.string " Device to Host bandwidth (GB/s): %f\n"
.section .rodata.str1.1
.LC4:
.string "*** %s transfers failed *** \n"
.text
.globl _Z13profileCopiesPfS_S_jPc
.type _Z13profileCopiesPfS_S_jPc, @function
_Z13profileCopiesPfS_S_jPc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r14
movl %ecx, %r12d
movq %r8, %r15
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %r8, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leal 0(,%r12,4), %r13d
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %r13d, %r13d
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
movsd %xmm0, 8(%rsp)
divsd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
movsd 8(%rsp), %xmm0
divsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %r12d, %r12d
je .L6
movl %r12d, %r12d
salq $2, %r12
movl $0, %eax
.L9:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L11
jne .L11
addq $4, %rax
cmpq %r12, %rax
jne .L9
jmp .L6
.L11:
movq %r15, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z13profileCopiesPfS_S_jPc, .-_Z13profileCopiesPfS_S_jPc
.section .rodata.str1.1
.LC5:
.string "\nDevice: %s\n"
.LC6:
.string "Transfer size (MB): %d\n"
.LC7:
.string "Pageable"
.LC8:
.string "Pinned"
.LC9:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1072, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $0, %eax
.L16:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L16
movl $16777216, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call memcpy@PLT
movl $16777216, %edx
movl $0, %esi
movq %rbp, %rdi
call memset@PLT
leaq 32(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %r12, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %r8
movl $4194304, %ecx
movq 24(%rsp), %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z13profileCopiesPfS_S_jPc
leaq .LC8(%rip), %r8
movl $4194304, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z13profileCopiesPfS_S_jPc
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call.
// this is a No-op in release builds.
// inline suggests to the compiler to define this function in
// a way that it can be replaceable. This can speed up execution.
// this presents the compiler from going through the normal function
// overhead when it is called. It isn't looked up. It is compiled so
// that the instructions are just right there. This is used when the
// function has a small number of instructions.
inline cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n",
cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
// Copies the data between the device and the host. It also takes
// performance measurements.
// If the transfers are small, then it would be better in a real
// application to do them batched transfers. You can do this by
// using a temporary array, preferably pinned, and packing all
// of the data that needs to be transferred into it. Transfer
// it when ready.
// this method can be used: (there is also a 3D version)
// cudaMemcpy2D(dest, dest_pitch, src, src_pitch, w, h, cudaMemcpyHostToDevice)
void profileCopies(float* h_a, float* h_b, float* d, unsigned int n, char* desc) {
printf("\n%s transfers\n", desc);
unsigned int bytes = n * sizeof(float);
//events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda(cudaEventCreate(&startEvent));
checkCuda(cudaEventCreate(&stopEvent));
// record the time it takes for the host to copy the
// data over to the device.
// Note, it's better to do this kind of analysis with
// nvprof or Nsight rather than instrument the code.
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(d, h_a, bytes, cudaMemcpyHostToDevice));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
// print result
float time;
checkCuda(cudaEventElapsedTime(&time, startEvent, stopEvent));
printf(" Host to Deice bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
// Do the same thing from the device back to the host.
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(h_b, d, bytes, cudaMemcpyDeviceToHost));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&time, startEvent, stopEvent));
printf(" Device to Host bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
for (int i = 0; i < n; i++) {
if (h_a[i] != h_b[i]) {
printf("*** %s transfers failed *** \n", desc);
break;
}
}
// clean up events
checkCuda(cudaEventDestroy(startEvent));
checkCuda(cudaEventDestroy(stopEvent));
}
int main()
{
unsigned int nElements = 4 * 1024 * 1024;
const unsigned int bytes = nElements * sizeof(float);
//host arrays
float *h_aPageable, *h_bPageable;
float *h_aPinned, *h_bPinned;
// device array
float *d_a;
// allocate and initialize
h_aPageable = (float*)malloc(bytes); // host pageable
h_bPageable = (float*)malloc(bytes); // host pageable
checkCuda(cudaMallocHost((void**)&h_aPinned, bytes)); // host pinned
checkCuda(cudaMallocHost((void**)&h_bPinned, bytes)); // host pinned
checkCuda(cudaMalloc((void**)&d_a, bytes)); // device
for (int i = 0; i < nElements; ++i) {
h_aPageable[i] = i;
}
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPageable, 0, bytes);
// output device info and transfer size
cudaDeviceProp prop;
checkCuda(cudaGetDeviceProperties(&prop, 0));
printf("\nDevice: %s\n", prop.name);
printf("Transfer size (MB): %d\n", bytes / (1024 * 1024));
// perform copies and report bandwidth
profileCopies(h_aPageable, h_bPageable, d_a, nElements, "Pageable");
profileCopies(h_aPinned, h_bPinned, d_a, nElements, "Pinned");
printf("\n");
// cleanup
cudaFree(d_a);
cudaFreeHost(h_aPinned);
cudaFreeHost(h_bPinned);
free(h_aPageable);
free(h_bPageable);
// On my machine the pinned memory is over 3 times faster.
// This is all device dependent, however.
// Do not overuse Pinned Memory though. It limits the memory
// available to the operating system, etc. So, test to make
// sure the application is working suitably.
// Ultimately, take care to minimize the number of transfers
// and to optomize them when they must happen. This is the
// bottleneck of hybrid CPU/GPU computing.
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call.
// this is a No-op in release builds.
// inline suggests to the compiler to define this function in
// a way that it can be replaceable. This can speed up execution.
// this presents the compiler from going through the normal function
// overhead when it is called. It isn't looked up. It is compiled so
// that the instructions are just right there. This is used when the
// function has a small number of instructions.
inline hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n",
hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
// Copies the data between the device and the host. It also takes
// performance measurements.
// If the transfers are small, then it would be better in a real
// application to do them batched transfers. You can do this by
// using a temporary array, preferably pinned, and packing all
// of the data that needs to be transferred into it. Transfer
// it when ready.
// this method can be used: (there is also a 3D version)
// cudaMemcpy2D(dest, dest_pitch, src, src_pitch, w, h, cudaMemcpyHostToDevice)
void profileCopies(float* h_a, float* h_b, float* d, unsigned int n, char* desc) {
printf("\n%s transfers\n", desc);
unsigned int bytes = n * sizeof(float);
//events for timing
hipEvent_t startEvent, stopEvent;
checkCuda(hipEventCreate(&startEvent));
checkCuda(hipEventCreate(&stopEvent));
// record the time it takes for the host to copy the
// data over to the device.
// Note, it's better to do this kind of analysis with
// nvprof or Nsight rather than instrument the code.
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(d, h_a, bytes, hipMemcpyHostToDevice));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
// print result
float time;
checkCuda(hipEventElapsedTime(&time, startEvent, stopEvent));
printf(" Host to Deice bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
// Do the same thing from the device back to the host.
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(h_b, d, bytes, hipMemcpyDeviceToHost));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&time, startEvent, stopEvent));
printf(" Device to Host bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
for (int i = 0; i < n; i++) {
if (h_a[i] != h_b[i]) {
printf("*** %s transfers failed *** \n", desc);
break;
}
}
// clean up events
checkCuda(hipEventDestroy(startEvent));
checkCuda(hipEventDestroy(stopEvent));
}
int main()
{
unsigned int nElements = 4 * 1024 * 1024;
const unsigned int bytes = nElements * sizeof(float);
//host arrays
float *h_aPageable, *h_bPageable;
float *h_aPinned, *h_bPinned;
// device array
float *d_a;
// allocate and initialize
h_aPageable = (float*)malloc(bytes); // host pageable
h_bPageable = (float*)malloc(bytes); // host pageable
checkCuda(hipHostMalloc((void**)&h_aPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipHostMalloc((void**)&h_bPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipMalloc((void**)&d_a, bytes)); // device
for (int i = 0; i < nElements; ++i) {
h_aPageable[i] = i;
}
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPageable, 0, bytes);
// output device info and transfer size
hipDeviceProp_t prop;
checkCuda(hipGetDeviceProperties(&prop, 0));
printf("\nDevice: %s\n", prop.name);
printf("Transfer size (MB): %d\n", bytes / (1024 * 1024));
// perform copies and report bandwidth
profileCopies(h_aPageable, h_bPageable, d_a, nElements, "Pageable");
profileCopies(h_aPinned, h_bPinned, d_a, nElements, "Pinned");
printf("\n");
// cleanup
hipFree(d_a);
hipHostFree(h_aPinned);
hipHostFree(h_bPinned);
free(h_aPageable);
free(h_bPageable);
// On my machine the pinned memory is over 3 times faster.
// This is all device dependent, however.
// Do not overuse Pinned Memory though. It limits the memory
// available to the operating system, etc. So, test to make
// sure the application is working suitably.
// Ultimately, take care to minimize the number of transfers
// and to optomize them when they must happen. This is the
// bottleneck of hybrid CPU/GPU computing.
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call.
// this is a No-op in release builds.
// inline suggests to the compiler to define this function in
// a way that it can be replaceable. This can speed up execution.
// this presents the compiler from going through the normal function
// overhead when it is called. It isn't looked up. It is compiled so
// that the instructions are just right there. This is used when the
// function has a small number of instructions.
inline hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n",
hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
// Copies the data between the device and the host. It also takes
// performance measurements.
// If the transfers are small, then it would be better in a real
// application to do them batched transfers. You can do this by
// using a temporary array, preferably pinned, and packing all
// of the data that needs to be transferred into it. Transfer
// it when ready.
// this method can be used: (there is also a 3D version)
// cudaMemcpy2D(dest, dest_pitch, src, src_pitch, w, h, cudaMemcpyHostToDevice)
void profileCopies(float* h_a, float* h_b, float* d, unsigned int n, char* desc) {
printf("\n%s transfers\n", desc);
unsigned int bytes = n * sizeof(float);
//events for timing
hipEvent_t startEvent, stopEvent;
checkCuda(hipEventCreate(&startEvent));
checkCuda(hipEventCreate(&stopEvent));
// record the time it takes for the host to copy the
// data over to the device.
// Note, it's better to do this kind of analysis with
// nvprof or Nsight rather than instrument the code.
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(d, h_a, bytes, hipMemcpyHostToDevice));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
// print result
float time;
checkCuda(hipEventElapsedTime(&time, startEvent, stopEvent));
printf(" Host to Deice bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
// Do the same thing from the device back to the host.
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(h_b, d, bytes, hipMemcpyDeviceToHost));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&time, startEvent, stopEvent));
printf(" Device to Host bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
for (int i = 0; i < n; i++) {
if (h_a[i] != h_b[i]) {
printf("*** %s transfers failed *** \n", desc);
break;
}
}
// clean up events
checkCuda(hipEventDestroy(startEvent));
checkCuda(hipEventDestroy(stopEvent));
}
int main()
{
unsigned int nElements = 4 * 1024 * 1024;
const unsigned int bytes = nElements * sizeof(float);
//host arrays
float *h_aPageable, *h_bPageable;
float *h_aPinned, *h_bPinned;
// device array
float *d_a;
// allocate and initialize
h_aPageable = (float*)malloc(bytes); // host pageable
h_bPageable = (float*)malloc(bytes); // host pageable
checkCuda(hipHostMalloc((void**)&h_aPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipHostMalloc((void**)&h_bPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipMalloc((void**)&d_a, bytes)); // device
for (int i = 0; i < nElements; ++i) {
h_aPageable[i] = i;
}
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPageable, 0, bytes);
// output device info and transfer size
hipDeviceProp_t prop;
checkCuda(hipGetDeviceProperties(&prop, 0));
printf("\nDevice: %s\n", prop.name);
printf("Transfer size (MB): %d\n", bytes / (1024 * 1024));
// perform copies and report bandwidth
profileCopies(h_aPageable, h_bPageable, d_a, nElements, "Pageable");
profileCopies(h_aPinned, h_bPinned, d_a, nElements, "Pinned");
printf("\n");
// cleanup
hipFree(d_a);
hipHostFree(h_aPinned);
hipHostFree(h_bPinned);
free(h_aPageable);
free(h_bPageable);
// On my machine the pinned memory is over 3 times faster.
// This is all device dependent, however.
// Do not overuse Pinned Memory though. It limits the memory
// available to the operating system, etc. So, test to make
// sure the application is working suitably.
// Ultimately, take care to minimize the number of transfers
// and to optomize them when they must happen. This is the
// bottleneck of hybrid CPU/GPU computing.
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call.
// this is a No-op in release builds.
// inline suggests to the compiler to define this function in
// a way that it can be replaceable. This can speed up execution.
// this presents the compiler from going through the normal function
// overhead when it is called. It isn't looked up. It is compiled so
// that the instructions are just right there. This is used when the
// function has a small number of instructions.
inline hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n",
hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
// Copies the data between the device and the host. It also takes
// performance measurements.
// If the transfers are small, then it would be better in a real
// application to do them batched transfers. You can do this by
// using a temporary array, preferably pinned, and packing all
// of the data that needs to be transferred into it. Transfer
// it when ready.
// this method can be used: (there is also a 3D version)
// cudaMemcpy2D(dest, dest_pitch, src, src_pitch, w, h, cudaMemcpyHostToDevice)
void profileCopies(float* h_a, float* h_b, float* d, unsigned int n, char* desc) {
printf("\n%s transfers\n", desc);
unsigned int bytes = n * sizeof(float);
//events for timing
hipEvent_t startEvent, stopEvent;
checkCuda(hipEventCreate(&startEvent));
checkCuda(hipEventCreate(&stopEvent));
// record the time it takes for the host to copy the
// data over to the device.
// Note, it's better to do this kind of analysis with
// nvprof or Nsight rather than instrument the code.
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(d, h_a, bytes, hipMemcpyHostToDevice));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
// print result
float time;
checkCuda(hipEventElapsedTime(&time, startEvent, stopEvent));
printf(" Host to Deice bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
// Do the same thing from the device back to the host.
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(h_b, d, bytes, hipMemcpyDeviceToHost));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&time, startEvent, stopEvent));
printf(" Device to Host bandwidth (GB/s): %f\n", bytes * 1e-6 / time);
for (int i = 0; i < n; i++) {
if (h_a[i] != h_b[i]) {
printf("*** %s transfers failed *** \n", desc);
break;
}
}
// clean up events
checkCuda(hipEventDestroy(startEvent));
checkCuda(hipEventDestroy(stopEvent));
}
int main()
{
unsigned int nElements = 4 * 1024 * 1024;
const unsigned int bytes = nElements * sizeof(float);
//host arrays
float *h_aPageable, *h_bPageable;
float *h_aPinned, *h_bPinned;
// device array
float *d_a;
// allocate and initialize
h_aPageable = (float*)malloc(bytes); // host pageable
h_bPageable = (float*)malloc(bytes); // host pageable
checkCuda(hipHostMalloc((void**)&h_aPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipHostMalloc((void**)&h_bPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipMalloc((void**)&d_a, bytes)); // device
for (int i = 0; i < nElements; ++i) {
h_aPageable[i] = i;
}
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPageable, 0, bytes);
// output device info and transfer size
hipDeviceProp_t prop;
checkCuda(hipGetDeviceProperties(&prop, 0));
printf("\nDevice: %s\n", prop.name);
printf("Transfer size (MB): %d\n", bytes / (1024 * 1024));
// perform copies and report bandwidth
profileCopies(h_aPageable, h_bPageable, d_a, nElements, "Pageable");
profileCopies(h_aPinned, h_bPinned, d_a, nElements, "Pinned");
printf("\n");
// cleanup
hipFree(d_a);
hipHostFree(h_aPinned);
hipHostFree(h_bPinned);
free(h_aPageable);
free(h_bPageable);
// On my machine the pinned memory is over 3 times faster.
// This is all device dependent, however.
// Do not overuse Pinned Memory though. It limits the memory
// available to the operating system, etc. So, test to make
// sure the application is working suitably.
// Ultimately, take care to minimize the number of transfers
// and to optomize them when they must happen. This is the
// bottleneck of hybrid CPU/GPU computing.
return 0;
} | .text
.file "kernel.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13profileCopiesPfS_S_jPc
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z13profileCopiesPfS_S_jPc
.p2align 4, 0x90
.type _Z13profileCopiesPfS_S_jPc,@function
_Z13profileCopiesPfS_S_jPc: # @_Z13profileCopiesPfS_S_jPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movq %rdx, %r13
movq %rsi, %r14
movq %rdi, %r15
movl $.L.str, %edi
movq %r8, 24(%rsp) # 8-byte Spill
movq %r8, %rsi
xorl %eax, %eax
callq printf
leal (,%r12,4), %ebp
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 20(%rsp), %rbx
movq %rbx, %rdi
callq hipEventElapsedTime
cvtsi2sd %rbp, %xmm2
mulsd .LCPI0_0(%rip), %xmm2
movsd %xmm2, 32(%rsp) # 8-byte Spill
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
movapd %xmm2, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
testl %r12d, %r12d
je .LBB0_5
# %bb.1: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r15,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r14,%rcx,4), %xmm0
jne .LBB0_4
jp .LBB0_4
# %bb.2: # in Loop: Header=BB0_3 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB0_3
jmp .LBB0_5
.LBB0_4:
movl $.L.str.3, %edi
movq 24(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
callq printf
.LBB0_5: # %.loopexit
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13profileCopiesPfS_S_jPc, .Lfunc_end0-_Z13profileCopiesPfS_S_jPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1504, %rsp # imm = 0x5E0
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
xorl %r15d, %r15d
movl $16777216, %esi # imm = 0x1000000
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
xorl %edx, %edx
callq hipHostMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $4194304, %r15 # imm = 0x400000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
callq memcpy@PLT
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 32(%rsp), %r15
movq %r15, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.4, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl $16, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdx
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %r14, %rsi
movl $4194304, %ecx # imm = 0x400000
callq _Z13profileCopiesPfS_S_jPc
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movl $.L.str.7, %r8d
movl $4194304, %ecx # imm = 0x400000
callq _Z13profileCopiesPfS_S_jPc
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $1504, %rsp # imm = 0x5E0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n%s transfers\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Host to Deice bandwidth (GB/s): %f\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Device to Host bandwidth (GB/s): %f\n"
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "*** %s transfers failed *** \n"
.size .L.str.3, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nDevice: %s\n"
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Transfer size (MB): %d\n"
.size .L.str.5, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Pageable"
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Pinned"
.size .L.str.7, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019a053_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n%s transfers\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string " Host to Deice bandwidth (GB/s): %f\n"
.align 8
.LC3:
.string " Device to Host bandwidth (GB/s): %f\n"
.section .rodata.str1.1
.LC4:
.string "*** %s transfers failed *** \n"
.text
.globl _Z13profileCopiesPfS_S_jPc
.type _Z13profileCopiesPfS_S_jPc, @function
_Z13profileCopiesPfS_S_jPc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r14
movl %ecx, %r12d
movq %r8, %r15
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %r8, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leal 0(,%r12,4), %r13d
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %r13d, %r13d
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
movsd %xmm0, 8(%rsp)
divsd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
movsd 8(%rsp), %xmm0
divsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %r12d, %r12d
je .L6
movl %r12d, %r12d
salq $2, %r12
movl $0, %eax
.L9:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L11
jne .L11
addq $4, %rax
cmpq %r12, %rax
jne .L9
jmp .L6
.L11:
movq %r15, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z13profileCopiesPfS_S_jPc, .-_Z13profileCopiesPfS_S_jPc
.section .rodata.str1.1
.LC5:
.string "\nDevice: %s\n"
.LC6:
.string "Transfer size (MB): %d\n"
.LC7:
.string "Pageable"
.LC8:
.string "Pinned"
.LC9:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1072, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $0, %eax
.L16:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L16
movl $16777216, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call memcpy@PLT
movl $16777216, %edx
movl $0, %esi
movq %rbp, %rdi
call memset@PLT
leaq 32(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %r12, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %r8
movl $4194304, %ecx
movq 24(%rsp), %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z13profileCopiesPfS_S_jPc
leaq .LC8(%rip), %r8
movl $4194304, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z13profileCopiesPfS_S_jPc
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13profileCopiesPfS_S_jPc
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z13profileCopiesPfS_S_jPc
.p2align 4, 0x90
.type _Z13profileCopiesPfS_S_jPc,@function
_Z13profileCopiesPfS_S_jPc: # @_Z13profileCopiesPfS_S_jPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movq %rdx, %r13
movq %rsi, %r14
movq %rdi, %r15
movl $.L.str, %edi
movq %r8, 24(%rsp) # 8-byte Spill
movq %r8, %rsi
xorl %eax, %eax
callq printf
leal (,%r12,4), %ebp
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 20(%rsp), %rbx
movq %rbx, %rdi
callq hipEventElapsedTime
cvtsi2sd %rbp, %xmm2
mulsd .LCPI0_0(%rip), %xmm2
movsd %xmm2, 32(%rsp) # 8-byte Spill
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
movapd %xmm2, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
testl %r12d, %r12d
je .LBB0_5
# %bb.1: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r15,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r14,%rcx,4), %xmm0
jne .LBB0_4
jp .LBB0_4
# %bb.2: # in Loop: Header=BB0_3 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB0_3
jmp .LBB0_5
.LBB0_4:
movl $.L.str.3, %edi
movq 24(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
callq printf
.LBB0_5: # %.loopexit
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13profileCopiesPfS_S_jPc, .Lfunc_end0-_Z13profileCopiesPfS_S_jPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1504, %rsp # imm = 0x5E0
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
xorl %r15d, %r15d
movl $16777216, %esi # imm = 0x1000000
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
xorl %edx, %edx
callq hipHostMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $4194304, %r15 # imm = 0x400000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
callq memcpy@PLT
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 32(%rsp), %r15
movq %r15, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.4, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl $16, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdx
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %r14, %rsi
movl $4194304, %ecx # imm = 0x400000
callq _Z13profileCopiesPfS_S_jPc
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movl $.L.str.7, %r8d
movl $4194304, %ecx # imm = 0x400000
callq _Z13profileCopiesPfS_S_jPc
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $1504, %rsp # imm = 0x5E0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n%s transfers\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Host to Deice bandwidth (GB/s): %f\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Device to Host bandwidth (GB/s): %f\n"
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "*** %s transfers failed *** \n"
.size .L.str.3, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nDevice: %s\n"
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Transfer size (MB): %d\n"
.size .L.str.5, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Pageable"
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Pinned"
.size .L.str.7, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
__global__ void cuda_hello(){
printf("Hello World from GPU! %d\n", threadIdx.x*gridDim.x);
}
/*
Nvidia Jetson Nano Cuda info
CUDA Device Query (Runtime API) version (CUDART static linking)
Detected 1 CUDA Capable device(s)
Device 0: "NVIDIA Tegra X1"
CUDA Driver Version / Runtime Version 10.0 / 10.0
CUDA Capability Major/Minor version number: 5.3
Total amount of global memory: 3957 MBytes (4148756480 bytes)
( 1) Multiprocessors, (128) CUDA Cores/MP: 128 CUDA Cores
GPU Max Clock rate: 922 MHz (0.92 GHz)
Memory Clock rate: 13 Mhz
Memory Bus Width: 64-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 32768
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: Yes
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device supports Compute Preemption: No
Supports Cooperative Kernel Launch: No
Supports MultiDevice Co-op Kernel Launch: No
Device PCI Domain ID / Bus ID / location ID: 0 / 0 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 10.0, CUDA Runtime Version = 10.0, NumDevs = 1
Result = PASS
*/
int main() {
printf("Hello World from CPU!\n");
cuda_hello<<<500,1024>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*0060*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x001fca00078e02ff */
/*00a0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0001e40000100800 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
__global__ void cuda_hello(){
printf("Hello World from GPU! %d\n", threadIdx.x*gridDim.x);
}
/*
Nvidia Jetson Nano Cuda info
CUDA Device Query (Runtime API) version (CUDART static linking)
Detected 1 CUDA Capable device(s)
Device 0: "NVIDIA Tegra X1"
CUDA Driver Version / Runtime Version 10.0 / 10.0
CUDA Capability Major/Minor version number: 5.3
Total amount of global memory: 3957 MBytes (4148756480 bytes)
( 1) Multiprocessors, (128) CUDA Cores/MP: 128 CUDA Cores
GPU Max Clock rate: 922 MHz (0.92 GHz)
Memory Clock rate: 13 Mhz
Memory Bus Width: 64-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 32768
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: Yes
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device supports Compute Preemption: No
Supports Cooperative Kernel Launch: No
Supports MultiDevice Co-op Kernel Launch: No
Device PCI Domain ID / Bus ID / location ID: 0 / 0 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 10.0, CUDA Runtime Version = 10.0, NumDevs = 1
Result = PASS
*/
int main() {
printf("Hello World from CPU!\n");
cuda_hello<<<500,1024>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0005e38a_00000000-6_hello.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $500, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
__global__ void cuda_hello(){
printf("Hello World from GPU! %d\n", threadIdx.x*gridDim.x);
}
/*
Nvidia Jetson Nano Cuda info
CUDA Device Query (Runtime API) version (CUDART static linking)
Detected 1 CUDA Capable device(s)
Device 0: "NVIDIA Tegra X1"
CUDA Driver Version / Runtime Version 10.0 / 10.0
CUDA Capability Major/Minor version number: 5.3
Total amount of global memory: 3957 MBytes (4148756480 bytes)
( 1) Multiprocessors, (128) CUDA Cores/MP: 128 CUDA Cores
GPU Max Clock rate: 922 MHz (0.92 GHz)
Memory Clock rate: 13 Mhz
Memory Bus Width: 64-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 32768
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: Yes
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device supports Compute Preemption: No
Supports Cooperative Kernel Launch: No
Supports MultiDevice Co-op Kernel Launch: No
Device PCI Domain ID / Bus ID / location ID: 0 / 0 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 10.0, CUDA Runtime Version = 10.0, NumDevs = 1
Result = PASS
*/
int main() {
printf("Hello World from CPU!\n");
cuda_hello<<<500,1024>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <stdio.h>
__global__ void cuda_hello(){
printf("Hello World from GPU! %d\n", threadIdx.x*gridDim.x);
}
/*
Nvidia Jetson Nano Cuda info
CUDA Device Query (Runtime API) version (CUDART static linking)
Detected 1 CUDA Capable device(s)
Device 0: "NVIDIA Tegra X1"
CUDA Driver Version / Runtime Version 10.0 / 10.0
CUDA Capability Major/Minor version number: 5.3
Total amount of global memory: 3957 MBytes (4148756480 bytes)
( 1) Multiprocessors, (128) CUDA Cores/MP: 128 CUDA Cores
GPU Max Clock rate: 922 MHz (0.92 GHz)
Memory Clock rate: 13 Mhz
Memory Bus Width: 64-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 32768
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: Yes
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device supports Compute Preemption: No
Supports Cooperative Kernel Launch: No
Supports MultiDevice Co-op Kernel Launch: No
Device PCI Domain ID / Bus ID / location ID: 0 / 0 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 10.0, CUDA Runtime Version = 10.0, NumDevs = 1
Result = PASS
*/
int main() {
printf("Hello World from CPU!\n");
cuda_hello<<<500,1024>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <stdio.h>
__global__ void cuda_hello(){
printf("Hello World from GPU! %d\n", threadIdx.x*gridDim.x);
}
/*
Nvidia Jetson Nano Cuda info
CUDA Device Query (Runtime API) version (CUDART static linking)
Detected 1 CUDA Capable device(s)
Device 0: "NVIDIA Tegra X1"
CUDA Driver Version / Runtime Version 10.0 / 10.0
CUDA Capability Major/Minor version number: 5.3
Total amount of global memory: 3957 MBytes (4148756480 bytes)
( 1) Multiprocessors, (128) CUDA Cores/MP: 128 CUDA Cores
GPU Max Clock rate: 922 MHz (0.92 GHz)
Memory Clock rate: 13 Mhz
Memory Bus Width: 64-bit
L2 Cache Size: 262144 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
Maximum Layered 1D Texture Size, (num) layers 1D=(16384), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(16384, 16384), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 32768
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: Yes
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device supports Compute Preemption: No
Supports Cooperative Kernel Launch: No
Supports MultiDevice Co-op Kernel Launch: No
Device PCI Domain ID / Bus ID / location ID: 0 / 0 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 10.0, CUDA Runtime Version = 10.0, NumDevs = 1
Result = PASS
*/
int main() {
printf("Hello World from CPU!\n");
cuda_hello<<<500,1024>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967796, %rdi # imm = 0x1000001F4
leaq 524(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005e38a_00000000-6_hello.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $500, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967796, %rdi # imm = 0x1000001F4
leaq 524(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void updateGradInputVarScaleKernel( float *gradOutputIntData, float *gradInputData, int h, int w, int nWindows, float *xMin, float *xMax, float *yMin, float *yMax) {
const int x = BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = BLOCK_SIZE * blockIdx.y + threadIdx.y;
if (x < h and y < w) {
int xMinCurr, xMaxCurr, yMinCurr, yMaxCurr;
double outValue = 0;
for (int windowIdx = 0; windowIdx < nWindows; ++windowIdx) {
xMinCurr = (int)ceil(-xMax[windowIdx]);
yMinCurr = (int)ceil(-yMax[windowIdx]);
xMaxCurr = (int)floor(-xMin[windowIdx]) + 1;
yMaxCurr = (int)floor(-yMin[windowIdx]) + 1;
// The following code block implements these lines
// as if they were executed simultaneously (see `void updateGradInputFrac()`):
// xMinCurr = (x == 0 and xMaxCurr >= 0 ? 0 : xMinCurr);
// xMaxCurr = (x == h-1 and xMinCurr <= 0 ? h+66 : xMaxCurr);
// yMinCurr = (y == 0 and yMaxCurr >= 0 ? 0 : yMinCurr);
// yMaxCurr = (y == w-1 and yMinCurr <= 0 ? w+66 : yMaxCurr);
bool needToChangeMin, needToChangeMax;
needToChangeMin = x == 0 and xMaxCurr >= 0;
needToChangeMax = x == h-1 and xMinCurr <= 0;
if (needToChangeMin) xMinCurr = 0;
if (needToChangeMax) xMaxCurr = h+66;
needToChangeMin = y == 0 and yMaxCurr >= 0;
needToChangeMax = y == w-1 and yMinCurr <= 0;
if (needToChangeMin) yMinCurr = 0;
if (needToChangeMax) yMaxCurr = w+66;
const int t = max(0, min(x+xMinCurr, h) );
const int b = max(0, min(x+xMaxCurr, h) );
const int l = max(0, min(y+yMinCurr, w) );
const int r = max(0, min(y+yMaxCurr, w) );
outValue += gradOutputIntData[b*(w+1) + r];
outValue -= gradOutputIntData[t*(w+1) + r];
outValue -= gradOutputIntData[b*(w+1) + l];
outValue += gradOutputIntData[t*(w+1) + l];
// go to the next channel
gradOutputIntData += (h+1)*(w+1);
}
gradInputData[x*w + y] = outValue;
}
} | code for sm_80
Function : _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR16, c[0x0][0x160] ; /* 0x0000580000107ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, 0x4, R3 ; /* 0x0000000400007824 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R5, R5, 0x4, R2 ; /* 0x0000000405057824 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*00e0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xec0 ; /* 0x00000dc000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P0, PT, R4.reuse, 0x1, PT ; /* 0x000000010400780c */
/* 0x040fe20003f05270 */
/*0110*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ LOP3.LUT R4, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104047812 */
/* 0x000fe200078ec0ff */
/*0130*/ UIADD3 UR9, UR5, -0x1, URZ ; /* 0xffffffff05097890 */
/* 0x000fe2000fffe03f */
/*0140*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0150*/ UIADD3 UR10, UR5, 0x42, URZ ; /* 0x00000042050a7890 */
/* 0x000fe2000fffe03f */
/*0160*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0170*/ UIADD3 UR7, UR4, -0x1, URZ ; /* 0xffffffff04077890 */
/* 0x000fe4000fffe03f */
/*0180*/ UIADD3 UR8, UR4, 0x42, URZ ; /* 0x0000004204087890 */
/* 0x000fe4000fffe03f */
/*0190*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fc4000fffe03f */
/*01a0*/ @!P0 BRA 0xa70 ; /* 0x000008c000008947 */
/* 0x000fea0003800000 */
/*01b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*01c0*/ ISETP.NE.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720c */
/* 0x040fe20003f05270 */
/*01d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*01e0*/ ISETP.NE.AND P1, PT, R5, UR7, PT ; /* 0x0000000705007c0c */
/* 0x000fe2000bf25270 */
/*01f0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0200*/ ISETP.NE.AND P2, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f45270 */
/*0210*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0220*/ ISETP.NE.AND P3, PT, R0, UR9, PT ; /* 0x0000000900007c0c */
/* 0x000fe2000bf65270 */
/*0230*/ USHF.R.S32.HI UR11, URZ, 0x1f, UR4 ; /* 0x0000001f3f0b7899 */
/* 0x000fe20008011404 */
/*0240*/ IADD3 R7, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004077a10 */
/* 0x000fe20007ffe1ff */
/*0250*/ USHF.L.U32 UR14, UR4, 0x1, URZ ; /* 0x00000001040e7899 */
/* 0x000fc4000800063f */
/*0260*/ USHF.L.U64.HI UR6, UR4, 0x1, UR11 ; /* 0x0000000104067899 */
/* 0x000fc8000801020b */
/*0270*/ USHF.L.U64.HI UR6, UR14, 0x2, UR6 ; /* 0x000000020e067899 */
/* 0x000fe40008010206 */
/*0280*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.WIDE R12, R6, R15, c[0x0][0x180] ; /* 0x00006000060c7625 */
/* 0x000fc800078e020f */
/*02a0*/ IMAD.WIDE R10, R6.reuse, R15.reuse, c[0x0][0x188] ; /* 0x00006200060a7625 */
/* 0x0c0fe200078e020f */
/*02b0*/ LDG.E R19, [R12.64] ; /* 0x0000000c0c137981 */
/* 0x001ea6000c1e1900 */
/*02c0*/ IMAD.WIDE R16, R6.reuse, R15.reuse, c[0x0][0x198] ; /* 0x0000660006107625 */
/* 0x0c0fe200078e020f */
/*02d0*/ LDG.E R9, [R10.64] ; /* 0x0000000c0a097981 */
/* 0x0000e6000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R6, R15, c[0x0][0x190] ; /* 0x00006400060e7625 */
/* 0x000fe200078e020f */
/*02f0*/ LDG.E R18, [R16.64] ; /* 0x0000000c10127981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R20, [R14.64] ; /* 0x0000000c0e147981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R8, [R10.64+0x4] ; /* 0x0000040c0a087981 */
/* 0x000128000c1e1900 */
/*0320*/ LDG.E R22, [R12.64+0x4] ; /* 0x0000040c0c167981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R21, [R16.64+0x4] ; /* 0x0000040c10157981 */
/* 0x002328000c1e1900 */
/*0340*/ LDG.E R24, [R14.64+0x4] ; /* 0x0000040c0e187981 */
/* 0x000322000c1e1900 */
/*0350*/ IMAD.U32 R10, RZ, RZ, UR16 ; /* 0x00000010ff0a7e24 */
/* 0x001fc4000f8e00ff */
/*0360*/ IMAD.U32 R11, RZ, RZ, UR17 ; /* 0x00000011ff0b7e24 */
/* 0x000fe2000f8e00ff */
/*0370*/ F2I.FLOOR.NTZ R19, -R19 ; /* 0x8000001300137305 */
/* 0x004e300000207100 */
/*0380*/ F2I.CEIL.NTZ R9, -R9 ; /* 0x8000000900097305 */
/* 0x008eb0000020b100 */
/*0390*/ F2I.FLOOR.NTZ R20, -R20 ; /* 0x8000001400147305 */
/* 0x020ef00000207100 */
/*03a0*/ F2I.CEIL.NTZ R18, -R18 ; /* 0x8000001200127305 */
/* 0x010f22000020b100 */
/*03b0*/ ISETP.GT.AND P5, PT, R19, -0x2, !P0 ; /* 0xfffffffe1300780c */
/* 0x001fc400047a4270 */
/*03c0*/ ISETP.LT.AND P6, PT, R9, 0x1, !P1 ; /* 0x000000010900780c */
/* 0x004fe40004fc1270 */
/*03d0*/ IADD3 R14, R19, 0x1, RZ ; /* 0x00000001130e7810 */
/* 0x002fc60007ffe0ff */
/*03e0*/ F2I.CEIL.NTZ R8, -R8 ; /* 0x8000000800087305 */
/* 0x000e22000020b100 */
/*03f0*/ SEL R16, R9, RZ, !P5 ; /* 0x000000ff09107207 */
/* 0x000fe40006800000 */
/*0400*/ ISETP.GT.AND P5, PT, R20, -0x2, !P2 ; /* 0xfffffffe1400780c */
/* 0x008fca00057a4270 */
/*0410*/ F2I.FLOOR.NTZ R23, -R22 ; /* 0x8000001600177305 */
/* 0x0002a20000207100 */
/*0420*/ IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fce0007ffe0ff */
/*0430*/ F2I.CEIL.NTZ R12, -R21 ; /* 0x80000015000c7305 */
/* 0x000ee2000020b100 */
/*0440*/ SEL R22, R14, UR8, !P6 ; /* 0x000000080e167c07 */
/* 0x002fe4000f000000 */
/*0450*/ ISETP.LT.AND P6, PT, R18, 0x1, !P3 ; /* 0x000000011200780c */
/* 0x010fca0005fc1270 */
/*0460*/ F2I.FLOOR.NTZ R13, -R24 ; /* 0x80000018000d7305 */
/* 0x000e620000207100 */
/*0470*/ SEL R17, R20, UR10, !P6 ; /* 0x0000000a14117c07 */
/* 0x000fe2000f000000 */
/*0480*/ IMAD.IADD R22, R5, 0x1, R22 ; /* 0x0000000105167824 */
/* 0x000fe200078e0216 */
/*0490*/ SEL R15, R18, RZ, !P5 ; /* 0x000000ff120f7207 */
/* 0x000fc60006800000 */
/*04a0*/ IMAD.IADD R17, R0, 0x1, R17 ; /* 0x0000000100117824 */
/* 0x000fe200078e0211 */
/*04b0*/ ISETP.LT.AND P4, PT, R8, 0x1, !P1 ; /* 0x000000010800780c */
/* 0x001fe40004f81270 */
/*04c0*/ IADD3 R9, R23, 0x1, RZ ; /* 0x0000000117097810 */
/* 0x004fe40007ffe0ff */
/*04d0*/ ISETP.LT.AND P6, PT, R12, 0x1, !P3 ; /* 0x000000010c00780c */
/* 0x008fe20005fc1270 */
/*04e0*/ IMAD.IADD R16, R5, 0x1, R16 ; /* 0x0000000105107824 */
/* 0x000fe200078e0210 */
/*04f0*/ ISETP.GT.AND P5, PT, R23, -0x2, !P0 ; /* 0xfffffffe1700780c */
/* 0x000fe400047a4270 */
/*0500*/ IADD3 R14, R13, 0x1, RZ ; /* 0x000000010d0e7810 */
/* 0x002fe20007ffe0ff */
/*0510*/ IMAD.IADD R15, R0, 0x1, R15 ; /* 0x00000001000f7824 */
/* 0x000fe200078e020f */
/*0520*/ IMNMX R22, R22, c[0x0][0x170], PT ; /* 0x00005c0016167a17 */
/* 0x000fc40003800200 */
/*0530*/ IMNMX R17, R17, c[0x0][0x174], PT ; /* 0x00005d0011117a17 */
/* 0x000fe40003800200 */
/*0540*/ SEL R18, R9, UR8, !P4 ; /* 0x0000000809127c07 */
/* 0x000fe4000e000000 */
/*0550*/ SEL R23, R14, UR10, !P6 ; /* 0x0000000a0e177c07 */
/* 0x000fe4000f000000 */
/*0560*/ IMNMX R16, R16, c[0x0][0x170], PT ; /* 0x00005c0010107a17 */
/* 0x000fe40003800200 */
/*0570*/ IMNMX R22, RZ, R22, !PT ; /* 0x00000016ff167217 */
/* 0x000fe40007800200 */
/*0580*/ IMNMX R17, RZ, R17, !PT ; /* 0x00000011ff117217 */
/* 0x000fe20007800200 */
/*0590*/ IMAD.IADD R18, R5, 0x1, R18 ; /* 0x0000000105127824 */
/* 0x000fe200078e0212 */
/*05a0*/ IMNMX R15, R15, c[0x0][0x174], PT ; /* 0x00005d000f0f7a17 */
/* 0x000fe20003800200 */
/*05b0*/ IMAD.IADD R23, R0, 0x1, R23 ; /* 0x0000000100177824 */
/* 0x000fe200078e0217 */
/*05c0*/ IMNMX R16, RZ, R16, !PT ; /* 0x00000010ff107217 */
/* 0x000fe20007800200 */
/*05d0*/ IMAD R21, R22, UR5, R17 ; /* 0x0000000516157c24 */
/* 0x000fe2000f8e0211 */
/*05e0*/ ISETP.GT.AND P4, PT, R13, -0x2, !P2 ; /* 0xfffffffe0d00780c */
/* 0x000fc40005784270 */
/*05f0*/ SEL R8, R8, RZ, !P5 ; /* 0x000000ff08087207 */
/* 0x000fe40006800000 */
/*0600*/ IMNMX R19, RZ, R15, !PT ; /* 0x0000000fff137217 */
/* 0x000fe40007800200 */
/*0610*/ IMNMX R18, R18, c[0x0][0x170], PT ; /* 0x00005c0012127a17 */
/* 0x000fe40003800200 */
/*0620*/ IMNMX R13, R23, c[0x0][0x174], PT ; /* 0x00005d00170d7a17 */
/* 0x000fe20003800200 */
/*0630*/ IMAD R15, R16, UR5, R17 ; /* 0x00000005100f7c24 */
/* 0x000fe2000f8e0211 */
/*0640*/ SEL R23, R12, RZ, !P4 ; /* 0x000000ff0c177207 */
/* 0x000fe20006000000 */
/*0650*/ IMAD.WIDE R20, R21, 0x4, R10 ; /* 0x0000000415147825 */
/* 0x000fc800078e020a */
/*0660*/ IMAD.IADD R12, R5, 0x1, R8 ; /* 0x00000001050c7824 */
/* 0x000fe200078e0208 */
/*0670*/ IMNMX R8, RZ, R13, !PT ; /* 0x0000000dff087217 */
/* 0x000fe20007800200 */
/*0680*/ IMAD R17, R22, UR5, R19.reuse ; /* 0x0000000516117c24 */
/* 0x100fe2000f8e0213 */
/*0690*/ LDG.E R13, [R20.64] ; /* 0x0000000c140d7981 */
/* 0x0000a2000c1e1900 */
/*06a0*/ IMAD R9, R16, UR5, R19 ; /* 0x0000000510097c24 */
/* 0x000fe2000f8e0213 */
/*06b0*/ IMNMX R19, RZ, R18, !PT ; /* 0x00000012ff137217 */
/* 0x000fe20007800200 */
/*06c0*/ IMAD.WIDE R14, R15, 0x4, R10 ; /* 0x000000040f0e7825 */
/* 0x000fe200078e020a */
/*06d0*/ IMNMX R12, R12, c[0x0][0x170], PT ; /* 0x00005c000c0c7a17 */
/* 0x000fc60003800200 */
/*06e0*/ IMAD.IADD R23, R0, 0x1, R23 ; /* 0x0000000100177824 */
/* 0x000fe400078e0217 */
/*06f0*/ IMAD R22, R19, UR5, R8 ; /* 0x0000000513167c24 */
/* 0x000fe2000f8e0208 */
/*0700*/ IMNMX R18, RZ, R12, !PT ; /* 0x0000000cff127217 */
/* 0x000fe20007800200 */
/*0710*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x0002e2000c1e1900 */
/*0720*/ IMNMX R23, R23, c[0x0][0x174], PT ; /* 0x00005d0017177a17 */
/* 0x000fe20003800200 */
/*0730*/ IMAD.WIDE R16, R17, 0x4, R10 ; /* 0x0000000411107825 */
/* 0x000fe200078e020a */
/*0740*/ IADD3 R24, P4, R22, UR4, RZ ; /* 0x0000000416187c10 */
/* 0x000fc6000ff9e0ff */
/*0750*/ IMAD R25, R18, UR5, R8 ; /* 0x0000000512197c24 */
/* 0x000fe2000f8e0208 */
/*0760*/ IMNMX R20, RZ, R23, !PT ; /* 0x00000017ff147217 */
/* 0x001fe20007800200 */
/*0770*/ LDG.E R12, [R16.64] ; /* 0x0000000c100c7981 */
/* 0x000122000c1e1900 */
/*0780*/ LEA.HI.X.SX32 R27, R22, UR11, 0x1, P4 ; /* 0x0000000b161b7c11 */
/* 0x000fe2000a0f0eff */
/*0790*/ IMAD.WIDE R22, R9, 0x4, R10 ; /* 0x0000000409167825 */
/* 0x000fe200078e020a */
/*07a0*/ LEA R8, P4, R24.reuse, UR16, 0x2 ; /* 0x0000001018087c11 */
/* 0x040fe4000f8810ff */
/*07b0*/ IADD3 R21, P5, R25, UR4, RZ ; /* 0x0000000419157c10 */
/* 0x000fe2000ffbe0ff */
/*07c0*/ IMAD R19, R19, UR5, R20 ; /* 0x0000000513137c24 */
/* 0x000fe2000f8e0214 */
/*07d0*/ LEA.HI.X R9, R24, UR17, R27, 0x2, P4 ; /* 0x0000001118097c11 */
/* 0x000fe2000a0f141b */
/*07e0*/ LDG.E R22, [R22.64] ; /* 0x0000000c16167981 */
/* 0x000f62000c1e1900 */
/*07f0*/ LEA.HI.X.SX32 R24, R25, UR11, 0x1, P5 ; /* 0x0000000b19187c11 */
/* 0x000fc4000a8f0eff */
/*0800*/ LEA R10, P4, R21, UR16, 0x2 ; /* 0x00000010150a7c11 */
/* 0x000fe2000f8810ff */
/*0810*/ IMAD R18, R18, UR5, R20 ; /* 0x0000000512127c24 */
/* 0x000fe2000f8e0214 */
/*0820*/ IADD3 R25, P5, R19, UR4, RZ ; /* 0x0000000413197c10 */
/* 0x000fe4000ffbe0ff */
/*0830*/ LEA.HI.X R11, R21, UR17, R24, 0x2, P4 ; /* 0x00000011150b7c11 */
/* 0x000fe4000a0f1418 */
/*0840*/ LDG.E R24, [R8.64] ; /* 0x0000000c08187981 */
/* 0x000962000c1e1900 */
/*0850*/ LEA.HI.X.SX32 R20, R19, UR11, 0x1, P5 ; /* 0x0000000b13147c11 */
/* 0x000fe4000a8f0eff */
/*0860*/ LEA R16, P4, R25, UR16, 0x2 ; /* 0x0000001019107c11 */
/* 0x001fe2000f8810ff */
/*0870*/ LDG.E R10, [R10.64] ; /* 0x0000000c0a0a7981 */
/* 0x000f62000c1e1900 */
/*0880*/ IADD3 R15, P5, R18, UR4, RZ ; /* 0x00000004120f7c10 */
/* 0x002fc4000ffbe0ff */
/*0890*/ LEA.HI.X R17, R25, UR17, R20, 0x2, P4 ; /* 0x0000001119117c11 */
/* 0x000fe4000a0f1414 */
/*08a0*/ LEA.HI.X.SX32 R20, R18, UR11, 0x1, P5 ; /* 0x0000000b12147c11 */
/* 0x000fe4000a8f0eff */
/*08b0*/ LEA R18, P4, R15.reuse, UR16, 0x2 ; /* 0x000000100f127c11 */
/* 0x040fe2000f8810ff */
/*08c0*/ LDG.E R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000f66000c1e1900 */
/*08d0*/ LEA.HI.X R19, R15, UR17, R20, 0x2, P4 ; /* 0x000000110f137c11 */
/* 0x000fca000a0f1414 */
/*08e0*/ LDG.E R18, [R18.64] ; /* 0x0000000c12127981 */
/* 0x000f62000c1e1900 */
/*08f0*/ IADD3 R7, R7, -0x2, RZ ; /* 0xfffffffe07077810 */
/* 0x000fc80007ffe0ff */
/*0900*/ ISETP.NE.AND P4, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f85270 */
/*0910*/ ULEA UR16, UP0, UR14, UR16, 0x2 ; /* 0x000000100e107291 */
/* 0x000fe2000f80103f */
/*0920*/ IADD3 R6, R6, 0x2, RZ ; /* 0x0000000206067810 */
/* 0x000fc60007ffe0ff */
/*0930*/ UIADD3.X UR17, UR17, UR6, URZ, UP0, !UPT ; /* 0x0000000611117290 */
/* 0x000fe200087fe43f */
/*0940*/ F2F.F64.F32 R20, R13 ; /* 0x0000000d00147310 */
/* 0x004e300000201800 */
/*0950*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x008e700000201800 */
/*0960*/ F2F.F64.F32 R8, R12 ; /* 0x0000000c00087310 */
/* 0x010ea20000201800 */
/*0970*/ DADD R20, R20, R2 ; /* 0x0000000014147229 */
/* 0x001e4e0000000002 */
/*0980*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x020e220000201800 */
/*0990*/ DADD R20, R20, -R14 ; /* 0x0000000014147229 */
/* 0x002e8e000000080e */
/*09a0*/ F2F.F64.F32 R24, R24 ; /* 0x0000001800187310 */
/* 0x000e620000201800 */
/*09b0*/ DADD R8, R20, -R8 ; /* 0x0000000014087229 */
/* 0x004e0e0000000808 */
/*09c0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x000ea20000201800 */
/*09d0*/ DADD R8, R8, R22 ; /* 0x0000000008087229 */
/* 0x001e4e0000000016 */
/*09e0*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x000e220000201800 */
/*09f0*/ DADD R8, R8, R24 ; /* 0x0000000008087229 */
/* 0x002e8e0000000018 */
/*0a00*/ F2F.F64.F32 R18, R18 ; /* 0x0000001200127310 */
/* 0x000e620000201800 */
/*0a10*/ DADD R8, R8, -R10 ; /* 0x0000000008087229 */
/* 0x004e0c000000080a */
/*0a20*/ DADD R8, R8, -R16 ; /* 0x0000000008087229 */
/* 0x001e4c0000000810 */
/*0a30*/ DADD R2, R8, R18 ; /* 0x0000000008027229 */
/* 0x0020620000000012 */
/*0a40*/ @P4 BRA 0x280 ; /* 0xfffff83000004947 */
/* 0x000fea000383ffff */
/*0a50*/ SHF.R.S32.HI R9, RZ, 0x1f, R6.reuse ; /* 0x0000001fff097819 */
/* 0x101fe20000011406 */
/*0a60*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0006 */
/*0a70*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0a80*/ IMAD.U32 R6, RZ, RZ, UR16 ; /* 0x00000010ff067e24 */
/* 0x000fe4000f8e00ff */
/*0a90*/ IMAD.U32 R7, RZ, RZ, UR17 ; /* 0x00000011ff077e24 */
/* 0x000fd4000f8e00ff */
/*0aa0*/ @!P0 BRA 0xeb0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ IMAD.SHL.U32 R14, R8.reuse, 0x4, RZ ; /* 0x00000004080e7824 */
/* 0x040fe200078e00ff */
/*0ac0*/ SHF.L.U64.HI R4, R8, 0x2, R9 ; /* 0x0000000208047819 */
/* 0x000fc80000010209 */
/*0ad0*/ IADD3 R8, P0, R14.reuse, c[0x0][0x188], RZ ; /* 0x000062000e087a10 */
/* 0x040fe40007f1e0ff */
/*0ae0*/ IADD3 R10, P1, R14.reuse, c[0x0][0x198], RZ ; /* 0x000066000e0a7a10 */
/* 0x040fe40007f3e0ff */
/*0af0*/ IADD3 R12, P2, R14, c[0x0][0x180], RZ ; /* 0x000060000e0c7a10 */
/* 0x000fe40007f5e0ff */
/*0b00*/ IADD3.X R9, R4, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630004097a10 */
/* 0x000fe400007fe4ff */
/*0b10*/ IADD3 R14, P0, R14, c[0x0][0x190], RZ ; /* 0x000064000e0e7a10 */
/* 0x000fe40007f1e0ff */
/*0b20*/ IADD3.X R11, R4.reuse, c[0x0][0x19c], RZ, P1, !PT ; /* 0x00006700040b7a10 */
/* 0x040fe20000ffe4ff */
/*0b30*/ LDG.E R8, [R8.64] ; /* 0x0000000c08087981 */
/* 0x000ea2000c1e1900 */
/*0b40*/ IADD3.X R13, R4, c[0x0][0x184], RZ, P2, !PT ; /* 0x00006100040d7a10 */
/* 0x000fc400017fe4ff */
/*0b50*/ IADD3.X R15, R4, c[0x0][0x194], RZ, P0, !PT ; /* 0x00006500040f7a10 */
/* 0x000fe200007fe4ff */
/*0b60*/ LDG.E R10, [R10.64] ; /* 0x0000000c0a0a7981 */
/* 0x000ee8000c1e1900 */
/*0b70*/ LDG.E R12, [R12.64] ; /* 0x0000000c0c0c7981 */
/* 0x000f28000c1e1900 */
/*0b80*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000f62000c1e1900 */
/*0b90*/ F2I.CEIL.NTZ R4, -R8 ; /* 0x8000000800047305 */
/* 0x004e30000020b100 */
/*0ba0*/ F2I.CEIL.NTZ R16, -R10 ; /* 0x8000000a00107305 */
/* 0x008eb0000020b100 */
/*0bb0*/ F2I.FLOOR.NTZ R17, -R12 ; /* 0x8000000c00117305 */
/* 0x010ef00000207100 */
/*0bc0*/ F2I.FLOOR.NTZ R18, -R14 ; /* 0x8000000e00127305 */
/* 0x020f220000207100 */
/*0bd0*/ ISETP.GE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x001fc40003f26270 */
/*0be0*/ ISETP.GE.AND P2, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x004fe40003f46270 */
/*0bf0*/ ISETP.EQ.AND P1, PT, R5, UR7, !P1 ; /* 0x0000000705007c0c */
/* 0x000fe4000cf22270 */
/*0c00*/ ISETP.EQ.AND P2, PT, R0, UR9, !P2 ; /* 0x0000000900007c0c */
/* 0x000fe4000d742270 */
/*0c10*/ IADD3 R9, R17.reuse, 0x1, RZ ; /* 0x0000000111097810 */
/* 0x048fe40007ffe0ff */
/*0c20*/ ISETP.GT.AND P0, PT, R17, -0x2, PT ; /* 0xfffffffe1100780c */
/* 0x000fe40003f04270 */
/*0c30*/ IADD3 R19, R18, 0x1, RZ ; /* 0x0000000112137810 */
/* 0x010fc40007ffe0ff */
/*0c40*/ SEL R8, R9, UR8, !P1 ; /* 0x0000000809087c07 */
/* 0x000fe4000c800000 */
/*0c50*/ SEL R19, R19, UR10, !P2 ; /* 0x0000000a13137c07 */
/* 0x000fe4000d000000 */
/*0c60*/ ISETP.EQ.AND P0, PT, R5.reuse, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x040fe40000702270 */
/*0c70*/ ISETP.GT.AND P1, PT, R18, -0x2, PT ; /* 0xfffffffe1200780c */
/* 0x000fe20003f24270 */
/*0c80*/ IMAD.IADD R8, R5, 0x1, R8 ; /* 0x0000000105087824 */
/* 0x000fe200078e0208 */
/*0c90*/ SEL R4, R4, RZ, !P0 ; /* 0x000000ff04047207 */
/* 0x000fe20004000000 */
/*0ca0*/ IMAD.IADD R19, R0.reuse, 0x1, R19 ; /* 0x0000000100137824 */
/* 0x040fe200078e0213 */
/*0cb0*/ ISETP.EQ.AND P1, PT, R0, RZ, P1 ; /* 0x000000ff0000720c */
/* 0x000fc40000f22270 */
/*0cc0*/ IMNMX R8, R8, c[0x0][0x170], PT ; /* 0x00005c0008087a17 */
/* 0x000fe20003800200 */
/*0cd0*/ IMAD.IADD R4, R5, 0x1, R4 ; /* 0x0000000105047824 */
/* 0x000fe200078e0204 */
/*0ce0*/ IMNMX R19, R19, c[0x0][0x174], PT ; /* 0x00005d0013137a17 */
/* 0x000fe40003800200 */
/*0cf0*/ SEL R9, R16, RZ, !P1 ; /* 0x000000ff10097207 */
/* 0x000fe40004800000 */
/*0d00*/ IMNMX R12, RZ, R8, !PT ; /* 0x00000008ff0c7217 */
/* 0x000fe40007800200 */
/*0d10*/ IMNMX R19, RZ, R19, !PT ; /* 0x00000013ff137217 */
/* 0x000fe20007800200 */
/*0d20*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x000fe200078e0209 */
/*0d30*/ IMNMX R4, R4, c[0x0][0x170], PT ; /* 0x00005c0004047a17 */
/* 0x000fc60003800200 */
/*0d40*/ IMAD R11, R12, UR5, R19 ; /* 0x000000050c0b7c24 */
/* 0x000fe2000f8e0213 */
/*0d50*/ IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff047217 */
/* 0x000fe40007800200 */
/*0d60*/ IMNMX R10, R9, c[0x0][0x174], PT ; /* 0x00005d00090a7a17 */
/* 0x000fe20003800200 */
/*0d70*/ IMAD.WIDE R8, R11, 0x4, R6 ; /* 0x000000040b087825 */
/* 0x000fc600078e0206 */
/*0d80*/ IMNMX R13, RZ, R10, !PT ; /* 0x0000000aff0d7217 */
/* 0x000fe20007800200 */
/*0d90*/ IMAD R11, R4, UR5, R19 ; /* 0x00000005040b7c24 */
/* 0x000fe2000f8e0213 */
/*0da0*/ LDG.E R18, [R8.64] ; /* 0x0000000c08127981 */
/* 0x000ea6000c1e1900 */
/*0db0*/ IMAD.WIDE R10, R11, 0x4, R6 ; /* 0x000000040b0a7825 */
/* 0x000fc800078e0206 */
/*0dc0*/ IMAD R15, R12, UR5, R13 ; /* 0x000000050c0f7c24 */
/* 0x000fe4000f8e020d */
/*0dd0*/ LDG.E R10, [R10.64] ; /* 0x0000000c0a0a7981 */
/* 0x000ee4000c1e1900 */
/*0de0*/ IMAD.WIDE R14, R15, 0x4, R6 ; /* 0x000000040f0e7825 */
/* 0x000fc800078e0206 */
/*0df0*/ IMAD R17, R4, UR5, R13 ; /* 0x0000000504117c24 */
/* 0x000fe4000f8e020d */
/*0e00*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000f24000c1e1900 */
/*0e10*/ IMAD.WIDE R16, R17, 0x4, R6 ; /* 0x0000000411107825 */
/* 0x000fcc00078e0206 */
/*0e20*/ LDG.E R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000f62000c1e1900 */
/*0e30*/ F2F.F64.F32 R6, R18 ; /* 0x0000001200067310 */
/* 0x004e300000201800 */
/*0e40*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */
/* 0x008eb00000201800 */
/*0e50*/ F2F.F64.F32 R8, R14 ; /* 0x0000000e00087310 */
/* 0x010ee20000201800 */
/*0e60*/ DADD R6, R2, R6 ; /* 0x0000000002067229 */
/* 0x003a8e0000000006 */
/*0e70*/ F2F.F64.F32 R2, R16 ; /* 0x0000001000027310 */
/* 0x020e220000201800 */
/*0e80*/ DADD R6, R6, -R12 ; /* 0x0000000006067229 */
/* 0x004ecc000000080c */
/*0e90*/ DADD R6, R6, -R8 ; /* 0x0000000006067229 */
/* 0x008e0c0000000808 */
/*0ea0*/ DADD R2, R6, R2 ; /* 0x0000000006027229 */
/* 0x0010520000000002 */
/*0eb0*/ F2F.F32.F64 R7, R2 ; /* 0x0000000200077310 */
/* 0x0030640000301000 */
/*0ec0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe400078e00ff */
/*0ed0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fc800078e0200 */
/*0ee0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0ef0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x002fe2000c10190c */
/*0f00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f10*/ BRA 0xf10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void updateGradInputVarScaleKernel( float *gradOutputIntData, float *gradInputData, int h, int w, int nWindows, float *xMin, float *xMax, float *yMin, float *yMax) {
const int x = BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = BLOCK_SIZE * blockIdx.y + threadIdx.y;
if (x < h and y < w) {
int xMinCurr, xMaxCurr, yMinCurr, yMaxCurr;
double outValue = 0;
for (int windowIdx = 0; windowIdx < nWindows; ++windowIdx) {
xMinCurr = (int)ceil(-xMax[windowIdx]);
yMinCurr = (int)ceil(-yMax[windowIdx]);
xMaxCurr = (int)floor(-xMin[windowIdx]) + 1;
yMaxCurr = (int)floor(-yMin[windowIdx]) + 1;
// The following code block implements these lines
// as if they were executed simultaneously (see `void updateGradInputFrac()`):
// xMinCurr = (x == 0 and xMaxCurr >= 0 ? 0 : xMinCurr);
// xMaxCurr = (x == h-1 and xMinCurr <= 0 ? h+66 : xMaxCurr);
// yMinCurr = (y == 0 and yMaxCurr >= 0 ? 0 : yMinCurr);
// yMaxCurr = (y == w-1 and yMinCurr <= 0 ? w+66 : yMaxCurr);
bool needToChangeMin, needToChangeMax;
needToChangeMin = x == 0 and xMaxCurr >= 0;
needToChangeMax = x == h-1 and xMinCurr <= 0;
if (needToChangeMin) xMinCurr = 0;
if (needToChangeMax) xMaxCurr = h+66;
needToChangeMin = y == 0 and yMaxCurr >= 0;
needToChangeMax = y == w-1 and yMinCurr <= 0;
if (needToChangeMin) yMinCurr = 0;
if (needToChangeMax) yMaxCurr = w+66;
const int t = max(0, min(x+xMinCurr, h) );
const int b = max(0, min(x+xMaxCurr, h) );
const int l = max(0, min(y+yMinCurr, w) );
const int r = max(0, min(y+yMaxCurr, w) );
outValue += gradOutputIntData[b*(w+1) + r];
outValue -= gradOutputIntData[t*(w+1) + r];
outValue -= gradOutputIntData[b*(w+1) + l];
outValue += gradOutputIntData[t*(w+1) + l];
// go to the next channel
gradOutputIntData += (h+1)*(w+1);
}
gradInputData[x*w + y] = outValue;
}
} | .file "tmpxft_000ead7c_00000000-6_updateGradInputVarScaleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_
.type _Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_, @function
_Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_, .-_Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_
.globl _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.type _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, @function
_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, .-_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void updateGradInputVarScaleKernel( float *gradOutputIntData, float *gradInputData, int h, int w, int nWindows, float *xMin, float *xMax, float *yMin, float *yMax) {
const int x = BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = BLOCK_SIZE * blockIdx.y + threadIdx.y;
if (x < h and y < w) {
int xMinCurr, xMaxCurr, yMinCurr, yMaxCurr;
double outValue = 0;
for (int windowIdx = 0; windowIdx < nWindows; ++windowIdx) {
xMinCurr = (int)ceil(-xMax[windowIdx]);
yMinCurr = (int)ceil(-yMax[windowIdx]);
xMaxCurr = (int)floor(-xMin[windowIdx]) + 1;
yMaxCurr = (int)floor(-yMin[windowIdx]) + 1;
// The following code block implements these lines
// as if they were executed simultaneously (see `void updateGradInputFrac()`):
// xMinCurr = (x == 0 and xMaxCurr >= 0 ? 0 : xMinCurr);
// xMaxCurr = (x == h-1 and xMinCurr <= 0 ? h+66 : xMaxCurr);
// yMinCurr = (y == 0 and yMaxCurr >= 0 ? 0 : yMinCurr);
// yMaxCurr = (y == w-1 and yMinCurr <= 0 ? w+66 : yMaxCurr);
bool needToChangeMin, needToChangeMax;
needToChangeMin = x == 0 and xMaxCurr >= 0;
needToChangeMax = x == h-1 and xMinCurr <= 0;
if (needToChangeMin) xMinCurr = 0;
if (needToChangeMax) xMaxCurr = h+66;
needToChangeMin = y == 0 and yMaxCurr >= 0;
needToChangeMax = y == w-1 and yMinCurr <= 0;
if (needToChangeMin) yMinCurr = 0;
if (needToChangeMax) yMaxCurr = w+66;
const int t = max(0, min(x+xMinCurr, h) );
const int b = max(0, min(x+xMaxCurr, h) );
const int l = max(0, min(y+yMinCurr, w) );
const int r = max(0, min(y+yMaxCurr, w) );
outValue += gradOutputIntData[b*(w+1) + r];
outValue -= gradOutputIntData[t*(w+1) + r];
outValue -= gradOutputIntData[b*(w+1) + l];
outValue += gradOutputIntData[t*(w+1) + l];
// go to the next channel
gradOutputIntData += (h+1)*(w+1);
}
gradInputData[x*w + y] = outValue;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void updateGradInputVarScaleKernel( float *gradOutputIntData, float *gradInputData, int h, int w, int nWindows, float *xMin, float *xMax, float *yMin, float *yMax) {
const int x = BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = BLOCK_SIZE * blockIdx.y + threadIdx.y;
if (x < h and y < w) {
int xMinCurr, xMaxCurr, yMinCurr, yMaxCurr;
double outValue = 0;
for (int windowIdx = 0; windowIdx < nWindows; ++windowIdx) {
xMinCurr = (int)ceil(-xMax[windowIdx]);
yMinCurr = (int)ceil(-yMax[windowIdx]);
xMaxCurr = (int)floor(-xMin[windowIdx]) + 1;
yMaxCurr = (int)floor(-yMin[windowIdx]) + 1;
// The following code block implements these lines
// as if they were executed simultaneously (see `void updateGradInputFrac()`):
// xMinCurr = (x == 0 and xMaxCurr >= 0 ? 0 : xMinCurr);
// xMaxCurr = (x == h-1 and xMinCurr <= 0 ? h+66 : xMaxCurr);
// yMinCurr = (y == 0 and yMaxCurr >= 0 ? 0 : yMinCurr);
// yMaxCurr = (y == w-1 and yMinCurr <= 0 ? w+66 : yMaxCurr);
bool needToChangeMin, needToChangeMax;
needToChangeMin = x == 0 and xMaxCurr >= 0;
needToChangeMax = x == h-1 and xMinCurr <= 0;
if (needToChangeMin) xMinCurr = 0;
if (needToChangeMax) xMaxCurr = h+66;
needToChangeMin = y == 0 and yMaxCurr >= 0;
needToChangeMax = y == w-1 and yMinCurr <= 0;
if (needToChangeMin) yMinCurr = 0;
if (needToChangeMax) yMaxCurr = w+66;
const int t = max(0, min(x+xMinCurr, h) );
const int b = max(0, min(x+xMaxCurr, h) );
const int l = max(0, min(y+yMinCurr, w) );
const int r = max(0, min(y+yMaxCurr, w) );
outValue += gradOutputIntData[b*(w+1) + r];
outValue -= gradOutputIntData[t*(w+1) + r];
outValue -= gradOutputIntData[b*(w+1) + l];
outValue += gradOutputIntData[t*(w+1) + l];
// go to the next channel
gradOutputIntData += (h+1)*(w+1);
}
gradInputData[x*w + y] = outValue;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void updateGradInputVarScaleKernel( float *gradOutputIntData, float *gradInputData, int h, int w, int nWindows, float *xMin, float *xMax, float *yMin, float *yMax) {
const int x = BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = BLOCK_SIZE * blockIdx.y + threadIdx.y;
if (x < h and y < w) {
int xMinCurr, xMaxCurr, yMinCurr, yMaxCurr;
double outValue = 0;
for (int windowIdx = 0; windowIdx < nWindows; ++windowIdx) {
xMinCurr = (int)ceil(-xMax[windowIdx]);
yMinCurr = (int)ceil(-yMax[windowIdx]);
xMaxCurr = (int)floor(-xMin[windowIdx]) + 1;
yMaxCurr = (int)floor(-yMin[windowIdx]) + 1;
// The following code block implements these lines
// as if they were executed simultaneously (see `void updateGradInputFrac()`):
// xMinCurr = (x == 0 and xMaxCurr >= 0 ? 0 : xMinCurr);
// xMaxCurr = (x == h-1 and xMinCurr <= 0 ? h+66 : xMaxCurr);
// yMinCurr = (y == 0 and yMaxCurr >= 0 ? 0 : yMinCurr);
// yMaxCurr = (y == w-1 and yMinCurr <= 0 ? w+66 : yMaxCurr);
bool needToChangeMin, needToChangeMax;
needToChangeMin = x == 0 and xMaxCurr >= 0;
needToChangeMax = x == h-1 and xMinCurr <= 0;
if (needToChangeMin) xMinCurr = 0;
if (needToChangeMax) xMaxCurr = h+66;
needToChangeMin = y == 0 and yMaxCurr >= 0;
needToChangeMax = y == w-1 and yMinCurr <= 0;
if (needToChangeMin) yMinCurr = 0;
if (needToChangeMax) yMaxCurr = w+66;
const int t = max(0, min(x+xMinCurr, h) );
const int b = max(0, min(x+xMaxCurr, h) );
const int l = max(0, min(y+yMinCurr, w) );
const int r = max(0, min(y+yMaxCurr, w) );
outValue += gradOutputIntData[b*(w+1) + r];
outValue -= gradOutputIntData[t*(w+1) + r];
outValue -= gradOutputIntData[b*(w+1) + l];
outValue += gradOutputIntData[t*(w+1) + l];
// go to the next channel
gradOutputIntData += (h+1)*(w+1);
}
gradInputData[x*w + y] = outValue;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.globl _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.p2align 8
.type _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_,@function
_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_:
s_load_b64 s[16:17], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v3, s14, 2, v1
v_lshl_add_u32 v0, s15, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s16, v3
v_cmp_gt_i32_e64 s2, s17, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b32 s22, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s22, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[18:19], s[0:1], 0x0
s_load_b256 s[8:15], s[0:1], 0x20
s_add_i32 s24, s17, 1
s_add_i32 s4, s16, 1
s_add_i32 s2, s16, -1
s_add_i32 s5, s17, -1
s_mul_i32 s6, s24, s4
v_mov_b32_e32 v1, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_cmp_eq_u32_e64 s2, s2, v3
v_cmp_eq_u32_e64 s3, 0, v0
v_mov_b32_e32 v2, 0
v_cmp_eq_u32_e64 s4, s5, v0
s_ashr_i32 s7, s6, 31
s_add_i32 s23, s16, 0x42
s_add_i32 s25, s17, 0x42
s_lshl_b64 s[20:21], s[6:7], 2
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[10:11], 0x0
s_load_b32 s6, s[8:9], 0x0
s_load_b32 s7, s[12:13], 0x0
s_load_b32 s26, s[14:15], 0x0
s_waitcnt lgkmcnt(0)
v_ceil_f32_e64 v4, -s5
v_floor_f32_e64 v5, -s6
v_floor_f32_e64 v6, -s7
v_ceil_f32_e64 v7, -s26
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v4, v4
v_cvt_i32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v6, v6
v_cvt_i32_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e64 s5, 1, v4
v_add_nc_u32_e32 v8, 1, v5
v_cmp_lt_i32_e64 s6, -2, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e64 s7, 1, v7
v_add_nc_u32_e32 v5, 1, v6
s_and_b32 s5, s2, s5
v_cndmask_b32_e64 v8, v8, s23, s5
s_and_b32 s5, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v9, v4, 0, s5
s_and_b32 s5, s4, s7
v_cndmask_b32_e64 v4, v5, s25, s5
v_add_nc_u32_e32 v5, v8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v9, v9, v3
v_add_nc_u32_e32 v4, v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_minmax_i32 v5, v5, s16, 0
v_minmax_i32 v10, v4, s17, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v5, s24
v_add_nc_u32_e32 v4, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s5, s18, v4
v_add_co_ci_u32_e64 v5, s5, s19, v5, s5
global_load_b32 v11, v[4:5], off
v_minmax_i32 v4, v9, s16, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v4, s24
v_add_nc_u32_e32 v4, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s5, s18, v4
v_add_co_ci_u32_e64 v5, s5, s19, v5, s5
v_cmp_lt_i32_e64 s5, -2, v6
global_load_b32 v6, v[4:5], off
s_and_b32 s5, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v7, 0, s5
v_add_nc_u32_e32 v4, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_minmax_i32 v7, v4, s17, 0
v_add_nc_u32_e32 v4, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s5, s18, v4
v_add_co_ci_u32_e64 v5, s5, s19, v5, s5
global_load_b32 v8, v[4:5], off
v_add_nc_u32_e32 v4, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s5, s18, v4
v_add_co_ci_u32_e64 v5, s5, s19, v5, s5
s_add_u32 s18, s18, s20
s_addc_u32 s19, s19, s21
s_add_i32 s22, s22, -1
global_load_b32 v9, v[4:5], off
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_add_u32 s12, s12, 4
s_addc_u32 s13, s13, 0
s_cmp_eq_u32 s22, 0
s_waitcnt vmcnt(3)
v_cvt_f64_f32_e32 v[4:5], v11
s_waitcnt vmcnt(2)
v_cvt_f64_f32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], v[4:5]
v_add_f64 v[1:2], v[1:2], -v[6:7]
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[4:5], v8
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], -v[4:5]
v_add_f64 v[1:2], v[1:2], v[6:7]
s_cbranch_scc0 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v1, v[1:2]
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v1, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s17, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 64
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, .Lfunc_end0-_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 64
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void updateGradInputVarScaleKernel( float *gradOutputIntData, float *gradInputData, int h, int w, int nWindows, float *xMin, float *xMax, float *yMin, float *yMax) {
const int x = BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = BLOCK_SIZE * blockIdx.y + threadIdx.y;
if (x < h and y < w) {
int xMinCurr, xMaxCurr, yMinCurr, yMaxCurr;
double outValue = 0;
for (int windowIdx = 0; windowIdx < nWindows; ++windowIdx) {
xMinCurr = (int)ceil(-xMax[windowIdx]);
yMinCurr = (int)ceil(-yMax[windowIdx]);
xMaxCurr = (int)floor(-xMin[windowIdx]) + 1;
yMaxCurr = (int)floor(-yMin[windowIdx]) + 1;
// The following code block implements these lines
// as if they were executed simultaneously (see `void updateGradInputFrac()`):
// xMinCurr = (x == 0 and xMaxCurr >= 0 ? 0 : xMinCurr);
// xMaxCurr = (x == h-1 and xMinCurr <= 0 ? h+66 : xMaxCurr);
// yMinCurr = (y == 0 and yMaxCurr >= 0 ? 0 : yMinCurr);
// yMaxCurr = (y == w-1 and yMinCurr <= 0 ? w+66 : yMaxCurr);
bool needToChangeMin, needToChangeMax;
needToChangeMin = x == 0 and xMaxCurr >= 0;
needToChangeMax = x == h-1 and xMinCurr <= 0;
if (needToChangeMin) xMinCurr = 0;
if (needToChangeMax) xMaxCurr = h+66;
needToChangeMin = y == 0 and yMaxCurr >= 0;
needToChangeMax = y == w-1 and yMinCurr <= 0;
if (needToChangeMin) yMinCurr = 0;
if (needToChangeMax) yMaxCurr = w+66;
const int t = max(0, min(x+xMinCurr, h) );
const int b = max(0, min(x+xMaxCurr, h) );
const int l = max(0, min(y+yMinCurr, w) );
const int r = max(0, min(y+yMaxCurr, w) );
outValue += gradOutputIntData[b*(w+1) + r];
outValue -= gradOutputIntData[t*(w+1) + r];
outValue -= gradOutputIntData[b*(w+1) + l];
outValue += gradOutputIntData[t*(w+1) + l];
// go to the next channel
gradOutputIntData += (h+1)*(w+1);
}
gradInputData[x*w + y] = outValue;
}
} | .text
.file "updateGradInputVarScaleKernel.hip"
.globl _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_ # -- Begin function _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.p2align 4, 0x90
.type _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_,@function
_Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_: # @_Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, .Lfunc_end0-_Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_,@object # @_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.p2align 3, 0x0
_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_:
.quad _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.size _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR16, c[0x0][0x160] ; /* 0x0000580000107ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, 0x4, R3 ; /* 0x0000000400007824 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R5, R5, 0x4, R2 ; /* 0x0000000405057824 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*00e0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xec0 ; /* 0x00000dc000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P0, PT, R4.reuse, 0x1, PT ; /* 0x000000010400780c */
/* 0x040fe20003f05270 */
/*0110*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ LOP3.LUT R4, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104047812 */
/* 0x000fe200078ec0ff */
/*0130*/ UIADD3 UR9, UR5, -0x1, URZ ; /* 0xffffffff05097890 */
/* 0x000fe2000fffe03f */
/*0140*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0150*/ UIADD3 UR10, UR5, 0x42, URZ ; /* 0x00000042050a7890 */
/* 0x000fe2000fffe03f */
/*0160*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0170*/ UIADD3 UR7, UR4, -0x1, URZ ; /* 0xffffffff04077890 */
/* 0x000fe4000fffe03f */
/*0180*/ UIADD3 UR8, UR4, 0x42, URZ ; /* 0x0000004204087890 */
/* 0x000fe4000fffe03f */
/*0190*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fc4000fffe03f */
/*01a0*/ @!P0 BRA 0xa70 ; /* 0x000008c000008947 */
/* 0x000fea0003800000 */
/*01b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*01c0*/ ISETP.NE.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720c */
/* 0x040fe20003f05270 */
/*01d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*01e0*/ ISETP.NE.AND P1, PT, R5, UR7, PT ; /* 0x0000000705007c0c */
/* 0x000fe2000bf25270 */
/*01f0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0200*/ ISETP.NE.AND P2, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f45270 */
/*0210*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0220*/ ISETP.NE.AND P3, PT, R0, UR9, PT ; /* 0x0000000900007c0c */
/* 0x000fe2000bf65270 */
/*0230*/ USHF.R.S32.HI UR11, URZ, 0x1f, UR4 ; /* 0x0000001f3f0b7899 */
/* 0x000fe20008011404 */
/*0240*/ IADD3 R7, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004077a10 */
/* 0x000fe20007ffe1ff */
/*0250*/ USHF.L.U32 UR14, UR4, 0x1, URZ ; /* 0x00000001040e7899 */
/* 0x000fc4000800063f */
/*0260*/ USHF.L.U64.HI UR6, UR4, 0x1, UR11 ; /* 0x0000000104067899 */
/* 0x000fc8000801020b */
/*0270*/ USHF.L.U64.HI UR6, UR14, 0x2, UR6 ; /* 0x000000020e067899 */
/* 0x000fe40008010206 */
/*0280*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.WIDE R12, R6, R15, c[0x0][0x180] ; /* 0x00006000060c7625 */
/* 0x000fc800078e020f */
/*02a0*/ IMAD.WIDE R10, R6.reuse, R15.reuse, c[0x0][0x188] ; /* 0x00006200060a7625 */
/* 0x0c0fe200078e020f */
/*02b0*/ LDG.E R19, [R12.64] ; /* 0x0000000c0c137981 */
/* 0x001ea6000c1e1900 */
/*02c0*/ IMAD.WIDE R16, R6.reuse, R15.reuse, c[0x0][0x198] ; /* 0x0000660006107625 */
/* 0x0c0fe200078e020f */
/*02d0*/ LDG.E R9, [R10.64] ; /* 0x0000000c0a097981 */
/* 0x0000e6000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R6, R15, c[0x0][0x190] ; /* 0x00006400060e7625 */
/* 0x000fe200078e020f */
/*02f0*/ LDG.E R18, [R16.64] ; /* 0x0000000c10127981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R20, [R14.64] ; /* 0x0000000c0e147981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R8, [R10.64+0x4] ; /* 0x0000040c0a087981 */
/* 0x000128000c1e1900 */
/*0320*/ LDG.E R22, [R12.64+0x4] ; /* 0x0000040c0c167981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R21, [R16.64+0x4] ; /* 0x0000040c10157981 */
/* 0x002328000c1e1900 */
/*0340*/ LDG.E R24, [R14.64+0x4] ; /* 0x0000040c0e187981 */
/* 0x000322000c1e1900 */
/*0350*/ IMAD.U32 R10, RZ, RZ, UR16 ; /* 0x00000010ff0a7e24 */
/* 0x001fc4000f8e00ff */
/*0360*/ IMAD.U32 R11, RZ, RZ, UR17 ; /* 0x00000011ff0b7e24 */
/* 0x000fe2000f8e00ff */
/*0370*/ F2I.FLOOR.NTZ R19, -R19 ; /* 0x8000001300137305 */
/* 0x004e300000207100 */
/*0380*/ F2I.CEIL.NTZ R9, -R9 ; /* 0x8000000900097305 */
/* 0x008eb0000020b100 */
/*0390*/ F2I.FLOOR.NTZ R20, -R20 ; /* 0x8000001400147305 */
/* 0x020ef00000207100 */
/*03a0*/ F2I.CEIL.NTZ R18, -R18 ; /* 0x8000001200127305 */
/* 0x010f22000020b100 */
/*03b0*/ ISETP.GT.AND P5, PT, R19, -0x2, !P0 ; /* 0xfffffffe1300780c */
/* 0x001fc400047a4270 */
/*03c0*/ ISETP.LT.AND P6, PT, R9, 0x1, !P1 ; /* 0x000000010900780c */
/* 0x004fe40004fc1270 */
/*03d0*/ IADD3 R14, R19, 0x1, RZ ; /* 0x00000001130e7810 */
/* 0x002fc60007ffe0ff */
/*03e0*/ F2I.CEIL.NTZ R8, -R8 ; /* 0x8000000800087305 */
/* 0x000e22000020b100 */
/*03f0*/ SEL R16, R9, RZ, !P5 ; /* 0x000000ff09107207 */
/* 0x000fe40006800000 */
/*0400*/ ISETP.GT.AND P5, PT, R20, -0x2, !P2 ; /* 0xfffffffe1400780c */
/* 0x008fca00057a4270 */
/*0410*/ F2I.FLOOR.NTZ R23, -R22 ; /* 0x8000001600177305 */
/* 0x0002a20000207100 */
/*0420*/ IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fce0007ffe0ff */
/*0430*/ F2I.CEIL.NTZ R12, -R21 ; /* 0x80000015000c7305 */
/* 0x000ee2000020b100 */
/*0440*/ SEL R22, R14, UR8, !P6 ; /* 0x000000080e167c07 */
/* 0x002fe4000f000000 */
/*0450*/ ISETP.LT.AND P6, PT, R18, 0x1, !P3 ; /* 0x000000011200780c */
/* 0x010fca0005fc1270 */
/*0460*/ F2I.FLOOR.NTZ R13, -R24 ; /* 0x80000018000d7305 */
/* 0x000e620000207100 */
/*0470*/ SEL R17, R20, UR10, !P6 ; /* 0x0000000a14117c07 */
/* 0x000fe2000f000000 */
/*0480*/ IMAD.IADD R22, R5, 0x1, R22 ; /* 0x0000000105167824 */
/* 0x000fe200078e0216 */
/*0490*/ SEL R15, R18, RZ, !P5 ; /* 0x000000ff120f7207 */
/* 0x000fc60006800000 */
/*04a0*/ IMAD.IADD R17, R0, 0x1, R17 ; /* 0x0000000100117824 */
/* 0x000fe200078e0211 */
/*04b0*/ ISETP.LT.AND P4, PT, R8, 0x1, !P1 ; /* 0x000000010800780c */
/* 0x001fe40004f81270 */
/*04c0*/ IADD3 R9, R23, 0x1, RZ ; /* 0x0000000117097810 */
/* 0x004fe40007ffe0ff */
/*04d0*/ ISETP.LT.AND P6, PT, R12, 0x1, !P3 ; /* 0x000000010c00780c */
/* 0x008fe20005fc1270 */
/*04e0*/ IMAD.IADD R16, R5, 0x1, R16 ; /* 0x0000000105107824 */
/* 0x000fe200078e0210 */
/*04f0*/ ISETP.GT.AND P5, PT, R23, -0x2, !P0 ; /* 0xfffffffe1700780c */
/* 0x000fe400047a4270 */
/*0500*/ IADD3 R14, R13, 0x1, RZ ; /* 0x000000010d0e7810 */
/* 0x002fe20007ffe0ff */
/*0510*/ IMAD.IADD R15, R0, 0x1, R15 ; /* 0x00000001000f7824 */
/* 0x000fe200078e020f */
/*0520*/ IMNMX R22, R22, c[0x0][0x170], PT ; /* 0x00005c0016167a17 */
/* 0x000fc40003800200 */
/*0530*/ IMNMX R17, R17, c[0x0][0x174], PT ; /* 0x00005d0011117a17 */
/* 0x000fe40003800200 */
/*0540*/ SEL R18, R9, UR8, !P4 ; /* 0x0000000809127c07 */
/* 0x000fe4000e000000 */
/*0550*/ SEL R23, R14, UR10, !P6 ; /* 0x0000000a0e177c07 */
/* 0x000fe4000f000000 */
/*0560*/ IMNMX R16, R16, c[0x0][0x170], PT ; /* 0x00005c0010107a17 */
/* 0x000fe40003800200 */
/*0570*/ IMNMX R22, RZ, R22, !PT ; /* 0x00000016ff167217 */
/* 0x000fe40007800200 */
/*0580*/ IMNMX R17, RZ, R17, !PT ; /* 0x00000011ff117217 */
/* 0x000fe20007800200 */
/*0590*/ IMAD.IADD R18, R5, 0x1, R18 ; /* 0x0000000105127824 */
/* 0x000fe200078e0212 */
/*05a0*/ IMNMX R15, R15, c[0x0][0x174], PT ; /* 0x00005d000f0f7a17 */
/* 0x000fe20003800200 */
/*05b0*/ IMAD.IADD R23, R0, 0x1, R23 ; /* 0x0000000100177824 */
/* 0x000fe200078e0217 */
/*05c0*/ IMNMX R16, RZ, R16, !PT ; /* 0x00000010ff107217 */
/* 0x000fe20007800200 */
/*05d0*/ IMAD R21, R22, UR5, R17 ; /* 0x0000000516157c24 */
/* 0x000fe2000f8e0211 */
/*05e0*/ ISETP.GT.AND P4, PT, R13, -0x2, !P2 ; /* 0xfffffffe0d00780c */
/* 0x000fc40005784270 */
/*05f0*/ SEL R8, R8, RZ, !P5 ; /* 0x000000ff08087207 */
/* 0x000fe40006800000 */
/*0600*/ IMNMX R19, RZ, R15, !PT ; /* 0x0000000fff137217 */
/* 0x000fe40007800200 */
/*0610*/ IMNMX R18, R18, c[0x0][0x170], PT ; /* 0x00005c0012127a17 */
/* 0x000fe40003800200 */
/*0620*/ IMNMX R13, R23, c[0x0][0x174], PT ; /* 0x00005d00170d7a17 */
/* 0x000fe20003800200 */
/*0630*/ IMAD R15, R16, UR5, R17 ; /* 0x00000005100f7c24 */
/* 0x000fe2000f8e0211 */
/*0640*/ SEL R23, R12, RZ, !P4 ; /* 0x000000ff0c177207 */
/* 0x000fe20006000000 */
/*0650*/ IMAD.WIDE R20, R21, 0x4, R10 ; /* 0x0000000415147825 */
/* 0x000fc800078e020a */
/*0660*/ IMAD.IADD R12, R5, 0x1, R8 ; /* 0x00000001050c7824 */
/* 0x000fe200078e0208 */
/*0670*/ IMNMX R8, RZ, R13, !PT ; /* 0x0000000dff087217 */
/* 0x000fe20007800200 */
/*0680*/ IMAD R17, R22, UR5, R19.reuse ; /* 0x0000000516117c24 */
/* 0x100fe2000f8e0213 */
/*0690*/ LDG.E R13, [R20.64] ; /* 0x0000000c140d7981 */
/* 0x0000a2000c1e1900 */
/*06a0*/ IMAD R9, R16, UR5, R19 ; /* 0x0000000510097c24 */
/* 0x000fe2000f8e0213 */
/*06b0*/ IMNMX R19, RZ, R18, !PT ; /* 0x00000012ff137217 */
/* 0x000fe20007800200 */
/*06c0*/ IMAD.WIDE R14, R15, 0x4, R10 ; /* 0x000000040f0e7825 */
/* 0x000fe200078e020a */
/*06d0*/ IMNMX R12, R12, c[0x0][0x170], PT ; /* 0x00005c000c0c7a17 */
/* 0x000fc60003800200 */
/*06e0*/ IMAD.IADD R23, R0, 0x1, R23 ; /* 0x0000000100177824 */
/* 0x000fe400078e0217 */
/*06f0*/ IMAD R22, R19, UR5, R8 ; /* 0x0000000513167c24 */
/* 0x000fe2000f8e0208 */
/*0700*/ IMNMX R18, RZ, R12, !PT ; /* 0x0000000cff127217 */
/* 0x000fe20007800200 */
/*0710*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x0002e2000c1e1900 */
/*0720*/ IMNMX R23, R23, c[0x0][0x174], PT ; /* 0x00005d0017177a17 */
/* 0x000fe20003800200 */
/*0730*/ IMAD.WIDE R16, R17, 0x4, R10 ; /* 0x0000000411107825 */
/* 0x000fe200078e020a */
/*0740*/ IADD3 R24, P4, R22, UR4, RZ ; /* 0x0000000416187c10 */
/* 0x000fc6000ff9e0ff */
/*0750*/ IMAD R25, R18, UR5, R8 ; /* 0x0000000512197c24 */
/* 0x000fe2000f8e0208 */
/*0760*/ IMNMX R20, RZ, R23, !PT ; /* 0x00000017ff147217 */
/* 0x001fe20007800200 */
/*0770*/ LDG.E R12, [R16.64] ; /* 0x0000000c100c7981 */
/* 0x000122000c1e1900 */
/*0780*/ LEA.HI.X.SX32 R27, R22, UR11, 0x1, P4 ; /* 0x0000000b161b7c11 */
/* 0x000fe2000a0f0eff */
/*0790*/ IMAD.WIDE R22, R9, 0x4, R10 ; /* 0x0000000409167825 */
/* 0x000fe200078e020a */
/*07a0*/ LEA R8, P4, R24.reuse, UR16, 0x2 ; /* 0x0000001018087c11 */
/* 0x040fe4000f8810ff */
/*07b0*/ IADD3 R21, P5, R25, UR4, RZ ; /* 0x0000000419157c10 */
/* 0x000fe2000ffbe0ff */
/*07c0*/ IMAD R19, R19, UR5, R20 ; /* 0x0000000513137c24 */
/* 0x000fe2000f8e0214 */
/*07d0*/ LEA.HI.X R9, R24, UR17, R27, 0x2, P4 ; /* 0x0000001118097c11 */
/* 0x000fe2000a0f141b */
/*07e0*/ LDG.E R22, [R22.64] ; /* 0x0000000c16167981 */
/* 0x000f62000c1e1900 */
/*07f0*/ LEA.HI.X.SX32 R24, R25, UR11, 0x1, P5 ; /* 0x0000000b19187c11 */
/* 0x000fc4000a8f0eff */
/*0800*/ LEA R10, P4, R21, UR16, 0x2 ; /* 0x00000010150a7c11 */
/* 0x000fe2000f8810ff */
/*0810*/ IMAD R18, R18, UR5, R20 ; /* 0x0000000512127c24 */
/* 0x000fe2000f8e0214 */
/*0820*/ IADD3 R25, P5, R19, UR4, RZ ; /* 0x0000000413197c10 */
/* 0x000fe4000ffbe0ff */
/*0830*/ LEA.HI.X R11, R21, UR17, R24, 0x2, P4 ; /* 0x00000011150b7c11 */
/* 0x000fe4000a0f1418 */
/*0840*/ LDG.E R24, [R8.64] ; /* 0x0000000c08187981 */
/* 0x000962000c1e1900 */
/*0850*/ LEA.HI.X.SX32 R20, R19, UR11, 0x1, P5 ; /* 0x0000000b13147c11 */
/* 0x000fe4000a8f0eff */
/*0860*/ LEA R16, P4, R25, UR16, 0x2 ; /* 0x0000001019107c11 */
/* 0x001fe2000f8810ff */
/*0870*/ LDG.E R10, [R10.64] ; /* 0x0000000c0a0a7981 */
/* 0x000f62000c1e1900 */
/*0880*/ IADD3 R15, P5, R18, UR4, RZ ; /* 0x00000004120f7c10 */
/* 0x002fc4000ffbe0ff */
/*0890*/ LEA.HI.X R17, R25, UR17, R20, 0x2, P4 ; /* 0x0000001119117c11 */
/* 0x000fe4000a0f1414 */
/*08a0*/ LEA.HI.X.SX32 R20, R18, UR11, 0x1, P5 ; /* 0x0000000b12147c11 */
/* 0x000fe4000a8f0eff */
/*08b0*/ LEA R18, P4, R15.reuse, UR16, 0x2 ; /* 0x000000100f127c11 */
/* 0x040fe2000f8810ff */
/*08c0*/ LDG.E R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000f66000c1e1900 */
/*08d0*/ LEA.HI.X R19, R15, UR17, R20, 0x2, P4 ; /* 0x000000110f137c11 */
/* 0x000fca000a0f1414 */
/*08e0*/ LDG.E R18, [R18.64] ; /* 0x0000000c12127981 */
/* 0x000f62000c1e1900 */
/*08f0*/ IADD3 R7, R7, -0x2, RZ ; /* 0xfffffffe07077810 */
/* 0x000fc80007ffe0ff */
/*0900*/ ISETP.NE.AND P4, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f85270 */
/*0910*/ ULEA UR16, UP0, UR14, UR16, 0x2 ; /* 0x000000100e107291 */
/* 0x000fe2000f80103f */
/*0920*/ IADD3 R6, R6, 0x2, RZ ; /* 0x0000000206067810 */
/* 0x000fc60007ffe0ff */
/*0930*/ UIADD3.X UR17, UR17, UR6, URZ, UP0, !UPT ; /* 0x0000000611117290 */
/* 0x000fe200087fe43f */
/*0940*/ F2F.F64.F32 R20, R13 ; /* 0x0000000d00147310 */
/* 0x004e300000201800 */
/*0950*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x008e700000201800 */
/*0960*/ F2F.F64.F32 R8, R12 ; /* 0x0000000c00087310 */
/* 0x010ea20000201800 */
/*0970*/ DADD R20, R20, R2 ; /* 0x0000000014147229 */
/* 0x001e4e0000000002 */
/*0980*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x020e220000201800 */
/*0990*/ DADD R20, R20, -R14 ; /* 0x0000000014147229 */
/* 0x002e8e000000080e */
/*09a0*/ F2F.F64.F32 R24, R24 ; /* 0x0000001800187310 */
/* 0x000e620000201800 */
/*09b0*/ DADD R8, R20, -R8 ; /* 0x0000000014087229 */
/* 0x004e0e0000000808 */
/*09c0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x000ea20000201800 */
/*09d0*/ DADD R8, R8, R22 ; /* 0x0000000008087229 */
/* 0x001e4e0000000016 */
/*09e0*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x000e220000201800 */
/*09f0*/ DADD R8, R8, R24 ; /* 0x0000000008087229 */
/* 0x002e8e0000000018 */
/*0a00*/ F2F.F64.F32 R18, R18 ; /* 0x0000001200127310 */
/* 0x000e620000201800 */
/*0a10*/ DADD R8, R8, -R10 ; /* 0x0000000008087229 */
/* 0x004e0c000000080a */
/*0a20*/ DADD R8, R8, -R16 ; /* 0x0000000008087229 */
/* 0x001e4c0000000810 */
/*0a30*/ DADD R2, R8, R18 ; /* 0x0000000008027229 */
/* 0x0020620000000012 */
/*0a40*/ @P4 BRA 0x280 ; /* 0xfffff83000004947 */
/* 0x000fea000383ffff */
/*0a50*/ SHF.R.S32.HI R9, RZ, 0x1f, R6.reuse ; /* 0x0000001fff097819 */
/* 0x101fe20000011406 */
/*0a60*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0006 */
/*0a70*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0a80*/ IMAD.U32 R6, RZ, RZ, UR16 ; /* 0x00000010ff067e24 */
/* 0x000fe4000f8e00ff */
/*0a90*/ IMAD.U32 R7, RZ, RZ, UR17 ; /* 0x00000011ff077e24 */
/* 0x000fd4000f8e00ff */
/*0aa0*/ @!P0 BRA 0xeb0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ IMAD.SHL.U32 R14, R8.reuse, 0x4, RZ ; /* 0x00000004080e7824 */
/* 0x040fe200078e00ff */
/*0ac0*/ SHF.L.U64.HI R4, R8, 0x2, R9 ; /* 0x0000000208047819 */
/* 0x000fc80000010209 */
/*0ad0*/ IADD3 R8, P0, R14.reuse, c[0x0][0x188], RZ ; /* 0x000062000e087a10 */
/* 0x040fe40007f1e0ff */
/*0ae0*/ IADD3 R10, P1, R14.reuse, c[0x0][0x198], RZ ; /* 0x000066000e0a7a10 */
/* 0x040fe40007f3e0ff */
/*0af0*/ IADD3 R12, P2, R14, c[0x0][0x180], RZ ; /* 0x000060000e0c7a10 */
/* 0x000fe40007f5e0ff */
/*0b00*/ IADD3.X R9, R4, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630004097a10 */
/* 0x000fe400007fe4ff */
/*0b10*/ IADD3 R14, P0, R14, c[0x0][0x190], RZ ; /* 0x000064000e0e7a10 */
/* 0x000fe40007f1e0ff */
/*0b20*/ IADD3.X R11, R4.reuse, c[0x0][0x19c], RZ, P1, !PT ; /* 0x00006700040b7a10 */
/* 0x040fe20000ffe4ff */
/*0b30*/ LDG.E R8, [R8.64] ; /* 0x0000000c08087981 */
/* 0x000ea2000c1e1900 */
/*0b40*/ IADD3.X R13, R4, c[0x0][0x184], RZ, P2, !PT ; /* 0x00006100040d7a10 */
/* 0x000fc400017fe4ff */
/*0b50*/ IADD3.X R15, R4, c[0x0][0x194], RZ, P0, !PT ; /* 0x00006500040f7a10 */
/* 0x000fe200007fe4ff */
/*0b60*/ LDG.E R10, [R10.64] ; /* 0x0000000c0a0a7981 */
/* 0x000ee8000c1e1900 */
/*0b70*/ LDG.E R12, [R12.64] ; /* 0x0000000c0c0c7981 */
/* 0x000f28000c1e1900 */
/*0b80*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000f62000c1e1900 */
/*0b90*/ F2I.CEIL.NTZ R4, -R8 ; /* 0x8000000800047305 */
/* 0x004e30000020b100 */
/*0ba0*/ F2I.CEIL.NTZ R16, -R10 ; /* 0x8000000a00107305 */
/* 0x008eb0000020b100 */
/*0bb0*/ F2I.FLOOR.NTZ R17, -R12 ; /* 0x8000000c00117305 */
/* 0x010ef00000207100 */
/*0bc0*/ F2I.FLOOR.NTZ R18, -R14 ; /* 0x8000000e00127305 */
/* 0x020f220000207100 */
/*0bd0*/ ISETP.GE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x001fc40003f26270 */
/*0be0*/ ISETP.GE.AND P2, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x004fe40003f46270 */
/*0bf0*/ ISETP.EQ.AND P1, PT, R5, UR7, !P1 ; /* 0x0000000705007c0c */
/* 0x000fe4000cf22270 */
/*0c00*/ ISETP.EQ.AND P2, PT, R0, UR9, !P2 ; /* 0x0000000900007c0c */
/* 0x000fe4000d742270 */
/*0c10*/ IADD3 R9, R17.reuse, 0x1, RZ ; /* 0x0000000111097810 */
/* 0x048fe40007ffe0ff */
/*0c20*/ ISETP.GT.AND P0, PT, R17, -0x2, PT ; /* 0xfffffffe1100780c */
/* 0x000fe40003f04270 */
/*0c30*/ IADD3 R19, R18, 0x1, RZ ; /* 0x0000000112137810 */
/* 0x010fc40007ffe0ff */
/*0c40*/ SEL R8, R9, UR8, !P1 ; /* 0x0000000809087c07 */
/* 0x000fe4000c800000 */
/*0c50*/ SEL R19, R19, UR10, !P2 ; /* 0x0000000a13137c07 */
/* 0x000fe4000d000000 */
/*0c60*/ ISETP.EQ.AND P0, PT, R5.reuse, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x040fe40000702270 */
/*0c70*/ ISETP.GT.AND P1, PT, R18, -0x2, PT ; /* 0xfffffffe1200780c */
/* 0x000fe20003f24270 */
/*0c80*/ IMAD.IADD R8, R5, 0x1, R8 ; /* 0x0000000105087824 */
/* 0x000fe200078e0208 */
/*0c90*/ SEL R4, R4, RZ, !P0 ; /* 0x000000ff04047207 */
/* 0x000fe20004000000 */
/*0ca0*/ IMAD.IADD R19, R0.reuse, 0x1, R19 ; /* 0x0000000100137824 */
/* 0x040fe200078e0213 */
/*0cb0*/ ISETP.EQ.AND P1, PT, R0, RZ, P1 ; /* 0x000000ff0000720c */
/* 0x000fc40000f22270 */
/*0cc0*/ IMNMX R8, R8, c[0x0][0x170], PT ; /* 0x00005c0008087a17 */
/* 0x000fe20003800200 */
/*0cd0*/ IMAD.IADD R4, R5, 0x1, R4 ; /* 0x0000000105047824 */
/* 0x000fe200078e0204 */
/*0ce0*/ IMNMX R19, R19, c[0x0][0x174], PT ; /* 0x00005d0013137a17 */
/* 0x000fe40003800200 */
/*0cf0*/ SEL R9, R16, RZ, !P1 ; /* 0x000000ff10097207 */
/* 0x000fe40004800000 */
/*0d00*/ IMNMX R12, RZ, R8, !PT ; /* 0x00000008ff0c7217 */
/* 0x000fe40007800200 */
/*0d10*/ IMNMX R19, RZ, R19, !PT ; /* 0x00000013ff137217 */
/* 0x000fe20007800200 */
/*0d20*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x000fe200078e0209 */
/*0d30*/ IMNMX R4, R4, c[0x0][0x170], PT ; /* 0x00005c0004047a17 */
/* 0x000fc60003800200 */
/*0d40*/ IMAD R11, R12, UR5, R19 ; /* 0x000000050c0b7c24 */
/* 0x000fe2000f8e0213 */
/*0d50*/ IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff047217 */
/* 0x000fe40007800200 */
/*0d60*/ IMNMX R10, R9, c[0x0][0x174], PT ; /* 0x00005d00090a7a17 */
/* 0x000fe20003800200 */
/*0d70*/ IMAD.WIDE R8, R11, 0x4, R6 ; /* 0x000000040b087825 */
/* 0x000fc600078e0206 */
/*0d80*/ IMNMX R13, RZ, R10, !PT ; /* 0x0000000aff0d7217 */
/* 0x000fe20007800200 */
/*0d90*/ IMAD R11, R4, UR5, R19 ; /* 0x00000005040b7c24 */
/* 0x000fe2000f8e0213 */
/*0da0*/ LDG.E R18, [R8.64] ; /* 0x0000000c08127981 */
/* 0x000ea6000c1e1900 */
/*0db0*/ IMAD.WIDE R10, R11, 0x4, R6 ; /* 0x000000040b0a7825 */
/* 0x000fc800078e0206 */
/*0dc0*/ IMAD R15, R12, UR5, R13 ; /* 0x000000050c0f7c24 */
/* 0x000fe4000f8e020d */
/*0dd0*/ LDG.E R10, [R10.64] ; /* 0x0000000c0a0a7981 */
/* 0x000ee4000c1e1900 */
/*0de0*/ IMAD.WIDE R14, R15, 0x4, R6 ; /* 0x000000040f0e7825 */
/* 0x000fc800078e0206 */
/*0df0*/ IMAD R17, R4, UR5, R13 ; /* 0x0000000504117c24 */
/* 0x000fe4000f8e020d */
/*0e00*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000f24000c1e1900 */
/*0e10*/ IMAD.WIDE R16, R17, 0x4, R6 ; /* 0x0000000411107825 */
/* 0x000fcc00078e0206 */
/*0e20*/ LDG.E R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000f62000c1e1900 */
/*0e30*/ F2F.F64.F32 R6, R18 ; /* 0x0000001200067310 */
/* 0x004e300000201800 */
/*0e40*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */
/* 0x008eb00000201800 */
/*0e50*/ F2F.F64.F32 R8, R14 ; /* 0x0000000e00087310 */
/* 0x010ee20000201800 */
/*0e60*/ DADD R6, R2, R6 ; /* 0x0000000002067229 */
/* 0x003a8e0000000006 */
/*0e70*/ F2F.F64.F32 R2, R16 ; /* 0x0000001000027310 */
/* 0x020e220000201800 */
/*0e80*/ DADD R6, R6, -R12 ; /* 0x0000000006067229 */
/* 0x004ecc000000080c */
/*0e90*/ DADD R6, R6, -R8 ; /* 0x0000000006067229 */
/* 0x008e0c0000000808 */
/*0ea0*/ DADD R2, R6, R2 ; /* 0x0000000006027229 */
/* 0x0010520000000002 */
/*0eb0*/ F2F.F32.F64 R7, R2 ; /* 0x0000000200077310 */
/* 0x0030640000301000 */
/*0ec0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe400078e00ff */
/*0ed0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fc800078e0200 */
/*0ee0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0ef0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x002fe2000c10190c */
/*0f00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f10*/ BRA 0xf10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.globl _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.p2align 8
.type _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_,@function
_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_:
s_load_b64 s[16:17], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v3, s14, 2, v1
v_lshl_add_u32 v0, s15, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s16, v3
v_cmp_gt_i32_e64 s2, s17, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b32 s22, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s22, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[18:19], s[0:1], 0x0
s_load_b256 s[8:15], s[0:1], 0x20
s_add_i32 s24, s17, 1
s_add_i32 s4, s16, 1
s_add_i32 s2, s16, -1
s_add_i32 s5, s17, -1
s_mul_i32 s6, s24, s4
v_mov_b32_e32 v1, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_cmp_eq_u32_e64 s2, s2, v3
v_cmp_eq_u32_e64 s3, 0, v0
v_mov_b32_e32 v2, 0
v_cmp_eq_u32_e64 s4, s5, v0
s_ashr_i32 s7, s6, 31
s_add_i32 s23, s16, 0x42
s_add_i32 s25, s17, 0x42
s_lshl_b64 s[20:21], s[6:7], 2
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[10:11], 0x0
s_load_b32 s6, s[8:9], 0x0
s_load_b32 s7, s[12:13], 0x0
s_load_b32 s26, s[14:15], 0x0
s_waitcnt lgkmcnt(0)
v_ceil_f32_e64 v4, -s5
v_floor_f32_e64 v5, -s6
v_floor_f32_e64 v6, -s7
v_ceil_f32_e64 v7, -s26
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v4, v4
v_cvt_i32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v6, v6
v_cvt_i32_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e64 s5, 1, v4
v_add_nc_u32_e32 v8, 1, v5
v_cmp_lt_i32_e64 s6, -2, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e64 s7, 1, v7
v_add_nc_u32_e32 v5, 1, v6
s_and_b32 s5, s2, s5
v_cndmask_b32_e64 v8, v8, s23, s5
s_and_b32 s5, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v9, v4, 0, s5
s_and_b32 s5, s4, s7
v_cndmask_b32_e64 v4, v5, s25, s5
v_add_nc_u32_e32 v5, v8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v9, v9, v3
v_add_nc_u32_e32 v4, v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_minmax_i32 v5, v5, s16, 0
v_minmax_i32 v10, v4, s17, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v5, s24
v_add_nc_u32_e32 v4, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s5, s18, v4
v_add_co_ci_u32_e64 v5, s5, s19, v5, s5
global_load_b32 v11, v[4:5], off
v_minmax_i32 v4, v9, s16, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v4, s24
v_add_nc_u32_e32 v4, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s5, s18, v4
v_add_co_ci_u32_e64 v5, s5, s19, v5, s5
v_cmp_lt_i32_e64 s5, -2, v6
global_load_b32 v6, v[4:5], off
s_and_b32 s5, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v7, 0, s5
v_add_nc_u32_e32 v4, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_minmax_i32 v7, v4, s17, 0
v_add_nc_u32_e32 v4, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s5, s18, v4
v_add_co_ci_u32_e64 v5, s5, s19, v5, s5
global_load_b32 v8, v[4:5], off
v_add_nc_u32_e32 v4, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s5, s18, v4
v_add_co_ci_u32_e64 v5, s5, s19, v5, s5
s_add_u32 s18, s18, s20
s_addc_u32 s19, s19, s21
s_add_i32 s22, s22, -1
global_load_b32 v9, v[4:5], off
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_add_u32 s12, s12, 4
s_addc_u32 s13, s13, 0
s_cmp_eq_u32 s22, 0
s_waitcnt vmcnt(3)
v_cvt_f64_f32_e32 v[4:5], v11
s_waitcnt vmcnt(2)
v_cvt_f64_f32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], v[4:5]
v_add_f64 v[1:2], v[1:2], -v[6:7]
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[4:5], v8
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], -v[4:5]
v_add_f64 v[1:2], v[1:2], v[6:7]
s_cbranch_scc0 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v1, v[1:2]
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v1, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s17, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 64
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, .Lfunc_end0-_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 64
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ead7c_00000000-6_updateGradInputVarScaleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_
.type _Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_, @function
_Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_, .-_Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_
.globl _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.type _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, @function
_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z62__device_stub__Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_PfS_iiiS_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, .-_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "updateGradInputVarScaleKernel.hip"
.globl _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_ # -- Begin function _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.p2align 4, 0x90
.type _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_,@function
_Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_: # @_Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, .Lfunc_end0-_Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_,@object # @_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.p2align 3, 0x0
_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_:
.quad _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.size _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29updateGradInputVarScaleKernelPfS_iiiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <time.h>
#include <cuda.h>
#include <cuda_profiler_api.h>
// Thread block sizes
#define BLOCK_SIZE 4096
#define TILE_WIDTH 4
// Matrix dimensions
// (chosen as multiples of the thread block size for simplicity)
#define MATRIX_SIZE 1* BLOCK_SIZE
#define WA (MATRIX_SIZE) // Matrix A width
#define HA (MATRIX_SIZE) // Matrix A height
#define WB (MATRIX_SIZE) // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Allocates a matrix with random float entries.
void randomInit(float* data, int size)
{
for (int i = 0; i < size; ++i)
data[i] = rand() / (float)RAND_MAX;
}
void printOutput(float *C, char a){
int i=0;
printf("Printing %c\n", a);
for(i=0;i<100;i++){
printf("%f\t", *C++);
}
}
__global__ void MatrixMulKernel(float* Md, float* Nd, float* Pd, int Width)
{
// Calculate the row index of the Pd element and M
int Row = blockIdx.y*BLOCK_SIZE + threadIdx.y;
// Calculate the column idenx of Pd and N
int Col = blockIdx.x*BLOCK_SIZE + threadIdx.x;
float Pvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k)
Pvalue += Md[Row*Width+k] * Nd[k*Width+Col];
Pd[Row*Width+Col] = Pvalue;
}
__global__ void MatrixMulKernelTiled(float* Md, float* Nd, float* Pd, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
void MatrixMulOnHost(float* M, float* N, float* P, int Width)
{
for (int i = 0; i < Width; ++i)
for (int j = 0; j < Width; ++j) {
double sum = 0;
for (int k = 0; k < Width; ++k) {
double a = M[i * Width + k];
double b = N[k * Width + j];
sum += a * b;
}
P[i * Width + j] = sum;
}
}
float runMatrixWithOutShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B)
{
cudaEvent_t start, stop;
cudaEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
char a='a',b='b',c='c';
printOutput(h_A,a);
printOutput(h_B,b);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventCreate(&startCopyHtoD);
cudaEventCreate(&stopCopyHtoD);
cudaEventCreate(&startCopyDtoH);
cudaEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
cudaMalloc((void**) &d_A, mem_size_A);
float* d_B;
cudaMalloc((void**) &d_B, mem_size_B);
cudaEventRecord(startCopyHtoD);
// copy host memory to device
cudaMemcpy(d_A, h_A, mem_size_A,cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, mem_size_B,cudaMemcpyHostToDevice);
cudaEventRecord(stopCopyHtoD);
cudaEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
cudaMalloc((void**) &d_C, mem_size_C);
// setup execution parameters
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
cudaEventRecord(start);
// execute the kernel
MatrixMulKernel<<< grid, threads >>>(d_A, d_B, d_C, WB);
cudaEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
cudaEventRecord(startCopyDtoH);
// copy result from device to host
cudaMemcpy(h_C, d_C, mem_size_C,cudaMemcpyDeviceToHost);
cudaEventRecord(stopCopyDtoH);
cudaEventSynchronize(stop);
cudaEventSynchronize(stopCopyDtoH);
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
cudaEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
cudaEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
cudaEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
float runMatrixWithShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B){
cudaEvent_t start, stop;
cudaEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventCreate(&startCopyHtoD);
cudaEventCreate(&stopCopyHtoD);
cudaEventCreate(&startCopyDtoH);
cudaEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
cudaMalloc((void**) &d_A, mem_size_A);
float* d_B;
cudaMalloc((void**) &d_B, mem_size_B);
cudaEventRecord(startCopyHtoD);
// copy host memory to device
cudaMemcpy(d_A, h_A, mem_size_A,cudaMemcpyHostToDevice) ;
cudaMemcpy(d_B, h_B, mem_size_B,cudaMemcpyHostToDevice);
cudaEventRecord(stopCopyHtoD);
cudaEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
cudaMalloc((void**) &d_C, mem_size_C);
dim3 dimThreads(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(WC / dimThreads.x, HA / dimThreads.y);
cudaEventRecord(start);
MatrixMulKernelTiled<<<dimGrid, dimThreads>>>(d_A, d_B, d_C,WB);
cudaEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
cudaEventRecord(startCopyDtoH);
// copy result from device to host
cudaMemcpy(h_C, d_C, mem_size_C,cudaMemcpyDeviceToHost);
cudaEventRecord(stopCopyDtoH);
cudaEventSynchronize(stop);
cudaEventSynchronize(stopCopyDtoH);
char c = 'c';
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
cudaEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
cudaEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
cudaEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
int main()
{
/*long long ctime,cudatime,cudatiletime,hosttime,inittime,totaltime;
struct timeval stime,stime2,etime, etime2,initstime,initetime,totalstime,totaletime,tilestime,tileetime;
gettimeofday(&totalstime,0);
gettimeofday(&initstime,0);
*/
printf("Matrix Size =%dX%d \n",MATRIX_SIZE,MATRIX_SIZE);
printf("Tile Width = %dX%d\n",TILE_WIDTH,TILE_WIDTH);
cudaEvent_t startInit, stopInit;
cudaEventCreate(&startInit);
cudaEventCreate(&stopInit);
cudaEventRecord(startInit);
srand(2006);
// allocate host memory for matrices A and B
unsigned int size_A = WA * HA;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
cudaEventRecord(stopInit);
float initTime = 0;
cudaEventElapsedTime(&initTime, startInit, stopInit);
printf("Init Time: %f\n", initTime);
/*----------------PARALLEL EXECUTION BEGINS HERE ----------------------------*/
printf("Starting Without Shared Memory\n\n");
float matTime = runMatrixWithOutShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time No TILING: %f\n\n", matTime);
/*------------------PARALLEL EXECUTION ENDS HERE ----------------------------*/
/* -----------------TILING EXECUTION BEGINS HERE-----------------------------*/
printf("Starting With Shared Memory\n\n");
float matTimeWithTile = runMatrixWithShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time With TILING: %f\n\n", matTimeWithTile);
/*------------------------------ TILING ENDS HERE ---------------------------------*/
/*
gettimeofday(&stime,0);
// compute reference solution
float* reference = (float*) malloc(mem_size_C);
MatrixMulOnHost(h_A, h_B, reference, WB);
gettimeofday(&etime,0);
hosttime = (etime.tv_sec-stime.tv_sec)*1000000LL + etime.tv_usec-stime.tv_usec;
//printf("host: %lld\ncuda: %lld\ncuda, w/copy: %lld\n", hosttime, cudatime, ctime);
gettimeofday(&totaletime,0);
totaltime = (totaletime.tv_sec-totalstime.tv_sec)*1000000LL + totaletime.tv_usec-totalstime.tv_usec;
*/
// clean up memory
free(h_A);
free(h_B);
//free(h_C);
//free(reference);
//cudaFree(d_A);
//cudaFree(d_B);
//cudaFree(d_C);
//cudaThreadExit();
/* printf("Total Time: %lld\n",totaltime );
printf("Initialization Time: %lld\n",inittime);
printf("Copy Time: %lld\n",ctime-cudatime);
printf("Parallel Time: %lld\n",cudatime);
printf("Host Time: %lld\n", hosttime);
printf("Tile Parallel Time: %lld\n",cudatiletime);
printf("Sum %lld\n", inittime+ctime+hosttime+cudatiletime);*/
} | .file "tmpxft_0005e919_00000000-6_tile_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Printing %c\n"
.LC2:
.string "%f\t"
.text
.globl _Z11printOutputPfc
.type _Z11printOutputPfc, @function
_Z11printOutputPfc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movsbl %sil, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 400(%rbx), %r12
leaq .LC2(%rip), %rbp
.L12:
addq $4, %rbx
pxor %xmm0, %xmm0
cvtss2sd -4(%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpq %rbx, %r12
jne .L12
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11printOutputPfc, .-_Z11printOutputPfc
.globl _Z15MatrixMulOnHostPfS_S_i
.type _Z15MatrixMulOnHostPfS_S_i, @function
_Z15MatrixMulOnHostPfS_S_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L23
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r11
movq %rdx, %r9
movl %ecx, %r12d
movslq %ecx, %rbx
leaq 0(,%rbx,4), %rcx
movq %rdi, %r10
leaq (%rdi,%rcx), %rsi
movl $0, %ebp
.L17:
movq %r11, %r8
movl $0, %edi
.L20:
movq %r8, %rdx
movq %r10, %rax
pxor %xmm1, %xmm1
.L18:
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
pxor %xmm2, %xmm2
cvtss2sd (%rdx), %xmm2
mulsd %xmm2, %xmm0
addsd %xmm0, %xmm1
addq $4, %rax
addq %rcx, %rdx
cmpq %rsi, %rax
jne .L18
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r9,%rdi,4)
addq $1, %rdi
addq $4, %r8
cmpq %rbx, %rdi
jne .L20
addl $1, %ebp
addq %rcx, %r9
addq %rcx, %r10
addq %rcx, %rsi
cmpl %ebp, %r12d
jne .L17
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z15MatrixMulOnHostPfS_S_i, .-_Z15MatrixMulOnHostPfS_S_i
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.section .rodata.str1.1
.LC5:
.string "Copy Time From H To D: %f\n"
.LC6:
.string "Copy Time From D To H: %f\n"
.text
.globl _Z22runMatrixWithOutSharedPfS_jj
.type _Z22runMatrixWithOutSharedPfS_jj, @function
_Z22runMatrixWithOutSharedPfS_jj:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $97, %esi
call _Z11printOutputPfc
movl $98, %esi
movq %r12, %rdi
call _Z11printOutputPfc
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl %ebp, %ebp
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %ebx, %ebx
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 88(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $4096, 96(%rsp)
movl $4096, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $67108864, %edx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $99, %esi
movq %rbx, %rdi
call _Z11printOutputPfc
movl $0x00000000, 12(%rsp)
movl $0x00000000, 16(%rsp)
movl $0x00000000, 20(%rsp)
leaq 16(%rsp), %rdi
movq 64(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 20(%rsp), %xmm0
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl $4096, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
jmp .L35
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z22runMatrixWithOutSharedPfS_jj, .-_Z22runMatrixWithOutSharedPfS_jj
.globl _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i
.type _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i, @function
_Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20MatrixMulKernelTiledPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i, .-_Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i
.globl _Z20MatrixMulKernelTiledPfS_S_i
.type _Z20MatrixMulKernelTiledPfS_S_i, @function
_Z20MatrixMulKernelTiledPfS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z20MatrixMulKernelTiledPfS_S_i, .-_Z20MatrixMulKernelTiledPfS_S_i
.globl _Z19runMatrixWithSharedPfS_jj
.type _Z19runMatrixWithSharedPfS_jj, @function
_Z19runMatrixWithSharedPfS_jj:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl %ebp, %ebp
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %ebx, %ebx
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 88(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $4096, 96(%rsp)
movl $4096, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L49:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $67108864, %edx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $99, %esi
movq %rbx, %rdi
call _Z11printOutputPfc
movl $0x00000000, 12(%rsp)
movl $0x00000000, 16(%rsp)
movl $0x00000000, 20(%rsp)
leaq 16(%rsp), %rdi
movq 64(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 20(%rsp), %xmm0
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl $4096, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i
jmp .L49
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z19runMatrixWithSharedPfS_jj, .-_Z19runMatrixWithSharedPfS_jj
.section .rodata.str1.1
.LC7:
.string "Matrix Size =%dX%d \n"
.LC8:
.string "Tile Width = %dX%d\n"
.LC9:
.string "Init Time: %f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "Starting Without Shared Memory\n\n"
.section .rodata.str1.1
.LC11:
.string "Mat Time No TILING: %f\n\n"
.LC12:
.string "Starting With Shared Memory\n\n"
.LC13:
.string "Mat Time With TILING: %f\n\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $4096, %ecx
movl $4096, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4, %ecx
movl $4, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $2006, %edi
call srand@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %esi
movq %rbp, %rdi
call _Z10randomInitPfi
movl $16777216, %esi
movq %rbx, %rdi
call _Z10randomInitPfi
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z22runMatrixWithOutSharedPfS_jj
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z19runMatrixWithSharedPfS_jj
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z20MatrixMulKernelTiledPfS_S_i"
.section .rodata.str1.1
.LC15:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z20MatrixMulKernelTiledPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <time.h>
#include <cuda.h>
#include <cuda_profiler_api.h>
// Thread block sizes
#define BLOCK_SIZE 4096
#define TILE_WIDTH 4
// Matrix dimensions
// (chosen as multiples of the thread block size for simplicity)
#define MATRIX_SIZE 1* BLOCK_SIZE
#define WA (MATRIX_SIZE) // Matrix A width
#define HA (MATRIX_SIZE) // Matrix A height
#define WB (MATRIX_SIZE) // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Allocates a matrix with random float entries.
void randomInit(float* data, int size)
{
for (int i = 0; i < size; ++i)
data[i] = rand() / (float)RAND_MAX;
}
void printOutput(float *C, char a){
int i=0;
printf("Printing %c\n", a);
for(i=0;i<100;i++){
printf("%f\t", *C++);
}
}
__global__ void MatrixMulKernel(float* Md, float* Nd, float* Pd, int Width)
{
// Calculate the row index of the Pd element and M
int Row = blockIdx.y*BLOCK_SIZE + threadIdx.y;
// Calculate the column idenx of Pd and N
int Col = blockIdx.x*BLOCK_SIZE + threadIdx.x;
float Pvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k)
Pvalue += Md[Row*Width+k] * Nd[k*Width+Col];
Pd[Row*Width+Col] = Pvalue;
}
__global__ void MatrixMulKernelTiled(float* Md, float* Nd, float* Pd, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
void MatrixMulOnHost(float* M, float* N, float* P, int Width)
{
for (int i = 0; i < Width; ++i)
for (int j = 0; j < Width; ++j) {
double sum = 0;
for (int k = 0; k < Width; ++k) {
double a = M[i * Width + k];
double b = N[k * Width + j];
sum += a * b;
}
P[i * Width + j] = sum;
}
}
float runMatrixWithOutShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B)
{
cudaEvent_t start, stop;
cudaEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
char a='a',b='b',c='c';
printOutput(h_A,a);
printOutput(h_B,b);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventCreate(&startCopyHtoD);
cudaEventCreate(&stopCopyHtoD);
cudaEventCreate(&startCopyDtoH);
cudaEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
cudaMalloc((void**) &d_A, mem_size_A);
float* d_B;
cudaMalloc((void**) &d_B, mem_size_B);
cudaEventRecord(startCopyHtoD);
// copy host memory to device
cudaMemcpy(d_A, h_A, mem_size_A,cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, mem_size_B,cudaMemcpyHostToDevice);
cudaEventRecord(stopCopyHtoD);
cudaEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
cudaMalloc((void**) &d_C, mem_size_C);
// setup execution parameters
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
cudaEventRecord(start);
// execute the kernel
MatrixMulKernel<<< grid, threads >>>(d_A, d_B, d_C, WB);
cudaEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
cudaEventRecord(startCopyDtoH);
// copy result from device to host
cudaMemcpy(h_C, d_C, mem_size_C,cudaMemcpyDeviceToHost);
cudaEventRecord(stopCopyDtoH);
cudaEventSynchronize(stop);
cudaEventSynchronize(stopCopyDtoH);
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
cudaEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
cudaEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
cudaEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
float runMatrixWithShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B){
cudaEvent_t start, stop;
cudaEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventCreate(&startCopyHtoD);
cudaEventCreate(&stopCopyHtoD);
cudaEventCreate(&startCopyDtoH);
cudaEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
cudaMalloc((void**) &d_A, mem_size_A);
float* d_B;
cudaMalloc((void**) &d_B, mem_size_B);
cudaEventRecord(startCopyHtoD);
// copy host memory to device
cudaMemcpy(d_A, h_A, mem_size_A,cudaMemcpyHostToDevice) ;
cudaMemcpy(d_B, h_B, mem_size_B,cudaMemcpyHostToDevice);
cudaEventRecord(stopCopyHtoD);
cudaEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
cudaMalloc((void**) &d_C, mem_size_C);
dim3 dimThreads(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(WC / dimThreads.x, HA / dimThreads.y);
cudaEventRecord(start);
MatrixMulKernelTiled<<<dimGrid, dimThreads>>>(d_A, d_B, d_C,WB);
cudaEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
cudaEventRecord(startCopyDtoH);
// copy result from device to host
cudaMemcpy(h_C, d_C, mem_size_C,cudaMemcpyDeviceToHost);
cudaEventRecord(stopCopyDtoH);
cudaEventSynchronize(stop);
cudaEventSynchronize(stopCopyDtoH);
char c = 'c';
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
cudaEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
cudaEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
cudaEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
int main()
{
/*long long ctime,cudatime,cudatiletime,hosttime,inittime,totaltime;
struct timeval stime,stime2,etime, etime2,initstime,initetime,totalstime,totaletime,tilestime,tileetime;
gettimeofday(&totalstime,0);
gettimeofday(&initstime,0);
*/
printf("Matrix Size =%dX%d \n",MATRIX_SIZE,MATRIX_SIZE);
printf("Tile Width = %dX%d\n",TILE_WIDTH,TILE_WIDTH);
cudaEvent_t startInit, stopInit;
cudaEventCreate(&startInit);
cudaEventCreate(&stopInit);
cudaEventRecord(startInit);
srand(2006);
// allocate host memory for matrices A and B
unsigned int size_A = WA * HA;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
cudaEventRecord(stopInit);
float initTime = 0;
cudaEventElapsedTime(&initTime, startInit, stopInit);
printf("Init Time: %f\n", initTime);
/*----------------PARALLEL EXECUTION BEGINS HERE ----------------------------*/
printf("Starting Without Shared Memory\n\n");
float matTime = runMatrixWithOutShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time No TILING: %f\n\n", matTime);
/*------------------PARALLEL EXECUTION ENDS HERE ----------------------------*/
/* -----------------TILING EXECUTION BEGINS HERE-----------------------------*/
printf("Starting With Shared Memory\n\n");
float matTimeWithTile = runMatrixWithShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time With TILING: %f\n\n", matTimeWithTile);
/*------------------------------ TILING ENDS HERE ---------------------------------*/
/*
gettimeofday(&stime,0);
// compute reference solution
float* reference = (float*) malloc(mem_size_C);
MatrixMulOnHost(h_A, h_B, reference, WB);
gettimeofday(&etime,0);
hosttime = (etime.tv_sec-stime.tv_sec)*1000000LL + etime.tv_usec-stime.tv_usec;
//printf("host: %lld\ncuda: %lld\ncuda, w/copy: %lld\n", hosttime, cudatime, ctime);
gettimeofday(&totaletime,0);
totaltime = (totaletime.tv_sec-totalstime.tv_sec)*1000000LL + totaletime.tv_usec-totalstime.tv_usec;
*/
// clean up memory
free(h_A);
free(h_B);
//free(h_C);
//free(reference);
//cudaFree(d_A);
//cudaFree(d_B);
//cudaFree(d_C);
//cudaThreadExit();
/* printf("Total Time: %lld\n",totaltime );
printf("Initialization Time: %lld\n",inittime);
printf("Copy Time: %lld\n",ctime-cudatime);
printf("Parallel Time: %lld\n",cudatime);
printf("Host Time: %lld\n", hosttime);
printf("Tile Parallel Time: %lld\n",cudatiletime);
printf("Sum %lld\n", inittime+ctime+hosttime+cudatiletime);*/
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
// Thread block sizes
#define BLOCK_SIZE 4096
#define TILE_WIDTH 4
// Matrix dimensions
// (chosen as multiples of the thread block size for simplicity)
#define MATRIX_SIZE 1* BLOCK_SIZE
#define WA (MATRIX_SIZE) // Matrix A width
#define HA (MATRIX_SIZE) // Matrix A height
#define WB (MATRIX_SIZE) // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Allocates a matrix with random float entries.
void randomInit(float* data, int size)
{
for (int i = 0; i < size; ++i)
data[i] = rand() / (float)RAND_MAX;
}
void printOutput(float *C, char a){
int i=0;
printf("Printing %c\n", a);
for(i=0;i<100;i++){
printf("%f\t", *C++);
}
}
__global__ void MatrixMulKernel(float* Md, float* Nd, float* Pd, int Width)
{
// Calculate the row index of the Pd element and M
int Row = blockIdx.y*BLOCK_SIZE + threadIdx.y;
// Calculate the column idenx of Pd and N
int Col = blockIdx.x*BLOCK_SIZE + threadIdx.x;
float Pvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k)
Pvalue += Md[Row*Width+k] * Nd[k*Width+Col];
Pd[Row*Width+Col] = Pvalue;
}
__global__ void MatrixMulKernelTiled(float* Md, float* Nd, float* Pd, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
void MatrixMulOnHost(float* M, float* N, float* P, int Width)
{
for (int i = 0; i < Width; ++i)
for (int j = 0; j < Width; ++j) {
double sum = 0;
for (int k = 0; k < Width; ++k) {
double a = M[i * Width + k];
double b = N[k * Width + j];
sum += a * b;
}
P[i * Width + j] = sum;
}
}
float runMatrixWithOutShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B)
{
hipEvent_t start, stop;
hipEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
char a='a',b='b',c='c';
printOutput(h_A,a);
printOutput(h_B,b);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventCreate(&startCopyHtoD);
hipEventCreate(&stopCopyHtoD);
hipEventCreate(&startCopyDtoH);
hipEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
hipMalloc((void**) &d_A, mem_size_A);
float* d_B;
hipMalloc((void**) &d_B, mem_size_B);
hipEventRecord(startCopyHtoD);
// copy host memory to device
hipMemcpy(d_A, h_A, mem_size_A,hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, mem_size_B,hipMemcpyHostToDevice);
hipEventRecord(stopCopyHtoD);
hipEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
// setup execution parameters
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
hipEventRecord(start);
// execute the kernel
MatrixMulKernel<<< grid, threads >>>(d_A, d_B, d_C, WB);
hipEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
hipEventRecord(startCopyDtoH);
// copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C,hipMemcpyDeviceToHost);
hipEventRecord(stopCopyDtoH);
hipEventSynchronize(stop);
hipEventSynchronize(stopCopyDtoH);
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
hipEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
hipEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
hipEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
float runMatrixWithShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B){
hipEvent_t start, stop;
hipEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventCreate(&startCopyHtoD);
hipEventCreate(&stopCopyHtoD);
hipEventCreate(&startCopyDtoH);
hipEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
hipMalloc((void**) &d_A, mem_size_A);
float* d_B;
hipMalloc((void**) &d_B, mem_size_B);
hipEventRecord(startCopyHtoD);
// copy host memory to device
hipMemcpy(d_A, h_A, mem_size_A,hipMemcpyHostToDevice) ;
hipMemcpy(d_B, h_B, mem_size_B,hipMemcpyHostToDevice);
hipEventRecord(stopCopyHtoD);
hipEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
dim3 dimThreads(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(WC / dimThreads.x, HA / dimThreads.y);
hipEventRecord(start);
MatrixMulKernelTiled<<<dimGrid, dimThreads>>>(d_A, d_B, d_C,WB);
hipEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
hipEventRecord(startCopyDtoH);
// copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C,hipMemcpyDeviceToHost);
hipEventRecord(stopCopyDtoH);
hipEventSynchronize(stop);
hipEventSynchronize(stopCopyDtoH);
char c = 'c';
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
hipEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
hipEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
hipEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
int main()
{
/*long long ctime,cudatime,cudatiletime,hosttime,inittime,totaltime;
struct timeval stime,stime2,etime, etime2,initstime,initetime,totalstime,totaletime,tilestime,tileetime;
gettimeofday(&totalstime,0);
gettimeofday(&initstime,0);
*/
printf("Matrix Size =%dX%d \n",MATRIX_SIZE,MATRIX_SIZE);
printf("Tile Width = %dX%d\n",TILE_WIDTH,TILE_WIDTH);
hipEvent_t startInit, stopInit;
hipEventCreate(&startInit);
hipEventCreate(&stopInit);
hipEventRecord(startInit);
srand(2006);
// allocate host memory for matrices A and B
unsigned int size_A = WA * HA;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
hipEventRecord(stopInit);
float initTime = 0;
hipEventElapsedTime(&initTime, startInit, stopInit);
printf("Init Time: %f\n", initTime);
/*----------------PARALLEL EXECUTION BEGINS HERE ----------------------------*/
printf("Starting Without Shared Memory\n\n");
float matTime = runMatrixWithOutShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time No TILING: %f\n\n", matTime);
/*------------------PARALLEL EXECUTION ENDS HERE ----------------------------*/
/* -----------------TILING EXECUTION BEGINS HERE-----------------------------*/
printf("Starting With Shared Memory\n\n");
float matTimeWithTile = runMatrixWithShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time With TILING: %f\n\n", matTimeWithTile);
/*------------------------------ TILING ENDS HERE ---------------------------------*/
/*
gettimeofday(&stime,0);
// compute reference solution
float* reference = (float*) malloc(mem_size_C);
MatrixMulOnHost(h_A, h_B, reference, WB);
gettimeofday(&etime,0);
hosttime = (etime.tv_sec-stime.tv_sec)*1000000LL + etime.tv_usec-stime.tv_usec;
//printf("host: %lld\ncuda: %lld\ncuda, w/copy: %lld\n", hosttime, cudatime, ctime);
gettimeofday(&totaletime,0);
totaltime = (totaletime.tv_sec-totalstime.tv_sec)*1000000LL + totaletime.tv_usec-totalstime.tv_usec;
*/
// clean up memory
free(h_A);
free(h_B);
//free(h_C);
//free(reference);
//cudaFree(d_A);
//cudaFree(d_B);
//cudaFree(d_C);
//cudaThreadExit();
/* printf("Total Time: %lld\n",totaltime );
printf("Initialization Time: %lld\n",inittime);
printf("Copy Time: %lld\n",ctime-cudatime);
printf("Parallel Time: %lld\n",cudatime);
printf("Host Time: %lld\n", hosttime);
printf("Tile Parallel Time: %lld\n",cudatiletime);
printf("Sum %lld\n", inittime+ctime+hosttime+cudatiletime);*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
// Thread block sizes
#define BLOCK_SIZE 4096
#define TILE_WIDTH 4
// Matrix dimensions
// (chosen as multiples of the thread block size for simplicity)
#define MATRIX_SIZE 1* BLOCK_SIZE
#define WA (MATRIX_SIZE) // Matrix A width
#define HA (MATRIX_SIZE) // Matrix A height
#define WB (MATRIX_SIZE) // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Allocates a matrix with random float entries.
void randomInit(float* data, int size)
{
for (int i = 0; i < size; ++i)
data[i] = rand() / (float)RAND_MAX;
}
void printOutput(float *C, char a){
int i=0;
printf("Printing %c\n", a);
for(i=0;i<100;i++){
printf("%f\t", *C++);
}
}
__global__ void MatrixMulKernel(float* Md, float* Nd, float* Pd, int Width)
{
// Calculate the row index of the Pd element and M
int Row = blockIdx.y*BLOCK_SIZE + threadIdx.y;
// Calculate the column idenx of Pd and N
int Col = blockIdx.x*BLOCK_SIZE + threadIdx.x;
float Pvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k)
Pvalue += Md[Row*Width+k] * Nd[k*Width+Col];
Pd[Row*Width+Col] = Pvalue;
}
__global__ void MatrixMulKernelTiled(float* Md, float* Nd, float* Pd, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
void MatrixMulOnHost(float* M, float* N, float* P, int Width)
{
for (int i = 0; i < Width; ++i)
for (int j = 0; j < Width; ++j) {
double sum = 0;
for (int k = 0; k < Width; ++k) {
double a = M[i * Width + k];
double b = N[k * Width + j];
sum += a * b;
}
P[i * Width + j] = sum;
}
}
float runMatrixWithOutShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B)
{
hipEvent_t start, stop;
hipEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
char a='a',b='b',c='c';
printOutput(h_A,a);
printOutput(h_B,b);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventCreate(&startCopyHtoD);
hipEventCreate(&stopCopyHtoD);
hipEventCreate(&startCopyDtoH);
hipEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
hipMalloc((void**) &d_A, mem_size_A);
float* d_B;
hipMalloc((void**) &d_B, mem_size_B);
hipEventRecord(startCopyHtoD);
// copy host memory to device
hipMemcpy(d_A, h_A, mem_size_A,hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, mem_size_B,hipMemcpyHostToDevice);
hipEventRecord(stopCopyHtoD);
hipEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
// setup execution parameters
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
hipEventRecord(start);
// execute the kernel
MatrixMulKernel<<< grid, threads >>>(d_A, d_B, d_C, WB);
hipEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
hipEventRecord(startCopyDtoH);
// copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C,hipMemcpyDeviceToHost);
hipEventRecord(stopCopyDtoH);
hipEventSynchronize(stop);
hipEventSynchronize(stopCopyDtoH);
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
hipEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
hipEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
hipEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
float runMatrixWithShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B){
hipEvent_t start, stop;
hipEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventCreate(&startCopyHtoD);
hipEventCreate(&stopCopyHtoD);
hipEventCreate(&startCopyDtoH);
hipEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
hipMalloc((void**) &d_A, mem_size_A);
float* d_B;
hipMalloc((void**) &d_B, mem_size_B);
hipEventRecord(startCopyHtoD);
// copy host memory to device
hipMemcpy(d_A, h_A, mem_size_A,hipMemcpyHostToDevice) ;
hipMemcpy(d_B, h_B, mem_size_B,hipMemcpyHostToDevice);
hipEventRecord(stopCopyHtoD);
hipEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
dim3 dimThreads(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(WC / dimThreads.x, HA / dimThreads.y);
hipEventRecord(start);
MatrixMulKernelTiled<<<dimGrid, dimThreads>>>(d_A, d_B, d_C,WB);
hipEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
hipEventRecord(startCopyDtoH);
// copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C,hipMemcpyDeviceToHost);
hipEventRecord(stopCopyDtoH);
hipEventSynchronize(stop);
hipEventSynchronize(stopCopyDtoH);
char c = 'c';
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
hipEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
hipEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
hipEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
int main()
{
/*long long ctime,cudatime,cudatiletime,hosttime,inittime,totaltime;
struct timeval stime,stime2,etime, etime2,initstime,initetime,totalstime,totaletime,tilestime,tileetime;
gettimeofday(&totalstime,0);
gettimeofday(&initstime,0);
*/
printf("Matrix Size =%dX%d \n",MATRIX_SIZE,MATRIX_SIZE);
printf("Tile Width = %dX%d\n",TILE_WIDTH,TILE_WIDTH);
hipEvent_t startInit, stopInit;
hipEventCreate(&startInit);
hipEventCreate(&stopInit);
hipEventRecord(startInit);
srand(2006);
// allocate host memory for matrices A and B
unsigned int size_A = WA * HA;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
hipEventRecord(stopInit);
float initTime = 0;
hipEventElapsedTime(&initTime, startInit, stopInit);
printf("Init Time: %f\n", initTime);
/*----------------PARALLEL EXECUTION BEGINS HERE ----------------------------*/
printf("Starting Without Shared Memory\n\n");
float matTime = runMatrixWithOutShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time No TILING: %f\n\n", matTime);
/*------------------PARALLEL EXECUTION ENDS HERE ----------------------------*/
/* -----------------TILING EXECUTION BEGINS HERE-----------------------------*/
printf("Starting With Shared Memory\n\n");
float matTimeWithTile = runMatrixWithShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time With TILING: %f\n\n", matTimeWithTile);
/*------------------------------ TILING ENDS HERE ---------------------------------*/
/*
gettimeofday(&stime,0);
// compute reference solution
float* reference = (float*) malloc(mem_size_C);
MatrixMulOnHost(h_A, h_B, reference, WB);
gettimeofday(&etime,0);
hosttime = (etime.tv_sec-stime.tv_sec)*1000000LL + etime.tv_usec-stime.tv_usec;
//printf("host: %lld\ncuda: %lld\ncuda, w/copy: %lld\n", hosttime, cudatime, ctime);
gettimeofday(&totaletime,0);
totaltime = (totaletime.tv_sec-totalstime.tv_sec)*1000000LL + totaletime.tv_usec-totalstime.tv_usec;
*/
// clean up memory
free(h_A);
free(h_B);
//free(h_C);
//free(reference);
//cudaFree(d_A);
//cudaFree(d_B);
//cudaFree(d_C);
//cudaThreadExit();
/* printf("Total Time: %lld\n",totaltime );
printf("Initialization Time: %lld\n",inittime);
printf("Copy Time: %lld\n",ctime-cudatime);
printf("Parallel Time: %lld\n",cudatime);
printf("Host Time: %lld\n", hosttime);
printf("Tile Parallel Time: %lld\n",cudatiletime);
printf("Sum %lld\n", inittime+ctime+hosttime+cudatiletime);*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_or_b32 v5, s15, 12, v1
v_lshl_or_b32 v0, s14, 12, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v5, s2
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v4, v[1:2], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v4, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v5, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20MatrixMulKernelTiledPfS_S_i
.globl _Z20MatrixMulKernelTiledPfS_S_i
.p2align 8
.type _Z20MatrixMulKernelTiledPfS_S_i,@function
_Z20MatrixMulKernelTiledPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 2, v5
v_lshl_add_u32 v0, s14, 2, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 4
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 4, v5
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 64, v8
s_lshr_b32 s3, s3, 30
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 2
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
s_lshl_b32 s9, s8, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 16, v9
s_cmp_eq_u32 s9, 16
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB1_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20MatrixMulKernelTiledPfS_S_i
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20MatrixMulKernelTiledPfS_S_i, .Lfunc_end1-_Z20MatrixMulKernelTiledPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20MatrixMulKernelTiledPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20MatrixMulKernelTiledPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
// Thread block sizes
#define BLOCK_SIZE 4096
#define TILE_WIDTH 4
// Matrix dimensions
// (chosen as multiples of the thread block size for simplicity)
#define MATRIX_SIZE 1* BLOCK_SIZE
#define WA (MATRIX_SIZE) // Matrix A width
#define HA (MATRIX_SIZE) // Matrix A height
#define WB (MATRIX_SIZE) // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Allocates a matrix with random float entries.
void randomInit(float* data, int size)
{
for (int i = 0; i < size; ++i)
data[i] = rand() / (float)RAND_MAX;
}
void printOutput(float *C, char a){
int i=0;
printf("Printing %c\n", a);
for(i=0;i<100;i++){
printf("%f\t", *C++);
}
}
__global__ void MatrixMulKernel(float* Md, float* Nd, float* Pd, int Width)
{
// Calculate the row index of the Pd element and M
int Row = blockIdx.y*BLOCK_SIZE + threadIdx.y;
// Calculate the column idenx of Pd and N
int Col = blockIdx.x*BLOCK_SIZE + threadIdx.x;
float Pvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k)
Pvalue += Md[Row*Width+k] * Nd[k*Width+Col];
Pd[Row*Width+Col] = Pvalue;
}
__global__ void MatrixMulKernelTiled(float* Md, float* Nd, float* Pd, int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
void MatrixMulOnHost(float* M, float* N, float* P, int Width)
{
for (int i = 0; i < Width; ++i)
for (int j = 0; j < Width; ++j) {
double sum = 0;
for (int k = 0; k < Width; ++k) {
double a = M[i * Width + k];
double b = N[k * Width + j];
sum += a * b;
}
P[i * Width + j] = sum;
}
}
float runMatrixWithOutShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B)
{
hipEvent_t start, stop;
hipEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
char a='a',b='b',c='c';
printOutput(h_A,a);
printOutput(h_B,b);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventCreate(&startCopyHtoD);
hipEventCreate(&stopCopyHtoD);
hipEventCreate(&startCopyDtoH);
hipEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
hipMalloc((void**) &d_A, mem_size_A);
float* d_B;
hipMalloc((void**) &d_B, mem_size_B);
hipEventRecord(startCopyHtoD);
// copy host memory to device
hipMemcpy(d_A, h_A, mem_size_A,hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, mem_size_B,hipMemcpyHostToDevice);
hipEventRecord(stopCopyHtoD);
hipEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
// setup execution parameters
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
hipEventRecord(start);
// execute the kernel
MatrixMulKernel<<< grid, threads >>>(d_A, d_B, d_C, WB);
hipEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
hipEventRecord(startCopyDtoH);
// copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C,hipMemcpyDeviceToHost);
hipEventRecord(stopCopyDtoH);
hipEventSynchronize(stop);
hipEventSynchronize(stopCopyDtoH);
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
hipEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
hipEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
hipEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
float runMatrixWithShared(float *h_A, float *h_B, unsigned int mem_size_A, unsigned int mem_size_B){
hipEvent_t start, stop;
hipEvent_t startCopyHtoD, startCopyDtoH, stopCopyHtoD, stopCopyDtoH;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventCreate(&startCopyHtoD);
hipEventCreate(&stopCopyHtoD);
hipEventCreate(&startCopyDtoH);
hipEventCreate(&stopCopyDtoH);
// allocate device memory
float* d_A;
hipMalloc((void**) &d_A, mem_size_A);
float* d_B;
hipMalloc((void**) &d_B, mem_size_B);
hipEventRecord(startCopyHtoD);
// copy host memory to device
hipMemcpy(d_A, h_A, mem_size_A,hipMemcpyHostToDevice) ;
hipMemcpy(d_B, h_B, mem_size_B,hipMemcpyHostToDevice);
hipEventRecord(stopCopyHtoD);
hipEventSynchronize(stopCopyHtoD);
// allocate device memory for result
unsigned int size_C = WC * HC;
unsigned int mem_size_C = sizeof(float) * size_C;
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
dim3 dimThreads(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(WC / dimThreads.x, HA / dimThreads.y);
hipEventRecord(start);
MatrixMulKernelTiled<<<dimGrid, dimThreads>>>(d_A, d_B, d_C,WB);
hipEventRecord(stop);
// allocate host memory for the result
float* h_C = (float*) malloc(mem_size_C);
hipEventRecord(startCopyDtoH);
// copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C,hipMemcpyDeviceToHost);
hipEventRecord(stopCopyDtoH);
hipEventSynchronize(stop);
hipEventSynchronize(stopCopyDtoH);
char c = 'c';
printOutput(h_C,c);
float copyHtoD = 0;
float copyDtoH = 0;
float kernelRunTime = 0;
hipEventElapsedTime(©DtoH, startCopyDtoH, stopCopyDtoH);
hipEventElapsedTime(©HtoD, startCopyHtoD, stopCopyHtoD);
hipEventElapsedTime(&kernelRunTime, start, stop);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("Copy Time From H To D: %f\n",copyHtoD);
printf("Copy Time From D To H: %f\n",copyDtoH);
return kernelRunTime;
}
int main()
{
/*long long ctime,cudatime,cudatiletime,hosttime,inittime,totaltime;
struct timeval stime,stime2,etime, etime2,initstime,initetime,totalstime,totaletime,tilestime,tileetime;
gettimeofday(&totalstime,0);
gettimeofday(&initstime,0);
*/
printf("Matrix Size =%dX%d \n",MATRIX_SIZE,MATRIX_SIZE);
printf("Tile Width = %dX%d\n",TILE_WIDTH,TILE_WIDTH);
hipEvent_t startInit, stopInit;
hipEventCreate(&startInit);
hipEventCreate(&stopInit);
hipEventRecord(startInit);
srand(2006);
// allocate host memory for matrices A and B
unsigned int size_A = WA * HA;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
hipEventRecord(stopInit);
float initTime = 0;
hipEventElapsedTime(&initTime, startInit, stopInit);
printf("Init Time: %f\n", initTime);
/*----------------PARALLEL EXECUTION BEGINS HERE ----------------------------*/
printf("Starting Without Shared Memory\n\n");
float matTime = runMatrixWithOutShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time No TILING: %f\n\n", matTime);
/*------------------PARALLEL EXECUTION ENDS HERE ----------------------------*/
/* -----------------TILING EXECUTION BEGINS HERE-----------------------------*/
printf("Starting With Shared Memory\n\n");
float matTimeWithTile = runMatrixWithShared(h_A,h_B,mem_size_A,mem_size_B);
printf("Mat Time With TILING: %f\n\n", matTimeWithTile);
/*------------------------------ TILING ENDS HERE ---------------------------------*/
/*
gettimeofday(&stime,0);
// compute reference solution
float* reference = (float*) malloc(mem_size_C);
MatrixMulOnHost(h_A, h_B, reference, WB);
gettimeofday(&etime,0);
hosttime = (etime.tv_sec-stime.tv_sec)*1000000LL + etime.tv_usec-stime.tv_usec;
//printf("host: %lld\ncuda: %lld\ncuda, w/copy: %lld\n", hosttime, cudatime, ctime);
gettimeofday(&totaletime,0);
totaltime = (totaletime.tv_sec-totalstime.tv_sec)*1000000LL + totaletime.tv_usec-totalstime.tv_usec;
*/
// clean up memory
free(h_A);
free(h_B);
//free(h_C);
//free(reference);
//cudaFree(d_A);
//cudaFree(d_B);
//cudaFree(d_C);
//cudaThreadExit();
/* printf("Total Time: %lld\n",totaltime );
printf("Initialization Time: %lld\n",inittime);
printf("Copy Time: %lld\n",ctime-cudatime);
printf("Parallel Time: %lld\n",cudatime);
printf("Host Time: %lld\n", hosttime);
printf("Tile Parallel Time: %lld\n",cudatiletime);
printf("Sum %lld\n", inittime+ctime+hosttime+cudatiletime);*/
} | .text
.file "tile_test.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10randomInitPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10randomInitPfi, .Lfunc_end0-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl _Z11printOutputPfc # -- Begin function _Z11printOutputPfc
.p2align 4, 0x90
.type _Z11printOutputPfc,@function
_Z11printOutputPfc: # @_Z11printOutputPfc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpl $100, %r14d
jne .LBB1_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11printOutputPfc, .Lfunc_end1-_Z11printOutputPfc
.cfi_endproc
# -- End function
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end2-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__MatrixMulKernelTiledPfS_S_i # -- Begin function _Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.p2align 4, 0x90
.type _Z35__device_stub__MatrixMulKernelTiledPfS_S_i,@function
_Z35__device_stub__MatrixMulKernelTiledPfS_S_i: # @_Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20MatrixMulKernelTiledPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z35__device_stub__MatrixMulKernelTiledPfS_S_i, .Lfunc_end3-_Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.cfi_endproc
# -- End function
.globl _Z15MatrixMulOnHostPfS_S_i # -- Begin function _Z15MatrixMulOnHostPfS_S_i
.p2align 4, 0x90
.type _Z15MatrixMulOnHostPfS_S_i,@function
_Z15MatrixMulOnHostPfS_S_i: # @_Z15MatrixMulOnHostPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_8
# %bb.1: # %.preheader28.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_2: # %.preheader28
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
# Child Loop BB4_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # %.preheader
# Parent Loop BB4_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_4 Depth 3
xorpd %xmm0, %xmm0
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# Parent Loop BB4_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r12), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
mulsd %xmm1, %xmm2
addsd %xmm2, %xmm0
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB4_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB4_3 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB4_3
# %bb.6: # %._crit_edge32
# in Loop: Header=BB4_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB4_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB4_8: # %._crit_edge34
retq
.Lfunc_end4:
.size _Z15MatrixMulOnHostPfS_S_i, .Lfunc_end4-_Z15MatrixMulOnHostPfS_S_i
.cfi_endproc
# -- End function
.globl _Z22runMatrixWithOutSharedPfS_jj # -- Begin function _Z22runMatrixWithOutSharedPfS_jj
.p2align 4, 0x90
.type _Z22runMatrixWithOutSharedPfS_jj,@function
_Z22runMatrixWithOutSharedPfS_jj: # @_Z22runMatrixWithOutSharedPfS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r14
xorl %r12d, %r12d
movl $.L.str, %edi
movl $97, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpl $100, %r12d
jne .LBB5_1
# %bb.2: # %_Z11printOutputPfc.exit
xorl %r12d, %r12d
movl $.L.str, %edi
movl $98, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB5_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpl $100, %r12d
jne .LBB5_3
# %bb.4: # %_Z11printOutputPfc.exit26
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl %r15d, %r15d
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl %ebp, %r12d
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17592186048512, %rdx # imm = 0x100000001000
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movl $4096, 84(%rsp) # imm = 0x1000
leaq 184(%rsp), %rax
movq %rax, 112(%rsp)
leaq 176(%rsp), %rax
movq %rax, 120(%rsp)
leaq 168(%rsp), %rax
movq %rax, 128(%rsp)
leaq 84(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
movq 48(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rdi
callq hipEventSynchronize
movl $.L.str, %edi
movl $99, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB5_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpl $100, %r14d
jne .LBB5_7
# %bb.8: # %_Z11printOutputPfc.exit30
movl $0, 112(%rsp)
movl $0, 72(%rsp)
movl $0, 56(%rsp)
movq 88(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 72(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 104(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss 72(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z22runMatrixWithOutSharedPfS_jj, .Lfunc_end5-_Z22runMatrixWithOutSharedPfS_jj
.cfi_endproc
# -- End function
.globl _Z19runMatrixWithSharedPfS_jj # -- Begin function _Z19runMatrixWithSharedPfS_jj
.p2align 4, 0x90
.type _Z19runMatrixWithSharedPfS_jj,@function
_Z19runMatrixWithSharedPfS_jj: # @_Z19runMatrixWithSharedPfS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r14
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl %r15d, %r15d
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl %ebp, %r12d
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17592186048512, %rdx # imm = 0x100000001000
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movl $4096, 84(%rsp) # imm = 0x1000
leaq 184(%rsp), %rax
movq %rax, 112(%rsp)
leaq 176(%rsp), %rax
movq %rax, 120(%rsp)
leaq 168(%rsp), %rax
movq %rax, 128(%rsp)
leaq 84(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20MatrixMulKernelTiledPfS_S_i, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movq 48(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rdi
callq hipEventSynchronize
movl $.L.str, %edi
movl $99, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB6_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpl $100, %r14d
jne .LBB6_3
# %bb.4: # %_Z11printOutputPfc.exit
movl $0, 112(%rsp)
movl $0, 72(%rsp)
movl $0, 56(%rsp)
movq 88(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 72(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 104(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss 72(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z19runMatrixWithSharedPfS_jj, .Lfunc_end6-_Z19runMatrixWithSharedPfS_jj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r15d, %r15d
movl $.L.str.4, %edi
movl $4096, %esi # imm = 0x1000
movl $4096, %edx # imm = 0x1000
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl $4, %esi
movl $4, %edx
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $2006, %edi # imm = 0x7D6
callq srand
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
.p2align 4, 0x90
.LBB7_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI7_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $16777216, %r15 # imm = 0x1000000
jne .LBB7_1
# %bb.2: # %.lr.ph.i20.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_3: # %.lr.ph.i20
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI7_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $16777216, %r15 # imm = 0x1000000
jne .LBB7_3
# %bb.4: # %_Z10randomInitPfi.exit24
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $0, 12(%rsp)
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
movq %r14, %rsi
movl $67108864, %edx # imm = 0x4000000
movl $67108864, %ecx # imm = 0x4000000
callq _Z22runMatrixWithOutSharedPfS_jj
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
movq %r14, %rsi
movl $67108864, %edx # imm = 0x4000000
movl $67108864, %ecx # imm = 0x4000000
callq _Z19runMatrixWithSharedPfS_jj
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20MatrixMulKernelTiledPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Printing %c\n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f\t"
.size .L.str.1, 4
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type _Z20MatrixMulKernelTiledPfS_S_i,@object # @_Z20MatrixMulKernelTiledPfS_S_i
.globl _Z20MatrixMulKernelTiledPfS_S_i
.p2align 3, 0x0
_Z20MatrixMulKernelTiledPfS_S_i:
.quad _Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.size _Z20MatrixMulKernelTiledPfS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Copy Time From H To D: %f\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Copy Time From D To H: %f\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Matrix Size =%dX%d \n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tile Width = %dX%d\n"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Init Time: %f\n"
.size .L.str.6, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Mat Time No TILING: %f\n\n"
.size .L.str.8, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Mat Time With TILING: %f\n\n"
.size .L.str.10, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20MatrixMulKernelTiledPfS_S_i"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Starting Without Shared Memory\n"
.size .Lstr, 32
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Starting With Shared Memory\n"
.size .Lstr.1, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym _Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym _Z20MatrixMulKernelTiledPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005e919_00000000-6_tile_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Printing %c\n"
.LC2:
.string "%f\t"
.text
.globl _Z11printOutputPfc
.type _Z11printOutputPfc, @function
_Z11printOutputPfc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movsbl %sil, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 400(%rbx), %r12
leaq .LC2(%rip), %rbp
.L12:
addq $4, %rbx
pxor %xmm0, %xmm0
cvtss2sd -4(%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpq %rbx, %r12
jne .L12
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11printOutputPfc, .-_Z11printOutputPfc
.globl _Z15MatrixMulOnHostPfS_S_i
.type _Z15MatrixMulOnHostPfS_S_i, @function
_Z15MatrixMulOnHostPfS_S_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L23
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r11
movq %rdx, %r9
movl %ecx, %r12d
movslq %ecx, %rbx
leaq 0(,%rbx,4), %rcx
movq %rdi, %r10
leaq (%rdi,%rcx), %rsi
movl $0, %ebp
.L17:
movq %r11, %r8
movl $0, %edi
.L20:
movq %r8, %rdx
movq %r10, %rax
pxor %xmm1, %xmm1
.L18:
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
pxor %xmm2, %xmm2
cvtss2sd (%rdx), %xmm2
mulsd %xmm2, %xmm0
addsd %xmm0, %xmm1
addq $4, %rax
addq %rcx, %rdx
cmpq %rsi, %rax
jne .L18
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r9,%rdi,4)
addq $1, %rdi
addq $4, %r8
cmpq %rbx, %rdi
jne .L20
addl $1, %ebp
addq %rcx, %r9
addq %rcx, %r10
addq %rcx, %rsi
cmpl %ebp, %r12d
jne .L17
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z15MatrixMulOnHostPfS_S_i, .-_Z15MatrixMulOnHostPfS_S_i
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.section .rodata.str1.1
.LC5:
.string "Copy Time From H To D: %f\n"
.LC6:
.string "Copy Time From D To H: %f\n"
.text
.globl _Z22runMatrixWithOutSharedPfS_jj
.type _Z22runMatrixWithOutSharedPfS_jj, @function
_Z22runMatrixWithOutSharedPfS_jj:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $97, %esi
call _Z11printOutputPfc
movl $98, %esi
movq %r12, %rdi
call _Z11printOutputPfc
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl %ebp, %ebp
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %ebx, %ebx
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 88(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $4096, 96(%rsp)
movl $4096, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $67108864, %edx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $99, %esi
movq %rbx, %rdi
call _Z11printOutputPfc
movl $0x00000000, 12(%rsp)
movl $0x00000000, 16(%rsp)
movl $0x00000000, 20(%rsp)
leaq 16(%rsp), %rdi
movq 64(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 20(%rsp), %xmm0
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl $4096, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
jmp .L35
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z22runMatrixWithOutSharedPfS_jj, .-_Z22runMatrixWithOutSharedPfS_jj
.globl _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i
.type _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i, @function
_Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20MatrixMulKernelTiledPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i, .-_Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i
.globl _Z20MatrixMulKernelTiledPfS_S_i
.type _Z20MatrixMulKernelTiledPfS_S_i, @function
_Z20MatrixMulKernelTiledPfS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z20MatrixMulKernelTiledPfS_S_i, .-_Z20MatrixMulKernelTiledPfS_S_i
.globl _Z19runMatrixWithSharedPfS_jj
.type _Z19runMatrixWithSharedPfS_jj, @function
_Z19runMatrixWithSharedPfS_jj:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl %ebp, %ebp
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %ebx, %ebx
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 88(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $4096, 96(%rsp)
movl $4096, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L49:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $67108864, %edx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $99, %esi
movq %rbx, %rdi
call _Z11printOutputPfc
movl $0x00000000, 12(%rsp)
movl $0x00000000, 16(%rsp)
movl $0x00000000, 20(%rsp)
leaq 16(%rsp), %rdi
movq 64(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 20(%rsp), %xmm0
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl $4096, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z45__device_stub__Z20MatrixMulKernelTiledPfS_S_iPfS_S_i
jmp .L49
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z19runMatrixWithSharedPfS_jj, .-_Z19runMatrixWithSharedPfS_jj
.section .rodata.str1.1
.LC7:
.string "Matrix Size =%dX%d \n"
.LC8:
.string "Tile Width = %dX%d\n"
.LC9:
.string "Init Time: %f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "Starting Without Shared Memory\n\n"
.section .rodata.str1.1
.LC11:
.string "Mat Time No TILING: %f\n\n"
.LC12:
.string "Starting With Shared Memory\n\n"
.LC13:
.string "Mat Time With TILING: %f\n\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $4096, %ecx
movl $4096, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4, %ecx
movl $4, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $2006, %edi
call srand@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %esi
movq %rbp, %rdi
call _Z10randomInitPfi
movl $16777216, %esi
movq %rbx, %rdi
call _Z10randomInitPfi
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z22runMatrixWithOutSharedPfS_jj
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z19runMatrixWithSharedPfS_jj
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z20MatrixMulKernelTiledPfS_S_i"
.section .rodata.str1.1
.LC15:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z20MatrixMulKernelTiledPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tile_test.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10randomInitPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10randomInitPfi, .Lfunc_end0-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl _Z11printOutputPfc # -- Begin function _Z11printOutputPfc
.p2align 4, 0x90
.type _Z11printOutputPfc,@function
_Z11printOutputPfc: # @_Z11printOutputPfc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpl $100, %r14d
jne .LBB1_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11printOutputPfc, .Lfunc_end1-_Z11printOutputPfc
.cfi_endproc
# -- End function
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end2-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__MatrixMulKernelTiledPfS_S_i # -- Begin function _Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.p2align 4, 0x90
.type _Z35__device_stub__MatrixMulKernelTiledPfS_S_i,@function
_Z35__device_stub__MatrixMulKernelTiledPfS_S_i: # @_Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20MatrixMulKernelTiledPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z35__device_stub__MatrixMulKernelTiledPfS_S_i, .Lfunc_end3-_Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.cfi_endproc
# -- End function
.globl _Z15MatrixMulOnHostPfS_S_i # -- Begin function _Z15MatrixMulOnHostPfS_S_i
.p2align 4, 0x90
.type _Z15MatrixMulOnHostPfS_S_i,@function
_Z15MatrixMulOnHostPfS_S_i: # @_Z15MatrixMulOnHostPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_8
# %bb.1: # %.preheader28.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_2: # %.preheader28
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
# Child Loop BB4_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # %.preheader
# Parent Loop BB4_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_4 Depth 3
xorpd %xmm0, %xmm0
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# Parent Loop BB4_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r12), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
mulsd %xmm1, %xmm2
addsd %xmm2, %xmm0
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB4_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB4_3 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB4_3
# %bb.6: # %._crit_edge32
# in Loop: Header=BB4_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB4_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB4_8: # %._crit_edge34
retq
.Lfunc_end4:
.size _Z15MatrixMulOnHostPfS_S_i, .Lfunc_end4-_Z15MatrixMulOnHostPfS_S_i
.cfi_endproc
# -- End function
.globl _Z22runMatrixWithOutSharedPfS_jj # -- Begin function _Z22runMatrixWithOutSharedPfS_jj
.p2align 4, 0x90
.type _Z22runMatrixWithOutSharedPfS_jj,@function
_Z22runMatrixWithOutSharedPfS_jj: # @_Z22runMatrixWithOutSharedPfS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r14
xorl %r12d, %r12d
movl $.L.str, %edi
movl $97, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpl $100, %r12d
jne .LBB5_1
# %bb.2: # %_Z11printOutputPfc.exit
xorl %r12d, %r12d
movl $.L.str, %edi
movl $98, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB5_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpl $100, %r12d
jne .LBB5_3
# %bb.4: # %_Z11printOutputPfc.exit26
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl %r15d, %r15d
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl %ebp, %r12d
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17592186048512, %rdx # imm = 0x100000001000
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movl $4096, 84(%rsp) # imm = 0x1000
leaq 184(%rsp), %rax
movq %rax, 112(%rsp)
leaq 176(%rsp), %rax
movq %rax, 120(%rsp)
leaq 168(%rsp), %rax
movq %rax, 128(%rsp)
leaq 84(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
movq 48(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rdi
callq hipEventSynchronize
movl $.L.str, %edi
movl $99, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB5_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpl $100, %r14d
jne .LBB5_7
# %bb.8: # %_Z11printOutputPfc.exit30
movl $0, 112(%rsp)
movl $0, 72(%rsp)
movl $0, 56(%rsp)
movq 88(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 72(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 104(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss 72(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z22runMatrixWithOutSharedPfS_jj, .Lfunc_end5-_Z22runMatrixWithOutSharedPfS_jj
.cfi_endproc
# -- End function
.globl _Z19runMatrixWithSharedPfS_jj # -- Begin function _Z19runMatrixWithSharedPfS_jj
.p2align 4, 0x90
.type _Z19runMatrixWithSharedPfS_jj,@function
_Z19runMatrixWithSharedPfS_jj: # @_Z19runMatrixWithSharedPfS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r14
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl %r15d, %r15d
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl %ebp, %r12d
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17592186048512, %rdx # imm = 0x100000001000
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movl $4096, 84(%rsp) # imm = 0x1000
leaq 184(%rsp), %rax
movq %rax, 112(%rsp)
leaq 176(%rsp), %rax
movq %rax, 120(%rsp)
leaq 168(%rsp), %rax
movq %rax, 128(%rsp)
leaq 84(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20MatrixMulKernelTiledPfS_S_i, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movq 48(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rdi
callq hipEventSynchronize
movl $.L.str, %edi
movl $99, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB6_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpl $100, %r14d
jne .LBB6_3
# %bb.4: # %_Z11printOutputPfc.exit
movl $0, 112(%rsp)
movl $0, 72(%rsp)
movl $0, 56(%rsp)
movq 88(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 72(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 104(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss 72(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z19runMatrixWithSharedPfS_jj, .Lfunc_end6-_Z19runMatrixWithSharedPfS_jj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r15d, %r15d
movl $.L.str.4, %edi
movl $4096, %esi # imm = 0x1000
movl $4096, %edx # imm = 0x1000
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl $4, %esi
movl $4, %edx
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $2006, %edi # imm = 0x7D6
callq srand
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
.p2align 4, 0x90
.LBB7_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI7_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $16777216, %r15 # imm = 0x1000000
jne .LBB7_1
# %bb.2: # %.lr.ph.i20.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_3: # %.lr.ph.i20
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI7_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $16777216, %r15 # imm = 0x1000000
jne .LBB7_3
# %bb.4: # %_Z10randomInitPfi.exit24
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $0, 12(%rsp)
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
movq %r14, %rsi
movl $67108864, %edx # imm = 0x4000000
movl $67108864, %ecx # imm = 0x4000000
callq _Z22runMatrixWithOutSharedPfS_jj
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
movq %r14, %rsi
movl $67108864, %edx # imm = 0x4000000
movl $67108864, %ecx # imm = 0x4000000
callq _Z19runMatrixWithSharedPfS_jj
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20MatrixMulKernelTiledPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Printing %c\n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f\t"
.size .L.str.1, 4
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type _Z20MatrixMulKernelTiledPfS_S_i,@object # @_Z20MatrixMulKernelTiledPfS_S_i
.globl _Z20MatrixMulKernelTiledPfS_S_i
.p2align 3, 0x0
_Z20MatrixMulKernelTiledPfS_S_i:
.quad _Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.size _Z20MatrixMulKernelTiledPfS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Copy Time From H To D: %f\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Copy Time From D To H: %f\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Matrix Size =%dX%d \n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tile Width = %dX%d\n"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Init Time: %f\n"
.size .L.str.6, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Mat Time No TILING: %f\n\n"
.size .L.str.8, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Mat Time With TILING: %f\n\n"
.size .L.str.10, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20MatrixMulKernelTiledPfS_S_i"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Starting Without Shared Memory\n"
.size .Lstr, 32
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Starting With Shared Memory\n"
.size .Lstr.1, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym _Z35__device_stub__MatrixMulKernelTiledPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym _Z20MatrixMulKernelTiledPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
int main()
{
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
int main()
{
} | .file "tmpxft_0013a3cc_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
int main()
{
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
int main()
{
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
int main()
{
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
int main()
{
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a3cc_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: genechng@gmail.com
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Adding two numbers in the device
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <stdio.h>
#include <iostream>
using namespace std;
// --------------------- CUDA KERNELS
// kernel function sum with three parameters
__global__ void sum(int a, int b, int *c)
{
*c = a + b;
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising host and device variables" << endl;
int c; // host variable
int a = 2;
int b = 7;
int *dev_c; // device variable
cout << "------------ allocate device memory dev_c" << endl;
// allocate dev_c memory in the device
// we need to return the summed value to the host for printing
// and thus the need to create a device variable.
cudaMalloc( (void**)&dev_c, sizeof(int) );
cout << "------------ calling kernel" << endl;
// sum 2 + 7 on the kernel, using just 1 block and 1 thread
sum<<<1,1>>>(a, b, dev_c);
cout << "------------ copy dev_c to c from device to host" << endl;
// once we have assigned the sum of 2 + 7 to dev_c, we need to
// bring it back to the host by using cudaMemcpy(destination, source, ...)
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
cout << "------------ display results" << endl;
printf( "%d + %d = %d\n", a, b, c);
// ---- FREE ALLOCATED KERNEL MEMORY
cudaFree( dev_c );
return 0;
} | code for sm_80
Function : _Z3sumiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: genechng@gmail.com
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Adding two numbers in the device
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <stdio.h>
#include <iostream>
using namespace std;
// --------------------- CUDA KERNELS
// kernel function sum with three parameters
__global__ void sum(int a, int b, int *c)
{
*c = a + b;
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising host and device variables" << endl;
int c; // host variable
int a = 2;
int b = 7;
int *dev_c; // device variable
cout << "------------ allocate device memory dev_c" << endl;
// allocate dev_c memory in the device
// we need to return the summed value to the host for printing
// and thus the need to create a device variable.
cudaMalloc( (void**)&dev_c, sizeof(int) );
cout << "------------ calling kernel" << endl;
// sum 2 + 7 on the kernel, using just 1 block and 1 thread
sum<<<1,1>>>(a, b, dev_c);
cout << "------------ copy dev_c to c from device to host" << endl;
// once we have assigned the sum of 2 + 7 to dev_c, we need to
// bring it back to the host by using cudaMemcpy(destination, source, ...)
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
cout << "------------ display results" << endl;
printf( "%d + %d = %d\n", a, b, c);
// ---- FREE ALLOCATED KERNEL MEMORY
cudaFree( dev_c );
return 0;
} | .file "tmpxft_000085dd_00000000-6_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3sumiiPiiiPi
.type _Z24__device_stub__Z3sumiiPiiiPi, @function
_Z24__device_stub__Z3sumiiPiiiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z3sumiiPiiiPi, .-_Z24__device_stub__Z3sumiiPiiiPi
.globl _Z3sumiiPi
.type _Z3sumiiPi, @function
_Z3sumiiPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3sumiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3sumiiPi, .-_Z3sumiiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "------------ initialising host and device variables"
.align 8
.LC1:
.string "------------ allocate device memory dev_c"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "------------ calling kernel"
.section .rodata.str1.8
.align 8
.LC3:
.string "------------ copy dev_c to c from device to host"
.section .rodata.str1.1
.LC4:
.string "------------ display results"
.LC5:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 28(%rsp), %r8d
movl $7, %ecx
movl $2, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3sumiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3sumiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: genechng@gmail.com
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Adding two numbers in the device
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <stdio.h>
#include <iostream>
using namespace std;
// --------------------- CUDA KERNELS
// kernel function sum with three parameters
__global__ void sum(int a, int b, int *c)
{
*c = a + b;
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising host and device variables" << endl;
int c; // host variable
int a = 2;
int b = 7;
int *dev_c; // device variable
cout << "------------ allocate device memory dev_c" << endl;
// allocate dev_c memory in the device
// we need to return the summed value to the host for printing
// and thus the need to create a device variable.
cudaMalloc( (void**)&dev_c, sizeof(int) );
cout << "------------ calling kernel" << endl;
// sum 2 + 7 on the kernel, using just 1 block and 1 thread
sum<<<1,1>>>(a, b, dev_c);
cout << "------------ copy dev_c to c from device to host" << endl;
// once we have assigned the sum of 2 + 7 to dev_c, we need to
// bring it back to the host by using cudaMemcpy(destination, source, ...)
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
cout << "------------ display results" << endl;
printf( "%d + %d = %d\n", a, b, c);
// ---- FREE ALLOCATED KERNEL MEMORY
cudaFree( dev_c );
return 0;
} | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: genechng@gmail.com
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Adding two numbers in the device
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
// --------------------- CUDA KERNELS
// kernel function sum with three parameters
__global__ void sum(int a, int b, int *c)
{
*c = a + b;
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising host and device variables" << endl;
int c; // host variable
int a = 2;
int b = 7;
int *dev_c; // device variable
cout << "------------ allocate device memory dev_c" << endl;
// allocate dev_c memory in the device
// we need to return the summed value to the host for printing
// and thus the need to create a device variable.
hipMalloc( (void**)&dev_c, sizeof(int) );
cout << "------------ calling kernel" << endl;
// sum 2 + 7 on the kernel, using just 1 block and 1 thread
sum<<<1,1>>>(a, b, dev_c);
cout << "------------ copy dev_c to c from device to host" << endl;
// once we have assigned the sum of 2 + 7 to dev_c, we need to
// bring it back to the host by using cudaMemcpy(destination, source, ...)
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
cout << "------------ display results" << endl;
printf( "%d + %d = %d\n", a, b, c);
// ---- FREE ALLOCATED KERNEL MEMORY
hipFree( dev_c );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: genechng@gmail.com
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Adding two numbers in the device
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
// --------------------- CUDA KERNELS
// kernel function sum with three parameters
__global__ void sum(int a, int b, int *c)
{
*c = a + b;
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising host and device variables" << endl;
int c; // host variable
int a = 2;
int b = 7;
int *dev_c; // device variable
cout << "------------ allocate device memory dev_c" << endl;
// allocate dev_c memory in the device
// we need to return the summed value to the host for printing
// and thus the need to create a device variable.
hipMalloc( (void**)&dev_c, sizeof(int) );
cout << "------------ calling kernel" << endl;
// sum 2 + 7 on the kernel, using just 1 block and 1 thread
sum<<<1,1>>>(a, b, dev_c);
cout << "------------ copy dev_c to c from device to host" << endl;
// once we have assigned the sum of 2 + 7 to dev_c, we need to
// bring it back to the host by using cudaMemcpy(destination, source, ...)
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
cout << "------------ display results" << endl;
printf( "%d + %d = %d\n", a, b, c);
// ---- FREE ALLOCATED KERNEL MEMORY
hipFree( dev_c );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumiiPi
.globl _Z3sumiiPi
.p2align 8
.type _Z3sumiiPi,@function
_Z3sumiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumiiPi, .Lfunc_end0-_Z3sumiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3sumiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: genechng@gmail.com
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Adding two numbers in the device
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
// --------------------- CUDA KERNELS
// kernel function sum with three parameters
__global__ void sum(int a, int b, int *c)
{
*c = a + b;
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising host and device variables" << endl;
int c; // host variable
int a = 2;
int b = 7;
int *dev_c; // device variable
cout << "------------ allocate device memory dev_c" << endl;
// allocate dev_c memory in the device
// we need to return the summed value to the host for printing
// and thus the need to create a device variable.
hipMalloc( (void**)&dev_c, sizeof(int) );
cout << "------------ calling kernel" << endl;
// sum 2 + 7 on the kernel, using just 1 block and 1 thread
sum<<<1,1>>>(a, b, dev_c);
cout << "------------ copy dev_c to c from device to host" << endl;
// once we have assigned the sum of 2 + 7 to dev_c, we need to
// bring it back to the host by using cudaMemcpy(destination, source, ...)
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
cout << "------------ display results" << endl;
printf( "%d + %d = %d\n", a, b, c);
// ---- FREE ALLOCATED KERNEL MEMORY
hipFree( dev_c );
return 0;
} | .text
.file "sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__sumiiPi # -- Begin function _Z18__device_stub__sumiiPi
.p2align 4, 0x90
.type _Z18__device_stub__sumiiPi,@function
_Z18__device_stub__sumiiPi: # @_Z18__device_stub__sumiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3sumiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__sumiiPi, .Lfunc_end0-_Z18__device_stub__sumiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $51, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $41, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %eax
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3sumiiPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %eax
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%rbx)
je .LBB1_21
# %bb.20:
movzbl 67(%rbx), %eax
jmp .LBB1_22
.LBB1_21:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 16(%rsp), %ecx
movl $.L.str.5, %edi
movl $2, %esi
movl $7, %edx
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumiiPi,@object # @_Z3sumiiPi
.section .rodata,"a",@progbits
.globl _Z3sumiiPi
.p2align 3, 0x0
_Z3sumiiPi:
.quad _Z18__device_stub__sumiiPi
.size _Z3sumiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "------------ initialising host and device variables"
.size .L.str, 52
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "------------ allocate device memory dev_c"
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "------------ calling kernel"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "------------ copy dev_c to c from device to host"
.size .L.str.3, 49
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "------------ display results"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d + %d = %d\n"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumiiPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumiiPi
.globl _Z3sumiiPi
.p2align 8
.type _Z3sumiiPi,@function
_Z3sumiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumiiPi, .Lfunc_end0-_Z3sumiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3sumiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000085dd_00000000-6_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3sumiiPiiiPi
.type _Z24__device_stub__Z3sumiiPiiiPi, @function
_Z24__device_stub__Z3sumiiPiiiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z3sumiiPiiiPi, .-_Z24__device_stub__Z3sumiiPiiiPi
.globl _Z3sumiiPi
.type _Z3sumiiPi, @function
_Z3sumiiPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3sumiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3sumiiPi, .-_Z3sumiiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "------------ initialising host and device variables"
.align 8
.LC1:
.string "------------ allocate device memory dev_c"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "------------ calling kernel"
.section .rodata.str1.8
.align 8
.LC3:
.string "------------ copy dev_c to c from device to host"
.section .rodata.str1.1
.LC4:
.string "------------ display results"
.LC5:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 28(%rsp), %r8d
movl $7, %ecx
movl $2, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3sumiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3sumiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__sumiiPi # -- Begin function _Z18__device_stub__sumiiPi
.p2align 4, 0x90
.type _Z18__device_stub__sumiiPi,@function
_Z18__device_stub__sumiiPi: # @_Z18__device_stub__sumiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3sumiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__sumiiPi, .Lfunc_end0-_Z18__device_stub__sumiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $51, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $41, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %eax
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3sumiiPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %eax
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%rbx)
je .LBB1_21
# %bb.20:
movzbl 67(%rbx), %eax
jmp .LBB1_22
.LBB1_21:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 16(%rsp), %ecx
movl $.L.str.5, %edi
movl $2, %esi
movl $7, %edx
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumiiPi,@object # @_Z3sumiiPi
.section .rodata,"a",@progbits
.globl _Z3sumiiPi
.p2align 3, 0x0
_Z3sumiiPi:
.quad _Z18__device_stub__sumiiPi
.size _Z3sumiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "------------ initialising host and device variables"
.size .L.str, 52
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "------------ allocate device memory dev_c"
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "------------ calling kernel"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "------------ copy dev_c to c from device to host"
.size .L.str.3, 49
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "------------ display results"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d + %d = %d\n"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumiiPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void callOperation(int * a, int *b, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
res[tid] = a[tid] - b[tid];
if (res[tid] < 0)
{
res[tid] = 0;
}
} | code for sm_80
Function : _Z13callOperationPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R0, -R4, R3, RZ ; /* 0x0000000304007210 */
/* 0x004fc80007ffe1ff */
/*00e0*/ IMNMX R9, RZ, R0, !PT ; /* 0x00000000ff097217 */
/* 0x000fca0007800200 */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void callOperation(int * a, int *b, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
res[tid] = a[tid] - b[tid];
if (res[tid] < 0)
{
res[tid] = 0;
}
} | .file "tmpxft_00023ced_00000000-6_callOperation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13callOperationPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i
.globl _Z13callOperationPiS_S_i
.type _Z13callOperationPiS_S_i, @function
_Z13callOperationPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13callOperationPiS_S_i, .-_Z13callOperationPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13callOperationPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13callOperationPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void callOperation(int * a, int *b, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
res[tid] = a[tid] - b[tid];
if (res[tid] < 0)
{
res[tid] = 0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void callOperation(int * a, int *b, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
res[tid] = a[tid] - b[tid];
if (res[tid] < 0)
{
res[tid] = 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void callOperation(int * a, int *b, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
res[tid] = a[tid] - b[tid];
if (res[tid] < 0)
{
res[tid] = 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13callOperationPiS_S_i
.globl _Z13callOperationPiS_S_i
.p2align 8
.type _Z13callOperationPiS_S_i,@function
_Z13callOperationPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_max_i32_e32 v2, 0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13callOperationPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13callOperationPiS_S_i, .Lfunc_end0-_Z13callOperationPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13callOperationPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13callOperationPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void callOperation(int * a, int *b, int *res, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
res[tid] = a[tid] - b[tid];
if (res[tid] < 0)
{
res[tid] = 0;
}
} | .text
.file "callOperation.hip"
.globl _Z28__device_stub__callOperationPiS_S_i # -- Begin function _Z28__device_stub__callOperationPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__callOperationPiS_S_i,@function
_Z28__device_stub__callOperationPiS_S_i: # @_Z28__device_stub__callOperationPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13callOperationPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__callOperationPiS_S_i, .Lfunc_end0-_Z28__device_stub__callOperationPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13callOperationPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13callOperationPiS_S_i,@object # @_Z13callOperationPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13callOperationPiS_S_i
.p2align 3, 0x0
_Z13callOperationPiS_S_i:
.quad _Z28__device_stub__callOperationPiS_S_i
.size _Z13callOperationPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13callOperationPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__callOperationPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13callOperationPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13callOperationPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R0, -R4, R3, RZ ; /* 0x0000000304007210 */
/* 0x004fc80007ffe1ff */
/*00e0*/ IMNMX R9, RZ, R0, !PT ; /* 0x00000000ff097217 */
/* 0x000fca0007800200 */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13callOperationPiS_S_i
.globl _Z13callOperationPiS_S_i
.p2align 8
.type _Z13callOperationPiS_S_i,@function
_Z13callOperationPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_max_i32_e32 v2, 0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13callOperationPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13callOperationPiS_S_i, .Lfunc_end0-_Z13callOperationPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13callOperationPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13callOperationPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00023ced_00000000-6_callOperation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13callOperationPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i
.globl _Z13callOperationPiS_S_i
.type _Z13callOperationPiS_S_i, @function
_Z13callOperationPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13callOperationPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13callOperationPiS_S_i, .-_Z13callOperationPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13callOperationPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13callOperationPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "callOperation.hip"
.globl _Z28__device_stub__callOperationPiS_S_i # -- Begin function _Z28__device_stub__callOperationPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__callOperationPiS_S_i,@function
_Z28__device_stub__callOperationPiS_S_i: # @_Z28__device_stub__callOperationPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13callOperationPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__callOperationPiS_S_i, .Lfunc_end0-_Z28__device_stub__callOperationPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13callOperationPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13callOperationPiS_S_i,@object # @_Z13callOperationPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13callOperationPiS_S_i
.p2align 3, 0x0
_Z13callOperationPiS_S_i:
.quad _Z28__device_stub__callOperationPiS_S_i
.size _Z13callOperationPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13callOperationPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__callOperationPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13callOperationPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #pragma once
#include <curand.h>
#include <curand_kernel.h>
#include <ctime>
#include <stdio.h>
#include <utility>
#include <algorithm>
#include <numeric>
#include <iostream>
#include <chrono>
#include <iomanip>
#include <sstream>
#include <fstream>
typedef double(*FunctionCallback)(double);
namespace parallel {
__global__ void minMaxThread(int n, double *generatedNumbers, double *devMin, double *devMax, FunctionCallback func, double a, double b)
{
int i = threadIdx.x;
if (i < n)
{
double x = generatedNumbers[i] * (b - a) + a;
double value = func(x);
devMax[i] = ( value > devMax[i] ) ? value : devMax[i];
devMin[i] = ( value < devMin[i] ) ? value : devMin[i];
}
}
void minMaxKernelsStart(int n, double *generatedNumbers, double *devMin, double *devMax, FunctionCallback func, double a, double b)
{
int device_number = 0;
cudaDeviceProp iProp;
cudaGetDeviceProperties(&iProp, device_number);
curandGenerator_t gen;
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
curandSetPseudoRandomGeneratorSeed(gen, time(NULL));
curandGenerateUniformDouble(gen, generatedNumbers, n);
minMaxThread<<<(n + iProp.maxThreadsPerBlock - 1) / iProp.maxThreadsPerBlock, iProp.maxThreadsPerBlock>>>
(n, generatedNumbers, devMin, devMax, func, a, b);
cudaDeviceSynchronize();
}
std::pair<double, double> minMaxValue(int n, double a, double b, FunctionCallback func)
{
const int S = 1<<20; //2^20
double *generatedNumbers, *devMin, *devMax, *hostMin, *hostMax;
int loopSize, arraySize;
loopSize = (( n + S - 1) / S);
arraySize = S;
hostMin = (double *)malloc(S * sizeof(double));
hostMax = (double *)malloc(S * sizeof(double));
cudaMalloc((void**)&devMin, S * sizeof(double));
cudaMalloc((void**)&devMax, S * sizeof(double));
cudaMalloc((void**)&generatedNumbers, S * sizeof(double));
std::fill(hostMin, hostMin + arraySize, std::numeric_limits<double>::max());
std::fill(hostMax, hostMax + arraySize, std::numeric_limits<double>::lowest());
cudaMemcpy(devMin, hostMin, arraySize * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(devMax, hostMax, arraySize * sizeof(double), cudaMemcpyHostToDevice);
for (int i = 0; i < loopSize; i++)
{
minMaxKernelsStart(arraySize, generatedNumbers, devMin, devMax, func, a, b);
}
cudaMemcpy(hostMin, devMin, arraySize * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(hostMax, devMax, arraySize * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(generatedNumbers);
cudaFree(devMin);
cudaFree(devMax);
auto pair = std::make_pair( *std::min_element(hostMin, hostMin + arraySize),
*std::max_element(hostMax, hostMax + arraySize));
free(hostMin);
free(hostMax);
return pair;
}
__global__ void minMaxThreadV2(unsigned long seed, double a, double b, double *devMin, double *devMax, int size, int calculationsPerThread, FunctionCallback f)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size)
{
curandState_t state;
curand_init(seed, idx, 0, &state);
double x, y;
double min = devMin[idx];
double max = devMax[idx];
for(int i =0; i< calculationsPerThread; i++)
{
x = curand_uniform_double(&state) * (b - a) + a;
y = f(x);
max = ( y > max ) ? y : max;
min = ( y < min ) ? y : min;
}
devMin[idx] = min;
devMax[idx] = max;
}
}
std::pair<double, double> minMaxValueV2(int n, double a, double b, FunctionCallback func)
{
unsigned long cuRand_seed = time(NULL);
cudaDeviceProp iProp;
cudaGetDeviceProperties(&iProp, 0);
//int threads = 512;
//int blocks = 100;
int threads = iProp.maxThreadsPerBlock;
int blocks = iProp.multiProcessorCount;
int size = threads * blocks;
int sizeInBytes = size * sizeof(double);
double *devMin, *devMax, *hostMin, *hostMax;
cudaMalloc((void**)&devMin, sizeInBytes * sizeof(double));
cudaMalloc((void**)&devMax, sizeInBytes * sizeof(double));
hostMin = (double *)malloc(sizeInBytes);
hostMax = (double *)malloc(sizeInBytes);
std::fill(hostMin, hostMin + size, std::numeric_limits<double>::max());
std::fill(hostMax, hostMax + size, std::numeric_limits<double>::lowest());
cudaMemcpy(devMin, hostMin, sizeInBytes, cudaMemcpyHostToDevice);
cudaMemcpy(devMax, hostMax, sizeInBytes, cudaMemcpyHostToDevice);
int calculationsPerThread = (n + size -1) / size;
minMaxThreadV2<<<blocks, threads>>>(cuRand_seed, a, b, devMin, devMax, size, calculationsPerThread, func);
cudaDeviceSynchronize();
cudaMemcpy(hostMin, devMin, sizeInBytes, cudaMemcpyDeviceToHost);
cudaMemcpy(hostMax, devMax, sizeInBytes, cudaMemcpyDeviceToHost);
cudaFree(devMin);
cudaFree(devMax);
auto pair = std::make_pair( *std::min_element(hostMin, hostMin + size),
*std::max_element(hostMax, hostMax + size));
free(hostMin);
free(hostMax);
return pair;
}
void timeTestMinMaxPar(int m, int n, double a, double b, FunctionCallback f){
std::cout << std::setprecision(5);
std::chrono::duration<double> total = std::chrono::duration<double>::zero();
std::chrono::duration<double> diff;
std::chrono::high_resolution_clock::time_point start;
std::chrono::high_resolution_clock::time_point end;
std::ofstream file;
std::stringstream filename;
filename << "minMaxPar_" << m << '_' << n << ".txt";
n = 1 << n;
file.open(filename.str());
if (file.good() == true)
{
std::cout << "Testing parallel MinMax... for size: " << n << std::endl;
for(int i = 1; i <= m; ++i){
start = std::chrono::high_resolution_clock::now();
minMaxValue(n, a, b, f);
end = std::chrono::high_resolution_clock::now();
std::cout << "\r" << i * 100.0 / m << "% ";
std::cout << std::flush;
diff = end - start;
file << diff.count() << std::endl;
total += diff;
}
file.close();
}
std::cout << std::endl;
std::cout << "Parallel MinMax average time: " << total.count()/m << std::endl;
}
} | .file "tmpxft_000872a5_00000000-6_findMinMax.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4654:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4654:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__ZN8parallel12minMaxThreadEiPdS0_S0_PFddEddiPdS_S_PFddEdd
.type _Z57__device_stub__ZN8parallel12minMaxThreadEiPdS0_S0_PFddEddiPdS_S_PFddEdd, @function
_Z57__device_stub__ZN8parallel12minMaxThreadEiPdS0_S0_PFddEddiPdS_S_PFddEdd:
.LFB4676:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZN8parallel12minMaxThreadEiPdS0_S0_PFddEdd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4676:
.size _Z57__device_stub__ZN8parallel12minMaxThreadEiPdS0_S0_PFddEddiPdS_S_PFddEdd, .-_Z57__device_stub__ZN8parallel12minMaxThreadEiPdS0_S0_PFddEddiPdS_S_PFddEdd
.globl _ZN8parallel12minMaxThreadEiPdS0_S0_PFddEdd
.type _ZN8parallel12minMaxThreadEiPdS0_S0_PFddEdd, @function
_ZN8parallel12minMaxThreadEiPdS0_S0_PFddEdd:
.LFB4677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__ZN8parallel12minMaxThreadEiPdS0_S0_PFddEddiPdS_S_PFddEdd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4677:
.size _ZN8parallel12minMaxThreadEiPdS0_S0_PFddEdd, .-_ZN8parallel12minMaxThreadEiPdS0_S0_PFddEdd
.globl _ZN8parallel18minMaxKernelsStartEiPdS0_S0_PFddEdd
.type _ZN8parallel18minMaxKernelsStartEiPdS0_S0_PFddEdd, @function
_ZN8parallel18minMaxKernelsStartEiPdS0_S0_PFddEdd:
.LFB4633:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1088, %rsp
.cfi_def_cfa_offset 1136
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movsd %xmm0, (%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
leaq 16(%rsp), %rdi
movl $100, %esi
call curandCreateGenerator@PLT
movl $0, %edi
call time@PLT
movq %rax, %rsi
movq 16(%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
movslq %ebx, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call curandGenerateUniformDouble@PLT
movl 368(%rsp), %ecx
movl %ecx, 36(%rsp)
movl $1, 40(%rsp)
leal -1(%rcx,%rbx), %eax
cltd
idivl %ecx
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $1088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movsd 8(%rsp), %xmm1
movsd (%rsp), %xmm0
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z57__device_stub__ZN8parallel12minMaxThreadEiPdS0_S0_PFddEddiPdS_S_PFddEdd
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4633:
.size _ZN8parallel18minMaxKernelsStartEiPdS0_S0_PFddEdd, .-_ZN8parallel18minMaxKernelsStartEiPdS0_S0_PFddEdd
.globl _ZN8parallel11minMaxValueEiddPFddE
.type _ZN8parallel11minMaxValueEiddPFddE, @function
_ZN8parallel11minMaxValueEiddPFddE:
.LFB4635:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movsd %xmm0, 8(%rsp)
movsd %xmm1, 16(%rsp)
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 2097150(%rdi), %r13d
movl %edi, %eax
addl $1048575, %eax
cmovns %eax, %r13d
sarl $20, %r13d
movl $8388608, %edi
call malloc@PLT
movq %rax, %r15
movl $8388608, %edi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 40(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 8388608(%r15), %rbp
movq %r15, %rax
movsd .LC0(%rip), %xmm0
.L18:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rax, %rbp
jne .L18
movq 24(%rsp), %rax
leaq 8388608(%rax), %r12
movsd .LC1(%rip), %xmm0
.L19:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rax, %r12
jne .L19
movl $1, %ecx
movl $8388608, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8388608, %edx
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L20
movl $0, %ebx
.L21:
movsd 16(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movq %r14, %r8
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movl $1048576, %edi
call _ZN8parallel18minMaxKernelsStartEiPdS0_S0_PFddEdd
addl $1, %ebx
cmpl %ebx, %r13d
jg .L21
.L20:
movl $2, %ecx
movl $8388608, %edx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $8388608, %edx
movq 48(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdx
leaq 8(%rbx), %rax
.L23:
movsd (%rax), %xmm0
ucomisd (%rdx), %xmm0
cmova %rax, %rdx
addq $8, %rax
cmpq %rax, %r12
jne .L23
leaq 8(%r15), %rax
movq %r15, %rcx
.L25:
movsd (%rcx), %xmm0
ucomisd (%rax), %xmm0
cmova %rax, %rcx
addq $8, %rax
cmpq %rax, %rbp
jne .L25
movq (%rcx), %rbp
movq (%rdx), %rbx
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movq %rbp, %xmm0
movq %rbx, %xmm1
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4635:
.size _ZN8parallel11minMaxValueEiddPFddE, .-_ZN8parallel11minMaxValueEiddPFddE
.globl _Z58__device_stub__ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddEmddPdS_iiPFddE
.type _Z58__device_stub__ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddEmddPdS_iiPFddE, @function
_Z58__device_stub__ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddEmddPdS_iiPFddE:
.LFB4678:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
movsd %xmm1, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddE(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4678:
.size _Z58__device_stub__ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddEmddPdS_iiPFddE, .-_Z58__device_stub__ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddEmddPdS_iiPFddE
.globl _ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddE
.type _ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddE, @function
_ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddE:
.LFB4679:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddEmddPdS_iiPFddE
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4679:
.size _ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddE, .-_ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddE
.globl _ZN8parallel13minMaxValueV2EiddPFddE
.type _ZN8parallel13minMaxValueV2EiddPFddE, @function
_ZN8parallel13minMaxValueV2EiddPFddE:
.LFB4636:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movl %edi, 20(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 32(%rsp)
movq %rsi, 40(%rsp)
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movq %rax, 8(%rsp)
leaq 96(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %r15d
movl %r15d, 4(%rsp)
movl 484(%rsp), %eax
movl %eax, 16(%rsp)
imull %eax, %r15d
movslq %r15d, %rbx
leal 0(,%r15,8), %r14d
movslq %r14d, %r14
leaq 0(,%r14,8), %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
salq $3, %rbx
leaq 0(%r13,%rbx), %rbp
cmpq %r13, %rbp
je .L45
movq %r13, %rax
movsd .LC0(%rip), %xmm0
.L46:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rax, %rbp
jne .L46
.L45:
addq %r12, %rbx
cmpq %r12, %rbx
je .L47
movq %r12, %rax
movsd .LC1(%rip), %xmm0
.L48:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rax, %rbx
jne .L48
.L47:
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
movl %eax, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl 16(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L49:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r14, %rdx
movq 64(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
cmpq %r12, %rbx
je .L57
leaq 8(%r12), %rax
cmpq %rax, %rbx
je .L58
movq %r12, %rdx
.L52:
movsd (%rax), %xmm0
ucomisd (%rdx), %xmm0
cmova %rax, %rdx
addq $8, %rax
cmpq %rax, %rbx
jne .L52
.L50:
cmpq %r13, %rbp
je .L60
leaq 8(%r13), %rax
cmpq %rax, %rbp
je .L61
movq %r13, %rcx
.L55:
movsd (%rcx), %xmm0
ucomisd (%rax), %xmm0
cmova %rax, %rcx
addq $8, %rax
cmpq %rax, %rbp
jne .L55
.L53:
movq (%rcx), %rbp
movq (%rdx), %rbx
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L69
movq %rbp, %xmm0
movq %rbx, %xmm1
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movl 20(%rsp), %eax
leal -1(%r15,%rax), %eax
cltd
idivl %r15d
movq 40(%rsp), %r9
movl %eax, %r8d
movl %r15d, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movsd 32(%rsp), %xmm1
movsd 24(%rsp), %xmm0
movq 8(%rsp), %rdi
call _Z58__device_stub__ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddEmddPdS_iiPFddE
jmp .L49
.L57:
movq %r12, %rdx
jmp .L50
.L58:
movq %r12, %rdx
jmp .L50
.L60:
movq %r13, %rcx
jmp .L53
.L61:
movq %r13, %rcx
jmp .L53
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4636:
.size _ZN8parallel13minMaxValueV2EiddPFddE, .-_ZN8parallel13minMaxValueV2EiddPFddE
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddE"
.align 8
.LC3:
.string "_ZN8parallel12minMaxThreadEiPdS0_S0_PFddEdd"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "precalc_xorwow_matrix"
.LC5:
.string "precalc_xorwow_offset_matrix"
.LC6:
.string "mrg32k3aM1"
.LC7:
.string "mrg32k3aM2"
.LC8:
.string "mrg32k3aM1SubSeq"
.LC9:
.string "mrg32k3aM2SubSeq"
.LC10:
.string "mrg32k3aM1Seq"
.LC11:
.string "mrg32k3aM2Seq"
.LC12:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4681:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN8parallel14minMaxThreadV2EmddPdS0_iiPFddE(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN8parallel12minMaxThreadEiPdS0_S0_PFddEdd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4681:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC14:
.string "minMaxPar_"
.LC15:
.string ".txt"
.section .rodata.str1.8
.align 8
.LC16:
.string "Testing parallel MinMax... for size: "
.section .rodata.str1.1
.LC17:
.string "\r"
.LC19:
.string "% "
.section .rodata.str1.8
.align 8
.LC21:
.string "Parallel MinMax average time: "
.text
.globl _ZN8parallel17timeTestMinMaxParEiiddPFddE
.type _ZN8parallel17timeTestMinMaxParEiiddPFddE, @function
_ZN8parallel17timeTestMinMaxParEiiddPFddE:
.LFB4637:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4637
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1032, %rsp
.cfi_def_cfa_offset 1088
movl %edi, %r12d
movl %esi, %ebp
movsd %xmm0, 16(%rsp)
movsd %xmm1, 24(%rsp)
movq %rdx, 32(%rsp)
movq %fs:40, %rax
movq %rax, 1016(%rsp)
xorl %eax, %eax
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq $5, 8(%rdx,%rax)
leaq 496(%rsp), %rbx
leaq 744(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 744(%rsp)
movq $0, 960(%rsp)
movb $0, 968(%rsp)
movb $0, 969(%rsp)
movq $0, 976(%rsp)
movq $0, 984(%rsp)
movq $0, 992(%rsp)
movq $0, 1000(%rsp)
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 496(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 496(%rsp,%rax)
movq 496(%rsp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 496(%rsp)
leaq 40(%rax), %rax
movq %rax, 744(%rsp)
leaq 504(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 504(%rsp), %rsi
leaq 744(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
jmp .L138
.L128:
endbr64
movq %rax, %rbx
leaq 504(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L75:
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 496(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 496(%rsp,%rax)
.L76:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 744(%rsp)
leaq 744(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 1016(%rsp), %rax
subq %fs:40, %rax
je .L77
call __stack_chk_fail@PLT
.L127:
endbr64
movq %rax, %rbx
jmp .L75
.L126:
endbr64
movq %rax, %rbx
jmp .L76
.L77:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L138:
leaq 96(%rsp), %rbx
leaq 224(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 224(%rsp)
movq $0, 440(%rsp)
movb $0, 448(%rsp)
movb $0, 449(%rsp)
movq $0, 456(%rsp)
movq $0, 464(%rsp)
movq $0, 472(%rsp)
movq $0, 480(%rsp)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r14
movq %r14, 96(%rsp)
movq -24(%r14), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 96(%rsp,%rax)
movq $0, 104(%rsp)
movq 96(%rsp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB4:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE4:
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 112(%rsp)
movq -24(%rax), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 112(%rsp,%rax)
movq 112(%rsp), %rax
movq -24(%rax), %rax
leaq 112(%rsp,%rax), %rdi
movl $0, %esi
.LEHB5:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE5:
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 96(%rsp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 96(%rsp,%rax)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 96(%rsp)
leaq 80(%rax), %rax
movq %rax, 224(%rsp)
leaq -40(%rax), %rax
movq %rax, 112(%rsp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movq $0, 152(%rsp)
movq $0, 160(%rsp)
movq $0, 168(%rsp)
leaq 176(%rsp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 120(%rsp)
movl $24, 184(%rsp)
leaq 208(%rsp), %rax
movq %rax, 192(%rsp)
movq $0, 200(%rsp)
movb $0, 208(%rsp)
leaq 120(%rsp), %rsi
leaq 224(%rsp), %rdi
.LEHB6:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE6:
jmp .L139
.L129:
endbr64
movq %r14, 96(%rsp)
movq -24(%r14), %rdx
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 96(%rsp,%rdx)
movq $0, 104(%rsp)
movq %rax, %rbx
.L80:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 224(%rsp)
leaq 224(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L83:
leaq 496(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1016(%rsp), %rax
subq %fs:40, %rax
je .L118
call __stack_chk_fail@PLT
.L125:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 120(%rsp)
movq 192(%rsp), %rdi
leaq 208(%rsp), %rax
cmpq %rax, %rdi
je .L82
movq 208(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L82:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rbp
leaq 176(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
leaq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rbp, %rdi
call _ZNSdD2Ev@PLT
jmp .L80
.L124:
endbr64
movq %rax, %rbx
jmp .L80
.L139:
leaq 112(%rsp), %rdi
movl $10, %edx
leaq .LC14(%rip), %rsi
.LEHB7:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 112(%rsp), %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rbx
movb $95, 63(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L84
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L85:
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
jmp .L140
.L84:
movl $95, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L85
.L140:
movq %rax, %rdi
movl $4, %edx
leaq .LC15(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.LEHE7:
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movq $0, 72(%rsp)
movb $0, 80(%rsp)
movq 160(%rsp), %r8
testq %r8, %r8
je .L86
movq 144(%rsp), %rax
movq %r8, %rdx
cmpq %r8, %rax
cmovnb %rax, %r8
testq %rax, %rax
cmove %rdx, %r8
movq 152(%rsp), %rcx
leaq 64(%rsp), %rdi
subq %rcx, %r8
movl $0, %edx
movl $0, %esi
.LEHB8:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
jmp .L88
.L86:
leaq 192(%rsp), %rsi
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_assignERKS4_@PLT
.LEHE8:
.L88:
leaq 504(%rsp), %rdi
movl $16, %edx
movq 64(%rsp), %rsi
.LEHB9:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L141
movq 496(%rsp), %rax
movq -24(%rax), %rax
leaq 496(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L93
.L130:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L91:
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
jmp .L83
.L141:
movq 496(%rsp), %rax
movq -24(%rax), %rax
leaq 496(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE9:
.L93:
movq 64(%rsp), %rdi
leaq 80(%rsp), %rax
cmpq %rax, %rdi
je .L94
movq 80(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L94:
cmpl $0, 776(%rsp)
jne .L120
movl $37, %edx
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB10:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %eax
movl %ebp, %ecx
sall %cl, %eax
movl %eax, 44(%rsp)
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L142
cmpb $0, 56(%rbp)
je .L98
movzbl 67(%rbp), %esi
.L99:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L143
.L142:
movq 1016(%rsp), %rax
subq %fs:40, %rax
jne .L144
call _ZSt16__throw_bad_castv@PLT
.L144:
call __stack_chk_fail@PLT
.L98:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L99
.L143:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
testl %r12d, %r12d
jle .L121
movl $1, %ebp
movq $0x000000000, (%rsp)
leaq _ZSt4cout(%rip), %r13
jmp .L105
.L148:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC17(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC18(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r12d, %xmm1
divsd %xmm1, %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC19(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r13, %rdi
call _ZNSo5flushEv@PLT
subq %r15, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC20(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq 496(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L145
cmpb $0, 56(%r15)
je .L103
movzbl 67(%r15), %esi
.L104:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L146
.L145:
movq 1016(%rsp), %rax
subq %fs:40, %rax
jne .L147
call _ZSt16__throw_bad_castv@PLT
.L122:
endbr64
movq %rax, %rbx
jmp .L91
.L147:
call __stack_chk_fail@PLT
.L103:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L104
.L146:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movsd (%rsp), %xmm2
addsd 8(%rsp), %xmm2
movsd %xmm2, (%rsp)
addl $1, %ebp
cmpl %ebp, %r12d
jl .L100
.L105:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r15
movq 32(%rsp), %rsi
movsd 24(%rsp), %xmm1
movsd 16(%rsp), %xmm0
movl 44(%rsp), %edi
call _ZN8parallel11minMaxValueEiddPFddE
jmp .L148
.L121:
movq $0x000000000, (%rsp)
.L100:
leaq 504(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
testq %rax, %rax
jne .L95
movq 496(%rsp), %rax
movq -24(%rax), %rax
leaq 496(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L95
.L120:
movq $0x000000000, (%rsp)
.L95:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L149
cmpb $0, 56(%rbx)
je .L108
movzbl 67(%rbx), %esi
.L109:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
jmp .L150
.L149:
movq 1016(%rsp), %rax
subq %fs:40, %rax
jne .L151
call _ZSt16__throw_bad_castv@PLT
.L151:
call __stack_chk_fail@PLT
.L108:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L109
.L150:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $30, %edx
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %r12d, %xmm1
movsd (%rsp), %xmm0
divsd %xmm1, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L152
cmpb $0, 56(%rbp)
je .L112
movzbl 67(%rbp), %esi
.L113:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L153
.L152:
movq 1016(%rsp), %rax
subq %fs:40, %rax
jne .L154
call _ZSt16__throw_bad_castv@PLT
.L154:
call __stack_chk_fail@PLT
.L112:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L113
.L153:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE10:
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 96(%rsp)
leaq 80(%rax), %rax
movq %rax, 224(%rsp)
leaq -40(%rax), %rax
movq %rax, 112(%rsp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 120(%rsp)
movq 192(%rsp), %rdi
leaq 208(%rsp), %rax
cmpq %rax, %rdi
je .L114
movq 208(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L114:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 96(%rsp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 96(%rsp,%rax)
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 112(%rsp)
movq -24(%rax), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 112(%rsp,%rax)
movq %r14, 96(%rsp)
movq -24(%r14), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 96(%rsp,%rax)
movq $0, 104(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 224(%rsp)
leaq 224(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 496(%rsp)
leaq 40(%rax), %rax
movq %rax, 744(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 504(%rsp)
leaq 504(%rsp), %rdi
.LEHB11:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE11:
jmp .L116
.L131:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L116:
leaq 608(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 504(%rsp)
leaq 560(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 496(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 496(%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 744(%rsp)
leaq 744(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 1016(%rsp), %rax
subq %fs:40, %rax
jne .L155
addq $1032, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L123:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L91
.L118:
movq %rbx, %rdi
.LEHB12:
call _Unwind_Resume@PLT
.LEHE12:
.L155:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4637:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA4637:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4637-.LLSDATTD4637
.LLSDATTD4637:
.byte 0x1
.uleb128 .LLSDACSE4637-.LLSDACSB4637
.LLSDACSB4637:
.uleb128 .LEHB0-.LFB4637
.uleb128 .LEHE0-.LEHB0
.uleb128 .L126-.LFB4637
.uleb128 0
.uleb128 .LEHB1-.LFB4637
.uleb128 .LEHE1-.LEHB1
.uleb128 .L127-.LFB4637
.uleb128 0
.uleb128 .LEHB2-.LFB4637
.uleb128 .LEHE2-.LEHB2
.uleb128 .L128-.LFB4637
.uleb128 0
.uleb128 .LEHB3-.LFB4637
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4637
.uleb128 .LEHE4-.LEHB4
.uleb128 .L124-.LFB4637
.uleb128 0
.uleb128 .LEHB5-.LFB4637
.uleb128 .LEHE5-.LEHB5
.uleb128 .L129-.LFB4637
.uleb128 0
.uleb128 .LEHB6-.LFB4637
.uleb128 .LEHE6-.LEHB6
.uleb128 .L125-.LFB4637
.uleb128 0
.uleb128 .LEHB7-.LFB4637
.uleb128 .LEHE7-.LEHB7
.uleb128 .L122-.LFB4637
.uleb128 0
.uleb128 .LEHB8-.LFB4637
.uleb128 .LEHE8-.LEHB8
.uleb128 .L130-.LFB4637
.uleb128 0
.uleb128 .LEHB9-.LFB4637
.uleb128 .LEHE9-.LEHB9
.uleb128 .L123-.LFB4637
.uleb128 0
.uleb128 .LEHB10-.LFB4637
.uleb128 .LEHE10-.LEHB10
.uleb128 .L122-.LFB4637
.uleb128 0
.uleb128 .LEHB11-.LFB4637
.uleb128 .LEHE11-.LEHB11
.uleb128 .L131-.LFB4637
.uleb128 0x1
.uleb128 .LEHB12-.LFB4637
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.LLSDACSE4637:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4637:
.text
.size _ZN8parallel17timeTestMinMaxParEiiddPFddE, .-_ZN8parallel17timeTestMinMaxParEiiddPFddE
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1
.long 2146435071
.align 8
.LC1:
.long -1
.long -1048577
.align 8
.LC18:
.long 0
.long 1079574528
.align 8
.LC20:
.long 0
.long 1104006501
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #pragma once
#include <curand.h>
#include <curand_kernel.h>
#include <ctime>
#include <stdio.h>
#include <utility>
#include <algorithm>
#include <numeric>
#include <iostream>
#include <chrono>
#include <iomanip>
#include <sstream>
#include <fstream>
typedef double(*FunctionCallback)(double);
namespace parallel {
__global__ void minMaxThread(int n, double *generatedNumbers, double *devMin, double *devMax, FunctionCallback func, double a, double b)
{
int i = threadIdx.x;
if (i < n)
{
double x = generatedNumbers[i] * (b - a) + a;
double value = func(x);
devMax[i] = ( value > devMax[i] ) ? value : devMax[i];
devMin[i] = ( value < devMin[i] ) ? value : devMin[i];
}
}
void minMaxKernelsStart(int n, double *generatedNumbers, double *devMin, double *devMax, FunctionCallback func, double a, double b)
{
int device_number = 0;
cudaDeviceProp iProp;
cudaGetDeviceProperties(&iProp, device_number);
curandGenerator_t gen;
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
curandSetPseudoRandomGeneratorSeed(gen, time(NULL));
curandGenerateUniformDouble(gen, generatedNumbers, n);
minMaxThread<<<(n + iProp.maxThreadsPerBlock - 1) / iProp.maxThreadsPerBlock, iProp.maxThreadsPerBlock>>>
(n, generatedNumbers, devMin, devMax, func, a, b);
cudaDeviceSynchronize();
}
std::pair<double, double> minMaxValue(int n, double a, double b, FunctionCallback func)
{
const int S = 1<<20; //2^20
double *generatedNumbers, *devMin, *devMax, *hostMin, *hostMax;
int loopSize, arraySize;
loopSize = (( n + S - 1) / S);
arraySize = S;
hostMin = (double *)malloc(S * sizeof(double));
hostMax = (double *)malloc(S * sizeof(double));
cudaMalloc((void**)&devMin, S * sizeof(double));
cudaMalloc((void**)&devMax, S * sizeof(double));
cudaMalloc((void**)&generatedNumbers, S * sizeof(double));
std::fill(hostMin, hostMin + arraySize, std::numeric_limits<double>::max());
std::fill(hostMax, hostMax + arraySize, std::numeric_limits<double>::lowest());
cudaMemcpy(devMin, hostMin, arraySize * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(devMax, hostMax, arraySize * sizeof(double), cudaMemcpyHostToDevice);
for (int i = 0; i < loopSize; i++)
{
minMaxKernelsStart(arraySize, generatedNumbers, devMin, devMax, func, a, b);
}
cudaMemcpy(hostMin, devMin, arraySize * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(hostMax, devMax, arraySize * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(generatedNumbers);
cudaFree(devMin);
cudaFree(devMax);
auto pair = std::make_pair( *std::min_element(hostMin, hostMin + arraySize),
*std::max_element(hostMax, hostMax + arraySize));
free(hostMin);
free(hostMax);
return pair;
}
__global__ void minMaxThreadV2(unsigned long seed, double a, double b, double *devMin, double *devMax, int size, int calculationsPerThread, FunctionCallback f)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size)
{
curandState_t state;
curand_init(seed, idx, 0, &state);
double x, y;
double min = devMin[idx];
double max = devMax[idx];
for(int i =0; i< calculationsPerThread; i++)
{
x = curand_uniform_double(&state) * (b - a) + a;
y = f(x);
max = ( y > max ) ? y : max;
min = ( y < min ) ? y : min;
}
devMin[idx] = min;
devMax[idx] = max;
}
}
std::pair<double, double> minMaxValueV2(int n, double a, double b, FunctionCallback func)
{
unsigned long cuRand_seed = time(NULL);
cudaDeviceProp iProp;
cudaGetDeviceProperties(&iProp, 0);
//int threads = 512;
//int blocks = 100;
int threads = iProp.maxThreadsPerBlock;
int blocks = iProp.multiProcessorCount;
int size = threads * blocks;
int sizeInBytes = size * sizeof(double);
double *devMin, *devMax, *hostMin, *hostMax;
cudaMalloc((void**)&devMin, sizeInBytes * sizeof(double));
cudaMalloc((void**)&devMax, sizeInBytes * sizeof(double));
hostMin = (double *)malloc(sizeInBytes);
hostMax = (double *)malloc(sizeInBytes);
std::fill(hostMin, hostMin + size, std::numeric_limits<double>::max());
std::fill(hostMax, hostMax + size, std::numeric_limits<double>::lowest());
cudaMemcpy(devMin, hostMin, sizeInBytes, cudaMemcpyHostToDevice);
cudaMemcpy(devMax, hostMax, sizeInBytes, cudaMemcpyHostToDevice);
int calculationsPerThread = (n + size -1) / size;
minMaxThreadV2<<<blocks, threads>>>(cuRand_seed, a, b, devMin, devMax, size, calculationsPerThread, func);
cudaDeviceSynchronize();
cudaMemcpy(hostMin, devMin, sizeInBytes, cudaMemcpyDeviceToHost);
cudaMemcpy(hostMax, devMax, sizeInBytes, cudaMemcpyDeviceToHost);
cudaFree(devMin);
cudaFree(devMax);
auto pair = std::make_pair( *std::min_element(hostMin, hostMin + size),
*std::max_element(hostMax, hostMax + size));
free(hostMin);
free(hostMax);
return pair;
}
void timeTestMinMaxPar(int m, int n, double a, double b, FunctionCallback f){
std::cout << std::setprecision(5);
std::chrono::duration<double> total = std::chrono::duration<double>::zero();
std::chrono::duration<double> diff;
std::chrono::high_resolution_clock::time_point start;
std::chrono::high_resolution_clock::time_point end;
std::ofstream file;
std::stringstream filename;
filename << "minMaxPar_" << m << '_' << n << ".txt";
n = 1 << n;
file.open(filename.str());
if (file.good() == true)
{
std::cout << "Testing parallel MinMax... for size: " << n << std::endl;
for(int i = 1; i <= m; ++i){
start = std::chrono::high_resolution_clock::now();
minMaxValue(n, a, b, f);
end = std::chrono::high_resolution_clock::now();
std::cout << "\r" << i * 100.0 / m << "% ";
std::cout << std::flush;
diff = end - start;
file << diff.count() << std::endl;
total += diff;
}
file.close();
}
std::cout << std::endl;
std::cout << "Parallel MinMax average time: " << total.count()/m << std::endl;
}
} | #pragma once
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <ctime>
#include <stdio.h>
#include <utility>
#include <algorithm>
#include <numeric>
#include <iostream>
#include <chrono>
#include <iomanip>
#include <sstream>
#include <fstream>
typedef double(*FunctionCallback)(double);
namespace parallel {
__global__ void minMaxThread(int n, double *generatedNumbers, double *devMin, double *devMax, FunctionCallback func, double a, double b)
{
int i = threadIdx.x;
if (i < n)
{
double x = generatedNumbers[i] * (b - a) + a;
double value = func(x);
devMax[i] = ( value > devMax[i] ) ? value : devMax[i];
devMin[i] = ( value < devMin[i] ) ? value : devMin[i];
}
}
void minMaxKernelsStart(int n, double *generatedNumbers, double *devMin, double *devMax, FunctionCallback func, double a, double b)
{
int device_number = 0;
hipDeviceProp_t iProp;
hipGetDeviceProperties(&iProp, device_number);
hiprandGenerator_t gen;
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
hiprandSetPseudoRandomGeneratorSeed(gen, time(NULL));
hiprandGenerateUniformDouble(gen, generatedNumbers, n);
minMaxThread<<<(n + iProp.maxThreadsPerBlock - 1) / iProp.maxThreadsPerBlock, iProp.maxThreadsPerBlock>>>
(n, generatedNumbers, devMin, devMax, func, a, b);
hipDeviceSynchronize();
}
std::pair<double, double> minMaxValue(int n, double a, double b, FunctionCallback func)
{
const int S = 1<<20; //2^20
double *generatedNumbers, *devMin, *devMax, *hostMin, *hostMax;
int loopSize, arraySize;
loopSize = (( n + S - 1) / S);
arraySize = S;
hostMin = (double *)malloc(S * sizeof(double));
hostMax = (double *)malloc(S * sizeof(double));
hipMalloc((void**)&devMin, S * sizeof(double));
hipMalloc((void**)&devMax, S * sizeof(double));
hipMalloc((void**)&generatedNumbers, S * sizeof(double));
std::fill(hostMin, hostMin + arraySize, std::numeric_limits<double>::max());
std::fill(hostMax, hostMax + arraySize, std::numeric_limits<double>::lowest());
hipMemcpy(devMin, hostMin, arraySize * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(devMax, hostMax, arraySize * sizeof(double), hipMemcpyHostToDevice);
for (int i = 0; i < loopSize; i++)
{
minMaxKernelsStart(arraySize, generatedNumbers, devMin, devMax, func, a, b);
}
hipMemcpy(hostMin, devMin, arraySize * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(hostMax, devMax, arraySize * sizeof(double), hipMemcpyDeviceToHost);
hipFree(generatedNumbers);
hipFree(devMin);
hipFree(devMax);
auto pair = std::make_pair( *std::min_element(hostMin, hostMin + arraySize),
*std::max_element(hostMax, hostMax + arraySize));
free(hostMin);
free(hostMax);
return pair;
}
__global__ void minMaxThreadV2(unsigned long seed, double a, double b, double *devMin, double *devMax, int size, int calculationsPerThread, FunctionCallback f)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size)
{
hiprandState_t state;
hiprand_init(seed, idx, 0, &state);
double x, y;
double min = devMin[idx];
double max = devMax[idx];
for(int i =0; i< calculationsPerThread; i++)
{
x = hiprand_uniform_double(&state) * (b - a) + a;
y = f(x);
max = ( y > max ) ? y : max;
min = ( y < min ) ? y : min;
}
devMin[idx] = min;
devMax[idx] = max;
}
}
std::pair<double, double> minMaxValueV2(int n, double a, double b, FunctionCallback func)
{
unsigned long cuRand_seed = time(NULL);
hipDeviceProp_t iProp;
hipGetDeviceProperties(&iProp, 0);
//int threads = 512;
//int blocks = 100;
int threads = iProp.maxThreadsPerBlock;
int blocks = iProp.multiProcessorCount;
int size = threads * blocks;
int sizeInBytes = size * sizeof(double);
double *devMin, *devMax, *hostMin, *hostMax;
hipMalloc((void**)&devMin, sizeInBytes * sizeof(double));
hipMalloc((void**)&devMax, sizeInBytes * sizeof(double));
hostMin = (double *)malloc(sizeInBytes);
hostMax = (double *)malloc(sizeInBytes);
std::fill(hostMin, hostMin + size, std::numeric_limits<double>::max());
std::fill(hostMax, hostMax + size, std::numeric_limits<double>::lowest());
hipMemcpy(devMin, hostMin, sizeInBytes, hipMemcpyHostToDevice);
hipMemcpy(devMax, hostMax, sizeInBytes, hipMemcpyHostToDevice);
int calculationsPerThread = (n + size -1) / size;
minMaxThreadV2<<<blocks, threads>>>(cuRand_seed, a, b, devMin, devMax, size, calculationsPerThread, func);
hipDeviceSynchronize();
hipMemcpy(hostMin, devMin, sizeInBytes, hipMemcpyDeviceToHost);
hipMemcpy(hostMax, devMax, sizeInBytes, hipMemcpyDeviceToHost);
hipFree(devMin);
hipFree(devMax);
auto pair = std::make_pair( *std::min_element(hostMin, hostMin + size),
*std::max_element(hostMax, hostMax + size));
free(hostMin);
free(hostMax);
return pair;
}
void timeTestMinMaxPar(int m, int n, double a, double b, FunctionCallback f){
std::cout << std::setprecision(5);
std::chrono::duration<double> total = std::chrono::duration<double>::zero();
std::chrono::duration<double> diff;
std::chrono::high_resolution_clock::time_point start;
std::chrono::high_resolution_clock::time_point end;
std::ofstream file;
std::stringstream filename;
filename << "minMaxPar_" << m << '_' << n << ".txt";
n = 1 << n;
file.open(filename.str());
if (file.good() == true)
{
std::cout << "Testing parallel MinMax... for size: " << n << std::endl;
for(int i = 1; i <= m; ++i){
start = std::chrono::high_resolution_clock::now();
minMaxValue(n, a, b, f);
end = std::chrono::high_resolution_clock::now();
std::cout << "\r" << i * 100.0 / m << "% ";
std::cout << std::flush;
diff = end - start;
file << diff.count() << std::endl;
total += diff;
}
file.close();
}
std::cout << std::endl;
std::cout << "Parallel MinMax average time: " << total.count()/m << std::endl;
}
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void PartialMM(double *A, double *B, double *C, unsigned int N) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int j = blockIdx.y * blockDim.y + threadIdx.y;
double c = 0.0;
#pragma unroll
for (unsigned int k = 0u; k < N; ++k) {
c += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = c;
}
int main(int argc, char *argv[]) {
unsigned int threads = 1024u;
unsigned int N = 1024u;
if (argc > 1) {
threads = (unsigned int) atoi(argv[1]);
}
if (argc > 2) {
N = (unsigned int) atoi(argv[2]);
}
srand((unsigned int) time(NULL));
unsigned int size = N * N * sizeof(double);
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *) malloc(size);
h_B = (double *) malloc(size);
h_C = (double *) malloc(size);
cudaMalloc((void **) &d_A, size);
cudaMalloc((void **) &d_B, size);
cudaMalloc((void **) &d_C, size);
for (unsigned int k = 0u; k < N * N; ++k) {
h_A[k] = 2.0;//rand();
h_B[k] = 3.0;//rand();
h_C[k] = 0.0;
}
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
dim3 block(1, 1);
switch (threads) {
case 1:
block.x = 1;
block.y = 1;
break;
case 2:
block.x = 2;
block.y = 1;
break;
case 4:
block.x = 2;
block.y = 2;
break;
case 8:
block.x = 4;
block.y = 2;
break;
case 16:
block.x = 4;
block.y = 4;
break;
case 32:
block.x = 8;
block.y = 4;
break;
case 64:
block.x = 8;
block.y = 8;
break;
case 128:
block.x = 16;
block.y = 8;
break;
case 256:
block.x = 16;
block.y = 16;
break;
case 512:
block.x = 32;
block.y = 16;
break;
case 1024:
block.x = 32;
block.y = 32;
break;
}
dim3 grid(N / block.x, N / block.y);
//@formatter:off
PartialMM<<<grid, block>>>(d_A, d_B, d_C, N);
//@formatter:on
cudaDeviceSynchronize();
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
printf("Size\t\t%dx%d\n", N, N);
printf("Result:");
for (unsigned int k = 0u; k < N * N; ++k) {
if (k % N == 0)
printf("\n");
printf("%f ", h_C[k]);
}
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaDeviceReset();
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z9PartialMMPdS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R28, SRZ ; /* 0x00000000001c7805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0060*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002600 */
/*0070*/ S2R R25, SR_TID.Y ; /* 0x0000000000197919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0090*/ IMAD R3, R8, c[0x0][0x4], R25 ; /* 0x0000010008037a24 */
/* 0x002fe200078e0219 */
/*00a0*/ @!P0 BRA 0x4b0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*00c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*00d0*/ CS2R R28, SRZ ; /* 0x00000000001c7805 */
/* 0x000fc6000001ff00 */
/*00e0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304057812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0110*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fd60003f05270 */
/*0120*/ @!P1 BRA 0x3d0 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R25, R25, c[0x0][0x178], RZ ; /* 0x00005e0019197a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD R22, R0, R4, 0x3 ; /* 0x0000000300167424 */
/* 0x000fe200078e0204 */
/*0150*/ IADD3 R27, R5, -c[0x0][0x178], RZ ; /* 0x80005e00051b7a10 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD R2, R4, 0x2, R3 ; /* 0x0000000204027824 */
/* 0x000fe200078e0203 */
/*0170*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R25, R8, c[0x0][0x4], R25 ; /* 0x0000010008197a24 */
/* 0x000fe200078e0219 */
/*0190*/ CS2R R28, SRZ ; /* 0x00000000001c7805 */
/* 0x000fe2000001ff00 */
/*01a0*/ IMAD R7, R4, 0x3, R3.reuse ; /* 0x0000000304077824 */
/* 0x100fe400078e0203 */
/*01b0*/ IMAD.MOV.U32 R23, RZ, RZ, R3 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0003 */
/*01c0*/ IADD3 R9, R22, -0x3, RZ ; /* 0xfffffffd16097810 */
/* 0x001fe40007ffe0ff */
/*01d0*/ MOV R18, 0x8 ; /* 0x0000000800127802 */
/* 0x000fca0000000f00 */
/*01e0*/ IMAD.WIDE.U32 R8, R9, R18, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc800078e0012 */
/*01f0*/ IMAD.WIDE.U32 R20, R23, R18.reuse, c[0x0][0x168] ; /* 0x00005a0017147625 */
/* 0x080fe400078e0012 */
/*0200*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0210*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0000a2000c1e1b00 */
/*0220*/ IADD3 R17, R22.reuse, -0x2, RZ ; /* 0xfffffffe16117810 */
/* 0x040fe20007ffe0ff */
/*0230*/ IMAD.WIDE.U32 R14, R25, R18, c[0x0][0x168] ; /* 0x00005a00190e7625 */
/* 0x000fe200078e0012 */
/*0240*/ IADD3 R13, R22, -0x1, RZ ; /* 0xffffffff160d7810 */
/* 0x000fc60007ffe0ff */
/*0250*/ IMAD.WIDE.U32 R16, R17, R18.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe400078e0012 */
/*0260*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee8000c1e1b00 */
/*0270*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1b00 */
/*0280*/ IMAD.WIDE.U32 R12, R13, R18, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fc800078e0012 */
/*0290*/ IMAD.WIDE.U32 R20, R22, R18.reuse, c[0x0][0x160] ; /* 0x0000580016147625 */
/* 0x081fe400078e0012 */
/*02a0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f28000c1e1b00 */
/*02b0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f62000c1e1b00 */
/*02c0*/ DFMA R8, R10, R8, R28 ; /* 0x000000080a08722b */
/* 0x0060e4000000001c */
/*02d0*/ IMAD.WIDE.U32 R10, R2, R18, c[0x0][0x168] ; /* 0x00005a00020a7625 */
/* 0x001fc800078e0012 */
/*02e0*/ IMAD.WIDE.U32 R18, R7, R18, c[0x0][0x168] ; /* 0x00005a0007127625 */
/* 0x000fe400078e0012 */
/*02f0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f28000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*0310*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0320*/ DFMA R8, R14, R16, R8 ; /* 0x000000100e08722b */
/* 0x0081080000000008 */
/*0330*/ IMAD.IADD R14, R27, 0x1, R6 ; /* 0x000000011b0e7824 */
/* 0x001fca00078e0206 */
/*0340*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*0350*/ IMAD R2, R4.reuse, 0x4, R2 ; /* 0x0000000404027824 */
/* 0x040fe200078e0202 */
/*0360*/ LEA R25, R4.reuse, R25, 0x2 ; /* 0x0000001904197211 */
/* 0x040fe200078e10ff */
/*0370*/ IMAD R7, R4.reuse, 0x4, R7 ; /* 0x0000000404077824 */
/* 0x040fe200078e0207 */
/*0380*/ LEA R23, R4, R23, 0x2 ; /* 0x0000001704177211 */
/* 0x000fe400078e10ff */
/*0390*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ DFMA R8, R10, R12, R8 ; /* 0x0000000c0a08722b */
/* 0x010f4c0000000008 */
/*03b0*/ DFMA R28, R18, R20, R8 ; /* 0x00000014121c722b */
/* 0x0200620000000008 */
/*03c0*/ @P1 BRA 0x1c0 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*03d0*/ @!P0 BRA 0x4b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD R2, R6, c[0x0][0x178], R3 ; /* 0x00005e0006027a24 */
/* 0x000fe400078e0203 */
/*03f0*/ IMAD R4, R0, c[0x0][0x178], R6 ; /* 0x00005e0000047a24 */
/* 0x000fe400078e0206 */
/*0400*/ MOV R9, 0x8 ; /* 0x0000000800097802 */
/* 0x001fca0000000f00 */
/*0410*/ IMAD.WIDE.U32 R6, R4, R9, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fc800078e0009 */
/*0420*/ IMAD.WIDE.U32 R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fe400078e0009 */
/*0430*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*0440*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0450*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0460*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0470*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc40003f05270 */
/*0480*/ IADD3 R2, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe20007ffe0ff */
/*0490*/ DFMA R28, R8, R6, R28 ; /* 0x00000006081c722b */
/* 0x006054000000001c */
/*04a0*/ @P0 BRA 0x400 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*04b0*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*04c0*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fc800078e0203 */
/*04d0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0002 */
/*04e0*/ STG.E.64 [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x002fe2000c101b04 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void PartialMM(double *A, double *B, double *C, unsigned int N) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int j = blockIdx.y * blockDim.y + threadIdx.y;
double c = 0.0;
#pragma unroll
for (unsigned int k = 0u; k < N; ++k) {
c += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = c;
}
int main(int argc, char *argv[]) {
unsigned int threads = 1024u;
unsigned int N = 1024u;
if (argc > 1) {
threads = (unsigned int) atoi(argv[1]);
}
if (argc > 2) {
N = (unsigned int) atoi(argv[2]);
}
srand((unsigned int) time(NULL));
unsigned int size = N * N * sizeof(double);
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *) malloc(size);
h_B = (double *) malloc(size);
h_C = (double *) malloc(size);
cudaMalloc((void **) &d_A, size);
cudaMalloc((void **) &d_B, size);
cudaMalloc((void **) &d_C, size);
for (unsigned int k = 0u; k < N * N; ++k) {
h_A[k] = 2.0;//rand();
h_B[k] = 3.0;//rand();
h_C[k] = 0.0;
}
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
dim3 block(1, 1);
switch (threads) {
case 1:
block.x = 1;
block.y = 1;
break;
case 2:
block.x = 2;
block.y = 1;
break;
case 4:
block.x = 2;
block.y = 2;
break;
case 8:
block.x = 4;
block.y = 2;
break;
case 16:
block.x = 4;
block.y = 4;
break;
case 32:
block.x = 8;
block.y = 4;
break;
case 64:
block.x = 8;
block.y = 8;
break;
case 128:
block.x = 16;
block.y = 8;
break;
case 256:
block.x = 16;
block.y = 16;
break;
case 512:
block.x = 32;
block.y = 16;
break;
case 1024:
block.x = 32;
block.y = 32;
break;
}
dim3 grid(N / block.x, N / block.y);
//@formatter:off
PartialMM<<<grid, block>>>(d_A, d_B, d_C, N);
//@formatter:on
cudaDeviceSynchronize();
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
printf("Size\t\t%dx%d\n", N, N);
printf("Result:");
for (unsigned int k = 0u; k < N * N; ++k) {
if (k % N == 0)
printf("\n");
printf("%f ", h_C[k]);
}
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaDeviceReset();
return EXIT_SUCCESS;
} | .file "tmpxft_00072310_00000000-6_MatrixCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j
.type _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j, @function
_Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9PartialMMPdS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j, .-_Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j
.globl _Z9PartialMMPdS_S_j
.type _Z9PartialMMPdS_S_j, @function
_Z9PartialMMPdS_S_j:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9PartialMMPdS_S_j, .-_Z9PartialMMPdS_S_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Size\t\t%dx%d\n"
.LC4:
.string "Result:"
.LC5:
.string "\n"
.LC6:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1024, %ebx
cmpl $1, %edi
jg .L42
.L12:
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $8388608, %edi
call malloc@PLT
movq %rax, %r14
movl $8388608, %edi
call malloc@PLT
movq %rax, %r13
movl $8388608, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1048576, 12(%rsp)
movl $1024, %ebp
movl $8388608, %r15d
.L28:
movl 12(%rsp), %edx
salq $3, %rdx
movl $0, %eax
movsd .LC0(%rip), %xmm1
movsd .LC1(%rip), %xmm0
.L14:
movsd %xmm1, (%r14,%rax)
movsd %xmm0, 0(%r13,%rax)
movq $0x000000000, (%r12,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L14
.L13:
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
cmpl $64, %ebx
je .L31
cmpl $64, %ebx
ja .L16
leal -2(%rbx), %eax
cmpl $30, %eax
ja .L32
ja .L17
movl %eax, %eax
leaq .L19(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L19:
.long .L33-.L19
.long .L17-.L19
.long .L22-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L21-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L20-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L18-.L19
.text
.L42:
movl %edi, %ebp
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
cmpl $2, %ebp
jle .L12
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %ebp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl %r12d, %eax
imull %r12d, %eax
movl %eax, 12(%rsp)
leal 0(,%rax,8), %r15d
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
cmpl $0, 12(%rsp)
je .L13
jmp .L28
.L22:
movl $2, %ecx
movl $2, %ebx
jmp .L15
.L17:
movl $1, %ecx
movl $1, %ebx
.L15:
movl %ebp, %eax
movl $0, %edx
divl %ebx
movl %eax, 60(%rsp)
movl %ebp, %eax
movl $0, %edx
divl %ecx
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl %ecx, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L24:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %ebp, %ecx
movl %ebp, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L25
movl %eax, %r15d
movl $0, %ebx
jmp .L27
.L16:
cmpl $512, %ebx
je .L34
cmpl $512, %ebx
ja .L23
cmpl $128, %ebx
je .L35
cmpl $256, %ebx
jne .L44
movl $16, %ecx
movl $16, %ebx
jmp .L15
.L44:
movl $1, %ecx
movl $1, %ebx
jmp .L15
.L23:
cmpl $1024, %ebx
jne .L45
movl $32, %ecx
movl $32, %ebx
jmp .L15
.L45:
movl $1, %ecx
movl $1, %ebx
jmp .L15
.L21:
movl $2, %ecx
movl $4, %ebx
jmp .L15
.L20:
movl $4, %ecx
movl $4, %ebx
jmp .L15
.L18:
movl $4, %ecx
movl $8, %ebx
jmp .L15
.L31:
movl $8, %ecx
movl $8, %ebx
jmp .L15
.L32:
movl $1, %ecx
movl $1, %ebx
jmp .L15
.L33:
movl $1, %ecx
jmp .L15
.L34:
movl $16, %ecx
movl $32, %ebx
jmp .L15
.L35:
movl $8, %ecx
movl $16, %ebx
jmp .L15
.L43:
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j
jmp .L24
.L26:
movsd (%r12,%rbx,8), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r15, %rbx
je .L25
.L27:
movl %ebx, %eax
movl $0, %edx
divl %ebp
testl %edx, %edx
jne .L26
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L25:
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9PartialMMPdS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9PartialMMPdS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.align 8
.LC1:
.long 0
.long 1074266112
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void PartialMM(double *A, double *B, double *C, unsigned int N) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int j = blockIdx.y * blockDim.y + threadIdx.y;
double c = 0.0;
#pragma unroll
for (unsigned int k = 0u; k < N; ++k) {
c += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = c;
}
int main(int argc, char *argv[]) {
unsigned int threads = 1024u;
unsigned int N = 1024u;
if (argc > 1) {
threads = (unsigned int) atoi(argv[1]);
}
if (argc > 2) {
N = (unsigned int) atoi(argv[2]);
}
srand((unsigned int) time(NULL));
unsigned int size = N * N * sizeof(double);
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *) malloc(size);
h_B = (double *) malloc(size);
h_C = (double *) malloc(size);
cudaMalloc((void **) &d_A, size);
cudaMalloc((void **) &d_B, size);
cudaMalloc((void **) &d_C, size);
for (unsigned int k = 0u; k < N * N; ++k) {
h_A[k] = 2.0;//rand();
h_B[k] = 3.0;//rand();
h_C[k] = 0.0;
}
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
dim3 block(1, 1);
switch (threads) {
case 1:
block.x = 1;
block.y = 1;
break;
case 2:
block.x = 2;
block.y = 1;
break;
case 4:
block.x = 2;
block.y = 2;
break;
case 8:
block.x = 4;
block.y = 2;
break;
case 16:
block.x = 4;
block.y = 4;
break;
case 32:
block.x = 8;
block.y = 4;
break;
case 64:
block.x = 8;
block.y = 8;
break;
case 128:
block.x = 16;
block.y = 8;
break;
case 256:
block.x = 16;
block.y = 16;
break;
case 512:
block.x = 32;
block.y = 16;
break;
case 1024:
block.x = 32;
block.y = 32;
break;
}
dim3 grid(N / block.x, N / block.y);
//@formatter:off
PartialMM<<<grid, block>>>(d_A, d_B, d_C, N);
//@formatter:on
cudaDeviceSynchronize();
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
printf("Size\t\t%dx%d\n", N, N);
printf("Result:");
for (unsigned int k = 0u; k < N * N; ++k) {
if (k % N == 0)
printf("\n");
printf("%f ", h_C[k]);
}
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaDeviceReset();
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void PartialMM(double *A, double *B, double *C, unsigned int N) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int j = blockIdx.y * blockDim.y + threadIdx.y;
double c = 0.0;
#pragma unroll
for (unsigned int k = 0u; k < N; ++k) {
c += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = c;
}
int main(int argc, char *argv[]) {
unsigned int threads = 1024u;
unsigned int N = 1024u;
if (argc > 1) {
threads = (unsigned int) atoi(argv[1]);
}
if (argc > 2) {
N = (unsigned int) atoi(argv[2]);
}
srand((unsigned int) time(NULL));
unsigned int size = N * N * sizeof(double);
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *) malloc(size);
h_B = (double *) malloc(size);
h_C = (double *) malloc(size);
hipMalloc((void **) &d_A, size);
hipMalloc((void **) &d_B, size);
hipMalloc((void **) &d_C, size);
for (unsigned int k = 0u; k < N * N; ++k) {
h_A[k] = 2.0;//rand();
h_B[k] = 3.0;//rand();
h_C[k] = 0.0;
}
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
dim3 block(1, 1);
switch (threads) {
case 1:
block.x = 1;
block.y = 1;
break;
case 2:
block.x = 2;
block.y = 1;
break;
case 4:
block.x = 2;
block.y = 2;
break;
case 8:
block.x = 4;
block.y = 2;
break;
case 16:
block.x = 4;
block.y = 4;
break;
case 32:
block.x = 8;
block.y = 4;
break;
case 64:
block.x = 8;
block.y = 8;
break;
case 128:
block.x = 16;
block.y = 8;
break;
case 256:
block.x = 16;
block.y = 16;
break;
case 512:
block.x = 32;
block.y = 16;
break;
case 1024:
block.x = 32;
block.y = 32;
break;
}
dim3 grid(N / block.x, N / block.y);
//@formatter:off
PartialMM<<<grid, block>>>(d_A, d_B, d_C, N);
//@formatter:on
hipDeviceSynchronize();
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
printf("Size\t\t%dx%d\n", N, N);
printf("Result:");
for (unsigned int k = 0u; k < N * N; ++k) {
if (k % N == 0)
printf("\n");
printf("%f ", h_C[k]);
}
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipDeviceReset();
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void PartialMM(double *A, double *B, double *C, unsigned int N) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int j = blockIdx.y * blockDim.y + threadIdx.y;
double c = 0.0;
#pragma unroll
for (unsigned int k = 0u; k < N; ++k) {
c += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = c;
}
int main(int argc, char *argv[]) {
unsigned int threads = 1024u;
unsigned int N = 1024u;
if (argc > 1) {
threads = (unsigned int) atoi(argv[1]);
}
if (argc > 2) {
N = (unsigned int) atoi(argv[2]);
}
srand((unsigned int) time(NULL));
unsigned int size = N * N * sizeof(double);
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *) malloc(size);
h_B = (double *) malloc(size);
h_C = (double *) malloc(size);
hipMalloc((void **) &d_A, size);
hipMalloc((void **) &d_B, size);
hipMalloc((void **) &d_C, size);
for (unsigned int k = 0u; k < N * N; ++k) {
h_A[k] = 2.0;//rand();
h_B[k] = 3.0;//rand();
h_C[k] = 0.0;
}
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
dim3 block(1, 1);
switch (threads) {
case 1:
block.x = 1;
block.y = 1;
break;
case 2:
block.x = 2;
block.y = 1;
break;
case 4:
block.x = 2;
block.y = 2;
break;
case 8:
block.x = 4;
block.y = 2;
break;
case 16:
block.x = 4;
block.y = 4;
break;
case 32:
block.x = 8;
block.y = 4;
break;
case 64:
block.x = 8;
block.y = 8;
break;
case 128:
block.x = 16;
block.y = 8;
break;
case 256:
block.x = 16;
block.y = 16;
break;
case 512:
block.x = 32;
block.y = 16;
break;
case 1024:
block.x = 32;
block.y = 32;
break;
}
dim3 grid(N / block.x, N / block.y);
//@formatter:off
PartialMM<<<grid, block>>>(d_A, d_B, d_C, N);
//@formatter:on
hipDeviceSynchronize();
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
printf("Size\t\t%dx%d\n", N, N);
printf("Result:");
for (unsigned int k = 0u; k < N * N; ++k) {
if (k % N == 0)
printf("\n");
printf("%f ", h_C[k]);
}
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipDeviceReset();
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9PartialMMPdS_S_j
.globl _Z9PartialMMPdS_S_j
.p2align 8
.type _Z9PartialMMPdS_S_j,@function
_Z9PartialMMPdS_S_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v8, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
s_mul_i32 s15, s15, s3
s_cmp_eq_u32 s2, 0
v_add_nc_u32_e32 v1, s15, v8
s_mov_b32 s3, 0
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v9, v0, s2
s_cmp_lt_u32 s2, 8
s_cbranch_scc1 .LBB0_5
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, v1
s_and_b32 s8, s2, -8
s_mul_i32 s9, s2, 7
s_lshl_b32 s10, s2, 3
s_mul_i32 s11, s2, 6
s_mul_i32 s12, s2, 5
s_lshl_b32 s13, s2, 2
s_mul_i32 s14, s2, 3
s_lshl_b32 s16, s2, 1
.LBB0_3:
v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, s3, v9
v_dual_mov_b32 v15, v5 :: v_dual_add_nc_u32 v14, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_mov_b32 v17, v5 :: v_dual_add_nc_u32 v16, 1, v4
v_lshlrev_b64 v[10:11], 3, v[4:5]
v_lshlrev_b64 v[12:13], 3, v[6:7]
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[14:15], 3, v[14:15]
v_dual_mov_b32 v19, v5 :: v_dual_add_nc_u32 v18, s16, v6
v_lshlrev_b64 v[16:17], 3, v[16:17]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[12:13], v[12:13], off
v_add_co_u32 v14, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s4, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
global_load_b64 v[14:15], v[14:15], off
global_load_b64 v[16:17], v[16:17], off
v_dual_mov_b32 v21, v5 :: v_dual_add_nc_u32 v20, 2, v4
v_lshlrev_b64 v[18:19], 3, v[18:19]
v_dual_mov_b32 v23, v5 :: v_dual_add_nc_u32 v22, s14, v6
v_dual_mov_b32 v25, v5 :: v_dual_add_nc_u32 v24, 3, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[20:21], 3, v[20:21]
v_add_co_u32 v18, vcc_lo, s6, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
v_lshlrev_b64 v[22:23], 3, v[22:23]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v20, vcc_lo, s4, v20
v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
global_load_b64 v[18:19], v[18:19], off
global_load_b64 v[20:21], v[20:21], off
v_lshlrev_b64 v[24:25], 3, v[24:25]
v_add_co_u32 v22, vcc_lo, s6, v22
v_add_co_ci_u32_e32 v23, vcc_lo, s7, v23, vcc_lo
v_dual_mov_b32 v27, v5 :: v_dual_add_nc_u32 v26, s13, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v24, vcc_lo, s4, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v25, vcc_lo
global_load_b64 v[22:23], v[22:23], off
global_load_b64 v[24:25], v[24:25], off
v_dual_mov_b32 v29, v5 :: v_dual_add_nc_u32 v28, 4, v4
v_lshlrev_b64 v[26:27], 3, v[26:27]
v_dual_mov_b32 v31, v5 :: v_dual_add_nc_u32 v30, s12, v6
v_dual_mov_b32 v33, v5 :: v_dual_add_nc_u32 v32, 5, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[28:29], 3, v[28:29]
v_add_co_u32 v26, vcc_lo, s6, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s7, v27, vcc_lo
v_lshlrev_b64 v[30:31], 3, v[30:31]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v28, vcc_lo, s4, v28
v_add_co_ci_u32_e32 v29, vcc_lo, s5, v29, vcc_lo
global_load_b64 v[26:27], v[26:27], off
global_load_b64 v[28:29], v[28:29], off
v_lshlrev_b64 v[32:33], 3, v[32:33]
v_add_co_u32 v30, vcc_lo, s6, v30
v_add_co_ci_u32_e32 v31, vcc_lo, s7, v31, vcc_lo
v_dual_mov_b32 v35, v5 :: v_dual_add_nc_u32 v34, s11, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v32, vcc_lo, s4, v32
v_add_co_ci_u32_e32 v33, vcc_lo, s5, v33, vcc_lo
global_load_b64 v[30:31], v[30:31], off
global_load_b64 v[32:33], v[32:33], off
v_dual_mov_b32 v37, v5 :: v_dual_add_nc_u32 v36, 6, v4
v_lshlrev_b64 v[34:35], 3, v[34:35]
v_add_nc_u32_e32 v4, 7, v4
s_add_i32 s3, s3, 8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[36:37], 3, v[36:37]
s_cmp_eq_u32 s8, s3
v_add_co_u32 v34, vcc_lo, s6, v34
v_add_co_ci_u32_e32 v35, vcc_lo, s7, v35, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v36, vcc_lo, s4, v36
v_add_co_ci_u32_e32 v37, vcc_lo, s5, v37, vcc_lo
global_load_b64 v[34:35], v[34:35], off
global_load_b64 v[36:37], v[36:37], off
v_lshlrev_b64 v[38:39], 3, v[4:5]
v_add_nc_u32_e32 v4, s9, v6
v_add_nc_u32_e32 v6, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[40:41], 3, v[4:5]
v_add_co_u32 v38, vcc_lo, s4, v38
v_add_co_ci_u32_e32 v39, vcc_lo, s5, v39, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v40, vcc_lo, s6, v40
v_add_co_ci_u32_e32 v41, vcc_lo, s7, v41, vcc_lo
global_load_b64 v[38:39], v[38:39], off
global_load_b64 v[40:41], v[40:41], off
s_waitcnt vmcnt(14)
v_fma_f64 v[2:3], v[10:11], v[12:13], v[2:3]
s_waitcnt vmcnt(12)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[16:17], v[14:15], v[2:3]
s_waitcnt vmcnt(10)
v_fma_f64 v[2:3], v[20:21], v[18:19], v[2:3]
s_waitcnt vmcnt(8)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[24:25], v[22:23], v[2:3]
s_waitcnt vmcnt(6)
v_fma_f64 v[2:3], v[28:29], v[26:27], v[2:3]
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[32:33], v[30:31], v[2:3]
s_waitcnt vmcnt(2)
v_fma_f64 v[2:3], v[36:37], v[34:35], v[2:3]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[38:39], v[40:41], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_6
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_branch .LBB0_9
.LBB0_5:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_6:
s_and_b32 s8, s2, 7
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_9
s_mul_i32 s9, s3, s2
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s3, v9
v_add3_u32 v6, s15, s9, v8
.p2align 6
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v7, v5
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_add_nc_u32_e32 v4, 1, v4
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 0
v_lshlrev_b64 v[10:11], 3, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v9, vcc_lo
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v11, vcc_lo
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[7:8], v[9:10], v[2:3]
s_cbranch_scc1 .LBB0_8
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9PartialMMPdS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 42
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9PartialMMPdS_S_j, .Lfunc_end0-_Z9PartialMMPdS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9PartialMMPdS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z9PartialMMPdS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 42
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void PartialMM(double *A, double *B, double *C, unsigned int N) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int j = blockIdx.y * blockDim.y + threadIdx.y;
double c = 0.0;
#pragma unroll
for (unsigned int k = 0u; k < N; ++k) {
c += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = c;
}
int main(int argc, char *argv[]) {
unsigned int threads = 1024u;
unsigned int N = 1024u;
if (argc > 1) {
threads = (unsigned int) atoi(argv[1]);
}
if (argc > 2) {
N = (unsigned int) atoi(argv[2]);
}
srand((unsigned int) time(NULL));
unsigned int size = N * N * sizeof(double);
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *) malloc(size);
h_B = (double *) malloc(size);
h_C = (double *) malloc(size);
hipMalloc((void **) &d_A, size);
hipMalloc((void **) &d_B, size);
hipMalloc((void **) &d_C, size);
for (unsigned int k = 0u; k < N * N; ++k) {
h_A[k] = 2.0;//rand();
h_B[k] = 3.0;//rand();
h_C[k] = 0.0;
}
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
dim3 block(1, 1);
switch (threads) {
case 1:
block.x = 1;
block.y = 1;
break;
case 2:
block.x = 2;
block.y = 1;
break;
case 4:
block.x = 2;
block.y = 2;
break;
case 8:
block.x = 4;
block.y = 2;
break;
case 16:
block.x = 4;
block.y = 4;
break;
case 32:
block.x = 8;
block.y = 4;
break;
case 64:
block.x = 8;
block.y = 8;
break;
case 128:
block.x = 16;
block.y = 8;
break;
case 256:
block.x = 16;
block.y = 16;
break;
case 512:
block.x = 32;
block.y = 16;
break;
case 1024:
block.x = 32;
block.y = 32;
break;
}
dim3 grid(N / block.x, N / block.y);
//@formatter:off
PartialMM<<<grid, block>>>(d_A, d_B, d_C, N);
//@formatter:on
hipDeviceSynchronize();
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
printf("Size\t\t%dx%d\n", N, N);
printf("Result:");
for (unsigned int k = 0u; k < N * N; ++k) {
if (k % N == 0)
printf("\n");
printf("%f ", h_C[k]);
}
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipDeviceReset();
return EXIT_SUCCESS;
} | .text
.file "MatrixCUDA.hip"
.globl _Z24__device_stub__PartialMMPdS_S_j # -- Begin function _Z24__device_stub__PartialMMPdS_S_j
.p2align 4, 0x90
.type _Z24__device_stub__PartialMMPdS_S_j,@function
_Z24__device_stub__PartialMMPdS_S_j: # @_Z24__device_stub__PartialMMPdS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9PartialMMPdS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__PartialMMPdS_S_j, .Lfunc_end0-_Z24__device_stub__PartialMMPdS_S_j
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
movl $1024, %ebx # imm = 0x400
movl $1024, %eax # imm = 0x400
cmpl $2, %edi
jl .LBB1_2
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB1_2:
movq %rax, 48(%rsp) # 8-byte Spill
cmpl $3, %ebp
jl .LBB1_4
# %bb.3:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB1_4:
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %ebx, %r13d
imull %r13d, %r13d
leal (,%r13,8), %ebp
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbp, 40(%rsp) # 8-byte Spill
movq %rbp, %rsi
callq hipMalloc
movl %r13d, %ebp
movq %r13, (%rsp) # 8-byte Spill
testl %r13d, %r13d
je .LBB1_7
# %bb.5: # %.lr.ph.preheader
leaq (,%rbp,8), %rdx
xorl %r13d, %r13d
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movabsq $4613937818241073152, %rcx # imm = 0x4008000000000000
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rax, (%r14,%r13,8)
movq %rcx, (%r15,%r13,8)
incq %r13
cmpq %r13, %rbp
jne .LBB1_6
.LBB1_7: # %._crit_edge
movq 24(%rsp), %rdi
movq %r14, %rsi
movq 40(%rsp), %r13 # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rax # 8-byte Reload
cmpl $63, %eax
jg .LBB1_11
# %bb.8: # %._crit_edge
addl $-2, %eax
cmpl $30, %eax
ja .LBB1_26
# %bb.9: # %._crit_edge
movabsq $4294967297, %r8 # imm = 0x100000001
jmpq *.LJTI1_0(,%rax,8)
.LBB1_10:
incq %r8
jmp .LBB1_27
.LBB1_11: # %._crit_edge
cmpl $255, %eax
jle .LBB1_16
# %bb.12: # %._crit_edge
cmpl $256, %eax # imm = 0x100
movabsq $4294967297, %r8 # imm = 0x100000001
je .LBB1_24
# %bb.13: # %._crit_edge
cmpl $512, %eax # imm = 0x200
movq (%rsp), %r13 # 8-byte Reload
je .LBB1_25
# %bb.14: # %._crit_edge
cmpl $1024, %eax # imm = 0x400
jne .LBB1_28
# %bb.15:
movabsq $137438953504, %r8 # imm = 0x2000000020
jmp .LBB1_28
.LBB1_16: # %._crit_edge
cmpl $64, %eax
movabsq $4294967297, %r8 # imm = 0x100000001
je .LBB1_23
# %bb.17: # %._crit_edge
cmpl $128, %eax
movq (%rsp), %r13 # 8-byte Reload
jne .LBB1_28
# %bb.18:
movabsq $34359738376, %r8 # imm = 0x800000008
addq $8, %r8
jmp .LBB1_28
.LBB1_19:
movabsq $17179869188, %r8 # imm = 0x400000004
addq $4, %r8
jmp .LBB1_27
.LBB1_20:
movabsq $8589934594, %r8 # imm = 0x200000002
jmp .LBB1_27
.LBB1_21:
movabsq $17179869188, %r8 # imm = 0x400000004
jmp .LBB1_27
.LBB1_22:
movabsq $8589934594, %r8 # imm = 0x200000002
addq $2, %r8
jmp .LBB1_27
.LBB1_23:
movabsq $34359738376, %r8 # imm = 0x800000008
jmp .LBB1_27
.LBB1_24:
movabsq $68719476752, %r8 # imm = 0x1000000010
.LBB1_27:
movq (%rsp), %r13 # 8-byte Reload
.LBB1_28:
movl %ebx, %eax
xorl %edx, %edx
divl %r8d
movl %eax, %edi
movq %r8, %rcx
shrq $32, %rcx
movl %ebx, %eax
xorl %edx, %edx
divl %ecx
# kill: def $eax killed $eax def $rax
shlq $32, %rax
orq %rax, %rdi
movl $1, %esi
movq %r8, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_30
# %bb.29:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %ebx, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9PartialMMPdS_S_j, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_30:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r12, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl %ebx, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
testl %r13d, %r13d
je .LBB1_35
# %bb.31: # %.lr.ph127.preheader
xorl %r13d, %r13d
jmp .LBB1_33
.p2align 4, 0x90
.LBB1_32: # in Loop: Header=BB1_33 Depth=1
movsd (%r12,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbp
je .LBB1_35
.LBB1_33: # %.lr.ph127
# =>This Inner Loop Header: Depth=1
movl %r13d, %eax
xorl %edx, %edx
divl %ebx
testl %edx, %edx
jne .LBB1_32
# %bb.34: # in Loop: Header=BB1_33 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_32
.LBB1_35: # %._crit_edge128
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_25:
.cfi_def_cfa_offset 224
movabsq $68719476752, %r8 # imm = 0x1000000010
addq $16, %r8
jmp .LBB1_28
.LBB1_26:
movq (%rsp), %r13 # 8-byte Reload
movabsq $4294967297, %r8 # imm = 0x100000001
jmp .LBB1_28
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI1_0:
.quad .LBB1_10
.quad .LBB1_27
.quad .LBB1_20
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_22
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_21
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_19
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9PartialMMPdS_S_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9PartialMMPdS_S_j,@object # @_Z9PartialMMPdS_S_j
.section .rodata,"a",@progbits
.globl _Z9PartialMMPdS_S_j
.p2align 3, 0x0
_Z9PartialMMPdS_S_j:
.quad _Z24__device_stub__PartialMMPdS_S_j
.size _Z9PartialMMPdS_S_j, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Size\t\t%dx%d\n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Result:"
.size .L.str.1, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9PartialMMPdS_S_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__PartialMMPdS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9PartialMMPdS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9PartialMMPdS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R28, SRZ ; /* 0x00000000001c7805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0060*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002600 */
/*0070*/ S2R R25, SR_TID.Y ; /* 0x0000000000197919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0090*/ IMAD R3, R8, c[0x0][0x4], R25 ; /* 0x0000010008037a24 */
/* 0x002fe200078e0219 */
/*00a0*/ @!P0 BRA 0x4b0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*00c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*00d0*/ CS2R R28, SRZ ; /* 0x00000000001c7805 */
/* 0x000fc6000001ff00 */
/*00e0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304057812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0110*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fd60003f05270 */
/*0120*/ @!P1 BRA 0x3d0 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R25, R25, c[0x0][0x178], RZ ; /* 0x00005e0019197a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD R22, R0, R4, 0x3 ; /* 0x0000000300167424 */
/* 0x000fe200078e0204 */
/*0150*/ IADD3 R27, R5, -c[0x0][0x178], RZ ; /* 0x80005e00051b7a10 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD R2, R4, 0x2, R3 ; /* 0x0000000204027824 */
/* 0x000fe200078e0203 */
/*0170*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R25, R8, c[0x0][0x4], R25 ; /* 0x0000010008197a24 */
/* 0x000fe200078e0219 */
/*0190*/ CS2R R28, SRZ ; /* 0x00000000001c7805 */
/* 0x000fe2000001ff00 */
/*01a0*/ IMAD R7, R4, 0x3, R3.reuse ; /* 0x0000000304077824 */
/* 0x100fe400078e0203 */
/*01b0*/ IMAD.MOV.U32 R23, RZ, RZ, R3 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0003 */
/*01c0*/ IADD3 R9, R22, -0x3, RZ ; /* 0xfffffffd16097810 */
/* 0x001fe40007ffe0ff */
/*01d0*/ MOV R18, 0x8 ; /* 0x0000000800127802 */
/* 0x000fca0000000f00 */
/*01e0*/ IMAD.WIDE.U32 R8, R9, R18, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc800078e0012 */
/*01f0*/ IMAD.WIDE.U32 R20, R23, R18.reuse, c[0x0][0x168] ; /* 0x00005a0017147625 */
/* 0x080fe400078e0012 */
/*0200*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0210*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0000a2000c1e1b00 */
/*0220*/ IADD3 R17, R22.reuse, -0x2, RZ ; /* 0xfffffffe16117810 */
/* 0x040fe20007ffe0ff */
/*0230*/ IMAD.WIDE.U32 R14, R25, R18, c[0x0][0x168] ; /* 0x00005a00190e7625 */
/* 0x000fe200078e0012 */
/*0240*/ IADD3 R13, R22, -0x1, RZ ; /* 0xffffffff160d7810 */
/* 0x000fc60007ffe0ff */
/*0250*/ IMAD.WIDE.U32 R16, R17, R18.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe400078e0012 */
/*0260*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee8000c1e1b00 */
/*0270*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1b00 */
/*0280*/ IMAD.WIDE.U32 R12, R13, R18, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fc800078e0012 */
/*0290*/ IMAD.WIDE.U32 R20, R22, R18.reuse, c[0x0][0x160] ; /* 0x0000580016147625 */
/* 0x081fe400078e0012 */
/*02a0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f28000c1e1b00 */
/*02b0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f62000c1e1b00 */
/*02c0*/ DFMA R8, R10, R8, R28 ; /* 0x000000080a08722b */
/* 0x0060e4000000001c */
/*02d0*/ IMAD.WIDE.U32 R10, R2, R18, c[0x0][0x168] ; /* 0x00005a00020a7625 */
/* 0x001fc800078e0012 */
/*02e0*/ IMAD.WIDE.U32 R18, R7, R18, c[0x0][0x168] ; /* 0x00005a0007127625 */
/* 0x000fe400078e0012 */
/*02f0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f28000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*0310*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0320*/ DFMA R8, R14, R16, R8 ; /* 0x000000100e08722b */
/* 0x0081080000000008 */
/*0330*/ IMAD.IADD R14, R27, 0x1, R6 ; /* 0x000000011b0e7824 */
/* 0x001fca00078e0206 */
/*0340*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*0350*/ IMAD R2, R4.reuse, 0x4, R2 ; /* 0x0000000404027824 */
/* 0x040fe200078e0202 */
/*0360*/ LEA R25, R4.reuse, R25, 0x2 ; /* 0x0000001904197211 */
/* 0x040fe200078e10ff */
/*0370*/ IMAD R7, R4.reuse, 0x4, R7 ; /* 0x0000000404077824 */
/* 0x040fe200078e0207 */
/*0380*/ LEA R23, R4, R23, 0x2 ; /* 0x0000001704177211 */
/* 0x000fe400078e10ff */
/*0390*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ DFMA R8, R10, R12, R8 ; /* 0x0000000c0a08722b */
/* 0x010f4c0000000008 */
/*03b0*/ DFMA R28, R18, R20, R8 ; /* 0x00000014121c722b */
/* 0x0200620000000008 */
/*03c0*/ @P1 BRA 0x1c0 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*03d0*/ @!P0 BRA 0x4b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD R2, R6, c[0x0][0x178], R3 ; /* 0x00005e0006027a24 */
/* 0x000fe400078e0203 */
/*03f0*/ IMAD R4, R0, c[0x0][0x178], R6 ; /* 0x00005e0000047a24 */
/* 0x000fe400078e0206 */
/*0400*/ MOV R9, 0x8 ; /* 0x0000000800097802 */
/* 0x001fca0000000f00 */
/*0410*/ IMAD.WIDE.U32 R6, R4, R9, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fc800078e0009 */
/*0420*/ IMAD.WIDE.U32 R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fe400078e0009 */
/*0430*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*0440*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0450*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0460*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0470*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc40003f05270 */
/*0480*/ IADD3 R2, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe20007ffe0ff */
/*0490*/ DFMA R28, R8, R6, R28 ; /* 0x00000006081c722b */
/* 0x006054000000001c */
/*04a0*/ @P0 BRA 0x400 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*04b0*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*04c0*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fc800078e0203 */
/*04d0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0002 */
/*04e0*/ STG.E.64 [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x002fe2000c101b04 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9PartialMMPdS_S_j
.globl _Z9PartialMMPdS_S_j
.p2align 8
.type _Z9PartialMMPdS_S_j,@function
_Z9PartialMMPdS_S_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v8, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
s_mul_i32 s15, s15, s3
s_cmp_eq_u32 s2, 0
v_add_nc_u32_e32 v1, s15, v8
s_mov_b32 s3, 0
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v9, v0, s2
s_cmp_lt_u32 s2, 8
s_cbranch_scc1 .LBB0_5
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, v1
s_and_b32 s8, s2, -8
s_mul_i32 s9, s2, 7
s_lshl_b32 s10, s2, 3
s_mul_i32 s11, s2, 6
s_mul_i32 s12, s2, 5
s_lshl_b32 s13, s2, 2
s_mul_i32 s14, s2, 3
s_lshl_b32 s16, s2, 1
.LBB0_3:
v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v4, s3, v9
v_dual_mov_b32 v15, v5 :: v_dual_add_nc_u32 v14, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_mov_b32 v17, v5 :: v_dual_add_nc_u32 v16, 1, v4
v_lshlrev_b64 v[10:11], 3, v[4:5]
v_lshlrev_b64 v[12:13], 3, v[6:7]
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[14:15], 3, v[14:15]
v_dual_mov_b32 v19, v5 :: v_dual_add_nc_u32 v18, s16, v6
v_lshlrev_b64 v[16:17], 3, v[16:17]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[12:13], v[12:13], off
v_add_co_u32 v14, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s4, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
global_load_b64 v[14:15], v[14:15], off
global_load_b64 v[16:17], v[16:17], off
v_dual_mov_b32 v21, v5 :: v_dual_add_nc_u32 v20, 2, v4
v_lshlrev_b64 v[18:19], 3, v[18:19]
v_dual_mov_b32 v23, v5 :: v_dual_add_nc_u32 v22, s14, v6
v_dual_mov_b32 v25, v5 :: v_dual_add_nc_u32 v24, 3, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[20:21], 3, v[20:21]
v_add_co_u32 v18, vcc_lo, s6, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
v_lshlrev_b64 v[22:23], 3, v[22:23]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v20, vcc_lo, s4, v20
v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
global_load_b64 v[18:19], v[18:19], off
global_load_b64 v[20:21], v[20:21], off
v_lshlrev_b64 v[24:25], 3, v[24:25]
v_add_co_u32 v22, vcc_lo, s6, v22
v_add_co_ci_u32_e32 v23, vcc_lo, s7, v23, vcc_lo
v_dual_mov_b32 v27, v5 :: v_dual_add_nc_u32 v26, s13, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v24, vcc_lo, s4, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v25, vcc_lo
global_load_b64 v[22:23], v[22:23], off
global_load_b64 v[24:25], v[24:25], off
v_dual_mov_b32 v29, v5 :: v_dual_add_nc_u32 v28, 4, v4
v_lshlrev_b64 v[26:27], 3, v[26:27]
v_dual_mov_b32 v31, v5 :: v_dual_add_nc_u32 v30, s12, v6
v_dual_mov_b32 v33, v5 :: v_dual_add_nc_u32 v32, 5, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[28:29], 3, v[28:29]
v_add_co_u32 v26, vcc_lo, s6, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s7, v27, vcc_lo
v_lshlrev_b64 v[30:31], 3, v[30:31]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v28, vcc_lo, s4, v28
v_add_co_ci_u32_e32 v29, vcc_lo, s5, v29, vcc_lo
global_load_b64 v[26:27], v[26:27], off
global_load_b64 v[28:29], v[28:29], off
v_lshlrev_b64 v[32:33], 3, v[32:33]
v_add_co_u32 v30, vcc_lo, s6, v30
v_add_co_ci_u32_e32 v31, vcc_lo, s7, v31, vcc_lo
v_dual_mov_b32 v35, v5 :: v_dual_add_nc_u32 v34, s11, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v32, vcc_lo, s4, v32
v_add_co_ci_u32_e32 v33, vcc_lo, s5, v33, vcc_lo
global_load_b64 v[30:31], v[30:31], off
global_load_b64 v[32:33], v[32:33], off
v_dual_mov_b32 v37, v5 :: v_dual_add_nc_u32 v36, 6, v4
v_lshlrev_b64 v[34:35], 3, v[34:35]
v_add_nc_u32_e32 v4, 7, v4
s_add_i32 s3, s3, 8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[36:37], 3, v[36:37]
s_cmp_eq_u32 s8, s3
v_add_co_u32 v34, vcc_lo, s6, v34
v_add_co_ci_u32_e32 v35, vcc_lo, s7, v35, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v36, vcc_lo, s4, v36
v_add_co_ci_u32_e32 v37, vcc_lo, s5, v37, vcc_lo
global_load_b64 v[34:35], v[34:35], off
global_load_b64 v[36:37], v[36:37], off
v_lshlrev_b64 v[38:39], 3, v[4:5]
v_add_nc_u32_e32 v4, s9, v6
v_add_nc_u32_e32 v6, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[40:41], 3, v[4:5]
v_add_co_u32 v38, vcc_lo, s4, v38
v_add_co_ci_u32_e32 v39, vcc_lo, s5, v39, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v40, vcc_lo, s6, v40
v_add_co_ci_u32_e32 v41, vcc_lo, s7, v41, vcc_lo
global_load_b64 v[38:39], v[38:39], off
global_load_b64 v[40:41], v[40:41], off
s_waitcnt vmcnt(14)
v_fma_f64 v[2:3], v[10:11], v[12:13], v[2:3]
s_waitcnt vmcnt(12)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[16:17], v[14:15], v[2:3]
s_waitcnt vmcnt(10)
v_fma_f64 v[2:3], v[20:21], v[18:19], v[2:3]
s_waitcnt vmcnt(8)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[24:25], v[22:23], v[2:3]
s_waitcnt vmcnt(6)
v_fma_f64 v[2:3], v[28:29], v[26:27], v[2:3]
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[32:33], v[30:31], v[2:3]
s_waitcnt vmcnt(2)
v_fma_f64 v[2:3], v[36:37], v[34:35], v[2:3]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[38:39], v[40:41], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_6
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_branch .LBB0_9
.LBB0_5:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_6:
s_and_b32 s8, s2, 7
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_9
s_mul_i32 s9, s3, s2
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s3, v9
v_add3_u32 v6, s15, s9, v8
.p2align 6
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v7, v5
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_add_nc_u32_e32 v4, 1, v4
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 0
v_lshlrev_b64 v[10:11], 3, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v9, vcc_lo
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v11, vcc_lo
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[7:8], v[9:10], v[2:3]
s_cbranch_scc1 .LBB0_8
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9PartialMMPdS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 42
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9PartialMMPdS_S_j, .Lfunc_end0-_Z9PartialMMPdS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9PartialMMPdS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z9PartialMMPdS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 42
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00072310_00000000-6_MatrixCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j
.type _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j, @function
_Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9PartialMMPdS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j, .-_Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j
.globl _Z9PartialMMPdS_S_j
.type _Z9PartialMMPdS_S_j, @function
_Z9PartialMMPdS_S_j:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9PartialMMPdS_S_j, .-_Z9PartialMMPdS_S_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Size\t\t%dx%d\n"
.LC4:
.string "Result:"
.LC5:
.string "\n"
.LC6:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1024, %ebx
cmpl $1, %edi
jg .L42
.L12:
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $8388608, %edi
call malloc@PLT
movq %rax, %r14
movl $8388608, %edi
call malloc@PLT
movq %rax, %r13
movl $8388608, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1048576, 12(%rsp)
movl $1024, %ebp
movl $8388608, %r15d
.L28:
movl 12(%rsp), %edx
salq $3, %rdx
movl $0, %eax
movsd .LC0(%rip), %xmm1
movsd .LC1(%rip), %xmm0
.L14:
movsd %xmm1, (%r14,%rax)
movsd %xmm0, 0(%r13,%rax)
movq $0x000000000, (%r12,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L14
.L13:
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
cmpl $64, %ebx
je .L31
cmpl $64, %ebx
ja .L16
leal -2(%rbx), %eax
cmpl $30, %eax
ja .L32
ja .L17
movl %eax, %eax
leaq .L19(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L19:
.long .L33-.L19
.long .L17-.L19
.long .L22-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L21-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L20-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L17-.L19
.long .L18-.L19
.text
.L42:
movl %edi, %ebp
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
cmpl $2, %ebp
jle .L12
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %ebp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl %r12d, %eax
imull %r12d, %eax
movl %eax, 12(%rsp)
leal 0(,%rax,8), %r15d
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
cmpl $0, 12(%rsp)
je .L13
jmp .L28
.L22:
movl $2, %ecx
movl $2, %ebx
jmp .L15
.L17:
movl $1, %ecx
movl $1, %ebx
.L15:
movl %ebp, %eax
movl $0, %edx
divl %ebx
movl %eax, 60(%rsp)
movl %ebp, %eax
movl $0, %edx
divl %ecx
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl %ecx, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L24:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %ebp, %ecx
movl %ebp, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L25
movl %eax, %r15d
movl $0, %ebx
jmp .L27
.L16:
cmpl $512, %ebx
je .L34
cmpl $512, %ebx
ja .L23
cmpl $128, %ebx
je .L35
cmpl $256, %ebx
jne .L44
movl $16, %ecx
movl $16, %ebx
jmp .L15
.L44:
movl $1, %ecx
movl $1, %ebx
jmp .L15
.L23:
cmpl $1024, %ebx
jne .L45
movl $32, %ecx
movl $32, %ebx
jmp .L15
.L45:
movl $1, %ecx
movl $1, %ebx
jmp .L15
.L21:
movl $2, %ecx
movl $4, %ebx
jmp .L15
.L20:
movl $4, %ecx
movl $4, %ebx
jmp .L15
.L18:
movl $4, %ecx
movl $8, %ebx
jmp .L15
.L31:
movl $8, %ecx
movl $8, %ebx
jmp .L15
.L32:
movl $1, %ecx
movl $1, %ebx
jmp .L15
.L33:
movl $1, %ecx
jmp .L15
.L34:
movl $16, %ecx
movl $32, %ebx
jmp .L15
.L35:
movl $8, %ecx
movl $16, %ebx
jmp .L15
.L43:
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9PartialMMPdS_S_jPdS_S_j
jmp .L24
.L26:
movsd (%r12,%rbx,8), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r15, %rbx
je .L25
.L27:
movl %ebx, %eax
movl $0, %edx
divl %ebp
testl %edx, %edx
jne .L26
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L25:
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9PartialMMPdS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9PartialMMPdS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.align 8
.LC1:
.long 0
.long 1074266112
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixCUDA.hip"
.globl _Z24__device_stub__PartialMMPdS_S_j # -- Begin function _Z24__device_stub__PartialMMPdS_S_j
.p2align 4, 0x90
.type _Z24__device_stub__PartialMMPdS_S_j,@function
_Z24__device_stub__PartialMMPdS_S_j: # @_Z24__device_stub__PartialMMPdS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9PartialMMPdS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__PartialMMPdS_S_j, .Lfunc_end0-_Z24__device_stub__PartialMMPdS_S_j
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
movl $1024, %ebx # imm = 0x400
movl $1024, %eax # imm = 0x400
cmpl $2, %edi
jl .LBB1_2
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB1_2:
movq %rax, 48(%rsp) # 8-byte Spill
cmpl $3, %ebp
jl .LBB1_4
# %bb.3:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB1_4:
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %ebx, %r13d
imull %r13d, %r13d
leal (,%r13,8), %ebp
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbp, 40(%rsp) # 8-byte Spill
movq %rbp, %rsi
callq hipMalloc
movl %r13d, %ebp
movq %r13, (%rsp) # 8-byte Spill
testl %r13d, %r13d
je .LBB1_7
# %bb.5: # %.lr.ph.preheader
leaq (,%rbp,8), %rdx
xorl %r13d, %r13d
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movabsq $4613937818241073152, %rcx # imm = 0x4008000000000000
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rax, (%r14,%r13,8)
movq %rcx, (%r15,%r13,8)
incq %r13
cmpq %r13, %rbp
jne .LBB1_6
.LBB1_7: # %._crit_edge
movq 24(%rsp), %rdi
movq %r14, %rsi
movq 40(%rsp), %r13 # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rax # 8-byte Reload
cmpl $63, %eax
jg .LBB1_11
# %bb.8: # %._crit_edge
addl $-2, %eax
cmpl $30, %eax
ja .LBB1_26
# %bb.9: # %._crit_edge
movabsq $4294967297, %r8 # imm = 0x100000001
jmpq *.LJTI1_0(,%rax,8)
.LBB1_10:
incq %r8
jmp .LBB1_27
.LBB1_11: # %._crit_edge
cmpl $255, %eax
jle .LBB1_16
# %bb.12: # %._crit_edge
cmpl $256, %eax # imm = 0x100
movabsq $4294967297, %r8 # imm = 0x100000001
je .LBB1_24
# %bb.13: # %._crit_edge
cmpl $512, %eax # imm = 0x200
movq (%rsp), %r13 # 8-byte Reload
je .LBB1_25
# %bb.14: # %._crit_edge
cmpl $1024, %eax # imm = 0x400
jne .LBB1_28
# %bb.15:
movabsq $137438953504, %r8 # imm = 0x2000000020
jmp .LBB1_28
.LBB1_16: # %._crit_edge
cmpl $64, %eax
movabsq $4294967297, %r8 # imm = 0x100000001
je .LBB1_23
# %bb.17: # %._crit_edge
cmpl $128, %eax
movq (%rsp), %r13 # 8-byte Reload
jne .LBB1_28
# %bb.18:
movabsq $34359738376, %r8 # imm = 0x800000008
addq $8, %r8
jmp .LBB1_28
.LBB1_19:
movabsq $17179869188, %r8 # imm = 0x400000004
addq $4, %r8
jmp .LBB1_27
.LBB1_20:
movabsq $8589934594, %r8 # imm = 0x200000002
jmp .LBB1_27
.LBB1_21:
movabsq $17179869188, %r8 # imm = 0x400000004
jmp .LBB1_27
.LBB1_22:
movabsq $8589934594, %r8 # imm = 0x200000002
addq $2, %r8
jmp .LBB1_27
.LBB1_23:
movabsq $34359738376, %r8 # imm = 0x800000008
jmp .LBB1_27
.LBB1_24:
movabsq $68719476752, %r8 # imm = 0x1000000010
.LBB1_27:
movq (%rsp), %r13 # 8-byte Reload
.LBB1_28:
movl %ebx, %eax
xorl %edx, %edx
divl %r8d
movl %eax, %edi
movq %r8, %rcx
shrq $32, %rcx
movl %ebx, %eax
xorl %edx, %edx
divl %ecx
# kill: def $eax killed $eax def $rax
shlq $32, %rax
orq %rax, %rdi
movl $1, %esi
movq %r8, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_30
# %bb.29:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %ebx, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9PartialMMPdS_S_j, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_30:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r12, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl %ebx, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
testl %r13d, %r13d
je .LBB1_35
# %bb.31: # %.lr.ph127.preheader
xorl %r13d, %r13d
jmp .LBB1_33
.p2align 4, 0x90
.LBB1_32: # in Loop: Header=BB1_33 Depth=1
movsd (%r12,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbp
je .LBB1_35
.LBB1_33: # %.lr.ph127
# =>This Inner Loop Header: Depth=1
movl %r13d, %eax
xorl %edx, %edx
divl %ebx
testl %edx, %edx
jne .LBB1_32
# %bb.34: # in Loop: Header=BB1_33 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_32
.LBB1_35: # %._crit_edge128
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_25:
.cfi_def_cfa_offset 224
movabsq $68719476752, %r8 # imm = 0x1000000010
addq $16, %r8
jmp .LBB1_28
.LBB1_26:
movq (%rsp), %r13 # 8-byte Reload
movabsq $4294967297, %r8 # imm = 0x100000001
jmp .LBB1_28
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI1_0:
.quad .LBB1_10
.quad .LBB1_27
.quad .LBB1_20
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_22
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_21
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_27
.quad .LBB1_19
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9PartialMMPdS_S_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9PartialMMPdS_S_j,@object # @_Z9PartialMMPdS_S_j
.section .rodata,"a",@progbits
.globl _Z9PartialMMPdS_S_j
.p2align 3, 0x0
_Z9PartialMMPdS_S_j:
.quad _Z24__device_stub__PartialMMPdS_S_j
.size _Z9PartialMMPdS_S_j, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Size\t\t%dx%d\n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Result:"
.size .L.str.1, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9PartialMMPdS_S_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__PartialMMPdS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9PartialMMPdS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
void init_matrix(int m, int n, double *mat, double value)
{
int i, j;
for (i = 0; i < m; i++)
for (j = 0; j < n; j++)
mat[i * m + j] = value;
}
void init_vector(int m, double *v, double value)
{
int i;
for (i = 0; i < m; i++)
v[i] = value;
}
double *malloc_2d(int m, int n)
{
if (m <= 0 || n <= 0)
return NULL;
double *mat = (double *)malloc(m * n * sizeof(double));
if (mat)
return mat;
return NULL;
}
void print_matrix(int m, int n, double *mat)
{
int i, j;
for (i = 0; i < m; i++)
{
for (j = 0; j < n; j++)
{
if (j == 0)
printf("|");
printf(" %.2f ", mat[i * m + j]);
if (j == n - 1)
printf("|");
}
printf("\n");
}
printf("\n\n");
}
void print_vector(int m, double* v)
{
int i;
for (i = 0; i < m; i++)
printf("%.3f\n", v[i]);
printf("\n\n");
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
void init_matrix(int m, int n, double *mat, double value)
{
int i, j;
for (i = 0; i < m; i++)
for (j = 0; j < n; j++)
mat[i * m + j] = value;
}
void init_vector(int m, double *v, double value)
{
int i;
for (i = 0; i < m; i++)
v[i] = value;
}
double *malloc_2d(int m, int n)
{
if (m <= 0 || n <= 0)
return NULL;
double *mat = (double *)malloc(m * n * sizeof(double));
if (mat)
return mat;
return NULL;
}
void print_matrix(int m, int n, double *mat)
{
int i, j;
for (i = 0; i < m; i++)
{
for (j = 0; j < n; j++)
{
if (j == 0)
printf("|");
printf(" %.2f ", mat[i * m + j]);
if (j == n - 1)
printf("|");
}
printf("\n");
}
printf("\n\n");
}
void print_vector(int m, double* v)
{
int i;
for (i = 0; i < m; i++)
printf("%.3f\n", v[i]);
printf("\n\n");
} | .file "tmpxft_0017efbd_00000000-6_matrixlib.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11init_matrixiiPdd
.type _Z11init_matrixiiPdd, @function
_Z11init_matrixiiPdd:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movl $0, %r9d
movl $0, %r8d
movslq %esi, %r10
jmp .L5
.L7:
movslq %r9d, %rcx
leaq (%rdx,%rcx,8), %rax
addq %r10, %rcx
leaq (%rdx,%rcx,8), %rcx
.L6:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r8d
addl %edi, %r9d
cmpl %r8d, %edi
je .L3
.L5:
testl %esi, %esi
jg .L7
jmp .L8
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z11init_matrixiiPdd, .-_Z11init_matrixiiPdd
.globl _Z11init_vectoriPdd
.type _Z11init_vectoriPdd, @function
_Z11init_vectoriPdd:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L10
movq %rsi, %rax
movslq %edi, %rdi
leaq (%rsi,%rdi,8), %rdx
.L12:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L12
.L10:
ret
.cfi_endproc
.LFE2058:
.size _Z11init_vectoriPdd, .-_Z11init_vectoriPdd
.globl _Z9malloc_2dii
.type _Z9malloc_2dii, @function
_Z9malloc_2dii:
.LFB2059:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L16
testl %esi, %esi
jle .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
imull %esi, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
movl $0, %eax
ret
.cfi_endproc
.LFE2059:
.size _Z9malloc_2dii, .-_Z9malloc_2dii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "|"
.LC1:
.string " %.2f "
.LC2:
.string "\n"
.LC3:
.string "\n\n"
.text
.globl _Z12print_matrixiiPd
.type _Z12print_matrixiiPd, @function
_Z12print_matrixiiPd:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %esi, 8(%rsp)
movq %rdx, 24(%rsp)
testl %edi, %edi
jle .L22
movl $0, 12(%rsp)
movl $0, %ebp
movslq %esi, %r15
leaq .LC1(%rip), %r14
movl %edi, 20(%rsp)
jmp .L23
.L24:
movsd 0(%r13,%rbx,8), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl %ebp, %r12d
je .L31
.L25:
addq $1, %rbx
cmpq %r15, %rbx
je .L32
.L26:
movl %ebx, %ebp
testl %ebx, %ebx
jne .L24
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L31:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L32:
movl 16(%rsp), %ebp
.L28:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 20(%rsp), %ecx
addl %ecx, 12(%rsp)
cmpl %ebp, %ecx
je .L22
.L23:
cmpl $0, 8(%rsp)
jle .L28
movslq 12(%rsp), %rax
movq 24(%rsp), %rdx
leaq (%rdx,%rax,8), %r13
movl $0, %ebx
movl 8(%rsp), %eax
leal -1(%rax), %r12d
movl %ebp, 16(%rsp)
jmp .L26
.L22:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12print_matrixiiPd, .-_Z12print_matrixiiPd
.section .rodata.str1.1
.LC4:
.string "%.3f\n"
.text
.globl _Z12print_vectoriPd
.type _Z12print_vectoriPd, @function
_Z12print_vectoriPd:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %edi, %edi
jle .L34
movq %rsi, %rbx
movslq %edi, %rdi
leaq (%rsi,%rdi,8), %r12
leaq .LC4(%rip), %rbp
.L35:
movsd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L35
.L34:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z12print_vectoriPd, .-_Z12print_vectoriPd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
void init_matrix(int m, int n, double *mat, double value)
{
int i, j;
for (i = 0; i < m; i++)
for (j = 0; j < n; j++)
mat[i * m + j] = value;
}
void init_vector(int m, double *v, double value)
{
int i;
for (i = 0; i < m; i++)
v[i] = value;
}
double *malloc_2d(int m, int n)
{
if (m <= 0 || n <= 0)
return NULL;
double *mat = (double *)malloc(m * n * sizeof(double));
if (mat)
return mat;
return NULL;
}
void print_matrix(int m, int n, double *mat)
{
int i, j;
for (i = 0; i < m; i++)
{
for (j = 0; j < n; j++)
{
if (j == 0)
printf("|");
printf(" %.2f ", mat[i * m + j]);
if (j == n - 1)
printf("|");
}
printf("\n");
}
printf("\n\n");
}
void print_vector(int m, double* v)
{
int i;
for (i = 0; i < m; i++)
printf("%.3f\n", v[i]);
printf("\n\n");
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
void init_matrix(int m, int n, double *mat, double value)
{
int i, j;
for (i = 0; i < m; i++)
for (j = 0; j < n; j++)
mat[i * m + j] = value;
}
void init_vector(int m, double *v, double value)
{
int i;
for (i = 0; i < m; i++)
v[i] = value;
}
double *malloc_2d(int m, int n)
{
if (m <= 0 || n <= 0)
return NULL;
double *mat = (double *)malloc(m * n * sizeof(double));
if (mat)
return mat;
return NULL;
}
void print_matrix(int m, int n, double *mat)
{
int i, j;
for (i = 0; i < m; i++)
{
for (j = 0; j < n; j++)
{
if (j == 0)
printf("|");
printf(" %.2f ", mat[i * m + j]);
if (j == n - 1)
printf("|");
}
printf("\n");
}
printf("\n\n");
}
void print_vector(int m, double* v)
{
int i;
for (i = 0; i < m; i++)
printf("%.3f\n", v[i]);
printf("\n\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
void init_matrix(int m, int n, double *mat, double value)
{
int i, j;
for (i = 0; i < m; i++)
for (j = 0; j < n; j++)
mat[i * m + j] = value;
}
void init_vector(int m, double *v, double value)
{
int i;
for (i = 0; i < m; i++)
v[i] = value;
}
double *malloc_2d(int m, int n)
{
if (m <= 0 || n <= 0)
return NULL;
double *mat = (double *)malloc(m * n * sizeof(double));
if (mat)
return mat;
return NULL;
}
void print_matrix(int m, int n, double *mat)
{
int i, j;
for (i = 0; i < m; i++)
{
for (j = 0; j < n; j++)
{
if (j == 0)
printf("|");
printf(" %.2f ", mat[i * m + j]);
if (j == n - 1)
printf("|");
}
printf("\n");
}
printf("\n\n");
}
void print_vector(int m, double* v)
{
int i;
for (i = 0; i < m; i++)
printf("%.3f\n", v[i]);
printf("\n\n");
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
void init_matrix(int m, int n, double *mat, double value)
{
int i, j;
for (i = 0; i < m; i++)
for (j = 0; j < n; j++)
mat[i * m + j] = value;
}
void init_vector(int m, double *v, double value)
{
int i;
for (i = 0; i < m; i++)
v[i] = value;
}
double *malloc_2d(int m, int n)
{
if (m <= 0 || n <= 0)
return NULL;
double *mat = (double *)malloc(m * n * sizeof(double));
if (mat)
return mat;
return NULL;
}
void print_matrix(int m, int n, double *mat)
{
int i, j;
for (i = 0; i < m; i++)
{
for (j = 0; j < n; j++)
{
if (j == 0)
printf("|");
printf(" %.2f ", mat[i * m + j]);
if (j == n - 1)
printf("|");
}
printf("\n");
}
printf("\n\n");
}
void print_vector(int m, double* v)
{
int i;
for (i = 0; i < m; i++)
printf("%.3f\n", v[i]);
printf("\n\n");
} | .text
.file "matrixlib.hip"
.globl _Z11init_matrixiiPdd # -- Begin function _Z11init_matrixiiPdd
.p2align 4, 0x90
.type _Z11init_matrixiiPdd,@function
_Z11init_matrixiiPdd: # @_Z11init_matrixiiPdd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edi, %eax
movl %esi, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r9
addl %edi, %r8d
cmpq %rax, %r9
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %esi, %esi
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r8d, %r10d
leaq (%rdx,%r10,8), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd %xmm0, (%r10,%r11,8)
incq %r11
cmpq %r11, %rcx
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge14
retq
.Lfunc_end0:
.size _Z11init_matrixiiPdd, .Lfunc_end0-_Z11init_matrixiiPdd
.cfi_endproc
# -- End function
.globl _Z11init_vectoriPdd # -- Begin function _Z11init_vectoriPdd
.p2align 4, 0x90
.type _Z11init_vectoriPdd,@function
_Z11init_vectoriPdd: # @_Z11init_vectoriPdd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd %xmm0, (%rsi,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11init_vectoriPdd, .Lfunc_end1-_Z11init_vectoriPdd
.cfi_endproc
# -- End function
.globl _Z9malloc_2dii # -- Begin function _Z9malloc_2dii
.p2align 4, 0x90
.type _Z9malloc_2dii,@function
_Z9malloc_2dii: # @_Z9malloc_2dii
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_2
# %bb.1:
testl %esi, %esi
jle .LBB2_2
# %bb.3:
imull %edi, %esi
movslq %esi, %rdi
shlq $3, %rdi
jmp malloc # TAILCALL
.LBB2_2:
xorl %eax, %eax
retq
.Lfunc_end2:
.size _Z9malloc_2dii, .Lfunc_end2-_Z9malloc_2dii
.cfi_endproc
# -- End function
.globl _Z12print_matrixiiPd # -- Begin function _Z12print_matrixiiPd
.p2align 4, 0x90
.type _Z12print_matrixiiPd,@function
_Z12print_matrixiiPd: # @_Z12print_matrixiiPd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 24(%rsp) # 8-byte Spill
# kill: def $esi killed $esi def $rsi
movq %rsi, 16(%rsp) # 8-byte Spill
movl %edi, 12(%rsp) # 4-byte Spill
testl %edi, %edi
jle .LBB3_10
# %bb.1: # %.preheader.lr.ph
movq 16(%rsp), %rax # 8-byte Reload
leal -1(%rax), %r15d
movl 12(%rsp), %ecx # 4-byte Reload
movq %rcx, 32(%rsp) # 8-byte Spill
movl %eax, %r13d
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_9: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl 12(%rsp), %ebx # 4-byte Folded Reload
cmpq 32(%rsp), %r14 # 8-byte Folded Reload
je .LBB3_10
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, 16(%rsp) # 4-byte Folded Reload
jle .LBB3_9
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %ebx, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r12
xorl %ebp, %ebp
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_4 Depth=2
incq %rbp
cmpq %rbp, %r13
je .LBB3_9
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
testq %rbp, %rbp
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movl $124, %edi
callq putchar@PLT
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
movsd (%r12,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
cmpq %rbp, %r15
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_4 Depth=2
movl $124, %edi
callq putchar@PLT
jmp .LBB3_8
.LBB3_10: # %._crit_edge19
movl $.Lstr.1, %edi
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z12print_matrixiiPd, .Lfunc_end3-_Z12print_matrixiiPd
.cfi_endproc
# -- End function
.globl _Z12print_vectoriPd # -- Begin function _Z12print_vectoriPd
.p2align 4, 0x90
.type _Z12print_vectoriPd,@function
_Z12print_vectoriPd: # @_Z12print_vectoriPd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB4_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB4_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_4: # %._crit_edge
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z12print_vectoriPd, .Lfunc_end4-_Z12print_vectoriPd
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " %.2f "
.size .L.str.1, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.3f\n"
.size .L.str.4, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017efbd_00000000-6_matrixlib.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11init_matrixiiPdd
.type _Z11init_matrixiiPdd, @function
_Z11init_matrixiiPdd:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movl $0, %r9d
movl $0, %r8d
movslq %esi, %r10
jmp .L5
.L7:
movslq %r9d, %rcx
leaq (%rdx,%rcx,8), %rax
addq %r10, %rcx
leaq (%rdx,%rcx,8), %rcx
.L6:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r8d
addl %edi, %r9d
cmpl %r8d, %edi
je .L3
.L5:
testl %esi, %esi
jg .L7
jmp .L8
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z11init_matrixiiPdd, .-_Z11init_matrixiiPdd
.globl _Z11init_vectoriPdd
.type _Z11init_vectoriPdd, @function
_Z11init_vectoriPdd:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L10
movq %rsi, %rax
movslq %edi, %rdi
leaq (%rsi,%rdi,8), %rdx
.L12:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L12
.L10:
ret
.cfi_endproc
.LFE2058:
.size _Z11init_vectoriPdd, .-_Z11init_vectoriPdd
.globl _Z9malloc_2dii
.type _Z9malloc_2dii, @function
_Z9malloc_2dii:
.LFB2059:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L16
testl %esi, %esi
jle .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
imull %esi, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
movl $0, %eax
ret
.cfi_endproc
.LFE2059:
.size _Z9malloc_2dii, .-_Z9malloc_2dii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "|"
.LC1:
.string " %.2f "
.LC2:
.string "\n"
.LC3:
.string "\n\n"
.text
.globl _Z12print_matrixiiPd
.type _Z12print_matrixiiPd, @function
_Z12print_matrixiiPd:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %esi, 8(%rsp)
movq %rdx, 24(%rsp)
testl %edi, %edi
jle .L22
movl $0, 12(%rsp)
movl $0, %ebp
movslq %esi, %r15
leaq .LC1(%rip), %r14
movl %edi, 20(%rsp)
jmp .L23
.L24:
movsd 0(%r13,%rbx,8), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl %ebp, %r12d
je .L31
.L25:
addq $1, %rbx
cmpq %r15, %rbx
je .L32
.L26:
movl %ebx, %ebp
testl %ebx, %ebx
jne .L24
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L31:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L32:
movl 16(%rsp), %ebp
.L28:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 20(%rsp), %ecx
addl %ecx, 12(%rsp)
cmpl %ebp, %ecx
je .L22
.L23:
cmpl $0, 8(%rsp)
jle .L28
movslq 12(%rsp), %rax
movq 24(%rsp), %rdx
leaq (%rdx,%rax,8), %r13
movl $0, %ebx
movl 8(%rsp), %eax
leal -1(%rax), %r12d
movl %ebp, 16(%rsp)
jmp .L26
.L22:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12print_matrixiiPd, .-_Z12print_matrixiiPd
.section .rodata.str1.1
.LC4:
.string "%.3f\n"
.text
.globl _Z12print_vectoriPd
.type _Z12print_vectoriPd, @function
_Z12print_vectoriPd:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %edi, %edi
jle .L34
movq %rsi, %rbx
movslq %edi, %rdi
leaq (%rsi,%rdi,8), %r12
leaq .LC4(%rip), %rbp
.L35:
movsd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L35
.L34:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z12print_vectoriPd, .-_Z12print_vectoriPd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixlib.hip"
.globl _Z11init_matrixiiPdd # -- Begin function _Z11init_matrixiiPdd
.p2align 4, 0x90
.type _Z11init_matrixiiPdd,@function
_Z11init_matrixiiPdd: # @_Z11init_matrixiiPdd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edi, %eax
movl %esi, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r9
addl %edi, %r8d
cmpq %rax, %r9
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %esi, %esi
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r8d, %r10d
leaq (%rdx,%r10,8), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd %xmm0, (%r10,%r11,8)
incq %r11
cmpq %r11, %rcx
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge14
retq
.Lfunc_end0:
.size _Z11init_matrixiiPdd, .Lfunc_end0-_Z11init_matrixiiPdd
.cfi_endproc
# -- End function
.globl _Z11init_vectoriPdd # -- Begin function _Z11init_vectoriPdd
.p2align 4, 0x90
.type _Z11init_vectoriPdd,@function
_Z11init_vectoriPdd: # @_Z11init_vectoriPdd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd %xmm0, (%rsi,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11init_vectoriPdd, .Lfunc_end1-_Z11init_vectoriPdd
.cfi_endproc
# -- End function
.globl _Z9malloc_2dii # -- Begin function _Z9malloc_2dii
.p2align 4, 0x90
.type _Z9malloc_2dii,@function
_Z9malloc_2dii: # @_Z9malloc_2dii
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_2
# %bb.1:
testl %esi, %esi
jle .LBB2_2
# %bb.3:
imull %edi, %esi
movslq %esi, %rdi
shlq $3, %rdi
jmp malloc # TAILCALL
.LBB2_2:
xorl %eax, %eax
retq
.Lfunc_end2:
.size _Z9malloc_2dii, .Lfunc_end2-_Z9malloc_2dii
.cfi_endproc
# -- End function
.globl _Z12print_matrixiiPd # -- Begin function _Z12print_matrixiiPd
.p2align 4, 0x90
.type _Z12print_matrixiiPd,@function
_Z12print_matrixiiPd: # @_Z12print_matrixiiPd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 24(%rsp) # 8-byte Spill
# kill: def $esi killed $esi def $rsi
movq %rsi, 16(%rsp) # 8-byte Spill
movl %edi, 12(%rsp) # 4-byte Spill
testl %edi, %edi
jle .LBB3_10
# %bb.1: # %.preheader.lr.ph
movq 16(%rsp), %rax # 8-byte Reload
leal -1(%rax), %r15d
movl 12(%rsp), %ecx # 4-byte Reload
movq %rcx, 32(%rsp) # 8-byte Spill
movl %eax, %r13d
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_9: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl 12(%rsp), %ebx # 4-byte Folded Reload
cmpq 32(%rsp), %r14 # 8-byte Folded Reload
je .LBB3_10
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, 16(%rsp) # 4-byte Folded Reload
jle .LBB3_9
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %ebx, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r12
xorl %ebp, %ebp
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_4 Depth=2
incq %rbp
cmpq %rbp, %r13
je .LBB3_9
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
testq %rbp, %rbp
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movl $124, %edi
callq putchar@PLT
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
movsd (%r12,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
cmpq %rbp, %r15
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_4 Depth=2
movl $124, %edi
callq putchar@PLT
jmp .LBB3_8
.LBB3_10: # %._crit_edge19
movl $.Lstr.1, %edi
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z12print_matrixiiPd, .Lfunc_end3-_Z12print_matrixiiPd
.cfi_endproc
# -- End function
.globl _Z12print_vectoriPd # -- Begin function _Z12print_vectoriPd
.p2align 4, 0x90
.type _Z12print_vectoriPd,@function
_Z12print_vectoriPd: # @_Z12print_vectoriPd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB4_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB4_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_4: # %._crit_edge
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z12print_vectoriPd, .Lfunc_end4-_Z12print_vectoriPd
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " %.2f "
.size .L.str.1, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.3f\n"
.size .L.str.4, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define min(X,Y) ((X) < (Y) ? (X) : (Y))
__global__ void accel_update(int nx, int ny, double dx2inv, double dy2inv, double* d_z, double* d_a) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
double ax, ay;
int r = i / nx;
int c = i % nx;
if(i < nx*ny) {
if(r<ny-1 && r>0 && c<nx-1 && c>0){
ax = (d_z[i+nx]+d_z[i-nx]-2.0*d_z[i])*dx2inv;
ay = (d_z[i+1]+d_z[i-1]-2.0*d_z[i])*dy2inv;
d_a[i] = (ax+ay)/2;
}
else
d_a[i] = 0.0;
}
} | code for sm_80
Function : _Z12accel_updateiiddPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x160] ; /* 0x0000580000057a13 */
/* 0x000fe20000000000 */
/*0090*/ UIADD3 UR6, UR5, -0x1, URZ ; /* 0xffffffff05067890 */
/* 0x000fe2000fffe03f */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00d0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fce000fffe03f */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0180*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01a0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*01d0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0210*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0220*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff03aa12 */
/* 0x000fc800078e33ff */
/*0230*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f04270 */
/*0240*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0a03 */
/*0250*/ ISETP.LT.AND P0, PT, R3, UR6, P0 ; /* 0x0000000603007c0c */
/* 0x000fe20008701270 */
/*0260*/ IMAD R2, R5, c[0x0][0x160], R0 ; /* 0x0000580005027a24 */
/* 0x000fe200078e0200 */
/*0270*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0280*/ ISETP.LT.AND P0, PT, R2, UR4, P0 ; /* 0x0000000402007c0c */
/* 0x000fc80008701270 */
/*0290*/ ISETP.GT.AND P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20000704270 */
/*02a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fd800078e0209 */
/*02b0*/ @!P0 STG.E.64 [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e2000c101b06 */
/*02c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02d0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*02e0*/ LEA R10, P0, R0.reuse, c[0x0][0x178], 0x3 ; /* 0x00005e00000a7a11 */
/* 0x040fe400078018ff */
/*02f0*/ IADD3 R6, R0.reuse, -c[0x0][0x160], RZ ; /* 0x8000580000067a10 */
/* 0x040fe40007ffe0ff */
/*0300*/ IADD3 R4, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x040fe40007ffe0ff */
/*0310*/ LEA.HI.X R11, R0, c[0x0][0x17c], R5, 0x3, P0 ; /* 0x00005f00000b7a11 */
/* 0x000fe200000f1c05 */
/*0320*/ IMAD.WIDE R6, R6, R9, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0209 */
/*0330*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e0209 */
/*0340*/ LDG.E.64 R12, [R10.64+-0x8] ; /* 0xfffff8060a0c7981 */
/* 0x000ea8000c1e1b00 */
/*0350*/ LDG.E.64 R14, [R10.64+0x8] ; /* 0x000008060a0e7981 */
/* 0x000ea8000c1e1b00 */
/*0360*/ LDG.E.64 R8, [R10.64] ; /* 0x000000060a087981 */
/* 0x000ee8000c1e1b00 */
/*0370*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000f28000c1e1b00 */
/*0380*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f22000c1e1b00 */
/*0390*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x004fc8000000000e */
/*03a0*/ DADD R12, R8, R8 ; /* 0x00000000080c7229 */
/* 0x008e4c0000000008 */
/*03b0*/ DADD R14, -R12, R14 ; /* 0x000000000c0e7229 */
/* 0x002e48000000010e */
/*03c0*/ DADD R8, R6, R4 ; /* 0x0000000006087229 */
/* 0x010e880000000004 */
/*03d0*/ DMUL R14, R14, c[0x0][0x170] ; /* 0x00005c000e0e7a28 */
/* 0x002fc80000000000 */
/*03e0*/ DADD R8, R8, -R12 ; /* 0x0000000008087229 */
/* 0x004e4c000000080c */
/*03f0*/ DFMA R8, R8, c[0x0][0x168], R14 ; /* 0x00005a0008087a2b */
/* 0x002e4c000000000e */
/*0400*/ DMUL R8, R8, 0.5 ; /* 0x3fe0000008087828 */
/* 0x002e4e0000000000 */
/*0410*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b06 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define min(X,Y) ((X) < (Y) ? (X) : (Y))
__global__ void accel_update(int nx, int ny, double dx2inv, double dy2inv, double* d_z, double* d_a) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
double ax, ay;
int r = i / nx;
int c = i % nx;
if(i < nx*ny) {
if(r<ny-1 && r>0 && c<nx-1 && c>0){
ax = (d_z[i+nx]+d_z[i-nx]-2.0*d_z[i])*dx2inv;
ay = (d_z[i+1]+d_z[i-1]-2.0*d_z[i])*dy2inv;
d_a[i] = (ax+ay)/2;
}
else
d_a[i] = 0.0;
}
} | .file "tmpxft_000bfcc2_00000000-6_accel_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_
.type _Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_, @function
_Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12accel_updateiiddPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_, .-_Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_
.globl _Z12accel_updateiiddPdS_
.type _Z12accel_updateiiddPdS_, @function
_Z12accel_updateiiddPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12accel_updateiiddPdS_, .-_Z12accel_updateiiddPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12accel_updateiiddPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12accel_updateiiddPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define min(X,Y) ((X) < (Y) ? (X) : (Y))
__global__ void accel_update(int nx, int ny, double dx2inv, double dy2inv, double* d_z, double* d_a) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
double ax, ay;
int r = i / nx;
int c = i % nx;
if(i < nx*ny) {
if(r<ny-1 && r>0 && c<nx-1 && c>0){
ax = (d_z[i+nx]+d_z[i-nx]-2.0*d_z[i])*dx2inv;
ay = (d_z[i+1]+d_z[i-1]-2.0*d_z[i])*dy2inv;
d_a[i] = (ax+ay)/2;
}
else
d_a[i] = 0.0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define min(X,Y) ((X) < (Y) ? (X) : (Y))
__global__ void accel_update(int nx, int ny, double dx2inv, double dy2inv, double* d_z, double* d_a) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
double ax, ay;
int r = i / nx;
int c = i % nx;
if(i < nx*ny) {
if(r<ny-1 && r>0 && c<nx-1 && c>0){
ax = (d_z[i+nx]+d_z[i-nx]-2.0*d_z[i])*dx2inv;
ay = (d_z[i+1]+d_z[i-1]-2.0*d_z[i])*dy2inv;
d_a[i] = (ax+ay)/2;
}
else
d_a[i] = 0.0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define min(X,Y) ((X) < (Y) ? (X) : (Y))
__global__ void accel_update(int nx, int ny, double dx2inv, double dy2inv, double* d_z, double* d_a) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
double ax, ay;
int r = i / nx;
int c = i % nx;
if(i < nx*ny) {
if(r<ny-1 && r>0 && c<nx-1 && c>0){
ax = (d_z[i+nx]+d_z[i-nx]-2.0*d_z[i])*dx2inv;
ay = (d_z[i+1]+d_z[i-1]-2.0*d_z[i])*dy2inv;
d_a[i] = (ax+ay)/2;
}
else
d_a[i] = 0.0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12accel_updateiiddPdS_
.globl _Z12accel_updateiiddPdS_
.p2align 8
.type _Z12accel_updateiiddPdS_,@function
_Z12accel_updateiiddPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_ashr_i32 s2, s4, 31
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s3, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s2
v_add_nc_u32_e32 v3, v1, v4
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s6, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v3, v4
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v4, s2, v4
s_add_i32 s2, s5, -1
s_mov_b32 s5, 0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v5, v0, 0
v_mul_lo_u32 v0, v3, s3
v_add_nc_u32_e32 v2, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v5, v0
v_subrev_nc_u32_e32 v5, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_dual_cndmask_b32 v0, v0, v5 :: v_dual_add_nc_u32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e32 v0, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s2, 0, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, s2, -1
s_and_saveexec_b32 s3, s2
v_mul_lo_u32 v0, v0, s4
s_add_i32 s2, s4, -1
s_and_not1_b32 s6, s6, exec_lo
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_cmp_le_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s6, s2
s_or_b32 exec_lo, exec_lo, s3
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s7, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s7
s_mov_b64 s[2:3], 0
s_and_not1_b32 s5, s5, exec_lo
s_or_b32 exec_lo, exec_lo, s6
v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
s_and_saveexec_b32 s2, s5
s_cbranch_execz .LBB0_7
s_load_b64 s[6:7], s[0:1], 0x18
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v9, s4, v1
v_subrev_nc_u32_e32 v11, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_clause 0x1
global_load_b128 v[3:6], v[7:8], off
global_load_b64 v[7:8], v[7:8], off offset:-8
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
s_clause 0x1
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[11:12], v[11:12], off
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt vmcnt(2)
v_add_f64 v[5:6], v[5:6], v[7:8]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[3:4], -2.0, v[5:6]
v_fma_f64 v[3:4], v[3:4], -2.0, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[5:6], v[5:6], s[6:7]
v_fma_f64 v[3:4], v[3:4], s[4:5], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], 0.5
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x20
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12accel_updateiiddPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12accel_updateiiddPdS_, .Lfunc_end0-_Z12accel_updateiiddPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12accel_updateiiddPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12accel_updateiiddPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define min(X,Y) ((X) < (Y) ? (X) : (Y))
__global__ void accel_update(int nx, int ny, double dx2inv, double dy2inv, double* d_z, double* d_a) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
double ax, ay;
int r = i / nx;
int c = i % nx;
if(i < nx*ny) {
if(r<ny-1 && r>0 && c<nx-1 && c>0){
ax = (d_z[i+nx]+d_z[i-nx]-2.0*d_z[i])*dx2inv;
ay = (d_z[i+1]+d_z[i-1]-2.0*d_z[i])*dy2inv;
d_a[i] = (ax+ay)/2;
}
else
d_a[i] = 0.0;
}
} | .text
.file "accel_update.hip"
.globl _Z27__device_stub__accel_updateiiddPdS_ # -- Begin function _Z27__device_stub__accel_updateiiddPdS_
.p2align 4, 0x90
.type _Z27__device_stub__accel_updateiiddPdS_,@function
_Z27__device_stub__accel_updateiiddPdS_: # @_Z27__device_stub__accel_updateiiddPdS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12accel_updateiiddPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__accel_updateiiddPdS_, .Lfunc_end0-_Z27__device_stub__accel_updateiiddPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12accel_updateiiddPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12accel_updateiiddPdS_,@object # @_Z12accel_updateiiddPdS_
.section .rodata,"a",@progbits
.globl _Z12accel_updateiiddPdS_
.p2align 3, 0x0
_Z12accel_updateiiddPdS_:
.quad _Z27__device_stub__accel_updateiiddPdS_
.size _Z12accel_updateiiddPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12accel_updateiiddPdS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__accel_updateiiddPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12accel_updateiiddPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12accel_updateiiddPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x160] ; /* 0x0000580000057a13 */
/* 0x000fe20000000000 */
/*0090*/ UIADD3 UR6, UR5, -0x1, URZ ; /* 0xffffffff05067890 */
/* 0x000fe2000fffe03f */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00d0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fce000fffe03f */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0180*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01a0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*01d0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0210*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0220*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff03aa12 */
/* 0x000fc800078e33ff */
/*0230*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f04270 */
/*0240*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0a03 */
/*0250*/ ISETP.LT.AND P0, PT, R3, UR6, P0 ; /* 0x0000000603007c0c */
/* 0x000fe20008701270 */
/*0260*/ IMAD R2, R5, c[0x0][0x160], R0 ; /* 0x0000580005027a24 */
/* 0x000fe200078e0200 */
/*0270*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0280*/ ISETP.LT.AND P0, PT, R2, UR4, P0 ; /* 0x0000000402007c0c */
/* 0x000fc80008701270 */
/*0290*/ ISETP.GT.AND P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20000704270 */
/*02a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fd800078e0209 */
/*02b0*/ @!P0 STG.E.64 [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e2000c101b06 */
/*02c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02d0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*02e0*/ LEA R10, P0, R0.reuse, c[0x0][0x178], 0x3 ; /* 0x00005e00000a7a11 */
/* 0x040fe400078018ff */
/*02f0*/ IADD3 R6, R0.reuse, -c[0x0][0x160], RZ ; /* 0x8000580000067a10 */
/* 0x040fe40007ffe0ff */
/*0300*/ IADD3 R4, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x040fe40007ffe0ff */
/*0310*/ LEA.HI.X R11, R0, c[0x0][0x17c], R5, 0x3, P0 ; /* 0x00005f00000b7a11 */
/* 0x000fe200000f1c05 */
/*0320*/ IMAD.WIDE R6, R6, R9, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0209 */
/*0330*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e0209 */
/*0340*/ LDG.E.64 R12, [R10.64+-0x8] ; /* 0xfffff8060a0c7981 */
/* 0x000ea8000c1e1b00 */
/*0350*/ LDG.E.64 R14, [R10.64+0x8] ; /* 0x000008060a0e7981 */
/* 0x000ea8000c1e1b00 */
/*0360*/ LDG.E.64 R8, [R10.64] ; /* 0x000000060a087981 */
/* 0x000ee8000c1e1b00 */
/*0370*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000f28000c1e1b00 */
/*0380*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f22000c1e1b00 */
/*0390*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x004fc8000000000e */
/*03a0*/ DADD R12, R8, R8 ; /* 0x00000000080c7229 */
/* 0x008e4c0000000008 */
/*03b0*/ DADD R14, -R12, R14 ; /* 0x000000000c0e7229 */
/* 0x002e48000000010e */
/*03c0*/ DADD R8, R6, R4 ; /* 0x0000000006087229 */
/* 0x010e880000000004 */
/*03d0*/ DMUL R14, R14, c[0x0][0x170] ; /* 0x00005c000e0e7a28 */
/* 0x002fc80000000000 */
/*03e0*/ DADD R8, R8, -R12 ; /* 0x0000000008087229 */
/* 0x004e4c000000080c */
/*03f0*/ DFMA R8, R8, c[0x0][0x168], R14 ; /* 0x00005a0008087a2b */
/* 0x002e4c000000000e */
/*0400*/ DMUL R8, R8, 0.5 ; /* 0x3fe0000008087828 */
/* 0x002e4e0000000000 */
/*0410*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b06 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12accel_updateiiddPdS_
.globl _Z12accel_updateiiddPdS_
.p2align 8
.type _Z12accel_updateiiddPdS_,@function
_Z12accel_updateiiddPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_ashr_i32 s2, s4, 31
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s3, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s2
v_add_nc_u32_e32 v3, v1, v4
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s6, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v3, v4
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v4, s2, v4
s_add_i32 s2, s5, -1
s_mov_b32 s5, 0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v5, v0, 0
v_mul_lo_u32 v0, v3, s3
v_add_nc_u32_e32 v2, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v5, v0
v_subrev_nc_u32_e32 v5, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_dual_cndmask_b32 v0, v0, v5 :: v_dual_add_nc_u32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e32 v0, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s2, 0, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, s2, -1
s_and_saveexec_b32 s3, s2
v_mul_lo_u32 v0, v0, s4
s_add_i32 s2, s4, -1
s_and_not1_b32 s6, s6, exec_lo
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_cmp_le_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s6, s2
s_or_b32 exec_lo, exec_lo, s3
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s7, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s7
s_mov_b64 s[2:3], 0
s_and_not1_b32 s5, s5, exec_lo
s_or_b32 exec_lo, exec_lo, s6
v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
s_and_saveexec_b32 s2, s5
s_cbranch_execz .LBB0_7
s_load_b64 s[6:7], s[0:1], 0x18
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v9, s4, v1
v_subrev_nc_u32_e32 v11, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_clause 0x1
global_load_b128 v[3:6], v[7:8], off
global_load_b64 v[7:8], v[7:8], off offset:-8
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
s_clause 0x1
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[11:12], v[11:12], off
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt vmcnt(2)
v_add_f64 v[5:6], v[5:6], v[7:8]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[3:4], -2.0, v[5:6]
v_fma_f64 v[3:4], v[3:4], -2.0, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[5:6], v[5:6], s[6:7]
v_fma_f64 v[3:4], v[3:4], s[4:5], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], 0.5
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x20
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12accel_updateiiddPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12accel_updateiiddPdS_, .Lfunc_end0-_Z12accel_updateiiddPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12accel_updateiiddPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12accel_updateiiddPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bfcc2_00000000-6_accel_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_
.type _Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_, @function
_Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12accel_updateiiddPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_, .-_Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_
.globl _Z12accel_updateiiddPdS_
.type _Z12accel_updateiiddPdS_, @function
_Z12accel_updateiiddPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12accel_updateiiddPdS_iiddPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12accel_updateiiddPdS_, .-_Z12accel_updateiiddPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12accel_updateiiddPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12accel_updateiiddPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "accel_update.hip"
.globl _Z27__device_stub__accel_updateiiddPdS_ # -- Begin function _Z27__device_stub__accel_updateiiddPdS_
.p2align 4, 0x90
.type _Z27__device_stub__accel_updateiiddPdS_,@function
_Z27__device_stub__accel_updateiiddPdS_: # @_Z27__device_stub__accel_updateiiddPdS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12accel_updateiiddPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__accel_updateiiddPdS_, .Lfunc_end0-_Z27__device_stub__accel_updateiiddPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12accel_updateiiddPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12accel_updateiiddPdS_,@object # @_Z12accel_updateiiddPdS_
.section .rodata,"a",@progbits
.globl _Z12accel_updateiiddPdS_
.p2align 3, 0x0
_Z12accel_updateiiddPdS_:
.quad _Z27__device_stub__accel_updateiiddPdS_
.size _Z12accel_updateiiddPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12accel_updateiiddPdS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__accel_updateiiddPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12accel_updateiiddPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sec_mean_cuda_(int nProposal, int C, float *inp, int *offsets, float *out){
for(int p_id = blockIdx.x; p_id < nProposal; p_id += gridDim.x){
int start = offsets[p_id];
int end = offsets[p_id + 1];
float count = (float)(end - start);
for(int plane = threadIdx.x; plane < C; plane += blockDim.x){
float mean = 0;
for(int i = start; i < end; i++){
mean += (inp[i * C + plane] / count);
}
out[p_id * C + plane] = mean;
}
}
} | code for sm_80
Function : _Z14sec_mean_cuda_iiPfPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x164], PT ; /* 0x0000590002007a0c */
/* 0x001fe20003f06270 */
/*0070*/ BSSY B0, 0xb30 ; /* 0x00000ab000007945 */
/* 0x000fd80003800000 */
/*0080*/ @P0 BRA 0xb20 ; /* 0x00000a9000000947 */
/* 0x002fea0003800000 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD.WIDE R8, R3, R7, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fca00078e0207 */
/*00b0*/ LDG.E R4, [R8.64+0x4] ; /* 0x0000040408047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IADD3 R0, R4.reuse, -R5.reuse, RZ ; /* 0x8000000504007210 */
/* 0x0c4fe40007ffe0ff */
/*00e0*/ ISETP.GT.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04270 */
/*00f0*/ I2F R6, R0 ; /* 0x0000000000067306 */
/* 0x0000760000201400 */
/*0100*/ @P0 BRA 0x190 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x001fc800078e0002 */
/*0120*/ IMAD R4, R3, c[0x0][0x164], R0 ; /* 0x0000590003047a24 */
/* 0x001fe200078e0200 */
/*0130*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc60007ffe0ff */
/*0140*/ IMAD.WIDE R4, R4, R7, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e0207 */
/*0150*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fc80003f06270 */
/*0160*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001f2000c101904 */
/*0170*/ @!P0 BRA 0x120 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0180*/ BRA 0xb20 ; /* 0x0000099000007947 */
/* 0x000fea0003800000 */
/*0190*/ LOP3.LUT R11, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff0b7212 */
/* 0x001fe200078e33ff */
/*01a0*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0002 */
/*01b0*/ LOP3.LUT R7, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300077812 */
/* 0x000fc400078ec0ff */
/*01c0*/ IADD3 R8, R5.reuse, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ IADD3 R9, R5.reuse, 0x2, RZ ; /* 0x0000000205097810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ IADD3 R10, R5, 0x3, RZ ; /* 0x00000003050a7810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IADD3 R11, R4, R11, RZ ; /* 0x0000000b040b7210 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0210*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x001fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fd400078e0005 */
/*0230*/ @!P0 BRA 0x610 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0240*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0250*/ IMAD R14, R5, c[0x0][0x164], R12 ; /* 0x00005900050e7a24 */
/* 0x000fd200078e020c */
/*0260*/ IMAD.WIDE R16, R14, R17, c[0x0][0x168] ; /* 0x00005a000e107625 */
/* 0x000fca00078e0211 */
/*0270*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000ea2000c1e1900 */
/*0280*/ MUFU.RCP R13, R6 ; /* 0x00000006000d7308 */
/* 0x002e220000001000 */
/*0290*/ BSSY B1, 0x360 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*02a0*/ ISETP.NE.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f45270 */
/*02b0*/ FFMA R0, -R6, R13, 1 ; /* 0x3f80000006007423 */
/* 0x001fc8000000010d */
/*02c0*/ FFMA R0, R13, R0, R13 ; /* 0x000000000d007223 */
/* 0x000fe2000000000d */
/*02d0*/ FCHK P0, R22, R6 ; /* 0x0000000616007302 */
/* 0x004e260000000000 */
/*02e0*/ FFMA R13, R22, R0, RZ ; /* 0x00000000160d7223 */
/* 0x000fc800000000ff */
/*02f0*/ FFMA R15, -R6, R13, R22 ; /* 0x0000000d060f7223 */
/* 0x000fc80000000116 */
/*0300*/ FFMA R0, R0, R15, R13 ; /* 0x0000000f00007223 */
/* 0x000fe2000000000d */
/*0310*/ @!P0 BRA 0x350 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0320*/ MOV R0, 0x340 ; /* 0x0000034000007802 */
/* 0x000fe40000000f00 */
/*0330*/ CALL.REL.NOINC 0xb80 ; /* 0x0000084000007944 */
/* 0x000fea0003c00000 */
/*0340*/ IMAD.MOV.U32 R0, RZ, RZ, R21 ; /* 0x000000ffff007224 */
/* 0x001fe400078e0015 */
/*0350*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0360*/ FADD R24, RZ, R0 ; /* 0x00000000ff187221 */
/* 0x000fe40000000000 */
/*0370*/ IMAD.MOV.U32 R13, RZ, RZ, R8 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0008 */
/*0380*/ @!P2 BRA 0x610 ; /* 0x000002800000a947 */
/* 0x000fea0003800000 */
/*0390*/ IADD3 R14, R14, c[0x0][0x164], RZ ; /* 0x000059000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*03a0*/ MOV R17, 0x4 ; /* 0x0000000400117802 */
/* 0x000fca0000000f00 */
/*03b0*/ IMAD.WIDE R16, R14, R17, c[0x0][0x168] ; /* 0x00005a000e107625 */
/* 0x000fca00078e0211 */
/*03c0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ MUFU.RCP R13, R6 ; /* 0x00000006000d7308 */
/* 0x000e220000001000 */
/*03e0*/ BSSY B1, 0x4b0 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*03f0*/ ISETP.NE.AND P2, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fe20003f45270 */
/*0400*/ FFMA R0, -R6, R13, 1 ; /* 0x3f80000006007423 */
/* 0x001fc8000000010d */
/*0410*/ FFMA R15, R13, R0, R13 ; /* 0x000000000d0f7223 */
/* 0x000fe2000000000d */
/*0420*/ FCHK P0, R22, R6 ; /* 0x0000000616007302 */
/* 0x004e260000000000 */
/*0430*/ FFMA R13, R15, R22, RZ ; /* 0x000000160f0d7223 */
/* 0x000fc800000000ff */
/*0440*/ FFMA R0, -R6, R13, R22 ; /* 0x0000000d06007223 */
/* 0x000fc80000000116 */
/*0450*/ FFMA R13, R15, R0, R13 ; /* 0x000000000f0d7223 */
/* 0x000fe2000000000d */
/*0460*/ @!P0 BRA 0x4a0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0470*/ MOV R0, 0x490 ; /* 0x0000049000007802 */
/* 0x000fe40000000f00 */
/*0480*/ CALL.REL.NOINC 0xb80 ; /* 0x000006f000007944 */
/* 0x000fea0003c00000 */
/*0490*/ IMAD.MOV.U32 R13, RZ, RZ, R21 ; /* 0x000000ffff0d7224 */
/* 0x001fe400078e0015 */
/*04a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04b0*/ FADD R24, R24, R13 ; /* 0x0000000d18187221 */
/* 0x000fe40000000000 */
/*04c0*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0009 */
/*04d0*/ @!P2 BRA 0x610 ; /* 0x000001300000a947 */
/* 0x000fea0003800000 */
/*04e0*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fe200000001ff */
/*04f0*/ IADD3 R14, R14, c[0x0][0x164], RZ ; /* 0x000059000e0e7a10 */
/* 0x000fd20007ffe0ff */
/*0500*/ IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fca00078e020f */
/*0510*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea2000c1e1900 */
/*0520*/ MUFU.RCP R13, R6 ; /* 0x00000006000d7308 */
/* 0x000e220000001000 */
/*0530*/ BSSY B1, 0x5f0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0540*/ FFMA R0, -R6, R13, 1 ; /* 0x3f80000006007423 */
/* 0x001fc8000000010d */
/*0550*/ FFMA R17, R13, R0, R13 ; /* 0x000000000d117223 */
/* 0x000fe4000000000d */
/*0560*/ FCHK P0, R22, R6 ; /* 0x0000000616007302 */
/* 0x004e240000000000 */
/*0570*/ FFMA R13, R17, R22, RZ ; /* 0x00000016110d7223 */
/* 0x000fc800000000ff */
/*0580*/ FFMA R0, -R6, R13, R22 ; /* 0x0000000d06007223 */
/* 0x000fc80000000116 */
/*0590*/ FFMA R13, R17, R0, R13 ; /* 0x00000000110d7223 */
/* 0x000fe2000000000d */
/*05a0*/ @!P0 BRA 0x5e0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*05b0*/ MOV R0, 0x5d0 ; /* 0x000005d000007802 */
/* 0x000fe40000000f00 */
/*05c0*/ CALL.REL.NOINC 0xb80 ; /* 0x000005b000007944 */
/* 0x000fea0003c00000 */
/*05d0*/ IMAD.MOV.U32 R13, RZ, RZ, R21 ; /* 0x000000ffff0d7224 */
/* 0x001fe400078e0015 */
/*05e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05f0*/ FADD R24, R24, R13 ; /* 0x0000000d18187221 */
/* 0x000fe40000000000 */
/*0600*/ IMAD.MOV.U32 R13, RZ, RZ, R10 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e000a */
/*0610*/ ISETP.GE.U32.AND P0, PT, R11, 0x3, PT ; /* 0x000000030b00780c */
/* 0x000fda0003f06070 */
/*0620*/ @!P0 BRA 0xab0 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*0630*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fe20000000f00 */
/*0640*/ IMAD R14, R13, c[0x0][0x164], R12 ; /* 0x000059000d0e7a24 */
/* 0x000fc800078e020c */
/*0650*/ IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fca00078e020f */
/*0660*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea2000c1e1900 */
/*0670*/ MUFU.RCP R17, R6 ; /* 0x0000000600117308 */
/* 0x002e220000001000 */
/*0680*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fe20007ffe0ff */
/*0690*/ BSSY B1, 0x760 ; /* 0x000000c000017945 */
/* 0x000fe60003800000 */
/*06a0*/ ISETP.GE.AND P2, PT, R13, R4, PT ; /* 0x000000040d00720c */
/* 0x000fe20003f46270 */
/*06b0*/ FFMA R0, -R6, R17, 1 ; /* 0x3f80000006007423 */
/* 0x001fc80000000111 */
/*06c0*/ FFMA R19, R17, R0, R17 ; /* 0x0000000011137223 */
/* 0x000fe20000000011 */
/*06d0*/ FCHK P0, R22, R6 ; /* 0x0000000616007302 */
/* 0x004e260000000000 */
/*06e0*/ FFMA R17, R19, R22, RZ ; /* 0x0000001613117223 */
/* 0x000fc800000000ff */
/*06f0*/ FFMA R0, -R6, R17, R22 ; /* 0x0000001106007223 */
/* 0x000fc80000000116 */
/*0700*/ FFMA R17, R19, R0, R17 ; /* 0x0000000013117223 */
/* 0x000fe20000000011 */
/*0710*/ @!P0 BRA 0x750 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0720*/ MOV R0, 0x740 ; /* 0x0000074000007802 */
/* 0x000fe40000000f00 */
/*0730*/ CALL.REL.NOINC 0xb80 ; /* 0x0000044000007944 */
/* 0x000fea0003c00000 */
/*0740*/ IMAD.MOV.U32 R17, RZ, RZ, R21 ; /* 0x000000ffff117224 */
/* 0x001fe400078e0015 */
/*0750*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fc800078e00ff */
/*0770*/ IMAD.WIDE R14, R19, c[0x0][0x164], R14 ; /* 0x00005900130e7a25 */
/* 0x000fca00078e020e */
/*0780*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea2000c1e1900 */
/*0790*/ MUFU.RCP R19, R6 ; /* 0x0000000600137308 */
/* 0x000e220000001000 */
/*07a0*/ BSSY B1, 0x870 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*07b0*/ FADD R24, R17, R24 ; /* 0x0000001811187221 */
/* 0x000fe40000000000 */
/*07c0*/ FFMA R0, -R6, R19, 1 ; /* 0x3f80000006007423 */
/* 0x001fc80000000113 */
/*07d0*/ FFMA R21, R19, R0, R19 ; /* 0x0000000013157223 */
/* 0x000fe20000000013 */
/*07e0*/ FCHK P0, R22, R6 ; /* 0x0000000616007302 */
/* 0x004e260000000000 */
/*07f0*/ FFMA R19, R21, R22, RZ ; /* 0x0000001615137223 */
/* 0x000fc800000000ff */
/*0800*/ FFMA R0, -R6, R19, R22 ; /* 0x0000001306007223 */
/* 0x000fc80000000116 */
/*0810*/ FFMA R19, R21, R0, R19 ; /* 0x0000000015137223 */
/* 0x000fe20000000013 */
/*0820*/ @!P0 BRA 0x860 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0830*/ MOV R0, 0x850 ; /* 0x0000085000007802 */
/* 0x000fe40000000f00 */
/*0840*/ CALL.REL.NOINC 0xb80 ; /* 0x0000033000007944 */
/* 0x000fea0003c00000 */
/*0850*/ MOV R19, R21 ; /* 0x0000001500137202 */
/* 0x001fe40000000f00 */
/*0860*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0870*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fc800078e00ff */
/*0880*/ IMAD.WIDE R14, R17, c[0x0][0x164], R14 ; /* 0x00005900110e7a25 */
/* 0x000fca00078e020e */
/*0890*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea2000c1e1900 */
/*08a0*/ MUFU.RCP R17, R6 ; /* 0x0000000600117308 */
/* 0x000e220000001000 */
/*08b0*/ BSSY B1, 0x980 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*08c0*/ FADD R24, R24, R19 ; /* 0x0000001318187221 */
/* 0x000fe40000000000 */
/*08d0*/ FFMA R0, -R6, R17, 1 ; /* 0x3f80000006007423 */
/* 0x001fc80000000111 */
/*08e0*/ FFMA R21, R17, R0, R17 ; /* 0x0000000011157223 */
/* 0x000fe20000000011 */
/*08f0*/ FCHK P0, R22, R6 ; /* 0x0000000616007302 */
/* 0x004e260000000000 */
/*0900*/ FFMA R17, R21, R22, RZ ; /* 0x0000001615117223 */
/* 0x000fc800000000ff */
/*0910*/ FFMA R0, -R6, R17, R22 ; /* 0x0000001106007223 */
/* 0x000fc80000000116 */
/*0920*/ FFMA R19, R21, R0, R17 ; /* 0x0000000015137223 */
/* 0x000fe20000000011 */
/*0930*/ @!P0 BRA 0x970 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0940*/ MOV R0, 0x960 ; /* 0x0000096000007802 */
/* 0x000fe40000000f00 */
/*0950*/ CALL.REL.NOINC 0xb80 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*0960*/ IMAD.MOV.U32 R19, RZ, RZ, R21 ; /* 0x000000ffff137224 */
/* 0x001fe400078e0015 */
/*0970*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0980*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fd400000001ff */
/*0990*/ IMAD.WIDE R16, R23, c[0x0][0x164], R14 ; /* 0x0000590017107a25 */
/* 0x000fca00078e020e */
/*09a0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ MUFU.RCP R15, R6 ; /* 0x00000006000f7308 */
/* 0x000e220000001000 */
/*09c0*/ BSSY B1, 0xa90 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*09d0*/ FADD R24, R24, R19 ; /* 0x0000001318187221 */
/* 0x000fe40000000000 */
/*09e0*/ FFMA R0, -R6, R15, 1 ; /* 0x3f80000006007423 */
/* 0x001fc8000000010f */
/*09f0*/ FFMA R25, R15, R0, R15 ; /* 0x000000000f197223 */
/* 0x000fe4000000000f */
/*0a00*/ IMAD.WIDE R14, R23, c[0x0][0x164], R16 ; /* 0x00005900170e7a25 */
/* 0x000fe200078e0210 */
/*0a10*/ FCHK P0, R22, R6 ; /* 0x0000000616007302 */
/* 0x004e260000000000 */
/*0a20*/ FFMA R21, R25, R22, RZ ; /* 0x0000001619157223 */
/* 0x000fc800000000ff */
/*0a30*/ FFMA R0, -R6, R21, R22 ; /* 0x0000001506007223 */
/* 0x000fc80000000116 */
/*0a40*/ FFMA R21, R25, R0, R21 ; /* 0x0000000019157223 */
/* 0x000fe20000000015 */
/*0a50*/ @!P0 BRA 0xa80 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0a60*/ MOV R0, 0xa80 ; /* 0x00000a8000007802 */
/* 0x000fe40000000f00 */
/*0a70*/ CALL.REL.NOINC 0xb80 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0a80*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a90*/ FADD R24, R24, R21 ; /* 0x0000001518187221 */
/* 0x001fe20000000000 */
/*0aa0*/ @!P2 BRA 0x660 ; /* 0xfffffbb00000a947 */
/* 0x000fea000383ffff */
/*0ab0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*0ac0*/ IMAD R14, R3, c[0x0][0x164], R12 ; /* 0x00005900030e7a24 */
/* 0x000fe200078e020c */
/*0ad0*/ IADD3 R12, R12, c[0x0][0x0], RZ ; /* 0x000000000c0c7a10 */
/* 0x000fc60007ffe0ff */
/*0ae0*/ IMAD.WIDE R14, R14, R15, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fe200078e020f */
/*0af0*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x164], PT ; /* 0x000059000c007a0c */
/* 0x000fc80003f06270 */
/*0b00*/ STG.E [R14.64], R24 ; /* 0x000000180e007986 */
/* 0x0001f2000c101904 */
/*0b10*/ @!P0 BRA 0x200 ; /* 0xfffff6e000008947 */
/* 0x000fea000383ffff */
/*0b20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b30*/ IADD3 R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a10 */
/* 0x000fc80007ffe0ff */
/*0b40*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0b50*/ @P0 CALL.REL.NOINC 0xb70 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0b60*/ BRA 0x60 ; /* 0xfffff4f000007947 */
/* 0x000fea000383ffff */
/*0b70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b80*/ SHF.R.U32.HI R16, RZ, 0x17, R6 ; /* 0x00000017ff107819 */
/* 0x000fe20000011606 */
/*0b90*/ BSSY B2, 0x11d0 ; /* 0x0000063000027945 */
/* 0x000fe20003800000 */
/*0ba0*/ SHF.R.U32.HI R19, RZ, 0x17, R22 ; /* 0x00000017ff137819 */
/* 0x000fe20000011616 */
/*0bb0*/ IMAD.MOV.U32 R21, RZ, RZ, R6 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0006 */
/*0bc0*/ LOP3.LUT R16, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10107812 */
/* 0x000fe400078ec0ff */
/*0bd0*/ LOP3.LUT R19, R19, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff13137812 */
/* 0x000fe400078ec0ff */
/*0be0*/ IADD3 R18, R16, -0x1, RZ ; /* 0xffffffff10127810 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ IADD3 R20, R19, -0x1, RZ ; /* 0xffffffff13147810 */
/* 0x000fc40007ffe0ff */
/*0c00*/ ISETP.GT.U32.AND P0, PT, R18, 0xfd, PT ; /* 0x000000fd1200780c */
/* 0x000fc80003f04070 */
/*0c10*/ ISETP.GT.U32.OR P0, PT, R20, 0xfd, P0 ; /* 0x000000fd1400780c */
/* 0x000fda0000704470 */
/*0c20*/ @!P0 MOV R17, RZ ; /* 0x000000ff00118202 */
/* 0x000fe20000000f00 */
/*0c30*/ @!P0 BRA 0xdb0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0c40*/ FSETP.GTU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fe40003f1c200 */
/*0c50*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0c60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0c70*/ @P0 BRA 0x11b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0c80*/ LOP3.LUT P0, RZ, R21, 0x7fffffff, R22, 0xc8, !PT ; /* 0x7fffffff15ff7812 */
/* 0x000fda000780c816 */
/*0c90*/ @!P0 BRA 0x1190 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0ca0*/ FSETP.NEU.FTZ.AND P3, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fe40003f7d200 */
/*0cb0*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0cc0*/ FSETP.NEU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fd60003f1d200 */
/*0cd0*/ @!P1 BRA !P3, 0x1190 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*0ce0*/ LOP3.LUT P3, RZ, R22, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff16ff7812 */
/* 0x000fc8000786c0ff */
/*0cf0*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0d00*/ @P1 BRA 0x1170 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0d10*/ LOP3.LUT P1, RZ, R21, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff15ff7812 */
/* 0x000fc8000782c0ff */
/*0d20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0d30*/ @P0 BRA 0x1140 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0d40*/ ISETP.GE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f06270 */
/*0d50*/ ISETP.GE.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fd60003f26270 */
/*0d60*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff110224 */
/* 0x000fe200078e00ff */
/*0d70*/ @!P0 MOV R17, 0xffffffc0 ; /* 0xffffffc000118802 */
/* 0x000fe20000000f00 */
/*0d80*/ @!P0 FFMA R22, R22, 1.84467440737095516160e+19, RZ ; /* 0x5f80000016168823 */
/* 0x000fe400000000ff */
/*0d90*/ @!P1 FFMA R21, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006159823 */
/* 0x000fe200000000ff */
/*0da0*/ @!P1 IADD3 R17, R17, 0x40, RZ ; /* 0x0000004011119810 */
/* 0x000fe40007ffe0ff */
/*0db0*/ LEA R18, R16, 0xc0800000, 0x17 ; /* 0xc080000010127811 */
/* 0x000fe200078eb8ff */
/*0dc0*/ BSSY B3, 0x1130 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*0dd0*/ IADD3 R19, R19, -0x7f, RZ ; /* 0xffffff8113137810 */
/* 0x000fc60007ffe0ff */
/*0de0*/ IMAD.IADD R25, R21, 0x1, -R18 ; /* 0x0000000115197824 */
/* 0x000fe400078e0a12 */
/*0df0*/ IMAD R21, R19, -0x800000, R22 ; /* 0xff80000013157824 */
/* 0x000fe400078e0216 */
/*0e00*/ MUFU.RCP R23, R25 ; /* 0x0000001900177308 */
/* 0x000e220000001000 */
/*0e10*/ FADD.FTZ R18, -R25, -RZ ; /* 0x800000ff19127221 */
/* 0x000fc80000010100 */
/*0e20*/ FFMA R20, R23, R18, 1 ; /* 0x3f80000017147423 */
/* 0x001fc80000000012 */
/*0e30*/ FFMA R20, R23, R20, R23 ; /* 0x0000001417147223 */
/* 0x000fc80000000017 */
/*0e40*/ FFMA R23, R21, R20, RZ ; /* 0x0000001415177223 */
/* 0x000fc800000000ff */
/*0e50*/ FFMA R22, R18, R23, R21 ; /* 0x0000001712167223 */
/* 0x000fc80000000015 */
/*0e60*/ FFMA R23, R20, R22, R23 ; /* 0x0000001614177223 */
/* 0x000fe20000000017 */
/*0e70*/ IADD3 R22, R19, 0x7f, -R16 ; /* 0x0000007f13167810 */
/* 0x000fc60007ffe810 */
/*0e80*/ FFMA R18, R18, R23, R21 ; /* 0x0000001712127223 */
/* 0x000fe20000000015 */
/*0e90*/ IADD3 R22, R22, R17, RZ ; /* 0x0000001116167210 */
/* 0x000fc60007ffe0ff */
/*0ea0*/ FFMA R21, R20, R18, R23 ; /* 0x0000001214157223 */
/* 0x000fca0000000017 */
/*0eb0*/ SHF.R.U32.HI R16, RZ, 0x17, R21 ; /* 0x00000017ff107819 */
/* 0x000fc80000011615 */
/*0ec0*/ LOP3.LUT R17, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10117812 */
/* 0x000fca00078ec0ff */
/*0ed0*/ IMAD.IADD R16, R17, 0x1, R22 ; /* 0x0000000111107824 */
/* 0x000fca00078e0216 */
/*0ee0*/ IADD3 R17, R16, -0x1, RZ ; /* 0xffffffff10117810 */
/* 0x000fc80007ffe0ff */
/*0ef0*/ ISETP.GE.U32.AND P0, PT, R17, 0xfe, PT ; /* 0x000000fe1100780c */
/* 0x000fda0003f06070 */
/*0f00*/ @!P0 BRA 0x1110 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0f10*/ ISETP.GT.AND P0, PT, R16, 0xfe, PT ; /* 0x000000fe1000780c */
/* 0x000fda0003f04270 */
/*0f20*/ @P0 BRA 0x10e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0f30*/ ISETP.GE.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fda0003f06270 */
/*0f40*/ @P0 BRA 0x1120 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0f50*/ ISETP.GE.AND P0, PT, R16, -0x18, PT ; /* 0xffffffe81000780c */
/* 0x000fe40003f06270 */
/*0f60*/ LOP3.LUT R21, R21, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000015157812 */
/* 0x000fd600078ec0ff */
/*0f70*/ @!P0 BRA 0x1120 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0f80*/ FFMA.RZ R17, R20, R18.reuse, R23.reuse ; /* 0x0000001214117223 */
/* 0x180fe2000000c017 */
/*0f90*/ ISETP.NE.AND P3, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f65270 */
/*0fa0*/ FFMA.RP R19, R20, R18.reuse, R23.reuse ; /* 0x0000001214137223 */
/* 0x180fe20000008017 */
/*0fb0*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f25270 */
/*0fc0*/ FFMA.RM R20, R20, R18, R23 ; /* 0x0000001214147223 */
/* 0x000fe20000004017 */
/*0fd0*/ LOP3.LUT R17, R17, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff11117812 */
/* 0x000fe400078ec0ff */
/*0fe0*/ IADD3 R18, R16.reuse, 0x20, RZ ; /* 0x0000002010127810 */
/* 0x040fe40007ffe0ff */
/*0ff0*/ LOP3.LUT R17, R17, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000011117812 */
/* 0x000fe400078efcff */
/*1000*/ IADD3 R16, -R16, RZ, RZ ; /* 0x000000ff10107210 */
/* 0x000fc40007ffe1ff */
/*1010*/ SHF.L.U32 R18, R17, R18, RZ ; /* 0x0000001211127219 */
/* 0x000fe400000006ff */
/*1020*/ FSETP.NEU.FTZ.AND P0, PT, R19, R20, PT ; /* 0x000000141300720b */
/* 0x000fe40003f1d000 */
/*1030*/ SEL R16, R16, RZ, P3 ; /* 0x000000ff10107207 */
/* 0x000fe40001800000 */
/*1040*/ ISETP.NE.AND P1, PT, R18, RZ, P1 ; /* 0x000000ff1200720c */
/* 0x000fe40000f25270 */
/*1050*/ SHF.R.U32.HI R17, RZ, R16, R17 ; /* 0x00000010ff117219 */
/* 0x000fe40000011611 */
/*1060*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*1070*/ SHF.R.U32.HI R16, RZ, 0x1, R17 ; /* 0x00000001ff107819 */
/* 0x000fe40000011611 */
/*1080*/ SEL R19, RZ, 0x1, !P0 ; /* 0x00000001ff137807 */
/* 0x000fc80004000000 */
/*1090*/ LOP3.LUT R18, R19, 0x1, R16, 0xf8, !PT ; /* 0x0000000113127812 */
/* 0x000fc800078ef810 */
/*10a0*/ LOP3.LUT R17, R18, R17, RZ, 0xc0, !PT ; /* 0x0000001112117212 */
/* 0x000fca00078ec0ff */
/*10b0*/ IMAD.IADD R16, R16, 0x1, R17 ; /* 0x0000000110107824 */
/* 0x000fca00078e0211 */
/*10c0*/ LOP3.LUT R21, R16, R21, RZ, 0xfc, !PT ; /* 0x0000001510157212 */
/* 0x000fe200078efcff */
/*10d0*/ BRA 0x1120 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*10e0*/ LOP3.LUT R21, R21, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000015157812 */
/* 0x000fc800078ec0ff */
/*10f0*/ LOP3.LUT R21, R21, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000015157812 */
/* 0x000fe200078efcff */
/*1100*/ BRA 0x1120 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1110*/ LEA R21, R22, R21, 0x17 ; /* 0x0000001516157211 */
/* 0x000fe400078eb8ff */
/*1120*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*1130*/ BRA 0x11c0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1140*/ LOP3.LUT R21, R21, 0x80000000, R22, 0x48, !PT ; /* 0x8000000015157812 */
/* 0x000fc800078e4816 */
/*1150*/ LOP3.LUT R21, R21, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000015157812 */
/* 0x000fe200078efcff */
/*1160*/ BRA 0x11c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1170*/ LOP3.LUT R21, R21, 0x80000000, R22, 0x48, !PT ; /* 0x8000000015157812 */
/* 0x000fe200078e4816 */
/*1180*/ BRA 0x11c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1190*/ MUFU.RSQ R21, -QNAN ; /* 0xffc0000000157908 */
/* 0x000e220000001400 */
/*11a0*/ BRA 0x11c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*11b0*/ FADD.FTZ R21, R22, R6 ; /* 0x0000000616157221 */
/* 0x000fe40000010000 */
/*11c0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*11d0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fe200000001ff */
/*11e0*/ IMAD.MOV.U32 R16, RZ, RZ, R0 ; /* 0x000000ffff107224 */
/* 0x000fca00078e0000 */
/*11f0*/ RET.REL.NODEC R16 0x0 ; /* 0xffffee0010007950 */
/* 0x000fea0003c3ffff */
/*1200*/ BRA 0x1200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sec_mean_cuda_(int nProposal, int C, float *inp, int *offsets, float *out){
for(int p_id = blockIdx.x; p_id < nProposal; p_id += gridDim.x){
int start = offsets[p_id];
int end = offsets[p_id + 1];
float count = (float)(end - start);
for(int plane = threadIdx.x; plane < C; plane += blockDim.x){
float mean = 0;
for(int i = start; i < end; i++){
mean += (inp[i * C + plane] / count);
}
out[p_id * C + plane] = mean;
}
}
} | .file "tmpxft_0016e23b_00000000-6_sec_mean_cuda_.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_
.type _Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_, @function
_Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sec_mean_cuda_iiPfPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_, .-_Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_
.globl _Z14sec_mean_cuda_iiPfPiS_
.type _Z14sec_mean_cuda_iiPfPiS_, @function
_Z14sec_mean_cuda_iiPfPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sec_mean_cuda_iiPfPiS_, .-_Z14sec_mean_cuda_iiPfPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sec_mean_cuda_iiPfPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sec_mean_cuda_iiPfPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sec_mean_cuda_(int nProposal, int C, float *inp, int *offsets, float *out){
for(int p_id = blockIdx.x; p_id < nProposal; p_id += gridDim.x){
int start = offsets[p_id];
int end = offsets[p_id + 1];
float count = (float)(end - start);
for(int plane = threadIdx.x; plane < C; plane += blockDim.x){
float mean = 0;
for(int i = start; i < end; i++){
mean += (inp[i * C + plane] / count);
}
out[p_id * C + plane] = mean;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sec_mean_cuda_(int nProposal, int C, float *inp, int *offsets, float *out){
for(int p_id = blockIdx.x; p_id < nProposal; p_id += gridDim.x){
int start = offsets[p_id];
int end = offsets[p_id + 1];
float count = (float)(end - start);
for(int plane = threadIdx.x; plane < C; plane += blockDim.x){
float mean = 0;
for(int i = start; i < end; i++){
mean += (inp[i * C + plane] / count);
}
out[p_id * C + plane] = mean;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sec_mean_cuda_(int nProposal, int C, float *inp, int *offsets, float *out){
for(int p_id = blockIdx.x; p_id < nProposal; p_id += gridDim.x){
int start = offsets[p_id];
int end = offsets[p_id + 1];
float count = (float)(end - start);
for(int plane = threadIdx.x; plane < C; plane += blockDim.x){
float mean = 0;
for(int i = start; i < end; i++){
mean += (inp[i * C + plane] / count);
}
out[p_id * C + plane] = mean;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sec_mean_cuda_iiPfPiS_
.globl _Z14sec_mean_cuda_iiPfPiS_
.p2align 8
.type _Z14sec_mean_cuda_iiPfPiS_,@function
_Z14sec_mean_cuda_iiPfPiS_:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_9
s_clause 0x3
s_load_b32 s16, s[0:1], 0x4
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[10:11], s[0:1], 0x18
s_load_b32 s17, s[0:1], 0x20
s_add_u32 s12, s0, 32
s_mov_b32 s8, s15
s_addc_u32 s13, s1, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s16, v0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s8, s17, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s8, s3
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s2
s_cbranch_execz .LBB0_2
s_ashr_i32 s9, s8, 31
v_mov_b32_e32 v5, v0
s_lshl_b64 s[14:15], s[8:9], 2
s_mul_i32 s18, s8, s16
s_add_u32 s14, s6, s14
s_addc_u32 s15, s7, s15
s_mov_b32 s20, 0
s_load_b64 s[14:15], s[14:15], 0x0
s_load_b32 s0, s[12:13], 0xc
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s16, s14, v[0:1]
s_sub_i32 s9, s15, s14
s_cmp_gt_i32 s15, s14
v_cvt_f32_i32_e32 v4, s9
s_cselect_b32 s9, -1, 0
s_and_b32 s19, s0, 0xffff
s_branch .LBB0_6
.LBB0_5:
v_add_nc_u32_e32 v2, s18, v5
v_add_nc_u32_e32 v5, s19, v5
v_add_nc_u32_e32 v1, s19, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_le_i32_e32 vcc_lo, s16, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_or_b32 s20, vcc_lo, s20
v_add_co_u32 v2, s0, s10, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
global_store_b32 v[2:3], v6, off
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execz .LBB0_2
.LBB0_6:
v_mov_b32_e32 v6, 0
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_5
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, v1
s_mov_b32 s0, s14
.p2align 6
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s0, s0, 1
s_cmp_ge_i32 s0, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s16, v2
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v3, v[7:8], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v7, null, v4, v4, v3
v_div_scale_f32 v10, vcc_lo, v3, v4, v3
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_mul_f32_e32 v9, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v7, v9, v10
v_fmac_f32_e32 v9, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v9, v10
v_div_fmas_f32 v7, v7, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v7, v4, v3
v_add_f32_e32 v6, v6, v3
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sec_mean_cuda_iiPfPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sec_mean_cuda_iiPfPiS_, .Lfunc_end0-_Z14sec_mean_cuda_iiPfPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sec_mean_cuda_iiPfPiS_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z14sec_mean_cuda_iiPfPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sec_mean_cuda_(int nProposal, int C, float *inp, int *offsets, float *out){
for(int p_id = blockIdx.x; p_id < nProposal; p_id += gridDim.x){
int start = offsets[p_id];
int end = offsets[p_id + 1];
float count = (float)(end - start);
for(int plane = threadIdx.x; plane < C; plane += blockDim.x){
float mean = 0;
for(int i = start; i < end; i++){
mean += (inp[i * C + plane] / count);
}
out[p_id * C + plane] = mean;
}
}
} | .text
.file "sec_mean_cuda_.hip"
.globl _Z29__device_stub__sec_mean_cuda_iiPfPiS_ # -- Begin function _Z29__device_stub__sec_mean_cuda_iiPfPiS_
.p2align 4, 0x90
.type _Z29__device_stub__sec_mean_cuda_iiPfPiS_,@function
_Z29__device_stub__sec_mean_cuda_iiPfPiS_: # @_Z29__device_stub__sec_mean_cuda_iiPfPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sec_mean_cuda_iiPfPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__sec_mean_cuda_iiPfPiS_, .Lfunc_end0-_Z29__device_stub__sec_mean_cuda_iiPfPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sec_mean_cuda_iiPfPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sec_mean_cuda_iiPfPiS_,@object # @_Z14sec_mean_cuda_iiPfPiS_
.section .rodata,"a",@progbits
.globl _Z14sec_mean_cuda_iiPfPiS_
.p2align 3, 0x0
_Z14sec_mean_cuda_iiPfPiS_:
.quad _Z29__device_stub__sec_mean_cuda_iiPfPiS_
.size _Z14sec_mean_cuda_iiPfPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sec_mean_cuda_iiPfPiS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sec_mean_cuda_iiPfPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sec_mean_cuda_iiPfPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016e23b_00000000-6_sec_mean_cuda_.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_
.type _Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_, @function
_Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sec_mean_cuda_iiPfPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_, .-_Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_
.globl _Z14sec_mean_cuda_iiPfPiS_
.type _Z14sec_mean_cuda_iiPfPiS_, @function
_Z14sec_mean_cuda_iiPfPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14sec_mean_cuda_iiPfPiS_iiPfPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sec_mean_cuda_iiPfPiS_, .-_Z14sec_mean_cuda_iiPfPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sec_mean_cuda_iiPfPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sec_mean_cuda_iiPfPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sec_mean_cuda_.hip"
.globl _Z29__device_stub__sec_mean_cuda_iiPfPiS_ # -- Begin function _Z29__device_stub__sec_mean_cuda_iiPfPiS_
.p2align 4, 0x90
.type _Z29__device_stub__sec_mean_cuda_iiPfPiS_,@function
_Z29__device_stub__sec_mean_cuda_iiPfPiS_: # @_Z29__device_stub__sec_mean_cuda_iiPfPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sec_mean_cuda_iiPfPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__sec_mean_cuda_iiPfPiS_, .Lfunc_end0-_Z29__device_stub__sec_mean_cuda_iiPfPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sec_mean_cuda_iiPfPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sec_mean_cuda_iiPfPiS_,@object # @_Z14sec_mean_cuda_iiPfPiS_
.section .rodata,"a",@progbits
.globl _Z14sec_mean_cuda_iiPfPiS_
.p2align 3, 0x0
_Z14sec_mean_cuda_iiPfPiS_:
.quad _Z29__device_stub__sec_mean_cuda_iiPfPiS_
.size _Z14sec_mean_cuda_iiPfPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sec_mean_cuda_iiPfPiS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sec_mean_cuda_iiPfPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sec_mean_cuda_iiPfPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void stencil2DKernel(double* temperature, double* new_temperature, int block_x, int block_y, int thread_size) {
int i_start = (blockDim.x * blockIdx.x + threadIdx.x) * thread_size + 1;
int i_finish =
(blockDim.x * blockIdx.x + threadIdx.x) * thread_size + thread_size;
int j_start = (blockDim.y * blockIdx.y + threadIdx.y) * thread_size + 1;
int j_finish =
(blockDim.y * blockIdx.y + threadIdx.y) * thread_size + thread_size;
for (int i = i_start; i <= i_finish; i++) {
for (int j = j_start; j <= j_finish; j++) {
if (i <= block_x && j <= block_y) {
new_temperature[j * (block_x + 2) + i] =
(temperature[j * (block_x + 2) + (i - 1)] +
temperature[j * (block_x + 2) + (i + 1)] +
temperature[(j - 1) * (block_x + 2) + i] +
temperature[(j + 1) * (block_x + 2) + i] +
temperature[j * (block_x + 2) + i]) *
DIVIDEBY5;
}
}
}
/* TODO Use shared memory
int i = istart + threadIdx.x + blockDim.x*blockIdx.x;
int j = jstart + threadIdx.y + blockDim.y*blockIdx.y;
if (i < ifinish && j < jfinish) {
__shared__ double shared_temperature[TILE_SIZE][TILE_SIZE];
double center = temperature[j*(block_x+2)+i];
shared_temperature[threadIdx.x][threadIdx.y] = center;
__syncthreads();
// update my value based on the surrounding values
new_temperature[j*(block_x+2)+i] = (
((threadIdx.x > 1) ? shared_temperature[threadIdx.x-1][threadIdx.y] :
temperature[j*(block_x+2)+(i-1)]) +
((threadIdx.x < blockDim.x-1) ?
shared_temperature[threadIdx.x+1][threadIdx.y] :
temperature[j*(block_x+2)+(i+1)]) +
((threadIdx.y > 1) ? shared_temperature[threadIdx.x][threadIdx.y-1] :
temperature[(j-1)*(block_x+2)+i]) +
((threadIdx.y < blockDim.y-1) ?
shared_temperature[threadIdx.x][threadIdx.y+1] :
temperature[(j+1)*(block_x+2)+i]) +
center) * DIVIDEBY5;
}
*/
} | code for sm_80
Function : _Z15stencil2DKernelPdS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0060*/ IMAD R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a24 */
/* 0x000fca00078e02ff */
/*0070*/ IADD3 R0, R4.reuse, c[0x0][0x178], RZ ; /* 0x00005e0004007a10 */
/* 0x040fe40007ffe0ff */
/*0080*/ IADD3 R9, R4, 0x1, RZ ; /* 0x0000000104097810 */
/* 0x000fc80007ffe0ff */
/*0090*/ ISETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff087624 */
/* 0x003fe200078e00ff */
/*00c0*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x000fe200078e0202 */
/*00e0*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IADD3 R2, R8, 0x2, RZ ; /* 0x0000000208027810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R7, R3, c[0x0][0x178], RZ ; /* 0x00005e0003077a24 */
/* 0x000fc800078e02ff */
/*0120*/ IMAD R3, R7.reuse, R2.reuse, RZ ; /* 0x0000000207037224 */
/* 0x0c0fe200078e02ff */
/*0130*/ IADD3 R5, R7.reuse, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x040fe40007ffe0ff */
/*0140*/ IADD3 R6, R7, c[0x0][0x178], RZ ; /* 0x00005e0007067a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD R8, R8, 0x2, R3 ; /* 0x0000000208087824 */
/* 0x000fe400078e0203 */
/*0160*/ IMAD R7, R5, R2, RZ ; /* 0x0000000205077224 */
/* 0x000fc600078e02ff */
/*0170*/ IADD3 R9, R8, 0x4, RZ ; /* 0x0000000408097810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GT.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x000fe20003f04270 */
/*0190*/ BSSY B0, 0x3b0 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fd600078e0004 */
/*01b0*/ @P0 BRA 0x3a0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R29, R7, R10, RZ ; /* 0x0000000a071d7210 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.IADD R27, R9, 0x1, R4.reuse ; /* 0x00000001091b7824 */
/* 0x100fe200078e0204 */
/*01e0*/ IADD3 R23, R3, R4, RZ ; /* 0x0000000403177210 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.IADD R25, R7, 0x1, R4 ; /* 0x0000000107197824 */
/* 0x000fe200078e0204 */
/*0200*/ MOV R22, R5 ; /* 0x0000000500167202 */
/* 0x000fc80000000f00 */
/*0210*/ ISETP.GT.AND P0, PT, R22, c[0x0][0x174], PT ; /* 0x00005d0016007a0c */
/* 0x000fc80003f04270 */
/*0220*/ ISETP.GT.OR P0, PT, R4, c[0x0][0x170], P0 ; /* 0x00005c0004007a0c */
/* 0x000fda0000704670 */
/*0230*/ @!P0 IMAD.MOV.U32 R24, RZ, RZ, 0x8 ; /* 0x00000008ff188424 */
/* 0x000fc800078e00ff */
/*0240*/ @!P0 IMAD.WIDE R12, R29, R24, c[0x0][0x160] ; /* 0x000058001d0c8625 */
/* 0x000fc800078e0218 */
/*0250*/ @!P0 IMAD.WIDE R14, R23, R24.reuse, c[0x0][0x160] ; /* 0x00005800170e8625 */
/* 0x080fe200078e0218 */
/*0260*/ @!P0 LDG.E.64 R16, [R12.64+0x10] ; /* 0x000010040c108981 */
/* 0x000ea8000c1e1b00 */
/*0270*/ @!P0 LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a8981 */
/* 0x000ea2000c1e1b00 */
/*0280*/ @!P0 IMAD.WIDE R18, R27, R24, c[0x0][0x160] ; /* 0x000058001b128625 */
/* 0x000fc600078e0218 */
/*0290*/ @!P0 LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e8981 */
/* 0x000ee8000c1e1b00 */
/*02a0*/ @!P0 LDG.E.64 R18, [R18.64] ; /* 0x0000000412128981 */
/* 0x000f28000c1e1b00 */
/*02b0*/ @!P0 LDG.E.64 R20, [R12.64+0x8] ; /* 0x000008040c148981 */
/* 0x000f62000c1e1b00 */
/*02c0*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ IMAD.IADD R23, R2.reuse, 0x1, R23 ; /* 0x0000000102177824 */
/* 0x040fe200078e0217 */
/*02e0*/ IADD3 R29, R2, R29, RZ ; /* 0x0000001d021d7210 */
/* 0x000fc40007ffe0ff */
/*02f0*/ IADD3 R27, R2, R27, RZ ; /* 0x0000001b021b7210 */
/* 0x000fe20007ffe0ff */
/*0300*/ @!P0 DADD R10, R16, R10 ; /* 0x00000000100a8229 */
/* 0x0040e4000000000a */
/*0310*/ @!P0 IMAD.WIDE R16, R25, R24, c[0x0][0x168] ; /* 0x00005a0019108625 */
/* 0x001fc800078e0218 */
/*0320*/ @!P0 DADD R10, R10, R14 ; /* 0x000000000a0a8229 */
/* 0x008f22000000000e */
/*0330*/ IMAD.IADD R25, R2, 0x1, R25 ; /* 0x0000000102197824 */
/* 0x000fca00078e0219 */
/*0340*/ @!P0 DADD R10, R10, R18 ; /* 0x000000000a0a8229 */
/* 0x010f4c0000000012 */
/*0350*/ @!P0 DADD R10, R10, R20 ; /* 0x000000000a0a8229 */
/* 0x020e0c0000000014 */
/*0360*/ @!P0 DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a8a28 */
/* 0x001e0e0000000000 */
/*0370*/ @!P0 STG.E.64 [R16.64], R10 ; /* 0x0000000a10008986 */
/* 0x0011e2000c101b04 */
/*0380*/ ISETP.GT.AND P0, PT, R22, R6, PT ; /* 0x000000061600720c */
/* 0x000fda0003f04270 */
/*0390*/ @!P0 BRA 0x210 ; /* 0xfffffe7000008947 */
/* 0x001fea000383ffff */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fe40000000f00 */
/*03d0*/ ISETP.GT.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fda0003f04270 */
/*03e0*/ @!P0 BRA 0x180 ; /* 0xfffffd9000008947 */
/* 0x000fea000383ffff */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ BRA 0x400; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void stencil2DKernel(double* temperature, double* new_temperature, int block_x, int block_y, int thread_size) {
int i_start = (blockDim.x * blockIdx.x + threadIdx.x) * thread_size + 1;
int i_finish =
(blockDim.x * blockIdx.x + threadIdx.x) * thread_size + thread_size;
int j_start = (blockDim.y * blockIdx.y + threadIdx.y) * thread_size + 1;
int j_finish =
(blockDim.y * blockIdx.y + threadIdx.y) * thread_size + thread_size;
for (int i = i_start; i <= i_finish; i++) {
for (int j = j_start; j <= j_finish; j++) {
if (i <= block_x && j <= block_y) {
new_temperature[j * (block_x + 2) + i] =
(temperature[j * (block_x + 2) + (i - 1)] +
temperature[j * (block_x + 2) + (i + 1)] +
temperature[(j - 1) * (block_x + 2) + i] +
temperature[(j + 1) * (block_x + 2) + i] +
temperature[j * (block_x + 2) + i]) *
DIVIDEBY5;
}
}
}
/* TODO Use shared memory
int i = istart + threadIdx.x + blockDim.x*blockIdx.x;
int j = jstart + threadIdx.y + blockDim.y*blockIdx.y;
if (i < ifinish && j < jfinish) {
__shared__ double shared_temperature[TILE_SIZE][TILE_SIZE];
double center = temperature[j*(block_x+2)+i];
shared_temperature[threadIdx.x][threadIdx.y] = center;
__syncthreads();
// update my value based on the surrounding values
new_temperature[j*(block_x+2)+i] = (
((threadIdx.x > 1) ? shared_temperature[threadIdx.x-1][threadIdx.y] :
temperature[j*(block_x+2)+(i-1)]) +
((threadIdx.x < blockDim.x-1) ?
shared_temperature[threadIdx.x+1][threadIdx.y] :
temperature[j*(block_x+2)+(i+1)]) +
((threadIdx.y > 1) ? shared_temperature[threadIdx.x][threadIdx.y-1] :
temperature[(j-1)*(block_x+2)+i]) +
((threadIdx.y < blockDim.y-1) ?
shared_temperature[threadIdx.x][threadIdx.y+1] :
temperature[(j+1)*(block_x+2)+i]) +
center) * DIVIDEBY5;
}
*/
} | .file "tmpxft_00166364_00000000-6_stencil2DKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii
.type _Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii, @function
_Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15stencil2DKernelPdS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii, .-_Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii
.globl _Z15stencil2DKernelPdS_iii
.type _Z15stencil2DKernelPdS_iii, @function
_Z15stencil2DKernelPdS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15stencil2DKernelPdS_iii, .-_Z15stencil2DKernelPdS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15stencil2DKernelPdS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15stencil2DKernelPdS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void stencil2DKernel(double* temperature, double* new_temperature, int block_x, int block_y, int thread_size) {
int i_start = (blockDim.x * blockIdx.x + threadIdx.x) * thread_size + 1;
int i_finish =
(blockDim.x * blockIdx.x + threadIdx.x) * thread_size + thread_size;
int j_start = (blockDim.y * blockIdx.y + threadIdx.y) * thread_size + 1;
int j_finish =
(blockDim.y * blockIdx.y + threadIdx.y) * thread_size + thread_size;
for (int i = i_start; i <= i_finish; i++) {
for (int j = j_start; j <= j_finish; j++) {
if (i <= block_x && j <= block_y) {
new_temperature[j * (block_x + 2) + i] =
(temperature[j * (block_x + 2) + (i - 1)] +
temperature[j * (block_x + 2) + (i + 1)] +
temperature[(j - 1) * (block_x + 2) + i] +
temperature[(j + 1) * (block_x + 2) + i] +
temperature[j * (block_x + 2) + i]) *
DIVIDEBY5;
}
}
}
/* TODO Use shared memory
int i = istart + threadIdx.x + blockDim.x*blockIdx.x;
int j = jstart + threadIdx.y + blockDim.y*blockIdx.y;
if (i < ifinish && j < jfinish) {
__shared__ double shared_temperature[TILE_SIZE][TILE_SIZE];
double center = temperature[j*(block_x+2)+i];
shared_temperature[threadIdx.x][threadIdx.y] = center;
__syncthreads();
// update my value based on the surrounding values
new_temperature[j*(block_x+2)+i] = (
((threadIdx.x > 1) ? shared_temperature[threadIdx.x-1][threadIdx.y] :
temperature[j*(block_x+2)+(i-1)]) +
((threadIdx.x < blockDim.x-1) ?
shared_temperature[threadIdx.x+1][threadIdx.y] :
temperature[j*(block_x+2)+(i+1)]) +
((threadIdx.y > 1) ? shared_temperature[threadIdx.x][threadIdx.y-1] :
temperature[(j-1)*(block_x+2)+i]) +
((threadIdx.y < blockDim.y-1) ?
shared_temperature[threadIdx.x][threadIdx.y+1] :
temperature[(j+1)*(block_x+2)+i]) +
center) * DIVIDEBY5;
}
*/
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void stencil2DKernel(double* temperature, double* new_temperature, int block_x, int block_y, int thread_size) {
int i_start = (blockDim.x * blockIdx.x + threadIdx.x) * thread_size + 1;
int i_finish =
(blockDim.x * blockIdx.x + threadIdx.x) * thread_size + thread_size;
int j_start = (blockDim.y * blockIdx.y + threadIdx.y) * thread_size + 1;
int j_finish =
(blockDim.y * blockIdx.y + threadIdx.y) * thread_size + thread_size;
for (int i = i_start; i <= i_finish; i++) {
for (int j = j_start; j <= j_finish; j++) {
if (i <= block_x && j <= block_y) {
new_temperature[j * (block_x + 2) + i] =
(temperature[j * (block_x + 2) + (i - 1)] +
temperature[j * (block_x + 2) + (i + 1)] +
temperature[(j - 1) * (block_x + 2) + i] +
temperature[(j + 1) * (block_x + 2) + i] +
temperature[j * (block_x + 2) + i]) *
DIVIDEBY5;
}
}
}
/* TODO Use shared memory
int i = istart + threadIdx.x + blockDim.x*blockIdx.x;
int j = jstart + threadIdx.y + blockDim.y*blockIdx.y;
if (i < ifinish && j < jfinish) {
__shared__ double shared_temperature[TILE_SIZE][TILE_SIZE];
double center = temperature[j*(block_x+2)+i];
shared_temperature[threadIdx.x][threadIdx.y] = center;
__syncthreads();
// update my value based on the surrounding values
new_temperature[j*(block_x+2)+i] = (
((threadIdx.x > 1) ? shared_temperature[threadIdx.x-1][threadIdx.y] :
temperature[j*(block_x+2)+(i-1)]) +
((threadIdx.x < blockDim.x-1) ?
shared_temperature[threadIdx.x+1][threadIdx.y] :
temperature[j*(block_x+2)+(i+1)]) +
((threadIdx.y > 1) ? shared_temperature[threadIdx.x][threadIdx.y-1] :
temperature[(j-1)*(block_x+2)+i]) +
((threadIdx.y < blockDim.y-1) ?
shared_temperature[threadIdx.x][threadIdx.y+1] :
temperature[(j+1)*(block_x+2)+i]) +
center) * DIVIDEBY5;
}
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void stencil2DKernel(double* temperature, double* new_temperature, int block_x, int block_y, int thread_size) {
int i_start = (blockDim.x * blockIdx.x + threadIdx.x) * thread_size + 1;
int i_finish =
(blockDim.x * blockIdx.x + threadIdx.x) * thread_size + thread_size;
int j_start = (blockDim.y * blockIdx.y + threadIdx.y) * thread_size + 1;
int j_finish =
(blockDim.y * blockIdx.y + threadIdx.y) * thread_size + thread_size;
for (int i = i_start; i <= i_finish; i++) {
for (int j = j_start; j <= j_finish; j++) {
if (i <= block_x && j <= block_y) {
new_temperature[j * (block_x + 2) + i] =
(temperature[j * (block_x + 2) + (i - 1)] +
temperature[j * (block_x + 2) + (i + 1)] +
temperature[(j - 1) * (block_x + 2) + i] +
temperature[(j + 1) * (block_x + 2) + i] +
temperature[j * (block_x + 2) + i]) *
DIVIDEBY5;
}
}
}
/* TODO Use shared memory
int i = istart + threadIdx.x + blockDim.x*blockIdx.x;
int j = jstart + threadIdx.y + blockDim.y*blockIdx.y;
if (i < ifinish && j < jfinish) {
__shared__ double shared_temperature[TILE_SIZE][TILE_SIZE];
double center = temperature[j*(block_x+2)+i];
shared_temperature[threadIdx.x][threadIdx.y] = center;
__syncthreads();
// update my value based on the surrounding values
new_temperature[j*(block_x+2)+i] = (
((threadIdx.x > 1) ? shared_temperature[threadIdx.x-1][threadIdx.y] :
temperature[j*(block_x+2)+(i-1)]) +
((threadIdx.x < blockDim.x-1) ?
shared_temperature[threadIdx.x+1][threadIdx.y] :
temperature[j*(block_x+2)+(i+1)]) +
((threadIdx.y > 1) ? shared_temperature[threadIdx.x][threadIdx.y-1] :
temperature[(j-1)*(block_x+2)+i]) +
((threadIdx.y < blockDim.y-1) ?
shared_temperature[threadIdx.x][threadIdx.y+1] :
temperature[(j+1)*(block_x+2)+i]) +
center) * DIVIDEBY5;
}
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15stencil2DKernelPdS_iii
.globl _Z15stencil2DKernelPdS_iii
.p2align 8
.type _Z15stencil2DKernelPdS_iii,@function
_Z15stencil2DKernelPdS_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
v_and_b32_e32 v1, 0x3ff, v0
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s4
s_mov_b32 s4, exec_lo
v_add_nc_u32_e32 v2, s14, v1
v_mul_lo_u32 v3, v2, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s8, v3
v_add_nc_u32_e32 v5, 1, v3
v_cmpx_le_i32_e64 v5, v4
s_cbranch_execz .LBB0_9
s_load_b32 s4, s[2:3], 0xc
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s9, 0x3fc99999
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_add_i32 s10, s2, 2
v_mad_u64_u32 v[6:7], null, s15, s4, v[0:1]
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v6, s8
v_mul_lo_u32 v2, v6, s10
v_add_nc_u32_e32 v6, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add3_u32 v2, v1, v2, s14
v_add_nc_u32_e32 v7, s8, v0
v_mul_lo_u32 v8, s10, v6
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s8, v2, 1
s_mov_b32 s8, 0x9999999a
v_mad_u64_u32 v[1:2], null, s10, v6, v[3:4]
v_cmp_le_i32_e32 vcc_lo, v6, v7
v_add3_u32 v2, v3, v8, 1
.LBB0_2:
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz .LBB0_7
v_cmp_lt_i32_e64 s0, s2, v5
v_mov_b32_e32 v3, v6
s_mov_b32 s13, 0
s_mov_b32 s15, s11
s_delay_alu instid0(VALU_DEP_2)
s_xor_b32 s14, s0, -1
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v3, 1, v3
s_add_i32 s15, s15, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, v3, v7
s_or_b32 s13, s0, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_7
.LBB0_5:
v_cmp_ge_i32_e64 s0, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s14, s0
s_and_saveexec_b32 s16, s0
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v8, s15, v1
v_add_nc_u32_e32 v15, s15, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v10, 2, v8
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v16, 31, v15
v_add_nc_u32_e32 v17, 1, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[12:13], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[15:16], 3, v[15:16]
v_ashrrev_i32_e32 v18, 31, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 3, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, s0, s4, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v12, s0, s5, v13, s0
v_add_co_u32 v9, s0, s4, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s0, s5, v10, s0
v_add_nc_u32_e32 v13, s15, v0
v_lshlrev_b64 v[17:18], 3, v[17:18]
s_clause 0x1
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[9:10], v[9:10], off
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v13, s0, s4, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s0, s5, v14, s0
v_add_co_u32 v15, s0, s4, v15
v_add_co_ci_u32_e64 v16, s0, s5, v16, s0
global_load_b64 v[13:14], v[13:14], off
v_add_co_u32 v19, s0, s4, v17
global_load_b64 v[15:16], v[15:16], off
v_add_co_ci_u32_e64 v20, s0, s5, v18, s0
global_load_b64 v[19:20], v[19:20], off
s_waitcnt vmcnt(3)
v_add_f64 v[8:9], v[11:12], v[9:10]
v_add_co_u32 v10, s0, s6, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v11, s0, s7, v18, s0
s_waitcnt vmcnt(2)
v_add_f64 v[8:9], v[8:9], v[13:14]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], v[15:16]
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[8:9], v[19:20]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[8:9], v[8:9], s[8:9]
global_store_b64 v[10:11], v[8:9], off
s_branch .LBB0_4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s11, s11, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, v5, v4
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15stencil2DKernelPdS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15stencil2DKernelPdS_iii, .Lfunc_end0-_Z15stencil2DKernelPdS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15stencil2DKernelPdS_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z15stencil2DKernelPdS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void stencil2DKernel(double* temperature, double* new_temperature, int block_x, int block_y, int thread_size) {
int i_start = (blockDim.x * blockIdx.x + threadIdx.x) * thread_size + 1;
int i_finish =
(blockDim.x * blockIdx.x + threadIdx.x) * thread_size + thread_size;
int j_start = (blockDim.y * blockIdx.y + threadIdx.y) * thread_size + 1;
int j_finish =
(blockDim.y * blockIdx.y + threadIdx.y) * thread_size + thread_size;
for (int i = i_start; i <= i_finish; i++) {
for (int j = j_start; j <= j_finish; j++) {
if (i <= block_x && j <= block_y) {
new_temperature[j * (block_x + 2) + i] =
(temperature[j * (block_x + 2) + (i - 1)] +
temperature[j * (block_x + 2) + (i + 1)] +
temperature[(j - 1) * (block_x + 2) + i] +
temperature[(j + 1) * (block_x + 2) + i] +
temperature[j * (block_x + 2) + i]) *
DIVIDEBY5;
}
}
}
/* TODO Use shared memory
int i = istart + threadIdx.x + blockDim.x*blockIdx.x;
int j = jstart + threadIdx.y + blockDim.y*blockIdx.y;
if (i < ifinish && j < jfinish) {
__shared__ double shared_temperature[TILE_SIZE][TILE_SIZE];
double center = temperature[j*(block_x+2)+i];
shared_temperature[threadIdx.x][threadIdx.y] = center;
__syncthreads();
// update my value based on the surrounding values
new_temperature[j*(block_x+2)+i] = (
((threadIdx.x > 1) ? shared_temperature[threadIdx.x-1][threadIdx.y] :
temperature[j*(block_x+2)+(i-1)]) +
((threadIdx.x < blockDim.x-1) ?
shared_temperature[threadIdx.x+1][threadIdx.y] :
temperature[j*(block_x+2)+(i+1)]) +
((threadIdx.y > 1) ? shared_temperature[threadIdx.x][threadIdx.y-1] :
temperature[(j-1)*(block_x+2)+i]) +
((threadIdx.y < blockDim.y-1) ?
shared_temperature[threadIdx.x][threadIdx.y+1] :
temperature[(j+1)*(block_x+2)+i]) +
center) * DIVIDEBY5;
}
*/
} | .text
.file "stencil2DKernel.hip"
.globl _Z30__device_stub__stencil2DKernelPdS_iii # -- Begin function _Z30__device_stub__stencil2DKernelPdS_iii
.p2align 4, 0x90
.type _Z30__device_stub__stencil2DKernelPdS_iii,@function
_Z30__device_stub__stencil2DKernelPdS_iii: # @_Z30__device_stub__stencil2DKernelPdS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15stencil2DKernelPdS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__stencil2DKernelPdS_iii, .Lfunc_end0-_Z30__device_stub__stencil2DKernelPdS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15stencil2DKernelPdS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15stencil2DKernelPdS_iii,@object # @_Z15stencil2DKernelPdS_iii
.section .rodata,"a",@progbits
.globl _Z15stencil2DKernelPdS_iii
.p2align 3, 0x0
_Z15stencil2DKernelPdS_iii:
.quad _Z30__device_stub__stencil2DKernelPdS_iii
.size _Z15stencil2DKernelPdS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15stencil2DKernelPdS_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__stencil2DKernelPdS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15stencil2DKernelPdS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15stencil2DKernelPdS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0060*/ IMAD R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a24 */
/* 0x000fca00078e02ff */
/*0070*/ IADD3 R0, R4.reuse, c[0x0][0x178], RZ ; /* 0x00005e0004007a10 */
/* 0x040fe40007ffe0ff */
/*0080*/ IADD3 R9, R4, 0x1, RZ ; /* 0x0000000104097810 */
/* 0x000fc80007ffe0ff */
/*0090*/ ISETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff087624 */
/* 0x003fe200078e00ff */
/*00c0*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x000fe200078e0202 */
/*00e0*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IADD3 R2, R8, 0x2, RZ ; /* 0x0000000208027810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R7, R3, c[0x0][0x178], RZ ; /* 0x00005e0003077a24 */
/* 0x000fc800078e02ff */
/*0120*/ IMAD R3, R7.reuse, R2.reuse, RZ ; /* 0x0000000207037224 */
/* 0x0c0fe200078e02ff */
/*0130*/ IADD3 R5, R7.reuse, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x040fe40007ffe0ff */
/*0140*/ IADD3 R6, R7, c[0x0][0x178], RZ ; /* 0x00005e0007067a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD R8, R8, 0x2, R3 ; /* 0x0000000208087824 */
/* 0x000fe400078e0203 */
/*0160*/ IMAD R7, R5, R2, RZ ; /* 0x0000000205077224 */
/* 0x000fc600078e02ff */
/*0170*/ IADD3 R9, R8, 0x4, RZ ; /* 0x0000000408097810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GT.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x000fe20003f04270 */
/*0190*/ BSSY B0, 0x3b0 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fd600078e0004 */
/*01b0*/ @P0 BRA 0x3a0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R29, R7, R10, RZ ; /* 0x0000000a071d7210 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.IADD R27, R9, 0x1, R4.reuse ; /* 0x00000001091b7824 */
/* 0x100fe200078e0204 */
/*01e0*/ IADD3 R23, R3, R4, RZ ; /* 0x0000000403177210 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.IADD R25, R7, 0x1, R4 ; /* 0x0000000107197824 */
/* 0x000fe200078e0204 */
/*0200*/ MOV R22, R5 ; /* 0x0000000500167202 */
/* 0x000fc80000000f00 */
/*0210*/ ISETP.GT.AND P0, PT, R22, c[0x0][0x174], PT ; /* 0x00005d0016007a0c */
/* 0x000fc80003f04270 */
/*0220*/ ISETP.GT.OR P0, PT, R4, c[0x0][0x170], P0 ; /* 0x00005c0004007a0c */
/* 0x000fda0000704670 */
/*0230*/ @!P0 IMAD.MOV.U32 R24, RZ, RZ, 0x8 ; /* 0x00000008ff188424 */
/* 0x000fc800078e00ff */
/*0240*/ @!P0 IMAD.WIDE R12, R29, R24, c[0x0][0x160] ; /* 0x000058001d0c8625 */
/* 0x000fc800078e0218 */
/*0250*/ @!P0 IMAD.WIDE R14, R23, R24.reuse, c[0x0][0x160] ; /* 0x00005800170e8625 */
/* 0x080fe200078e0218 */
/*0260*/ @!P0 LDG.E.64 R16, [R12.64+0x10] ; /* 0x000010040c108981 */
/* 0x000ea8000c1e1b00 */
/*0270*/ @!P0 LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a8981 */
/* 0x000ea2000c1e1b00 */
/*0280*/ @!P0 IMAD.WIDE R18, R27, R24, c[0x0][0x160] ; /* 0x000058001b128625 */
/* 0x000fc600078e0218 */
/*0290*/ @!P0 LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e8981 */
/* 0x000ee8000c1e1b00 */
/*02a0*/ @!P0 LDG.E.64 R18, [R18.64] ; /* 0x0000000412128981 */
/* 0x000f28000c1e1b00 */
/*02b0*/ @!P0 LDG.E.64 R20, [R12.64+0x8] ; /* 0x000008040c148981 */
/* 0x000f62000c1e1b00 */
/*02c0*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ IMAD.IADD R23, R2.reuse, 0x1, R23 ; /* 0x0000000102177824 */
/* 0x040fe200078e0217 */
/*02e0*/ IADD3 R29, R2, R29, RZ ; /* 0x0000001d021d7210 */
/* 0x000fc40007ffe0ff */
/*02f0*/ IADD3 R27, R2, R27, RZ ; /* 0x0000001b021b7210 */
/* 0x000fe20007ffe0ff */
/*0300*/ @!P0 DADD R10, R16, R10 ; /* 0x00000000100a8229 */
/* 0x0040e4000000000a */
/*0310*/ @!P0 IMAD.WIDE R16, R25, R24, c[0x0][0x168] ; /* 0x00005a0019108625 */
/* 0x001fc800078e0218 */
/*0320*/ @!P0 DADD R10, R10, R14 ; /* 0x000000000a0a8229 */
/* 0x008f22000000000e */
/*0330*/ IMAD.IADD R25, R2, 0x1, R25 ; /* 0x0000000102197824 */
/* 0x000fca00078e0219 */
/*0340*/ @!P0 DADD R10, R10, R18 ; /* 0x000000000a0a8229 */
/* 0x010f4c0000000012 */
/*0350*/ @!P0 DADD R10, R10, R20 ; /* 0x000000000a0a8229 */
/* 0x020e0c0000000014 */
/*0360*/ @!P0 DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a8a28 */
/* 0x001e0e0000000000 */
/*0370*/ @!P0 STG.E.64 [R16.64], R10 ; /* 0x0000000a10008986 */
/* 0x0011e2000c101b04 */
/*0380*/ ISETP.GT.AND P0, PT, R22, R6, PT ; /* 0x000000061600720c */
/* 0x000fda0003f04270 */
/*0390*/ @!P0 BRA 0x210 ; /* 0xfffffe7000008947 */
/* 0x001fea000383ffff */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fe40000000f00 */
/*03d0*/ ISETP.GT.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fda0003f04270 */
/*03e0*/ @!P0 BRA 0x180 ; /* 0xfffffd9000008947 */
/* 0x000fea000383ffff */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ BRA 0x400; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15stencil2DKernelPdS_iii
.globl _Z15stencil2DKernelPdS_iii
.p2align 8
.type _Z15stencil2DKernelPdS_iii,@function
_Z15stencil2DKernelPdS_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
v_and_b32_e32 v1, 0x3ff, v0
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s4
s_mov_b32 s4, exec_lo
v_add_nc_u32_e32 v2, s14, v1
v_mul_lo_u32 v3, v2, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s8, v3
v_add_nc_u32_e32 v5, 1, v3
v_cmpx_le_i32_e64 v5, v4
s_cbranch_execz .LBB0_9
s_load_b32 s4, s[2:3], 0xc
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s9, 0x3fc99999
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_add_i32 s10, s2, 2
v_mad_u64_u32 v[6:7], null, s15, s4, v[0:1]
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v6, s8
v_mul_lo_u32 v2, v6, s10
v_add_nc_u32_e32 v6, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add3_u32 v2, v1, v2, s14
v_add_nc_u32_e32 v7, s8, v0
v_mul_lo_u32 v8, s10, v6
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s8, v2, 1
s_mov_b32 s8, 0x9999999a
v_mad_u64_u32 v[1:2], null, s10, v6, v[3:4]
v_cmp_le_i32_e32 vcc_lo, v6, v7
v_add3_u32 v2, v3, v8, 1
.LBB0_2:
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz .LBB0_7
v_cmp_lt_i32_e64 s0, s2, v5
v_mov_b32_e32 v3, v6
s_mov_b32 s13, 0
s_mov_b32 s15, s11
s_delay_alu instid0(VALU_DEP_2)
s_xor_b32 s14, s0, -1
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v3, 1, v3
s_add_i32 s15, s15, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, v3, v7
s_or_b32 s13, s0, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_7
.LBB0_5:
v_cmp_ge_i32_e64 s0, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s14, s0
s_and_saveexec_b32 s16, s0
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v8, s15, v1
v_add_nc_u32_e32 v15, s15, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v10, 2, v8
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v16, 31, v15
v_add_nc_u32_e32 v17, 1, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[12:13], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[15:16], 3, v[15:16]
v_ashrrev_i32_e32 v18, 31, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 3, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, s0, s4, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v12, s0, s5, v13, s0
v_add_co_u32 v9, s0, s4, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s0, s5, v10, s0
v_add_nc_u32_e32 v13, s15, v0
v_lshlrev_b64 v[17:18], 3, v[17:18]
s_clause 0x1
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[9:10], v[9:10], off
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v13, s0, s4, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s0, s5, v14, s0
v_add_co_u32 v15, s0, s4, v15
v_add_co_ci_u32_e64 v16, s0, s5, v16, s0
global_load_b64 v[13:14], v[13:14], off
v_add_co_u32 v19, s0, s4, v17
global_load_b64 v[15:16], v[15:16], off
v_add_co_ci_u32_e64 v20, s0, s5, v18, s0
global_load_b64 v[19:20], v[19:20], off
s_waitcnt vmcnt(3)
v_add_f64 v[8:9], v[11:12], v[9:10]
v_add_co_u32 v10, s0, s6, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v11, s0, s7, v18, s0
s_waitcnt vmcnt(2)
v_add_f64 v[8:9], v[8:9], v[13:14]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], v[15:16]
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[8:9], v[19:20]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[8:9], v[8:9], s[8:9]
global_store_b64 v[10:11], v[8:9], off
s_branch .LBB0_4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s11, s11, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, v5, v4
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15stencil2DKernelPdS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15stencil2DKernelPdS_iii, .Lfunc_end0-_Z15stencil2DKernelPdS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15stencil2DKernelPdS_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z15stencil2DKernelPdS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00166364_00000000-6_stencil2DKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii
.type _Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii, @function
_Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15stencil2DKernelPdS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii, .-_Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii
.globl _Z15stencil2DKernelPdS_iii
.type _Z15stencil2DKernelPdS_iii, @function
_Z15stencil2DKernelPdS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15stencil2DKernelPdS_iiiPdS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15stencil2DKernelPdS_iii, .-_Z15stencil2DKernelPdS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15stencil2DKernelPdS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15stencil2DKernelPdS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stencil2DKernel.hip"
.globl _Z30__device_stub__stencil2DKernelPdS_iii # -- Begin function _Z30__device_stub__stencil2DKernelPdS_iii
.p2align 4, 0x90
.type _Z30__device_stub__stencil2DKernelPdS_iii,@function
_Z30__device_stub__stencil2DKernelPdS_iii: # @_Z30__device_stub__stencil2DKernelPdS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15stencil2DKernelPdS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__stencil2DKernelPdS_iii, .Lfunc_end0-_Z30__device_stub__stencil2DKernelPdS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15stencil2DKernelPdS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15stencil2DKernelPdS_iii,@object # @_Z15stencil2DKernelPdS_iii
.section .rodata,"a",@progbits
.globl _Z15stencil2DKernelPdS_iii
.p2align 3, 0x0
_Z15stencil2DKernelPdS_iii:
.quad _Z30__device_stub__stencil2DKernelPdS_iii
.size _Z15stencil2DKernelPdS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15stencil2DKernelPdS_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__stencil2DKernelPdS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15stencil2DKernelPdS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | # include <stdio.h>
# include <stdint.h>
# include "cuda_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
cudaSetDevice(1);
measure_global();
cudaDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 592*256*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
cudaDeviceReset();
cudaError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != cudaSuccess) {
printf("Error 1.0 is %s\n", cudaGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// 16MB*33
for (i=0; i<33; i++){
h_a[i * 1024 * 256 * 16] = (i+1)*256*1024*16;
h_a[i * 1024 * 256 * 16+1] = (1+i) * 1024 * 256 * 16+1;
}
// 1MB*63
for (i=0; i<63 ; i++){
h_a[(528+i)*256*1024] = (529+i)*256*1024;
}
h_a[528*256*1024+1] = 528*256*1024+2;
h_a[528*256*1024+2] = 528*256*1024+3;
h_a[528*256*1024+3] = 528*256*1024+1;
h_a[591*256*1024 ] = 1;
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
if (error_id != cudaSuccess) {
printf("Error 1.1 is %s\n", cudaGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *duration;
error_id = cudaMalloc ((void **) &duration, sizeof(unsigned int)*160);
if (error_id != cudaSuccess) {
printf("Error 1.2 is %s\n", cudaGetErrorString(error_id));
}
unsigned int *d_index;
error_id = cudaMalloc( (void **) &d_index, sizeof(unsigned int)*160 );
if (error_id != cudaSuccess) {
printf("Error 1.3 is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
cudaThreadSynchronize ();
error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
printf("Error kernel is %s\n", cudaGetErrorString(error_id));
}
/* copy results from GPU to CPU */
cudaThreadSynchronize ();
error_id = cudaMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) {
printf("Error 2.0 is %s\n", cudaGetErrorString(error_id));
}
error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) {
printf("Error 2.1 is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize ();
for(i=0;i<160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
cudaFree(d_a);
cudaFree(d_index);
cudaFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
cudaDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[160];
__shared__ unsigned int s_index[160];
int k;
for(k=0; k<160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
// for (k = 0; k < iterations*256; k++)
// j = my_array[j];
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} | .file "tmpxft_000ed11b_00000000-6_pattern_fermi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
.type _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_, @function
_Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14global_latencyPjiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_, .-_Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
.globl _Z14global_latencyPjiiS_S_
.type _Z14global_latencyPjiiS_S_, @function
_Z14global_latencyPjiiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14global_latencyPjiiS_S_, .-_Z14global_latencyPjiiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error 1.0 is %s\n"
.LC1:
.string "Error 1.1 is %s\n"
.LC2:
.string "Error 1.2 is %s\n"
.LC3:
.string "Error 1.3 is %s\n"
.LC4:
.string "Error kernel is %s\n"
.LC5:
.string "Error 2.0 is %s\n"
.LC6:
.string "Error 2.1 is %s\n"
.LC7:
.string "%d\t %d\n"
.text
.globl _Z25parametric_measure_globalii
.type _Z25parametric_measure_globalii, @function
_Z25parametric_measure_globalii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r12d
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaDeviceReset@PLT
leal 2(%r12), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
.L12:
testl %r12d, %r12d
jle .L13
movq %rbp, %rax
leaq -8(%rbp,%rbx), %rdx
.L14:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
.L13:
movq %rbp, %rdx
movl $4194305, %eax
.L15:
leal -1(%rax), %ecx
movl %ecx, (%rdx)
movl %eax, 4(%rdx)
addq $16777216, %rdx
addl $4194304, %eax
cmpl $142606337, %eax
jne .L15
leaq 553648128(%rbp), %rdx
movl $138674176, %eax
.L16:
movl %eax, (%rdx)
addl $262144, %eax
addq $1048576, %rdx
cmpl $155189248, %eax
jne .L16
movl $138412034, 553648132(%rbp)
movl $138412035, 553648136(%rbp)
movl $138412033, 553648140(%rbp)
movl $1, 619708416(%rbp)
leaq -8(%rbx), %rdx
movl $0, -8(%rbp,%rbx)
movl $0, -4(%rbp,%rbx)
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
.L17:
movl $640, %edi
call malloc@PLT
movq %rax, %r15
movl $640, %edi
call malloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $640, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
.L18:
leaq 24(%rsp), %rdi
movl $640, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
.L19:
call cudaThreadSynchronize@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L20:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
.L21:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $640, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
.L22:
movl $2, %ecx
movl $640, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
.L23:
call cudaThreadSynchronize@PLT
movl $0, %ebx
leaq .LC7(%rip), %r12
.L24:
movl (%r14,%rbx), %ecx
movl (%r15,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $640, %rbx
jne .L24
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L35:
movq 24(%rsp), %r8
movq 16(%rsp), %rcx
movl %r13d, %edx
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
jmp .L20
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z25parametric_measure_globalii, .-_Z25parametric_measure_globalii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n"
.align 8
.LC10:
.string "===============================================\n\n"
.text
.globl _Z14measure_globalv
.type _Z14measure_globalv, @function
_Z14measure_globalv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %esi
movl $155189248, %edi
call _Z25parametric_measure_globalii
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z14measure_globalv, .-_Z14measure_globalv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call cudaSetDevice@PLT
call _Z14measure_globalv
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z14global_latencyPjiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z14global_latencyPjiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1082294272
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | # include <stdio.h>
# include <stdint.h>
# include "cuda_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
cudaSetDevice(1);
measure_global();
cudaDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 592*256*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
cudaDeviceReset();
cudaError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != cudaSuccess) {
printf("Error 1.0 is %s\n", cudaGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// 16MB*33
for (i=0; i<33; i++){
h_a[i * 1024 * 256 * 16] = (i+1)*256*1024*16;
h_a[i * 1024 * 256 * 16+1] = (1+i) * 1024 * 256 * 16+1;
}
// 1MB*63
for (i=0; i<63 ; i++){
h_a[(528+i)*256*1024] = (529+i)*256*1024;
}
h_a[528*256*1024+1] = 528*256*1024+2;
h_a[528*256*1024+2] = 528*256*1024+3;
h_a[528*256*1024+3] = 528*256*1024+1;
h_a[591*256*1024 ] = 1;
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
if (error_id != cudaSuccess) {
printf("Error 1.1 is %s\n", cudaGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *duration;
error_id = cudaMalloc ((void **) &duration, sizeof(unsigned int)*160);
if (error_id != cudaSuccess) {
printf("Error 1.2 is %s\n", cudaGetErrorString(error_id));
}
unsigned int *d_index;
error_id = cudaMalloc( (void **) &d_index, sizeof(unsigned int)*160 );
if (error_id != cudaSuccess) {
printf("Error 1.3 is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
cudaThreadSynchronize ();
error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
printf("Error kernel is %s\n", cudaGetErrorString(error_id));
}
/* copy results from GPU to CPU */
cudaThreadSynchronize ();
error_id = cudaMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) {
printf("Error 2.0 is %s\n", cudaGetErrorString(error_id));
}
error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) {
printf("Error 2.1 is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize ();
for(i=0;i<160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
cudaFree(d_a);
cudaFree(d_index);
cudaFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
cudaDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[160];
__shared__ unsigned int s_index[160];
int k;
for(k=0; k<160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
// for (k = 0; k < iterations*256; k++)
// j = my_array[j];
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} | # include <stdio.h>
# include <stdint.h>
# include "hip/hip_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
hipSetDevice(1);
measure_global();
hipDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 592*256*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
hipDeviceReset();
hipError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = hipMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != hipSuccess) {
printf("Error 1.0 is %s\n", hipGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// 16MB*33
for (i=0; i<33; i++){
h_a[i * 1024 * 256 * 16] = (i+1)*256*1024*16;
h_a[i * 1024 * 256 * 16+1] = (1+i) * 1024 * 256 * 16+1;
}
// 1MB*63
for (i=0; i<63 ; i++){
h_a[(528+i)*256*1024] = (529+i)*256*1024;
}
h_a[528*256*1024+1] = 528*256*1024+2;
h_a[528*256*1024+2] = 528*256*1024+3;
h_a[528*256*1024+3] = 528*256*1024+1;
h_a[591*256*1024 ] = 1;
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = hipMemcpy(d_a, h_a, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
if (error_id != hipSuccess) {
printf("Error 1.1 is %s\n", hipGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *duration;
error_id = hipMalloc ((void **) &duration, sizeof(unsigned int)*160);
if (error_id != hipSuccess) {
printf("Error 1.2 is %s\n", hipGetErrorString(error_id));
}
unsigned int *d_index;
error_id = hipMalloc( (void **) &d_index, sizeof(unsigned int)*160 );
if (error_id != hipSuccess) {
printf("Error 1.3 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
hipDeviceSynchronize ();
error_id = hipGetLastError();
if (error_id != hipSuccess) {
printf("Error kernel is %s\n", hipGetErrorString(error_id));
}
/* copy results from GPU to CPU */
hipDeviceSynchronize ();
error_id = hipMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.0 is %s\n", hipGetErrorString(error_id));
}
error_id = hipMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.1 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
for(i=0;i<160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
hipFree(d_a);
hipFree(d_index);
hipFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
hipDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[160];
__shared__ unsigned int s_index[160];
int k;
for(k=0; k<160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
// for (k = 0; k < iterations*256; k++)
// j = my_array[j];
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | # include <stdio.h>
# include <stdint.h>
# include "hip/hip_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
hipSetDevice(1);
measure_global();
hipDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 592*256*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
hipDeviceReset();
hipError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = hipMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != hipSuccess) {
printf("Error 1.0 is %s\n", hipGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// 16MB*33
for (i=0; i<33; i++){
h_a[i * 1024 * 256 * 16] = (i+1)*256*1024*16;
h_a[i * 1024 * 256 * 16+1] = (1+i) * 1024 * 256 * 16+1;
}
// 1MB*63
for (i=0; i<63 ; i++){
h_a[(528+i)*256*1024] = (529+i)*256*1024;
}
h_a[528*256*1024+1] = 528*256*1024+2;
h_a[528*256*1024+2] = 528*256*1024+3;
h_a[528*256*1024+3] = 528*256*1024+1;
h_a[591*256*1024 ] = 1;
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = hipMemcpy(d_a, h_a, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
if (error_id != hipSuccess) {
printf("Error 1.1 is %s\n", hipGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160);
unsigned int *duration;
error_id = hipMalloc ((void **) &duration, sizeof(unsigned int)*160);
if (error_id != hipSuccess) {
printf("Error 1.2 is %s\n", hipGetErrorString(error_id));
}
unsigned int *d_index;
error_id = hipMalloc( (void **) &d_index, sizeof(unsigned int)*160 );
if (error_id != hipSuccess) {
printf("Error 1.3 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
hipDeviceSynchronize ();
error_id = hipGetLastError();
if (error_id != hipSuccess) {
printf("Error kernel is %s\n", hipGetErrorString(error_id));
}
/* copy results from GPU to CPU */
hipDeviceSynchronize ();
error_id = hipMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.0 is %s\n", hipGetErrorString(error_id));
}
error_id = hipMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.1 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
for(i=0;i<160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
hipFree(d_a);
hipFree(d_index);
hipFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
hipDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[160];
__shared__ unsigned int s_index[160];
int k;
for(k=0; k<160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
// for (k = 0; k < iterations*256; k++)
// j = my_array[j];
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14global_latencyPjiiS_S_
.globl _Z14global_latencyPjiiS_S_
.p2align 8
.type _Z14global_latencyPjiiS_S_,@function
_Z14global_latencyPjiiS_S_:
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
.LBB0_1:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_cmpk_eq_i32 s2, 0x280
ds_store_2addr_b32 v1, v0, v0 offset1:160
s_cbranch_scc0 .LBB0_1
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_mulk_i32 s2, 0xa0
s_mov_b32 s3, 0
s_max_i32 s2, s2, 1
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_getreg_b32 s6, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_add_i32 s2, s2, -1
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
v_mov_b32_e32 v2, s3
s_add_i32 s3, s3, 4
s_waitcnt vmcnt(0)
ds_store_b32 v2, v0
s_getreg_b32 s7, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s6, s7, s6
s_cmp_lg_u32 s2, 0
v_mov_b32_e32 v3, s6
ds_store_b32 v2, v3 offset:640
s_cbranch_scc1 .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6:
s_load_b32 s6, s[0:1], 0x8
v_mov_b32_e32 v1, 0
s_load_b128 s[0:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s4, s6
s_addc_u32 s9, s5, s7
s_mov_b64 s[4:5], 0
global_store_b32 v1, v0, s[8:9]
global_load_b32 v0, v[2:3], off
s_mov_b32 s6, 0
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[8:9] offset:4
.LBB0_7:
v_mov_b32_e32 v0, s6
s_add_u32 s8, s2, s4
s_addc_u32 s9, s3, s5
s_add_u32 s10, s0, s4
s_addc_u32 s11, s1, s5
ds_load_2addr_b32 v[2:3], v0 offset1:160
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_i32 s6, s6, 4
s_cmpk_lg_i32 s4, 0x280
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v1, v2, s[8:9]
global_store_b32 v1, v3, s[10:11]
s_cbranch_scc1 .LBB0_7
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14global_latencyPjiiS_S_
.amdhsa_group_segment_fixed_size 1280
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14global_latencyPjiiS_S_, .Lfunc_end0-_Z14global_latencyPjiiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1280
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14global_latencyPjiiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z14global_latencyPjiiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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