system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Matrix Multiply
#include<stdio.h>
// perform MatrixMul on Device
__global__ void MatrixMulDevice( float *A, float *B, float *C, int *matrixSize)
{
int chunk = (*matrixSize) / gridDim.x;
int sum, i, k;
for(i = blockIdx.x * chunk; i < blockIdx.x * chunk + chunk - 1; i++) {
sum = 0;
for(k = 0; k < *matrixSize; k++) {
sum += A[i * *matrixSize + k] * B [k * *matrixSize + threadIdx.x];
}
C[i * *matrixSize + threadIdx.x] = sum;
}
}
int MatrixMulHostValidate(float *A, float *B, float *C, int dim)
{
float a, b, sum;
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
sum = 0;
for (int k = 0; k < dim; k++) {
a = A[ i* dim + k ];
b = B[ k * dim + j ];
sum += a * b;
}
if (C[ i* dim + j ] != sum)
return 0;
}
}
return 1;
}
void initMatrix(float *A, int dim) {
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
A[i* dim + j] = ((float)i + j) / dim;
}
}
}
int main(void) {
float *A, *B, *C;
int dim = 512;
float *d_A, *d_B, *d_C;
int *d_matrixSize;
// Allocate memory for the matrices.
A = (float *) malloc(sizeof(float) * dim * dim);
B = (float *) malloc(sizeof(float) * dim * dim);
C = (float *) malloc(sizeof(float) * dim * dim);
// I/O to load A, B and C.
initMatrix(A, dim);
initMatrix(B, dim);
// define thread hierarchy
int nblocks= 4;
int tpb= 512;
// allocate device memory
size_t memSize;
memSize= dim * dim * sizeof(float);
cudaMalloc( (void**) &d_A, memSize);
cudaMalloc( (void**) &d_B, memSize);
cudaMalloc( (void**) &d_C, memSize);
cudaMalloc( (void**) &d_matrixSize, sizeof(float));
// initialize device memory
cudaMemcpy(d_A, A, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_matrixSize, &dim, sizeof(float), cudaMemcpyHostToDevice);
// launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
// perform MatrixMulon Device
MatrixMulDevice<<< dimGrid, dimBlock>>>(d_A, d_B, d_C, d_matrixSize);
// retrieve results
cudaMemcpy(C, d_C, memSize, cudaMemcpyDeviceToHost);
// verfiy results
if(!MatrixMulHostValidate(A, B, C, dim))
fprintf(stderr, "Wrong results for matrix multiply\n");
else
printf("Matrix multiply was successful\n");
// Free memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFree(d_matrixSize);
free(A);
free(B);
free(C);
} | code for sm_80
Function : _Z15MatrixMulDevicePfS_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*0050*/ I2F.U32.RP R6, c[0x0][0xc] ; /* 0x0000030000067b06 */
/* 0x000e220000209000 */
/*0060*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fce0003f45070 */
/*0070*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*00c0*/ IMAD R7, R7, c[0x0][0xc], RZ ; /* 0x0000030007077a24 */
/* 0x000fca00078e02ff */
/*00d0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe400078e0004 */
/*00e0*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*00f0*/ IMAD.HI.U32 R5, R5, R0, RZ ; /* 0x0000000005057227 */
/* 0x004fc800078e00ff */
/*0100*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a05 */
/*0110*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0xc], PT ; /* 0x0000030000007a0c */
/* 0x000fda0003f06070 */
/*0130*/ @P0 IADD3 R0, R0, -c[0x0][0xc], RZ ; /* 0x8000030000000a10 */
/* 0x000fe40007ffe0ff */
/*0140*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0xc], PT ; /* 0x0000030000007a0c */
/* 0x000fda0003f26070 */
/*0160*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0170*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0xc], RZ, 0x33, !PT ; /* 0x00000300ff05aa12 */
/* 0x000fca00078e33ff */
/*0180*/ IMAD R15, R5, R4, RZ ; /* 0x00000004050f7224 */
/* 0x001fca00078e02ff */
/*0190*/ IADD3 R0, R5, -0x1, R15 ; /* 0xffffffff05007810 */
/* 0x000fc80007ffe00f */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R15, R0, PT ; /* 0x000000000f00720c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01c0*/ S2R R14, SR_TID.X ; /* 0x00000000000e7919 */
/* 0x000e240000002100 */
/*01d0*/ LDG.E R17, [R2.64] ; /* 0x0000000602117981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ ISETP.GT.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x004fda0003f04270 */
/*01f0*/ @!P0 MOV R21, RZ ; /* 0x000000ff00158202 */
/* 0x001fe20000000f00 */
/*0200*/ @!P0 BRA 0x6f0 ; /* 0x000004e000008947 */
/* 0x000fea0003800000 */
/*0210*/ IADD3 R4, R17.reuse, -0x1, RZ ; /* 0xffffffff11047810 */
/* 0x040fe20007ffe0ff */
/*0220*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0230*/ LOP3.LUT R16, R17.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000311107812 */
/* 0x040fe200078ec0ff */
/*0240*/ IMAD R18, R17, R15, RZ ; /* 0x0000000f11127224 */
/* 0x000fe200078e02ff */
/*0250*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0260*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f05270 */
/*0280*/ @!P1 BRA 0x530 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0290*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*02a0*/ IMAD.IADD R22, R17.reuse, 0x1, R14.reuse ; /* 0x0000000111167824 */
/* 0x141fe200078e020e */
/*02b0*/ LEA R20, R17.reuse, R14.reuse, 0x1 ; /* 0x0000000e11147211 */
/* 0x0c0fe200078e08ff */
/*02c0*/ IMAD R24, R17, 0x3, R14 ; /* 0x0000000311187824 */
/* 0x000fe200078e020e */
/*02d0*/ MOV R26, R14 ; /* 0x0000000e001a7202 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.IADD R27, R16, 0x1, -R17 ; /* 0x00000001101b7824 */
/* 0x000fe200078e0a11 */
/*02f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc80008000000 */
/*0300*/ IMAD.WIDE R4, R18, R19, c[0x0][0x160] ; /* 0x0000580012047625 */
/* 0x000fc800078e0213 */
/*0310*/ IMAD.WIDE.U32 R6, R26, R19.reuse, c[0x0][0x168] ; /* 0x00005a001a067625 */
/* 0x080fe200078e0013 */
/*0320*/ LDG.E R23, [R4.64] ; /* 0x0000000604177981 */
/* 0x0010a6000c1e1900 */
/*0330*/ IMAD.WIDE.U32 R8, R22, R19.reuse, c[0x0][0x168] ; /* 0x00005a0016087625 */
/* 0x080fe200078e0013 */
/*0340*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040604197981 */
/* 0x0000e8000c1e1900 */
/*0350*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee2000c1e1900 */
/*0370*/ IMAD.WIDE.U32 R10, R20, R19, c[0x0][0x168] ; /* 0x00005a00140a7625 */
/* 0x000fc600078e0013 */
/*0380*/ LDG.E R29, [R4.64+0x8] ; /* 0x00000806041d7981 */
/* 0x000128000c1e1900 */
/*0390*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f22000c1e1900 */
/*03a0*/ IMAD.WIDE.U32 R12, R24, R19, c[0x0][0x168] ; /* 0x00005a00180c7625 */
/* 0x000fc600078e0013 */
/*03b0*/ LDG.E R28, [R4.64+0xc] ; /* 0x00000c06041c7981 */
/* 0x000168000c1e1900 */
/*03c0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f62000c1e1900 */
/*03d0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002ea20000201400 */
/*03e0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*03f0*/ IADD3 R4, P2, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x001fe20007f5e0ff */
/*0400*/ IMAD R24, R17.reuse, 0x4, R24 ; /* 0x0000000411187824 */
/* 0x040fe200078e0218 */
/*0410*/ LEA R22, R17.reuse, R22, 0x2 ; /* 0x0000001611167211 */
/* 0x040fe400078e10ff */
/*0420*/ LEA R20, R17.reuse, R20, 0x2 ; /* 0x0000001411147211 */
/* 0x040fe200078e10ff */
/*0430*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0440*/ LEA R26, R17, R26, 0x2 ; /* 0x0000001a111a7211 */
/* 0x000fe200078e10ff */
/*0450*/ FFMA R6, R6, R23, R21 ; /* 0x0000001706067223 */
/* 0x004fcc0000000015 */
/*0460*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*0470*/ I2F R7, R6 ; /* 0x0000000600077306 */
/* 0x001ee40000201400 */
/*0480*/ FFMA R7, R8, R25, R7 ; /* 0x0000001908077223 */
/* 0x008fcc0000000007 */
/*0490*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*04a0*/ I2F R8, R7 ; /* 0x0000000700087306 */
/* 0x001f240000201400 */
/*04b0*/ FFMA R8, R10, R29, R8 ; /* 0x0000001d0a087223 */
/* 0x010fcc0000000008 */
/*04c0*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e22000020f100 */
/*04d0*/ IADD3 R10, R27, UR4, RZ ; /* 0x000000041b0a7c10 */
/* 0x000fce000fffe0ff */
/*04e0*/ I2F R9, R8 ; /* 0x0000000800097306 */
/* 0x001f620000201400 */
/*04f0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0500*/ FFMA R9, R12, R28, R9 ; /* 0x0000001c0c097223 */
/* 0x020fcc0000000009 */
/*0510*/ F2I.TRUNC.NTZ R21, R9 ; /* 0x0000000900157305 */
/* 0x00006c000020f100 */
/*0520*/ @P1 BRA 0x310 ; /* 0xfffffde000001947 */
/* 0x000fea000383ffff */
/*0530*/ @!P0 BRA 0x6f0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0540*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0550*/ IADD3 R4, R18, UR4, RZ ; /* 0x0000000412047c10 */
/* 0x000fe2000fffe0ff */
/*0560*/ IMAD R8, R17, UR4, R14 ; /* 0x0000000411087c24 */
/* 0x001fd0000f8e020e */
/*0570*/ IMAD.WIDE.U32 R6, R8, R13, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fc800078e000d */
/*0580*/ IMAD.WIDE R4, R4, R13, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e020d */
/*0590*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002ea20000201400 */
/*05c0*/ ISETP.NE.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe20003f05270 */
/*05d0*/ FFMA R9, R6, R9, R21 ; /* 0x0000000906097223 */
/* 0x004fcc0000000015 */
/*05e0*/ F2I.TRUNC.NTZ R21, R9 ; /* 0x0000000900157305 */
/* 0x00006c000020f100 */
/*05f0*/ @!P0 BRA 0x6f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0600*/ IMAD.IADD R8, R17, 0x1, R8 ; /* 0x0000000111087824 */
/* 0x000fe200078e0208 */
/*0610*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x000ea6000c1e1900 */
/*0620*/ IMAD.WIDE.U32 R6, R8, R13, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fcc00078e000d */
/*0630*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1900 */
/*0640*/ ISETP.NE.AND P0, PT, R16, 0x2, PT ; /* 0x000000021000780c */
/* 0x000fda0003f05270 */
/*0650*/ @P0 IADD3 R8, R17, R8, RZ ; /* 0x0000000811080210 */
/* 0x000fca0007ffe0ff */
/*0660*/ @P0 IMAD.WIDE.U32 R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008080625 */
/* 0x001fe400078e000d */
/*0670*/ @P0 LDG.E R13, [R4.64+0x8] ; /* 0x00000806040d0981 */
/* 0x000ee8000c1e1900 */
/*0680*/ @P0 LDG.E R8, [R8.64] ; /* 0x0000000608080981 */
/* 0x000ee2000c1e1900 */
/*0690*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002ea40000201400 */
/*06a0*/ FFMA R11, R6, R11, R21 ; /* 0x0000000b060b7223 */
/* 0x004fcc0000000015 */
/*06b0*/ F2I.TRUNC.NTZ R21, R11 ; /* 0x0000000b00157305 */
/* 0x000e30000020f100 */
/*06c0*/ @P0 I2F R10, R21 ; /* 0x00000015000a0306 */
/* 0x001ee40000201400 */
/*06d0*/ @P0 FFMA R13, R8, R13, R10 ; /* 0x0000000d080d0223 */
/* 0x008fcc000000000a */
/*06e0*/ @P0 F2I.TRUNC.NTZ R21, R13 ; /* 0x0000000d00150305 */
/* 0x000064000020f100 */
/*06f0*/ IMAD R4, R17, R15, R14 ; /* 0x0000000f11047224 */
/* 0x001fe200078e020e */
/*0700*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002e220000201400 */
/*0710*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe40007ffe0ff */
/*0720*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe40000000f00 */
/*0730*/ ISETP.GE.U32.AND P0, PT, R15, R0, PT ; /* 0x000000000f00720c */
/* 0x000fc60003f06070 */
/*0740*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0005 */
/*0750*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0011ea000c101906 */
/*0760*/ @!P0 BRA 0x1d0 ; /* 0xfffffa6000008947 */
/* 0x000fea000383ffff */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Matrix Multiply
#include<stdio.h>
// perform MatrixMul on Device
__global__ void MatrixMulDevice( float *A, float *B, float *C, int *matrixSize)
{
int chunk = (*matrixSize) / gridDim.x;
int sum, i, k;
for(i = blockIdx.x * chunk; i < blockIdx.x * chunk + chunk - 1; i++) {
sum = 0;
for(k = 0; k < *matrixSize; k++) {
sum += A[i * *matrixSize + k] * B [k * *matrixSize + threadIdx.x];
}
C[i * *matrixSize + threadIdx.x] = sum;
}
}
int MatrixMulHostValidate(float *A, float *B, float *C, int dim)
{
float a, b, sum;
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
sum = 0;
for (int k = 0; k < dim; k++) {
a = A[ i* dim + k ];
b = B[ k * dim + j ];
sum += a * b;
}
if (C[ i* dim + j ] != sum)
return 0;
}
}
return 1;
}
void initMatrix(float *A, int dim) {
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
A[i* dim + j] = ((float)i + j) / dim;
}
}
}
int main(void) {
float *A, *B, *C;
int dim = 512;
float *d_A, *d_B, *d_C;
int *d_matrixSize;
// Allocate memory for the matrices.
A = (float *) malloc(sizeof(float) * dim * dim);
B = (float *) malloc(sizeof(float) * dim * dim);
C = (float *) malloc(sizeof(float) * dim * dim);
// I/O to load A, B and C.
initMatrix(A, dim);
initMatrix(B, dim);
// define thread hierarchy
int nblocks= 4;
int tpb= 512;
// allocate device memory
size_t memSize;
memSize= dim * dim * sizeof(float);
cudaMalloc( (void**) &d_A, memSize);
cudaMalloc( (void**) &d_B, memSize);
cudaMalloc( (void**) &d_C, memSize);
cudaMalloc( (void**) &d_matrixSize, sizeof(float));
// initialize device memory
cudaMemcpy(d_A, A, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_matrixSize, &dim, sizeof(float), cudaMemcpyHostToDevice);
// launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
// perform MatrixMulon Device
MatrixMulDevice<<< dimGrid, dimBlock>>>(d_A, d_B, d_C, d_matrixSize);
// retrieve results
cudaMemcpy(C, d_C, memSize, cudaMemcpyDeviceToHost);
// verfiy results
if(!MatrixMulHostValidate(A, B, C, dim))
fprintf(stderr, "Wrong results for matrix multiply\n");
else
printf("Matrix multiply was successful\n");
// Free memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFree(d_matrixSize);
free(A);
free(B);
free(C);
} | .file "tmpxft_0010d023_00000000-6_matrixMultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21MatrixMulHostValidatePfS_S_i
.type _Z21MatrixMulHostValidatePfS_S_i, @function
_Z21MatrixMulHostValidatePfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L10
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r10
movl %ecx, %ebp
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movq %rdi, %r11
leaq (%rdi,%r8), %rsi
movl $0, %r12d
.L5:
movq %rbx, %r9
movl $0, %edi
jmp .L9
.L19:
ucomiss (%r10,%rdi,4), %xmm1
jp .L11
jne .L11
addq $1, %rdi
addq $4, %r9
cmpq %rcx, %rdi
je .L8
.L9:
movq %r9, %rdx
movq %r11, %rax
pxor %xmm1, %xmm1
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %r8, %rdx
cmpq %rsi, %rax
jne .L6
jmp .L19
.L8:
addl $1, %r12d
addq %r8, %r10
addq %r8, %r11
addq %r8, %rsi
cmpl %r12d, %ebp
jne .L5
movl $1, %eax
jmp .L3
.L10:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
movl $1, %eax
ret
.L11:
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
.cfi_offset 6, -24
.cfi_offset 12, -16
movl $0, %eax
.L3:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z21MatrixMulHostValidatePfS_S_i, .-_Z21MatrixMulHostValidatePfS_S_i
.globl _Z10initMatrixPfi
.type _Z10initMatrixPfi, @function
_Z10initMatrixPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L20
movslq %esi, %rdx
leaq 0(,%rdx,4), %r8
movl $0, %ecx
pxor %xmm2, %xmm2
cvtsi2ssl %esi, %xmm2
.L22:
movl $0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
.L23:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm1, %xmm0
divss %xmm2, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L23
addl $1, %ecx
addq %r8, %rdi
cmpl %ecx, %esi
jne .L22
.L20:
ret
.cfi_endproc
.LFE2058:
.size _Z10initMatrixPfi, .-_Z10initMatrixPfi
.globl _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi
.type _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi, @function
_Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulDevicePfS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi, .-_Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi
.globl _Z15MatrixMulDevicePfS_S_Pi
.type _Z15MatrixMulDevicePfS_S_Pi, @function
_Z15MatrixMulDevicePfS_S_Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15MatrixMulDevicePfS_S_Pi, .-_Z15MatrixMulDevicePfS_S_Pi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Wrong results for matrix multiply\n"
.align 8
.LC2:
.string "Matrix multiply was successful\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $512, 12(%rsp)
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %edi
call malloc@PLT
movq %rax, %r12
movl $512, %esi
movq %rbp, %rdi
call _Z10initMatrixPfi
movl $512, %esi
movq %rbx, %rdi
call _Z10initMatrixPfi
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L34:
movl $2, %ecx
movl $1048576, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z21MatrixMulHostValidatePfS_S_i
testl %eax, %eax
jne .L35
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
.L36:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi
jmp .L34
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z15MatrixMulDevicePfS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulDevicePfS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Matrix Multiply
#include<stdio.h>
// perform MatrixMul on Device
__global__ void MatrixMulDevice( float *A, float *B, float *C, int *matrixSize)
{
int chunk = (*matrixSize) / gridDim.x;
int sum, i, k;
for(i = blockIdx.x * chunk; i < blockIdx.x * chunk + chunk - 1; i++) {
sum = 0;
for(k = 0; k < *matrixSize; k++) {
sum += A[i * *matrixSize + k] * B [k * *matrixSize + threadIdx.x];
}
C[i * *matrixSize + threadIdx.x] = sum;
}
}
int MatrixMulHostValidate(float *A, float *B, float *C, int dim)
{
float a, b, sum;
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
sum = 0;
for (int k = 0; k < dim; k++) {
a = A[ i* dim + k ];
b = B[ k * dim + j ];
sum += a * b;
}
if (C[ i* dim + j ] != sum)
return 0;
}
}
return 1;
}
void initMatrix(float *A, int dim) {
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
A[i* dim + j] = ((float)i + j) / dim;
}
}
}
int main(void) {
float *A, *B, *C;
int dim = 512;
float *d_A, *d_B, *d_C;
int *d_matrixSize;
// Allocate memory for the matrices.
A = (float *) malloc(sizeof(float) * dim * dim);
B = (float *) malloc(sizeof(float) * dim * dim);
C = (float *) malloc(sizeof(float) * dim * dim);
// I/O to load A, B and C.
initMatrix(A, dim);
initMatrix(B, dim);
// define thread hierarchy
int nblocks= 4;
int tpb= 512;
// allocate device memory
size_t memSize;
memSize= dim * dim * sizeof(float);
cudaMalloc( (void**) &d_A, memSize);
cudaMalloc( (void**) &d_B, memSize);
cudaMalloc( (void**) &d_C, memSize);
cudaMalloc( (void**) &d_matrixSize, sizeof(float));
// initialize device memory
cudaMemcpy(d_A, A, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_matrixSize, &dim, sizeof(float), cudaMemcpyHostToDevice);
// launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
// perform MatrixMulon Device
MatrixMulDevice<<< dimGrid, dimBlock>>>(d_A, d_B, d_C, d_matrixSize);
// retrieve results
cudaMemcpy(C, d_C, memSize, cudaMemcpyDeviceToHost);
// verfiy results
if(!MatrixMulHostValidate(A, B, C, dim))
fprintf(stderr, "Wrong results for matrix multiply\n");
else
printf("Matrix multiply was successful\n");
// Free memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFree(d_matrixSize);
free(A);
free(B);
free(C);
} | // Matrix Multiply
#include <hip/hip_runtime.h>
#include<stdio.h>
// perform MatrixMul on Device
__global__ void MatrixMulDevice( float *A, float *B, float *C, int *matrixSize)
{
int chunk = (*matrixSize) / gridDim.x;
int sum, i, k;
for(i = blockIdx.x * chunk; i < blockIdx.x * chunk + chunk - 1; i++) {
sum = 0;
for(k = 0; k < *matrixSize; k++) {
sum += A[i * *matrixSize + k] * B [k * *matrixSize + threadIdx.x];
}
C[i * *matrixSize + threadIdx.x] = sum;
}
}
int MatrixMulHostValidate(float *A, float *B, float *C, int dim)
{
float a, b, sum;
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
sum = 0;
for (int k = 0; k < dim; k++) {
a = A[ i* dim + k ];
b = B[ k * dim + j ];
sum += a * b;
}
if (C[ i* dim + j ] != sum)
return 0;
}
}
return 1;
}
void initMatrix(float *A, int dim) {
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
A[i* dim + j] = ((float)i + j) / dim;
}
}
}
int main(void) {
float *A, *B, *C;
int dim = 512;
float *d_A, *d_B, *d_C;
int *d_matrixSize;
// Allocate memory for the matrices.
A = (float *) malloc(sizeof(float) * dim * dim);
B = (float *) malloc(sizeof(float) * dim * dim);
C = (float *) malloc(sizeof(float) * dim * dim);
// I/O to load A, B and C.
initMatrix(A, dim);
initMatrix(B, dim);
// define thread hierarchy
int nblocks= 4;
int tpb= 512;
// allocate device memory
size_t memSize;
memSize= dim * dim * sizeof(float);
hipMalloc( (void**) &d_A, memSize);
hipMalloc( (void**) &d_B, memSize);
hipMalloc( (void**) &d_C, memSize);
hipMalloc( (void**) &d_matrixSize, sizeof(float));
// initialize device memory
hipMemcpy(d_A, A, memSize, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, memSize, hipMemcpyHostToDevice);
hipMemcpy(d_matrixSize, &dim, sizeof(float), hipMemcpyHostToDevice);
// launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
// perform MatrixMulon Device
MatrixMulDevice<<< dimGrid, dimBlock>>>(d_A, d_B, d_C, d_matrixSize);
// retrieve results
hipMemcpy(C, d_C, memSize, hipMemcpyDeviceToHost);
// verfiy results
if(!MatrixMulHostValidate(A, B, C, dim))
fprintf(stderr, "Wrong results for matrix multiply\n");
else
printf("Matrix multiply was successful\n");
// Free memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipFree(d_matrixSize);
free(A);
free(B);
free(C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Matrix Multiply
#include <hip/hip_runtime.h>
#include<stdio.h>
// perform MatrixMul on Device
__global__ void MatrixMulDevice( float *A, float *B, float *C, int *matrixSize)
{
int chunk = (*matrixSize) / gridDim.x;
int sum, i, k;
for(i = blockIdx.x * chunk; i < blockIdx.x * chunk + chunk - 1; i++) {
sum = 0;
for(k = 0; k < *matrixSize; k++) {
sum += A[i * *matrixSize + k] * B [k * *matrixSize + threadIdx.x];
}
C[i * *matrixSize + threadIdx.x] = sum;
}
}
int MatrixMulHostValidate(float *A, float *B, float *C, int dim)
{
float a, b, sum;
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
sum = 0;
for (int k = 0; k < dim; k++) {
a = A[ i* dim + k ];
b = B[ k * dim + j ];
sum += a * b;
}
if (C[ i* dim + j ] != sum)
return 0;
}
}
return 1;
}
void initMatrix(float *A, int dim) {
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
A[i* dim + j] = ((float)i + j) / dim;
}
}
}
int main(void) {
float *A, *B, *C;
int dim = 512;
float *d_A, *d_B, *d_C;
int *d_matrixSize;
// Allocate memory for the matrices.
A = (float *) malloc(sizeof(float) * dim * dim);
B = (float *) malloc(sizeof(float) * dim * dim);
C = (float *) malloc(sizeof(float) * dim * dim);
// I/O to load A, B and C.
initMatrix(A, dim);
initMatrix(B, dim);
// define thread hierarchy
int nblocks= 4;
int tpb= 512;
// allocate device memory
size_t memSize;
memSize= dim * dim * sizeof(float);
hipMalloc( (void**) &d_A, memSize);
hipMalloc( (void**) &d_B, memSize);
hipMalloc( (void**) &d_C, memSize);
hipMalloc( (void**) &d_matrixSize, sizeof(float));
// initialize device memory
hipMemcpy(d_A, A, memSize, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, memSize, hipMemcpyHostToDevice);
hipMemcpy(d_matrixSize, &dim, sizeof(float), hipMemcpyHostToDevice);
// launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
// perform MatrixMulon Device
MatrixMulDevice<<< dimGrid, dimBlock>>>(d_A, d_B, d_C, d_matrixSize);
// retrieve results
hipMemcpy(C, d_C, memSize, hipMemcpyDeviceToHost);
// verfiy results
if(!MatrixMulHostValidate(A, B, C, dim))
fprintf(stderr, "Wrong results for matrix multiply\n");
else
printf("Matrix multiply was successful\n");
// Free memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipFree(d_matrixSize);
free(A);
free(B);
free(C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulDevicePfS_S_Pi
.globl _Z15MatrixMulDevicePfS_S_Pi
.p2align 8
.type _Z15MatrixMulDevicePfS_S_Pi,@function
_Z15MatrixMulDevicePfS_S_Pi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s4
s_load_b32 s12, s[2:3], 0x0
s_sub_i32 s3, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_waitcnt lgkmcnt(0)
s_mul_hi_u32 s2, s12, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s2, s4
s_add_i32 s5, s2, 1
s_sub_i32 s3, s12, s3
s_sub_i32 s6, s3, s4
s_cmp_ge_u32 s3, s4
s_cselect_b32 s2, s5, s2
s_cselect_b32 s3, s6, s3
s_add_i32 s5, s2, 1
s_cmp_ge_u32 s3, s4
s_cselect_b32 s8, s5, s2
s_add_i32 s2, s15, 1
s_mul_i32 s13, s8, s15
s_mul_i32 s14, s8, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s14, s14, -1
s_cmp_ge_u32 s13, s14
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_cmp_gt_i32 s12, 0
v_mov_b32_e32 v2, 0
s_cselect_b32 s0, -1, 0
s_mul_i32 s1, s8, s15
v_cndmask_b32_e64 v1, 0, 1, s0
s_mul_i32 s8, s1, s12
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_mad_u64_u32 v[4:5], null, s13, s12, v[0:1]
v_mov_b32_e32 v5, v2
v_cvt_f32_i32_e32 v1, v3
s_add_i32 s13, s13, 1
s_add_i32 s8, s8, s12
s_cmp_lt_u32 s13, s14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
global_store_b32 v[3:4], v1, off
s_cbranch_scc0 .LBB0_6
.LBB0_3:
v_mov_b32_e32 v3, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
s_ashr_i32 s9, s8, 31
v_mov_b32_e32 v3, 0
s_lshl_b64 s[10:11], s[8:9], 2
v_mov_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_mov_b32 s1, s12
.p2align 6
.LBB0_5:
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v3, v3
s_add_i32 s1, s1, -1
v_add_nc_u32_e32 v1, s12, v1
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v6, v2, s[10:11]
global_load_b32 v4, v[4:5], off
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s1, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v6, v4
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v3, v3
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulDevicePfS_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulDevicePfS_S_Pi, .Lfunc_end0-_Z15MatrixMulDevicePfS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulDevicePfS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulDevicePfS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Matrix Multiply
#include <hip/hip_runtime.h>
#include<stdio.h>
// perform MatrixMul on Device
__global__ void MatrixMulDevice( float *A, float *B, float *C, int *matrixSize)
{
int chunk = (*matrixSize) / gridDim.x;
int sum, i, k;
for(i = blockIdx.x * chunk; i < blockIdx.x * chunk + chunk - 1; i++) {
sum = 0;
for(k = 0; k < *matrixSize; k++) {
sum += A[i * *matrixSize + k] * B [k * *matrixSize + threadIdx.x];
}
C[i * *matrixSize + threadIdx.x] = sum;
}
}
int MatrixMulHostValidate(float *A, float *B, float *C, int dim)
{
float a, b, sum;
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
sum = 0;
for (int k = 0; k < dim; k++) {
a = A[ i* dim + k ];
b = B[ k * dim + j ];
sum += a * b;
}
if (C[ i* dim + j ] != sum)
return 0;
}
}
return 1;
}
void initMatrix(float *A, int dim) {
for (int i= 0; i< dim; i++)
{
for (int j = 0; j < dim; j++)
{
A[i* dim + j] = ((float)i + j) / dim;
}
}
}
int main(void) {
float *A, *B, *C;
int dim = 512;
float *d_A, *d_B, *d_C;
int *d_matrixSize;
// Allocate memory for the matrices.
A = (float *) malloc(sizeof(float) * dim * dim);
B = (float *) malloc(sizeof(float) * dim * dim);
C = (float *) malloc(sizeof(float) * dim * dim);
// I/O to load A, B and C.
initMatrix(A, dim);
initMatrix(B, dim);
// define thread hierarchy
int nblocks= 4;
int tpb= 512;
// allocate device memory
size_t memSize;
memSize= dim * dim * sizeof(float);
hipMalloc( (void**) &d_A, memSize);
hipMalloc( (void**) &d_B, memSize);
hipMalloc( (void**) &d_C, memSize);
hipMalloc( (void**) &d_matrixSize, sizeof(float));
// initialize device memory
hipMemcpy(d_A, A, memSize, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, memSize, hipMemcpyHostToDevice);
hipMemcpy(d_matrixSize, &dim, sizeof(float), hipMemcpyHostToDevice);
// launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
// perform MatrixMulon Device
MatrixMulDevice<<< dimGrid, dimBlock>>>(d_A, d_B, d_C, d_matrixSize);
// retrieve results
hipMemcpy(C, d_C, memSize, hipMemcpyDeviceToHost);
// verfiy results
if(!MatrixMulHostValidate(A, B, C, dim))
fprintf(stderr, "Wrong results for matrix multiply\n");
else
printf("Matrix multiply was successful\n");
// Free memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipFree(d_matrixSize);
free(A);
free(B);
free(C);
} | .text
.file "matrixMultiply.hip"
.globl _Z30__device_stub__MatrixMulDevicePfS_S_Pi # -- Begin function _Z30__device_stub__MatrixMulDevicePfS_S_Pi
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulDevicePfS_S_Pi,@function
_Z30__device_stub__MatrixMulDevicePfS_S_Pi: # @_Z30__device_stub__MatrixMulDevicePfS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulDevicePfS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulDevicePfS_S_Pi, .Lfunc_end0-_Z30__device_stub__MatrixMulDevicePfS_S_Pi
.cfi_endproc
# -- End function
.globl _Z21MatrixMulHostValidatePfS_S_i # -- Begin function _Z21MatrixMulHostValidatePfS_S_i
.p2align 4, 0x90
.type _Z21MatrixMulHostValidatePfS_S_i,@function
_Z21MatrixMulHostValidatePfS_S_i: # @_Z21MatrixMulHostValidatePfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
setle %al
jle .LBB1_10
# %bb.1: # %.preheader36.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ecx
leaq (,%rcx,4), %r8
xorl %r9d, %r9d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_2 Depth=1
testb $1, %bpl
jne .LBB1_9
.LBB1_8: # %.critedge
# in Loop: Header=BB1_2 Depth=1
incq %r9
cmpq %rcx, %r9
setae %al
addq %r8, %rdi
cmpq %rcx, %r9
je .LBB1_9
.LBB1_2: # %.preheader36
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_5 Depth 3
movq %r9, %r10
imulq %rcx, %r10
leaq (%rdx,%r10,4), %r10
movb $1, %bpl
movq %rsi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_5 Depth 3
xorps %xmm0, %xmm0
movq %r11, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14), %xmm1
addss %xmm1, %xmm0
incq %r15
addq %r8, %r14
cmpq %r15, %rcx
jne .LBB1_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
movss (%r10,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB1_7
jp .LBB1_7
# %bb.3: # in Loop: Header=BB1_4 Depth=2
incq %rbx
cmpq %rcx, %rbx
setb %bpl
addq $4, %r11
cmpq %rcx, %rbx
jne .LBB1_4
jmp .LBB1_8
.LBB1_9:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_10: # %._crit_edge47
movzbl %al, %eax
andl $1, %eax
retq
.Lfunc_end1:
.size _Z21MatrixMulHostValidatePfS_S_i, .Lfunc_end1-_Z21MatrixMulHostValidatePfS_S_i
.cfi_endproc
# -- End function
.globl _Z10initMatrixPfi # -- Begin function _Z10initMatrixPfi
.p2align 4, 0x90
.type _Z10initMatrixPfi,@function
_Z10initMatrixPfi: # @_Z10initMatrixPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
cvtsi2ss %esi, %xmm0
movl %esi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ecx, %r8d
leaq (%rdi,%r8,4), %r8
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2ss %r9d, %xmm2
addss %xmm1, %xmm2
divss %xmm0, %xmm2
movss %xmm2, (%r8,%r9,4)
incq %r9
cmpq %r9, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addl %esi, %ecx
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge16
retq
.Lfunc_end2:
.size _Z10initMatrixPfi, .Lfunc_end2-_Z10initMatrixPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3b000000 # float 0.001953125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader.lr.ph.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, 12(%rsp) # imm = 0x200
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rcx
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
addss %xmm1, %xmm2
mulss %xmm0, %xmm2
movss %xmm2, (%rcx,%rdx,4)
incq %rdx
cmpq $512, %rdx # imm = 0x200
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %rax
addq $2048, %rcx # imm = 0x800
cmpq $512, %rax # imm = 0x200
jne .LBB3_1
# %bb.4: # %.preheader.i28.preheader
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB3_5: # %.preheader.i28
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
addss %xmm1, %xmm2
mulss %xmm0, %xmm2
movss %xmm2, (%rcx,%rdx,4)
incq %rdx
cmpq $512, %rdx # imm = 0x200
jne .LBB3_6
# %bb.7: # %._crit_edge.i34
# in Loop: Header=BB3_5 Depth=1
incq %rax
addq $2048, %rcx # imm = 0x800
cmpq $512, %rax # imm = 0x200
jne .LBB3_5
# %bb.8: # %_Z10initMatrixPfi.exit37
leaq 40(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 40(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 508(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15MatrixMulDevicePfS_S_Pi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 24(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
testl %eax, %eax
setle %dil
jle .LBB3_19
# %bb.11: # %.preheader36.lr.ph.i
leaq (,%rax,4), %rcx
xorl %edx, %edx
movq %rbx, %rsi
xorl %edi, %edi
jmp .LBB3_12
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_12 Depth=1
testb $1, %r11b
jne .LBB3_19
.LBB3_18: # %.critedge.i
# in Loop: Header=BB3_12 Depth=1
incq %rdx
addq %rcx, %rsi
cmpq %rax, %rdx
setae %dil
je .LBB3_19
.LBB3_12: # %.preheader36.i
# =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
# Child Loop BB3_15 Depth 3
movq %rdx, %r8
imulq %rax, %r8
leaq (%r15,%r8,4), %r8
movb $1, %r11b
movq %r14, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_14: # %.preheader.i38
# Parent Loop BB3_12 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_15 Depth 3
xorps %xmm0, %xmm0
movq %r9, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_15: # Parent Loop BB3_12 Depth=1
# Parent Loop BB3_14 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r13), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
addq $4, %r13
addq %rcx, %r12
cmpq %r13, %rcx
jne .LBB3_15
# %bb.16: # %._crit_edge.i43
# in Loop: Header=BB3_14 Depth=2
movss (%r8,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB3_17
jp .LBB3_17
# %bb.13: # in Loop: Header=BB3_14 Depth=2
incq %r10
addq $4, %r9
cmpq %rax, %r10
setb %r11b
jne .LBB3_14
jmp .LBB3_18
.LBB3_19: # %_Z21MatrixMulHostValidatePfS_S_i.exit
testb $1, %dil
je .LBB3_20
# %bb.21:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_22:
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_20:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $34, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB3_22
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulDevicePfS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulDevicePfS_S_Pi,@object # @_Z15MatrixMulDevicePfS_S_Pi
.section .rodata,"a",@progbits
.globl _Z15MatrixMulDevicePfS_S_Pi
.p2align 3, 0x0
_Z15MatrixMulDevicePfS_S_Pi:
.quad _Z30__device_stub__MatrixMulDevicePfS_S_Pi
.size _Z15MatrixMulDevicePfS_S_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Wrong results for matrix multiply\n"
.size .L.str, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulDevicePfS_S_Pi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matrix multiply was successful"
.size .Lstr, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulDevicePfS_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulDevicePfS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulDevicePfS_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*0050*/ I2F.U32.RP R6, c[0x0][0xc] ; /* 0x0000030000067b06 */
/* 0x000e220000209000 */
/*0060*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fce0003f45070 */
/*0070*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*00c0*/ IMAD R7, R7, c[0x0][0xc], RZ ; /* 0x0000030007077a24 */
/* 0x000fca00078e02ff */
/*00d0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe400078e0004 */
/*00e0*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*00f0*/ IMAD.HI.U32 R5, R5, R0, RZ ; /* 0x0000000005057227 */
/* 0x004fc800078e00ff */
/*0100*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a05 */
/*0110*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0xc], PT ; /* 0x0000030000007a0c */
/* 0x000fda0003f06070 */
/*0130*/ @P0 IADD3 R0, R0, -c[0x0][0xc], RZ ; /* 0x8000030000000a10 */
/* 0x000fe40007ffe0ff */
/*0140*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0xc], PT ; /* 0x0000030000007a0c */
/* 0x000fda0003f26070 */
/*0160*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0170*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0xc], RZ, 0x33, !PT ; /* 0x00000300ff05aa12 */
/* 0x000fca00078e33ff */
/*0180*/ IMAD R15, R5, R4, RZ ; /* 0x00000004050f7224 */
/* 0x001fca00078e02ff */
/*0190*/ IADD3 R0, R5, -0x1, R15 ; /* 0xffffffff05007810 */
/* 0x000fc80007ffe00f */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R15, R0, PT ; /* 0x000000000f00720c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01c0*/ S2R R14, SR_TID.X ; /* 0x00000000000e7919 */
/* 0x000e240000002100 */
/*01d0*/ LDG.E R17, [R2.64] ; /* 0x0000000602117981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ ISETP.GT.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x004fda0003f04270 */
/*01f0*/ @!P0 MOV R21, RZ ; /* 0x000000ff00158202 */
/* 0x001fe20000000f00 */
/*0200*/ @!P0 BRA 0x6f0 ; /* 0x000004e000008947 */
/* 0x000fea0003800000 */
/*0210*/ IADD3 R4, R17.reuse, -0x1, RZ ; /* 0xffffffff11047810 */
/* 0x040fe20007ffe0ff */
/*0220*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0230*/ LOP3.LUT R16, R17.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000311107812 */
/* 0x040fe200078ec0ff */
/*0240*/ IMAD R18, R17, R15, RZ ; /* 0x0000000f11127224 */
/* 0x000fe200078e02ff */
/*0250*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0260*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f05270 */
/*0280*/ @!P1 BRA 0x530 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0290*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*02a0*/ IMAD.IADD R22, R17.reuse, 0x1, R14.reuse ; /* 0x0000000111167824 */
/* 0x141fe200078e020e */
/*02b0*/ LEA R20, R17.reuse, R14.reuse, 0x1 ; /* 0x0000000e11147211 */
/* 0x0c0fe200078e08ff */
/*02c0*/ IMAD R24, R17, 0x3, R14 ; /* 0x0000000311187824 */
/* 0x000fe200078e020e */
/*02d0*/ MOV R26, R14 ; /* 0x0000000e001a7202 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.IADD R27, R16, 0x1, -R17 ; /* 0x00000001101b7824 */
/* 0x000fe200078e0a11 */
/*02f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc80008000000 */
/*0300*/ IMAD.WIDE R4, R18, R19, c[0x0][0x160] ; /* 0x0000580012047625 */
/* 0x000fc800078e0213 */
/*0310*/ IMAD.WIDE.U32 R6, R26, R19.reuse, c[0x0][0x168] ; /* 0x00005a001a067625 */
/* 0x080fe200078e0013 */
/*0320*/ LDG.E R23, [R4.64] ; /* 0x0000000604177981 */
/* 0x0010a6000c1e1900 */
/*0330*/ IMAD.WIDE.U32 R8, R22, R19.reuse, c[0x0][0x168] ; /* 0x00005a0016087625 */
/* 0x080fe200078e0013 */
/*0340*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040604197981 */
/* 0x0000e8000c1e1900 */
/*0350*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee2000c1e1900 */
/*0370*/ IMAD.WIDE.U32 R10, R20, R19, c[0x0][0x168] ; /* 0x00005a00140a7625 */
/* 0x000fc600078e0013 */
/*0380*/ LDG.E R29, [R4.64+0x8] ; /* 0x00000806041d7981 */
/* 0x000128000c1e1900 */
/*0390*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f22000c1e1900 */
/*03a0*/ IMAD.WIDE.U32 R12, R24, R19, c[0x0][0x168] ; /* 0x00005a00180c7625 */
/* 0x000fc600078e0013 */
/*03b0*/ LDG.E R28, [R4.64+0xc] ; /* 0x00000c06041c7981 */
/* 0x000168000c1e1900 */
/*03c0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f62000c1e1900 */
/*03d0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002ea20000201400 */
/*03e0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*03f0*/ IADD3 R4, P2, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x001fe20007f5e0ff */
/*0400*/ IMAD R24, R17.reuse, 0x4, R24 ; /* 0x0000000411187824 */
/* 0x040fe200078e0218 */
/*0410*/ LEA R22, R17.reuse, R22, 0x2 ; /* 0x0000001611167211 */
/* 0x040fe400078e10ff */
/*0420*/ LEA R20, R17.reuse, R20, 0x2 ; /* 0x0000001411147211 */
/* 0x040fe200078e10ff */
/*0430*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0440*/ LEA R26, R17, R26, 0x2 ; /* 0x0000001a111a7211 */
/* 0x000fe200078e10ff */
/*0450*/ FFMA R6, R6, R23, R21 ; /* 0x0000001706067223 */
/* 0x004fcc0000000015 */
/*0460*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*0470*/ I2F R7, R6 ; /* 0x0000000600077306 */
/* 0x001ee40000201400 */
/*0480*/ FFMA R7, R8, R25, R7 ; /* 0x0000001908077223 */
/* 0x008fcc0000000007 */
/*0490*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*04a0*/ I2F R8, R7 ; /* 0x0000000700087306 */
/* 0x001f240000201400 */
/*04b0*/ FFMA R8, R10, R29, R8 ; /* 0x0000001d0a087223 */
/* 0x010fcc0000000008 */
/*04c0*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e22000020f100 */
/*04d0*/ IADD3 R10, R27, UR4, RZ ; /* 0x000000041b0a7c10 */
/* 0x000fce000fffe0ff */
/*04e0*/ I2F R9, R8 ; /* 0x0000000800097306 */
/* 0x001f620000201400 */
/*04f0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0500*/ FFMA R9, R12, R28, R9 ; /* 0x0000001c0c097223 */
/* 0x020fcc0000000009 */
/*0510*/ F2I.TRUNC.NTZ R21, R9 ; /* 0x0000000900157305 */
/* 0x00006c000020f100 */
/*0520*/ @P1 BRA 0x310 ; /* 0xfffffde000001947 */
/* 0x000fea000383ffff */
/*0530*/ @!P0 BRA 0x6f0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0540*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0550*/ IADD3 R4, R18, UR4, RZ ; /* 0x0000000412047c10 */
/* 0x000fe2000fffe0ff */
/*0560*/ IMAD R8, R17, UR4, R14 ; /* 0x0000000411087c24 */
/* 0x001fd0000f8e020e */
/*0570*/ IMAD.WIDE.U32 R6, R8, R13, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fc800078e000d */
/*0580*/ IMAD.WIDE R4, R4, R13, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e020d */
/*0590*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002ea20000201400 */
/*05c0*/ ISETP.NE.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe20003f05270 */
/*05d0*/ FFMA R9, R6, R9, R21 ; /* 0x0000000906097223 */
/* 0x004fcc0000000015 */
/*05e0*/ F2I.TRUNC.NTZ R21, R9 ; /* 0x0000000900157305 */
/* 0x00006c000020f100 */
/*05f0*/ @!P0 BRA 0x6f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0600*/ IMAD.IADD R8, R17, 0x1, R8 ; /* 0x0000000111087824 */
/* 0x000fe200078e0208 */
/*0610*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x000ea6000c1e1900 */
/*0620*/ IMAD.WIDE.U32 R6, R8, R13, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fcc00078e000d */
/*0630*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1900 */
/*0640*/ ISETP.NE.AND P0, PT, R16, 0x2, PT ; /* 0x000000021000780c */
/* 0x000fda0003f05270 */
/*0650*/ @P0 IADD3 R8, R17, R8, RZ ; /* 0x0000000811080210 */
/* 0x000fca0007ffe0ff */
/*0660*/ @P0 IMAD.WIDE.U32 R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008080625 */
/* 0x001fe400078e000d */
/*0670*/ @P0 LDG.E R13, [R4.64+0x8] ; /* 0x00000806040d0981 */
/* 0x000ee8000c1e1900 */
/*0680*/ @P0 LDG.E R8, [R8.64] ; /* 0x0000000608080981 */
/* 0x000ee2000c1e1900 */
/*0690*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002ea40000201400 */
/*06a0*/ FFMA R11, R6, R11, R21 ; /* 0x0000000b060b7223 */
/* 0x004fcc0000000015 */
/*06b0*/ F2I.TRUNC.NTZ R21, R11 ; /* 0x0000000b00157305 */
/* 0x000e30000020f100 */
/*06c0*/ @P0 I2F R10, R21 ; /* 0x00000015000a0306 */
/* 0x001ee40000201400 */
/*06d0*/ @P0 FFMA R13, R8, R13, R10 ; /* 0x0000000d080d0223 */
/* 0x008fcc000000000a */
/*06e0*/ @P0 F2I.TRUNC.NTZ R21, R13 ; /* 0x0000000d00150305 */
/* 0x000064000020f100 */
/*06f0*/ IMAD R4, R17, R15, R14 ; /* 0x0000000f11047224 */
/* 0x001fe200078e020e */
/*0700*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002e220000201400 */
/*0710*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe40007ffe0ff */
/*0720*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe40000000f00 */
/*0730*/ ISETP.GE.U32.AND P0, PT, R15, R0, PT ; /* 0x000000000f00720c */
/* 0x000fc60003f06070 */
/*0740*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0005 */
/*0750*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0011ea000c101906 */
/*0760*/ @!P0 BRA 0x1d0 ; /* 0xfffffa6000008947 */
/* 0x000fea000383ffff */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulDevicePfS_S_Pi
.globl _Z15MatrixMulDevicePfS_S_Pi
.p2align 8
.type _Z15MatrixMulDevicePfS_S_Pi,@function
_Z15MatrixMulDevicePfS_S_Pi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s4
s_load_b32 s12, s[2:3], 0x0
s_sub_i32 s3, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_waitcnt lgkmcnt(0)
s_mul_hi_u32 s2, s12, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s2, s4
s_add_i32 s5, s2, 1
s_sub_i32 s3, s12, s3
s_sub_i32 s6, s3, s4
s_cmp_ge_u32 s3, s4
s_cselect_b32 s2, s5, s2
s_cselect_b32 s3, s6, s3
s_add_i32 s5, s2, 1
s_cmp_ge_u32 s3, s4
s_cselect_b32 s8, s5, s2
s_add_i32 s2, s15, 1
s_mul_i32 s13, s8, s15
s_mul_i32 s14, s8, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s14, s14, -1
s_cmp_ge_u32 s13, s14
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_cmp_gt_i32 s12, 0
v_mov_b32_e32 v2, 0
s_cselect_b32 s0, -1, 0
s_mul_i32 s1, s8, s15
v_cndmask_b32_e64 v1, 0, 1, s0
s_mul_i32 s8, s1, s12
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_mad_u64_u32 v[4:5], null, s13, s12, v[0:1]
v_mov_b32_e32 v5, v2
v_cvt_f32_i32_e32 v1, v3
s_add_i32 s13, s13, 1
s_add_i32 s8, s8, s12
s_cmp_lt_u32 s13, s14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
global_store_b32 v[3:4], v1, off
s_cbranch_scc0 .LBB0_6
.LBB0_3:
v_mov_b32_e32 v3, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
s_ashr_i32 s9, s8, 31
v_mov_b32_e32 v3, 0
s_lshl_b64 s[10:11], s[8:9], 2
v_mov_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_mov_b32 s1, s12
.p2align 6
.LBB0_5:
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v3, v3
s_add_i32 s1, s1, -1
v_add_nc_u32_e32 v1, s12, v1
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v6, v2, s[10:11]
global_load_b32 v4, v[4:5], off
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s1, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v6, v4
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v3, v3
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulDevicePfS_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulDevicePfS_S_Pi, .Lfunc_end0-_Z15MatrixMulDevicePfS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulDevicePfS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulDevicePfS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010d023_00000000-6_matrixMultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21MatrixMulHostValidatePfS_S_i
.type _Z21MatrixMulHostValidatePfS_S_i, @function
_Z21MatrixMulHostValidatePfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L10
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r10
movl %ecx, %ebp
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movq %rdi, %r11
leaq (%rdi,%r8), %rsi
movl $0, %r12d
.L5:
movq %rbx, %r9
movl $0, %edi
jmp .L9
.L19:
ucomiss (%r10,%rdi,4), %xmm1
jp .L11
jne .L11
addq $1, %rdi
addq $4, %r9
cmpq %rcx, %rdi
je .L8
.L9:
movq %r9, %rdx
movq %r11, %rax
pxor %xmm1, %xmm1
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %r8, %rdx
cmpq %rsi, %rax
jne .L6
jmp .L19
.L8:
addl $1, %r12d
addq %r8, %r10
addq %r8, %r11
addq %r8, %rsi
cmpl %r12d, %ebp
jne .L5
movl $1, %eax
jmp .L3
.L10:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
movl $1, %eax
ret
.L11:
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
.cfi_offset 6, -24
.cfi_offset 12, -16
movl $0, %eax
.L3:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z21MatrixMulHostValidatePfS_S_i, .-_Z21MatrixMulHostValidatePfS_S_i
.globl _Z10initMatrixPfi
.type _Z10initMatrixPfi, @function
_Z10initMatrixPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L20
movslq %esi, %rdx
leaq 0(,%rdx,4), %r8
movl $0, %ecx
pxor %xmm2, %xmm2
cvtsi2ssl %esi, %xmm2
.L22:
movl $0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
.L23:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm1, %xmm0
divss %xmm2, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L23
addl $1, %ecx
addq %r8, %rdi
cmpl %ecx, %esi
jne .L22
.L20:
ret
.cfi_endproc
.LFE2058:
.size _Z10initMatrixPfi, .-_Z10initMatrixPfi
.globl _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi
.type _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi, @function
_Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulDevicePfS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi, .-_Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi
.globl _Z15MatrixMulDevicePfS_S_Pi
.type _Z15MatrixMulDevicePfS_S_Pi, @function
_Z15MatrixMulDevicePfS_S_Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15MatrixMulDevicePfS_S_Pi, .-_Z15MatrixMulDevicePfS_S_Pi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Wrong results for matrix multiply\n"
.align 8
.LC2:
.string "Matrix multiply was successful\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $512, 12(%rsp)
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %edi
call malloc@PLT
movq %rax, %r12
movl $512, %esi
movq %rbp, %rdi
call _Z10initMatrixPfi
movl $512, %esi
movq %rbx, %rdi
call _Z10initMatrixPfi
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L34:
movl $2, %ecx
movl $1048576, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z21MatrixMulHostValidatePfS_S_i
testl %eax, %eax
jne .L35
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
.L36:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z41__device_stub__Z15MatrixMulDevicePfS_S_PiPfS_S_Pi
jmp .L34
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z15MatrixMulDevicePfS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulDevicePfS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiply.hip"
.globl _Z30__device_stub__MatrixMulDevicePfS_S_Pi # -- Begin function _Z30__device_stub__MatrixMulDevicePfS_S_Pi
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulDevicePfS_S_Pi,@function
_Z30__device_stub__MatrixMulDevicePfS_S_Pi: # @_Z30__device_stub__MatrixMulDevicePfS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulDevicePfS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulDevicePfS_S_Pi, .Lfunc_end0-_Z30__device_stub__MatrixMulDevicePfS_S_Pi
.cfi_endproc
# -- End function
.globl _Z21MatrixMulHostValidatePfS_S_i # -- Begin function _Z21MatrixMulHostValidatePfS_S_i
.p2align 4, 0x90
.type _Z21MatrixMulHostValidatePfS_S_i,@function
_Z21MatrixMulHostValidatePfS_S_i: # @_Z21MatrixMulHostValidatePfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
setle %al
jle .LBB1_10
# %bb.1: # %.preheader36.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ecx
leaq (,%rcx,4), %r8
xorl %r9d, %r9d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_2 Depth=1
testb $1, %bpl
jne .LBB1_9
.LBB1_8: # %.critedge
# in Loop: Header=BB1_2 Depth=1
incq %r9
cmpq %rcx, %r9
setae %al
addq %r8, %rdi
cmpq %rcx, %r9
je .LBB1_9
.LBB1_2: # %.preheader36
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_5 Depth 3
movq %r9, %r10
imulq %rcx, %r10
leaq (%rdx,%r10,4), %r10
movb $1, %bpl
movq %rsi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_5 Depth 3
xorps %xmm0, %xmm0
movq %r11, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14), %xmm1
addss %xmm1, %xmm0
incq %r15
addq %r8, %r14
cmpq %r15, %rcx
jne .LBB1_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
movss (%r10,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB1_7
jp .LBB1_7
# %bb.3: # in Loop: Header=BB1_4 Depth=2
incq %rbx
cmpq %rcx, %rbx
setb %bpl
addq $4, %r11
cmpq %rcx, %rbx
jne .LBB1_4
jmp .LBB1_8
.LBB1_9:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_10: # %._crit_edge47
movzbl %al, %eax
andl $1, %eax
retq
.Lfunc_end1:
.size _Z21MatrixMulHostValidatePfS_S_i, .Lfunc_end1-_Z21MatrixMulHostValidatePfS_S_i
.cfi_endproc
# -- End function
.globl _Z10initMatrixPfi # -- Begin function _Z10initMatrixPfi
.p2align 4, 0x90
.type _Z10initMatrixPfi,@function
_Z10initMatrixPfi: # @_Z10initMatrixPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
cvtsi2ss %esi, %xmm0
movl %esi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ecx, %r8d
leaq (%rdi,%r8,4), %r8
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2ss %r9d, %xmm2
addss %xmm1, %xmm2
divss %xmm0, %xmm2
movss %xmm2, (%r8,%r9,4)
incq %r9
cmpq %r9, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addl %esi, %ecx
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge16
retq
.Lfunc_end2:
.size _Z10initMatrixPfi, .Lfunc_end2-_Z10initMatrixPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3b000000 # float 0.001953125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader.lr.ph.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, 12(%rsp) # imm = 0x200
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rcx
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
addss %xmm1, %xmm2
mulss %xmm0, %xmm2
movss %xmm2, (%rcx,%rdx,4)
incq %rdx
cmpq $512, %rdx # imm = 0x200
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %rax
addq $2048, %rcx # imm = 0x800
cmpq $512, %rax # imm = 0x200
jne .LBB3_1
# %bb.4: # %.preheader.i28.preheader
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB3_5: # %.preheader.i28
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
addss %xmm1, %xmm2
mulss %xmm0, %xmm2
movss %xmm2, (%rcx,%rdx,4)
incq %rdx
cmpq $512, %rdx # imm = 0x200
jne .LBB3_6
# %bb.7: # %._crit_edge.i34
# in Loop: Header=BB3_5 Depth=1
incq %rax
addq $2048, %rcx # imm = 0x800
cmpq $512, %rax # imm = 0x200
jne .LBB3_5
# %bb.8: # %_Z10initMatrixPfi.exit37
leaq 40(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 40(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 508(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15MatrixMulDevicePfS_S_Pi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 24(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
testl %eax, %eax
setle %dil
jle .LBB3_19
# %bb.11: # %.preheader36.lr.ph.i
leaq (,%rax,4), %rcx
xorl %edx, %edx
movq %rbx, %rsi
xorl %edi, %edi
jmp .LBB3_12
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_12 Depth=1
testb $1, %r11b
jne .LBB3_19
.LBB3_18: # %.critedge.i
# in Loop: Header=BB3_12 Depth=1
incq %rdx
addq %rcx, %rsi
cmpq %rax, %rdx
setae %dil
je .LBB3_19
.LBB3_12: # %.preheader36.i
# =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
# Child Loop BB3_15 Depth 3
movq %rdx, %r8
imulq %rax, %r8
leaq (%r15,%r8,4), %r8
movb $1, %r11b
movq %r14, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_14: # %.preheader.i38
# Parent Loop BB3_12 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_15 Depth 3
xorps %xmm0, %xmm0
movq %r9, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_15: # Parent Loop BB3_12 Depth=1
# Parent Loop BB3_14 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r13), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
addq $4, %r13
addq %rcx, %r12
cmpq %r13, %rcx
jne .LBB3_15
# %bb.16: # %._crit_edge.i43
# in Loop: Header=BB3_14 Depth=2
movss (%r8,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB3_17
jp .LBB3_17
# %bb.13: # in Loop: Header=BB3_14 Depth=2
incq %r10
addq $4, %r9
cmpq %rax, %r10
setb %r11b
jne .LBB3_14
jmp .LBB3_18
.LBB3_19: # %_Z21MatrixMulHostValidatePfS_S_i.exit
testb $1, %dil
je .LBB3_20
# %bb.21:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_22:
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_20:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $34, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB3_22
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulDevicePfS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulDevicePfS_S_Pi,@object # @_Z15MatrixMulDevicePfS_S_Pi
.section .rodata,"a",@progbits
.globl _Z15MatrixMulDevicePfS_S_Pi
.p2align 3, 0x0
_Z15MatrixMulDevicePfS_S_Pi:
.quad _Z30__device_stub__MatrixMulDevicePfS_S_Pi
.size _Z15MatrixMulDevicePfS_S_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Wrong results for matrix multiply\n"
.size .L.str, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulDevicePfS_S_Pi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matrix multiply was successful"
.size .Lstr, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulDevicePfS_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulDevicePfS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
int main(void){
int a,b,c;
int *d_a,*d_b,*d_c;
int size = sizeof(int);
cudaMalloc((void **)&d_a,size);
cudaMalloc((void **)&d_b,size);
cudaMalloc((void **)&d_c,size);
a = 3;
b = 5;
cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
printf("Result: %d",c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
int main(void){
int a,b,c;
int *d_a,*d_b,*d_c;
int size = sizeof(int);
cudaMalloc((void **)&d_a,size);
cudaMalloc((void **)&d_b,size);
cudaMalloc((void **)&d_c,size);
a = 3;
b = 5;
cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
printf("Result: %d",c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_000cfce1_00000000-6_sample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result: %d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $3, (%rsp)
movl $5, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
int main(void){
int a,b,c;
int *d_a,*d_b,*d_c;
int size = sizeof(int);
cudaMalloc((void **)&d_a,size);
cudaMalloc((void **)&d_b,size);
cudaMalloc((void **)&d_c,size);
a = 3;
b = 5;
cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
printf("Result: %d",c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
int main(void){
int a,b,c;
int *d_a,*d_b,*d_c;
int size = sizeof(int);
hipMalloc((void **)&d_a,size);
hipMalloc((void **)&d_b,size);
hipMalloc((void **)&d_c,size);
a = 3;
b = 5;
hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
printf("Result: %d",c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
int main(void){
int a,b,c;
int *d_a,*d_b,*d_c;
int size = sizeof(int);
hipMalloc((void **)&d_a,size);
hipMalloc((void **)&d_b,size);
hipMalloc((void **)&d_c,size);
a = 3;
b = 5;
hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
printf("Result: %d",c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
int main(void){
int a,b,c;
int *d_a,*d_b,*d_c;
int size = sizeof(int);
hipMalloc((void **)&d_a,size);
hipMalloc((void **)&d_b,size);
hipMalloc((void **)&d_c,size);
a = 3;
b = 5;
hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
printf("Result: %d",c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "sample.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $3, 28(%rsp)
movl $5, 24(%rsp)
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result: %d"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cfce1_00000000-6_sample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result: %d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $3, (%rsp)
movl $5, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sample.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $3, 28(%rsp)
movl $5, 24(%rsp)
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result: %d"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define N 1<<1
#define TILE_WIDTH 1
#define RANDRANGE 5
__global__ void matrixMultKernel(float* Md, float* Nd, float* Pd, int Width) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i)
data[i] = (float)(rand() % RANDRANGE +1);
}
/////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////
int main(int argc, char** argv) {
// set seed for rand()
srand(2015);
// allocate host memory for matrices A and B
unsigned int size_A = N * N;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = N * N;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
// allocate device memory
float* d_A; float* d_B;
cudaMalloc((void**) &d_A, mem_size_A);
cudaMalloc((void**) &d_B, mem_size_B);
// copy host memory to device
cudaMemcpy(d_A, h_A, mem_size_A,
cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, mem_size_B,
cudaMemcpyHostToDevice);
// allocate host memory for the result C
unsigned int size_C = N*N ;
unsigned int mem_size_C = sizeof(float) * size_C;
float* h_C = (float*) malloc(mem_size_C);
memset(h_C,0,mem_size_C);
// allocate device memory for the result
float* d_C;
cudaMalloc((void**) &d_C, mem_size_C);
// perform the calculation
// setup execution parameters
dim3 blocks(TILE_WIDTH, TILE_WIDTH);
dim3 grid(N/ TILE_WIDTH, N/ TILE_WIDTH);
// execute the kernel
matrixMultKernel<<< grid, blocks >>>(d_A, d_B, d_C, N);
// copy result from device to host
cudaMemcpy(h_C, d_C, mem_size_C,
cudaMemcpyDeviceToHost);
//ToDo: Your Test code here......
printf("N= %d and TILE_WIDTH =%d\n", N,TILE_WIDTH);
for (int i=0; i < N*N; i++) {
printf("%20.15f : %20.15f : %20.15f \n", h_A[i], h_B[i], h_C[i] );
}
// clean up memory
free(h_A); free(h_B); free(h_C);
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
} | .file "tmpxft_0017c174_00000000-6_matrixmult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.globl _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i
.type _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i, @function
_Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16matrixMultKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i, .-_Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i
.globl _Z16matrixMultKernelPfS_S_i
.type _Z16matrixMultKernelPfS_S_i, @function
_Z16matrixMultKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16matrixMultKernelPfS_S_i, .-_Z16matrixMultKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "N= %d and TILE_WIDTH =%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "%20.15f : %20.15f : %20.15f \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2015, %edi
call srand@PLT
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %esi
movq %r13, %rdi
call _Z10randomInitPfi
movl $4, %esi
movq %r12, %rdi
call _Z10randomInitPfi
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
pxor %xmm0, %xmm0
movups %xmm0, (%rax)
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
movl $2, %ecx
movl $16, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
.L21:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 0(%rbp,%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $16, %rbx
jne .L21
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $2, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z16matrixMultKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrixMultKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define N 1<<1
#define TILE_WIDTH 1
#define RANDRANGE 5
__global__ void matrixMultKernel(float* Md, float* Nd, float* Pd, int Width) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i)
data[i] = (float)(rand() % RANDRANGE +1);
}
/////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////
int main(int argc, char** argv) {
// set seed for rand()
srand(2015);
// allocate host memory for matrices A and B
unsigned int size_A = N * N;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = N * N;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
// allocate device memory
float* d_A; float* d_B;
cudaMalloc((void**) &d_A, mem_size_A);
cudaMalloc((void**) &d_B, mem_size_B);
// copy host memory to device
cudaMemcpy(d_A, h_A, mem_size_A,
cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, mem_size_B,
cudaMemcpyHostToDevice);
// allocate host memory for the result C
unsigned int size_C = N*N ;
unsigned int mem_size_C = sizeof(float) * size_C;
float* h_C = (float*) malloc(mem_size_C);
memset(h_C,0,mem_size_C);
// allocate device memory for the result
float* d_C;
cudaMalloc((void**) &d_C, mem_size_C);
// perform the calculation
// setup execution parameters
dim3 blocks(TILE_WIDTH, TILE_WIDTH);
dim3 grid(N/ TILE_WIDTH, N/ TILE_WIDTH);
// execute the kernel
matrixMultKernel<<< grid, blocks >>>(d_A, d_B, d_C, N);
// copy result from device to host
cudaMemcpy(h_C, d_C, mem_size_C,
cudaMemcpyDeviceToHost);
//ToDo: Your Test code here......
printf("N= %d and TILE_WIDTH =%d\n", N,TILE_WIDTH);
for (int i=0; i < N*N; i++) {
printf("%20.15f : %20.15f : %20.15f \n", h_A[i], h_B[i], h_C[i] );
}
// clean up memory
free(h_A); free(h_B); free(h_C);
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define N 1<<1
#define TILE_WIDTH 1
#define RANDRANGE 5
__global__ void matrixMultKernel(float* Md, float* Nd, float* Pd, int Width) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i)
data[i] = (float)(rand() % RANDRANGE +1);
}
/////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////
int main(int argc, char** argv) {
// set seed for rand()
srand(2015);
// allocate host memory for matrices A and B
unsigned int size_A = N * N;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = N * N;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
// allocate device memory
float* d_A; float* d_B;
hipMalloc((void**) &d_A, mem_size_A);
hipMalloc((void**) &d_B, mem_size_B);
// copy host memory to device
hipMemcpy(d_A, h_A, mem_size_A,
hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, mem_size_B,
hipMemcpyHostToDevice);
// allocate host memory for the result C
unsigned int size_C = N*N ;
unsigned int mem_size_C = sizeof(float) * size_C;
float* h_C = (float*) malloc(mem_size_C);
memset(h_C,0,mem_size_C);
// allocate device memory for the result
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
// perform the calculation
// setup execution parameters
dim3 blocks(TILE_WIDTH, TILE_WIDTH);
dim3 grid(N/ TILE_WIDTH, N/ TILE_WIDTH);
// execute the kernel
matrixMultKernel<<< grid, blocks >>>(d_A, d_B, d_C, N);
// copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C,
hipMemcpyDeviceToHost);
//ToDo: Your Test code here......
printf("N= %d and TILE_WIDTH =%d\n", N,TILE_WIDTH);
for (int i=0; i < N*N; i++) {
printf("%20.15f : %20.15f : %20.15f \n", h_A[i], h_B[i], h_C[i] );
}
// clean up memory
free(h_A); free(h_B); free(h_C);
hipFree(d_A); hipFree(d_B); hipFree(d_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define N 1<<1
#define TILE_WIDTH 1
#define RANDRANGE 5
__global__ void matrixMultKernel(float* Md, float* Nd, float* Pd, int Width) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i)
data[i] = (float)(rand() % RANDRANGE +1);
}
/////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////
int main(int argc, char** argv) {
// set seed for rand()
srand(2015);
// allocate host memory for matrices A and B
unsigned int size_A = N * N;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = N * N;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
// allocate device memory
float* d_A; float* d_B;
hipMalloc((void**) &d_A, mem_size_A);
hipMalloc((void**) &d_B, mem_size_B);
// copy host memory to device
hipMemcpy(d_A, h_A, mem_size_A,
hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, mem_size_B,
hipMemcpyHostToDevice);
// allocate host memory for the result C
unsigned int size_C = N*N ;
unsigned int mem_size_C = sizeof(float) * size_C;
float* h_C = (float*) malloc(mem_size_C);
memset(h_C,0,mem_size_C);
// allocate device memory for the result
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
// perform the calculation
// setup execution parameters
dim3 blocks(TILE_WIDTH, TILE_WIDTH);
dim3 grid(N/ TILE_WIDTH, N/ TILE_WIDTH);
// execute the kernel
matrixMultKernel<<< grid, blocks >>>(d_A, d_B, d_C, N);
// copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C,
hipMemcpyDeviceToHost);
//ToDo: Your Test code here......
printf("N= %d and TILE_WIDTH =%d\n", N,TILE_WIDTH);
for (int i=0; i < N*N; i++) {
printf("%20.15f : %20.15f : %20.15f \n", h_A[i], h_B[i], h_C[i] );
}
// clean up memory
free(h_A); free(h_B); free(h_C);
hipFree(d_A); hipFree(d_B); hipFree(d_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrixMultKernelPfS_S_i
.globl _Z16matrixMultKernelPfS_S_i
.p2align 8
.type _Z16matrixMultKernelPfS_S_i,@function
_Z16matrixMultKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v4, s15, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_lshlrev_b32_e32 v6, 2, v1
v_mul_lo_u32 v3, v1, s2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, 4, v2
v_add_nc_u32_e32 v8, v6, v2
v_mad_u64_u32 v[1:2], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v9, v7, v6
v_add3_u32 v2, v0, s14, v3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s3, v1
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, s3
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[12:13], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_b32 v3, v[12:13], off
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v10
ds_store_b32 v9, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v6
ds_load_b32 v10, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v5, v3, v10
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v5, 0
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_mul_lo_u32 v1, v4, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16matrixMultKernelPfS_S_i
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16matrixMultKernelPfS_S_i, .Lfunc_end0-_Z16matrixMultKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16matrixMultKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16matrixMultKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define N 1<<1
#define TILE_WIDTH 1
#define RANDRANGE 5
__global__ void matrixMultKernel(float* Md, float* Nd, float* Pd, int Width) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {
// Collaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i)
data[i] = (float)(rand() % RANDRANGE +1);
}
/////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////
int main(int argc, char** argv) {
// set seed for rand()
srand(2015);
// allocate host memory for matrices A and B
unsigned int size_A = N * N;
unsigned int mem_size_A = sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = N * N;
unsigned int mem_size_B = sizeof(float) * size_B;
float* h_B = (float*) malloc(mem_size_B);
// initialize host memory
randomInit(h_A, size_A);
randomInit(h_B, size_B);
// allocate device memory
float* d_A; float* d_B;
hipMalloc((void**) &d_A, mem_size_A);
hipMalloc((void**) &d_B, mem_size_B);
// copy host memory to device
hipMemcpy(d_A, h_A, mem_size_A,
hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, mem_size_B,
hipMemcpyHostToDevice);
// allocate host memory for the result C
unsigned int size_C = N*N ;
unsigned int mem_size_C = sizeof(float) * size_C;
float* h_C = (float*) malloc(mem_size_C);
memset(h_C,0,mem_size_C);
// allocate device memory for the result
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
// perform the calculation
// setup execution parameters
dim3 blocks(TILE_WIDTH, TILE_WIDTH);
dim3 grid(N/ TILE_WIDTH, N/ TILE_WIDTH);
// execute the kernel
matrixMultKernel<<< grid, blocks >>>(d_A, d_B, d_C, N);
// copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C,
hipMemcpyDeviceToHost);
//ToDo: Your Test code here......
printf("N= %d and TILE_WIDTH =%d\n", N,TILE_WIDTH);
for (int i=0; i < N*N; i++) {
printf("%20.15f : %20.15f : %20.15f \n", h_A[i], h_B[i], h_C[i] );
}
// clean up memory
free(h_A); free(h_B); free(h_C);
hipFree(d_A); hipFree(d_B); hipFree(d_C);
} | .text
.file "matrixmult.hip"
.globl _Z31__device_stub__matrixMultKernelPfS_S_i # -- Begin function _Z31__device_stub__matrixMultKernelPfS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__matrixMultKernelPfS_S_i,@function
_Z31__device_stub__matrixMultKernelPfS_S_i: # @_Z31__device_stub__matrixMultKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16matrixMultKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__matrixMultKernelPfS_S_i, .Lfunc_end0-_Z31__device_stub__matrixMultKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z10randomInitPfi # -- Begin function _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10randomInitPfi, .Lfunc_end1-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2015, %edi # imm = 0x7DF
callq srand
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $4, %r15
jne .LBB2_1
# %bb.2: # %.lr.ph.i38.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i38
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $4, %r15
jne .LBB2_3
# %bb.4: # %_Z10randomInitPfi.exit42
leaq 24(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $16, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $2, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16matrixMultKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $16, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movl $.L.str, %edi
movl $2, %esi
movl $1, %edx
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r15,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.1, %edi
movb $3, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_7
# %bb.8:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrixMultKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrixMultKernelPfS_S_i,@object # @_Z16matrixMultKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z16matrixMultKernelPfS_S_i
.p2align 3, 0x0
_Z16matrixMultKernelPfS_S_i:
.quad _Z31__device_stub__matrixMultKernelPfS_S_i
.size _Z16matrixMultKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "N= %d and TILE_WIDTH =%d\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%20.15f : %20.15f : %20.15f \n"
.size .L.str.1, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16matrixMultKernelPfS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrixMultKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrixMultKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017c174_00000000-6_matrixmult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.globl _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i
.type _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i, @function
_Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16matrixMultKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i, .-_Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i
.globl _Z16matrixMultKernelPfS_S_i
.type _Z16matrixMultKernelPfS_S_i, @function
_Z16matrixMultKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16matrixMultKernelPfS_S_i, .-_Z16matrixMultKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "N= %d and TILE_WIDTH =%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "%20.15f : %20.15f : %20.15f \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2015, %edi
call srand@PLT
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %esi
movq %r13, %rdi
call _Z10randomInitPfi
movl $4, %esi
movq %r12, %rdi
call _Z10randomInitPfi
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
pxor %xmm0, %xmm0
movups %xmm0, (%rax)
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
movl $2, %ecx
movl $16, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
.L21:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 0(%rbp,%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $16, %rbx
jne .L21
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $2, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z41__device_stub__Z16matrixMultKernelPfS_S_iPfS_S_i
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z16matrixMultKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrixMultKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixmult.hip"
.globl _Z31__device_stub__matrixMultKernelPfS_S_i # -- Begin function _Z31__device_stub__matrixMultKernelPfS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__matrixMultKernelPfS_S_i,@function
_Z31__device_stub__matrixMultKernelPfS_S_i: # @_Z31__device_stub__matrixMultKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16matrixMultKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__matrixMultKernelPfS_S_i, .Lfunc_end0-_Z31__device_stub__matrixMultKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z10randomInitPfi # -- Begin function _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10randomInitPfi, .Lfunc_end1-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2015, %edi # imm = 0x7DF
callq srand
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $4, %r15
jne .LBB2_1
# %bb.2: # %.lr.ph.i38.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i38
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $4, %r15
jne .LBB2_3
# %bb.4: # %_Z10randomInitPfi.exit42
leaq 24(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $16, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $2, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16matrixMultKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $16, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movl $.L.str, %edi
movl $2, %esi
movl $1, %edx
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r15,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.1, %edi
movb $3, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_7
# %bb.8:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrixMultKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrixMultKernelPfS_S_i,@object # @_Z16matrixMultKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z16matrixMultKernelPfS_S_i
.p2align 3, 0x0
_Z16matrixMultKernelPfS_S_i:
.quad _Z31__device_stub__matrixMultKernelPfS_S_i
.size _Z16matrixMultKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "N= %d and TILE_WIDTH =%d\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%20.15f : %20.15f : %20.15f \n"
.size .L.str.1, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16matrixMultKernelPfS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrixMultKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrixMultKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | struct MyStruct {
float floatvalue;
int intvalue;
};
__device__ __host__ float sumStruct(struct MyStruct **p_structs, int N) {
float sum = 0;
for(int i = 0; i < N; i++) {
struct MyStruct *mystruct = p_structs[i];
sum += mystruct->floatvalue + float(mystruct->intvalue) * 3.5f;
}
return sum;
}
__global__ void mykernel(float *data, MyStruct *structs, int N) {
data[0] = sumStruct(&structs, N);
data[3] = sumStruct(&structs, 123);
data[4] = sumStruct(&structs, 12300);
} | .file "tmpxft_00123e65_00000000-6_phiaddressspace.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9sumStructPP8MyStructi
.type _Z9sumStructPP8MyStructi, @function
_Z9sumStructPP8MyStructi:
.LFB2027:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L6
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rcx
pxor %xmm1, %xmm1
movss .LC1(%rip), %xmm2
.L5:
movq (%rax), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rdx), %xmm0
mulss %xmm2, %xmm0
addss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $8, %rax
cmpq %rcx, %rax
jne .L5
.L3:
movaps %xmm1, %xmm0
ret
.L6:
pxor %xmm1, %xmm1
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z9sumStructPP8MyStructi, .-_Z9sumStructPP8MyStructi
.globl _Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi
.type _Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi, @function
_Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mykernelPfP8MyStructi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi, .-_Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi
.globl _Z8mykernelPfP8MyStructi
.type _Z8mykernelPfP8MyStructi, @function
_Z8mykernelPfP8MyStructi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8mykernelPfP8MyStructi, .-_Z8mykernelPfP8MyStructi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z8mykernelPfP8MyStructi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelPfP8MyStructi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1080033280
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | struct MyStruct {
float floatvalue;
int intvalue;
};
__device__ __host__ float sumStruct(struct MyStruct **p_structs, int N) {
float sum = 0;
for(int i = 0; i < N; i++) {
struct MyStruct *mystruct = p_structs[i];
sum += mystruct->floatvalue + float(mystruct->intvalue) * 3.5f;
}
return sum;
}
__global__ void mykernel(float *data, MyStruct *structs, int N) {
data[0] = sumStruct(&structs, N);
data[3] = sumStruct(&structs, 123);
data[4] = sumStruct(&structs, 12300);
} | #include <hip/hip_runtime.h>
struct MyStruct {
float floatvalue;
int intvalue;
};
__device__ __host__ float sumStruct(struct MyStruct **p_structs, int N) {
float sum = 0;
for(int i = 0; i < N; i++) {
struct MyStruct *mystruct = p_structs[i];
sum += mystruct->floatvalue + float(mystruct->intvalue) * 3.5f;
}
return sum;
}
__global__ void mykernel(float *data, MyStruct *structs, int N) {
data[0] = sumStruct(&structs, N);
data[3] = sumStruct(&structs, 123);
data[4] = sumStruct(&structs, 12300);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
struct MyStruct {
float floatvalue;
int intvalue;
};
__device__ __host__ float sumStruct(struct MyStruct **p_structs, int N) {
float sum = 0;
for(int i = 0; i < N; i++) {
struct MyStruct *mystruct = p_structs[i];
sum += mystruct->floatvalue + float(mystruct->intvalue) * 3.5f;
}
return sum;
}
__global__ void mykernel(float *data, MyStruct *structs, int N) {
data[0] = sumStruct(&structs, N);
data[3] = sumStruct(&structs, 123);
data[4] = sumStruct(&structs, 12300);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelPfP8MyStructi
.globl _Z8mykernelPfP8MyStructi
.p2align 8
.type _Z8mykernelPfP8MyStructi,@function
_Z8mykernelPfP8MyStructi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v0, s7
v_mov_b32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmamk_f32 v1, v0, 0x40600000, v1 :: v_dual_mov_b32 v0, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v0, v0, v1
s_add_i32 s4, s4, -1
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_load_b32 s4, s[2:3], 0x4
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
global_load_b32 v0, v1, s[2:3]
v_cvt_f32_i32_e32 v2, s4
s_movk_i32 s4, 0x7b
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmamk_f32 v0, v2, 0x40600000, v0
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v1, v1, v0
s_add_i32 s4, s4, -1
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_5
v_mov_b32_e32 v0, 0
global_store_b32 v0, v1, s[0:1] offset:12
global_load_b32 v1, v0, s[2:3]
s_load_b32 s2, s[2:3], 0x4
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v2, s2
s_movk_i32 s2, 0x300c
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmamk_f32 v1, v2, 0x40600000, v1
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v0, v0, v1
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_7
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1] offset:16
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelPfP8MyStructi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelPfP8MyStructi, .Lfunc_end0-_Z8mykernelPfP8MyStructi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelPfP8MyStructi
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z8mykernelPfP8MyStructi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
struct MyStruct {
float floatvalue;
int intvalue;
};
__device__ __host__ float sumStruct(struct MyStruct **p_structs, int N) {
float sum = 0;
for(int i = 0; i < N; i++) {
struct MyStruct *mystruct = p_structs[i];
sum += mystruct->floatvalue + float(mystruct->intvalue) * 3.5f;
}
return sum;
}
__global__ void mykernel(float *data, MyStruct *structs, int N) {
data[0] = sumStruct(&structs, N);
data[3] = sumStruct(&structs, 123);
data[4] = sumStruct(&structs, 12300);
} | .text
.file "phiaddressspace.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9sumStructPP8MyStructi
.LCPI0_0:
.long 0x40600000 # float 3.5
.text
.globl _Z9sumStructPP8MyStructi
.p2align 4, 0x90
.type _Z9sumStructPP8MyStructi,@function
_Z9sumStructPP8MyStructi: # @_Z9sumStructPP8MyStructi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rcx,8), %rdx
xorps %xmm2, %xmm2
cvtsi2ssl 4(%rdx), %xmm2
mulss %xmm1, %xmm2
addss (%rdx), %xmm2
addss %xmm2, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB0_4
# %bb.2: # %._crit_edge
retq
.LBB0_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end0:
.size _Z9sumStructPP8MyStructi, .Lfunc_end0-_Z9sumStructPP8MyStructi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__mykernelPfP8MyStructi # -- Begin function _Z23__device_stub__mykernelPfP8MyStructi
.p2align 4, 0x90
.type _Z23__device_stub__mykernelPfP8MyStructi,@function
_Z23__device_stub__mykernelPfP8MyStructi: # @_Z23__device_stub__mykernelPfP8MyStructi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mykernelPfP8MyStructi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__mykernelPfP8MyStructi, .Lfunc_end1-_Z23__device_stub__mykernelPfP8MyStructi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelPfP8MyStructi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelPfP8MyStructi,@object # @_Z8mykernelPfP8MyStructi
.section .rodata,"a",@progbits
.globl _Z8mykernelPfP8MyStructi
.p2align 3, 0x0
_Z8mykernelPfP8MyStructi:
.quad _Z23__device_stub__mykernelPfP8MyStructi
.size _Z8mykernelPfP8MyStructi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelPfP8MyStructi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelPfP8MyStructi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelPfP8MyStructi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00123e65_00000000-6_phiaddressspace.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9sumStructPP8MyStructi
.type _Z9sumStructPP8MyStructi, @function
_Z9sumStructPP8MyStructi:
.LFB2027:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L6
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rcx
pxor %xmm1, %xmm1
movss .LC1(%rip), %xmm2
.L5:
movq (%rax), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rdx), %xmm0
mulss %xmm2, %xmm0
addss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $8, %rax
cmpq %rcx, %rax
jne .L5
.L3:
movaps %xmm1, %xmm0
ret
.L6:
pxor %xmm1, %xmm1
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z9sumStructPP8MyStructi, .-_Z9sumStructPP8MyStructi
.globl _Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi
.type _Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi, @function
_Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mykernelPfP8MyStructi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi, .-_Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi
.globl _Z8mykernelPfP8MyStructi
.type _Z8mykernelPfP8MyStructi, @function
_Z8mykernelPfP8MyStructi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z8mykernelPfP8MyStructiPfP8MyStructi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8mykernelPfP8MyStructi, .-_Z8mykernelPfP8MyStructi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z8mykernelPfP8MyStructi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelPfP8MyStructi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1080033280
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "phiaddressspace.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9sumStructPP8MyStructi
.LCPI0_0:
.long 0x40600000 # float 3.5
.text
.globl _Z9sumStructPP8MyStructi
.p2align 4, 0x90
.type _Z9sumStructPP8MyStructi,@function
_Z9sumStructPP8MyStructi: # @_Z9sumStructPP8MyStructi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rcx,8), %rdx
xorps %xmm2, %xmm2
cvtsi2ssl 4(%rdx), %xmm2
mulss %xmm1, %xmm2
addss (%rdx), %xmm2
addss %xmm2, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB0_4
# %bb.2: # %._crit_edge
retq
.LBB0_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end0:
.size _Z9sumStructPP8MyStructi, .Lfunc_end0-_Z9sumStructPP8MyStructi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__mykernelPfP8MyStructi # -- Begin function _Z23__device_stub__mykernelPfP8MyStructi
.p2align 4, 0x90
.type _Z23__device_stub__mykernelPfP8MyStructi,@function
_Z23__device_stub__mykernelPfP8MyStructi: # @_Z23__device_stub__mykernelPfP8MyStructi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mykernelPfP8MyStructi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__mykernelPfP8MyStructi, .Lfunc_end1-_Z23__device_stub__mykernelPfP8MyStructi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelPfP8MyStructi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelPfP8MyStructi,@object # @_Z8mykernelPfP8MyStructi
.section .rodata,"a",@progbits
.globl _Z8mykernelPfP8MyStructi
.p2align 3, 0x0
_Z8mykernelPfP8MyStructi:
.quad _Z23__device_stub__mykernelPfP8MyStructi
.size _Z8mykernelPfP8MyStructi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelPfP8MyStructi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelPfP8MyStructi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelPfP8MyStructi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
__global__ void vectorAddKernel(int N, int *c_a, int *c_b, int *c_c){
int threadIndex = threadIdx.x;
int blockIndex = blockIdx.x;
int threadCount = blockDim.x;
int n = threadIndex + threadCount*blockIndex;
// check if n is in [0,N)
if(n<N)
c_c[n] = c_a[n] + c_b[n];
}
int main(int argc, char **argv){
int N = 4097;
int threadsPerBlock = 32;
int blocks = (N+threadsPerBlock-1)/threadsPerBlock;
// ON HOST
int *h_a = (int*) malloc(N*sizeof(int));
int *h_b = (int*) malloc(N*sizeof(int));
int *h_c = (int*) malloc(N*sizeof(int));
int n;
for(n=0;n<N;++n){
h_a[n] = 1 + n;
h_b[n] = 1 - n;
}
// ON DEVICE
int *c_a, *c_b, *c_c;
cudaMalloc(&c_a, N*sizeof(int));
cudaMalloc(&c_b, N*sizeof(int));
cudaMalloc(&c_c, N*sizeof(int));
cudaMemcpy(c_a, h_a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c_b, h_b, N*sizeof(int), cudaMemcpyHostToDevice);
// INITIATE KERNEL ON DEVICE
vectorAddKernel <<< blocks, threadsPerBlock >>> (N, c_a, c_b, c_c);
// COPY DATA FROM DEVICE TO HOST
cudaMemcpy(h_c, c_c, N*sizeof(int), cudaMemcpyDeviceToHost);
// PRINT ENTRIES
for(n=0;n<5;++n){
printf("c[%d] = %d\n", n, h_c[n]);
}
cudaDeviceSynchronize();
cudaFree(c_a);
cudaFree(c_b);
cudaFree(c_c);
} | code for sm_80
Function : _Z15vectorAddKerneliPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
__global__ void vectorAddKernel(int N, int *c_a, int *c_b, int *c_c){
int threadIndex = threadIdx.x;
int blockIndex = blockIdx.x;
int threadCount = blockDim.x;
int n = threadIndex + threadCount*blockIndex;
// check if n is in [0,N)
if(n<N)
c_c[n] = c_a[n] + c_b[n];
}
int main(int argc, char **argv){
int N = 4097;
int threadsPerBlock = 32;
int blocks = (N+threadsPerBlock-1)/threadsPerBlock;
// ON HOST
int *h_a = (int*) malloc(N*sizeof(int));
int *h_b = (int*) malloc(N*sizeof(int));
int *h_c = (int*) malloc(N*sizeof(int));
int n;
for(n=0;n<N;++n){
h_a[n] = 1 + n;
h_b[n] = 1 - n;
}
// ON DEVICE
int *c_a, *c_b, *c_c;
cudaMalloc(&c_a, N*sizeof(int));
cudaMalloc(&c_b, N*sizeof(int));
cudaMalloc(&c_c, N*sizeof(int));
cudaMemcpy(c_a, h_a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c_b, h_b, N*sizeof(int), cudaMemcpyHostToDevice);
// INITIATE KERNEL ON DEVICE
vectorAddKernel <<< blocks, threadsPerBlock >>> (N, c_a, c_b, c_c);
// COPY DATA FROM DEVICE TO HOST
cudaMemcpy(h_c, c_c, N*sizeof(int), cudaMemcpyDeviceToHost);
// PRINT ENTRIES
for(n=0;n<5;++n){
printf("c[%d] = %d\n", n, h_c[n]);
}
cudaDeviceSynchronize();
cudaFree(c_a);
cudaFree(c_b);
cudaFree(c_c);
} | .file "tmpxft_0011cfa3_00000000-6_data.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_
.type _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_, @function
_Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15vectorAddKerneliPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_, .-_Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_
.globl _Z15vectorAddKerneliPiS_S_
.type _Z15vectorAddKerneliPiS_S_, @function
_Z15vectorAddKerneliPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15vectorAddKerneliPiS_S_, .-_Z15vectorAddKerneliPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16388, %edi
call malloc@PLT
movq %rax, %rbp
movl $16388, %edi
call malloc@PLT
movq %rax, %rbx
movl $16388, %edi
call malloc@PLT
movq %rax, %r12
movl $1, %eax
movl $2, %ecx
.L12:
movl %eax, -4(%rbp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $4098, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $16388, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16388, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16388, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16388, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16388, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $129, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $16388, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl (%r12,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L14
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $4097, %edi
call _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15vectorAddKerneliPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15vectorAddKerneliPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
__global__ void vectorAddKernel(int N, int *c_a, int *c_b, int *c_c){
int threadIndex = threadIdx.x;
int blockIndex = blockIdx.x;
int threadCount = blockDim.x;
int n = threadIndex + threadCount*blockIndex;
// check if n is in [0,N)
if(n<N)
c_c[n] = c_a[n] + c_b[n];
}
int main(int argc, char **argv){
int N = 4097;
int threadsPerBlock = 32;
int blocks = (N+threadsPerBlock-1)/threadsPerBlock;
// ON HOST
int *h_a = (int*) malloc(N*sizeof(int));
int *h_b = (int*) malloc(N*sizeof(int));
int *h_c = (int*) malloc(N*sizeof(int));
int n;
for(n=0;n<N;++n){
h_a[n] = 1 + n;
h_b[n] = 1 - n;
}
// ON DEVICE
int *c_a, *c_b, *c_c;
cudaMalloc(&c_a, N*sizeof(int));
cudaMalloc(&c_b, N*sizeof(int));
cudaMalloc(&c_c, N*sizeof(int));
cudaMemcpy(c_a, h_a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c_b, h_b, N*sizeof(int), cudaMemcpyHostToDevice);
// INITIATE KERNEL ON DEVICE
vectorAddKernel <<< blocks, threadsPerBlock >>> (N, c_a, c_b, c_c);
// COPY DATA FROM DEVICE TO HOST
cudaMemcpy(h_c, c_c, N*sizeof(int), cudaMemcpyDeviceToHost);
// PRINT ENTRIES
for(n=0;n<5;++n){
printf("c[%d] = %d\n", n, h_c[n]);
}
cudaDeviceSynchronize();
cudaFree(c_a);
cudaFree(c_b);
cudaFree(c_c);
} | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void vectorAddKernel(int N, int *c_a, int *c_b, int *c_c){
int threadIndex = threadIdx.x;
int blockIndex = blockIdx.x;
int threadCount = blockDim.x;
int n = threadIndex + threadCount*blockIndex;
// check if n is in [0,N)
if(n<N)
c_c[n] = c_a[n] + c_b[n];
}
int main(int argc, char **argv){
int N = 4097;
int threadsPerBlock = 32;
int blocks = (N+threadsPerBlock-1)/threadsPerBlock;
// ON HOST
int *h_a = (int*) malloc(N*sizeof(int));
int *h_b = (int*) malloc(N*sizeof(int));
int *h_c = (int*) malloc(N*sizeof(int));
int n;
for(n=0;n<N;++n){
h_a[n] = 1 + n;
h_b[n] = 1 - n;
}
// ON DEVICE
int *c_a, *c_b, *c_c;
hipMalloc(&c_a, N*sizeof(int));
hipMalloc(&c_b, N*sizeof(int));
hipMalloc(&c_c, N*sizeof(int));
hipMemcpy(c_a, h_a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c_b, h_b, N*sizeof(int), hipMemcpyHostToDevice);
// INITIATE KERNEL ON DEVICE
vectorAddKernel <<< blocks, threadsPerBlock >>> (N, c_a, c_b, c_c);
// COPY DATA FROM DEVICE TO HOST
hipMemcpy(h_c, c_c, N*sizeof(int), hipMemcpyDeviceToHost);
// PRINT ENTRIES
for(n=0;n<5;++n){
printf("c[%d] = %d\n", n, h_c[n]);
}
hipDeviceSynchronize();
hipFree(c_a);
hipFree(c_b);
hipFree(c_c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void vectorAddKernel(int N, int *c_a, int *c_b, int *c_c){
int threadIndex = threadIdx.x;
int blockIndex = blockIdx.x;
int threadCount = blockDim.x;
int n = threadIndex + threadCount*blockIndex;
// check if n is in [0,N)
if(n<N)
c_c[n] = c_a[n] + c_b[n];
}
int main(int argc, char **argv){
int N = 4097;
int threadsPerBlock = 32;
int blocks = (N+threadsPerBlock-1)/threadsPerBlock;
// ON HOST
int *h_a = (int*) malloc(N*sizeof(int));
int *h_b = (int*) malloc(N*sizeof(int));
int *h_c = (int*) malloc(N*sizeof(int));
int n;
for(n=0;n<N;++n){
h_a[n] = 1 + n;
h_b[n] = 1 - n;
}
// ON DEVICE
int *c_a, *c_b, *c_c;
hipMalloc(&c_a, N*sizeof(int));
hipMalloc(&c_b, N*sizeof(int));
hipMalloc(&c_c, N*sizeof(int));
hipMemcpy(c_a, h_a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c_b, h_b, N*sizeof(int), hipMemcpyHostToDevice);
// INITIATE KERNEL ON DEVICE
vectorAddKernel <<< blocks, threadsPerBlock >>> (N, c_a, c_b, c_c);
// COPY DATA FROM DEVICE TO HOST
hipMemcpy(h_c, c_c, N*sizeof(int), hipMemcpyDeviceToHost);
// PRINT ENTRIES
for(n=0;n<5;++n){
printf("c[%d] = %d\n", n, h_c[n]);
}
hipDeviceSynchronize();
hipFree(c_a);
hipFree(c_b);
hipFree(c_c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15vectorAddKerneliPiS_S_
.globl _Z15vectorAddKerneliPiS_S_
.p2align 8
.type _Z15vectorAddKerneliPiS_S_,@function
_Z15vectorAddKerneliPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15vectorAddKerneliPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15vectorAddKerneliPiS_S_, .Lfunc_end0-_Z15vectorAddKerneliPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15vectorAddKerneliPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15vectorAddKerneliPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void vectorAddKernel(int N, int *c_a, int *c_b, int *c_c){
int threadIndex = threadIdx.x;
int blockIndex = blockIdx.x;
int threadCount = blockDim.x;
int n = threadIndex + threadCount*blockIndex;
// check if n is in [0,N)
if(n<N)
c_c[n] = c_a[n] + c_b[n];
}
int main(int argc, char **argv){
int N = 4097;
int threadsPerBlock = 32;
int blocks = (N+threadsPerBlock-1)/threadsPerBlock;
// ON HOST
int *h_a = (int*) malloc(N*sizeof(int));
int *h_b = (int*) malloc(N*sizeof(int));
int *h_c = (int*) malloc(N*sizeof(int));
int n;
for(n=0;n<N;++n){
h_a[n] = 1 + n;
h_b[n] = 1 - n;
}
// ON DEVICE
int *c_a, *c_b, *c_c;
hipMalloc(&c_a, N*sizeof(int));
hipMalloc(&c_b, N*sizeof(int));
hipMalloc(&c_c, N*sizeof(int));
hipMemcpy(c_a, h_a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c_b, h_b, N*sizeof(int), hipMemcpyHostToDevice);
// INITIATE KERNEL ON DEVICE
vectorAddKernel <<< blocks, threadsPerBlock >>> (N, c_a, c_b, c_c);
// COPY DATA FROM DEVICE TO HOST
hipMemcpy(h_c, c_c, N*sizeof(int), hipMemcpyDeviceToHost);
// PRINT ENTRIES
for(n=0;n<5;++n){
printf("c[%d] = %d\n", n, h_c[n]);
}
hipDeviceSynchronize();
hipFree(c_a);
hipFree(c_b);
hipFree(c_c);
} | .text
.file "data.hip"
.globl _Z30__device_stub__vectorAddKerneliPiS_S_ # -- Begin function _Z30__device_stub__vectorAddKerneliPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__vectorAddKerneliPiS_S_,@function
_Z30__device_stub__vectorAddKerneliPiS_S_: # @_Z30__device_stub__vectorAddKerneliPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15vectorAddKerneliPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__vectorAddKerneliPiS_S_, .Lfunc_end0-_Z30__device_stub__vectorAddKerneliPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16388, %edi # imm = 0x4004
callq malloc
movq %rax, %r15
movl $16388, %edi # imm = 0x4004
callq malloc
movq %rax, %r14
movl $16388, %edi # imm = 0x4004
callq malloc
movq %rax, %rbx
movl $1, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%r15,%rcx,4)
movl %eax, (%r14,%rcx,4)
decl %eax
movq %rdx, %rcx
cmpq $4097, %rdx # imm = 0x1001
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $16388, %esi # imm = 0x4004
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16388, %esi # imm = 0x4004
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16388, %esi # imm = 0x4004
callq hipMalloc
movq 24(%rsp), %rdi
movl $16388, %edx # imm = 0x4004
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16388, %edx # imm = 0x4004
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 97(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $4097, 36(%rsp) # imm = 0x1001
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15vectorAddKerneliPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $16388, %edx # imm = 0x4004
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $5, %r14
jne .LBB1_5
# %bb.6:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15vectorAddKerneliPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15vectorAddKerneliPiS_S_,@object # @_Z15vectorAddKerneliPiS_S_
.section .rodata,"a",@progbits
.globl _Z15vectorAddKerneliPiS_S_
.p2align 3, 0x0
_Z15vectorAddKerneliPiS_S_:
.quad _Z30__device_stub__vectorAddKerneliPiS_S_
.size _Z15vectorAddKerneliPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15vectorAddKerneliPiS_S_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__vectorAddKerneliPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15vectorAddKerneliPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15vectorAddKerneliPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15vectorAddKerneliPiS_S_
.globl _Z15vectorAddKerneliPiS_S_
.p2align 8
.type _Z15vectorAddKerneliPiS_S_,@function
_Z15vectorAddKerneliPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15vectorAddKerneliPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15vectorAddKerneliPiS_S_, .Lfunc_end0-_Z15vectorAddKerneliPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15vectorAddKerneliPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15vectorAddKerneliPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011cfa3_00000000-6_data.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_
.type _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_, @function
_Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15vectorAddKerneliPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_, .-_Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_
.globl _Z15vectorAddKerneliPiS_S_
.type _Z15vectorAddKerneliPiS_S_, @function
_Z15vectorAddKerneliPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15vectorAddKerneliPiS_S_, .-_Z15vectorAddKerneliPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16388, %edi
call malloc@PLT
movq %rax, %rbp
movl $16388, %edi
call malloc@PLT
movq %rax, %rbx
movl $16388, %edi
call malloc@PLT
movq %rax, %r12
movl $1, %eax
movl $2, %ecx
.L12:
movl %eax, -4(%rbp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $4098, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $16388, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16388, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16388, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16388, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16388, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $129, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $16388, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl (%r12,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L14
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $4097, %edi
call _Z40__device_stub__Z15vectorAddKerneliPiS_S_iPiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15vectorAddKerneliPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15vectorAddKerneliPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "data.hip"
.globl _Z30__device_stub__vectorAddKerneliPiS_S_ # -- Begin function _Z30__device_stub__vectorAddKerneliPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__vectorAddKerneliPiS_S_,@function
_Z30__device_stub__vectorAddKerneliPiS_S_: # @_Z30__device_stub__vectorAddKerneliPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15vectorAddKerneliPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__vectorAddKerneliPiS_S_, .Lfunc_end0-_Z30__device_stub__vectorAddKerneliPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16388, %edi # imm = 0x4004
callq malloc
movq %rax, %r15
movl $16388, %edi # imm = 0x4004
callq malloc
movq %rax, %r14
movl $16388, %edi # imm = 0x4004
callq malloc
movq %rax, %rbx
movl $1, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%r15,%rcx,4)
movl %eax, (%r14,%rcx,4)
decl %eax
movq %rdx, %rcx
cmpq $4097, %rdx # imm = 0x1001
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $16388, %esi # imm = 0x4004
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16388, %esi # imm = 0x4004
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16388, %esi # imm = 0x4004
callq hipMalloc
movq 24(%rsp), %rdi
movl $16388, %edx # imm = 0x4004
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16388, %edx # imm = 0x4004
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 97(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $4097, 36(%rsp) # imm = 0x1001
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15vectorAddKerneliPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $16388, %edx # imm = 0x4004
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $5, %r14
jne .LBB1_5
# %bb.6:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15vectorAddKerneliPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15vectorAddKerneliPiS_S_,@object # @_Z15vectorAddKerneliPiS_S_
.section .rodata,"a",@progbits
.globl _Z15vectorAddKerneliPiS_S_
.p2align 3, 0x0
_Z15vectorAddKerneliPiS_S_:
.quad _Z30__device_stub__vectorAddKerneliPiS_S_
.size _Z15vectorAddKerneliPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15vectorAddKerneliPiS_S_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__vectorAddKerneliPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15vectorAddKerneliPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#ifndef checkCudaErrors
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
void __checkCudaErrors(cudaError_t err, const char *file, const int line)
{
if(cudaSuccess != err)
{
fprintf(stderr, "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n", err, cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#endif
int main(void)
{
int *dev_a;
checkCudaErrors(cudaMalloc((void**)&dev_a, 10000000000000 * sizeof(int)));
cudaFree(dev_a);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#ifndef checkCudaErrors
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
void __checkCudaErrors(cudaError_t err, const char *file, const int line)
{
if(cudaSuccess != err)
{
fprintf(stderr, "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n", err, cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#endif
int main(void)
{
int *dev_a;
checkCudaErrors(cudaMalloc((void**)&dev_a, 10000000000000 * sizeof(int)));
cudaFree(dev_a);
return 0;
} | .file "tmpxft_0003a47d_00000000-6_error_checking3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n"
.text
.globl _Z17__checkCudaErrors9cudaErrorPKci
.type _Z17__checkCudaErrors9cudaErrorPKci, @function
_Z17__checkCudaErrors9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
movq %rsi, %rbp
movl %edx, %r12d
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
movq %rbp, %r9
movl %ebx, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z17__checkCudaErrors9cudaErrorPKci, .-_Z17__checkCudaErrors9cudaErrorPKci
.section .rodata.str1.8
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/rmuenste/cuda-intro/master/debugging/error_checking3.cu"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movabsq $40000000000000, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $25, %edx
leaq .LC1(%rip), %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#ifndef checkCudaErrors
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
void __checkCudaErrors(cudaError_t err, const char *file, const int line)
{
if(cudaSuccess != err)
{
fprintf(stderr, "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n", err, cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#endif
int main(void)
{
int *dev_a;
checkCudaErrors(cudaMalloc((void**)&dev_a, 10000000000000 * sizeof(int)));
cudaFree(dev_a);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#ifndef checkCudaErrors
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
void __checkCudaErrors(hipError_t err, const char *file, const int line)
{
if(hipSuccess != err)
{
fprintf(stderr, "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n", err, hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#endif
int main(void)
{
int *dev_a;
checkCudaErrors(hipMalloc((void**)&dev_a, 10000000000000 * sizeof(int)));
hipFree(dev_a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#ifndef checkCudaErrors
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
void __checkCudaErrors(hipError_t err, const char *file, const int line)
{
if(hipSuccess != err)
{
fprintf(stderr, "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n", err, hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#endif
int main(void)
{
int *dev_a;
checkCudaErrors(hipMalloc((void**)&dev_a, 10000000000000 * sizeof(int)));
hipFree(dev_a);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#ifndef checkCudaErrors
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
void __checkCudaErrors(hipError_t err, const char *file, const int line)
{
if(hipSuccess != err)
{
fprintf(stderr, "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n", err, hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#endif
int main(void)
{
int *dev_a;
checkCudaErrors(hipMalloc((void**)&dev_a, 10000000000000 * sizeof(int)));
hipFree(dev_a);
return 0;
} | .text
.file "error_checking3.hip"
.globl _Z17__checkCudaErrors10hipError_tPKci # -- Begin function _Z17__checkCudaErrors10hipError_tPKci
.p2align 4, 0x90
.type _Z17__checkCudaErrors10hipError_tPKci,@function
_Z17__checkCudaErrors10hipError_tPKci: # @_Z17__checkCudaErrors10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq stderr(%rip), %rbx
movl %edi, %ebp
movl %edx, %r14d
movq %rsi, %r15
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movq %r15, %r8
movl %r14d, %r9d
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z17__checkCudaErrors10hipError_tPKci, .Lfunc_end0-_Z17__checkCudaErrors10hipError_tPKci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movabsq $40000000000000, %rsi # imm = 0x246139CA8000
callq hipMalloc
testl %eax, %eax
jne .LBB1_2
# %bb.1: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $25, %r9d
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n"
.size .L.str, 73
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/rmuenste/cuda-intro/master/debugging/error_checking3.hip"
.size .L.str.1, 114
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003a47d_00000000-6_error_checking3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n"
.text
.globl _Z17__checkCudaErrors9cudaErrorPKci
.type _Z17__checkCudaErrors9cudaErrorPKci, @function
_Z17__checkCudaErrors9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
movq %rsi, %rbp
movl %edx, %r12d
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
movq %rbp, %r9
movl %ebx, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z17__checkCudaErrors9cudaErrorPKci, .-_Z17__checkCudaErrors9cudaErrorPKci
.section .rodata.str1.8
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/rmuenste/cuda-intro/master/debugging/error_checking3.cu"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movabsq $40000000000000, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $25, %edx
leaq .LC1(%rip), %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "error_checking3.hip"
.globl _Z17__checkCudaErrors10hipError_tPKci # -- Begin function _Z17__checkCudaErrors10hipError_tPKci
.p2align 4, 0x90
.type _Z17__checkCudaErrors10hipError_tPKci,@function
_Z17__checkCudaErrors10hipError_tPKci: # @_Z17__checkCudaErrors10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq stderr(%rip), %rbx
movl %edi, %ebp
movl %edx, %r14d
movq %rsi, %r15
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movq %r15, %r8
movl %r14d, %r9d
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z17__checkCudaErrors10hipError_tPKci, .Lfunc_end0-_Z17__checkCudaErrors10hipError_tPKci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movabsq $40000000000000, %rsi # imm = 0x246139CA8000
callq hipMalloc
testl %eax, %eax
jne .LBB1_2
# %bb.1: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $25, %r9d
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "checkCudaErrors() Driver API error = %04d \"%s\" from file <%s>, line %i.\n"
.size .L.str, 73
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/rmuenste/cuda-intro/master/debugging/error_checking3.hip"
.size .L.str.1, 114
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void vectorAdd(float *, float *, float *, int);
__global__
void vectorAdd(float *A, float *B, float *C, int n)
{
// CUDA kernel definition
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
C[i] = A[i] + B[i];
}
return;
}
void vecAdd(float *h_A, float *h_B, float *h_C, int n)
{
// host program
int size = n * sizeof(float);
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
err = cudaMalloc((void **) &d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_B, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_C, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
int threadsPerBlock = 256;
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
vectorAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, n);
err = cudaGetLastError();
// device function (CUDA kernel) called from host does not have return type
// CUDA runtime functions (execute in host side) can have return type
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Verify that the result vector is correct
for (int i = 0; i < n; ++i)
{
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
return;
}
int main()
{
int n;
float *h_A, *h_B, *h_C;
int i;
printf("Enter the number of elements: ");
scanf("%d", &n);
h_A = (float *) malloc(sizeof(float) * n);
h_B = (float *) malloc(sizeof(float) * n);
h_C = (float *) malloc(sizeof(float) * n);
srand(time(0));
for (i = 0; i < n; ++i)
{
h_A[i] = rand();
h_B[i] = rand();
}
vecAdd(h_A, h_B, h_C, n);
return 0;
} | code for sm_80
Function : _Z9vectorAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void vectorAdd(float *, float *, float *, int);
__global__
void vectorAdd(float *A, float *B, float *C, int n)
{
// CUDA kernel definition
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
C[i] = A[i] + B[i];
}
return;
}
void vecAdd(float *h_A, float *h_B, float *h_C, int n)
{
// host program
int size = n * sizeof(float);
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
err = cudaMalloc((void **) &d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_B, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_C, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
int threadsPerBlock = 256;
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
vectorAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, n);
err = cudaGetLastError();
// device function (CUDA kernel) called from host does not have return type
// CUDA runtime functions (execute in host side) can have return type
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Verify that the result vector is correct
for (int i = 0; i < n; ++i)
{
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
return;
}
int main()
{
int n;
float *h_A, *h_B, *h_C;
int i;
printf("Enter the number of elements: ");
scanf("%d", &n);
h_A = (float *) malloc(sizeof(float) * n);
h_B = (float *) malloc(sizeof(float) * n);
h_C = (float *) malloc(sizeof(float) * n);
srand(time(0));
for (i = 0; i < n; ++i)
{
h_A[i] = rand();
h_B[i] = rand();
}
vecAdd(h_A, h_B, h_C, n);
return 0;
} | .file "tmpxft_00037a1a_00000000-6_1_vector_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i
.globl _Z9vectorAddPfS_S_i
.type _Z9vectorAddPfS_S_i, @function
_Z9vectorAddPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9vectorAddPfS_S_i, .-_Z9vectorAddPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate device vector A (error code %s)!\n"
.align 8
.LC1:
.string "Failed to allocate device vector B (error code %s)!\n"
.align 8
.LC2:
.string "Failed to allocate device vector C (error code %s)!\n"
.align 8
.LC3:
.string "Copy input data from the host memory to the CUDA device\n"
.align 8
.LC4:
.string "Failed to copy vector A from host to device (error code %s)!\n"
.align 8
.LC5:
.string "Failed to copy vector B from host to device (error code %s)!\n"
.align 8
.LC6:
.string "CUDA kernel launch with %d blocks of %d threads\n"
.align 8
.LC7:
.string "Failed to launch vectorAdd kernel (error code %s)!\n"
.align 8
.LC8:
.string "Failed to copy vector C from device to host (error code %s)!\n"
.align 8
.LC11:
.string "Result verification failed at element %d!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "Test PASSED\n"
.text
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %ecx, %r13
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leal 0(,%rcx,4), %r15d
movslq %r15d, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L29
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
leal 510(%r14), %eax
movl %r14d, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl $256, %ecx
movl %eax, 12(%rsp)
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl 12(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L17:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %r14d, %r14d
jle .L20
movl $0, %eax
movss .LC9(%rip), %xmm2
movsd .LC10(%rip), %xmm1
.L23:
movss (%rbx,%rax,4), %xmm0
addss 0(%rbp,%rax,4), %xmm0
subss (%r12,%rax,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L37
addq $1, %rax
cmpq %rax, %r13
jne .L23
.L20:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %r14d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i
jmp .L17
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.8
.align 8
.LC13:
.string "Enter the number of elements: "
.section .rodata.str1.1
.LC14:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC13(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC14(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 4(%rsp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl 4(%rsp), %ecx
testl %ecx, %ecx
jle .L40
movl $0, %ebx
.L41:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
movl 4(%rsp), %ecx
addq $1, %rbx
cmpl %ebx, %ecx
jg .L41
.L40:
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z6vecAddPfS_S_i
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z9vectorAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void vectorAdd(float *, float *, float *, int);
__global__
void vectorAdd(float *A, float *B, float *C, int n)
{
// CUDA kernel definition
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
C[i] = A[i] + B[i];
}
return;
}
void vecAdd(float *h_A, float *h_B, float *h_C, int n)
{
// host program
int size = n * sizeof(float);
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
err = cudaMalloc((void **) &d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_B, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_C, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
int threadsPerBlock = 256;
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
vectorAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, n);
err = cudaGetLastError();
// device function (CUDA kernel) called from host does not have return type
// CUDA runtime functions (execute in host side) can have return type
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Verify that the result vector is correct
for (int i = 0; i < n; ++i)
{
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
return;
}
int main()
{
int n;
float *h_A, *h_B, *h_C;
int i;
printf("Enter the number of elements: ");
scanf("%d", &n);
h_A = (float *) malloc(sizeof(float) * n);
h_B = (float *) malloc(sizeof(float) * n);
h_C = (float *) malloc(sizeof(float) * n);
srand(time(0));
for (i = 0; i < n; ++i)
{
h_A[i] = rand();
h_B[i] = rand();
}
vecAdd(h_A, h_B, h_C, n);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void vectorAdd(float *, float *, float *, int);
__global__
void vectorAdd(float *A, float *B, float *C, int n)
{
// CUDA kernel definition
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
C[i] = A[i] + B[i];
}
return;
}
void vecAdd(float *h_A, float *h_B, float *h_C, int n)
{
// host program
int size = n * sizeof(float);
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
err = hipMalloc((void **) &d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_B, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_C, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
int threadsPerBlock = 256;
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
vectorAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, n);
err = hipGetLastError();
// device function (CUDA kernel) called from host does not have return type
// CUDA runtime functions (execute in host side) can have return type
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Verify that the result vector is correct
for (int i = 0; i < n; ++i)
{
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
return;
}
int main()
{
int n;
float *h_A, *h_B, *h_C;
int i;
printf("Enter the number of elements: ");
scanf("%d", &n);
h_A = (float *) malloc(sizeof(float) * n);
h_B = (float *) malloc(sizeof(float) * n);
h_C = (float *) malloc(sizeof(float) * n);
srand(time(0));
for (i = 0; i < n; ++i)
{
h_A[i] = rand();
h_B[i] = rand();
}
vecAdd(h_A, h_B, h_C, n);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void vectorAdd(float *, float *, float *, int);
__global__
void vectorAdd(float *A, float *B, float *C, int n)
{
// CUDA kernel definition
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
C[i] = A[i] + B[i];
}
return;
}
void vecAdd(float *h_A, float *h_B, float *h_C, int n)
{
// host program
int size = n * sizeof(float);
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
err = hipMalloc((void **) &d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_B, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_C, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
int threadsPerBlock = 256;
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
vectorAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, n);
err = hipGetLastError();
// device function (CUDA kernel) called from host does not have return type
// CUDA runtime functions (execute in host side) can have return type
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Verify that the result vector is correct
for (int i = 0; i < n; ++i)
{
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
return;
}
int main()
{
int n;
float *h_A, *h_B, *h_C;
int i;
printf("Enter the number of elements: ");
scanf("%d", &n);
h_A = (float *) malloc(sizeof(float) * n);
h_B = (float *) malloc(sizeof(float) * n);
h_C = (float *) malloc(sizeof(float) * n);
srand(time(0));
for (i = 0; i < n; ++i)
{
h_A[i] = rand();
h_B[i] = rand();
}
vecAdd(h_A, h_B, h_C, n);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPfS_S_i
.globl _Z9vectorAddPfS_S_i
.p2align 8
.type _Z9vectorAddPfS_S_i,@function
_Z9vectorAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPfS_S_i, .Lfunc_end0-_Z9vectorAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void vectorAdd(float *, float *, float *, int);
__global__
void vectorAdd(float *A, float *B, float *C, int n)
{
// CUDA kernel definition
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
C[i] = A[i] + B[i];
}
return;
}
void vecAdd(float *h_A, float *h_B, float *h_C, int n)
{
// host program
int size = n * sizeof(float);
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
err = hipMalloc((void **) &d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_B, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_C, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
int threadsPerBlock = 256;
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
vectorAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, n);
err = hipGetLastError();
// device function (CUDA kernel) called from host does not have return type
// CUDA runtime functions (execute in host side) can have return type
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Verify that the result vector is correct
for (int i = 0; i < n; ++i)
{
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
printf("Test PASSED\n");
return;
}
int main()
{
int n;
float *h_A, *h_B, *h_C;
int i;
printf("Enter the number of elements: ");
scanf("%d", &n);
h_A = (float *) malloc(sizeof(float) * n);
h_B = (float *) malloc(sizeof(float) * n);
h_C = (float *) malloc(sizeof(float) * n);
srand(time(0));
for (i = 0; i < n; ++i)
{
h_A[i] = rand();
h_B[i] = rand();
}
vecAdd(h_A, h_B, h_C, n);
return 0;
} | .text
.file "1_vector_addition.hip"
.globl _Z24__device_stub__vectorAddPfS_S_i # -- Begin function _Z24__device_stub__vectorAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPfS_S_i,@function
_Z24__device_stub__vectorAddPfS_S_i: # @_Z24__device_stub__vectorAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__vectorAddPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6vecAddPfS_S_i
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl _Z6vecAddPfS_S_i
.p2align 4, 0x90
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i: # @_Z6vecAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leal (,%r12,4), %eax
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movslq %eax, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5:
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11:
leal 255(%r12), %eax
leal 510(%r12), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $8, %ebp
movl $.L.str.6, %edi
movl %ebp, %esi
movl $256, %edx # imm = 0x100
xorl %eax, %eax
callq printf
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rbp
orq $256, %rdx # imm = 0x100
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r12d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9vectorAddPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
testl %r12d, %r12d
jle .LBB1_21
# %bb.18: # %.lr.ph.preheader
movl %r12d, %eax
xorl %edx, %edx
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_19: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r15,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss (%r14,%rdx,4), %xmm2
subss (%rbx,%rdx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB1_22
# %bb.20: # in Loop: Header=BB1_19 Depth=1
incq %rdx
cmpq %rdx, %rax
jne .LBB1_19
.LBB1_21: # %._crit_edge
movl $.Lstr.2, %edi
callq puts@PLT
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_1:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
.LBB1_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z6vecAddPfS_S_i, .Lfunc_end1-_Z6vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, %r15
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl 4(%rsp), %ecx
testl %ecx, %ecx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
movslq 4(%rsp), %rcx
cmpq %rcx, %r12
jl .LBB2_2
.LBB2_3: # %._crit_edge
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
# kill: def $ecx killed $ecx killed $rcx
callq _Z6vecAddPfS_S_i
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPfS_S_i,@object # @_Z9vectorAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectorAddPfS_S_i
.p2align 3, 0x0
_Z9vectorAddPfS_S_i:
.quad _Z24__device_stub__vectorAddPfS_S_i
.size _Z9vectorAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate device vector A (error code %s)!\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate device vector B (error code %s)!\n"
.size .L.str.1, 53
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device vector C (error code %s)!\n"
.size .L.str.2, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to copy vector A from host to device (error code %s)!\n"
.size .L.str.4, 62
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy vector B from host to device (error code %s)!\n"
.size .L.str.5, 62
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA kernel launch with %d blocks of %d threads\n"
.size .L.str.6, 49
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to launch vectorAdd kernel (error code %s)!\n"
.size .L.str.7, 52
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to copy vector C from device to host (error code %s)!\n"
.size .L.str.8, 62
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result verification failed at element %d!\n"
.size .L.str.9, 43
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Enter the number of elements: "
.size .L.str.11, 31
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d"
.size .L.str.12, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vectorAddPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Copy input data from the host memory to the CUDA device"
.size .Lstr.1, 56
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Test PASSED"
.size .Lstr.2, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9vectorAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPfS_S_i
.globl _Z9vectorAddPfS_S_i
.p2align 8
.type _Z9vectorAddPfS_S_i,@function
_Z9vectorAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPfS_S_i, .Lfunc_end0-_Z9vectorAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00037a1a_00000000-6_1_vector_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i
.globl _Z9vectorAddPfS_S_i
.type _Z9vectorAddPfS_S_i, @function
_Z9vectorAddPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9vectorAddPfS_S_i, .-_Z9vectorAddPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate device vector A (error code %s)!\n"
.align 8
.LC1:
.string "Failed to allocate device vector B (error code %s)!\n"
.align 8
.LC2:
.string "Failed to allocate device vector C (error code %s)!\n"
.align 8
.LC3:
.string "Copy input data from the host memory to the CUDA device\n"
.align 8
.LC4:
.string "Failed to copy vector A from host to device (error code %s)!\n"
.align 8
.LC5:
.string "Failed to copy vector B from host to device (error code %s)!\n"
.align 8
.LC6:
.string "CUDA kernel launch with %d blocks of %d threads\n"
.align 8
.LC7:
.string "Failed to launch vectorAdd kernel (error code %s)!\n"
.align 8
.LC8:
.string "Failed to copy vector C from device to host (error code %s)!\n"
.align 8
.LC11:
.string "Result verification failed at element %d!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "Test PASSED\n"
.text
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %ecx, %r13
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leal 0(,%rcx,4), %r15d
movslq %r15d, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L29
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
leal 510(%r14), %eax
movl %r14d, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl $256, %ecx
movl %eax, 12(%rsp)
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl 12(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L17:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %r14d, %r14d
jle .L20
movl $0, %eax
movss .LC9(%rip), %xmm2
movsd .LC10(%rip), %xmm1
.L23:
movss (%rbx,%rax,4), %xmm0
addss 0(%rbp,%rax,4), %xmm0
subss (%r12,%rax,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L37
addq $1, %rax
cmpq %rax, %r13
jne .L23
.L20:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %r14d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9vectorAddPfS_S_iPfS_S_i
jmp .L17
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.8
.align 8
.LC13:
.string "Enter the number of elements: "
.section .rodata.str1.1
.LC14:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC13(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC14(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 4(%rsp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl 4(%rsp), %ecx
testl %ecx, %ecx
jle .L40
movl $0, %ebx
.L41:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
movl 4(%rsp), %ecx
addq $1, %rbx
cmpl %ebx, %ecx
jg .L41
.L40:
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z6vecAddPfS_S_i
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z9vectorAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1_vector_addition.hip"
.globl _Z24__device_stub__vectorAddPfS_S_i # -- Begin function _Z24__device_stub__vectorAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPfS_S_i,@function
_Z24__device_stub__vectorAddPfS_S_i: # @_Z24__device_stub__vectorAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__vectorAddPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6vecAddPfS_S_i
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl _Z6vecAddPfS_S_i
.p2align 4, 0x90
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i: # @_Z6vecAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leal (,%r12,4), %eax
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movslq %eax, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5:
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11:
leal 255(%r12), %eax
leal 510(%r12), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $8, %ebp
movl $.L.str.6, %edi
movl %ebp, %esi
movl $256, %edx # imm = 0x100
xorl %eax, %eax
callq printf
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rbp
orq $256, %rdx # imm = 0x100
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r12d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9vectorAddPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
testl %r12d, %r12d
jle .LBB1_21
# %bb.18: # %.lr.ph.preheader
movl %r12d, %eax
xorl %edx, %edx
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_19: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r15,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss (%r14,%rdx,4), %xmm2
subss (%rbx,%rdx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB1_22
# %bb.20: # in Loop: Header=BB1_19 Depth=1
incq %rdx
cmpq %rdx, %rax
jne .LBB1_19
.LBB1_21: # %._crit_edge
movl $.Lstr.2, %edi
callq puts@PLT
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_1:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
.LBB1_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z6vecAddPfS_S_i, .Lfunc_end1-_Z6vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, %r15
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl 4(%rsp), %ecx
testl %ecx, %ecx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
movslq 4(%rsp), %rcx
cmpq %rcx, %r12
jl .LBB2_2
.LBB2_3: # %._crit_edge
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
# kill: def $ecx killed $ecx killed $rcx
callq _Z6vecAddPfS_S_i
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPfS_S_i,@object # @_Z9vectorAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectorAddPfS_S_i
.p2align 3, 0x0
_Z9vectorAddPfS_S_i:
.quad _Z24__device_stub__vectorAddPfS_S_i
.size _Z9vectorAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate device vector A (error code %s)!\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate device vector B (error code %s)!\n"
.size .L.str.1, 53
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device vector C (error code %s)!\n"
.size .L.str.2, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to copy vector A from host to device (error code %s)!\n"
.size .L.str.4, 62
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy vector B from host to device (error code %s)!\n"
.size .L.str.5, 62
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA kernel launch with %d blocks of %d threads\n"
.size .L.str.6, 49
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to launch vectorAdd kernel (error code %s)!\n"
.size .L.str.7, 52
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to copy vector C from device to host (error code %s)!\n"
.size .L.str.8, 62
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result verification failed at element %d!\n"
.size .L.str.9, 43
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Enter the number of elements: "
.size .L.str.11, 31
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d"
.size .L.str.12, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vectorAddPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Copy input data from the host memory to the CUDA device"
.size .Lstr.1, 56
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Test PASSED"
.size .Lstr.2, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void InterpolateFromMemBlock(float* input1, float* input2, float* output, float* weightMemBlock, int inputSize)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
if (weightMemBlock[0] <= 0)
{
output[threadId] = input1[threadId];
}
else if (weightMemBlock[0] >= 1)
{
output[threadId] = input2[threadId];
}
else
{
output[threadId] = (1 - weightMemBlock[0]) * input1[threadId] + weightMemBlock[0] * input2[threadId];
}
}
} | code for sm_80
Function : _Z23InterpolateFromMemBlockPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fca0000000f00 */
/*00b0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fd20000011400 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0100*/ FSETP.GTU.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x004fda0003f0c000 */
/*0110*/ @P0 BRA 0x150 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0130*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ FSETP.GE.AND P0, PT, R8, 1, PT ; /* 0x3f8000000800780b */
/* 0x000fe40003f06000 */
/*0160*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078210ff */
/*0170*/ LEA.HI.X R3, R0, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fce00008f1409 */
/*0180*/ @!P0 BRA 0x1c0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee2000c1e1900 */
/*01e0*/ FADD R0, -R8, 1 ; /* 0x3f80000008007421 */
/* 0x000fc40000000100 */
/*01f0*/ FMUL R8, R8, R3 ; /* 0x0000000308087220 */
/* 0x004fc80000400000 */
/*0200*/ FFMA R9, R0, R5, R8 ; /* 0x0000000500097223 */
/* 0x008fca0000000008 */
/*0210*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void InterpolateFromMemBlock(float* input1, float* input2, float* output, float* weightMemBlock, int inputSize)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
if (weightMemBlock[0] <= 0)
{
output[threadId] = input1[threadId];
}
else if (weightMemBlock[0] >= 1)
{
output[threadId] = input2[threadId];
}
else
{
output[threadId] = (1 - weightMemBlock[0]) * input1[threadId] + weightMemBlock[0] * input2[threadId];
}
}
} | .file "tmpxft_0011931b_00000000-6_InterpolateFromMemBlock.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i
.type _Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i, @function
_Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23InterpolateFromMemBlockPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i, .-_Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i
.globl _Z23InterpolateFromMemBlockPfS_S_S_i
.type _Z23InterpolateFromMemBlockPfS_S_S_i, @function
_Z23InterpolateFromMemBlockPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23InterpolateFromMemBlockPfS_S_S_i, .-_Z23InterpolateFromMemBlockPfS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23InterpolateFromMemBlockPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23InterpolateFromMemBlockPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void InterpolateFromMemBlock(float* input1, float* input2, float* output, float* weightMemBlock, int inputSize)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
if (weightMemBlock[0] <= 0)
{
output[threadId] = input1[threadId];
}
else if (weightMemBlock[0] >= 1)
{
output[threadId] = input2[threadId];
}
else
{
output[threadId] = (1 - weightMemBlock[0]) * input1[threadId] + weightMemBlock[0] * input2[threadId];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InterpolateFromMemBlock(float* input1, float* input2, float* output, float* weightMemBlock, int inputSize)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
if (weightMemBlock[0] <= 0)
{
output[threadId] = input1[threadId];
}
else if (weightMemBlock[0] >= 1)
{
output[threadId] = input2[threadId];
}
else
{
output[threadId] = (1 - weightMemBlock[0]) * input1[threadId] + weightMemBlock[0] * input2[threadId];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InterpolateFromMemBlock(float* input1, float* input2, float* output, float* weightMemBlock, int inputSize)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
if (weightMemBlock[0] <= 0)
{
output[threadId] = input1[threadId];
}
else if (weightMemBlock[0] >= 1)
{
output[threadId] = input2[threadId];
}
else
{
output[threadId] = (1 - weightMemBlock[0]) * input1[threadId] + weightMemBlock[0] * input2[threadId];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23InterpolateFromMemBlockPfS_S_S_i
.globl _Z23InterpolateFromMemBlockPfS_S_S_i
.p2align 8
.type _Z23InterpolateFromMemBlockPfS_S_S_i,@function
_Z23InterpolateFromMemBlockPfS_S_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_nle_f32_e64 s4, s6, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_mov_b32 s4, 0
s_cbranch_vccnz .LBB0_3
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_4
s_branch .LBB0_8
.LBB0_3:
.LBB0_4:
s_load_b64 s[4:5], s[0:1], 0x8
v_cmp_nge_f32_e64 s7, s6, 1.0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_6
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_cbranch_execz .LBB0_7
s_branch .LBB0_8
.LBB0_6:
.LBB0_7:
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
v_sub_f32_e64 v4, 1.0, s6
s_waitcnt vmcnt(1)
v_mul_f32_e32 v0, s6, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v0, v4, v3
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23InterpolateFromMemBlockPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23InterpolateFromMemBlockPfS_S_S_i, .Lfunc_end0-_Z23InterpolateFromMemBlockPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23InterpolateFromMemBlockPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23InterpolateFromMemBlockPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InterpolateFromMemBlock(float* input1, float* input2, float* output, float* weightMemBlock, int inputSize)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
if (weightMemBlock[0] <= 0)
{
output[threadId] = input1[threadId];
}
else if (weightMemBlock[0] >= 1)
{
output[threadId] = input2[threadId];
}
else
{
output[threadId] = (1 - weightMemBlock[0]) * input1[threadId] + weightMemBlock[0] * input2[threadId];
}
}
} | .text
.file "InterpolateFromMemBlock.hip"
.globl _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i # -- Begin function _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.p2align 4, 0x90
.type _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i,@function
_Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i: # @_Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23InterpolateFromMemBlockPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i, .Lfunc_end0-_Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23InterpolateFromMemBlockPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23InterpolateFromMemBlockPfS_S_S_i,@object # @_Z23InterpolateFromMemBlockPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z23InterpolateFromMemBlockPfS_S_S_i
.p2align 3, 0x0
_Z23InterpolateFromMemBlockPfS_S_S_i:
.quad _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.size _Z23InterpolateFromMemBlockPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23InterpolateFromMemBlockPfS_S_S_i"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23InterpolateFromMemBlockPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23InterpolateFromMemBlockPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fca0000000f00 */
/*00b0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fd20000011400 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0100*/ FSETP.GTU.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x004fda0003f0c000 */
/*0110*/ @P0 BRA 0x150 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0130*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ FSETP.GE.AND P0, PT, R8, 1, PT ; /* 0x3f8000000800780b */
/* 0x000fe40003f06000 */
/*0160*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078210ff */
/*0170*/ LEA.HI.X R3, R0, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fce00008f1409 */
/*0180*/ @!P0 BRA 0x1c0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee2000c1e1900 */
/*01e0*/ FADD R0, -R8, 1 ; /* 0x3f80000008007421 */
/* 0x000fc40000000100 */
/*01f0*/ FMUL R8, R8, R3 ; /* 0x0000000308087220 */
/* 0x004fc80000400000 */
/*0200*/ FFMA R9, R0, R5, R8 ; /* 0x0000000500097223 */
/* 0x008fca0000000008 */
/*0210*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23InterpolateFromMemBlockPfS_S_S_i
.globl _Z23InterpolateFromMemBlockPfS_S_S_i
.p2align 8
.type _Z23InterpolateFromMemBlockPfS_S_S_i,@function
_Z23InterpolateFromMemBlockPfS_S_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_nle_f32_e64 s4, s6, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_mov_b32 s4, 0
s_cbranch_vccnz .LBB0_3
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_4
s_branch .LBB0_8
.LBB0_3:
.LBB0_4:
s_load_b64 s[4:5], s[0:1], 0x8
v_cmp_nge_f32_e64 s7, s6, 1.0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_6
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_cbranch_execz .LBB0_7
s_branch .LBB0_8
.LBB0_6:
.LBB0_7:
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
v_sub_f32_e64 v4, 1.0, s6
s_waitcnt vmcnt(1)
v_mul_f32_e32 v0, s6, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v0, v4, v3
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23InterpolateFromMemBlockPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23InterpolateFromMemBlockPfS_S_S_i, .Lfunc_end0-_Z23InterpolateFromMemBlockPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23InterpolateFromMemBlockPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23InterpolateFromMemBlockPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011931b_00000000-6_InterpolateFromMemBlock.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i
.type _Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i, @function
_Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23InterpolateFromMemBlockPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i, .-_Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i
.globl _Z23InterpolateFromMemBlockPfS_S_S_i
.type _Z23InterpolateFromMemBlockPfS_S_S_i, @function
_Z23InterpolateFromMemBlockPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z23InterpolateFromMemBlockPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23InterpolateFromMemBlockPfS_S_S_i, .-_Z23InterpolateFromMemBlockPfS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23InterpolateFromMemBlockPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23InterpolateFromMemBlockPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "InterpolateFromMemBlock.hip"
.globl _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i # -- Begin function _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.p2align 4, 0x90
.type _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i,@function
_Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i: # @_Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23InterpolateFromMemBlockPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i, .Lfunc_end0-_Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23InterpolateFromMemBlockPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23InterpolateFromMemBlockPfS_S_S_i,@object # @_Z23InterpolateFromMemBlockPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z23InterpolateFromMemBlockPfS_S_S_i
.p2align 3, 0x0
_Z23InterpolateFromMemBlockPfS_S_S_i:
.quad _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.size _Z23InterpolateFromMemBlockPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23InterpolateFromMemBlockPfS_S_S_i"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__InterpolateFromMemBlockPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23InterpolateFromMemBlockPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
/**
* @brief color kernel 1
* @param row CSR pointer array
* @param col CSR column array
* @param node_value Vertex value array
* @param color_array Color value array
* @param stop Termination variable
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color1(int *row, int *col, int *node_value, int *color_array,
int *stop, int *max_d, const int color,
const int num_nodes, const int num_edges)
{
// Get my thread workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
// Get the start and end pointer of the neighbor list
int start = row[tid];
int end;
if (tid + 1 < num_nodes)
end = row[tid + 1];
else
end = num_edges;
int maximum = -1;
// Navigate the neighbor list
for (int edge = start; edge < end; edge++) {
// Determine if the vertex value is the maximum in the neighborhood
if (color_array[col[edge]] == -1 && start != end - 1) {
*stop = 1;
if (node_value[col[edge]] > maximum)
maximum = node_value[col[edge]];
}
}
// Assign maximum the max array
max_d[tid] = maximum;
}
}
}
/**
* @brief color kernel 2
* @param node_value Vertex value array
* @param color_array Color value array
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color2(int *node_value, int *color_array, int *max_d,
const int color, const int num_nodes,
const int num_edges)
{
// Get my workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
if (node_value[tid] >= max_d[tid])
// Assign a color
color_array[tid] = color;
}
}
} | code for sm_80
Function : _Z6color2PiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00d0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011400 */
/*00e0*/ IADD3 R4, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006047a10 */
/* 0x000fe40007f3e0ff */
/*00f0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*0100*/ IADD3 R6, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe40007f1e0ff */
/*0110*/ IADD3.X R5, R0.reuse, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000057a10 */
/* 0x040fe40000ffe4ff */
/*0120*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000077a10 */
/* 0x000fc600007fe4ff */
/*0130*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*0150*/ ISETP.GE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f06270 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff057624 */
/* 0x000fca00078e00ff */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6color1PiS_S_S_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x194], PT ; /* 0x0000650006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.SHL.U32 R0, R6, 0x4, RZ ; /* 0x0000000406007824 */
/* 0x000fe200078e00ff */
/*00e0*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff0b7624 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x194], PT ; /* 0x0000650002007a0c */
/* 0x000fe40003f06270 */
/*0110*/ SHF.L.U64.HI R6, R6, 0x2, R3 ; /* 0x0000000206067819 */
/* 0x000fe40000010203 */
/*0120*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*0130*/ IADD3.X R3, R6, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590006037a10 */
/* 0x000fca0000ffe4ff */
/*0140*/ @!P0 LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b8981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x740 ; /* 0x000005d000007945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, -0x1 ; /* 0xffffffffff0a7424 */
/* 0x000fe200078e00ff */
/*0180*/ ISETP.GT.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720c */
/* 0x004fda0003f04270 */
/*0190*/ @!P0 BRA 0x730 ; /* 0x0000059000008947 */
/* 0x000fea0003800000 */
/*01a0*/ LOP3.LUT R2, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff027212 */
/* 0x000fe200078e33ff */
/*01b0*/ IMAD.IADD R12, R11, 0x1, -R8.reuse ; /* 0x000000010b0c7824 */
/* 0x100fe200078e0a08 */
/*01c0*/ BSSY B1, 0x5e0 ; /* 0x0000041000017945 */
/* 0x000fe20003800000 */
/*01d0*/ IMAD.MOV.U32 R10, RZ, RZ, -0x1 ; /* 0xffffffffff0a7424 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3 R2, R2, R11, RZ ; /* 0x0000000b02027210 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0200*/ LOP3.LUT R9, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c097812 */
/* 0x000fe400078ec0ff */
/*0210*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0220*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc40003f05270 */
/*0230*/ IADD3 R11, R11, -0x1, RZ ; /* 0xffffffff0b0b7810 */
/* 0x000fd20007ffe0ff */
/*0240*/ @!P1 BRA 0x5d0 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.WIDE R2, R8.reuse, R7, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x040fe200078e0207 */
/*0260*/ ISETP.NE.AND P1, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x000fe40003f25270 */
/*0270*/ MOV R10, 0xffffffff ; /* 0xffffffff000a7802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*02a0*/ IMAD.IADD R12, R12, 0x1, -R9 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0a09 */
/*02b0*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fc400078e0008 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe400078e00ff */
/*02e0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.WIDE R16, R16, R7, c[0x0][0x178] ; /* 0x00005e0010107625 */
/* 0x004fcc00078e0207 */
/*0310*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*0320*/ ISETP.NE.OR P4, PT, R16, -0x1, !P1 ; /* 0xffffffff1000780c */
/* 0x004fda0004f85670 */
/*0330*/ @!P4 IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0fc424 */
/* 0x000fca00078e00ff */
/*0340*/ @!P4 STG.E [R2.64], R15 ; /* 0x0000000f0200c986 */
/* 0x0001e8000c101904 */
/*0350*/ LDG.E R20, [R4.64+0x4] ; /* 0x0000040404147981 */
/* 0x000ea8000c1e1900 */
/*0360*/ @!P4 LDG.E R18, [R4.64] ; /* 0x000000040412c981 */
/* 0x000ee2000c1e1900 */
/*0370*/ IMAD.WIDE R20, R20, R7, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x004fcc00078e0207 */
/*0380*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea2000c1e1900 */
/*0390*/ @!P4 IMAD.WIDE R18, R18, R7, c[0x0][0x170] ; /* 0x00005c001212c625 */
/* 0x008fca00078e0207 */
/*03a0*/ @!P4 LDG.E R13, [R18.64] ; /* 0x00000004120dc981 */
/* 0x0002e2000c1e1900 */
/*03b0*/ ISETP.NE.OR P5, PT, R20, -0x1, !P1 ; /* 0xffffffff1400780c */
/* 0x004fda0004fa5670 */
/*03c0*/ @!P5 MOV R25, 0x1 ; /* 0x000000010019d802 */
/* 0x000fca0000000f00 */
/*03d0*/ @!P5 STG.E [R2.64], R25 ; /* 0x000000190200d986 */
/* 0x0005e8000c101904 */
/*03e0*/ LDG.E R22, [R4.64+0x8] ; /* 0x0000080404167981 */
/* 0x000f28000c1e1900 */
/*03f0*/ @!P5 LDG.E R16, [R4.64+0x4] ; /* 0x000004040410d981 */
/* 0x000f62000c1e1900 */
/*0400*/ IMAD.WIDE R22, R22, R7, c[0x0][0x178] ; /* 0x00005e0016167625 */
/* 0x010fcc00078e0207 */
/*0410*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f22000c1e1900 */
/*0420*/ @!P5 IMAD.WIDE R16, R16, R7, c[0x0][0x170] ; /* 0x00005c001010d625 */
/* 0x020fca00078e0207 */
/*0430*/ @!P5 LDG.E R15, [R16.64] ; /* 0x00000004100fd981 */
/* 0x001162000c1e1900 */
/*0440*/ ISETP.NE.OR P3, PT, R22, -0x1, !P1 ; /* 0xffffffff1600780c */
/* 0x010fda0004f65670 */
/*0450*/ @!P3 IMAD.MOV.U32 R27, RZ, RZ, 0x1 ; /* 0x00000001ff1bb424 */
/* 0x000fca00078e00ff */
/*0460*/ @!P3 STG.E [R2.64], R27 ; /* 0x0000001b0200b986 */
/* 0x0005e8000c101904 */
/*0470*/ LDG.E R20, [R4.64+0xc] ; /* 0x00000c0404147981 */
/* 0x000f28000c1e1900 */
/*0480*/ @!P3 LDG.E R18, [R4.64+0x8] ; /* 0x000008040412b981 */
/* 0x002ea2000c1e1900 */
/*0490*/ IMAD.WIDE R20, R20, R7, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x010fcc00078e0207 */
/*04a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f22000c1e1900 */
/*04b0*/ @!P3 IMAD.WIDE R18, R18, R7, c[0x0][0x170] ; /* 0x00005c001212b625 */
/* 0x004fcc00078e0207 */
/*04c0*/ @!P3 LDG.E R19, [R18.64] ; /* 0x000000041213b981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ ISETP.NE.OR P2, PT, R20, -0x1, !P1 ; /* 0xffffffff1400780c */
/* 0x010fda0004f45670 */
/*04e0*/ @!P2 IMAD.MOV.U32 R23, RZ, RZ, 0x1 ; /* 0x00000001ff17a424 */
/* 0x000fca00078e00ff */
/*04f0*/ @!P2 STG.E [R2.64], R23 ; /* 0x000000170200a986 */
/* 0x0003e8000c101904 */
/*0500*/ @!P2 LDG.E R16, [R4.64+0xc] ; /* 0x00000c040410a981 */
/* 0x001f22000c1e1900 */
/*0510*/ @!P4 IMNMX R10, R10, R13, !PT ; /* 0x0000000d0a0ac217 */
/* 0x008fe40007800200 */
/*0520*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe40007ffe0ff */
/*0530*/ @!P5 IMNMX R10, R10, R15, !PT ; /* 0x0000000f0a0ad217 */
/* 0x020fe40007800200 */
/*0540*/ ISETP.NE.AND P5, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003fa5270 */
/*0550*/ @!P2 IMAD.WIDE R16, R16, R7, c[0x0][0x170] ; /* 0x00005c001010a625 */
/* 0x010fcc00078e0207 */
/*0560*/ @!P2 LDG.E R17, [R16.64] ; /* 0x000000041011a981 */
/* 0x000ee2000c1e1900 */
/*0570*/ IADD3 R4, P4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007f9e0ff */
/*0580*/ @!P3 IMNMX R10, R10, R19, !PT ; /* 0x000000130a0ab217 */
/* 0x004fe40007800200 */
/*0590*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x000fe200020e0605 */
/*05b0*/ @!P2 IMNMX R10, R10, R17, !PT ; /* 0x000000110a0aa217 */
/* 0x008fe20007800200 */
/*05c0*/ @P5 BRA 0x2e0 ; /* 0xfffffd1000005947 */
/* 0x002fea000383ffff */
/*05d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05e0*/ @!P0 BRA 0x730 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*05f0*/ IMAD.WIDE R2, R14, R7, c[0x0][0x168] ; /* 0x00005a000e027625 */
/* 0x000fca00078e0207 */
/*0600*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*0610*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.WIDE R4, R4, R13, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x004fcc00078e020d */
/*0630*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0640*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fc80003f05270 */
/*0650*/ ISETP.EQ.OR P0, PT, R8, R11, P0 ; /* 0x0000000b0800720c */
/* 0x000fda0000702670 */
/*0660*/ @!P0 MOV R7, 0x1 ; /* 0x0000000100078802 */
/* 0x000fe20000000f00 */
/*0670*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0e8624 */
/* 0x000fe400078e00ff */
/*0680*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff0f8624 */
/* 0x000fca00078e00ff */
/*0690*/ @!P0 STG.E [R14.64], R7 ; /* 0x000000070e008986 */
/* 0x0001e8000c101904 */
/*06a0*/ @!P0 LDG.E R12, [R2.64] ; /* 0x00000004020c8981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fc80007ffe0ff */
/*06c0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*06d0*/ @!P0 IMAD.WIDE R12, R12, R13, c[0x0][0x170] ; /* 0x00005c000c0c8625 */
/* 0x004fcc00078e020d */
/*06e0*/ @!P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d8981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fca0007f5e0ff */
/*0700*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0710*/ @!P0 IMNMX R10, R10, R13, !PT ; /* 0x0000000d0a0a8217 */
/* 0x004fe20007800200 */
/*0720*/ @P1 BRA 0x600 ; /* 0xfffffed000001947 */
/* 0x001fea000383ffff */
/*0730*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R2, P0, R0, c[0x0][0x188], RZ ; /* 0x0000620000027a10 */
/* 0x000fc80007f1e0ff */
/*0750*/ IADD3.X R3, R6, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630006037a10 */
/* 0x000fca00007fe4ff */
/*0760*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
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* may be used to endorse or promote products derived from this software *
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* those regulations, please refer to the U.S. Bureau of Industry and Security's *
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* *
\************************************************************************************/
/**
* @brief color kernel 1
* @param row CSR pointer array
* @param col CSR column array
* @param node_value Vertex value array
* @param color_array Color value array
* @param stop Termination variable
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color1(int *row, int *col, int *node_value, int *color_array,
int *stop, int *max_d, const int color,
const int num_nodes, const int num_edges)
{
// Get my thread workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
// Get the start and end pointer of the neighbor list
int start = row[tid];
int end;
if (tid + 1 < num_nodes)
end = row[tid + 1];
else
end = num_edges;
int maximum = -1;
// Navigate the neighbor list
for (int edge = start; edge < end; edge++) {
// Determine if the vertex value is the maximum in the neighborhood
if (color_array[col[edge]] == -1 && start != end - 1) {
*stop = 1;
if (node_value[col[edge]] > maximum)
maximum = node_value[col[edge]];
}
}
// Assign maximum the max array
max_d[tid] = maximum;
}
}
}
/**
* @brief color kernel 2
* @param node_value Vertex value array
* @param color_array Color value array
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color2(int *node_value, int *color_array, int *max_d,
const int color, const int num_nodes,
const int num_edges)
{
// Get my workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
if (node_value[tid] >= max_d[tid])
// Assign a color
color_array[tid] = color;
}
}
} | .file "tmpxft_000eee39_00000000-6_kernel_max.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii
.type _Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii, @function
_Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6color1PiS_S_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii, .-_Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii
.globl _Z6color1PiS_S_S_S_S_iii
.type _Z6color1PiS_S_S_S_S_iii, @function
_Z6color1PiS_S_S_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6color1PiS_S_S_S_S_iii, .-_Z6color1PiS_S_S_S_S_iii
.globl _Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii
.type _Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii, @function
_Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6color2PiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii, .-_Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii
.globl _Z6color2PiS_S_iii
.type _Z6color2PiS_S_iii, @function
_Z6color2PiS_S_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z6color2PiS_S_iii, .-_Z6color2PiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6color2PiS_S_iii"
.LC1:
.string "_Z6color1PiS_S_S_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6color2PiS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6color1PiS_S_S_S_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
/**
* @brief color kernel 1
* @param row CSR pointer array
* @param col CSR column array
* @param node_value Vertex value array
* @param color_array Color value array
* @param stop Termination variable
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color1(int *row, int *col, int *node_value, int *color_array,
int *stop, int *max_d, const int color,
const int num_nodes, const int num_edges)
{
// Get my thread workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
// Get the start and end pointer of the neighbor list
int start = row[tid];
int end;
if (tid + 1 < num_nodes)
end = row[tid + 1];
else
end = num_edges;
int maximum = -1;
// Navigate the neighbor list
for (int edge = start; edge < end; edge++) {
// Determine if the vertex value is the maximum in the neighborhood
if (color_array[col[edge]] == -1 && start != end - 1) {
*stop = 1;
if (node_value[col[edge]] > maximum)
maximum = node_value[col[edge]];
}
}
// Assign maximum the max array
max_d[tid] = maximum;
}
}
}
/**
* @brief color kernel 2
* @param node_value Vertex value array
* @param color_array Color value array
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color2(int *node_value, int *color_array, int *max_d,
const int color, const int num_nodes,
const int num_edges)
{
// Get my workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
if (node_value[tid] >= max_d[tid])
// Assign a color
color_array[tid] = color;
}
}
} | #include <hip/hip_runtime.h>
/************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
/**
* @brief color kernel 1
* @param row CSR pointer array
* @param col CSR column array
* @param node_value Vertex value array
* @param color_array Color value array
* @param stop Termination variable
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color1(int *row, int *col, int *node_value, int *color_array,
int *stop, int *max_d, const int color,
const int num_nodes, const int num_edges)
{
// Get my thread workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
// Get the start and end pointer of the neighbor list
int start = row[tid];
int end;
if (tid + 1 < num_nodes)
end = row[tid + 1];
else
end = num_edges;
int maximum = -1;
// Navigate the neighbor list
for (int edge = start; edge < end; edge++) {
// Determine if the vertex value is the maximum in the neighborhood
if (color_array[col[edge]] == -1 && start != end - 1) {
*stop = 1;
if (node_value[col[edge]] > maximum)
maximum = node_value[col[edge]];
}
}
// Assign maximum the max array
max_d[tid] = maximum;
}
}
}
/**
* @brief color kernel 2
* @param node_value Vertex value array
* @param color_array Color value array
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color2(int *node_value, int *color_array, int *max_d,
const int color, const int num_nodes,
const int num_edges)
{
// Get my workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
if (node_value[tid] >= max_d[tid])
// Assign a color
color_array[tid] = color;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
/**
* @brief color kernel 1
* @param row CSR pointer array
* @param col CSR column array
* @param node_value Vertex value array
* @param color_array Color value array
* @param stop Termination variable
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color1(int *row, int *col, int *node_value, int *color_array,
int *stop, int *max_d, const int color,
const int num_nodes, const int num_edges)
{
// Get my thread workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
// Get the start and end pointer of the neighbor list
int start = row[tid];
int end;
if (tid + 1 < num_nodes)
end = row[tid + 1];
else
end = num_edges;
int maximum = -1;
// Navigate the neighbor list
for (int edge = start; edge < end; edge++) {
// Determine if the vertex value is the maximum in the neighborhood
if (color_array[col[edge]] == -1 && start != end - 1) {
*stop = 1;
if (node_value[col[edge]] > maximum)
maximum = node_value[col[edge]];
}
}
// Assign maximum the max array
max_d[tid] = maximum;
}
}
}
/**
* @brief color kernel 2
* @param node_value Vertex value array
* @param color_array Color value array
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color2(int *node_value, int *color_array, int *max_d,
const int color, const int num_nodes,
const int num_edges)
{
// Get my workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
if (node_value[tid] >= max_d[tid])
// Assign a color
color_array[tid] = color;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6color1PiS_S_S_S_S_iii
.globl _Z6color1PiS_S_S_S_S_iii
.p2align 8
.type _Z6color1PiS_S_S_S_S_iii,@function
_Z6color1PiS_S_S_S_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s4, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_11
s_load_b64 s[8:9], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_mov_b32_e32 v0, s5
global_load_b32 v3, v[3:4], off
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v4
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v0, v[4:5], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v6, -1
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v0
s_cbranch_execz .LBB0_10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[10:11], s[0:1], 0x20
v_ashrrev_i32_e32 v4, 31, v3
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v8, -1, v0
v_mov_b32_e32 v6, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_cmp_eq_u32_e32 vcc_lo, v3, v8
v_mov_b32_e32 v8, 1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s2, s4, v4
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
s_mov_b32 s4, 0
s_xor_b32 s5, vcc_lo, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v4, s2, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s2, 0, v5, s2
v_cmp_ge_i32_e32 vcc_lo, v3, v0
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_9
.LBB0_7:
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v9
s_and_b32 s12, vcc_lo, s5
s_and_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_6
global_store_b32 v7, v8, s[10:11]
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_max_i32_e32 v6, v9, v6
s_branch .LBB0_6
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6color1PiS_S_S_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6color1PiS_S_S_S_S_iii, .Lfunc_end0-_Z6color1PiS_S_S_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6color2PiS_S_iii
.globl _Z6color2PiS_S_iii
.p2align 8
.type _Z6color2PiS_S_iii,@function
_Z6color2PiS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_4
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v4, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_4
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6color2PiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6color2PiS_S_iii, .Lfunc_end1-_Z6color2PiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6color1PiS_S_S_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6color1PiS_S_S_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6color2PiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6color2PiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR"�) (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
/**
* @brief color kernel 1
* @param row CSR pointer array
* @param col CSR column array
* @param node_value Vertex value array
* @param color_array Color value array
* @param stop Termination variable
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color1(int *row, int *col, int *node_value, int *color_array,
int *stop, int *max_d, const int color,
const int num_nodes, const int num_edges)
{
// Get my thread workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
// Get the start and end pointer of the neighbor list
int start = row[tid];
int end;
if (tid + 1 < num_nodes)
end = row[tid + 1];
else
end = num_edges;
int maximum = -1;
// Navigate the neighbor list
for (int edge = start; edge < end; edge++) {
// Determine if the vertex value is the maximum in the neighborhood
if (color_array[col[edge]] == -1 && start != end - 1) {
*stop = 1;
if (node_value[col[edge]] > maximum)
maximum = node_value[col[edge]];
}
}
// Assign maximum the max array
max_d[tid] = maximum;
}
}
}
/**
* @brief color kernel 2
* @param node_value Vertex value array
* @param color_array Color value array
* @param max_d Max array
* @param color Current color label
* @param num_nodes Number of vertices
* @param num_edges Number of edges
*/
__global__ void color2(int *node_value, int *color_array, int *max_d,
const int color, const int num_nodes,
const int num_edges)
{
// Get my workitem id
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_nodes) {
// If the vertex is still not colored
if (color_array[tid] == -1) {
if (node_value[tid] >= max_d[tid])
// Assign a color
color_array[tid] = color;
}
}
} | .text
.file "kernel_max.hip"
.globl _Z21__device_stub__color1PiS_S_S_S_S_iii # -- Begin function _Z21__device_stub__color1PiS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__color1PiS_S_S_S_S_iii,@function
_Z21__device_stub__color1PiS_S_S_S_S_iii: # @_Z21__device_stub__color1PiS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6color1PiS_S_S_S_S_iii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z21__device_stub__color1PiS_S_S_S_S_iii, .Lfunc_end0-_Z21__device_stub__color1PiS_S_S_S_S_iii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__color2PiS_S_iii # -- Begin function _Z21__device_stub__color2PiS_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__color2PiS_S_iii,@function
_Z21__device_stub__color2PiS_S_iii: # @_Z21__device_stub__color2PiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6color2PiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z21__device_stub__color2PiS_S_iii, .Lfunc_end1-_Z21__device_stub__color2PiS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6color1PiS_S_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6color2PiS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6color1PiS_S_S_S_S_iii,@object # @_Z6color1PiS_S_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z6color1PiS_S_S_S_S_iii
.p2align 3, 0x0
_Z6color1PiS_S_S_S_S_iii:
.quad _Z21__device_stub__color1PiS_S_S_S_S_iii
.size _Z6color1PiS_S_S_S_S_iii, 8
.type _Z6color2PiS_S_iii,@object # @_Z6color2PiS_S_iii
.globl _Z6color2PiS_S_iii
.p2align 3, 0x0
_Z6color2PiS_S_iii:
.quad _Z21__device_stub__color2PiS_S_iii
.size _Z6color2PiS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6color1PiS_S_S_S_S_iii"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6color2PiS_S_iii"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__color1PiS_S_S_S_S_iii
.addrsig_sym _Z21__device_stub__color2PiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6color1PiS_S_S_S_S_iii
.addrsig_sym _Z6color2PiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6color2PiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00d0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011400 */
/*00e0*/ IADD3 R4, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006047a10 */
/* 0x000fe40007f3e0ff */
/*00f0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*0100*/ IADD3 R6, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe40007f1e0ff */
/*0110*/ IADD3.X R5, R0.reuse, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000057a10 */
/* 0x040fe40000ffe4ff */
/*0120*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000077a10 */
/* 0x000fc600007fe4ff */
/*0130*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*0150*/ ISETP.GE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f06270 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff057624 */
/* 0x000fca00078e00ff */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6color1PiS_S_S_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x194], PT ; /* 0x0000650006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.SHL.U32 R0, R6, 0x4, RZ ; /* 0x0000000406007824 */
/* 0x000fe200078e00ff */
/*00e0*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff0b7624 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x194], PT ; /* 0x0000650002007a0c */
/* 0x000fe40003f06270 */
/*0110*/ SHF.L.U64.HI R6, R6, 0x2, R3 ; /* 0x0000000206067819 */
/* 0x000fe40000010203 */
/*0120*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*0130*/ IADD3.X R3, R6, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590006037a10 */
/* 0x000fca0000ffe4ff */
/*0140*/ @!P0 LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b8981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x740 ; /* 0x000005d000007945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, -0x1 ; /* 0xffffffffff0a7424 */
/* 0x000fe200078e00ff */
/*0180*/ ISETP.GT.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720c */
/* 0x004fda0003f04270 */
/*0190*/ @!P0 BRA 0x730 ; /* 0x0000059000008947 */
/* 0x000fea0003800000 */
/*01a0*/ LOP3.LUT R2, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff027212 */
/* 0x000fe200078e33ff */
/*01b0*/ IMAD.IADD R12, R11, 0x1, -R8.reuse ; /* 0x000000010b0c7824 */
/* 0x100fe200078e0a08 */
/*01c0*/ BSSY B1, 0x5e0 ; /* 0x0000041000017945 */
/* 0x000fe20003800000 */
/*01d0*/ IMAD.MOV.U32 R10, RZ, RZ, -0x1 ; /* 0xffffffffff0a7424 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3 R2, R2, R11, RZ ; /* 0x0000000b02027210 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0200*/ LOP3.LUT R9, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c097812 */
/* 0x000fe400078ec0ff */
/*0210*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0220*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc40003f05270 */
/*0230*/ IADD3 R11, R11, -0x1, RZ ; /* 0xffffffff0b0b7810 */
/* 0x000fd20007ffe0ff */
/*0240*/ @!P1 BRA 0x5d0 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.WIDE R2, R8.reuse, R7, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x040fe200078e0207 */
/*0260*/ ISETP.NE.AND P1, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x000fe40003f25270 */
/*0270*/ MOV R10, 0xffffffff ; /* 0xffffffff000a7802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*02a0*/ IMAD.IADD R12, R12, 0x1, -R9 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0a09 */
/*02b0*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fc400078e0008 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe400078e00ff */
/*02e0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.WIDE R16, R16, R7, c[0x0][0x178] ; /* 0x00005e0010107625 */
/* 0x004fcc00078e0207 */
/*0310*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*0320*/ ISETP.NE.OR P4, PT, R16, -0x1, !P1 ; /* 0xffffffff1000780c */
/* 0x004fda0004f85670 */
/*0330*/ @!P4 IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0fc424 */
/* 0x000fca00078e00ff */
/*0340*/ @!P4 STG.E [R2.64], R15 ; /* 0x0000000f0200c986 */
/* 0x0001e8000c101904 */
/*0350*/ LDG.E R20, [R4.64+0x4] ; /* 0x0000040404147981 */
/* 0x000ea8000c1e1900 */
/*0360*/ @!P4 LDG.E R18, [R4.64] ; /* 0x000000040412c981 */
/* 0x000ee2000c1e1900 */
/*0370*/ IMAD.WIDE R20, R20, R7, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x004fcc00078e0207 */
/*0380*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea2000c1e1900 */
/*0390*/ @!P4 IMAD.WIDE R18, R18, R7, c[0x0][0x170] ; /* 0x00005c001212c625 */
/* 0x008fca00078e0207 */
/*03a0*/ @!P4 LDG.E R13, [R18.64] ; /* 0x00000004120dc981 */
/* 0x0002e2000c1e1900 */
/*03b0*/ ISETP.NE.OR P5, PT, R20, -0x1, !P1 ; /* 0xffffffff1400780c */
/* 0x004fda0004fa5670 */
/*03c0*/ @!P5 MOV R25, 0x1 ; /* 0x000000010019d802 */
/* 0x000fca0000000f00 */
/*03d0*/ @!P5 STG.E [R2.64], R25 ; /* 0x000000190200d986 */
/* 0x0005e8000c101904 */
/*03e0*/ LDG.E R22, [R4.64+0x8] ; /* 0x0000080404167981 */
/* 0x000f28000c1e1900 */
/*03f0*/ @!P5 LDG.E R16, [R4.64+0x4] ; /* 0x000004040410d981 */
/* 0x000f62000c1e1900 */
/*0400*/ IMAD.WIDE R22, R22, R7, c[0x0][0x178] ; /* 0x00005e0016167625 */
/* 0x010fcc00078e0207 */
/*0410*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f22000c1e1900 */
/*0420*/ @!P5 IMAD.WIDE R16, R16, R7, c[0x0][0x170] ; /* 0x00005c001010d625 */
/* 0x020fca00078e0207 */
/*0430*/ @!P5 LDG.E R15, [R16.64] ; /* 0x00000004100fd981 */
/* 0x001162000c1e1900 */
/*0440*/ ISETP.NE.OR P3, PT, R22, -0x1, !P1 ; /* 0xffffffff1600780c */
/* 0x010fda0004f65670 */
/*0450*/ @!P3 IMAD.MOV.U32 R27, RZ, RZ, 0x1 ; /* 0x00000001ff1bb424 */
/* 0x000fca00078e00ff */
/*0460*/ @!P3 STG.E [R2.64], R27 ; /* 0x0000001b0200b986 */
/* 0x0005e8000c101904 */
/*0470*/ LDG.E R20, [R4.64+0xc] ; /* 0x00000c0404147981 */
/* 0x000f28000c1e1900 */
/*0480*/ @!P3 LDG.E R18, [R4.64+0x8] ; /* 0x000008040412b981 */
/* 0x002ea2000c1e1900 */
/*0490*/ IMAD.WIDE R20, R20, R7, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x010fcc00078e0207 */
/*04a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f22000c1e1900 */
/*04b0*/ @!P3 IMAD.WIDE R18, R18, R7, c[0x0][0x170] ; /* 0x00005c001212b625 */
/* 0x004fcc00078e0207 */
/*04c0*/ @!P3 LDG.E R19, [R18.64] ; /* 0x000000041213b981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ ISETP.NE.OR P2, PT, R20, -0x1, !P1 ; /* 0xffffffff1400780c */
/* 0x010fda0004f45670 */
/*04e0*/ @!P2 IMAD.MOV.U32 R23, RZ, RZ, 0x1 ; /* 0x00000001ff17a424 */
/* 0x000fca00078e00ff */
/*04f0*/ @!P2 STG.E [R2.64], R23 ; /* 0x000000170200a986 */
/* 0x0003e8000c101904 */
/*0500*/ @!P2 LDG.E R16, [R4.64+0xc] ; /* 0x00000c040410a981 */
/* 0x001f22000c1e1900 */
/*0510*/ @!P4 IMNMX R10, R10, R13, !PT ; /* 0x0000000d0a0ac217 */
/* 0x008fe40007800200 */
/*0520*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe40007ffe0ff */
/*0530*/ @!P5 IMNMX R10, R10, R15, !PT ; /* 0x0000000f0a0ad217 */
/* 0x020fe40007800200 */
/*0540*/ ISETP.NE.AND P5, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003fa5270 */
/*0550*/ @!P2 IMAD.WIDE R16, R16, R7, c[0x0][0x170] ; /* 0x00005c001010a625 */
/* 0x010fcc00078e0207 */
/*0560*/ @!P2 LDG.E R17, [R16.64] ; /* 0x000000041011a981 */
/* 0x000ee2000c1e1900 */
/*0570*/ IADD3 R4, P4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007f9e0ff */
/*0580*/ @!P3 IMNMX R10, R10, R19, !PT ; /* 0x000000130a0ab217 */
/* 0x004fe40007800200 */
/*0590*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x000fe200020e0605 */
/*05b0*/ @!P2 IMNMX R10, R10, R17, !PT ; /* 0x000000110a0aa217 */
/* 0x008fe20007800200 */
/*05c0*/ @P5 BRA 0x2e0 ; /* 0xfffffd1000005947 */
/* 0x002fea000383ffff */
/*05d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05e0*/ @!P0 BRA 0x730 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*05f0*/ IMAD.WIDE R2, R14, R7, c[0x0][0x168] ; /* 0x00005a000e027625 */
/* 0x000fca00078e0207 */
/*0600*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*0610*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.WIDE R4, R4, R13, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x004fcc00078e020d */
/*0630*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0640*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fc80003f05270 */
/*0650*/ ISETP.EQ.OR P0, PT, R8, R11, P0 ; /* 0x0000000b0800720c */
/* 0x000fda0000702670 */
/*0660*/ @!P0 MOV R7, 0x1 ; /* 0x0000000100078802 */
/* 0x000fe20000000f00 */
/*0670*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0e8624 */
/* 0x000fe400078e00ff */
/*0680*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff0f8624 */
/* 0x000fca00078e00ff */
/*0690*/ @!P0 STG.E [R14.64], R7 ; /* 0x000000070e008986 */
/* 0x0001e8000c101904 */
/*06a0*/ @!P0 LDG.E R12, [R2.64] ; /* 0x00000004020c8981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fc80007ffe0ff */
/*06c0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*06d0*/ @!P0 IMAD.WIDE R12, R12, R13, c[0x0][0x170] ; /* 0x00005c000c0c8625 */
/* 0x004fcc00078e020d */
/*06e0*/ @!P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d8981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fca0007f5e0ff */
/*0700*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0710*/ @!P0 IMNMX R10, R10, R13, !PT ; /* 0x0000000d0a0a8217 */
/* 0x004fe20007800200 */
/*0720*/ @P1 BRA 0x600 ; /* 0xfffffed000001947 */
/* 0x001fea000383ffff */
/*0730*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R2, P0, R0, c[0x0][0x188], RZ ; /* 0x0000620000027a10 */
/* 0x000fc80007f1e0ff */
/*0750*/ IADD3.X R3, R6, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630006037a10 */
/* 0x000fca00007fe4ff */
/*0760*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6color1PiS_S_S_S_S_iii
.globl _Z6color1PiS_S_S_S_S_iii
.p2align 8
.type _Z6color1PiS_S_S_S_S_iii,@function
_Z6color1PiS_S_S_S_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s4, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_11
s_load_b64 s[8:9], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_mov_b32_e32 v0, s5
global_load_b32 v3, v[3:4], off
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v4
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v0, v[4:5], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v6, -1
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v0
s_cbranch_execz .LBB0_10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[10:11], s[0:1], 0x20
v_ashrrev_i32_e32 v4, 31, v3
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v8, -1, v0
v_mov_b32_e32 v6, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_cmp_eq_u32_e32 vcc_lo, v3, v8
v_mov_b32_e32 v8, 1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s2, s4, v4
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
s_mov_b32 s4, 0
s_xor_b32 s5, vcc_lo, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v4, s2, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s2, 0, v5, s2
v_cmp_ge_i32_e32 vcc_lo, v3, v0
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_9
.LBB0_7:
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v9
s_and_b32 s12, vcc_lo, s5
s_and_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_6
global_store_b32 v7, v8, s[10:11]
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_max_i32_e32 v6, v9, v6
s_branch .LBB0_6
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6color1PiS_S_S_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6color1PiS_S_S_S_S_iii, .Lfunc_end0-_Z6color1PiS_S_S_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6color2PiS_S_iii
.globl _Z6color2PiS_S_iii
.p2align 8
.type _Z6color2PiS_S_iii,@function
_Z6color2PiS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_4
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v4, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_4
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6color2PiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6color2PiS_S_iii, .Lfunc_end1-_Z6color2PiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6color1PiS_S_S_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6color1PiS_S_S_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6color2PiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6color2PiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eee39_00000000-6_kernel_max.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii
.type _Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii, @function
_Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6color1PiS_S_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii, .-_Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii
.globl _Z6color1PiS_S_S_S_S_iii
.type _Z6color1PiS_S_S_S_S_iii, @function
_Z6color1PiS_S_S_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z38__device_stub__Z6color1PiS_S_S_S_S_iiiPiS_S_S_S_S_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6color1PiS_S_S_S_S_iii, .-_Z6color1PiS_S_S_S_S_iii
.globl _Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii
.type _Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii, @function
_Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6color2PiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii, .-_Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii
.globl _Z6color2PiS_S_iii
.type _Z6color2PiS_S_iii, @function
_Z6color2PiS_S_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6color2PiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z6color2PiS_S_iii, .-_Z6color2PiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6color2PiS_S_iii"
.LC1:
.string "_Z6color1PiS_S_S_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6color2PiS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6color1PiS_S_S_S_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_max.hip"
.globl _Z21__device_stub__color1PiS_S_S_S_S_iii # -- Begin function _Z21__device_stub__color1PiS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__color1PiS_S_S_S_S_iii,@function
_Z21__device_stub__color1PiS_S_S_S_S_iii: # @_Z21__device_stub__color1PiS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6color1PiS_S_S_S_S_iii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z21__device_stub__color1PiS_S_S_S_S_iii, .Lfunc_end0-_Z21__device_stub__color1PiS_S_S_S_S_iii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__color2PiS_S_iii # -- Begin function _Z21__device_stub__color2PiS_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__color2PiS_S_iii,@function
_Z21__device_stub__color2PiS_S_iii: # @_Z21__device_stub__color2PiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6color2PiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z21__device_stub__color2PiS_S_iii, .Lfunc_end1-_Z21__device_stub__color2PiS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6color1PiS_S_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6color2PiS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6color1PiS_S_S_S_S_iii,@object # @_Z6color1PiS_S_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z6color1PiS_S_S_S_S_iii
.p2align 3, 0x0
_Z6color1PiS_S_S_S_S_iii:
.quad _Z21__device_stub__color1PiS_S_S_S_S_iii
.size _Z6color1PiS_S_S_S_S_iii, 8
.type _Z6color2PiS_S_iii,@object # @_Z6color2PiS_S_iii
.globl _Z6color2PiS_S_iii
.p2align 3, 0x0
_Z6color2PiS_S_iii:
.quad _Z21__device_stub__color2PiS_S_iii
.size _Z6color2PiS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6color1PiS_S_S_S_S_iii"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6color2PiS_S_iii"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__color1PiS_S_S_S_S_iii
.addrsig_sym _Z21__device_stub__color2PiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6color1PiS_S_S_S_S_iii
.addrsig_sym _Z6color2PiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // CUDA programming
// Exercise n. 02
#include <errno.h>
#include <cuda.h>
#include <stdio.h>
#define BLOCKS 1
#define THREADS 1
// Prototype
__global__ void add(int *a, int *b, int *c);
int main(void)
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = sizeof(int);
// Setup input values
a = 5;
b = 9;
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
// Copy inputs to device
cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);
// Call the kernel on GPU
add<<< BLOCKS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
cudaMemcpy(&c, d_c, size, cudaMemcpyDeviceToHost);
// Cleanup
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return(EXIT_SUCCESS);
}
// Addition (on device)
__global__ void add(int *a, int *b, int *c)
{
*c = *a + *b;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // CUDA programming
// Exercise n. 02
#include <errno.h>
#include <cuda.h>
#include <stdio.h>
#define BLOCKS 1
#define THREADS 1
// Prototype
__global__ void add(int *a, int *b, int *c);
int main(void)
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = sizeof(int);
// Setup input values
a = 5;
b = 9;
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
// Copy inputs to device
cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);
// Call the kernel on GPU
add<<< BLOCKS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
cudaMemcpy(&c, d_c, size, cudaMemcpyDeviceToHost);
// Cleanup
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return(EXIT_SUCCESS);
}
// Addition (on device)
__global__ void add(int *a, int *b, int *c)
{
*c = *a + *b;
} | .file "tmpxft_00095d8d_00000000-6_ex02.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $5, (%rsp)
movl $9, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // CUDA programming
// Exercise n. 02
#include <errno.h>
#include <cuda.h>
#include <stdio.h>
#define BLOCKS 1
#define THREADS 1
// Prototype
__global__ void add(int *a, int *b, int *c);
int main(void)
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = sizeof(int);
// Setup input values
a = 5;
b = 9;
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
// Copy inputs to device
cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);
// Call the kernel on GPU
add<<< BLOCKS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
cudaMemcpy(&c, d_c, size, cudaMemcpyDeviceToHost);
// Cleanup
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return(EXIT_SUCCESS);
}
// Addition (on device)
__global__ void add(int *a, int *b, int *c)
{
*c = *a + *b;
} | // CUDA programming
// Exercise n. 02
#include <errno.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKS 1
#define THREADS 1
// Prototype
__global__ void add(int *a, int *b, int *c);
int main(void)
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = sizeof(int);
// Setup input values
a = 5;
b = 9;
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
// Copy inputs to device
hipMemcpy(d_a, &a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size, hipMemcpyHostToDevice);
// Call the kernel on GPU
add<<< BLOCKS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
hipMemcpy(&c, d_c, size, hipMemcpyDeviceToHost);
// Cleanup
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return(EXIT_SUCCESS);
}
// Addition (on device)
__global__ void add(int *a, int *b, int *c)
{
*c = *a + *b;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // CUDA programming
// Exercise n. 02
#include <errno.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKS 1
#define THREADS 1
// Prototype
__global__ void add(int *a, int *b, int *c);
int main(void)
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = sizeof(int);
// Setup input values
a = 5;
b = 9;
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
// Copy inputs to device
hipMemcpy(d_a, &a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size, hipMemcpyHostToDevice);
// Call the kernel on GPU
add<<< BLOCKS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
hipMemcpy(&c, d_c, size, hipMemcpyDeviceToHost);
// Cleanup
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return(EXIT_SUCCESS);
}
// Addition (on device)
__global__ void add(int *a, int *b, int *c)
{
*c = *a + *b;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // CUDA programming
// Exercise n. 02
#include <errno.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKS 1
#define THREADS 1
// Prototype
__global__ void add(int *a, int *b, int *c);
int main(void)
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = sizeof(int);
// Setup input values
a = 5;
b = 9;
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
// Copy inputs to device
hipMemcpy(d_a, &a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size, hipMemcpyHostToDevice);
// Call the kernel on GPU
add<<< BLOCKS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
hipMemcpy(&c, d_c, size, hipMemcpyDeviceToHost);
// Cleanup
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return(EXIT_SUCCESS);
}
// Addition (on device)
__global__ void add(int *a, int *b, int *c)
{
*c = *a + *b;
} | .text
.file "ex02.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl $5, 36(%rsp)
movl $9, 32(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 36(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end1-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00095d8d_00000000-6_ex02.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $5, (%rsp)
movl $9, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ex02.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl $5, 36(%rsp)
movl $9, 32(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 36(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end1-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <sys/time.h>
#include <stdlib.h>
#define N 1024
#define HEADER_SIZE (54)
#define LENGTH (3*N*N)
#define screenh N
#define screenw N
typedef unsigned char byte_t;
void BMPwrite(byte_t* bmp)
{
int i;
FILE *file;
file = fopen("cuda.bmp", "w+");
for(i = 0; i < LENGTH; i+=8)
{
putc(bmp[i], file);
putc(bmp[i+1], file);
putc(bmp[i+2], file);
putc(bmp[i+3], file);
putc(bmp[i+4], file);
putc(bmp[i+5], file);
putc(bmp[i+6], file);
putc(bmp[i+7], file);
}
fclose(file);
}
void BMPmake(byte_t* bitmap)
{
// bitmap signature
bitmap[0] = 'B';
bitmap[1] = 'M';
// file size
bitmap[2] = (HEADER_SIZE + LENGTH) & 0xFF; // 40 + 14 + 12
bitmap[3] = ((HEADER_SIZE + LENGTH) >> 8) & 0xFF;
bitmap[4] = ((HEADER_SIZE + LENGTH) >> 16) & 0xFF;
bitmap[5] = ((HEADER_SIZE + LENGTH) >> 24) & 0xFF;
// reserved field (in hex. 00 00 00 00)
int i;
for( i = 6; i < 10; i++) bitmap[i] = 0;
// offset of pixel data inside the image
bitmap[10]=54;
for( i = 11; i < 14; i++) bitmap[i] = 0;
// -- BITMAP HEADER -- //
// header size
bitmap[14] = 40;
for( i = 15; i < 18; i++) bitmap[i] = 0;
bitmap[18] = N & 0xFF;
bitmap[19] = (N >> 8) & 0xFF;
bitmap[20] = (N >> 16) & 0xFF;
bitmap[21] = (N >> 24) & 0xFF;
bitmap[22] = N & 0xFF;
bitmap[23] = (N >> 8) & 0xFF;
bitmap[24] = (N >> 16) & 0xFF;
bitmap[25] = (N >> 24) & 0xFF;
// reserved field
bitmap[26] = 1;
bitmap[27] = 0;
// number of bits per pixel
bitmap[28] = 24; // 3 byte
bitmap[29] = 0;
// compression method (no compression here)
for( i = 30; i < 34; i++) bitmap[i] = 0;
// size of pixel data
bitmap[34] = 255; // 12 bits => 4 pixels
bitmap[35] = 0;
bitmap[36] = 0;
bitmap[37] = 0;
// horizontal resolution of the image - pixels per meter (2835)
bitmap[38] = 0;
bitmap[39] = 0;
bitmap[40] = 48;
bitmap[41] = 177;
// vertical resolution of the image - pixels per meter (2835)
bitmap[42] = 0;
bitmap[43] = 0;
bitmap[44] = 48;
bitmap[45] = 177;
// color pallette information
for(i = 46; i < 50; i++) bitmap[i] = 0;
// number of important colors
for( i = 50; i < 54; i++) bitmap[i] = 0;
memset (bitmap + HEADER_SIZE, LENGTH, 0);
}
// should be consuming:
// - an array of chars, that will be the image
// - a FILE struct
// kernel forces every thread to color one character
// to the FILE object
__global__ void cudaColor (byte_t* bmp)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
bmp [3*(col + row * N)] = ((row & 0x20) ? 235 : 64);
// bmp [3*(col + row * N) + 1] = ((col & 0x20) ? 192 : 64);
// bmp [3*(col + row * N) + 2] = ((row & 0x80) || (col & 0x80) ? 192 : 64);
}
int main()
{
byte_t *bmp, *dev_bmp;
// mallocing space fo the bmp array, that has 3 N*N dimensions
bmp = (byte_t*)malloc ((HEADER_SIZE + LENGTH) * sizeof (byte_t));
BMPmake (bmp);
cudaError_t err;
err= cudaMalloc ((void**)&dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t));
printf("Cuda malloc bmp:%s \n", cudaGetErrorString(err));
err = cudaMemcpy (dev_bmp, bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
cudaMemcpyHostToDevice);
printf("Cuda memcpy to device bmp:%s \n", cudaGetErrorString(err));
// setting morphed dimensions
dim3 dimBlock (32, 32);
dim3 dimGrid (N / dimBlock.x, N / dimBlock.y);
struct timeval begin, end;
gettimeofday (&begin, NULL);
cudaColor <<< dimGrid, dimBlock >>> (dev_bmp + HEADER_SIZE);
err = cudaPeekAtLastError();
printf ("Cuda kernel:%s \n", cudaGetErrorString(err));
gettimeofday (&end, NULL);
err = cudaMemcpy (bmp, dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
cudaMemcpyDeviceToHost);
printf("Cuda memcpy to host bmp:%s \n", cudaGetErrorString(err));
BMPwrite(bmp);
int verify = 0,j;
for(j = 0; j < LENGTH; j++)
verify += (bmp [j + HEADER_SIZE] == 235);
printf ("Verify count: %d\n", verify);
if (verify == (N * N) / 2){
printf ("Verified!\n");
} else {
printf ("pixels not correct\n");
}
fprintf (stdout, "time = %lf\n", (end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec) * 1.0 / 1000000);
// copying from the device back to the host, time to read out the results
printf ("size of the image: %d\n", sizeof(bmp));
cudaFree(dev_bmp);
free(bmp);
return 0;
} | code for sm_80
Function : _Z9cudaColorPh
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc400078e0202 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x40 ; /* 0x00000040ff057424 */
/* 0x000fc600078e00ff */
/*0090*/ LEA R0, R3.reuse, R0, 0xa ; /* 0x0000000003007211 */
/* 0x040fe400078e50ff */
/*00a0*/ LOP3.LUT P0, RZ, R3, 0x20, RZ, 0xc0, !PT ; /* 0x0000002003ff7812 */
/* 0x000fc6000780c0ff */
/*00b0*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fe200078e02ff */
/*00c0*/ SEL R5, R5, 0xeb, !P0 ; /* 0x000000eb05057807 */
/* 0x000fc80004000000 */
/*00d0*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x000fca00008f0eff */
/*00f0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <sys/time.h>
#include <stdlib.h>
#define N 1024
#define HEADER_SIZE (54)
#define LENGTH (3*N*N)
#define screenh N
#define screenw N
typedef unsigned char byte_t;
void BMPwrite(byte_t* bmp)
{
int i;
FILE *file;
file = fopen("cuda.bmp", "w+");
for(i = 0; i < LENGTH; i+=8)
{
putc(bmp[i], file);
putc(bmp[i+1], file);
putc(bmp[i+2], file);
putc(bmp[i+3], file);
putc(bmp[i+4], file);
putc(bmp[i+5], file);
putc(bmp[i+6], file);
putc(bmp[i+7], file);
}
fclose(file);
}
void BMPmake(byte_t* bitmap)
{
// bitmap signature
bitmap[0] = 'B';
bitmap[1] = 'M';
// file size
bitmap[2] = (HEADER_SIZE + LENGTH) & 0xFF; // 40 + 14 + 12
bitmap[3] = ((HEADER_SIZE + LENGTH) >> 8) & 0xFF;
bitmap[4] = ((HEADER_SIZE + LENGTH) >> 16) & 0xFF;
bitmap[5] = ((HEADER_SIZE + LENGTH) >> 24) & 0xFF;
// reserved field (in hex. 00 00 00 00)
int i;
for( i = 6; i < 10; i++) bitmap[i] = 0;
// offset of pixel data inside the image
bitmap[10]=54;
for( i = 11; i < 14; i++) bitmap[i] = 0;
// -- BITMAP HEADER -- //
// header size
bitmap[14] = 40;
for( i = 15; i < 18; i++) bitmap[i] = 0;
bitmap[18] = N & 0xFF;
bitmap[19] = (N >> 8) & 0xFF;
bitmap[20] = (N >> 16) & 0xFF;
bitmap[21] = (N >> 24) & 0xFF;
bitmap[22] = N & 0xFF;
bitmap[23] = (N >> 8) & 0xFF;
bitmap[24] = (N >> 16) & 0xFF;
bitmap[25] = (N >> 24) & 0xFF;
// reserved field
bitmap[26] = 1;
bitmap[27] = 0;
// number of bits per pixel
bitmap[28] = 24; // 3 byte
bitmap[29] = 0;
// compression method (no compression here)
for( i = 30; i < 34; i++) bitmap[i] = 0;
// size of pixel data
bitmap[34] = 255; // 12 bits => 4 pixels
bitmap[35] = 0;
bitmap[36] = 0;
bitmap[37] = 0;
// horizontal resolution of the image - pixels per meter (2835)
bitmap[38] = 0;
bitmap[39] = 0;
bitmap[40] = 48;
bitmap[41] = 177;
// vertical resolution of the image - pixels per meter (2835)
bitmap[42] = 0;
bitmap[43] = 0;
bitmap[44] = 48;
bitmap[45] = 177;
// color pallette information
for(i = 46; i < 50; i++) bitmap[i] = 0;
// number of important colors
for( i = 50; i < 54; i++) bitmap[i] = 0;
memset (bitmap + HEADER_SIZE, LENGTH, 0);
}
// should be consuming:
// - an array of chars, that will be the image
// - a FILE struct
// kernel forces every thread to color one character
// to the FILE object
__global__ void cudaColor (byte_t* bmp)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
bmp [3*(col + row * N)] = ((row & 0x20) ? 235 : 64);
// bmp [3*(col + row * N) + 1] = ((col & 0x20) ? 192 : 64);
// bmp [3*(col + row * N) + 2] = ((row & 0x80) || (col & 0x80) ? 192 : 64);
}
int main()
{
byte_t *bmp, *dev_bmp;
// mallocing space fo the bmp array, that has 3 N*N dimensions
bmp = (byte_t*)malloc ((HEADER_SIZE + LENGTH) * sizeof (byte_t));
BMPmake (bmp);
cudaError_t err;
err= cudaMalloc ((void**)&dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t));
printf("Cuda malloc bmp:%s \n", cudaGetErrorString(err));
err = cudaMemcpy (dev_bmp, bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
cudaMemcpyHostToDevice);
printf("Cuda memcpy to device bmp:%s \n", cudaGetErrorString(err));
// setting morphed dimensions
dim3 dimBlock (32, 32);
dim3 dimGrid (N / dimBlock.x, N / dimBlock.y);
struct timeval begin, end;
gettimeofday (&begin, NULL);
cudaColor <<< dimGrid, dimBlock >>> (dev_bmp + HEADER_SIZE);
err = cudaPeekAtLastError();
printf ("Cuda kernel:%s \n", cudaGetErrorString(err));
gettimeofday (&end, NULL);
err = cudaMemcpy (bmp, dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
cudaMemcpyDeviceToHost);
printf("Cuda memcpy to host bmp:%s \n", cudaGetErrorString(err));
BMPwrite(bmp);
int verify = 0,j;
for(j = 0; j < LENGTH; j++)
verify += (bmp [j + HEADER_SIZE] == 235);
printf ("Verify count: %d\n", verify);
if (verify == (N * N) / 2){
printf ("Verified!\n");
} else {
printf ("pixels not correct\n");
}
fprintf (stdout, "time = %lf\n", (end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec) * 1.0 / 1000000);
// copying from the device back to the host, time to read out the results
printf ("size of the image: %d\n", sizeof(bmp));
cudaFree(dev_bmp);
free(bmp);
return 0;
} | .file "tmpxft_0004d314_00000000-6_bmp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w+"
.LC1:
.string "cuda.bmp"
.text
.globl _Z8BMPwritePh
.type _Z8BMPwritePh, @function
_Z8BMPwritePh:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %r12, %rbx
addq $3145728, %r12
.L4:
movzbl (%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 1(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 2(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 3(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 4(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 5(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 6(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 7(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L4
movq %rbp, %rdi
call fclose@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8BMPwritePh, .-_Z8BMPwritePh
.globl _Z7BMPmakePh
.type _Z7BMPmakePh, @function
_Z7BMPmakePh:
.LFB2058:
.cfi_startproc
endbr64
movb $66, (%rdi)
movb $77, 1(%rdi)
movb $54, 2(%rdi)
movb $0, 3(%rdi)
movb $48, 4(%rdi)
movb $0, 5(%rdi)
movb $0, 6(%rdi)
movb $0, 7(%rdi)
movb $0, 8(%rdi)
movb $0, 9(%rdi)
movb $54, 10(%rdi)
movb $0, 11(%rdi)
movb $0, 12(%rdi)
movb $0, 13(%rdi)
movb $40, 14(%rdi)
movb $0, 15(%rdi)
movb $0, 16(%rdi)
movb $0, 17(%rdi)
movb $0, 18(%rdi)
movb $4, 19(%rdi)
movb $0, 20(%rdi)
movb $0, 21(%rdi)
movb $0, 22(%rdi)
movb $4, 23(%rdi)
movb $0, 24(%rdi)
movb $0, 25(%rdi)
movb $1, 26(%rdi)
movb $0, 27(%rdi)
movb $24, 28(%rdi)
movb $0, 29(%rdi)
movb $0, 30(%rdi)
movb $0, 31(%rdi)
movb $0, 32(%rdi)
movb $0, 33(%rdi)
movb $-1, 34(%rdi)
movb $0, 35(%rdi)
movb $0, 36(%rdi)
movb $0, 37(%rdi)
movb $0, 38(%rdi)
movb $0, 39(%rdi)
movb $48, 40(%rdi)
movb $-79, 41(%rdi)
movb $0, 42(%rdi)
movb $0, 43(%rdi)
movb $48, 44(%rdi)
movb $-79, 45(%rdi)
movb $0, 46(%rdi)
movb $0, 47(%rdi)
movb $0, 48(%rdi)
movb $0, 49(%rdi)
movb $0, 50(%rdi)
movb $0, 51(%rdi)
movb $0, 52(%rdi)
movb $0, 53(%rdi)
ret
.cfi_endproc
.LFE2058:
.size _Z7BMPmakePh, .-_Z7BMPmakePh
.globl _Z28__device_stub__Z9cudaColorPhPh
.type _Z28__device_stub__Z9cudaColorPhPh, @function
_Z28__device_stub__Z9cudaColorPhPh:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9cudaColorPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z9cudaColorPhPh, .-_Z28__device_stub__Z9cudaColorPhPh
.globl _Z9cudaColorPh
.type _Z9cudaColorPh, @function
_Z9cudaColorPh:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9cudaColorPhPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9cudaColorPh, .-_Z9cudaColorPh
.section .rodata.str1.1
.LC2:
.string "Cuda malloc bmp:%s \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Cuda memcpy to device bmp:%s \n"
.section .rodata.str1.1
.LC4:
.string "Cuda kernel:%s \n"
.LC5:
.string "Cuda memcpy to host bmp:%s \n"
.LC6:
.string "Verify count: %d\n"
.LC7:
.string "Verified!\n"
.LC8:
.string "pixels not correct\n"
.LC10:
.string "time = %lf\n"
.LC11:
.string "size of the image: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $3145782, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, %rdi
call _Z7BMPmakePh
movq %rsp, %rdi
movl $3145782, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $3145782, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 16(%rsp)
movl $32, 20(%rsp)
movl $32, 24(%rsp)
movl $1, 28(%rsp)
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $32, 8(%rsp)
movl $32, 12(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L17:
call cudaPeekAtLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movl $3145782, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call _Z8BMPwritePh
leaq 54(%rbp), %rax
leaq 3145782(%rbp), %rcx
movl $0, %ebx
.L18:
cmpb $-21, (%rax)
sete %dl
movzbl %dl, %edx
addl %edx, %ebx
addq $1, %rax
cmpq %rcx, %rax
jne .L18
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $524288, %ebx
je .L25
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L20:
movq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $8, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq (%rsp), %rax
leaq 54(%rax), %rdi
call _Z28__device_stub__Z9cudaColorPhPh
jmp .L17
.L25:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9cudaColorPh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaColorPh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <sys/time.h>
#include <stdlib.h>
#define N 1024
#define HEADER_SIZE (54)
#define LENGTH (3*N*N)
#define screenh N
#define screenw N
typedef unsigned char byte_t;
void BMPwrite(byte_t* bmp)
{
int i;
FILE *file;
file = fopen("cuda.bmp", "w+");
for(i = 0; i < LENGTH; i+=8)
{
putc(bmp[i], file);
putc(bmp[i+1], file);
putc(bmp[i+2], file);
putc(bmp[i+3], file);
putc(bmp[i+4], file);
putc(bmp[i+5], file);
putc(bmp[i+6], file);
putc(bmp[i+7], file);
}
fclose(file);
}
void BMPmake(byte_t* bitmap)
{
// bitmap signature
bitmap[0] = 'B';
bitmap[1] = 'M';
// file size
bitmap[2] = (HEADER_SIZE + LENGTH) & 0xFF; // 40 + 14 + 12
bitmap[3] = ((HEADER_SIZE + LENGTH) >> 8) & 0xFF;
bitmap[4] = ((HEADER_SIZE + LENGTH) >> 16) & 0xFF;
bitmap[5] = ((HEADER_SIZE + LENGTH) >> 24) & 0xFF;
// reserved field (in hex. 00 00 00 00)
int i;
for( i = 6; i < 10; i++) bitmap[i] = 0;
// offset of pixel data inside the image
bitmap[10]=54;
for( i = 11; i < 14; i++) bitmap[i] = 0;
// -- BITMAP HEADER -- //
// header size
bitmap[14] = 40;
for( i = 15; i < 18; i++) bitmap[i] = 0;
bitmap[18] = N & 0xFF;
bitmap[19] = (N >> 8) & 0xFF;
bitmap[20] = (N >> 16) & 0xFF;
bitmap[21] = (N >> 24) & 0xFF;
bitmap[22] = N & 0xFF;
bitmap[23] = (N >> 8) & 0xFF;
bitmap[24] = (N >> 16) & 0xFF;
bitmap[25] = (N >> 24) & 0xFF;
// reserved field
bitmap[26] = 1;
bitmap[27] = 0;
// number of bits per pixel
bitmap[28] = 24; // 3 byte
bitmap[29] = 0;
// compression method (no compression here)
for( i = 30; i < 34; i++) bitmap[i] = 0;
// size of pixel data
bitmap[34] = 255; // 12 bits => 4 pixels
bitmap[35] = 0;
bitmap[36] = 0;
bitmap[37] = 0;
// horizontal resolution of the image - pixels per meter (2835)
bitmap[38] = 0;
bitmap[39] = 0;
bitmap[40] = 48;
bitmap[41] = 177;
// vertical resolution of the image - pixels per meter (2835)
bitmap[42] = 0;
bitmap[43] = 0;
bitmap[44] = 48;
bitmap[45] = 177;
// color pallette information
for(i = 46; i < 50; i++) bitmap[i] = 0;
// number of important colors
for( i = 50; i < 54; i++) bitmap[i] = 0;
memset (bitmap + HEADER_SIZE, LENGTH, 0);
}
// should be consuming:
// - an array of chars, that will be the image
// - a FILE struct
// kernel forces every thread to color one character
// to the FILE object
__global__ void cudaColor (byte_t* bmp)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
bmp [3*(col + row * N)] = ((row & 0x20) ? 235 : 64);
// bmp [3*(col + row * N) + 1] = ((col & 0x20) ? 192 : 64);
// bmp [3*(col + row * N) + 2] = ((row & 0x80) || (col & 0x80) ? 192 : 64);
}
int main()
{
byte_t *bmp, *dev_bmp;
// mallocing space fo the bmp array, that has 3 N*N dimensions
bmp = (byte_t*)malloc ((HEADER_SIZE + LENGTH) * sizeof (byte_t));
BMPmake (bmp);
cudaError_t err;
err= cudaMalloc ((void**)&dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t));
printf("Cuda malloc bmp:%s \n", cudaGetErrorString(err));
err = cudaMemcpy (dev_bmp, bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
cudaMemcpyHostToDevice);
printf("Cuda memcpy to device bmp:%s \n", cudaGetErrorString(err));
// setting morphed dimensions
dim3 dimBlock (32, 32);
dim3 dimGrid (N / dimBlock.x, N / dimBlock.y);
struct timeval begin, end;
gettimeofday (&begin, NULL);
cudaColor <<< dimGrid, dimBlock >>> (dev_bmp + HEADER_SIZE);
err = cudaPeekAtLastError();
printf ("Cuda kernel:%s \n", cudaGetErrorString(err));
gettimeofday (&end, NULL);
err = cudaMemcpy (bmp, dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
cudaMemcpyDeviceToHost);
printf("Cuda memcpy to host bmp:%s \n", cudaGetErrorString(err));
BMPwrite(bmp);
int verify = 0,j;
for(j = 0; j < LENGTH; j++)
verify += (bmp [j + HEADER_SIZE] == 235);
printf ("Verify count: %d\n", verify);
if (verify == (N * N) / 2){
printf ("Verified!\n");
} else {
printf ("pixels not correct\n");
}
fprintf (stdout, "time = %lf\n", (end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec) * 1.0 / 1000000);
// copying from the device back to the host, time to read out the results
printf ("size of the image: %d\n", sizeof(bmp));
cudaFree(dev_bmp);
free(bmp);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <sys/time.h>
#include <stdlib.h>
#define N 1024
#define HEADER_SIZE (54)
#define LENGTH (3*N*N)
#define screenh N
#define screenw N
typedef unsigned char byte_t;
void BMPwrite(byte_t* bmp)
{
int i;
FILE *file;
file = fopen("cuda.bmp", "w+");
for(i = 0; i < LENGTH; i+=8)
{
putc(bmp[i], file);
putc(bmp[i+1], file);
putc(bmp[i+2], file);
putc(bmp[i+3], file);
putc(bmp[i+4], file);
putc(bmp[i+5], file);
putc(bmp[i+6], file);
putc(bmp[i+7], file);
}
fclose(file);
}
void BMPmake(byte_t* bitmap)
{
// bitmap signature
bitmap[0] = 'B';
bitmap[1] = 'M';
// file size
bitmap[2] = (HEADER_SIZE + LENGTH) & 0xFF; // 40 + 14 + 12
bitmap[3] = ((HEADER_SIZE + LENGTH) >> 8) & 0xFF;
bitmap[4] = ((HEADER_SIZE + LENGTH) >> 16) & 0xFF;
bitmap[5] = ((HEADER_SIZE + LENGTH) >> 24) & 0xFF;
// reserved field (in hex. 00 00 00 00)
int i;
for( i = 6; i < 10; i++) bitmap[i] = 0;
// offset of pixel data inside the image
bitmap[10]=54;
for( i = 11; i < 14; i++) bitmap[i] = 0;
// -- BITMAP HEADER -- //
// header size
bitmap[14] = 40;
for( i = 15; i < 18; i++) bitmap[i] = 0;
bitmap[18] = N & 0xFF;
bitmap[19] = (N >> 8) & 0xFF;
bitmap[20] = (N >> 16) & 0xFF;
bitmap[21] = (N >> 24) & 0xFF;
bitmap[22] = N & 0xFF;
bitmap[23] = (N >> 8) & 0xFF;
bitmap[24] = (N >> 16) & 0xFF;
bitmap[25] = (N >> 24) & 0xFF;
// reserved field
bitmap[26] = 1;
bitmap[27] = 0;
// number of bits per pixel
bitmap[28] = 24; // 3 byte
bitmap[29] = 0;
// compression method (no compression here)
for( i = 30; i < 34; i++) bitmap[i] = 0;
// size of pixel data
bitmap[34] = 255; // 12 bits => 4 pixels
bitmap[35] = 0;
bitmap[36] = 0;
bitmap[37] = 0;
// horizontal resolution of the image - pixels per meter (2835)
bitmap[38] = 0;
bitmap[39] = 0;
bitmap[40] = 48;
bitmap[41] = 177;
// vertical resolution of the image - pixels per meter (2835)
bitmap[42] = 0;
bitmap[43] = 0;
bitmap[44] = 48;
bitmap[45] = 177;
// color pallette information
for(i = 46; i < 50; i++) bitmap[i] = 0;
// number of important colors
for( i = 50; i < 54; i++) bitmap[i] = 0;
memset (bitmap + HEADER_SIZE, LENGTH, 0);
}
// should be consuming:
// - an array of chars, that will be the image
// - a FILE struct
// kernel forces every thread to color one character
// to the FILE object
__global__ void cudaColor (byte_t* bmp)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
bmp [3*(col + row * N)] = ((row & 0x20) ? 235 : 64);
// bmp [3*(col + row * N) + 1] = ((col & 0x20) ? 192 : 64);
// bmp [3*(col + row * N) + 2] = ((row & 0x80) || (col & 0x80) ? 192 : 64);
}
int main()
{
byte_t *bmp, *dev_bmp;
// mallocing space fo the bmp array, that has 3 N*N dimensions
bmp = (byte_t*)malloc ((HEADER_SIZE + LENGTH) * sizeof (byte_t));
BMPmake (bmp);
hipError_t err;
err= hipMalloc ((void**)&dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t));
printf("Cuda malloc bmp:%s \n", hipGetErrorString(err));
err = hipMemcpy (dev_bmp, bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
hipMemcpyHostToDevice);
printf("Cuda memcpy to device bmp:%s \n", hipGetErrorString(err));
// setting morphed dimensions
dim3 dimBlock (32, 32);
dim3 dimGrid (N / dimBlock.x, N / dimBlock.y);
struct timeval begin, end;
gettimeofday (&begin, NULL);
cudaColor <<< dimGrid, dimBlock >>> (dev_bmp + HEADER_SIZE);
err = hipPeekAtLastError();
printf ("Cuda kernel:%s \n", hipGetErrorString(err));
gettimeofday (&end, NULL);
err = hipMemcpy (bmp, dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
hipMemcpyDeviceToHost);
printf("Cuda memcpy to host bmp:%s \n", hipGetErrorString(err));
BMPwrite(bmp);
int verify = 0,j;
for(j = 0; j < LENGTH; j++)
verify += (bmp [j + HEADER_SIZE] == 235);
printf ("Verify count: %d\n", verify);
if (verify == (N * N) / 2){
printf ("Verified!\n");
} else {
printf ("pixels not correct\n");
}
fprintf (stdout, "time = %lf\n", (end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec) * 1.0 / 1000000);
// copying from the device back to the host, time to read out the results
printf ("size of the image: %d\n", sizeof(bmp));
hipFree(dev_bmp);
free(bmp);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <sys/time.h>
#include <stdlib.h>
#define N 1024
#define HEADER_SIZE (54)
#define LENGTH (3*N*N)
#define screenh N
#define screenw N
typedef unsigned char byte_t;
void BMPwrite(byte_t* bmp)
{
int i;
FILE *file;
file = fopen("cuda.bmp", "w+");
for(i = 0; i < LENGTH; i+=8)
{
putc(bmp[i], file);
putc(bmp[i+1], file);
putc(bmp[i+2], file);
putc(bmp[i+3], file);
putc(bmp[i+4], file);
putc(bmp[i+5], file);
putc(bmp[i+6], file);
putc(bmp[i+7], file);
}
fclose(file);
}
void BMPmake(byte_t* bitmap)
{
// bitmap signature
bitmap[0] = 'B';
bitmap[1] = 'M';
// file size
bitmap[2] = (HEADER_SIZE + LENGTH) & 0xFF; // 40 + 14 + 12
bitmap[3] = ((HEADER_SIZE + LENGTH) >> 8) & 0xFF;
bitmap[4] = ((HEADER_SIZE + LENGTH) >> 16) & 0xFF;
bitmap[5] = ((HEADER_SIZE + LENGTH) >> 24) & 0xFF;
// reserved field (in hex. 00 00 00 00)
int i;
for( i = 6; i < 10; i++) bitmap[i] = 0;
// offset of pixel data inside the image
bitmap[10]=54;
for( i = 11; i < 14; i++) bitmap[i] = 0;
// -- BITMAP HEADER -- //
// header size
bitmap[14] = 40;
for( i = 15; i < 18; i++) bitmap[i] = 0;
bitmap[18] = N & 0xFF;
bitmap[19] = (N >> 8) & 0xFF;
bitmap[20] = (N >> 16) & 0xFF;
bitmap[21] = (N >> 24) & 0xFF;
bitmap[22] = N & 0xFF;
bitmap[23] = (N >> 8) & 0xFF;
bitmap[24] = (N >> 16) & 0xFF;
bitmap[25] = (N >> 24) & 0xFF;
// reserved field
bitmap[26] = 1;
bitmap[27] = 0;
// number of bits per pixel
bitmap[28] = 24; // 3 byte
bitmap[29] = 0;
// compression method (no compression here)
for( i = 30; i < 34; i++) bitmap[i] = 0;
// size of pixel data
bitmap[34] = 255; // 12 bits => 4 pixels
bitmap[35] = 0;
bitmap[36] = 0;
bitmap[37] = 0;
// horizontal resolution of the image - pixels per meter (2835)
bitmap[38] = 0;
bitmap[39] = 0;
bitmap[40] = 48;
bitmap[41] = 177;
// vertical resolution of the image - pixels per meter (2835)
bitmap[42] = 0;
bitmap[43] = 0;
bitmap[44] = 48;
bitmap[45] = 177;
// color pallette information
for(i = 46; i < 50; i++) bitmap[i] = 0;
// number of important colors
for( i = 50; i < 54; i++) bitmap[i] = 0;
memset (bitmap + HEADER_SIZE, LENGTH, 0);
}
// should be consuming:
// - an array of chars, that will be the image
// - a FILE struct
// kernel forces every thread to color one character
// to the FILE object
__global__ void cudaColor (byte_t* bmp)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
bmp [3*(col + row * N)] = ((row & 0x20) ? 235 : 64);
// bmp [3*(col + row * N) + 1] = ((col & 0x20) ? 192 : 64);
// bmp [3*(col + row * N) + 2] = ((row & 0x80) || (col & 0x80) ? 192 : 64);
}
int main()
{
byte_t *bmp, *dev_bmp;
// mallocing space fo the bmp array, that has 3 N*N dimensions
bmp = (byte_t*)malloc ((HEADER_SIZE + LENGTH) * sizeof (byte_t));
BMPmake (bmp);
hipError_t err;
err= hipMalloc ((void**)&dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t));
printf("Cuda malloc bmp:%s \n", hipGetErrorString(err));
err = hipMemcpy (dev_bmp, bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
hipMemcpyHostToDevice);
printf("Cuda memcpy to device bmp:%s \n", hipGetErrorString(err));
// setting morphed dimensions
dim3 dimBlock (32, 32);
dim3 dimGrid (N / dimBlock.x, N / dimBlock.y);
struct timeval begin, end;
gettimeofday (&begin, NULL);
cudaColor <<< dimGrid, dimBlock >>> (dev_bmp + HEADER_SIZE);
err = hipPeekAtLastError();
printf ("Cuda kernel:%s \n", hipGetErrorString(err));
gettimeofday (&end, NULL);
err = hipMemcpy (bmp, dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
hipMemcpyDeviceToHost);
printf("Cuda memcpy to host bmp:%s \n", hipGetErrorString(err));
BMPwrite(bmp);
int verify = 0,j;
for(j = 0; j < LENGTH; j++)
verify += (bmp [j + HEADER_SIZE] == 235);
printf ("Verify count: %d\n", verify);
if (verify == (N * N) / 2){
printf ("Verified!\n");
} else {
printf ("pixels not correct\n");
}
fprintf (stdout, "time = %lf\n", (end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec) * 1.0 / 1000000);
// copying from the device back to the host, time to read out the results
printf ("size of the image: %d\n", sizeof(bmp));
hipFree(dev_bmp);
free(bmp);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cudaColorPh
.globl _Z9cudaColorPh
.p2align 8
.type _Z9cudaColorPh,@function
_Z9cudaColorPh:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v1, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 10, v2
v_add3_u32 v0, s14, v0, v1
v_and_b32_e32 v1, 32, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, v0, 1, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v0
v_cndmask_b32_e64 v3, 0xffffffeb, 64, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b8 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cudaColorPh
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cudaColorPh, .Lfunc_end0-_Z9cudaColorPh
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cudaColorPh
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9cudaColorPh.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <sys/time.h>
#include <stdlib.h>
#define N 1024
#define HEADER_SIZE (54)
#define LENGTH (3*N*N)
#define screenh N
#define screenw N
typedef unsigned char byte_t;
void BMPwrite(byte_t* bmp)
{
int i;
FILE *file;
file = fopen("cuda.bmp", "w+");
for(i = 0; i < LENGTH; i+=8)
{
putc(bmp[i], file);
putc(bmp[i+1], file);
putc(bmp[i+2], file);
putc(bmp[i+3], file);
putc(bmp[i+4], file);
putc(bmp[i+5], file);
putc(bmp[i+6], file);
putc(bmp[i+7], file);
}
fclose(file);
}
void BMPmake(byte_t* bitmap)
{
// bitmap signature
bitmap[0] = 'B';
bitmap[1] = 'M';
// file size
bitmap[2] = (HEADER_SIZE + LENGTH) & 0xFF; // 40 + 14 + 12
bitmap[3] = ((HEADER_SIZE + LENGTH) >> 8) & 0xFF;
bitmap[4] = ((HEADER_SIZE + LENGTH) >> 16) & 0xFF;
bitmap[5] = ((HEADER_SIZE + LENGTH) >> 24) & 0xFF;
// reserved field (in hex. 00 00 00 00)
int i;
for( i = 6; i < 10; i++) bitmap[i] = 0;
// offset of pixel data inside the image
bitmap[10]=54;
for( i = 11; i < 14; i++) bitmap[i] = 0;
// -- BITMAP HEADER -- //
// header size
bitmap[14] = 40;
for( i = 15; i < 18; i++) bitmap[i] = 0;
bitmap[18] = N & 0xFF;
bitmap[19] = (N >> 8) & 0xFF;
bitmap[20] = (N >> 16) & 0xFF;
bitmap[21] = (N >> 24) & 0xFF;
bitmap[22] = N & 0xFF;
bitmap[23] = (N >> 8) & 0xFF;
bitmap[24] = (N >> 16) & 0xFF;
bitmap[25] = (N >> 24) & 0xFF;
// reserved field
bitmap[26] = 1;
bitmap[27] = 0;
// number of bits per pixel
bitmap[28] = 24; // 3 byte
bitmap[29] = 0;
// compression method (no compression here)
for( i = 30; i < 34; i++) bitmap[i] = 0;
// size of pixel data
bitmap[34] = 255; // 12 bits => 4 pixels
bitmap[35] = 0;
bitmap[36] = 0;
bitmap[37] = 0;
// horizontal resolution of the image - pixels per meter (2835)
bitmap[38] = 0;
bitmap[39] = 0;
bitmap[40] = 48;
bitmap[41] = 177;
// vertical resolution of the image - pixels per meter (2835)
bitmap[42] = 0;
bitmap[43] = 0;
bitmap[44] = 48;
bitmap[45] = 177;
// color pallette information
for(i = 46; i < 50; i++) bitmap[i] = 0;
// number of important colors
for( i = 50; i < 54; i++) bitmap[i] = 0;
memset (bitmap + HEADER_SIZE, LENGTH, 0);
}
// should be consuming:
// - an array of chars, that will be the image
// - a FILE struct
// kernel forces every thread to color one character
// to the FILE object
__global__ void cudaColor (byte_t* bmp)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
bmp [3*(col + row * N)] = ((row & 0x20) ? 235 : 64);
// bmp [3*(col + row * N) + 1] = ((col & 0x20) ? 192 : 64);
// bmp [3*(col + row * N) + 2] = ((row & 0x80) || (col & 0x80) ? 192 : 64);
}
int main()
{
byte_t *bmp, *dev_bmp;
// mallocing space fo the bmp array, that has 3 N*N dimensions
bmp = (byte_t*)malloc ((HEADER_SIZE + LENGTH) * sizeof (byte_t));
BMPmake (bmp);
hipError_t err;
err= hipMalloc ((void**)&dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t));
printf("Cuda malloc bmp:%s \n", hipGetErrorString(err));
err = hipMemcpy (dev_bmp, bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
hipMemcpyHostToDevice);
printf("Cuda memcpy to device bmp:%s \n", hipGetErrorString(err));
// setting morphed dimensions
dim3 dimBlock (32, 32);
dim3 dimGrid (N / dimBlock.x, N / dimBlock.y);
struct timeval begin, end;
gettimeofday (&begin, NULL);
cudaColor <<< dimGrid, dimBlock >>> (dev_bmp + HEADER_SIZE);
err = hipPeekAtLastError();
printf ("Cuda kernel:%s \n", hipGetErrorString(err));
gettimeofday (&end, NULL);
err = hipMemcpy (bmp, dev_bmp, (HEADER_SIZE + LENGTH) * sizeof (byte_t),
hipMemcpyDeviceToHost);
printf("Cuda memcpy to host bmp:%s \n", hipGetErrorString(err));
BMPwrite(bmp);
int verify = 0,j;
for(j = 0; j < LENGTH; j++)
verify += (bmp [j + HEADER_SIZE] == 235);
printf ("Verify count: %d\n", verify);
if (verify == (N * N) / 2){
printf ("Verified!\n");
} else {
printf ("pixels not correct\n");
}
fprintf (stdout, "time = %lf\n", (end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec) * 1.0 / 1000000);
// copying from the device back to the host, time to read out the results
printf ("size of the image: %d\n", sizeof(bmp));
hipFree(dev_bmp);
free(bmp);
return 0;
} | .text
.file "bmp.hip"
.globl _Z8BMPwritePh # -- Begin function _Z8BMPwritePh
.p2align 4, 0x90
.type _Z8BMPwritePh,@function
_Z8BMPwritePh: # @_Z8BMPwritePh
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
movq $-8, %r15
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movzbl 8(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 9(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 10(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 11(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 12(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 13(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 14(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 15(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
addq $8, %r15
cmpq $3145720, %r15 # imm = 0x2FFFF8
jb .LBB0_1
# %bb.2:
movq %r14, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z8BMPwritePh, .Lfunc_end0-_Z8BMPwritePh
.cfi_endproc
# -- End function
.globl _Z7BMPmakePh # -- Begin function _Z7BMPmakePh
.p2align 4, 0x90
.type _Z7BMPmakePh,@function
_Z7BMPmakePh: # @_Z7BMPmakePh
.cfi_startproc
# %bb.0: # %.preheader.preheader
movl $3558722, (%rdi) # imm = 0x364D42
movb $48, 4(%rdi)
movabsq $43980465124864, %rax # imm = 0x280000003600
movq %rax, 9(%rdi)
movl $0, 5(%rdi)
movb $0, 17(%rdi)
movabsq $4398046512128, %rax # imm = 0x40000000400
movq %rax, 18(%rdi)
movw $1, 26(%rdi)
movb $24, 28(%rdi)
movl $0, 29(%rdi)
movw $-256, 33(%rdi)
movb $0, 39(%rdi)
movl $0, 35(%rdi)
movl $45360, 40(%rdi) # imm = 0xB130
movw $-20176, 44(%rdi) # imm = 0xB130
movq $0, 46(%rdi)
retq
.Lfunc_end1:
.size _Z7BMPmakePh, .Lfunc_end1-_Z7BMPmakePh
.cfi_endproc
# -- End function
.globl _Z24__device_stub__cudaColorPh # -- Begin function _Z24__device_stub__cudaColorPh
.p2align 4, 0x90
.type _Z24__device_stub__cudaColorPh,@function
_Z24__device_stub__cudaColorPh: # @_Z24__device_stub__cudaColorPh
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9cudaColorPh, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z24__device_stub__cudaColorPh, .Lfunc_end2-_Z24__device_stub__cudaColorPh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $3145782, %edi # imm = 0x300036
callq malloc
movq %rax, %rbx
movl $3558722, (%rax) # imm = 0x364D42
movb $48, 4(%rax)
movl $0, 5(%rax)
movw $13824, 9(%rax) # imm = 0x3600
movq $671088640, 11(%rax) # imm = 0x28000000
movabsq $72057611217797124, %rax # imm = 0x100000400000004
movq %rax, 19(%rbx)
movw $6144, 27(%rbx) # imm = 0x1800
movl $0, 29(%rbx)
movw $-256, 33(%rbx)
movb $0, 39(%rbx)
movl $0, 35(%rbx)
movl $45360, 40(%rbx) # imm = 0xB130
movw $-20176, 44(%rbx) # imm = 0xB130
movq $0, 46(%rbx)
leaq 8(%rsp), %rdi
movl $3145782, %esi # imm = 0x300036
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
xorl %r14d, %r14d
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $3145782, %edx # imm = 0x300036
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
addq $54, %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 32(%rsp)
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z9cudaColorPh, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipPeekAtLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rsi
movl $3145782, %edx # imm = 0x300036
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq _Z8BMPwritePh
movl $54, %eax
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
xorl %ecx, %ecx
cmpb $-21, (%rbx,%rax)
sete %cl
addl %ecx, %r14d
incq %rax
cmpq $3145782, %rax # imm = 0x300036
jne .LBB3_3
# %bb.4:
movl $.L.str.6, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
cmpl $524288, %r14d # imm = 0x80000
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 88(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 96(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
movq stdout(%rip), %rdi
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.9, %esi
movb $1, %al
callq fprintf
movl $.L.str.10, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cudaColorPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cuda.bmp"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w+"
.size .L.str.1, 3
.type _Z9cudaColorPh,@object # @_Z9cudaColorPh
.section .rodata,"a",@progbits
.globl _Z9cudaColorPh
.p2align 3, 0x0
_Z9cudaColorPh:
.quad _Z24__device_stub__cudaColorPh
.size _Z9cudaColorPh, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Cuda malloc bmp:%s \n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda memcpy to device bmp:%s \n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cuda kernel:%s \n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cuda memcpy to host bmp:%s \n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Verify count: %d\n"
.size .L.str.6, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "time = %lf\n"
.size .L.str.9, 12
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "size of the image: %d\n"
.size .L.str.10, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9cudaColorPh"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "pixels not correct"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Verified!"
.size .Lstr.1, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cudaColorPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cudaColorPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9cudaColorPh
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc400078e0202 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x40 ; /* 0x00000040ff057424 */
/* 0x000fc600078e00ff */
/*0090*/ LEA R0, R3.reuse, R0, 0xa ; /* 0x0000000003007211 */
/* 0x040fe400078e50ff */
/*00a0*/ LOP3.LUT P0, RZ, R3, 0x20, RZ, 0xc0, !PT ; /* 0x0000002003ff7812 */
/* 0x000fc6000780c0ff */
/*00b0*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fe200078e02ff */
/*00c0*/ SEL R5, R5, 0xeb, !P0 ; /* 0x000000eb05057807 */
/* 0x000fc80004000000 */
/*00d0*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x000fca00008f0eff */
/*00f0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cudaColorPh
.globl _Z9cudaColorPh
.p2align 8
.type _Z9cudaColorPh,@function
_Z9cudaColorPh:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v1, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 10, v2
v_add3_u32 v0, s14, v0, v1
v_and_b32_e32 v1, 32, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, v0, 1, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v0
v_cndmask_b32_e64 v3, 0xffffffeb, 64, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b8 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cudaColorPh
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cudaColorPh, .Lfunc_end0-_Z9cudaColorPh
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cudaColorPh
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9cudaColorPh.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004d314_00000000-6_bmp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w+"
.LC1:
.string "cuda.bmp"
.text
.globl _Z8BMPwritePh
.type _Z8BMPwritePh, @function
_Z8BMPwritePh:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %r12, %rbx
addq $3145728, %r12
.L4:
movzbl (%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 1(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 2(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 3(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 4(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 5(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 6(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
movzbl 7(%rbx), %edi
movq %rbp, %rsi
call putc@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L4
movq %rbp, %rdi
call fclose@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8BMPwritePh, .-_Z8BMPwritePh
.globl _Z7BMPmakePh
.type _Z7BMPmakePh, @function
_Z7BMPmakePh:
.LFB2058:
.cfi_startproc
endbr64
movb $66, (%rdi)
movb $77, 1(%rdi)
movb $54, 2(%rdi)
movb $0, 3(%rdi)
movb $48, 4(%rdi)
movb $0, 5(%rdi)
movb $0, 6(%rdi)
movb $0, 7(%rdi)
movb $0, 8(%rdi)
movb $0, 9(%rdi)
movb $54, 10(%rdi)
movb $0, 11(%rdi)
movb $0, 12(%rdi)
movb $0, 13(%rdi)
movb $40, 14(%rdi)
movb $0, 15(%rdi)
movb $0, 16(%rdi)
movb $0, 17(%rdi)
movb $0, 18(%rdi)
movb $4, 19(%rdi)
movb $0, 20(%rdi)
movb $0, 21(%rdi)
movb $0, 22(%rdi)
movb $4, 23(%rdi)
movb $0, 24(%rdi)
movb $0, 25(%rdi)
movb $1, 26(%rdi)
movb $0, 27(%rdi)
movb $24, 28(%rdi)
movb $0, 29(%rdi)
movb $0, 30(%rdi)
movb $0, 31(%rdi)
movb $0, 32(%rdi)
movb $0, 33(%rdi)
movb $-1, 34(%rdi)
movb $0, 35(%rdi)
movb $0, 36(%rdi)
movb $0, 37(%rdi)
movb $0, 38(%rdi)
movb $0, 39(%rdi)
movb $48, 40(%rdi)
movb $-79, 41(%rdi)
movb $0, 42(%rdi)
movb $0, 43(%rdi)
movb $48, 44(%rdi)
movb $-79, 45(%rdi)
movb $0, 46(%rdi)
movb $0, 47(%rdi)
movb $0, 48(%rdi)
movb $0, 49(%rdi)
movb $0, 50(%rdi)
movb $0, 51(%rdi)
movb $0, 52(%rdi)
movb $0, 53(%rdi)
ret
.cfi_endproc
.LFE2058:
.size _Z7BMPmakePh, .-_Z7BMPmakePh
.globl _Z28__device_stub__Z9cudaColorPhPh
.type _Z28__device_stub__Z9cudaColorPhPh, @function
_Z28__device_stub__Z9cudaColorPhPh:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9cudaColorPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z9cudaColorPhPh, .-_Z28__device_stub__Z9cudaColorPhPh
.globl _Z9cudaColorPh
.type _Z9cudaColorPh, @function
_Z9cudaColorPh:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9cudaColorPhPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9cudaColorPh, .-_Z9cudaColorPh
.section .rodata.str1.1
.LC2:
.string "Cuda malloc bmp:%s \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Cuda memcpy to device bmp:%s \n"
.section .rodata.str1.1
.LC4:
.string "Cuda kernel:%s \n"
.LC5:
.string "Cuda memcpy to host bmp:%s \n"
.LC6:
.string "Verify count: %d\n"
.LC7:
.string "Verified!\n"
.LC8:
.string "pixels not correct\n"
.LC10:
.string "time = %lf\n"
.LC11:
.string "size of the image: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $3145782, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, %rdi
call _Z7BMPmakePh
movq %rsp, %rdi
movl $3145782, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $3145782, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 16(%rsp)
movl $32, 20(%rsp)
movl $32, 24(%rsp)
movl $1, 28(%rsp)
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $32, 8(%rsp)
movl $32, 12(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L17:
call cudaPeekAtLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movl $3145782, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call _Z8BMPwritePh
leaq 54(%rbp), %rax
leaq 3145782(%rbp), %rcx
movl $0, %ebx
.L18:
cmpb $-21, (%rax)
sete %dl
movzbl %dl, %edx
addl %edx, %ebx
addq $1, %rax
cmpq %rcx, %rax
jne .L18
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $524288, %ebx
je .L25
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L20:
movq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $8, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq (%rsp), %rax
leaq 54(%rax), %rdi
call _Z28__device_stub__Z9cudaColorPhPh
jmp .L17
.L25:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9cudaColorPh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaColorPh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bmp.hip"
.globl _Z8BMPwritePh # -- Begin function _Z8BMPwritePh
.p2align 4, 0x90
.type _Z8BMPwritePh,@function
_Z8BMPwritePh: # @_Z8BMPwritePh
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
movq $-8, %r15
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movzbl 8(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 9(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 10(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 11(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 12(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 13(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 14(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
movzbl 15(%rbx,%r15), %edi
movq %r14, %rsi
callq putc
addq $8, %r15
cmpq $3145720, %r15 # imm = 0x2FFFF8
jb .LBB0_1
# %bb.2:
movq %r14, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z8BMPwritePh, .Lfunc_end0-_Z8BMPwritePh
.cfi_endproc
# -- End function
.globl _Z7BMPmakePh # -- Begin function _Z7BMPmakePh
.p2align 4, 0x90
.type _Z7BMPmakePh,@function
_Z7BMPmakePh: # @_Z7BMPmakePh
.cfi_startproc
# %bb.0: # %.preheader.preheader
movl $3558722, (%rdi) # imm = 0x364D42
movb $48, 4(%rdi)
movabsq $43980465124864, %rax # imm = 0x280000003600
movq %rax, 9(%rdi)
movl $0, 5(%rdi)
movb $0, 17(%rdi)
movabsq $4398046512128, %rax # imm = 0x40000000400
movq %rax, 18(%rdi)
movw $1, 26(%rdi)
movb $24, 28(%rdi)
movl $0, 29(%rdi)
movw $-256, 33(%rdi)
movb $0, 39(%rdi)
movl $0, 35(%rdi)
movl $45360, 40(%rdi) # imm = 0xB130
movw $-20176, 44(%rdi) # imm = 0xB130
movq $0, 46(%rdi)
retq
.Lfunc_end1:
.size _Z7BMPmakePh, .Lfunc_end1-_Z7BMPmakePh
.cfi_endproc
# -- End function
.globl _Z24__device_stub__cudaColorPh # -- Begin function _Z24__device_stub__cudaColorPh
.p2align 4, 0x90
.type _Z24__device_stub__cudaColorPh,@function
_Z24__device_stub__cudaColorPh: # @_Z24__device_stub__cudaColorPh
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9cudaColorPh, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z24__device_stub__cudaColorPh, .Lfunc_end2-_Z24__device_stub__cudaColorPh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $3145782, %edi # imm = 0x300036
callq malloc
movq %rax, %rbx
movl $3558722, (%rax) # imm = 0x364D42
movb $48, 4(%rax)
movl $0, 5(%rax)
movw $13824, 9(%rax) # imm = 0x3600
movq $671088640, 11(%rax) # imm = 0x28000000
movabsq $72057611217797124, %rax # imm = 0x100000400000004
movq %rax, 19(%rbx)
movw $6144, 27(%rbx) # imm = 0x1800
movl $0, 29(%rbx)
movw $-256, 33(%rbx)
movb $0, 39(%rbx)
movl $0, 35(%rbx)
movl $45360, 40(%rbx) # imm = 0xB130
movw $-20176, 44(%rbx) # imm = 0xB130
movq $0, 46(%rbx)
leaq 8(%rsp), %rdi
movl $3145782, %esi # imm = 0x300036
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
xorl %r14d, %r14d
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $3145782, %edx # imm = 0x300036
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
addq $54, %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 32(%rsp)
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z9cudaColorPh, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipPeekAtLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rsi
movl $3145782, %edx # imm = 0x300036
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq _Z8BMPwritePh
movl $54, %eax
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
xorl %ecx, %ecx
cmpb $-21, (%rbx,%rax)
sete %cl
addl %ecx, %r14d
incq %rax
cmpq $3145782, %rax # imm = 0x300036
jne .LBB3_3
# %bb.4:
movl $.L.str.6, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
cmpl $524288, %r14d # imm = 0x80000
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 88(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 96(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
movq stdout(%rip), %rdi
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.9, %esi
movb $1, %al
callq fprintf
movl $.L.str.10, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cudaColorPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cuda.bmp"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w+"
.size .L.str.1, 3
.type _Z9cudaColorPh,@object # @_Z9cudaColorPh
.section .rodata,"a",@progbits
.globl _Z9cudaColorPh
.p2align 3, 0x0
_Z9cudaColorPh:
.quad _Z24__device_stub__cudaColorPh
.size _Z9cudaColorPh, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Cuda malloc bmp:%s \n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda memcpy to device bmp:%s \n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cuda kernel:%s \n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cuda memcpy to host bmp:%s \n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Verify count: %d\n"
.size .L.str.6, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "time = %lf\n"
.size .L.str.9, 12
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "size of the image: %d\n"
.size .L.str.10, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9cudaColorPh"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "pixels not correct"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Verified!"
.size .Lstr.1, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cudaColorPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cudaColorPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <stdio.h>
#include <chrono>
const int N = 16384;
const int blocksize1d = 64;
__global__
void threadnumber(float *c)
{
c[threadIdx.x] = threadIdx.x;
}
__global__
void squareroot(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
__global__
void add_matrix(float *a, float *b, float *result)
{
int row = (blockIdx.y * blockDim.y + threadIdx.y);
int col = (blockIdx.x * blockDim.x + threadIdx.x);
int e_per_row = (gridDim.x*blockDim.x);
int idx = row*e_per_row + col;
result[idx] = a[idx] + b[idx];
}
void cpu_add_matrix(float *a, float *b, float *result){
for (int i = 0; i < N*N; ++i)
result[i] = a[i] + b[i];
}
int main()
{
/* First part, 1D */
float *c = new float[N];
float *cd;
const int size = N*sizeof(float);
for(int i=0; i<N; ++i){
c[i] = 25.0f;
}
cudaMalloc( (void**)&cd, size );
dim3 dimBlock1d( N, 1 );
dim3 dimGrid( 1, 1 );
cudaMemcpy( cd, c, size, cudaMemcpyHostToDevice );
squareroot<<<dimGrid, dimBlock1d>>>(cd);
cudaThreadSynchronize();
cudaMemcpy( c, cd, size, cudaMemcpyDeviceToHost );
/*printf("Square root: \n");
for (int i = 0; i < N; i++)
printf("%f ", c[i]);
printf("\n");
*/
/* Second part, matrix and cuda event*/
float *gpu_result, *gpu_ma, *gpu_mb;
float *result = new float[N*N];
float *cpuresult = new float[N*N];
float *ma = new float[N*N];
float *mb = new float[N*N];
const int matrixsize = N*N*sizeof(float);
for(int i=0; i<N*N; ++i){
ma[i] = (float)i;
mb[i] = (float)i;
}
cudaEvent_t startEvent, endEvent;
//Allocate and send matrices to GPU
cudaMalloc( (void**)&gpu_result, matrixsize );
cudaMalloc( (void**)&gpu_ma, matrixsize );
cudaMalloc( (void**)&gpu_mb, matrixsize );
dim3 dimBlockmatrix( blocksize1d, blocksize1d );
dim3 dimGridmatrix( N/blocksize1d, N/blocksize1d );
cudaMemcpy( gpu_ma, ma, matrixsize, cudaMemcpyHostToDevice );
cudaMemcpy( gpu_mb, mb, matrixsize, cudaMemcpyHostToDevice );
//Time start
cudaEventCreate(&startEvent);
cudaEventRecord(startEvent, 0);
cudaEventSynchronize(startEvent);
//Computation
add_matrix<<<dimGridmatrix, dimBlockmatrix>>>(gpu_ma, gpu_mb, gpu_result);
cudaThreadSynchronize();
//Time end
cudaEventCreate(&endEvent);
cudaEventRecord(endEvent, 0);
cudaEventSynchronize(endEvent);
//Get result from GPU
cudaMemcpy( result, gpu_result, matrixsize, cudaMemcpyDeviceToHost );
float gpuTime = 0.0f;
cudaEventElapsedTime(&gpuTime, startEvent, endEvent);
/*printf("Matrix addition: \n");
for (int r = 0; r < N; r++){
for (int c = 0; c < N; c++)
printf("%f ", result[r*N + c]);
printf("\n");
}*/
//CPU equivalent
auto cpustart = std::chrono::system_clock::now();
cpu_add_matrix(ma, mb, cpuresult);
auto cpuend = std::chrono::system_clock::now();
std::chrono::duration<double> cpuTime = cpuend-cpustart;
printf("\nMatrix: %ix%i \nBlocksize: %ix%i \n", N, N, blocksize1d, blocksize1d);
printf("GPU compute time: %f \n", gpuTime);
printf("CPU compute time: %f \n", cpuTime.count());
cudaFree( cd );
cudaFree( gpu_ma );
cudaFree( gpu_mb );
cudaFree( gpu_result );
printf("done\n");
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z10add_matrixPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0209 */
/*00f0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10squarerootPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ BSSY B0, 0x140 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0070*/ IADD3 R4, R0, -0xd000000, RZ ; /* 0xf300000000047810 */
/* 0x004fe20007ffe0ff */
/*0080*/ MUFU.RSQ R5, R0 ; /* 0x0000000000057308 */
/* 0x0000660000001400 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*00a0*/ @!P0 BRA 0xf0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R9, 0xd0 ; /* 0x000000d000097802 */
/* 0x003fe40000000f00 */
/*00c0*/ CALL.REL.NOINC 0x160 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*00d0*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fe20000000f00 */
/*00e0*/ BRA 0x130 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*00f0*/ FMUL.FTZ R7, R0, R5 ; /* 0x0000000500077220 */
/* 0x003fe40000410000 */
/*0100*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0110*/ FFMA R0, -R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x000fc80000000100 */
/*0120*/ FFMA R5, R0, R5, R7 ; /* 0x0000000500057223 */
/* 0x000fe40000000007 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*0170*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*0180*/ @!P0 BRA 0x290 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0190*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*01a0*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*01b0*/ @!P0 BRA 0x290 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*01c0*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*01d0*/ @P0 FADD.FTZ R4, R0, 1 ; /* 0x3f80000000040421 */
/* 0x000fe20000010000 */
/*01e0*/ @P0 BRA 0x290 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*01f0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*0200*/ @P0 FFMA R5, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000050823 */
/* 0x000fc800000000ff */
/*0210*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0220*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*0230*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe20000410000 */
/*0240*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*0250*/ @P0 FADD.FTZ R7, -R6, -RZ ; /* 0x800000ff06070221 */
/* 0x000fc80000010100 */
/*0260*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*0270*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*0280*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*0290*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*02a0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*02b0*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fc80000000f00 */
/*02c0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffd3004007950 */
/* 0x000fea0003c3ffff */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12threadnumberPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x001e300000201000 */
/*0050*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <stdio.h>
#include <chrono>
const int N = 16384;
const int blocksize1d = 64;
__global__
void threadnumber(float *c)
{
c[threadIdx.x] = threadIdx.x;
}
__global__
void squareroot(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
__global__
void add_matrix(float *a, float *b, float *result)
{
int row = (blockIdx.y * blockDim.y + threadIdx.y);
int col = (blockIdx.x * blockDim.x + threadIdx.x);
int e_per_row = (gridDim.x*blockDim.x);
int idx = row*e_per_row + col;
result[idx] = a[idx] + b[idx];
}
void cpu_add_matrix(float *a, float *b, float *result){
for (int i = 0; i < N*N; ++i)
result[i] = a[i] + b[i];
}
int main()
{
/* First part, 1D */
float *c = new float[N];
float *cd;
const int size = N*sizeof(float);
for(int i=0; i<N; ++i){
c[i] = 25.0f;
}
cudaMalloc( (void**)&cd, size );
dim3 dimBlock1d( N, 1 );
dim3 dimGrid( 1, 1 );
cudaMemcpy( cd, c, size, cudaMemcpyHostToDevice );
squareroot<<<dimGrid, dimBlock1d>>>(cd);
cudaThreadSynchronize();
cudaMemcpy( c, cd, size, cudaMemcpyDeviceToHost );
/*printf("Square root: \n");
for (int i = 0; i < N; i++)
printf("%f ", c[i]);
printf("\n");
*/
/* Second part, matrix and cuda event*/
float *gpu_result, *gpu_ma, *gpu_mb;
float *result = new float[N*N];
float *cpuresult = new float[N*N];
float *ma = new float[N*N];
float *mb = new float[N*N];
const int matrixsize = N*N*sizeof(float);
for(int i=0; i<N*N; ++i){
ma[i] = (float)i;
mb[i] = (float)i;
}
cudaEvent_t startEvent, endEvent;
//Allocate and send matrices to GPU
cudaMalloc( (void**)&gpu_result, matrixsize );
cudaMalloc( (void**)&gpu_ma, matrixsize );
cudaMalloc( (void**)&gpu_mb, matrixsize );
dim3 dimBlockmatrix( blocksize1d, blocksize1d );
dim3 dimGridmatrix( N/blocksize1d, N/blocksize1d );
cudaMemcpy( gpu_ma, ma, matrixsize, cudaMemcpyHostToDevice );
cudaMemcpy( gpu_mb, mb, matrixsize, cudaMemcpyHostToDevice );
//Time start
cudaEventCreate(&startEvent);
cudaEventRecord(startEvent, 0);
cudaEventSynchronize(startEvent);
//Computation
add_matrix<<<dimGridmatrix, dimBlockmatrix>>>(gpu_ma, gpu_mb, gpu_result);
cudaThreadSynchronize();
//Time end
cudaEventCreate(&endEvent);
cudaEventRecord(endEvent, 0);
cudaEventSynchronize(endEvent);
//Get result from GPU
cudaMemcpy( result, gpu_result, matrixsize, cudaMemcpyDeviceToHost );
float gpuTime = 0.0f;
cudaEventElapsedTime(&gpuTime, startEvent, endEvent);
/*printf("Matrix addition: \n");
for (int r = 0; r < N; r++){
for (int c = 0; c < N; c++)
printf("%f ", result[r*N + c]);
printf("\n");
}*/
//CPU equivalent
auto cpustart = std::chrono::system_clock::now();
cpu_add_matrix(ma, mb, cpuresult);
auto cpuend = std::chrono::system_clock::now();
std::chrono::duration<double> cpuTime = cpuend-cpustart;
printf("\nMatrix: %ix%i \nBlocksize: %ix%i \n", N, N, blocksize1d, blocksize1d);
printf("GPU compute time: %f \n", gpuTime);
printf("CPU compute time: %f \n", cpuTime.count());
cudaFree( cd );
cudaFree( gpu_ma );
cudaFree( gpu_mb );
cudaFree( gpu_result );
printf("done\n");
return EXIT_SUCCESS;
} | .file "tmpxft_00038abf_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2164:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2164:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14cpu_add_matrixPfS_S_
.type _Z14cpu_add_matrixPfS_S_, @function
_Z14cpu_add_matrixPfS_S_:
.LFB2156:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L4
ret
.cfi_endproc
.LFE2156:
.size _Z14cpu_add_matrixPfS_S_, .-_Z14cpu_add_matrixPfS_S_
.globl _Z32__device_stub__Z12threadnumberPfPf
.type _Z32__device_stub__Z12threadnumberPfPf, @function
_Z32__device_stub__Z12threadnumberPfPf:
.LFB2186:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12threadnumberPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2186:
.size _Z32__device_stub__Z12threadnumberPfPf, .-_Z32__device_stub__Z12threadnumberPfPf
.globl _Z12threadnumberPf
.type _Z12threadnumberPf, @function
_Z12threadnumberPf:
.LFB2187:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12threadnumberPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2187:
.size _Z12threadnumberPf, .-_Z12threadnumberPf
.globl _Z30__device_stub__Z10squarerootPfPf
.type _Z30__device_stub__Z10squarerootPfPf, @function
_Z30__device_stub__Z10squarerootPfPf:
.LFB2188:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10squarerootPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2188:
.size _Z30__device_stub__Z10squarerootPfPf, .-_Z30__device_stub__Z10squarerootPfPf
.globl _Z10squarerootPf
.type _Z10squarerootPf, @function
_Z10squarerootPf:
.LFB2189:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10squarerootPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2189:
.size _Z10squarerootPf, .-_Z10squarerootPf
.globl _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_
.type _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_, @function
_Z34__device_stub__Z10add_matrixPfS_S_PfS_S_:
.LFB2190:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_matrixPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2190:
.size _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_, .-_Z34__device_stub__Z10add_matrixPfS_S_PfS_S_
.globl _Z10add_matrixPfS_S_
.type _Z10add_matrixPfS_S_, @function
_Z10add_matrixPfS_S_:
.LFB2191:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2191:
.size _Z10add_matrixPfS_S_, .-_Z10add_matrixPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\nMatrix: %ix%i \nBlocksize: %ix%i \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU compute time: %f \n"
.LC5:
.string "CPU compute time: %f \n"
.LC6:
.string "done\n"
.text
.globl main
.type main, @function
main:
.LFB2157:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $120, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $65536, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 65536(%rax), %rdx
movss .LC0(%rip), %xmm0
.L31:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L31
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
movl $16384, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, %ecx
movl $65536, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L32:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %r12
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %r13
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %rbx
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
.L33:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $268435456, %rax
jne .L33
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $64, 80(%rsp)
movl $64, 84(%rsp)
movl $1, 88(%rsp)
movl $256, 92(%rsp)
movl $256, 96(%rsp)
movl $1, 100(%rsp)
movl $1, %ecx
movl $1073741824, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L34:
call cudaThreadSynchronize@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $1073741824, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq %r13, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z14cpu_add_matrixPfS_S_
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %xmm0, %rbx
movl $64, %r9d
movl $64, %r8d
movl $16384, %ecx
movl $16384, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10squarerootPfPf
jmp .L32
.L40:
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_
jmp .L34
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2157:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10add_matrixPfS_S_"
.LC8:
.string "_Z10squarerootPf"
.LC9:
.string "_Z12threadnumberPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2193:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_matrixPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10squarerootPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12threadnumberPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2193:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1103626240
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <stdio.h>
#include <chrono>
const int N = 16384;
const int blocksize1d = 64;
__global__
void threadnumber(float *c)
{
c[threadIdx.x] = threadIdx.x;
}
__global__
void squareroot(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
__global__
void add_matrix(float *a, float *b, float *result)
{
int row = (blockIdx.y * blockDim.y + threadIdx.y);
int col = (blockIdx.x * blockDim.x + threadIdx.x);
int e_per_row = (gridDim.x*blockDim.x);
int idx = row*e_per_row + col;
result[idx] = a[idx] + b[idx];
}
void cpu_add_matrix(float *a, float *b, float *result){
for (int i = 0; i < N*N; ++i)
result[i] = a[i] + b[i];
}
int main()
{
/* First part, 1D */
float *c = new float[N];
float *cd;
const int size = N*sizeof(float);
for(int i=0; i<N; ++i){
c[i] = 25.0f;
}
cudaMalloc( (void**)&cd, size );
dim3 dimBlock1d( N, 1 );
dim3 dimGrid( 1, 1 );
cudaMemcpy( cd, c, size, cudaMemcpyHostToDevice );
squareroot<<<dimGrid, dimBlock1d>>>(cd);
cudaThreadSynchronize();
cudaMemcpy( c, cd, size, cudaMemcpyDeviceToHost );
/*printf("Square root: \n");
for (int i = 0; i < N; i++)
printf("%f ", c[i]);
printf("\n");
*/
/* Second part, matrix and cuda event*/
float *gpu_result, *gpu_ma, *gpu_mb;
float *result = new float[N*N];
float *cpuresult = new float[N*N];
float *ma = new float[N*N];
float *mb = new float[N*N];
const int matrixsize = N*N*sizeof(float);
for(int i=0; i<N*N; ++i){
ma[i] = (float)i;
mb[i] = (float)i;
}
cudaEvent_t startEvent, endEvent;
//Allocate and send matrices to GPU
cudaMalloc( (void**)&gpu_result, matrixsize );
cudaMalloc( (void**)&gpu_ma, matrixsize );
cudaMalloc( (void**)&gpu_mb, matrixsize );
dim3 dimBlockmatrix( blocksize1d, blocksize1d );
dim3 dimGridmatrix( N/blocksize1d, N/blocksize1d );
cudaMemcpy( gpu_ma, ma, matrixsize, cudaMemcpyHostToDevice );
cudaMemcpy( gpu_mb, mb, matrixsize, cudaMemcpyHostToDevice );
//Time start
cudaEventCreate(&startEvent);
cudaEventRecord(startEvent, 0);
cudaEventSynchronize(startEvent);
//Computation
add_matrix<<<dimGridmatrix, dimBlockmatrix>>>(gpu_ma, gpu_mb, gpu_result);
cudaThreadSynchronize();
//Time end
cudaEventCreate(&endEvent);
cudaEventRecord(endEvent, 0);
cudaEventSynchronize(endEvent);
//Get result from GPU
cudaMemcpy( result, gpu_result, matrixsize, cudaMemcpyDeviceToHost );
float gpuTime = 0.0f;
cudaEventElapsedTime(&gpuTime, startEvent, endEvent);
/*printf("Matrix addition: \n");
for (int r = 0; r < N; r++){
for (int c = 0; c < N; c++)
printf("%f ", result[r*N + c]);
printf("\n");
}*/
//CPU equivalent
auto cpustart = std::chrono::system_clock::now();
cpu_add_matrix(ma, mb, cpuresult);
auto cpuend = std::chrono::system_clock::now();
std::chrono::duration<double> cpuTime = cpuend-cpustart;
printf("\nMatrix: %ix%i \nBlocksize: %ix%i \n", N, N, blocksize1d, blocksize1d);
printf("GPU compute time: %f \n", gpuTime);
printf("CPU compute time: %f \n", cpuTime.count());
cudaFree( cd );
cudaFree( gpu_ma );
cudaFree( gpu_mb );
cudaFree( gpu_result );
printf("done\n");
return EXIT_SUCCESS;
} | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <chrono>
const int N = 16384;
const int blocksize1d = 64;
__global__
void threadnumber(float *c)
{
c[threadIdx.x] = threadIdx.x;
}
__global__
void squareroot(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
__global__
void add_matrix(float *a, float *b, float *result)
{
int row = (blockIdx.y * blockDim.y + threadIdx.y);
int col = (blockIdx.x * blockDim.x + threadIdx.x);
int e_per_row = (gridDim.x*blockDim.x);
int idx = row*e_per_row + col;
result[idx] = a[idx] + b[idx];
}
void cpu_add_matrix(float *a, float *b, float *result){
for (int i = 0; i < N*N; ++i)
result[i] = a[i] + b[i];
}
int main()
{
/* First part, 1D */
float *c = new float[N];
float *cd;
const int size = N*sizeof(float);
for(int i=0; i<N; ++i){
c[i] = 25.0f;
}
hipMalloc( (void**)&cd, size );
dim3 dimBlock1d( N, 1 );
dim3 dimGrid( 1, 1 );
hipMemcpy( cd, c, size, hipMemcpyHostToDevice );
squareroot<<<dimGrid, dimBlock1d>>>(cd);
hipDeviceSynchronize();
hipMemcpy( c, cd, size, hipMemcpyDeviceToHost );
/*printf("Square root: \n");
for (int i = 0; i < N; i++)
printf("%f ", c[i]);
printf("\n");
*/
/* Second part, matrix and cuda event*/
float *gpu_result, *gpu_ma, *gpu_mb;
float *result = new float[N*N];
float *cpuresult = new float[N*N];
float *ma = new float[N*N];
float *mb = new float[N*N];
const int matrixsize = N*N*sizeof(float);
for(int i=0; i<N*N; ++i){
ma[i] = (float)i;
mb[i] = (float)i;
}
hipEvent_t startEvent, endEvent;
//Allocate and send matrices to GPU
hipMalloc( (void**)&gpu_result, matrixsize );
hipMalloc( (void**)&gpu_ma, matrixsize );
hipMalloc( (void**)&gpu_mb, matrixsize );
dim3 dimBlockmatrix( blocksize1d, blocksize1d );
dim3 dimGridmatrix( N/blocksize1d, N/blocksize1d );
hipMemcpy( gpu_ma, ma, matrixsize, hipMemcpyHostToDevice );
hipMemcpy( gpu_mb, mb, matrixsize, hipMemcpyHostToDevice );
//Time start
hipEventCreate(&startEvent);
hipEventRecord(startEvent, 0);
hipEventSynchronize(startEvent);
//Computation
add_matrix<<<dimGridmatrix, dimBlockmatrix>>>(gpu_ma, gpu_mb, gpu_result);
hipDeviceSynchronize();
//Time end
hipEventCreate(&endEvent);
hipEventRecord(endEvent, 0);
hipEventSynchronize(endEvent);
//Get result from GPU
hipMemcpy( result, gpu_result, matrixsize, hipMemcpyDeviceToHost );
float gpuTime = 0.0f;
hipEventElapsedTime(&gpuTime, startEvent, endEvent);
/*printf("Matrix addition: \n");
for (int r = 0; r < N; r++){
for (int c = 0; c < N; c++)
printf("%f ", result[r*N + c]);
printf("\n");
}*/
//CPU equivalent
auto cpustart = std::chrono::system_clock::now();
cpu_add_matrix(ma, mb, cpuresult);
auto cpuend = std::chrono::system_clock::now();
std::chrono::duration<double> cpuTime = cpuend-cpustart;
printf("\nMatrix: %ix%i \nBlocksize: %ix%i \n", N, N, blocksize1d, blocksize1d);
printf("GPU compute time: %f \n", gpuTime);
printf("CPU compute time: %f \n", cpuTime.count());
hipFree( cd );
hipFree( gpu_ma );
hipFree( gpu_mb );
hipFree( gpu_result );
printf("done\n");
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <chrono>
const int N = 16384;
const int blocksize1d = 64;
__global__
void threadnumber(float *c)
{
c[threadIdx.x] = threadIdx.x;
}
__global__
void squareroot(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
__global__
void add_matrix(float *a, float *b, float *result)
{
int row = (blockIdx.y * blockDim.y + threadIdx.y);
int col = (blockIdx.x * blockDim.x + threadIdx.x);
int e_per_row = (gridDim.x*blockDim.x);
int idx = row*e_per_row + col;
result[idx] = a[idx] + b[idx];
}
void cpu_add_matrix(float *a, float *b, float *result){
for (int i = 0; i < N*N; ++i)
result[i] = a[i] + b[i];
}
int main()
{
/* First part, 1D */
float *c = new float[N];
float *cd;
const int size = N*sizeof(float);
for(int i=0; i<N; ++i){
c[i] = 25.0f;
}
hipMalloc( (void**)&cd, size );
dim3 dimBlock1d( N, 1 );
dim3 dimGrid( 1, 1 );
hipMemcpy( cd, c, size, hipMemcpyHostToDevice );
squareroot<<<dimGrid, dimBlock1d>>>(cd);
hipDeviceSynchronize();
hipMemcpy( c, cd, size, hipMemcpyDeviceToHost );
/*printf("Square root: \n");
for (int i = 0; i < N; i++)
printf("%f ", c[i]);
printf("\n");
*/
/* Second part, matrix and cuda event*/
float *gpu_result, *gpu_ma, *gpu_mb;
float *result = new float[N*N];
float *cpuresult = new float[N*N];
float *ma = new float[N*N];
float *mb = new float[N*N];
const int matrixsize = N*N*sizeof(float);
for(int i=0; i<N*N; ++i){
ma[i] = (float)i;
mb[i] = (float)i;
}
hipEvent_t startEvent, endEvent;
//Allocate and send matrices to GPU
hipMalloc( (void**)&gpu_result, matrixsize );
hipMalloc( (void**)&gpu_ma, matrixsize );
hipMalloc( (void**)&gpu_mb, matrixsize );
dim3 dimBlockmatrix( blocksize1d, blocksize1d );
dim3 dimGridmatrix( N/blocksize1d, N/blocksize1d );
hipMemcpy( gpu_ma, ma, matrixsize, hipMemcpyHostToDevice );
hipMemcpy( gpu_mb, mb, matrixsize, hipMemcpyHostToDevice );
//Time start
hipEventCreate(&startEvent);
hipEventRecord(startEvent, 0);
hipEventSynchronize(startEvent);
//Computation
add_matrix<<<dimGridmatrix, dimBlockmatrix>>>(gpu_ma, gpu_mb, gpu_result);
hipDeviceSynchronize();
//Time end
hipEventCreate(&endEvent);
hipEventRecord(endEvent, 0);
hipEventSynchronize(endEvent);
//Get result from GPU
hipMemcpy( result, gpu_result, matrixsize, hipMemcpyDeviceToHost );
float gpuTime = 0.0f;
hipEventElapsedTime(&gpuTime, startEvent, endEvent);
/*printf("Matrix addition: \n");
for (int r = 0; r < N; r++){
for (int c = 0; c < N; c++)
printf("%f ", result[r*N + c]);
printf("\n");
}*/
//CPU equivalent
auto cpustart = std::chrono::system_clock::now();
cpu_add_matrix(ma, mb, cpuresult);
auto cpuend = std::chrono::system_clock::now();
std::chrono::duration<double> cpuTime = cpuend-cpustart;
printf("\nMatrix: %ix%i \nBlocksize: %ix%i \n", N, N, blocksize1d, blocksize1d);
printf("GPU compute time: %f \n", gpuTime);
printf("CPU compute time: %f \n", cpuTime.count());
hipFree( cd );
hipFree( gpu_ma );
hipFree( gpu_mb );
hipFree( gpu_result );
printf("done\n");
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12threadnumberPf
.globl _Z12threadnumberPf
.p2align 8
.type _Z12threadnumberPf,@function
_Z12threadnumberPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_u32_e32 v1, v0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12threadnumberPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12threadnumberPf, .Lfunc_end0-_Z12threadnumberPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10squarerootPf
.globl _Z10squarerootPf
.p2align 8
.type _Z10squarerootPf,@function
_Z10squarerootPf:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v2, v1
v_fma_f32 v6, -v4, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10squarerootPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10squarerootPf, .Lfunc_end1-_Z10squarerootPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10add_matrixPfS_S_
.globl _Z10add_matrixPfS_S_
.p2align 8
.type _Z10add_matrixPfS_S_,@function
_Z10add_matrixPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_matrixPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10add_matrixPfS_S_, .Lfunc_end2-_Z10add_matrixPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12threadnumberPf
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z12threadnumberPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10squarerootPf
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z10squarerootPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_matrixPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_matrixPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Simple CUDA example by Ingemar Ragnemalm 2009. Simplest possible?
// Assigns every element in an array with its index.
// nvcc simple.cu -L /usr/local/cuda/lib -lcudart -o simple
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <chrono>
const int N = 16384;
const int blocksize1d = 64;
__global__
void threadnumber(float *c)
{
c[threadIdx.x] = threadIdx.x;
}
__global__
void squareroot(float *c)
{
c[threadIdx.x] = sqrt(c[threadIdx.x]);
}
__global__
void add_matrix(float *a, float *b, float *result)
{
int row = (blockIdx.y * blockDim.y + threadIdx.y);
int col = (blockIdx.x * blockDim.x + threadIdx.x);
int e_per_row = (gridDim.x*blockDim.x);
int idx = row*e_per_row + col;
result[idx] = a[idx] + b[idx];
}
void cpu_add_matrix(float *a, float *b, float *result){
for (int i = 0; i < N*N; ++i)
result[i] = a[i] + b[i];
}
int main()
{
/* First part, 1D */
float *c = new float[N];
float *cd;
const int size = N*sizeof(float);
for(int i=0; i<N; ++i){
c[i] = 25.0f;
}
hipMalloc( (void**)&cd, size );
dim3 dimBlock1d( N, 1 );
dim3 dimGrid( 1, 1 );
hipMemcpy( cd, c, size, hipMemcpyHostToDevice );
squareroot<<<dimGrid, dimBlock1d>>>(cd);
hipDeviceSynchronize();
hipMemcpy( c, cd, size, hipMemcpyDeviceToHost );
/*printf("Square root: \n");
for (int i = 0; i < N; i++)
printf("%f ", c[i]);
printf("\n");
*/
/* Second part, matrix and cuda event*/
float *gpu_result, *gpu_ma, *gpu_mb;
float *result = new float[N*N];
float *cpuresult = new float[N*N];
float *ma = new float[N*N];
float *mb = new float[N*N];
const int matrixsize = N*N*sizeof(float);
for(int i=0; i<N*N; ++i){
ma[i] = (float)i;
mb[i] = (float)i;
}
hipEvent_t startEvent, endEvent;
//Allocate and send matrices to GPU
hipMalloc( (void**)&gpu_result, matrixsize );
hipMalloc( (void**)&gpu_ma, matrixsize );
hipMalloc( (void**)&gpu_mb, matrixsize );
dim3 dimBlockmatrix( blocksize1d, blocksize1d );
dim3 dimGridmatrix( N/blocksize1d, N/blocksize1d );
hipMemcpy( gpu_ma, ma, matrixsize, hipMemcpyHostToDevice );
hipMemcpy( gpu_mb, mb, matrixsize, hipMemcpyHostToDevice );
//Time start
hipEventCreate(&startEvent);
hipEventRecord(startEvent, 0);
hipEventSynchronize(startEvent);
//Computation
add_matrix<<<dimGridmatrix, dimBlockmatrix>>>(gpu_ma, gpu_mb, gpu_result);
hipDeviceSynchronize();
//Time end
hipEventCreate(&endEvent);
hipEventRecord(endEvent, 0);
hipEventSynchronize(endEvent);
//Get result from GPU
hipMemcpy( result, gpu_result, matrixsize, hipMemcpyDeviceToHost );
float gpuTime = 0.0f;
hipEventElapsedTime(&gpuTime, startEvent, endEvent);
/*printf("Matrix addition: \n");
for (int r = 0; r < N; r++){
for (int c = 0; c < N; c++)
printf("%f ", result[r*N + c]);
printf("\n");
}*/
//CPU equivalent
auto cpustart = std::chrono::system_clock::now();
cpu_add_matrix(ma, mb, cpuresult);
auto cpuend = std::chrono::system_clock::now();
std::chrono::duration<double> cpuTime = cpuend-cpustart;
printf("\nMatrix: %ix%i \nBlocksize: %ix%i \n", N, N, blocksize1d, blocksize1d);
printf("GPU compute time: %f \n", gpuTime);
printf("CPU compute time: %f \n", cpuTime.count());
hipFree( cd );
hipFree( gpu_ma );
hipFree( gpu_mb );
hipFree( gpu_result );
printf("done\n");
return EXIT_SUCCESS;
} | .text
.file "simple.hip"
.globl _Z27__device_stub__threadnumberPf # -- Begin function _Z27__device_stub__threadnumberPf
.p2align 4, 0x90
.type _Z27__device_stub__threadnumberPf,@function
_Z27__device_stub__threadnumberPf: # @_Z27__device_stub__threadnumberPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12threadnumberPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z27__device_stub__threadnumberPf, .Lfunc_end0-_Z27__device_stub__threadnumberPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__squarerootPf # -- Begin function _Z25__device_stub__squarerootPf
.p2align 4, 0x90
.type _Z25__device_stub__squarerootPf,@function
_Z25__device_stub__squarerootPf: # @_Z25__device_stub__squarerootPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10squarerootPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z25__device_stub__squarerootPf, .Lfunc_end1-_Z25__device_stub__squarerootPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_matrixPfS_S_ # -- Begin function _Z25__device_stub__add_matrixPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__add_matrixPfS_S_,@function
_Z25__device_stub__add_matrixPfS_S_: # @_Z25__device_stub__add_matrixPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_matrixPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z25__device_stub__add_matrixPfS_S_, .Lfunc_end2-_Z25__device_stub__add_matrixPfS_S_
.cfi_endproc
# -- End function
.globl _Z14cpu_add_matrixPfS_S_ # -- Begin function _Z14cpu_add_matrixPfS_S_
.p2align 4, 0x90
.type _Z14cpu_add_matrixPfS_S_,@function
_Z14cpu_add_matrixPfS_S_: # @_Z14cpu_add_matrixPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB3_1
# %bb.2:
retq
.Lfunc_end3:
.size _Z14cpu_add_matrixPfS_S_, .Lfunc_end3-_Z14cpu_add_matrixPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $65536, %edi # imm = 0x10000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $1103626240, (%rbx,%rax,4) # imm = 0x41C80000
incq %rax
cmpq $16384, %rax # imm = 0x4000
jne .LBB4_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
movq 24(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 16383(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10squarerootPf, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r15
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB4_5
# %bb.6:
leaq 72(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 64(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 56(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movq 64(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movabsq $1099511628032, %rdi # imm = 0x10000000100
movabsq $274877907008, %rdx # imm = 0x4000000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 72(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10add_matrixPfS_S_, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8: # %_Z14cpu_add_matrixPfS_S_.exit
callq hipDeviceSynchronize
leaq 96(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 96(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $0, 8(%rsp)
movq 48(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 136(%rsp) # 8-byte Spill
movl $.L.str, %edi
movl $16384, %esi # imm = 0x4000
movl $16384, %edx # imm = 0x4000
movl $64, %ecx
movl $64, %r8d
xorl %eax, %eax
callq printf
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12threadnumberPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10squarerootPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_matrixPfS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12threadnumberPf,@object # @_Z12threadnumberPf
.section .rodata,"a",@progbits
.globl _Z12threadnumberPf
.p2align 3, 0x0
_Z12threadnumberPf:
.quad _Z27__device_stub__threadnumberPf
.size _Z12threadnumberPf, 8
.type _Z10squarerootPf,@object # @_Z10squarerootPf
.globl _Z10squarerootPf
.p2align 3, 0x0
_Z10squarerootPf:
.quad _Z25__device_stub__squarerootPf
.size _Z10squarerootPf, 8
.type _Z10add_matrixPfS_S_,@object # @_Z10add_matrixPfS_S_
.globl _Z10add_matrixPfS_S_
.p2align 3, 0x0
_Z10add_matrixPfS_S_:
.quad _Z25__device_stub__add_matrixPfS_S_
.size _Z10add_matrixPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nMatrix: %ix%i \nBlocksize: %ix%i \n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU compute time: %f \n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU compute time: %f \n"
.size .L.str.2, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12threadnumberPf"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10squarerootPf"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10add_matrixPfS_S_"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__threadnumberPf
.addrsig_sym _Z25__device_stub__squarerootPf
.addrsig_sym _Z25__device_stub__add_matrixPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12threadnumberPf
.addrsig_sym _Z10squarerootPf
.addrsig_sym _Z10add_matrixPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10add_matrixPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0209 */
/*00f0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10squarerootPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ BSSY B0, 0x140 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0070*/ IADD3 R4, R0, -0xd000000, RZ ; /* 0xf300000000047810 */
/* 0x004fe20007ffe0ff */
/*0080*/ MUFU.RSQ R5, R0 ; /* 0x0000000000057308 */
/* 0x0000660000001400 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*00a0*/ @!P0 BRA 0xf0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R9, 0xd0 ; /* 0x000000d000097802 */
/* 0x003fe40000000f00 */
/*00c0*/ CALL.REL.NOINC 0x160 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*00d0*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fe20000000f00 */
/*00e0*/ BRA 0x130 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*00f0*/ FMUL.FTZ R7, R0, R5 ; /* 0x0000000500077220 */
/* 0x003fe40000410000 */
/*0100*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0110*/ FFMA R0, -R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x000fc80000000100 */
/*0120*/ FFMA R5, R0, R5, R7 ; /* 0x0000000500057223 */
/* 0x000fe40000000007 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*0170*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*0180*/ @!P0 BRA 0x290 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0190*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*01a0*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*01b0*/ @!P0 BRA 0x290 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*01c0*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*01d0*/ @P0 FADD.FTZ R4, R0, 1 ; /* 0x3f80000000040421 */
/* 0x000fe20000010000 */
/*01e0*/ @P0 BRA 0x290 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*01f0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*0200*/ @P0 FFMA R5, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000050823 */
/* 0x000fc800000000ff */
/*0210*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0220*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*0230*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe20000410000 */
/*0240*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*0250*/ @P0 FADD.FTZ R7, -R6, -RZ ; /* 0x800000ff06070221 */
/* 0x000fc80000010100 */
/*0260*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*0270*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*0280*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*0290*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*02a0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*02b0*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fc80000000f00 */
/*02c0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffd3004007950 */
/* 0x000fea0003c3ffff */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12threadnumberPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x001e300000201000 */
/*0050*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12threadnumberPf
.globl _Z12threadnumberPf
.p2align 8
.type _Z12threadnumberPf,@function
_Z12threadnumberPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_u32_e32 v1, v0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12threadnumberPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12threadnumberPf, .Lfunc_end0-_Z12threadnumberPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10squarerootPf
.globl _Z10squarerootPf
.p2align 8
.type _Z10squarerootPf,@function
_Z10squarerootPf:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v2, v1
v_fma_f32 v6, -v4, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10squarerootPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10squarerootPf, .Lfunc_end1-_Z10squarerootPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10add_matrixPfS_S_
.globl _Z10add_matrixPfS_S_
.p2align 8
.type _Z10add_matrixPfS_S_,@function
_Z10add_matrixPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_matrixPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10add_matrixPfS_S_, .Lfunc_end2-_Z10add_matrixPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12threadnumberPf
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z12threadnumberPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10squarerootPf
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z10squarerootPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_matrixPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_matrixPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00038abf_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2164:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2164:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14cpu_add_matrixPfS_S_
.type _Z14cpu_add_matrixPfS_S_, @function
_Z14cpu_add_matrixPfS_S_:
.LFB2156:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L4
ret
.cfi_endproc
.LFE2156:
.size _Z14cpu_add_matrixPfS_S_, .-_Z14cpu_add_matrixPfS_S_
.globl _Z32__device_stub__Z12threadnumberPfPf
.type _Z32__device_stub__Z12threadnumberPfPf, @function
_Z32__device_stub__Z12threadnumberPfPf:
.LFB2186:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12threadnumberPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2186:
.size _Z32__device_stub__Z12threadnumberPfPf, .-_Z32__device_stub__Z12threadnumberPfPf
.globl _Z12threadnumberPf
.type _Z12threadnumberPf, @function
_Z12threadnumberPf:
.LFB2187:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12threadnumberPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2187:
.size _Z12threadnumberPf, .-_Z12threadnumberPf
.globl _Z30__device_stub__Z10squarerootPfPf
.type _Z30__device_stub__Z10squarerootPfPf, @function
_Z30__device_stub__Z10squarerootPfPf:
.LFB2188:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10squarerootPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2188:
.size _Z30__device_stub__Z10squarerootPfPf, .-_Z30__device_stub__Z10squarerootPfPf
.globl _Z10squarerootPf
.type _Z10squarerootPf, @function
_Z10squarerootPf:
.LFB2189:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10squarerootPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2189:
.size _Z10squarerootPf, .-_Z10squarerootPf
.globl _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_
.type _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_, @function
_Z34__device_stub__Z10add_matrixPfS_S_PfS_S_:
.LFB2190:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_matrixPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2190:
.size _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_, .-_Z34__device_stub__Z10add_matrixPfS_S_PfS_S_
.globl _Z10add_matrixPfS_S_
.type _Z10add_matrixPfS_S_, @function
_Z10add_matrixPfS_S_:
.LFB2191:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2191:
.size _Z10add_matrixPfS_S_, .-_Z10add_matrixPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\nMatrix: %ix%i \nBlocksize: %ix%i \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU compute time: %f \n"
.LC5:
.string "CPU compute time: %f \n"
.LC6:
.string "done\n"
.text
.globl main
.type main, @function
main:
.LFB2157:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $120, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $65536, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 65536(%rax), %rdx
movss .LC0(%rip), %xmm0
.L31:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L31
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
movl $16384, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, %ecx
movl $65536, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L32:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %r12
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %r13
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %rbx
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
.L33:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $268435456, %rax
jne .L33
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $64, 80(%rsp)
movl $64, 84(%rsp)
movl $1, 88(%rsp)
movl $256, 92(%rsp)
movl $256, 96(%rsp)
movl $1, 100(%rsp)
movl $1, %ecx
movl $1073741824, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L34:
call cudaThreadSynchronize@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $1073741824, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq %r13, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z14cpu_add_matrixPfS_S_
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %xmm0, %rbx
movl $64, %r9d
movl $64, %r8d
movl $16384, %ecx
movl $16384, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10squarerootPfPf
jmp .L32
.L40:
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z10add_matrixPfS_S_PfS_S_
jmp .L34
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2157:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10add_matrixPfS_S_"
.LC8:
.string "_Z10squarerootPf"
.LC9:
.string "_Z12threadnumberPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2193:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_matrixPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10squarerootPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12threadnumberPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2193:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1103626240
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple.hip"
.globl _Z27__device_stub__threadnumberPf # -- Begin function _Z27__device_stub__threadnumberPf
.p2align 4, 0x90
.type _Z27__device_stub__threadnumberPf,@function
_Z27__device_stub__threadnumberPf: # @_Z27__device_stub__threadnumberPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12threadnumberPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z27__device_stub__threadnumberPf, .Lfunc_end0-_Z27__device_stub__threadnumberPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__squarerootPf # -- Begin function _Z25__device_stub__squarerootPf
.p2align 4, 0x90
.type _Z25__device_stub__squarerootPf,@function
_Z25__device_stub__squarerootPf: # @_Z25__device_stub__squarerootPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10squarerootPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z25__device_stub__squarerootPf, .Lfunc_end1-_Z25__device_stub__squarerootPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_matrixPfS_S_ # -- Begin function _Z25__device_stub__add_matrixPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__add_matrixPfS_S_,@function
_Z25__device_stub__add_matrixPfS_S_: # @_Z25__device_stub__add_matrixPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_matrixPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z25__device_stub__add_matrixPfS_S_, .Lfunc_end2-_Z25__device_stub__add_matrixPfS_S_
.cfi_endproc
# -- End function
.globl _Z14cpu_add_matrixPfS_S_ # -- Begin function _Z14cpu_add_matrixPfS_S_
.p2align 4, 0x90
.type _Z14cpu_add_matrixPfS_S_,@function
_Z14cpu_add_matrixPfS_S_: # @_Z14cpu_add_matrixPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB3_1
# %bb.2:
retq
.Lfunc_end3:
.size _Z14cpu_add_matrixPfS_S_, .Lfunc_end3-_Z14cpu_add_matrixPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $65536, %edi # imm = 0x10000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $1103626240, (%rbx,%rax,4) # imm = 0x41C80000
incq %rax
cmpq $16384, %rax # imm = 0x4000
jne .LBB4_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
movq 24(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 16383(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10squarerootPf, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r15
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB4_5
# %bb.6:
leaq 72(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 64(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 56(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movq 64(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movabsq $1099511628032, %rdi # imm = 0x10000000100
movabsq $274877907008, %rdx # imm = 0x4000000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 72(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10add_matrixPfS_S_, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8: # %_Z14cpu_add_matrixPfS_S_.exit
callq hipDeviceSynchronize
leaq 96(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 96(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $0, 8(%rsp)
movq 48(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 136(%rsp) # 8-byte Spill
movl $.L.str, %edi
movl $16384, %esi # imm = 0x4000
movl $16384, %edx # imm = 0x4000
movl $64, %ecx
movl $64, %r8d
xorl %eax, %eax
callq printf
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12threadnumberPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10squarerootPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_matrixPfS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12threadnumberPf,@object # @_Z12threadnumberPf
.section .rodata,"a",@progbits
.globl _Z12threadnumberPf
.p2align 3, 0x0
_Z12threadnumberPf:
.quad _Z27__device_stub__threadnumberPf
.size _Z12threadnumberPf, 8
.type _Z10squarerootPf,@object # @_Z10squarerootPf
.globl _Z10squarerootPf
.p2align 3, 0x0
_Z10squarerootPf:
.quad _Z25__device_stub__squarerootPf
.size _Z10squarerootPf, 8
.type _Z10add_matrixPfS_S_,@object # @_Z10add_matrixPfS_S_
.globl _Z10add_matrixPfS_S_
.p2align 3, 0x0
_Z10add_matrixPfS_S_:
.quad _Z25__device_stub__add_matrixPfS_S_
.size _Z10add_matrixPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nMatrix: %ix%i \nBlocksize: %ix%i \n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU compute time: %f \n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU compute time: %f \n"
.size .L.str.2, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12threadnumberPf"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10squarerootPf"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10add_matrixPfS_S_"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__threadnumberPf
.addrsig_sym _Z25__device_stub__squarerootPf
.addrsig_sym _Z25__device_stub__add_matrixPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12threadnumberPf
.addrsig_sym _Z10squarerootPf
.addrsig_sym _Z10add_matrixPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
/* Mirror operations */
__global__
void mirror(uchar4* inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int TotalThread = blockDim.x * gridDim.x;
int stripe = numRows*numCols / TotalThread;
int col = (blockIdx.x * blockDim.x + threadIdx.x) * stripe;
int LoopLim = col + stripe;
for(int i=col ; i<LoopLim && i<numRows*numCols; i++)
{
unsigned char Y = 0.299f * inputChannel[i].x + 0.587 * inputChannel[i].y + 0.114 * inputChannel[i].z;
if(vertical)
outputChannel[i/numCols*numCols+(numCols-i%numCols)-1] = make_uchar4(Y, Y, Y, 255);
else
outputChannel[(numRows- (i/numCols) -1)*numCols +(i%numCols)] = make_uchar4(Y, Y, Y, 255);
}
}
uchar4* mirror_ops(uchar4 *d_inputImageRGBA, size_t numRows, size_t numCols, bool vertical)
{
//Creat Timing Event
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
//Set reasonable block size (i.e., number of threads per block)
dim3 blockSize(9);
//Calculate Grid SIze
dim3 gridSize(6);
//Calculate number of pixels
size_t numPixels = numRows * numCols;
//Allocate Memory Space on Device for output image
uchar4 *d_outputImageRGBA;
cudaMalloc(&d_outputImageRGBA, sizeof(uchar4) * numPixels);
//start Timer
cudaEventRecord(start, 0);
//Call mirror kernel.
mirror<<<gridSize, blockSize>>>(d_inputImageRGBA, d_outputImageRGBA, numRows, numCols, vertical);
//Stop Timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaDeviceSynchronize();
//Initialize memory on host for output uchar4*
uchar4* h_out;
h_out = (uchar4*)malloc(sizeof(uchar4) * numPixels);
//copy output from device to host
cudaMemcpy(h_out, d_outputImageRGBA, sizeof(uchar4) * numPixels, cudaMemcpyDeviceToHost);
//Cleanup memory on device
cudaFree(d_inputImageRGBA);
cudaFree(d_outputImageRGBA);
//Calculate Elapsed Time
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time = %5.2f ms\n", elapsedTime);
//return h_out
return h_out;
} | .file "tmpxft_0004f6e5_00000000-6_cuda1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib
.type _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib, @function
_Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6mirrorP6uchar4S0_iib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib, .-_Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib
.globl _Z6mirrorP6uchar4S0_iib
.type _Z6mirrorP6uchar4S0_iib, @function
_Z6mirrorP6uchar4S0_iib:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6mirrorP6uchar4S0_iib, .-_Z6mirrorP6uchar4S0_iib
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPU time = %5.2f ms\n"
.text
.globl _Z10mirror_opsP6uchar4mmb
.type _Z10mirror_opsP6uchar4mmb, @function
_Z10mirror_opsP6uchar4mmb:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %r13
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $9, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $6, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movq %rbp, %rbx
imulq %r13, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaDeviceSynchronize@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movq %rbp, %rax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movzbl %r14b, %r8d
movl %r13d, %ecx
movl %ebp, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z10mirror_opsP6uchar4mmb, .-_Z10mirror_opsP6uchar4mmb
.section .rodata.str1.1
.LC1:
.string "_Z6mirrorP6uchar4S0_iib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6mirrorP6uchar4S0_iib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
/* Mirror operations */
__global__
void mirror(uchar4* inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int TotalThread = blockDim.x * gridDim.x;
int stripe = numRows*numCols / TotalThread;
int col = (blockIdx.x * blockDim.x + threadIdx.x) * stripe;
int LoopLim = col + stripe;
for(int i=col ; i<LoopLim && i<numRows*numCols; i++)
{
unsigned char Y = 0.299f * inputChannel[i].x + 0.587 * inputChannel[i].y + 0.114 * inputChannel[i].z;
if(vertical)
outputChannel[i/numCols*numCols+(numCols-i%numCols)-1] = make_uchar4(Y, Y, Y, 255);
else
outputChannel[(numRows- (i/numCols) -1)*numCols +(i%numCols)] = make_uchar4(Y, Y, Y, 255);
}
}
uchar4* mirror_ops(uchar4 *d_inputImageRGBA, size_t numRows, size_t numCols, bool vertical)
{
//Creat Timing Event
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
//Set reasonable block size (i.e., number of threads per block)
dim3 blockSize(9);
//Calculate Grid SIze
dim3 gridSize(6);
//Calculate number of pixels
size_t numPixels = numRows * numCols;
//Allocate Memory Space on Device for output image
uchar4 *d_outputImageRGBA;
cudaMalloc(&d_outputImageRGBA, sizeof(uchar4) * numPixels);
//start Timer
cudaEventRecord(start, 0);
//Call mirror kernel.
mirror<<<gridSize, blockSize>>>(d_inputImageRGBA, d_outputImageRGBA, numRows, numCols, vertical);
//Stop Timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaDeviceSynchronize();
//Initialize memory on host for output uchar4*
uchar4* h_out;
h_out = (uchar4*)malloc(sizeof(uchar4) * numPixels);
//copy output from device to host
cudaMemcpy(h_out, d_outputImageRGBA, sizeof(uchar4) * numPixels, cudaMemcpyDeviceToHost);
//Cleanup memory on device
cudaFree(d_inputImageRGBA);
cudaFree(d_outputImageRGBA);
//Calculate Elapsed Time
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time = %5.2f ms\n", elapsedTime);
//return h_out
return h_out;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
/* Mirror operations */
__global__
void mirror(uchar4* inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int TotalThread = blockDim.x * gridDim.x;
int stripe = numRows*numCols / TotalThread;
int col = (blockIdx.x * blockDim.x + threadIdx.x) * stripe;
int LoopLim = col + stripe;
for(int i=col ; i<LoopLim && i<numRows*numCols; i++)
{
unsigned char Y = 0.299f * inputChannel[i].x + 0.587 * inputChannel[i].y + 0.114 * inputChannel[i].z;
if(vertical)
outputChannel[i/numCols*numCols+(numCols-i%numCols)-1] = make_uchar4(Y, Y, Y, 255);
else
outputChannel[(numRows- (i/numCols) -1)*numCols +(i%numCols)] = make_uchar4(Y, Y, Y, 255);
}
}
uchar4* mirror_ops(uchar4 *d_inputImageRGBA, size_t numRows, size_t numCols, bool vertical)
{
//Creat Timing Event
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
//Set reasonable block size (i.e., number of threads per block)
dim3 blockSize(9);
//Calculate Grid SIze
dim3 gridSize(6);
//Calculate number of pixels
size_t numPixels = numRows * numCols;
//Allocate Memory Space on Device for output image
uchar4 *d_outputImageRGBA;
hipMalloc(&d_outputImageRGBA, sizeof(uchar4) * numPixels);
//start Timer
hipEventRecord(start, 0);
//Call mirror kernel.
mirror<<<gridSize, blockSize>>>(d_inputImageRGBA, d_outputImageRGBA, numRows, numCols, vertical);
//Stop Timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipDeviceSynchronize();
//Initialize memory on host for output uchar4*
uchar4* h_out;
h_out = (uchar4*)malloc(sizeof(uchar4) * numPixels);
//copy output from device to host
hipMemcpy(h_out, d_outputImageRGBA, sizeof(uchar4) * numPixels, hipMemcpyDeviceToHost);
//Cleanup memory on device
hipFree(d_inputImageRGBA);
hipFree(d_outputImageRGBA);
//Calculate Elapsed Time
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time = %5.2f ms\n", elapsedTime);
//return h_out
return h_out;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
/* Mirror operations */
__global__
void mirror(uchar4* inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int TotalThread = blockDim.x * gridDim.x;
int stripe = numRows*numCols / TotalThread;
int col = (blockIdx.x * blockDim.x + threadIdx.x) * stripe;
int LoopLim = col + stripe;
for(int i=col ; i<LoopLim && i<numRows*numCols; i++)
{
unsigned char Y = 0.299f * inputChannel[i].x + 0.587 * inputChannel[i].y + 0.114 * inputChannel[i].z;
if(vertical)
outputChannel[i/numCols*numCols+(numCols-i%numCols)-1] = make_uchar4(Y, Y, Y, 255);
else
outputChannel[(numRows- (i/numCols) -1)*numCols +(i%numCols)] = make_uchar4(Y, Y, Y, 255);
}
}
uchar4* mirror_ops(uchar4 *d_inputImageRGBA, size_t numRows, size_t numCols, bool vertical)
{
//Creat Timing Event
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
//Set reasonable block size (i.e., number of threads per block)
dim3 blockSize(9);
//Calculate Grid SIze
dim3 gridSize(6);
//Calculate number of pixels
size_t numPixels = numRows * numCols;
//Allocate Memory Space on Device for output image
uchar4 *d_outputImageRGBA;
hipMalloc(&d_outputImageRGBA, sizeof(uchar4) * numPixels);
//start Timer
hipEventRecord(start, 0);
//Call mirror kernel.
mirror<<<gridSize, blockSize>>>(d_inputImageRGBA, d_outputImageRGBA, numRows, numCols, vertical);
//Stop Timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipDeviceSynchronize();
//Initialize memory on host for output uchar4*
uchar4* h_out;
h_out = (uchar4*)malloc(sizeof(uchar4) * numPixels);
//copy output from device to host
hipMemcpy(h_out, d_outputImageRGBA, sizeof(uchar4) * numPixels, hipMemcpyDeviceToHost);
//Cleanup memory on device
hipFree(d_inputImageRGBA);
hipFree(d_outputImageRGBA);
//Calculate Elapsed Time
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time = %5.2f ms\n", elapsedTime);
//return h_out
return h_out;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.globl _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.p2align 8
.type _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib,@function
_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x20
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s3, s4
s_ashr_i32 s5, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s5
s_xor_b32 s6, s2, s5
s_load_b64 s[2:3], s[0:1], 0x10
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s9, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s3, s2
v_cvt_u32_f32_e32 v1, v1
s_ashr_i32 s10, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_i32 s11, s8, s10
s_xor_b32 s5, s10, s5
v_readfirstlane_b32 s7, v1
s_xor_b32 s11, s11, s10
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s7
s_mul_hi_u32 s9, s7, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s9
s_mul_hi_u32 s7, s11, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s7, s6
s_add_i32 s10, s7, 1
s_sub_i32 s9, s11, s9
s_sub_i32 s11, s9, s6
s_cmp_ge_u32 s9, s6
s_cselect_b32 s7, s10, s7
s_cselect_b32 s9, s11, s9
s_add_i32 s10, s7, 1
s_cmp_ge_u32 s9, s6
s_cselect_b32 s4, s10, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s5
s_sub_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, s4
v_add_nc_u32_e32 v1, s4, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_i32_e32 v3, s8, v1
v_cmpx_lt_i32_e64 v0, v3
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s11, 0x3fe2c8b4
s_mov_b32 s10, 0x39581062
s_mov_b32 s13, 0x3fbd2f1a
s_mov_b32 s12, 0x9fbe76c9
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s8, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s15, s0, -1
s_add_u32 s8, s6, -4
s_addc_u32 s9, s7, -1
s_ashr_i32 s16, s3, 31
s_add_i32 s2, s2, -1
s_add_i32 s0, s3, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s17, s0, s16
v_cvt_f32_u32_e32 v1, s17
s_sub_i32 s0, 0, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s0, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
s_branch .LBB0_3
.LBB0_2:
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v2, v7
s_waitcnt vmcnt(1)
v_and_b32_e32 v6, 0xff, v6
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v2, 0x3e991687, v2
v_and_b32_e32 v8, 0xffff, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, v0, v3
v_cvt_f64_f32_e32 v[6:7], v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[8:9], v8
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 0xff, v5
s_or_b32 s14, vcc_lo, s14
v_and_b32_e32 v2, 0xffff, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f64_u32_e32 v[10:11], v2
v_fma_f64 v[5:6], v[8:9], s[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[10:11], s[12:13], v[5:6]
v_cvt_i32_f64_e32 v2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b16 v5, 8, v2
v_or_b32_e32 v6, 0xffffff00, v2
v_or_b32_e32 v5, v2, v5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v6, 16, v6
v_and_b32_e32 v5, 0xffff, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_or_b32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s0, v1
v_add_co_ci_u32_e64 v2, s0, s1, v2, s0
global_store_b32 v[1:2], v5, off
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v8, 31, v0
s_mov_b32 s0, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_and_b32 vcc_lo, exec_lo, s15
s_clause 0x2
global_load_u8 v7, v[1:2], off
global_load_u8 v6, v[1:2], off offset:1
global_load_u8 v5, v[1:2], off offset:2
s_cbranch_vccz .LBB0_5
v_add_nc_u32_e32 v1, v0, v8
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v8
v_mul_hi_u32 v2, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v2, s17
v_sub_nc_u32_e32 v1, v1, v9
v_add_nc_u32_e32 v9, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s17, v1
v_cmp_le_u32_e32 vcc_lo, s17, v1
v_dual_cndmask_b32 v2, v2, v9 :: v_dual_cndmask_b32 v1, v1, v10
v_xor_b32_e32 v10, s16, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v9, 1, v2
v_cmp_le_u32_e32 vcc_lo, s17, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v1, v2, v9, vcc_lo
v_lshl_add_u32 v2, v10, 1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v10
v_lshlrev_b32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v2, v1
v_mad_u64_u32 v[1:2], null, s3, v9, v[0:1]
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[6:7]
s_cbranch_vccnz .LBB0_2
v_add_nc_u32_e32 v1, v0, v8
s_mov_b64 s[0:1], s[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v8
v_mul_hi_u32 v2, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s17
v_sub_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s17, v1
v_cmp_le_u32_e32 vcc_lo, s17, v1
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s17, v1
v_cmp_le_u32_e32 vcc_lo, s17, v1
v_dual_cndmask_b32 v1, v1, v2 :: v_dual_add_nc_u32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v8
v_sub_nc_u32_e32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_sub_nc_u32_e32 v1, v2, v1
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib, .Lfunc_end0-_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
/* Mirror operations */
__global__
void mirror(uchar4* inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int TotalThread = blockDim.x * gridDim.x;
int stripe = numRows*numCols / TotalThread;
int col = (blockIdx.x * blockDim.x + threadIdx.x) * stripe;
int LoopLim = col + stripe;
for(int i=col ; i<LoopLim && i<numRows*numCols; i++)
{
unsigned char Y = 0.299f * inputChannel[i].x + 0.587 * inputChannel[i].y + 0.114 * inputChannel[i].z;
if(vertical)
outputChannel[i/numCols*numCols+(numCols-i%numCols)-1] = make_uchar4(Y, Y, Y, 255);
else
outputChannel[(numRows- (i/numCols) -1)*numCols +(i%numCols)] = make_uchar4(Y, Y, Y, 255);
}
}
uchar4* mirror_ops(uchar4 *d_inputImageRGBA, size_t numRows, size_t numCols, bool vertical)
{
//Creat Timing Event
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
//Set reasonable block size (i.e., number of threads per block)
dim3 blockSize(9);
//Calculate Grid SIze
dim3 gridSize(6);
//Calculate number of pixels
size_t numPixels = numRows * numCols;
//Allocate Memory Space on Device for output image
uchar4 *d_outputImageRGBA;
hipMalloc(&d_outputImageRGBA, sizeof(uchar4) * numPixels);
//start Timer
hipEventRecord(start, 0);
//Call mirror kernel.
mirror<<<gridSize, blockSize>>>(d_inputImageRGBA, d_outputImageRGBA, numRows, numCols, vertical);
//Stop Timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipDeviceSynchronize();
//Initialize memory on host for output uchar4*
uchar4* h_out;
h_out = (uchar4*)malloc(sizeof(uchar4) * numPixels);
//copy output from device to host
hipMemcpy(h_out, d_outputImageRGBA, sizeof(uchar4) * numPixels, hipMemcpyDeviceToHost);
//Cleanup memory on device
hipFree(d_inputImageRGBA);
hipFree(d_outputImageRGBA);
//Calculate Elapsed Time
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time = %5.2f ms\n", elapsedTime);
//return h_out
return h_out;
} | .text
.file "cuda1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib # -- Begin function _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.p2align 4, 0x90
.type _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib,@function
_Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib: # @_Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 7(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 7(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib, .Lfunc_end0-_Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.cfi_endproc
# -- End function
.globl _Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb # -- Begin function _Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb
.p2align 4, 0x90
.type _Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb,@function
_Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb: # @_Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %r12, %r14
imulq %r15, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967302, %rdi # imm = 0x100000006
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rbx, 104(%rsp)
movq %rax, 96(%rsp)
movl %r12d, 36(%rsp)
movl %r15d, 32(%rsp)
movb %bpl, 15(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 15(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
callq hipDeviceSynchronize
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq 16(%rsp), %rsi
movq %rax, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %r15, %rax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb, .Lfunc_end1-_Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib,@object # @_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.section .rodata,"a",@progbits
.globl _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.p2align 3, 0x0
_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib:
.quad _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.size _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU time = %5.2f ms\n"
.size .L.str, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004f6e5_00000000-6_cuda1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib
.type _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib, @function
_Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6mirrorP6uchar4S0_iib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib, .-_Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib
.globl _Z6mirrorP6uchar4S0_iib
.type _Z6mirrorP6uchar4S0_iib, @function
_Z6mirrorP6uchar4S0_iib:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6mirrorP6uchar4S0_iib, .-_Z6mirrorP6uchar4S0_iib
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPU time = %5.2f ms\n"
.text
.globl _Z10mirror_opsP6uchar4mmb
.type _Z10mirror_opsP6uchar4mmb, @function
_Z10mirror_opsP6uchar4mmb:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %r13
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $9, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $6, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movq %rbp, %rbx
imulq %r13, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaDeviceSynchronize@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movq %rbp, %rax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movzbl %r14b, %r8d
movl %r13d, %ecx
movl %ebp, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call _Z37__device_stub__Z6mirrorP6uchar4S0_iibP6uchar4S0_iib
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z10mirror_opsP6uchar4mmb, .-_Z10mirror_opsP6uchar4mmb
.section .rodata.str1.1
.LC1:
.string "_Z6mirrorP6uchar4S0_iib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6mirrorP6uchar4S0_iib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib # -- Begin function _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.p2align 4, 0x90
.type _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib,@function
_Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib: # @_Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 7(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 7(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib, .Lfunc_end0-_Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.cfi_endproc
# -- End function
.globl _Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb # -- Begin function _Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb
.p2align 4, 0x90
.type _Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb,@function
_Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb: # @_Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %r12, %r14
imulq %r15, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967302, %rdi # imm = 0x100000006
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rbx, 104(%rsp)
movq %rax, 96(%rsp)
movl %r12d, 36(%rsp)
movl %r15d, 32(%rsp)
movb %bpl, 15(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 15(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
callq hipDeviceSynchronize
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq 16(%rsp), %rsi
movq %rax, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %r15, %rax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb, .Lfunc_end1-_Z10mirror_opsP15HIP_vector_typeIhLj4EEmmb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib,@object # @_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.section .rodata,"a",@progbits
.globl _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.p2align 3, 0x0
_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib:
.quad _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.size _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU time = %5.2f ms\n"
.size .L.str, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6mirrorP15HIP_vector_typeIhLj4EES1_iib"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__mirrorP15HIP_vector_typeIhLj4EES1_iib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6mirrorP15HIP_vector_typeIhLj4EES1_iib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //SAXPY - Single-Precision A*X Plus Y
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 400
#define NUM_PARTICLES 100000
#define NUM_ITERS 1000
struct particle{
float3 pos;
float3 v;
};
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__device__ __host__ void update(struct particle *p){
p->v.x *= (1.0 + 1e-1);
p->v.y *= (1.0 + 1e-1);
p->v.z *= (1.0 + 1e-1);
p->pos.x += p->v.x;
p->pos.y += p->v.y;
p->pos.z += p->v.z;
}
__global__ void particle_kernel(struct particle *particles){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < NUM_PARTICLES){
update(&particles[i]);
}
}
__host__ void verify(struct particle *particles){
for(int i = 0; i < NUM_PARTICLES; i++){
update(&particles[i]);
}
}
__host__ void compare(struct particle *a, struct particle *b, float moe){
//Compare a to b using a distance metric on particle points s.t. |a - b| <= moe
for (int i = 0; i < NUM_PARTICLES; i++){
float len = sqrt(pow((a[i].pos.x - b[i].pos.x), 2) + pow((a[i].pos.y - b[i].pos.y), 2) + pow((a[i].pos.z - b[i].pos.z), 2));
if (len >= moe){
printf("Comparison failed w. %f accuracy.\n", moe);
return;
}
}
printf("Comparison successful w. %f accuracy.\n", moe);
}
int main(){
//Host address, intermediate memory and device adderss
particle particles_h[NUM_PARTICLES], intermediate_h[NUM_PARTICLES];
particle *particles_d = 0;
//Allocate host memory
//particles_h = (particle *) malloc(NUM_PARTICLES*sizeof(particle));
//intermediate_h = (particle *) malloc(ARRANUM_PARTICLESY_SIZE*sizeof(particle));
// Allocate device memory
cudaMalloc(&particles_d, NUM_PARTICLES*sizeof(particle));
//Populate host particles w. some uniformly distributed numbers from [0,1]
for(int i = 0; i < NUM_PARTICLES; i++){
float3 pos = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
float3 v = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
particles_h[i].pos = pos;
particles_h[i].v = v;
//= {pos: pos, v: v};
}
//Copy particles_h to device memory
cudaMemcpy(particles_d, particles_h, NUM_PARTICLES*sizeof(particle), cudaMemcpyHostToDevice);
//Launch kernel
printf("Computing simulation on the GPU...\n");
double t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
particle_kernel <<<(NUM_PARTICLES + BLOCK_SIZE -1)/BLOCK_SIZE, BLOCK_SIZE>>>(particles_d);
}
//Sync
cudaDeviceSynchronize();
printf("Done in %f seconds!\n", cpuSecond() - t);
//Run host verification
printf("Computing simulation on the CPU...\n");
t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
verify(particles_h);
}
printf("Done in %f seconds!\n", cpuSecond() - t);
//Copy yd from device to xh, then compare that xh and yh are equal
printf("Copying from device and comparing the output for device and host\n");
cudaMemcpy(intermediate_h, particles_d, NUM_PARTICLES*sizeof(particle), cudaMemcpyDeviceToHost);
compare(particles_h, intermediate_h, 1e-6);
cudaFree(particles_d);
//free(particles_h); free(intermediate_h);
return 0;
} | code for sm_80
Function : _Z15particle_kernelP8particle
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1869f, PT ; /* 0x0001869f0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64+0xc] ; /* 0x00000c0402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x000f28000c1e1900 */
/*00c0*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000f68000c1e1900 */
/*00d0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000f28000c1e1900 */
/*00e0*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000f62000c1e1900 */
/*00f0*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x004e300000201800 */
/*0100*/ F2F.F64.F32 R6, R10 ; /* 0x0000000a00067310 */
/* 0x008e700000201800 */
/*0110*/ F2F.F64.F32 R8, R11 ; /* 0x0000000b00087310 */
/* 0x010ea20000201800 */
/*0120*/ DMUL R4, R4, c[0x2][0x0] ; /* 0x0080000004047a28 */
/* 0x001e080000000000 */
/*0130*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x002e4c0000000000 */
/*0140*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001f620000301000 */
/*0150*/ DMUL R8, R8, c[0x2][0x0] ; /* 0x0080000008087a28 */
/* 0x004e0e0000000000 */
/*0160*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x002e700000301000 */
/*0170*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e220000301000 */
/*0180*/ FADD R13, R5, R12 ; /* 0x0000000c050d7221 */
/* 0x020fe20000000000 */
/*0190*/ STG.E [R2.64+0xc], R5 ; /* 0x00000c0502007986 */
/* 0x000fe8000c101904 */
/*01a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*01b0*/ FADD R15, R7, R14 ; /* 0x0000000e070f7221 */
/* 0x002fc60000000000 */
/*01c0*/ STG.E [R2.64+0x10], R7 ; /* 0x0000100702007986 */
/* 0x000fe8000c101904 */
/*01d0*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x000fe2000c101904 */
/*01e0*/ FADD R17, R9, R16 ; /* 0x0000001009117221 */
/* 0x001fc60000000000 */
/*01f0*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe8000c101904 */
/*0200*/ STG.E [R2.64+0x8], R17 ; /* 0x0000081102007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //SAXPY - Single-Precision A*X Plus Y
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 400
#define NUM_PARTICLES 100000
#define NUM_ITERS 1000
struct particle{
float3 pos;
float3 v;
};
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__device__ __host__ void update(struct particle *p){
p->v.x *= (1.0 + 1e-1);
p->v.y *= (1.0 + 1e-1);
p->v.z *= (1.0 + 1e-1);
p->pos.x += p->v.x;
p->pos.y += p->v.y;
p->pos.z += p->v.z;
}
__global__ void particle_kernel(struct particle *particles){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < NUM_PARTICLES){
update(&particles[i]);
}
}
__host__ void verify(struct particle *particles){
for(int i = 0; i < NUM_PARTICLES; i++){
update(&particles[i]);
}
}
__host__ void compare(struct particle *a, struct particle *b, float moe){
//Compare a to b using a distance metric on particle points s.t. |a - b| <= moe
for (int i = 0; i < NUM_PARTICLES; i++){
float len = sqrt(pow((a[i].pos.x - b[i].pos.x), 2) + pow((a[i].pos.y - b[i].pos.y), 2) + pow((a[i].pos.z - b[i].pos.z), 2));
if (len >= moe){
printf("Comparison failed w. %f accuracy.\n", moe);
return;
}
}
printf("Comparison successful w. %f accuracy.\n", moe);
}
int main(){
//Host address, intermediate memory and device adderss
particle particles_h[NUM_PARTICLES], intermediate_h[NUM_PARTICLES];
particle *particles_d = 0;
//Allocate host memory
//particles_h = (particle *) malloc(NUM_PARTICLES*sizeof(particle));
//intermediate_h = (particle *) malloc(ARRANUM_PARTICLESY_SIZE*sizeof(particle));
// Allocate device memory
cudaMalloc(&particles_d, NUM_PARTICLES*sizeof(particle));
//Populate host particles w. some uniformly distributed numbers from [0,1]
for(int i = 0; i < NUM_PARTICLES; i++){
float3 pos = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
float3 v = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
particles_h[i].pos = pos;
particles_h[i].v = v;
//= {pos: pos, v: v};
}
//Copy particles_h to device memory
cudaMemcpy(particles_d, particles_h, NUM_PARTICLES*sizeof(particle), cudaMemcpyHostToDevice);
//Launch kernel
printf("Computing simulation on the GPU...\n");
double t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
particle_kernel <<<(NUM_PARTICLES + BLOCK_SIZE -1)/BLOCK_SIZE, BLOCK_SIZE>>>(particles_d);
}
//Sync
cudaDeviceSynchronize();
printf("Done in %f seconds!\n", cpuSecond() - t);
//Run host verification
printf("Computing simulation on the CPU...\n");
t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
verify(particles_h);
}
printf("Done in %f seconds!\n", cpuSecond() - t);
//Copy yd from device to xh, then compare that xh and yh are equal
printf("Copying from device and comparing the output for device and host\n");
cudaMemcpy(intermediate_h, particles_d, NUM_PARTICLES*sizeof(particle), cudaMemcpyDeviceToHost);
compare(particles_h, intermediate_h, 1e-6);
cudaFree(particles_d);
//free(particles_h); free(intermediate_h);
return 0;
} | .file "tmpxft_0016144a_00000000-6_exercise_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z6updateP8particle
.type _Z6updateP8particle, @function
_Z6updateP8particle:
.LFB2058:
.cfi_startproc
endbr64
pxor %xmm2, %xmm2
cvtss2sd 12(%rdi), %xmm2
movsd .LC1(%rip), %xmm3
mulsd %xmm3, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, 12(%rdi)
pxor %xmm1, %xmm1
cvtss2sd 16(%rdi), %xmm1
mulsd %xmm3, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 16(%rdi)
pxor %xmm0, %xmm0
cvtss2sd 20(%rdi), %xmm0
mulsd %xmm3, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 20(%rdi)
addss (%rdi), %xmm2
movss %xmm2, (%rdi)
addss 4(%rdi), %xmm1
movss %xmm1, 4(%rdi)
addss 8(%rdi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2058:
.size _Z6updateP8particle, .-_Z6updateP8particle
.globl _Z6verifyP8particle
.type _Z6verifyP8particle, @function
_Z6verifyP8particle:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %rbx
leaq 2400000(%rdi), %rbp
.L9:
movq %rbx, %rdi
call _Z6updateP8particle
addq $24, %rbx
cmpq %rbp, %rbx
jne .L9
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z6verifyP8particle, .-_Z6verifyP8particle
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Comparison failed w. %f accuracy.\n"
.align 8
.LC3:
.string "Comparison successful w. %f accuracy.\n"
.text
.globl _Z7compareP8particleS0_f
.type _Z7compareP8particleS0_f, @function
_Z7compareP8particleS0_f:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movaps %xmm0, %xmm3
movq %rdi, %rax
addq $2400000, %rdi
.L16:
movss (%rax), %xmm0
subss (%rsi), %xmm0
cvtss2sd %xmm0, %xmm0
movss 4(%rax), %xmm2
subss 4(%rsi), %xmm2
cvtss2sd %xmm2, %xmm2
movss 8(%rax), %xmm1
subss 8(%rsi), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm0
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
cvtsd2ss %xmm0, %xmm0
comiss %xmm3, %xmm0
jnb .L21
addq $24, %rax
addq $24, %rsi
cmpq %rdi, %rax
jne .L16
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L12
.L21:
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L12:
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z7compareP8particleS0_f, .-_Z7compareP8particleS0_f
.globl _Z43__device_stub__Z15particle_kernelP8particleP8particle
.type _Z43__device_stub__Z15particle_kernelP8particleP8particle, @function
_Z43__device_stub__Z15particle_kernelP8particleP8particle:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15particle_kernelP8particle(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z43__device_stub__Z15particle_kernelP8particleP8particle, .-_Z43__device_stub__Z15particle_kernelP8particleP8particle
.globl _Z15particle_kernelP8particle
.type _Z15particle_kernelP8particle, @function
_Z15particle_kernelP8particle:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z15particle_kernelP8particleP8particle
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15particle_kernelP8particle, .-_Z15particle_kernelP8particle
.section .rodata.str1.8
.align 8
.LC5:
.string "Computing simulation on the GPU...\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Done in %f seconds!\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Computing simulation on the CPU...\n"
.align 8
.LC8:
.string "Copying from device and comparing the output for device and host\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -4796416(%rsp), %r11
.cfi_def_cfa 11, 4796472
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3656, %rsp
.cfi_def_cfa_offset 4800128
movq %fs:40, %rax
movq %rax, 4800056(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $2400000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rbx
leaq 2400048(%rsp), %r15
.L31:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movd %xmm1, %r12d
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
movd %xmm2, %r13d
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm3, %xmm3
cvtsd2ss %xmm0, %xmm3
movd %xmm3, %r14d
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm4, %xmm4
cvtsd2ss %xmm0, %xmm4
movss %xmm4, 8(%rsp)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm5, %xmm5
cvtsd2ss %xmm0, %xmm5
movd %xmm5, %ebp
call rand@PLT
movl %r14d, (%rbx)
movl %r13d, 4(%rbx)
movl %r12d, 8(%rbx)
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%rbx)
movl %ebp, 16(%rbx)
movss 8(%rsp), %xmm4
movss %xmm4, 20(%rbx)
addq $24, %rbx
cmpq %r15, %rbx
jne .L31
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $2400000, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl $1000, %ebx
jmp .L33
.L32:
subl $1, %ebx
je .L40
.L33:
movl $400, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $250, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq 16(%rsp), %rdi
call _Z43__device_stub__Z15particle_kernelP8particleP8particle
jmp .L32
.L40:
call cudaDeviceSynchronize@PLT
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl $1000, %ebx
leaq 48(%rsp), %rbp
.L34:
movq %rbp, %rdi
call _Z6verifyP8particle
subl $1, %ebx
jne .L34
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 2400048(%rsp), %rbx
movl $2, %ecx
movl $2400000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movss .LC9(%rip), %xmm0
movq %rbx, %rsi
call _Z7compareP8particleS0_f
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4800056(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $4800072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z15particle_kernelP8particle"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z15particle_kernelP8particle(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC1:
.long -1717986918
.long 1072798105
.align 8
.LC4:
.long 0
.long 1079574528
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //SAXPY - Single-Precision A*X Plus Y
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 400
#define NUM_PARTICLES 100000
#define NUM_ITERS 1000
struct particle{
float3 pos;
float3 v;
};
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__device__ __host__ void update(struct particle *p){
p->v.x *= (1.0 + 1e-1);
p->v.y *= (1.0 + 1e-1);
p->v.z *= (1.0 + 1e-1);
p->pos.x += p->v.x;
p->pos.y += p->v.y;
p->pos.z += p->v.z;
}
__global__ void particle_kernel(struct particle *particles){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < NUM_PARTICLES){
update(&particles[i]);
}
}
__host__ void verify(struct particle *particles){
for(int i = 0; i < NUM_PARTICLES; i++){
update(&particles[i]);
}
}
__host__ void compare(struct particle *a, struct particle *b, float moe){
//Compare a to b using a distance metric on particle points s.t. |a - b| <= moe
for (int i = 0; i < NUM_PARTICLES; i++){
float len = sqrt(pow((a[i].pos.x - b[i].pos.x), 2) + pow((a[i].pos.y - b[i].pos.y), 2) + pow((a[i].pos.z - b[i].pos.z), 2));
if (len >= moe){
printf("Comparison failed w. %f accuracy.\n", moe);
return;
}
}
printf("Comparison successful w. %f accuracy.\n", moe);
}
int main(){
//Host address, intermediate memory and device adderss
particle particles_h[NUM_PARTICLES], intermediate_h[NUM_PARTICLES];
particle *particles_d = 0;
//Allocate host memory
//particles_h = (particle *) malloc(NUM_PARTICLES*sizeof(particle));
//intermediate_h = (particle *) malloc(ARRANUM_PARTICLESY_SIZE*sizeof(particle));
// Allocate device memory
cudaMalloc(&particles_d, NUM_PARTICLES*sizeof(particle));
//Populate host particles w. some uniformly distributed numbers from [0,1]
for(int i = 0; i < NUM_PARTICLES; i++){
float3 pos = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
float3 v = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
particles_h[i].pos = pos;
particles_h[i].v = v;
//= {pos: pos, v: v};
}
//Copy particles_h to device memory
cudaMemcpy(particles_d, particles_h, NUM_PARTICLES*sizeof(particle), cudaMemcpyHostToDevice);
//Launch kernel
printf("Computing simulation on the GPU...\n");
double t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
particle_kernel <<<(NUM_PARTICLES + BLOCK_SIZE -1)/BLOCK_SIZE, BLOCK_SIZE>>>(particles_d);
}
//Sync
cudaDeviceSynchronize();
printf("Done in %f seconds!\n", cpuSecond() - t);
//Run host verification
printf("Computing simulation on the CPU...\n");
t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
verify(particles_h);
}
printf("Done in %f seconds!\n", cpuSecond() - t);
//Copy yd from device to xh, then compare that xh and yh are equal
printf("Copying from device and comparing the output for device and host\n");
cudaMemcpy(intermediate_h, particles_d, NUM_PARTICLES*sizeof(particle), cudaMemcpyDeviceToHost);
compare(particles_h, intermediate_h, 1e-6);
cudaFree(particles_d);
//free(particles_h); free(intermediate_h);
return 0;
} | //SAXPY - Single-Precision A*X Plus Y
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 400
#define NUM_PARTICLES 100000
#define NUM_ITERS 1000
struct particle{
float3 pos;
float3 v;
};
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__device__ __host__ void update(struct particle *p){
p->v.x *= (1.0 + 1e-1);
p->v.y *= (1.0 + 1e-1);
p->v.z *= (1.0 + 1e-1);
p->pos.x += p->v.x;
p->pos.y += p->v.y;
p->pos.z += p->v.z;
}
__global__ void particle_kernel(struct particle *particles){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < NUM_PARTICLES){
update(&particles[i]);
}
}
__host__ void verify(struct particle *particles){
for(int i = 0; i < NUM_PARTICLES; i++){
update(&particles[i]);
}
}
__host__ void compare(struct particle *a, struct particle *b, float moe){
//Compare a to b using a distance metric on particle points s.t. |a - b| <= moe
for (int i = 0; i < NUM_PARTICLES; i++){
float len = sqrt(pow((a[i].pos.x - b[i].pos.x), 2) + pow((a[i].pos.y - b[i].pos.y), 2) + pow((a[i].pos.z - b[i].pos.z), 2));
if (len >= moe){
printf("Comparison failed w. %f accuracy.\n", moe);
return;
}
}
printf("Comparison successful w. %f accuracy.\n", moe);
}
int main(){
//Host address, intermediate memory and device adderss
particle particles_h[NUM_PARTICLES], intermediate_h[NUM_PARTICLES];
particle *particles_d = 0;
//Allocate host memory
//particles_h = (particle *) malloc(NUM_PARTICLES*sizeof(particle));
//intermediate_h = (particle *) malloc(ARRANUM_PARTICLESY_SIZE*sizeof(particle));
// Allocate device memory
hipMalloc(&particles_d, NUM_PARTICLES*sizeof(particle));
//Populate host particles w. some uniformly distributed numbers from [0,1]
for(int i = 0; i < NUM_PARTICLES; i++){
float3 pos = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
float3 v = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
particles_h[i].pos = pos;
particles_h[i].v = v;
//= {pos: pos, v: v};
}
//Copy particles_h to device memory
hipMemcpy(particles_d, particles_h, NUM_PARTICLES*sizeof(particle), hipMemcpyHostToDevice);
//Launch kernel
printf("Computing simulation on the GPU...\n");
double t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
particle_kernel <<<(NUM_PARTICLES + BLOCK_SIZE -1)/BLOCK_SIZE, BLOCK_SIZE>>>(particles_d);
}
//Sync
hipDeviceSynchronize();
printf("Done in %f seconds!\n", cpuSecond() - t);
//Run host verification
printf("Computing simulation on the CPU...\n");
t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
verify(particles_h);
}
printf("Done in %f seconds!\n", cpuSecond() - t);
//Copy yd from device to xh, then compare that xh and yh are equal
printf("Copying from device and comparing the output for device and host\n");
hipMemcpy(intermediate_h, particles_d, NUM_PARTICLES*sizeof(particle), hipMemcpyDeviceToHost);
compare(particles_h, intermediate_h, 1e-6);
hipFree(particles_d);
//free(particles_h); free(intermediate_h);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //SAXPY - Single-Precision A*X Plus Y
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 400
#define NUM_PARTICLES 100000
#define NUM_ITERS 1000
struct particle{
float3 pos;
float3 v;
};
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__device__ __host__ void update(struct particle *p){
p->v.x *= (1.0 + 1e-1);
p->v.y *= (1.0 + 1e-1);
p->v.z *= (1.0 + 1e-1);
p->pos.x += p->v.x;
p->pos.y += p->v.y;
p->pos.z += p->v.z;
}
__global__ void particle_kernel(struct particle *particles){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < NUM_PARTICLES){
update(&particles[i]);
}
}
__host__ void verify(struct particle *particles){
for(int i = 0; i < NUM_PARTICLES; i++){
update(&particles[i]);
}
}
__host__ void compare(struct particle *a, struct particle *b, float moe){
//Compare a to b using a distance metric on particle points s.t. |a - b| <= moe
for (int i = 0; i < NUM_PARTICLES; i++){
float len = sqrt(pow((a[i].pos.x - b[i].pos.x), 2) + pow((a[i].pos.y - b[i].pos.y), 2) + pow((a[i].pos.z - b[i].pos.z), 2));
if (len >= moe){
printf("Comparison failed w. %f accuracy.\n", moe);
return;
}
}
printf("Comparison successful w. %f accuracy.\n", moe);
}
int main(){
//Host address, intermediate memory and device adderss
particle particles_h[NUM_PARTICLES], intermediate_h[NUM_PARTICLES];
particle *particles_d = 0;
//Allocate host memory
//particles_h = (particle *) malloc(NUM_PARTICLES*sizeof(particle));
//intermediate_h = (particle *) malloc(ARRANUM_PARTICLESY_SIZE*sizeof(particle));
// Allocate device memory
hipMalloc(&particles_d, NUM_PARTICLES*sizeof(particle));
//Populate host particles w. some uniformly distributed numbers from [0,1]
for(int i = 0; i < NUM_PARTICLES; i++){
float3 pos = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
float3 v = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
particles_h[i].pos = pos;
particles_h[i].v = v;
//= {pos: pos, v: v};
}
//Copy particles_h to device memory
hipMemcpy(particles_d, particles_h, NUM_PARTICLES*sizeof(particle), hipMemcpyHostToDevice);
//Launch kernel
printf("Computing simulation on the GPU...\n");
double t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
particle_kernel <<<(NUM_PARTICLES + BLOCK_SIZE -1)/BLOCK_SIZE, BLOCK_SIZE>>>(particles_d);
}
//Sync
hipDeviceSynchronize();
printf("Done in %f seconds!\n", cpuSecond() - t);
//Run host verification
printf("Computing simulation on the CPU...\n");
t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
verify(particles_h);
}
printf("Done in %f seconds!\n", cpuSecond() - t);
//Copy yd from device to xh, then compare that xh and yh are equal
printf("Copying from device and comparing the output for device and host\n");
hipMemcpy(intermediate_h, particles_d, NUM_PARTICLES*sizeof(particle), hipMemcpyDeviceToHost);
compare(particles_h, intermediate_h, 1e-6);
hipFree(particles_d);
//free(particles_h); free(intermediate_h);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15particle_kernelP8particle
.globl _Z15particle_kernelP8particle
.p2align 8
.type _Z15particle_kernelP8particle,@function
_Z15particle_kernelP8particle:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x186a0, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[4:5], null, v1, 24, s[0:1]
s_mov_b32 s1, 0x3ff19999
s_mov_b32 s0, 0x9999999a
s_clause 0x1
global_load_b128 v[0:3], v[4:5], off
global_load_b64 v[6:7], v[4:5], off offset:16
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[8:9], v3
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v6
v_cvt_f64_f32_e32 v[6:7], v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[8:9], v[8:9], s[0:1]
v_mul_f64 v[10:11], v[10:11], s[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[6:7], v[6:7], s[0:1]
v_cvt_f32_f64_e32 v3, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_f64_e32 v8, v[10:11]
v_cvt_f32_f64_e32 v9, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v0, v0, v3 :: v_dual_add_f32 v1, v1, v8
v_add_f32_e32 v2, v2, v9
s_clause 0x1
global_store_b64 v[4:5], v[8:9], off offset:16
global_store_b128 v[4:5], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15particle_kernelP8particle
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15particle_kernelP8particle, .Lfunc_end0-_Z15particle_kernelP8particle
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15particle_kernelP8particle
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15particle_kernelP8particle.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //SAXPY - Single-Precision A*X Plus Y
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define BLOCK_SIZE 400
#define NUM_PARTICLES 100000
#define NUM_ITERS 1000
struct particle{
float3 pos;
float3 v;
};
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__device__ __host__ void update(struct particle *p){
p->v.x *= (1.0 + 1e-1);
p->v.y *= (1.0 + 1e-1);
p->v.z *= (1.0 + 1e-1);
p->pos.x += p->v.x;
p->pos.y += p->v.y;
p->pos.z += p->v.z;
}
__global__ void particle_kernel(struct particle *particles){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < NUM_PARTICLES){
update(&particles[i]);
}
}
__host__ void verify(struct particle *particles){
for(int i = 0; i < NUM_PARTICLES; i++){
update(&particles[i]);
}
}
__host__ void compare(struct particle *a, struct particle *b, float moe){
//Compare a to b using a distance metric on particle points s.t. |a - b| <= moe
for (int i = 0; i < NUM_PARTICLES; i++){
float len = sqrt(pow((a[i].pos.x - b[i].pos.x), 2) + pow((a[i].pos.y - b[i].pos.y), 2) + pow((a[i].pos.z - b[i].pos.z), 2));
if (len >= moe){
printf("Comparison failed w. %f accuracy.\n", moe);
return;
}
}
printf("Comparison successful w. %f accuracy.\n", moe);
}
int main(){
//Host address, intermediate memory and device adderss
particle particles_h[NUM_PARTICLES], intermediate_h[NUM_PARTICLES];
particle *particles_d = 0;
//Allocate host memory
//particles_h = (particle *) malloc(NUM_PARTICLES*sizeof(particle));
//intermediate_h = (particle *) malloc(ARRANUM_PARTICLESY_SIZE*sizeof(particle));
// Allocate device memory
hipMalloc(&particles_d, NUM_PARTICLES*sizeof(particle));
//Populate host particles w. some uniformly distributed numbers from [0,1]
for(int i = 0; i < NUM_PARTICLES; i++){
float3 pos = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
float3 v = make_float3((rand() % 100)/100.0, (rand() % 100)/100.0, (rand() % 100)/100.0);
particles_h[i].pos = pos;
particles_h[i].v = v;
//= {pos: pos, v: v};
}
//Copy particles_h to device memory
hipMemcpy(particles_d, particles_h, NUM_PARTICLES*sizeof(particle), hipMemcpyHostToDevice);
//Launch kernel
printf("Computing simulation on the GPU...\n");
double t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
particle_kernel <<<(NUM_PARTICLES + BLOCK_SIZE -1)/BLOCK_SIZE, BLOCK_SIZE>>>(particles_d);
}
//Sync
hipDeviceSynchronize();
printf("Done in %f seconds!\n", cpuSecond() - t);
//Run host verification
printf("Computing simulation on the CPU...\n");
t = cpuSecond();
for(int i = 0; i < NUM_ITERS; i++){
verify(particles_h);
}
printf("Done in %f seconds!\n", cpuSecond() - t);
//Copy yd from device to xh, then compare that xh and yh are equal
printf("Copying from device and comparing the output for device and host\n");
hipMemcpy(intermediate_h, particles_d, NUM_PARTICLES*sizeof(particle), hipMemcpyDeviceToHost);
compare(particles_h, intermediate_h, 1e-6);
hipFree(particles_d);
//free(particles_h); free(intermediate_h);
return 0;
} | .text
.file "exercise_3.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6updateP8particle
.LCPI1_0:
.quad 0x3ff199999999999a # double 1.1000000000000001
.text
.globl _Z6updateP8particle
.p2align 4, 0x90
.type _Z6updateP8particle,@function
_Z6updateP8particle: # @_Z6updateP8particle
.cfi_startproc
# %bb.0:
movss 12(%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss 16(%rdi), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss %xmm0, 12(%rdi)
cvtss2sd %xmm2, %xmm2
mulsd %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, 16(%rdi)
movss 20(%rdi), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
mulsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsd2ss %xmm3, %xmm1
movss %xmm1, 20(%rdi)
addss (%rdi), %xmm0
movss %xmm0, (%rdi)
addss 4(%rdi), %xmm2
movss %xmm2, 4(%rdi)
addss 8(%rdi), %xmm1
movss %xmm1, 8(%rdi)
retq
.Lfunc_end1:
.size _Z6updateP8particle, .Lfunc_end1-_Z6updateP8particle
.cfi_endproc
# -- End function
.globl _Z30__device_stub__particle_kernelP8particle # -- Begin function _Z30__device_stub__particle_kernelP8particle
.p2align 4, 0x90
.type _Z30__device_stub__particle_kernelP8particle,@function
_Z30__device_stub__particle_kernelP8particle: # @_Z30__device_stub__particle_kernelP8particle
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15particle_kernelP8particle, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z30__device_stub__particle_kernelP8particle, .Lfunc_end2-_Z30__device_stub__particle_kernelP8particle
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6verifyP8particle
.LCPI3_0:
.quad 0x3ff199999999999a # double 1.1000000000000001
.text
.globl _Z6verifyP8particle
.p2align 4, 0x90
.type _Z6verifyP8particle,@function
_Z6verifyP8particle: # @_Z6verifyP8particle
.cfi_startproc
# %bb.0:
movl $20, %eax
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movss -8(%rdi,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss -4(%rdi,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss %xmm1, -8(%rdi,%rax)
cvtss2sd %xmm2, %xmm2
mulsd %xmm0, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, -4(%rdi,%rax)
movss (%rdi,%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
mulsd %xmm0, %xmm3
cvtsd2ss %xmm3, %xmm3
movss %xmm3, (%rdi,%rax)
addss -20(%rdi,%rax), %xmm1
movss %xmm1, -20(%rdi,%rax)
addss -16(%rdi,%rax), %xmm2
movss %xmm2, -16(%rdi,%rax)
addss -12(%rdi,%rax), %xmm3
movss %xmm3, -12(%rdi,%rax)
addq $24, %rax
cmpq $2400020, %rax # imm = 0x249F14
jne .LBB3_1
# %bb.2:
retq
.Lfunc_end3:
.size _Z6verifyP8particle, .Lfunc_end3-_Z6verifyP8particle
.cfi_endproc
# -- End function
.globl _Z7compareP8particleS0_f # -- Begin function _Z7compareP8particleS0_f
.p2align 4, 0x90
.type _Z7compareP8particleS0_f,@function
_Z7compareP8particleS0_f: # @_Z7compareP8particleS0_f
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps %xmm0, %xmm2
movq %rsi, %rbx
movq %rdi, %r14
movl $8, %r15d
xorl %r13d, %r13d
xorpd %xmm3, %xmm3
xorl %r12d, %r12d
movss %xmm0, 12(%rsp) # 4-byte Spill
.p2align 4, 0x90
.LBB4_2: # %.critedge
# =>This Inner Loop Header: Depth=1
movss -8(%r14,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss -8(%rbx,%r15), %xmm0
movss -4(%r14,%r15), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
subss -4(%rbx,%r15), %xmm1
mulsd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
mulsd %xmm1, %xmm1
addsd %xmm0, %xmm1
movss (%r14,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r15), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
ucomisd %xmm3, %xmm0
jb .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_4: # %call.sqrt
# in Loop: Header=BB4_2 Depth=1
callq sqrt
xorpd %xmm3, %xmm3
movss 12(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
.LBB4_5: # %.critedge.split
# in Loop: Header=BB4_2 Depth=1
cvtsd2ss %xmm0, %xmm0
ucomiss %xmm2, %xmm0
jae .LBB4_6
# %bb.1: # in Loop: Header=BB4_2 Depth=1
cmpq $99999, %r13 # imm = 0x1869F
leaq 1(%r13), %rax
setae %r12b
addq $24, %r15
movq %rax, %r13
cmpq $100000, %rax # imm = 0x186A0
jne .LBB4_2
jmp .LBB4_8
.LBB4_6:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
testb $1, %r12b
je .LBB4_7
.LBB4_8: # %.critedge24
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl $.L.str.1, %edi
movb $1, %al
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB4_7:
.cfi_def_cfa_offset 64
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z7compareP8particleS0_f, .Lfunc_end4-_Z7compareP8particleS0_f
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x4059000000000000 # double 100
.LCPI5_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI5_2:
.quad 0x3ff199999999999a # double 1.1000000000000001
.LCPI5_4:
.quad 0x3eb0c6f7a0000000 # double 9.9999999747524271E-7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_3:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $4800120, %rsp # imm = 0x493E78
.cfi_def_cfa_offset 4800176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $2400000, %esi # imm = 0x249F00
callq hipMalloc
movl $20, %ebx
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI5_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, 16(%rsp) # 16-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps 16(%rsp), %xmm1 # 16-byte Reload
unpcklps %xmm0, %xmm1 # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
movaps %xmm1, 16(%rsp) # 16-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 44(%rsp) # 4-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, 48(%rsp) # 16-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps 48(%rsp), %xmm1 # 16-byte Reload
unpcklps %xmm0, %xmm1 # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
movaps %xmm1, 48(%rsp) # 16-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps 16(%rsp), %xmm1 # 16-byte Reload
movlps %xmm1, 92(%rsp,%rbx)
movss 44(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss %xmm1, 100(%rsp,%rbx)
movaps 48(%rsp), %xmm1 # 16-byte Reload
movlps %xmm1, 104(%rsp,%rbx)
movss %xmm0, 112(%rsp,%rbx)
addq $24, %rbx
cmpq $2400020, %rbx # imm = 0x249F14
jne .LBB5_1
# %bb.2:
movabsq $4294967546, %rbx # imm = 0x1000000FA
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $2400000, %edx # imm = 0x249F00
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
leaq 2400112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 2400120(%rsp), %xmm0
mulsd .LCPI5_1(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 2400112(%rsp), %rax
movq %rax, 48(%rsp) # 8-byte Spill
movl $1000, %r12d # imm = 0x3E8
leaq 150(%rbx), %r15
leaq 80(%rsp), %r13
leaq 72(%rsp), %rbp
leaq 64(%rsp), %r14
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_3 Depth=1
decl %r12d
je .LBB5_6
.LBB5_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=1
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 64(%rsp)
leaq 2400112(%rsp), %rdi
leaq 88(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 2400112(%rsp), %rsi
movl 2400120(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z15particle_kernelP8particle, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_5
.LBB5_6:
xorps %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0 # 8-byte Folded Reload
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
xorl %ebx, %ebx
leaq 2400112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 2400112(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 2400120(%rsp), %xmm0
mulsd .LCPI5_1(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 2400112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 2400112(%rsp), %rax
cvtsi2sdq 2400120(%rsp), %xmm4
mulsd .LCPI5_1(%rip), %xmm4
movsd .LCPI5_2(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB5_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_8 Depth 2
movl $20, %ecx
.p2align 4, 0x90
.LBB5_8: # Parent Loop BB5_7 Depth=1
# => This Inner Loop Header: Depth=2
movss 104(%rsp,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss 108(%rsp,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss %xmm1, 104(%rsp,%rcx)
cvtss2sd %xmm2, %xmm2
mulsd %xmm0, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, 108(%rsp,%rcx)
movss 112(%rsp,%rcx), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
mulsd %xmm0, %xmm3
cvtsd2ss %xmm3, %xmm3
movss %xmm3, 112(%rsp,%rcx)
addss 92(%rsp,%rcx), %xmm1
movss %xmm1, 92(%rsp,%rcx)
addss 96(%rsp,%rcx), %xmm2
movss %xmm2, 96(%rsp,%rcx)
addss 100(%rsp,%rcx), %xmm3
movss %xmm3, 100(%rsp,%rcx)
addq $24, %rcx
cmpq $2400020, %rcx # imm = 0x249F14
jne .LBB5_8
# %bb.9: # %_Z6verifyP8particle.exit
# in Loop: Header=BB5_7 Depth=1
incl %ebx
cmpl $1000, %ebx # imm = 0x3E8
jne .LBB5_7
# %bb.10:
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm0, %xmm4
movsd %xmm4, 16(%rsp) # 8-byte Spill
xorl %ebx, %ebx
leaq 2400112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 2400112(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 2400120(%rsp), %xmm0
mulsd .LCPI5_1(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rsp), %rsi
leaq 2400112(%rsp), %rdi
movl $2400000, %edx # imm = 0x249F00
movl $2, %ecx
callq hipMemcpy
movl $8, %r14d
xorps %xmm2, %xmm2
movss .LCPI5_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_12: # %.critedge.i
# =>This Inner Loop Header: Depth=1
movss 104(%rsp,%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss 2400104(%rsp,%r14), %xmm0
movss 108(%rsp,%r14), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
subss 2400108(%rsp,%r14), %xmm1
mulsd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
mulsd %xmm1, %xmm1
addsd %xmm0, %xmm1
movss 112(%rsp,%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss 2400112(%rsp,%r14), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
ucomisd %xmm2, %xmm0
jb .LBB5_14
# %bb.13: # in Loop: Header=BB5_12 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB5_15
.p2align 4, 0x90
.LBB5_14: # %call.sqrt
# in Loop: Header=BB5_12 Depth=1
callq sqrt
movss .LCPI5_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
.LBB5_15: # %.critedge.i.split
# in Loop: Header=BB5_12 Depth=1
cvtsd2ss %xmm0, %xmm0
ucomiss %xmm3, %xmm0
jae .LBB5_16
# %bb.11: # in Loop: Header=BB5_12 Depth=1
cmpq $99999, %rbx # imm = 0x1869F
leaq 1(%rbx), %rax
setae %r15b
addq $24, %r14
movq %rax, %rbx
cmpq $100000, %rax # imm = 0x186A0
jne .LBB5_12
jmp .LBB5_17
.LBB5_16:
movsd .LCPI5_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r15b
je .LBB5_18
.LBB5_17: # %.critedge24.i
movsd .LCPI5_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
.LBB5_18: # %_Z7compareP8particleS0_f.exit
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4800120, %rsp # imm = 0x493E78
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15particle_kernelP8particle, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15particle_kernelP8particle,@object # @_Z15particle_kernelP8particle
.section .rodata,"a",@progbits
.globl _Z15particle_kernelP8particle
.p2align 3, 0x0
_Z15particle_kernelP8particle:
.quad _Z30__device_stub__particle_kernelP8particle
.size _Z15particle_kernelP8particle, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Comparison failed w. %f accuracy.\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Comparison successful w. %f accuracy.\n"
.size .L.str.1, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Done in %f seconds!\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15particle_kernelP8particle"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Computing simulation on the GPU..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Computing simulation on the CPU..."
.size .Lstr.1, 35
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Copying from device and comparing the output for device and host"
.size .Lstr.2, 65
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__particle_kernelP8particle
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15particle_kernelP8particle
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15particle_kernelP8particle
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1869f, PT ; /* 0x0001869f0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64+0xc] ; /* 0x00000c0402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x000f28000c1e1900 */
/*00c0*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000f68000c1e1900 */
/*00d0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000f28000c1e1900 */
/*00e0*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000f62000c1e1900 */
/*00f0*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x004e300000201800 */
/*0100*/ F2F.F64.F32 R6, R10 ; /* 0x0000000a00067310 */
/* 0x008e700000201800 */
/*0110*/ F2F.F64.F32 R8, R11 ; /* 0x0000000b00087310 */
/* 0x010ea20000201800 */
/*0120*/ DMUL R4, R4, c[0x2][0x0] ; /* 0x0080000004047a28 */
/* 0x001e080000000000 */
/*0130*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x002e4c0000000000 */
/*0140*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001f620000301000 */
/*0150*/ DMUL R8, R8, c[0x2][0x0] ; /* 0x0080000008087a28 */
/* 0x004e0e0000000000 */
/*0160*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x002e700000301000 */
/*0170*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e220000301000 */
/*0180*/ FADD R13, R5, R12 ; /* 0x0000000c050d7221 */
/* 0x020fe20000000000 */
/*0190*/ STG.E [R2.64+0xc], R5 ; /* 0x00000c0502007986 */
/* 0x000fe8000c101904 */
/*01a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*01b0*/ FADD R15, R7, R14 ; /* 0x0000000e070f7221 */
/* 0x002fc60000000000 */
/*01c0*/ STG.E [R2.64+0x10], R7 ; /* 0x0000100702007986 */
/* 0x000fe8000c101904 */
/*01d0*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x000fe2000c101904 */
/*01e0*/ FADD R17, R9, R16 ; /* 0x0000001009117221 */
/* 0x001fc60000000000 */
/*01f0*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe8000c101904 */
/*0200*/ STG.E [R2.64+0x8], R17 ; /* 0x0000081102007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15particle_kernelP8particle
.globl _Z15particle_kernelP8particle
.p2align 8
.type _Z15particle_kernelP8particle,@function
_Z15particle_kernelP8particle:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x186a0, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[4:5], null, v1, 24, s[0:1]
s_mov_b32 s1, 0x3ff19999
s_mov_b32 s0, 0x9999999a
s_clause 0x1
global_load_b128 v[0:3], v[4:5], off
global_load_b64 v[6:7], v[4:5], off offset:16
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[8:9], v3
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v6
v_cvt_f64_f32_e32 v[6:7], v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[8:9], v[8:9], s[0:1]
v_mul_f64 v[10:11], v[10:11], s[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[6:7], v[6:7], s[0:1]
v_cvt_f32_f64_e32 v3, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_f64_e32 v8, v[10:11]
v_cvt_f32_f64_e32 v9, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v0, v0, v3 :: v_dual_add_f32 v1, v1, v8
v_add_f32_e32 v2, v2, v9
s_clause 0x1
global_store_b64 v[4:5], v[8:9], off offset:16
global_store_b128 v[4:5], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15particle_kernelP8particle
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15particle_kernelP8particle, .Lfunc_end0-_Z15particle_kernelP8particle
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15particle_kernelP8particle
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15particle_kernelP8particle.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016144a_00000000-6_exercise_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z6updateP8particle
.type _Z6updateP8particle, @function
_Z6updateP8particle:
.LFB2058:
.cfi_startproc
endbr64
pxor %xmm2, %xmm2
cvtss2sd 12(%rdi), %xmm2
movsd .LC1(%rip), %xmm3
mulsd %xmm3, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, 12(%rdi)
pxor %xmm1, %xmm1
cvtss2sd 16(%rdi), %xmm1
mulsd %xmm3, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 16(%rdi)
pxor %xmm0, %xmm0
cvtss2sd 20(%rdi), %xmm0
mulsd %xmm3, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 20(%rdi)
addss (%rdi), %xmm2
movss %xmm2, (%rdi)
addss 4(%rdi), %xmm1
movss %xmm1, 4(%rdi)
addss 8(%rdi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2058:
.size _Z6updateP8particle, .-_Z6updateP8particle
.globl _Z6verifyP8particle
.type _Z6verifyP8particle, @function
_Z6verifyP8particle:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %rbx
leaq 2400000(%rdi), %rbp
.L9:
movq %rbx, %rdi
call _Z6updateP8particle
addq $24, %rbx
cmpq %rbp, %rbx
jne .L9
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z6verifyP8particle, .-_Z6verifyP8particle
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Comparison failed w. %f accuracy.\n"
.align 8
.LC3:
.string "Comparison successful w. %f accuracy.\n"
.text
.globl _Z7compareP8particleS0_f
.type _Z7compareP8particleS0_f, @function
_Z7compareP8particleS0_f:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movaps %xmm0, %xmm3
movq %rdi, %rax
addq $2400000, %rdi
.L16:
movss (%rax), %xmm0
subss (%rsi), %xmm0
cvtss2sd %xmm0, %xmm0
movss 4(%rax), %xmm2
subss 4(%rsi), %xmm2
cvtss2sd %xmm2, %xmm2
movss 8(%rax), %xmm1
subss 8(%rsi), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm0
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
cvtsd2ss %xmm0, %xmm0
comiss %xmm3, %xmm0
jnb .L21
addq $24, %rax
addq $24, %rsi
cmpq %rdi, %rax
jne .L16
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L12
.L21:
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L12:
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z7compareP8particleS0_f, .-_Z7compareP8particleS0_f
.globl _Z43__device_stub__Z15particle_kernelP8particleP8particle
.type _Z43__device_stub__Z15particle_kernelP8particleP8particle, @function
_Z43__device_stub__Z15particle_kernelP8particleP8particle:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15particle_kernelP8particle(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z43__device_stub__Z15particle_kernelP8particleP8particle, .-_Z43__device_stub__Z15particle_kernelP8particleP8particle
.globl _Z15particle_kernelP8particle
.type _Z15particle_kernelP8particle, @function
_Z15particle_kernelP8particle:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z15particle_kernelP8particleP8particle
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15particle_kernelP8particle, .-_Z15particle_kernelP8particle
.section .rodata.str1.8
.align 8
.LC5:
.string "Computing simulation on the GPU...\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Done in %f seconds!\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Computing simulation on the CPU...\n"
.align 8
.LC8:
.string "Copying from device and comparing the output for device and host\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -4796416(%rsp), %r11
.cfi_def_cfa 11, 4796472
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3656, %rsp
.cfi_def_cfa_offset 4800128
movq %fs:40, %rax
movq %rax, 4800056(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $2400000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rbx
leaq 2400048(%rsp), %r15
.L31:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movd %xmm1, %r12d
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
movd %xmm2, %r13d
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm3, %xmm3
cvtsd2ss %xmm0, %xmm3
movd %xmm3, %r14d
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm4, %xmm4
cvtsd2ss %xmm0, %xmm4
movss %xmm4, 8(%rsp)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
pxor %xmm5, %xmm5
cvtsd2ss %xmm0, %xmm5
movd %xmm5, %ebp
call rand@PLT
movl %r14d, (%rbx)
movl %r13d, 4(%rbx)
movl %r12d, 8(%rbx)
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%rbx)
movl %ebp, 16(%rbx)
movss 8(%rsp), %xmm4
movss %xmm4, 20(%rbx)
addq $24, %rbx
cmpq %r15, %rbx
jne .L31
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $2400000, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl $1000, %ebx
jmp .L33
.L32:
subl $1, %ebx
je .L40
.L33:
movl $400, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $250, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq 16(%rsp), %rdi
call _Z43__device_stub__Z15particle_kernelP8particleP8particle
jmp .L32
.L40:
call cudaDeviceSynchronize@PLT
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl $1000, %ebx
leaq 48(%rsp), %rbp
.L34:
movq %rbp, %rdi
call _Z6verifyP8particle
subl $1, %ebx
jne .L34
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 2400048(%rsp), %rbx
movl $2, %ecx
movl $2400000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movss .LC9(%rip), %xmm0
movq %rbx, %rsi
call _Z7compareP8particleS0_f
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4800056(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $4800072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z15particle_kernelP8particle"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z15particle_kernelP8particle(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC1:
.long -1717986918
.long 1072798105
.align 8
.LC4:
.long 0
.long 1079574528
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_3.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6updateP8particle
.LCPI1_0:
.quad 0x3ff199999999999a # double 1.1000000000000001
.text
.globl _Z6updateP8particle
.p2align 4, 0x90
.type _Z6updateP8particle,@function
_Z6updateP8particle: # @_Z6updateP8particle
.cfi_startproc
# %bb.0:
movss 12(%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss 16(%rdi), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss %xmm0, 12(%rdi)
cvtss2sd %xmm2, %xmm2
mulsd %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, 16(%rdi)
movss 20(%rdi), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
mulsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsd2ss %xmm3, %xmm1
movss %xmm1, 20(%rdi)
addss (%rdi), %xmm0
movss %xmm0, (%rdi)
addss 4(%rdi), %xmm2
movss %xmm2, 4(%rdi)
addss 8(%rdi), %xmm1
movss %xmm1, 8(%rdi)
retq
.Lfunc_end1:
.size _Z6updateP8particle, .Lfunc_end1-_Z6updateP8particle
.cfi_endproc
# -- End function
.globl _Z30__device_stub__particle_kernelP8particle # -- Begin function _Z30__device_stub__particle_kernelP8particle
.p2align 4, 0x90
.type _Z30__device_stub__particle_kernelP8particle,@function
_Z30__device_stub__particle_kernelP8particle: # @_Z30__device_stub__particle_kernelP8particle
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15particle_kernelP8particle, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z30__device_stub__particle_kernelP8particle, .Lfunc_end2-_Z30__device_stub__particle_kernelP8particle
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6verifyP8particle
.LCPI3_0:
.quad 0x3ff199999999999a # double 1.1000000000000001
.text
.globl _Z6verifyP8particle
.p2align 4, 0x90
.type _Z6verifyP8particle,@function
_Z6verifyP8particle: # @_Z6verifyP8particle
.cfi_startproc
# %bb.0:
movl $20, %eax
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movss -8(%rdi,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss -4(%rdi,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss %xmm1, -8(%rdi,%rax)
cvtss2sd %xmm2, %xmm2
mulsd %xmm0, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, -4(%rdi,%rax)
movss (%rdi,%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
mulsd %xmm0, %xmm3
cvtsd2ss %xmm3, %xmm3
movss %xmm3, (%rdi,%rax)
addss -20(%rdi,%rax), %xmm1
movss %xmm1, -20(%rdi,%rax)
addss -16(%rdi,%rax), %xmm2
movss %xmm2, -16(%rdi,%rax)
addss -12(%rdi,%rax), %xmm3
movss %xmm3, -12(%rdi,%rax)
addq $24, %rax
cmpq $2400020, %rax # imm = 0x249F14
jne .LBB3_1
# %bb.2:
retq
.Lfunc_end3:
.size _Z6verifyP8particle, .Lfunc_end3-_Z6verifyP8particle
.cfi_endproc
# -- End function
.globl _Z7compareP8particleS0_f # -- Begin function _Z7compareP8particleS0_f
.p2align 4, 0x90
.type _Z7compareP8particleS0_f,@function
_Z7compareP8particleS0_f: # @_Z7compareP8particleS0_f
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps %xmm0, %xmm2
movq %rsi, %rbx
movq %rdi, %r14
movl $8, %r15d
xorl %r13d, %r13d
xorpd %xmm3, %xmm3
xorl %r12d, %r12d
movss %xmm0, 12(%rsp) # 4-byte Spill
.p2align 4, 0x90
.LBB4_2: # %.critedge
# =>This Inner Loop Header: Depth=1
movss -8(%r14,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss -8(%rbx,%r15), %xmm0
movss -4(%r14,%r15), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
subss -4(%rbx,%r15), %xmm1
mulsd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
mulsd %xmm1, %xmm1
addsd %xmm0, %xmm1
movss (%r14,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r15), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
ucomisd %xmm3, %xmm0
jb .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_4: # %call.sqrt
# in Loop: Header=BB4_2 Depth=1
callq sqrt
xorpd %xmm3, %xmm3
movss 12(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
.LBB4_5: # %.critedge.split
# in Loop: Header=BB4_2 Depth=1
cvtsd2ss %xmm0, %xmm0
ucomiss %xmm2, %xmm0
jae .LBB4_6
# %bb.1: # in Loop: Header=BB4_2 Depth=1
cmpq $99999, %r13 # imm = 0x1869F
leaq 1(%r13), %rax
setae %r12b
addq $24, %r15
movq %rax, %r13
cmpq $100000, %rax # imm = 0x186A0
jne .LBB4_2
jmp .LBB4_8
.LBB4_6:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
testb $1, %r12b
je .LBB4_7
.LBB4_8: # %.critedge24
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl $.L.str.1, %edi
movb $1, %al
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB4_7:
.cfi_def_cfa_offset 64
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z7compareP8particleS0_f, .Lfunc_end4-_Z7compareP8particleS0_f
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x4059000000000000 # double 100
.LCPI5_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI5_2:
.quad 0x3ff199999999999a # double 1.1000000000000001
.LCPI5_4:
.quad 0x3eb0c6f7a0000000 # double 9.9999999747524271E-7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_3:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $4800120, %rsp # imm = 0x493E78
.cfi_def_cfa_offset 4800176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $2400000, %esi # imm = 0x249F00
callq hipMalloc
movl $20, %ebx
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI5_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, 16(%rsp) # 16-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps 16(%rsp), %xmm1 # 16-byte Reload
unpcklps %xmm0, %xmm1 # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
movaps %xmm1, 16(%rsp) # 16-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 44(%rsp) # 4-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, 48(%rsp) # 16-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps 48(%rsp), %xmm1 # 16-byte Reload
unpcklps %xmm0, %xmm1 # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
movaps %xmm1, 48(%rsp) # 16-byte Spill
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps 16(%rsp), %xmm1 # 16-byte Reload
movlps %xmm1, 92(%rsp,%rbx)
movss 44(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss %xmm1, 100(%rsp,%rbx)
movaps 48(%rsp), %xmm1 # 16-byte Reload
movlps %xmm1, 104(%rsp,%rbx)
movss %xmm0, 112(%rsp,%rbx)
addq $24, %rbx
cmpq $2400020, %rbx # imm = 0x249F14
jne .LBB5_1
# %bb.2:
movabsq $4294967546, %rbx # imm = 0x1000000FA
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $2400000, %edx # imm = 0x249F00
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
leaq 2400112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 2400120(%rsp), %xmm0
mulsd .LCPI5_1(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 2400112(%rsp), %rax
movq %rax, 48(%rsp) # 8-byte Spill
movl $1000, %r12d # imm = 0x3E8
leaq 150(%rbx), %r15
leaq 80(%rsp), %r13
leaq 72(%rsp), %rbp
leaq 64(%rsp), %r14
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_3 Depth=1
decl %r12d
je .LBB5_6
.LBB5_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=1
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 64(%rsp)
leaq 2400112(%rsp), %rdi
leaq 88(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 2400112(%rsp), %rsi
movl 2400120(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z15particle_kernelP8particle, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_5
.LBB5_6:
xorps %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0 # 8-byte Folded Reload
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
xorl %ebx, %ebx
leaq 2400112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 2400112(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 2400120(%rsp), %xmm0
mulsd .LCPI5_1(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 2400112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 2400112(%rsp), %rax
cvtsi2sdq 2400120(%rsp), %xmm4
mulsd .LCPI5_1(%rip), %xmm4
movsd .LCPI5_2(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB5_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_8 Depth 2
movl $20, %ecx
.p2align 4, 0x90
.LBB5_8: # Parent Loop BB5_7 Depth=1
# => This Inner Loop Header: Depth=2
movss 104(%rsp,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss 108(%rsp,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss %xmm1, 104(%rsp,%rcx)
cvtss2sd %xmm2, %xmm2
mulsd %xmm0, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, 108(%rsp,%rcx)
movss 112(%rsp,%rcx), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
mulsd %xmm0, %xmm3
cvtsd2ss %xmm3, %xmm3
movss %xmm3, 112(%rsp,%rcx)
addss 92(%rsp,%rcx), %xmm1
movss %xmm1, 92(%rsp,%rcx)
addss 96(%rsp,%rcx), %xmm2
movss %xmm2, 96(%rsp,%rcx)
addss 100(%rsp,%rcx), %xmm3
movss %xmm3, 100(%rsp,%rcx)
addq $24, %rcx
cmpq $2400020, %rcx # imm = 0x249F14
jne .LBB5_8
# %bb.9: # %_Z6verifyP8particle.exit
# in Loop: Header=BB5_7 Depth=1
incl %ebx
cmpl $1000, %ebx # imm = 0x3E8
jne .LBB5_7
# %bb.10:
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm0, %xmm4
movsd %xmm4, 16(%rsp) # 8-byte Spill
xorl %ebx, %ebx
leaq 2400112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 2400112(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 2400120(%rsp), %xmm0
mulsd .LCPI5_1(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rsp), %rsi
leaq 2400112(%rsp), %rdi
movl $2400000, %edx # imm = 0x249F00
movl $2, %ecx
callq hipMemcpy
movl $8, %r14d
xorps %xmm2, %xmm2
movss .LCPI5_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_12: # %.critedge.i
# =>This Inner Loop Header: Depth=1
movss 104(%rsp,%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss 2400104(%rsp,%r14), %xmm0
movss 108(%rsp,%r14), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
subss 2400108(%rsp,%r14), %xmm1
mulsd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
mulsd %xmm1, %xmm1
addsd %xmm0, %xmm1
movss 112(%rsp,%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss 2400112(%rsp,%r14), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
ucomisd %xmm2, %xmm0
jb .LBB5_14
# %bb.13: # in Loop: Header=BB5_12 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB5_15
.p2align 4, 0x90
.LBB5_14: # %call.sqrt
# in Loop: Header=BB5_12 Depth=1
callq sqrt
movss .LCPI5_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
.LBB5_15: # %.critedge.i.split
# in Loop: Header=BB5_12 Depth=1
cvtsd2ss %xmm0, %xmm0
ucomiss %xmm3, %xmm0
jae .LBB5_16
# %bb.11: # in Loop: Header=BB5_12 Depth=1
cmpq $99999, %rbx # imm = 0x1869F
leaq 1(%rbx), %rax
setae %r15b
addq $24, %r14
movq %rax, %rbx
cmpq $100000, %rax # imm = 0x186A0
jne .LBB5_12
jmp .LBB5_17
.LBB5_16:
movsd .LCPI5_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r15b
je .LBB5_18
.LBB5_17: # %.critedge24.i
movsd .LCPI5_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
.LBB5_18: # %_Z7compareP8particleS0_f.exit
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4800120, %rsp # imm = 0x493E78
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15particle_kernelP8particle, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15particle_kernelP8particle,@object # @_Z15particle_kernelP8particle
.section .rodata,"a",@progbits
.globl _Z15particle_kernelP8particle
.p2align 3, 0x0
_Z15particle_kernelP8particle:
.quad _Z30__device_stub__particle_kernelP8particle
.size _Z15particle_kernelP8particle, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Comparison failed w. %f accuracy.\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Comparison successful w. %f accuracy.\n"
.size .L.str.1, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Done in %f seconds!\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15particle_kernelP8particle"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Computing simulation on the GPU..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Computing simulation on the CPU..."
.size .Lstr.1, 35
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Copying from device and comparing the output for device and host"
.size .Lstr.2, 65
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__particle_kernelP8particle
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15particle_kernelP8particle
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void IfThenElse(bool * b, float * x, size_t idxb, size_t idxf, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("From IfThenElse %d, %f, %f\n", b[(idxb-1)*N+i], x[(idxf-1)*N+i], x[(idxf-2)*N+i]);
if (b[(idxb-1)*N+i])
x[(idxf-2)*N+i] = x[(idxf-1)*N+i];
//printf("After IfThenElse %f\n", x[(idxf-2)*N+i]);
}
return;
} | code for sm_80
Function : _Z10IfThenElsePbPfmmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x000fc80000011406 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x184], PT, P0 ; /* 0x0000610009007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R2, P1, RZ, -c[0x0][0x180], RZ ; /* 0x80006000ff027a10 */
/* 0x000fe20007f3e0ff */
/*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, -0x1 ; /* 0xffffffffff0a7424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*00d0*/ IADD3 R0, P0, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004007a10 */
/* 0x000fe20007f1e1ff */
/*00e0*/ IMAD.X R3, RZ, RZ, ~c[0x0][0x184], P1 ; /* 0x80006100ff037624 */
/* 0x000fc600008e06ff */
/*00f0*/ IADD3.X R16, R10, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a107a10 */
/* 0x000fe200007fe4ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x180], R2 ; /* 0x0000600000027a25 */
/* 0x000fe200078e0002 */
/*0110*/ IADD3 R4, P0, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fc60007f1e1ff */
/*0120*/ IMAD R5, R16, c[0x0][0x180], RZ ; /* 0x0000600010057a24 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD R7, R0, c[0x0][0x184], R5 ; /* 0x0000610000077a24 */
/* 0x000fe200078e0205 */
/*0140*/ IADD3.X R5, R10, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000a057a10 */
/* 0x000fc800007fe4ff */
/*0150*/ IADD3 R7, R3, R7, RZ ; /* 0x0000000703077210 */
/* 0x000fe40007ffe0ff */
/*0160*/ IMAD R13, R5, c[0x0][0x180], RZ ; /* 0x00006000050d7a24 */
/* 0x000fe400078e02ff */
/*0170*/ IMAD.WIDE.U32 R10, R4, c[0x0][0x180], R8 ; /* 0x00006000040a7a25 */
/* 0x000fc800078e0008 */
/*0180*/ IMAD R13, R4, c[0x0][0x184], R13 ; /* 0x00006100040d7a24 */
/* 0x000fe200078e020d */
/*0190*/ IADD3 R10, P0, R10, c[0x0][0x160], RZ ; /* 0x000058000a0a7a10 */
/* 0x000fc80007f1e0ff */
/*01a0*/ IADD3.X R11, R11, c[0x0][0x164], R13, P0, !PT ; /* 0x000059000b0b7a10 */
/* 0x000fca00007fe40d */
/*01b0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1100 */
/*01c0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*01d0*/ @P0 IMAD R15, R16, c[0x0][0x180], RZ ; /* 0x00006000100f0a24 */
/* 0x000fe400078e02ff */
/*01e0*/ @P0 IMAD.WIDE.U32 R12, R0, c[0x0][0x180], R8 ; /* 0x00006000000c0a25 */
/* 0x000fc800078e0008 */
/*01f0*/ @P0 IMAD R15, R0, c[0x0][0x184], R15 ; /* 0x00006100000f0a24 */
/* 0x000fe200078e020f */
/*0200*/ @P0 LEA R14, P1, R12, c[0x0][0x168], 0x2 ; /* 0x00005a000c0e0a11 */
/* 0x000fc600078210ff */
/*0210*/ @P0 IMAD.IADD R13, R15, 0x1, R13 ; /* 0x000000010f0d0824 */
/* 0x000fca00078e020d */
/*0220*/ @P0 LEA.HI.X R15, R12, c[0x0][0x16c], R13, 0x2, P1 ; /* 0x00005b000c0f0a11 */
/* 0x000fcc00008f140d */
/*0230*/ @P0 LDG.E R15, [R14.64] ; /* 0x000000040e0f0981 */
/* 0x000ea2000c1e1900 */
/*0240*/ @P0 IADD3 R8, P1, R8, R2, RZ ; /* 0x0000000208080210 */
/* 0x000fca0007f3e0ff */
/*0250*/ @P0 IMAD.X R9, R9, 0x1, R7, P1 ; /* 0x0000000109090824 */
/* 0x000fe200008e0607 */
/*0260*/ @P0 LEA R10, P1, R8, c[0x0][0x168], 0x2 ; /* 0x00005a00080a0a11 */
/* 0x000fc800078210ff */
/*0270*/ @P0 LEA.HI.X R11, R8, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b00080b0a11 */
/* 0x000fe400008f1409 */
/*0280*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fca0000000f00 */
/*0290*/ IMAD R8, R9, c[0x0][0xc], R6 ; /* 0x0000030009087a24 */
/* 0x000fc800078e0206 */
/*02a0*/ IMAD.MOV.U32 R6, RZ, RZ, R8.reuse ; /* 0x000000ffff067224 */
/* 0x100fe200078e0008 */
/*02b0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fe20000011408 */
/*02c0*/ @P0 STG.E [R10.64], R15 ; /* 0x0000000f0a000986 */
/* 0x0041e2000c101904 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fc80003f06070 */
/*02e0*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x184], PT, P0 ; /* 0x0000610009007a0c */
/* 0x000fda0003f06100 */
/*02f0*/ @!P0 BRA 0x160 ; /* 0xfffffe6000008947 */
/* 0x001fea000383ffff */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void IfThenElse(bool * b, float * x, size_t idxb, size_t idxf, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("From IfThenElse %d, %f, %f\n", b[(idxb-1)*N+i], x[(idxf-1)*N+i], x[(idxf-2)*N+i]);
if (b[(idxb-1)*N+i])
x[(idxf-2)*N+i] = x[(idxf-1)*N+i];
//printf("After IfThenElse %f\n", x[(idxf-2)*N+i]);
}
return;
} | .file "tmpxft_00041d3a_00000000-6_IfThenElse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm
.type _Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm, @function
_Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10IfThenElsePbPfmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm, .-_Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm
.globl _Z10IfThenElsePbPfmmm
.type _Z10IfThenElsePbPfmmm, @function
_Z10IfThenElsePbPfmmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10IfThenElsePbPfmmm, .-_Z10IfThenElsePbPfmmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10IfThenElsePbPfmmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10IfThenElsePbPfmmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void IfThenElse(bool * b, float * x, size_t idxb, size_t idxf, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("From IfThenElse %d, %f, %f\n", b[(idxb-1)*N+i], x[(idxf-1)*N+i], x[(idxf-2)*N+i]);
if (b[(idxb-1)*N+i])
x[(idxf-2)*N+i] = x[(idxf-1)*N+i];
//printf("After IfThenElse %f\n", x[(idxf-2)*N+i]);
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void IfThenElse(bool * b, float * x, size_t idxb, size_t idxf, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("From IfThenElse %d, %f, %f\n", b[(idxb-1)*N+i], x[(idxf-1)*N+i], x[(idxf-2)*N+i]);
if (b[(idxb-1)*N+i])
x[(idxf-2)*N+i] = x[(idxf-1)*N+i];
//printf("After IfThenElse %f\n", x[(idxf-2)*N+i]);
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void IfThenElse(bool * b, float * x, size_t idxb, size_t idxf, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("From IfThenElse %d, %f, %f\n", b[(idxb-1)*N+i], x[(idxf-1)*N+i], x[(idxf-2)*N+i]);
if (b[(idxb-1)*N+i])
x[(idxf-2)*N+i] = x[(idxf-1)*N+i];
//printf("After IfThenElse %f\n", x[(idxf-2)*N+i]);
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10IfThenElsePbPfmmm
.globl _Z10IfThenElsePbPfmmm
.p2align 8
.type _Z10IfThenElsePbPfmmm,@function
_Z10IfThenElsePbPfmmm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
s_add_u32 s10, s0, 40
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[8:9], v[1:2]
s_cbranch_execz .LBB0_5
s_load_b256 s[0:7], s[0:1], 0x0
s_load_b32 s10, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_mul_i32 s11, s4, s9
s_mul_hi_u32 s13, s4, s8
s_mul_i32 s5, s5, s8
s_add_i32 s11, s13, s11
s_mul_i32 s4, s4, s8
s_add_i32 s11, s11, s5
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s11
s_add_u32 s4, s6, -1
s_addc_u32 s5, s7, -1
s_mul_i32 s11, s4, s9
s_mul_hi_u32 s13, s4, s8
s_mul_i32 s5, s5, s8
s_add_i32 s11, s13, s11
s_mul_i32 s4, s4, s8
s_add_i32 s5, s11, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_add_u32 s6, s6, -2
s_addc_u32 s7, s7, -1
s_mul_i32 s11, s6, s9
s_mul_hi_u32 s13, s6, s8
s_mul_i32 s7, s7, s8
s_add_i32 s11, s13, s11
s_mul_i32 s6, s6, s8
s_add_i32 s7, s11, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
s_add_i32 s15, s15, s10
s_mul_i32 s6, s10, s12
v_mad_u64_u32 v[3:4], null, s15, s12, v[0:1]
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_cmp_le_u64_e32 vcc_lo, s[8:9], v[3:4]
v_add_nc_u32_e32 v3, s6, v3
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo
s_mov_b32 s10, exec_lo
global_load_u8 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v0
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10IfThenElsePbPfmmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10IfThenElsePbPfmmm, .Lfunc_end0-_Z10IfThenElsePbPfmmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10IfThenElsePbPfmmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10IfThenElsePbPfmmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void IfThenElse(bool * b, float * x, size_t idxb, size_t idxf, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("From IfThenElse %d, %f, %f\n", b[(idxb-1)*N+i], x[(idxf-1)*N+i], x[(idxf-2)*N+i]);
if (b[(idxb-1)*N+i])
x[(idxf-2)*N+i] = x[(idxf-1)*N+i];
//printf("After IfThenElse %f\n", x[(idxf-2)*N+i]);
}
return;
} | .text
.file "IfThenElse.hip"
.globl _Z25__device_stub__IfThenElsePbPfmmm # -- Begin function _Z25__device_stub__IfThenElsePbPfmmm
.p2align 4, 0x90
.type _Z25__device_stub__IfThenElsePbPfmmm,@function
_Z25__device_stub__IfThenElsePbPfmmm: # @_Z25__device_stub__IfThenElsePbPfmmm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10IfThenElsePbPfmmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z25__device_stub__IfThenElsePbPfmmm, .Lfunc_end0-_Z25__device_stub__IfThenElsePbPfmmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10IfThenElsePbPfmmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10IfThenElsePbPfmmm,@object # @_Z10IfThenElsePbPfmmm
.section .rodata,"a",@progbits
.globl _Z10IfThenElsePbPfmmm
.p2align 3, 0x0
_Z10IfThenElsePbPfmmm:
.quad _Z25__device_stub__IfThenElsePbPfmmm
.size _Z10IfThenElsePbPfmmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10IfThenElsePbPfmmm"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__IfThenElsePbPfmmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10IfThenElsePbPfmmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10IfThenElsePbPfmmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x000fc80000011406 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x184], PT, P0 ; /* 0x0000610009007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R2, P1, RZ, -c[0x0][0x180], RZ ; /* 0x80006000ff027a10 */
/* 0x000fe20007f3e0ff */
/*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, -0x1 ; /* 0xffffffffff0a7424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*00d0*/ IADD3 R0, P0, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004007a10 */
/* 0x000fe20007f1e1ff */
/*00e0*/ IMAD.X R3, RZ, RZ, ~c[0x0][0x184], P1 ; /* 0x80006100ff037624 */
/* 0x000fc600008e06ff */
/*00f0*/ IADD3.X R16, R10, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a107a10 */
/* 0x000fe200007fe4ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x180], R2 ; /* 0x0000600000027a25 */
/* 0x000fe200078e0002 */
/*0110*/ IADD3 R4, P0, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fc60007f1e1ff */
/*0120*/ IMAD R5, R16, c[0x0][0x180], RZ ; /* 0x0000600010057a24 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD R7, R0, c[0x0][0x184], R5 ; /* 0x0000610000077a24 */
/* 0x000fe200078e0205 */
/*0140*/ IADD3.X R5, R10, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000a057a10 */
/* 0x000fc800007fe4ff */
/*0150*/ IADD3 R7, R3, R7, RZ ; /* 0x0000000703077210 */
/* 0x000fe40007ffe0ff */
/*0160*/ IMAD R13, R5, c[0x0][0x180], RZ ; /* 0x00006000050d7a24 */
/* 0x000fe400078e02ff */
/*0170*/ IMAD.WIDE.U32 R10, R4, c[0x0][0x180], R8 ; /* 0x00006000040a7a25 */
/* 0x000fc800078e0008 */
/*0180*/ IMAD R13, R4, c[0x0][0x184], R13 ; /* 0x00006100040d7a24 */
/* 0x000fe200078e020d */
/*0190*/ IADD3 R10, P0, R10, c[0x0][0x160], RZ ; /* 0x000058000a0a7a10 */
/* 0x000fc80007f1e0ff */
/*01a0*/ IADD3.X R11, R11, c[0x0][0x164], R13, P0, !PT ; /* 0x000059000b0b7a10 */
/* 0x000fca00007fe40d */
/*01b0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1100 */
/*01c0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*01d0*/ @P0 IMAD R15, R16, c[0x0][0x180], RZ ; /* 0x00006000100f0a24 */
/* 0x000fe400078e02ff */
/*01e0*/ @P0 IMAD.WIDE.U32 R12, R0, c[0x0][0x180], R8 ; /* 0x00006000000c0a25 */
/* 0x000fc800078e0008 */
/*01f0*/ @P0 IMAD R15, R0, c[0x0][0x184], R15 ; /* 0x00006100000f0a24 */
/* 0x000fe200078e020f */
/*0200*/ @P0 LEA R14, P1, R12, c[0x0][0x168], 0x2 ; /* 0x00005a000c0e0a11 */
/* 0x000fc600078210ff */
/*0210*/ @P0 IMAD.IADD R13, R15, 0x1, R13 ; /* 0x000000010f0d0824 */
/* 0x000fca00078e020d */
/*0220*/ @P0 LEA.HI.X R15, R12, c[0x0][0x16c], R13, 0x2, P1 ; /* 0x00005b000c0f0a11 */
/* 0x000fcc00008f140d */
/*0230*/ @P0 LDG.E R15, [R14.64] ; /* 0x000000040e0f0981 */
/* 0x000ea2000c1e1900 */
/*0240*/ @P0 IADD3 R8, P1, R8, R2, RZ ; /* 0x0000000208080210 */
/* 0x000fca0007f3e0ff */
/*0250*/ @P0 IMAD.X R9, R9, 0x1, R7, P1 ; /* 0x0000000109090824 */
/* 0x000fe200008e0607 */
/*0260*/ @P0 LEA R10, P1, R8, c[0x0][0x168], 0x2 ; /* 0x00005a00080a0a11 */
/* 0x000fc800078210ff */
/*0270*/ @P0 LEA.HI.X R11, R8, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b00080b0a11 */
/* 0x000fe400008f1409 */
/*0280*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fca0000000f00 */
/*0290*/ IMAD R8, R9, c[0x0][0xc], R6 ; /* 0x0000030009087a24 */
/* 0x000fc800078e0206 */
/*02a0*/ IMAD.MOV.U32 R6, RZ, RZ, R8.reuse ; /* 0x000000ffff067224 */
/* 0x100fe200078e0008 */
/*02b0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fe20000011408 */
/*02c0*/ @P0 STG.E [R10.64], R15 ; /* 0x0000000f0a000986 */
/* 0x0041e2000c101904 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fc80003f06070 */
/*02e0*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x184], PT, P0 ; /* 0x0000610009007a0c */
/* 0x000fda0003f06100 */
/*02f0*/ @!P0 BRA 0x160 ; /* 0xfffffe6000008947 */
/* 0x001fea000383ffff */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10IfThenElsePbPfmmm
.globl _Z10IfThenElsePbPfmmm
.p2align 8
.type _Z10IfThenElsePbPfmmm,@function
_Z10IfThenElsePbPfmmm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
s_add_u32 s10, s0, 40
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[8:9], v[1:2]
s_cbranch_execz .LBB0_5
s_load_b256 s[0:7], s[0:1], 0x0
s_load_b32 s10, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_mul_i32 s11, s4, s9
s_mul_hi_u32 s13, s4, s8
s_mul_i32 s5, s5, s8
s_add_i32 s11, s13, s11
s_mul_i32 s4, s4, s8
s_add_i32 s11, s11, s5
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s11
s_add_u32 s4, s6, -1
s_addc_u32 s5, s7, -1
s_mul_i32 s11, s4, s9
s_mul_hi_u32 s13, s4, s8
s_mul_i32 s5, s5, s8
s_add_i32 s11, s13, s11
s_mul_i32 s4, s4, s8
s_add_i32 s5, s11, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_add_u32 s6, s6, -2
s_addc_u32 s7, s7, -1
s_mul_i32 s11, s6, s9
s_mul_hi_u32 s13, s6, s8
s_mul_i32 s7, s7, s8
s_add_i32 s11, s13, s11
s_mul_i32 s6, s6, s8
s_add_i32 s7, s11, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
s_add_i32 s15, s15, s10
s_mul_i32 s6, s10, s12
v_mad_u64_u32 v[3:4], null, s15, s12, v[0:1]
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_cmp_le_u64_e32 vcc_lo, s[8:9], v[3:4]
v_add_nc_u32_e32 v3, s6, v3
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo
s_mov_b32 s10, exec_lo
global_load_u8 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v0
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10IfThenElsePbPfmmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10IfThenElsePbPfmmm, .Lfunc_end0-_Z10IfThenElsePbPfmmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10IfThenElsePbPfmmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10IfThenElsePbPfmmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00041d3a_00000000-6_IfThenElse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm
.type _Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm, @function
_Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10IfThenElsePbPfmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm, .-_Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm
.globl _Z10IfThenElsePbPfmmm
.type _Z10IfThenElsePbPfmmm, @function
_Z10IfThenElsePbPfmmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10IfThenElsePbPfmmmPbPfmmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10IfThenElsePbPfmmm, .-_Z10IfThenElsePbPfmmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10IfThenElsePbPfmmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10IfThenElsePbPfmmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "IfThenElse.hip"
.globl _Z25__device_stub__IfThenElsePbPfmmm # -- Begin function _Z25__device_stub__IfThenElsePbPfmmm
.p2align 4, 0x90
.type _Z25__device_stub__IfThenElsePbPfmmm,@function
_Z25__device_stub__IfThenElsePbPfmmm: # @_Z25__device_stub__IfThenElsePbPfmmm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10IfThenElsePbPfmmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z25__device_stub__IfThenElsePbPfmmm, .Lfunc_end0-_Z25__device_stub__IfThenElsePbPfmmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10IfThenElsePbPfmmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10IfThenElsePbPfmmm,@object # @_Z10IfThenElsePbPfmmm
.section .rodata,"a",@progbits
.globl _Z10IfThenElsePbPfmmm
.p2align 3, 0x0
_Z10IfThenElsePbPfmmm:
.quad _Z25__device_stub__IfThenElsePbPfmmm
.size _Z10IfThenElsePbPfmmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10IfThenElsePbPfmmm"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__IfThenElsePbPfmmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10IfThenElsePbPfmmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /** size of A = 768
size of B = 180
gridDim = 60
blockDim = 256
k= 200000
x = 3
**/
__global__ void CompareAddVectors(const int* A, const int* B, int* C, int x, int k)
{
int size_A = x*blockDim.x;
int B_start_index = (blockIdx.x*gridDim.y + blockIdx.y)*x;
int t,i,j,temp;
__shared__ int c[3][768];
__shared__ int a[768];
int b_0, b_1, b_2;
for (t = 0; t < x; t++) {
temp = blockDim.x*t + threadIdx.x;
a[temp] = A[temp];
}
for (i = 0; i < x; i++) {
for (t = 0; t < x; t++) {
c[i][blockDim.x*t + threadIdx.x] = 0;
}
}
__syncthreads();
b_0 = B[B_start_index+0];
b_1 = B[B_start_index+1];
b_2 = B[B_start_index+2];
for (t = 0; t < k; t++) {
#pragma unroll
for (j = 0; j < x; j++) {
temp = blockDim.x*j+threadIdx.x;
c[0][temp] = max(a[temp]+b_0, c[0][temp]);
}
#pragma unroll
for (j = 0; j < x; j++) {
temp = blockDim.x*j+threadIdx.x;
c[1][temp] = max(a[temp]+b_1, c[1][temp]);
}
#pragma unroll
for (j = 0; j < x; j++) {
temp = blockDim.x*j+threadIdx.x;
c[2][temp] = max(a[temp]+b_2, c[2][temp]);
}
for (i = 0; i < x; i++) {
temp = blockDim.x*i+threadIdx.x;
a[temp] = max(a[temp]+10, a[temp]);
}
b_0 = max(b_0, b_0+10);
b_1 = max(b_1, b_1+10);
b_2 = max(b_2, b_2+10);
__syncthreads();
}
for (i = 0; i < x; i++) {
for (t = 0; t < x; t++) {
temp = t*blockDim.x + threadIdx.x;
C[(x*blockIdx.x+i)*size_A + temp] = c[i][temp];
}
}
} | .file "tmpxft_0019e7b6_00000000-6_intKernelMaxSharedAll.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17CompareAddVectorsPKiS0_PiiiPKiS0_Piii
.type _Z45__device_stub__Z17CompareAddVectorsPKiS0_PiiiPKiS0_Piii, @function
_Z45__device_stub__Z17CompareAddVectorsPKiS0_PiiiPKiS0_Piii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17CompareAddVectorsPKiS0_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17CompareAddVectorsPKiS0_PiiiPKiS0_Piii, .-_Z45__device_stub__Z17CompareAddVectorsPKiS0_PiiiPKiS0_Piii
.globl _Z17CompareAddVectorsPKiS0_Piii
.type _Z17CompareAddVectorsPKiS0_Piii, @function
_Z17CompareAddVectorsPKiS0_Piii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17CompareAddVectorsPKiS0_PiiiPKiS0_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17CompareAddVectorsPKiS0_Piii, .-_Z17CompareAddVectorsPKiS0_Piii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17CompareAddVectorsPKiS0_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17CompareAddVectorsPKiS0_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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