system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void lif_update_membrane_potentials(float *d_membrane_potentials_v, float * d_membrane_resistances_R, float * d_membrane_time_constants_tau_m, float * d_resting_potentials, float* d_current_injections, float timestep, size_t total_number_of_neurons){
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
float equation_constant = timestep / d_membrane_time_constants_tau_m[idx];
float membrane_potential_Vi = d_membrane_potentials_v[idx];
float current_injection_Ii = d_current_injections[idx];
float resting_potential_V0 = d_resting_potentials[idx];
float temp_membrane_resistance_R = d_membrane_resistances_R[idx];
float new_membrane_potential = equation_constant * (resting_potential_V0 + temp_membrane_resistance_R * current_injection_Ii) + (1 - equation_constant) * membrane_potential_Vi;
d_membrane_potentials_v[idx] = new_membrane_potential;
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .file "tmpxft_001b2fd9_00000000-6_lif_update_membrane_potentials.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm
.type _Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm, @function
_Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z30lif_update_membrane_potentialsPfS_S_S_S_fm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm, .-_Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm
.globl _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.type _Z30lif_update_membrane_potentialsPfS_S_S_S_fm, @function
_Z30lif_update_membrane_potentialsPfS_S_S_S_fm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30lif_update_membrane_potentialsPfS_S_S_S_fm, .-_Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30lif_update_membrane_potentialsPfS_S_S_S_fm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30lif_update_membrane_potentialsPfS_S_S_S_fm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void lif_update_membrane_potentials(float *d_membrane_potentials_v, float * d_membrane_resistances_R, float * d_membrane_time_constants_tau_m, float * d_resting_potentials, float* d_current_injections, float timestep, size_t total_number_of_neurons){
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
float equation_constant = timestep / d_membrane_time_constants_tau_m[idx];
float membrane_potential_Vi = d_membrane_potentials_v[idx];
float current_injection_Ii = d_current_injections[idx];
float resting_potential_V0 = d_resting_potentials[idx];
float temp_membrane_resistance_R = d_membrane_resistances_R[idx];
float new_membrane_potential = equation_constant * (resting_potential_V0 + temp_membrane_resistance_R * current_injection_Ii) + (1 - equation_constant) * membrane_potential_Vi;
d_membrane_potentials_v[idx] = new_membrane_potential;
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void lif_update_membrane_potentials(float *d_membrane_potentials_v, float * d_membrane_resistances_R, float * d_membrane_time_constants_tau_m, float * d_resting_potentials, float* d_current_injections, float timestep, size_t total_number_of_neurons){
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
float equation_constant = timestep / d_membrane_time_constants_tau_m[idx];
float membrane_potential_Vi = d_membrane_potentials_v[idx];
float current_injection_Ii = d_current_injections[idx];
float resting_potential_V0 = d_resting_potentials[idx];
float temp_membrane_resistance_R = d_membrane_resistances_R[idx];
float new_membrane_potential = equation_constant * (resting_potential_V0 + temp_membrane_resistance_R * current_injection_Ii) + (1 - equation_constant) * membrane_potential_Vi;
d_membrane_potentials_v[idx] = new_membrane_potential;
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void lif_update_membrane_potentials(float *d_membrane_potentials_v, float * d_membrane_resistances_R, float * d_membrane_time_constants_tau_m, float * d_resting_potentials, float* d_current_injections, float timestep, size_t total_number_of_neurons){
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
float equation_constant = timestep / d_membrane_time_constants_tau_m[idx];
float membrane_potential_Vi = d_membrane_potentials_v[idx];
float current_injection_Ii = d_current_injections[idx];
float resting_potential_V0 = d_resting_potentials[idx];
float temp_membrane_resistance_R = d_membrane_resistances_R[idx];
float new_membrane_potential = equation_constant * (resting_potential_V0 + temp_membrane_resistance_R * current_injection_Ii) + (1 - equation_constant) * membrane_potential_Vi;
d_membrane_potentials_v[idx] = new_membrane_potential;
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.globl _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.p2align 8
.type _Z30lif_update_membrane_potentialsPfS_S_S_S_fm,@function
_Z30lif_update_membrane_potentialsPfS_S_S_S_fm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x30
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s16, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[3:4]
s_cbranch_execz .LBB0_3
s_load_b32 s17, s[4:5], 0x0
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b32 s0, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s17
s_mul_i32 s1, s17, s16
v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
s_mov_b32 s15, 0
.LBB0_2:
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v7, v[6:7], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v9, v[5:6], off
s_waitcnt vmcnt(4)
v_div_scale_f32 v2, null, v0, v0, s0
v_div_scale_f32 v11, vcc_lo, s0, v0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v7, v4, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v2, v3, 1.0
v_fmac_f32_e32 v3, v10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v11, v3
v_fma_f32 v12, -v2, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v12, v3
v_fma_f32 v2, -v2, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v10
v_div_fixup_f32 v0, v2, v0, s0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v7, v0, v7 :: v_dual_mov_b32 v4, v2
v_sub_f32_e32 v0, 1.0, v0
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_mov_b32_e32 v3, v1
v_add_nc_u32_e32 v1, s1, v1
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v9, v0
s_or_b32 s15, vcc_lo, s15
global_store_b32 v[5:6], v7, off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30lif_update_membrane_potentialsPfS_S_S_S_fm, .Lfunc_end0-_Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z30lif_update_membrane_potentialsPfS_S_S_S_fm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void lif_update_membrane_potentials(float *d_membrane_potentials_v, float * d_membrane_resistances_R, float * d_membrane_time_constants_tau_m, float * d_resting_potentials, float* d_current_injections, float timestep, size_t total_number_of_neurons){
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
float equation_constant = timestep / d_membrane_time_constants_tau_m[idx];
float membrane_potential_Vi = d_membrane_potentials_v[idx];
float current_injection_Ii = d_current_injections[idx];
float resting_potential_V0 = d_resting_potentials[idx];
float temp_membrane_resistance_R = d_membrane_resistances_R[idx];
float new_membrane_potential = equation_constant * (resting_potential_V0 + temp_membrane_resistance_R * current_injection_Ii) + (1 - equation_constant) * membrane_potential_Vi;
d_membrane_potentials_v[idx] = new_membrane_potential;
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.file "lif_update_membrane_potentials.hip"
.globl _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm # -- Begin function _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.p2align 4, 0x90
.type _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm,@function
_Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm: # @_Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %r9, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z30lif_update_membrane_potentialsPfS_S_S_S_fm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm, .Lfunc_end0-_Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30lif_update_membrane_potentialsPfS_S_S_S_fm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30lif_update_membrane_potentialsPfS_S_S_S_fm,@object # @_Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.section .rodata,"a",@progbits
.globl _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.p2align 3, 0x0
_Z30lif_update_membrane_potentialsPfS_S_S_S_fm:
.quad _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.size _Z30lif_update_membrane_potentialsPfS_S_S_S_fm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30lif_update_membrane_potentialsPfS_S_S_S_fm"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x390 ; /* 0x0000036000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x190], PT ; /* 0x0000640000007a0c */
/* 0x000fe40003f06070 */
/*0060*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x194], PT, P0 ; /* 0x0000650002007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 BRA 0x380 ; /* 0x000002f000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0000 */
/*00b0*/ IMAD.SHL.U32 R3, R2.reuse, 0x4, RZ ; /* 0x0000000402037824 */
/* 0x040fe200078e00ff */
/*00c0*/ SHF.L.U64.HI R2, R2, 0x2, R7 ; /* 0x0000000202027819 */
/* 0x000fe20000010207 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IADD3 R4, P0, R3, c[0x0][0x170], RZ ; /* 0x00005c0003047a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R5, R2, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0002057a10 */
/* 0x000fca00007fe4ff */
/*0100*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0110*/ ULDC UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe20000000800 */
/*0120*/ BSSY B1, 0x1f0 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*0130*/ IMAD.U32 R10, RZ, RZ, UR4 ; /* 0x00000004ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*0140*/ MUFU.RCP R6, R11 ; /* 0x0000000b00067308 */
/* 0x004e300000001000 */
/*0150*/ FCHK P0, R10, R11 ; /* 0x0000000b0a007302 */
/* 0x000e620000000000 */
/*0160*/ FFMA R7, -R11, R6, 1 ; /* 0x3f8000000b077423 */
/* 0x001fc80000000106 */
/*0170*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0180*/ FFMA R6, R7, c[0x0][0x188], RZ ; /* 0x0000620007067a23 */
/* 0x000fc800000000ff */
/*0190*/ FFMA R8, -R11, R6, c[0x0][0x188] ; /* 0x000062000b087623 */
/* 0x000fc80000000106 */
/*01a0*/ FFMA R12, R7, R8, R6 ; /* 0x00000008070c7223 */
/* 0x000fe20000000006 */
/*01b0*/ @!P0 BRA 0x1e0 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*01c0*/ MOV R4, 0x1e0 ; /* 0x000001e000047802 */
/* 0x000fe40000000f00 */
/*01d0*/ CALL.REL.NOINC 0x3b0 ; /* 0x000001d000007944 */
/* 0x000fea0003c00000 */
/*01e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R8, P1, R3.reuse, c[0x0][0x180], RZ ; /* 0x0000600003087a10 */
/* 0x040fe20007f3e0ff */
/*0200*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0210*/ IADD3 R6, P0, R3.reuse, c[0x0][0x168], RZ ; /* 0x00005a0003067a10 */
/* 0x040fe40007f1e0ff */
/*0220*/ IADD3 R10, P2, R3, c[0x0][0x178], RZ ; /* 0x00005e00030a7a10 */
/* 0x000fe40007f5e0ff */
/*0230*/ IADD3.X R9, R2.reuse, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610002097a10 */
/* 0x040fe40000ffe4ff */
/*0240*/ IADD3.X R7, R2.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0002077a10 */
/* 0x040fe400007fe4ff */
/*0250*/ IADD3.X R11, R2, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f00020b7a10 */
/* 0x000fc400017fe4ff */
/*0260*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fe20007f1e0ff */
/*0270*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IADD3.X R5, R2, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590002057a10 */
/* 0x000fc600007fe4ff */
/*02a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FADD R2, -R12, 1 ; /* 0x3f8000000c027421 */
/* 0x000fe40000000100 */
/*02d0*/ FFMA R3, R6, R9, R10 ; /* 0x0000000906037223 */
/* 0x004fc8000000000a */
/*02e0*/ FMUL R3, R3, R12 ; /* 0x0000000c03037220 */
/* 0x000fc80000400000 */
/*02f0*/ FFMA R3, R2, R13, R3 ; /* 0x0000000d02037223 */
/* 0x008fe40000000003 */
/*0300*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fc600078e00ff */
/*0310*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e2000c101904 */
/*0320*/ IMAD R2, R13, c[0x0][0xc], R0 ; /* 0x000003000d027a24 */
/* 0x000fc800078e0200 */
/*0330*/ IMAD.MOV.U32 R0, RZ, RZ, R2.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0002 */
/*0340*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe40003f06070 */
/*0350*/ SHF.R.S32.HI R7, RZ, 0x1f, R2 ; /* 0x0000001fff077819 */
/* 0x000fc80000011402 */
/*0360*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x194], PT, P0 ; /* 0x0000650007007a0c */
/* 0x000fda0003f06100 */
/*0370*/ @!P0 BRA 0xb0 ; /* 0xfffffd3000008947 */
/* 0x001fea000383ffff */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ SHF.R.U32.HI R5, RZ, 0x17, R11.reuse ; /* 0x00000017ff057819 */
/* 0x100fe2000001160b */
/*03c0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0c7624 */
/* 0x000fe200078e00ff */
/*03d0*/ BSSY B2, 0xa30 ; /* 0x0000065000027945 */
/* 0x000fe20003800000 */
/*03e0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff077624 */
/* 0x000fe200078e00ff */
/*03f0*/ LOP3.LUT R13, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050d7812 */
/* 0x000fe200078ec0ff */
/*0400*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000b */
/*0410*/ SHF.R.U32.HI R5, RZ, 0x17, R12 ; /* 0x00000017ff057819 */
/* 0x000fc4000001160c */
/*0420*/ IADD3 R14, R13, -0x1, RZ ; /* 0xffffffff0d0e7810 */
/* 0x000fe40007ffe0ff */
/*0430*/ LOP3.LUT R6, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05067812 */
/* 0x000fe400078ec0ff */
/*0440*/ ISETP.GT.U32.AND P0, PT, R14, 0xfd, PT ; /* 0x000000fd0e00780c */
/* 0x000fe40003f04070 */
/*0450*/ IADD3 R10, R6, -0x1, RZ ; /* 0xffffffff060a7810 */
/* 0x000fc80007ffe0ff */
/*0460*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0470*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0480*/ @!P0 BRA 0x610 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe20003f1c200 */
/*04a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*04b0*/ FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f3c200 */
/*04c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*04d0*/ @P0 BRA 0xa10 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*04e0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*04f0*/ @!P0 BRA 0x9f0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0500*/ FSETP.NEU.FTZ.AND P2, PT, |R12|.reuse, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x040fe40003f5d200 */
/*0510*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0520*/ FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fd60003f1d200 */
/*0530*/ @!P1 BRA !P2, 0x9f0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0540*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0550*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0560*/ @P1 BRA 0x9d0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0570*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0580*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0590*/ @P0 BRA 0x9a0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*05b0*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd60003f26270 */
/*05c0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*05d0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*05e0*/ @!P0 FFMA R7, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c078823 */
/* 0x000fe400000000ff */
/*05f0*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0600*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0610*/ LEA R5, R13, 0xc0800000, 0x17 ; /* 0xc08000000d057811 */
/* 0x000fe200078eb8ff */
/*0620*/ BSSY B3, 0x990 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*0630*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0640*/ IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108087824 */
/* 0x000fe400078e0a05 */
/*0650*/ IMAD R7, R6, -0x800000, R7 ; /* 0xff80000006077824 */
/* 0x000fe400078e0207 */
/*0660*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x0000620000001000 */
/*0670*/ FADD.FTZ R10, -R8, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fe20000010100 */
/*0680*/ IADD3 R8, R6, 0x7f, -R13 ; /* 0x0000007f06087810 */
/* 0x001fca0007ffe80d */
/*0690*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*06a0*/ FFMA R12, R5, R10, 1 ; /* 0x3f800000050c7423 */
/* 0x002fc8000000000a */
/*06b0*/ FFMA R14, R5, R12, R5 ; /* 0x0000000c050e7223 */
/* 0x000fc80000000005 */
/*06c0*/ FFMA R5, R7, R14, RZ ; /* 0x0000000e07057223 */
/* 0x000fc800000000ff */
/*06d0*/ FFMA R12, R10, R5, R7 ; /* 0x000000050a0c7223 */
/* 0x000fc80000000007 */
/*06e0*/ FFMA R11, R14, R12, R5 ; /* 0x0000000c0e0b7223 */
/* 0x000fc80000000005 */
/*06f0*/ FFMA R7, R10, R11, R7 ; /* 0x0000000b0a077223 */
/* 0x000fc80000000007 */
/*0700*/ FFMA R5, R14, R7, R11 ; /* 0x000000070e057223 */
/* 0x000fca000000000b */
/*0710*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*0720*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*0730*/ IMAD.IADD R10, R6, 0x1, R8 ; /* 0x00000001060a7824 */
/* 0x000fca00078e0208 */
/*0740*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fc80007ffe0ff */
/*0750*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*0760*/ @!P0 BRA 0x970 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0780*/ @P0 BRA 0x940 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0790*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*07a0*/ @P0 BRA 0x980 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*07b0*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*07c0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*07d0*/ @!P0 BRA 0x980 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*07e0*/ FFMA.RZ R6, R14, R7.reuse, R11.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000c00b */
/*07f0*/ IADD3 R9, R10.reuse, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x040fe40007ffe0ff */
/*0800*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0810*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0820*/ FFMA.RP R6, R14, R7.reuse, R11.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000800b */
/*0830*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0840*/ FFMA.RM R7, R14, R7, R11 ; /* 0x000000070e077223 */
/* 0x000fe2000000400b */
/*0850*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe200078efcff */
/*0860*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0a0a */
/*0870*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0880*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fe40003f1d000 */
/*0890*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*08a0*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*08b0*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*08c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*08d0*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*08e0*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*08f0*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0900*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0910*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*0920*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*0930*/ BRA 0x980 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0950*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0960*/ BRA 0x980 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0970*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0980*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0990*/ BRA 0xa20 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*09a0*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4807 */
/*09b0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*09c0*/ BRA 0xa20 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4807 */
/*09e0*/ BRA 0xa20 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*09f0*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0a00*/ BRA 0xa20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a10*/ FADD.FTZ R5, R5, c[0x0][0x188] ; /* 0x0000620005057621 */
/* 0x000fe40000010000 */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ IMAD.MOV.U32 R12, RZ, RZ, R5 ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e0005 */
/*0a40*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0a50*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff5a004007950 */
/* 0x000fea0003c3ffff */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.globl _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.p2align 8
.type _Z30lif_update_membrane_potentialsPfS_S_S_S_fm,@function
_Z30lif_update_membrane_potentialsPfS_S_S_S_fm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x30
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s16, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[3:4]
s_cbranch_execz .LBB0_3
s_load_b32 s17, s[4:5], 0x0
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b32 s0, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s17
s_mul_i32 s1, s17, s16
v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
s_mov_b32 s15, 0
.LBB0_2:
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v7, v[6:7], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v9, v[5:6], off
s_waitcnt vmcnt(4)
v_div_scale_f32 v2, null, v0, v0, s0
v_div_scale_f32 v11, vcc_lo, s0, v0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v7, v4, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v2, v3, 1.0
v_fmac_f32_e32 v3, v10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v11, v3
v_fma_f32 v12, -v2, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v12, v3
v_fma_f32 v2, -v2, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v10
v_div_fixup_f32 v0, v2, v0, s0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v7, v0, v7 :: v_dual_mov_b32 v4, v2
v_sub_f32_e32 v0, 1.0, v0
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_mov_b32_e32 v3, v1
v_add_nc_u32_e32 v1, s1, v1
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v9, v0
s_or_b32 s15, vcc_lo, s15
global_store_b32 v[5:6], v7, off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30lif_update_membrane_potentialsPfS_S_S_S_fm, .Lfunc_end0-_Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z30lif_update_membrane_potentialsPfS_S_S_S_fm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b2fd9_00000000-6_lif_update_membrane_potentials.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm
.type _Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm, @function
_Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z30lif_update_membrane_potentialsPfS_S_S_S_fm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm, .-_Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm
.globl _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.type _Z30lif_update_membrane_potentialsPfS_S_S_S_fm, @function
_Z30lif_update_membrane_potentialsPfS_S_S_S_fm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z30lif_update_membrane_potentialsPfS_S_S_S_fmPfS_S_S_S_fm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30lif_update_membrane_potentialsPfS_S_S_S_fm, .-_Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30lif_update_membrane_potentialsPfS_S_S_S_fm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30lif_update_membrane_potentialsPfS_S_S_S_fm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lif_update_membrane_potentials.hip"
.globl _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm # -- Begin function _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.p2align 4, 0x90
.type _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm,@function
_Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm: # @_Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %r9, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z30lif_update_membrane_potentialsPfS_S_S_S_fm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm, .Lfunc_end0-_Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30lif_update_membrane_potentialsPfS_S_S_S_fm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30lif_update_membrane_potentialsPfS_S_S_S_fm,@object # @_Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.section .rodata,"a",@progbits
.globl _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.p2align 3, 0x0
_Z30lif_update_membrane_potentialsPfS_S_S_S_fm:
.quad _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.size _Z30lif_update_membrane_potentialsPfS_S_S_S_fm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30lif_update_membrane_potentialsPfS_S_S_S_fm"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__lif_update_membrane_potentialsPfS_S_S_S_fm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for (i = 0; i < n; ++i) {
int val = input[i];
largest = (val>largest) ? val : largest;
}
for (i = 0; i < n; ++i) {
float e = expf(input[i] / temp - largest / temp);
sum += e;
output[i] = e;
}
for (i = 0; i < n; ++i) {
output[i] /= sum;
}
}
__global__ void softmax_kernel(int n, int offset, int batch, float *input, float temp, float *output)
{
int b = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (b >= batch) return;
softmax_device(n, input + b*offset, temp, output + b*offset);
} | .file "tmpxft_001a86be_00000000-6_softmax_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14softmax_deviceiPffS_
.type _Z14softmax_deviceiPffS_, @function
_Z14softmax_deviceiPffS_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z14softmax_deviceiPffS_, .-_Z14softmax_deviceiPffS_
.globl _Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_
.type _Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_, @function
_Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movss %xmm0, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14softmax_kerneliiiPffS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_, .-_Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_
.globl _Z14softmax_kerneliiiPffS_
.type _Z14softmax_kerneliiiPffS_, @function
_Z14softmax_kerneliiiPffS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14softmax_kerneliiiPffS_, .-_Z14softmax_kerneliiiPffS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14softmax_kerneliiiPffS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14softmax_kerneliiiPffS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for (i = 0; i < n; ++i) {
int val = input[i];
largest = (val>largest) ? val : largest;
}
for (i = 0; i < n; ++i) {
float e = expf(input[i] / temp - largest / temp);
sum += e;
output[i] = e;
}
for (i = 0; i < n; ++i) {
output[i] /= sum;
}
}
__global__ void softmax_kernel(int n, int offset, int batch, float *input, float temp, float *output)
{
int b = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (b >= batch) return;
softmax_device(n, input + b*offset, temp, output + b*offset);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for (i = 0; i < n; ++i) {
int val = input[i];
largest = (val>largest) ? val : largest;
}
for (i = 0; i < n; ++i) {
float e = expf(input[i] / temp - largest / temp);
sum += e;
output[i] = e;
}
for (i = 0; i < n; ++i) {
output[i] /= sum;
}
}
__global__ void softmax_kernel(int n, int offset, int batch, float *input, float temp, float *output)
{
int b = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (b >= batch) return;
softmax_device(n, input + b*offset, temp, output + b*offset);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for (i = 0; i < n; ++i) {
int val = input[i];
largest = (val>largest) ? val : largest;
}
for (i = 0; i < n; ++i) {
float e = expf(input[i] / temp - largest / temp);
sum += e;
output[i] = e;
}
for (i = 0; i < n; ++i) {
output[i] /= sum;
}
}
__global__ void softmax_kernel(int n, int offset, int batch, float *input, float temp, float *output)
{
int b = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (b >= batch) return;
softmax_device(n, input + b*offset, temp, output + b*offset);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14softmax_kerneliiiPffS_
.globl _Z14softmax_kerneliiiPffS_
.p2align 8
.type _Z14softmax_kerneliiiPffS_,@function
_Z14softmax_kerneliiiPffS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_10
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v8, 0xff800000
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v1, s3
s_cmp_gt_i32 s2, 0
s_cselect_b32 s3, -1, 0
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
s_mov_b32 s4, s2
.LBB0_3:
global_load_b32 v6, v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v6, v6
v_cvt_f32_i32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v8, v6
v_cndmask_b32_e32 v8, v8, v6, vcc_lo
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_load_b64 s[4:5], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_cndmask_b32_e64 v7, 0, 1, s3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_7
s_load_b32 s0, s[0:1], 0x18
s_mov_b32 s1, s2
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v4, null, s0, s0, v8
v_div_scale_f32 v9, vcc_lo, v8, s0, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v9, v5
v_fma_f32 v10, -v4, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v10, v5
v_fma_f32 v4, -v4, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v5, v6
v_mov_b32_e32 v6, 0
v_div_fixup_f32 v8, v4, s0, v8
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
.LBB0_6:
global_load_b32 v9, v[0:1], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s1, 0
s_waitcnt vmcnt(0)
v_div_scale_f32 v10, null, s0, s0, v9
v_div_scale_f32 v12, vcc_lo, v9, s0, v9
v_rcp_f32_e32 v11, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v10, v11, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v11
v_mul_f32_e32 v13, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, -v10, v13, v12
v_fmac_f32_e32 v13, v14, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v10, v13, v12
v_div_fmas_f32 v10, v10, v11, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v9, v10, s0, v9
v_sub_f32_e32 v9, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, 0x3fb8aa3b, v9
v_fma_f32 v11, v9, 0x3fb8aa3b, -v10
v_rndne_f32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v11, 0x32a5705f, v9 :: v_dual_sub_f32 v10, v10, v12
v_add_f32_e32 v10, v10, v11
v_cvt_i32_f32_e32 v11, v12
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_ldexp_f32 v10, v10, v11
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v9, 0x7f800000, v10, vcc_lo
global_store_b32 v[4:5], v9, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_f32_e32 v6, v6, v9
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_8
.LBB0_7:
v_mov_b32_e32 v6, 0
.LBB0_8:
v_cmp_ne_u32_e32 vcc_lo, 1, v7
s_cbranch_vccnz .LBB0_10
.p2align 6
.LBB0_9:
global_load_b32 v0, v[2:3], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_div_scale_f32 v1, null, v6, v6, v0
v_div_scale_f32 v7, vcc_lo, v0, v6, v0
v_rcp_f32_e32 v4, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v1, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v1, v5, v7
v_fmac_f32_e32 v5, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v5, v7
v_div_fmas_f32 v1, v1, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v1, v6, v0
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_9
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14softmax_kerneliiiPffS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14softmax_kerneliiiPffS_, .Lfunc_end0-_Z14softmax_kerneliiiPffS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14softmax_kerneliiiPffS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14softmax_kerneliiiPffS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for (i = 0; i < n; ++i) {
int val = input[i];
largest = (val>largest) ? val : largest;
}
for (i = 0; i < n; ++i) {
float e = expf(input[i] / temp - largest / temp);
sum += e;
output[i] = e;
}
for (i = 0; i < n; ++i) {
output[i] /= sum;
}
}
__global__ void softmax_kernel(int n, int offset, int batch, float *input, float temp, float *output)
{
int b = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (b >= batch) return;
softmax_device(n, input + b*offset, temp, output + b*offset);
} | .text
.file "softmax_kernel.hip"
.globl _Z29__device_stub__softmax_kerneliiiPffS_ # -- Begin function _Z29__device_stub__softmax_kerneliiiPffS_
.p2align 4, 0x90
.type _Z29__device_stub__softmax_kerneliiiPffS_,@function
_Z29__device_stub__softmax_kerneliiiPffS_: # @_Z29__device_stub__softmax_kerneliiiPffS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movss %xmm0, (%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14softmax_kerneliiiPffS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z29__device_stub__softmax_kerneliiiPffS_, .Lfunc_end0-_Z29__device_stub__softmax_kerneliiiPffS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14softmax_kerneliiiPffS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14softmax_kerneliiiPffS_,@object # @_Z14softmax_kerneliiiPffS_
.section .rodata,"a",@progbits
.globl _Z14softmax_kerneliiiPffS_
.p2align 3, 0x0
_Z14softmax_kerneliiiPffS_:
.quad _Z29__device_stub__softmax_kerneliiiPffS_
.size _Z14softmax_kerneliiiPffS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14softmax_kerneliiiPffS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__softmax_kerneliiiPffS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14softmax_kerneliiiPffS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a86be_00000000-6_softmax_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14softmax_deviceiPffS_
.type _Z14softmax_deviceiPffS_, @function
_Z14softmax_deviceiPffS_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z14softmax_deviceiPffS_, .-_Z14softmax_deviceiPffS_
.globl _Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_
.type _Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_, @function
_Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movss %xmm0, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14softmax_kerneliiiPffS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_, .-_Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_
.globl _Z14softmax_kerneliiiPffS_
.type _Z14softmax_kerneliiiPffS_, @function
_Z14softmax_kerneliiiPffS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14softmax_kerneliiiPffS_iiiPffS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14softmax_kerneliiiPffS_, .-_Z14softmax_kerneliiiPffS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14softmax_kerneliiiPffS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14softmax_kerneliiiPffS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "softmax_kernel.hip"
.globl _Z29__device_stub__softmax_kerneliiiPffS_ # -- Begin function _Z29__device_stub__softmax_kerneliiiPffS_
.p2align 4, 0x90
.type _Z29__device_stub__softmax_kerneliiiPffS_,@function
_Z29__device_stub__softmax_kerneliiiPffS_: # @_Z29__device_stub__softmax_kerneliiiPffS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movss %xmm0, (%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14softmax_kerneliiiPffS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z29__device_stub__softmax_kerneliiiPffS_, .Lfunc_end0-_Z29__device_stub__softmax_kerneliiiPffS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14softmax_kerneliiiPffS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14softmax_kerneliiiPffS_,@object # @_Z14softmax_kerneliiiPffS_
.section .rodata,"a",@progbits
.globl _Z14softmax_kerneliiiPffS_
.p2align 3, 0x0
_Z14softmax_kerneliiiPffS_:
.quad _Z29__device_stub__softmax_kerneliiiPffS_
.size _Z14softmax_kerneliiiPffS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14softmax_kerneliiiPffS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__softmax_kerneliiiPffS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14softmax_kerneliiiPffS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
__global__ void convolution(float* input, float* kernel, float* output, int width, int height, int kernel_size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int k_radius = kernel_size / 2;
float sum = 0.0;
for (int i = -k_radius; i <= k_radius; i++) {
for (int j = -k_radius; j <= k_radius; j++) {
int cur_x = x + i;
int cur_y = y + j;
if (cur_x < 0 || cur_x >= width || cur_y < 0 || cur_y >= height) {
continue;
}
float val = input[cur_y * width + cur_x];
float kernel_val = kernel[(j + k_radius) * kernel_size + (i + k_radius)];
sum += val * kernel_val;
}
}
output[y * width + x] = sum;
}
__global__ void helloCUDA(float f){
printf ("Hello thread %d, f=%f\n", threadIdx.x, f);
} | code for sm_80
Function : _Z9helloCUDAf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0020*/ F2F.F64.F32 R2, c[0x0][0x160] ; /* 0x0000580000027b10 */
/* 0x000e620000201800 */
/*0030*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0080*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0004e60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0025e80000100a00 */
/*00b0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0015e60000100800 */
/*00c0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x004fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fc40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0120*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0130*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x008fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11convolutionPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*00c0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe4000f8f083f */
/*00d0*/ ULDC.64 UR20, c[0x0][0x118] ; /* 0x0000460000147ab9 */
/* 0x000fe40000000a00 */
/*00e0*/ USHF.R.S32.HI UR6, URZ, 0x1, UR4 ; /* 0x000000013f067899 */
/* 0x000fc80008011404 */
/*00f0*/ UIADD3 UR7, -UR6, URZ, URZ ; /* 0x0000003f06077290 */
/* 0x000fc8000fffe13f */
/*0100*/ UISETP.GE.AND UP0, UPT, UR6, UR7, UPT ; /* 0x000000070600728c */
/* 0x000fcc000bf06270 */
/*0110*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*0120*/ @!P0 BRA 0xa20 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*0130*/ UIADD3 UR8, -UR6, 0x1, URZ ; /* 0x0000000106087890 */
/* 0x000fe2000fffe13f */
/*0140*/ IADD3 R4, R0.reuse, -UR6, RZ ; /* 0x8000000600047c10 */
/* 0x040fe2000fffe0ff */
/*0150*/ USHF.L.U32 UR15, UR6, 0x1, URZ ; /* 0x00000001060f7899 */
/* 0x000fe2000800063f */
/*0160*/ IADD3 R5, R0.reuse, 0x3, RZ ; /* 0x0000000300057810 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0180*/ IADD3 R7, R0.reuse, 0x2, RZ ; /* 0x0000000200077810 */
/* 0x040fe20007ffe0ff */
/*0190*/ UIADD3 UR4, UR15, 0x1, URZ ; /* 0x000000010f047890 */
/* 0x000fe2000fffe03f */
/*01a0*/ IADD3 R6, R0.reuse, UR8, RZ ; /* 0x0000000800067c10 */
/* 0x040fe2000fffe0ff */
/*01b0*/ UIADD3 UR9, -UR6, 0x3, URZ ; /* 0x0000000306097890 */
/* 0x000fe2000fffe13f */
/*01c0*/ IADD3 R8, R0, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ ULOP3.LUT UR4, UR4, 0x3, URZ, 0xc0, !UPT ; /* 0x0000000304047892 */
/* 0x000fe2000f8ec03f */
/*01e0*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ UIADD3 UR16, UR6, 0x3, URZ ; /* 0x0000000306107890 */
/* 0x000fc4000fffe03f */
/*0200*/ UIADD3 UR17, UR6, 0x2, URZ ; /* 0x0000000206117890 */
/* 0x000fe4000fffe03f */
/*0210*/ UIADD3 UR18, UR6, 0x1, URZ ; /* 0x0000000106127890 */
/* 0x000fe4000fffe03f */
/*0220*/ UISETP.NE.AND UP0, UPT, UR4, 0x1, UPT ; /* 0x000000010400788c */
/* 0x000fc6000bf05270 */
/*0230*/ IADD3 R11, R3, UR7, RZ ; /* 0x00000007030b7c10 */
/* 0x000fe2000fffe0ff */
/*0240*/ UIADD3 UR13, UR6, UR7, URZ ; /* 0x00000007060d7290 */
/* 0x000fe2000fffe03f */
/*0250*/ BSSY B0, 0x380 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0260*/ PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2f008 */
/*0270*/ ISETP.GE.AND P3, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fe40003f66270 */
/*0280*/ LOP3.LUT R10, R4, R11, RZ, 0xfc, !PT ; /* 0x0000000b040a7212 */
/* 0x000fc800078efcff */
/*0290*/ ISETP.LT.OR P0, PT, R10, RZ, P3 ; /* 0x000000ff0a00720c */
/* 0x000fc80001f01670 */
/*02a0*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x17c], P0 ; /* 0x00005f0004007a0c */
/* 0x000fda0000706670 */
/*02b0*/ @P0 BRA 0x370 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*02c0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*02d0*/ UMOV UR10, 0x4 ; /* 0x00000004000a7882 */
/* 0x000fe20000000000 */
/*02e0*/ IMAD R12, R4, c[0x0][0x178], R11 ; /* 0x00005e00040c7a24 */
/* 0x000fe200078e020b */
/*02f0*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0300*/ UIMAD.WIDE UR4, UR13, UR10, UR4 ; /* 0x0000000a0d0472a5 */
/* 0x000fca000f8e0204 */
/*0310*/ IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e020d */
/*0320*/ IMAD.U32 R15, RZ, RZ, UR5 ; /* 0x00000005ff0f7e24 */
/* 0x000fe4000f8e00ff */
/*0330*/ IMAD.U32 R14, RZ, RZ, UR4 ; /* 0x00000004ff0e7e24 */
/* 0x000fe2000f8e00ff */
/*0340*/ LDG.E R12, [R12.64] ; /* 0x000000140c0c7981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R15, [R14.64] ; /* 0x000000140e0f7981 */
/* 0x000ea4000c1e1900 */
/*0360*/ FFMA R2, R15, R12, R2 ; /* 0x0000000c0f027223 */
/* 0x004fe40000000002 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ UMOV UR4, UR8 ; /* 0x0000000800047c82 */
/* 0x000fe20008000000 */
/*0390*/ @!P1 BRA 0x530 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*03a0*/ LOP3.LUT R12, R9, R11.reuse, RZ, 0xfc, !PT ; /* 0x0000000b090c7212 */
/* 0x080fe400078efcff */
/*03b0*/ LOP3.LUT R10, R6, R11, RZ, 0xfc, !PT ; /* 0x0000000b060a7212 */
/* 0x000fc400078efcff */
/*03c0*/ ISETP.LT.OR P1, PT, R12, RZ, P3 ; /* 0x000000ff0c00720c */
/* 0x000fe40001f21670 */
/*03d0*/ ISETP.LT.OR P0, PT, R10, RZ, P3 ; /* 0x000000ff0a00720c */
/* 0x000fe40001f01670 */
/*03e0*/ ISETP.GE.OR P1, PT, R9, c[0x0][0x17c], P1 ; /* 0x00005f0009007a0c */
/* 0x000fe40000f26670 */
/*03f0*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x17c], P0 ; /* 0x00005f0006007a0c */
/* 0x000fe40000706670 */
/*0400*/ MOV R12, UR13 ; /* 0x0000000d000c7c02 */
/* 0x000fd20008000f00 */
/*0410*/ @!P1 IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff109624 */
/* 0x000fe200078e00ff */
/*0420*/ @!P1 MOV R17, 0x4 ; /* 0x0000000400119802 */
/* 0x000fe20000000f00 */
/*0430*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d8424 */
/* 0x000fe200078e00ff */
/*0440*/ @!P0 IADD3 R12, R12, c[0x0][0x180], RZ ; /* 0x000060000c0c8a10 */
/* 0x000fe20007ffe0ff */
/*0450*/ @!P0 IMAD R18, R6, c[0x0][0x178], R11.reuse ; /* 0x00005e0006128a24 */
/* 0x100fe200078e020b */
/*0460*/ @!P1 LEA R16, R16, UR13, 0x1 ; /* 0x0000000d10109c11 */
/* 0x000fe2000f8e08ff */
/*0470*/ @!P1 IMAD R14, R9, c[0x0][0x178], R11 ; /* 0x00005e00090e9a24 */
/* 0x000fe400078e020b */
/*0480*/ @!P0 IMAD.WIDE R18, R18, R13, c[0x0][0x160] ; /* 0x0000580012128625 */
/* 0x000fc800078e020d */
/*0490*/ @!P0 IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; /* 0x00005a000c0c8625 */
/* 0x000fe400078e020d */
/*04a0*/ @!P0 LDG.E R18, [R18.64] ; /* 0x0000001412128981 */
/* 0x000ea4000c1e1900 */
/*04b0*/ @!P1 IMAD.WIDE R14, R14, R17.reuse, c[0x0][0x160] ; /* 0x000058000e0e9625 */
/* 0x080fe400078e0211 */
/*04c0*/ @!P0 LDG.E R13, [R12.64] ; /* 0x000000140c0d8981 */
/* 0x000ea4000c1e1900 */
/*04d0*/ @!P1 IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010109625 */
/* 0x000fe400078e0211 */
/*04e0*/ @!P1 LDG.E R14, [R14.64] ; /* 0x000000140e0e9981 */
/* 0x000ee8000c1e1900 */
/*04f0*/ @!P1 LDG.E R17, [R16.64] ; /* 0x0000001410119981 */
/* 0x000ee2000c1e1900 */
/*0500*/ UMOV UR4, UR9 ; /* 0x0000000900047c82 */
/* 0x000fe20008000000 */
/*0510*/ @!P0 FFMA R2, R13, R18, R2 ; /* 0x000000120d028223 */
/* 0x004fc80000000002 */
/*0520*/ @!P1 FFMA R2, R17, R14, R2 ; /* 0x0000000e11029223 */
/* 0x008fe40000000002 */
/*0530*/ UISETP.GE.U32.AND UP1, UPT, UR15, 0x3, UPT ; /* 0x000000030f00788c */
/* 0x000fe2000bf26070 */
/*0540*/ IMAD.U32 R10, RZ, RZ, UR7 ; /* 0x00000007ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*0550*/ UIADD3 UR7, UR7, 0x1, URZ ; /* 0x0000000107077890 */
/* 0x000fc8000fffe03f */
/*0560*/ PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f018 */
/*0570*/ ISETP.GE.AND P4, PT, R10, UR6, PT ; /* 0x000000060a007c0c */
/* 0x000fd6000bf86270 */
/*0580*/ @!P0 BRA 0xa10 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*0590*/ UIADD3 UR5, UR16, UR4, URZ ; /* 0x0000000410057290 */
/* 0x000fe2000fffe03f */
/*05a0*/ IADD3 R10, R7, UR4, RZ ; /* 0x00000004070a7c10 */
/* 0x000fe2000fffe0ff */
/*05b0*/ UIADD3 UR10, UR17, UR4, URZ ; /* 0x00000004110a7290 */
/* 0x000fe2000fffe03f */
/*05c0*/ IADD3 R12, R5, UR4, RZ ; /* 0x00000004050c7c10 */
/* 0x000fe2000fffe0ff */
/*05d0*/ UIADD3 UR11, UR18, UR4, URZ ; /* 0x00000004120b7290 */
/* 0x000fe2000fffe03f */
/*05e0*/ IADD3 R18, R8, UR4, RZ ; /* 0x0000000408127c10 */
/* 0x000fe2000fffe0ff */
/*05f0*/ UIADD3 UR12, UR6, UR4, URZ ; /* 0x00000004060c7290 */
/* 0x000fe2000fffe03f */
/*0600*/ IADD3 R22, R0, UR4, RZ ; /* 0x0000000400167c10 */
/* 0x000fe2000fffe0ff */
/*0610*/ ULDC UR14, c[0x0][0x180] ; /* 0x00006000000e7ab9 */
/* 0x000fe20000000800 */
/*0620*/ IMAD R13, R10, c[0x0][0x178], R11.reuse ; /* 0x00005e000a0d7a24 */
/* 0x100fe200078e020b */
/*0630*/ UIMAD UR5, UR5, UR14, UR13 ; /* 0x0000000e050572a4 */
/* 0x000fe2000f8e020d */
/*0640*/ IMAD R12, R12, c[0x0][0x178], R11.reuse ; /* 0x00005e000c0c7a24 */
/* 0x100fe200078e020b */
/*0650*/ UIMAD UR10, UR10, UR14, UR13 ; /* 0x0000000e0a0a72a4 */
/* 0x000fe2000f8e020d */
/*0660*/ IMAD R18, R18, c[0x0][0x178], R11.reuse ; /* 0x00005e0012127a24 */
/* 0x100fe200078e020b */
/*0670*/ UIMAD UR11, UR11, UR14, UR13 ; /* 0x0000000e0b0b72a4 */
/* 0x000fe2000f8e020d */
/*0680*/ IMAD R24, R22, c[0x0][0x178], R11 ; /* 0x00005e0016187a24 */
/* 0x000fe200078e020b */
/*0690*/ UIMAD UR12, UR12, UR14, UR13 ; /* 0x0000000e0c0c72a4 */
/* 0x000fe2000f8e020d */
/*06a0*/ IMAD.U32 R10, RZ, RZ, UR5 ; /* 0x00000005ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*06b0*/ MOV R19, UR10 ; /* 0x0000000a00137c02 */
/* 0x000fe20008000f00 */
/*06c0*/ UIADD3 UR19, UR4, -0x1, URZ ; /* 0xffffffff04137890 */
/* 0x000fe2000fffe03f */
/*06d0*/ IMAD.U32 R20, RZ, RZ, UR11 ; /* 0x0000000bff147e24 */
/* 0x000fc4000f8e00ff */
/*06e0*/ IMAD.U32 R26, RZ, RZ, UR12 ; /* 0x0000000cff1a7e24 */
/* 0x000fe4000f8e00ff */
/*06f0*/ LOP3.LUT R14, R22.reuse, R11, RZ, 0xfc, !PT ; /* 0x0000000b160e7212 */
/* 0x040fe200078efcff */
/*0700*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fe200000001ff */
/*0710*/ IADD3 R16, R22, 0x1, RZ ; /* 0x0000000116107810 */
/* 0x000fe40007ffe0ff */
/*0720*/ ISETP.LT.OR P2, PT, R14, RZ, P3 ; /* 0x000000ff0e00720c */
/* 0x000fc80001f41670 */
/*0730*/ ISETP.GE.OR P2, PT, R22, c[0x0][0x17c], P2 ; /* 0x00005f0016007a0c */
/* 0x000fe40001746670 */
/*0740*/ LOP3.LUT R17, R16, R11, RZ, 0xfc, !PT ; /* 0x0000000b10117212 */
/* 0x000fc800078efcff */
/*0750*/ ISETP.LT.OR P1, PT, R17, RZ, P3 ; /* 0x000000ff1100720c */
/* 0x000fc80001f21670 */
/*0760*/ ISETP.GE.OR P1, PT, R16, c[0x0][0x17c], P1 ; /* 0x00005f0010007a0c */
/* 0x000fc60000f26670 */
/*0770*/ @!P2 IMAD.WIDE R14, R24, R21, c[0x0][0x160] ; /* 0x00005800180ea625 */
/* 0x000fc800078e0215 */
/*0780*/ @!P2 IMAD.WIDE R28, R26, R21.reuse, c[0x0][0x168] ; /* 0x00005a001a1ca625 */
/* 0x080fe200078e0215 */
/*0790*/ @!P2 LDG.E R23, [R14.64] ; /* 0x000000140e17a981 */
/* 0x0000a8000c1e1900 */
/*07a0*/ @!P2 LDG.E R27, [R28.64] ; /* 0x000000141c1ba981 */
/* 0x0002a2000c1e1900 */
/*07b0*/ @!P1 IMAD.WIDE R16, R20, R21, c[0x0][0x168] ; /* 0x00005a0014109625 */
/* 0x000fc800078e0215 */
/*07c0*/ @!P1 IMAD.WIDE R14, R18, R21, c[0x0][0x160] ; /* 0x00005800120e9625 */
/* 0x001fe400078e0215 */
/*07d0*/ @!P1 LDG.E R16, [R16.64] ; /* 0x0000001410109981 */
/* 0x0000e8000c1e1900 */
/*07e0*/ @!P1 LDG.E R25, [R14.64] ; /* 0x000000140e199981 */
/* 0x0008e2000c1e1900 */
/*07f0*/ IADD3 R28, R22, 0x2, RZ ; /* 0x00000002161c7810 */
/* 0x002fc80007ffe0ff */
/*0800*/ LOP3.LUT R17, R28, R11, RZ, 0xfc, !PT ; /* 0x0000000b1c117212 */
/* 0x001fc800078efcff */
/*0810*/ ISETP.LT.OR P0, PT, R17, RZ, P3 ; /* 0x000000ff1100720c */
/* 0x000fc80001f01670 */
/*0820*/ ISETP.GE.OR P0, PT, R28, c[0x0][0x17c], P0 ; /* 0x00005f001c007a0c */
/* 0x000fe40000706670 */
/*0830*/ IADD3 R14, R22, 0x3, RZ ; /* 0x00000003160e7810 */
/* 0x010fc80007ffe0ff */
/*0840*/ LOP3.LUT R15, R14, R11, RZ, 0xfc, !PT ; /* 0x0000000b0e0f7212 */
/* 0x000fce00078efcff */
/*0850*/ @!P0 IMAD.WIDE R28, R13, R21, c[0x0][0x160] ; /* 0x000058000d1c8625 */
/* 0x000fc800078e0215 */
/*0860*/ @!P2 FFMA R2, R27, R23, R2 ; /* 0x000000171b02a223 */
/* 0x004fe20000000002 */
/*0870*/ ISETP.LT.OR P2, PT, R15, RZ, P3 ; /* 0x000000ff0f00720c */
/* 0x000fe20001f41670 */
/*0880*/ @!P0 LDG.E R23, [R28.64] ; /* 0x000000141c178981 */
/* 0x0000a6000c1e1900 */
/*0890*/ ISETP.GE.OR P2, PT, R14, c[0x0][0x17c], P2 ; /* 0x00005f000e007a0c */
/* 0x000fe20001746670 */
/*08a0*/ @!P0 IMAD.WIDE R28, R19, R21, c[0x0][0x168] ; /* 0x00005a00131c8625 */
/* 0x001fca00078e0215 */
/*08b0*/ @!P0 LDG.E R27, [R28.64] ; /* 0x000000141c1b8981 */
/* 0x000ea2000c1e1900 */
/*08c0*/ @!P1 FFMA R2, R16, R25, R2 ; /* 0x0000001910029223 */
/* 0x008fcc0000000002 */
/*08d0*/ @!P2 IMAD.WIDE R14, R12, R21, c[0x0][0x160] ; /* 0x000058000c0ea625 */
/* 0x000fc800078e0215 */
/*08e0*/ @!P2 IMAD.WIDE R16, R10, R21, c[0x0][0x168] ; /* 0x00005a000a10a625 */
/* 0x000fe400078e0215 */
/*08f0*/ @!P2 LDG.E R14, [R14.64] ; /* 0x000000140e0ea981 */
/* 0x000ee8000c1e1900 */
/*0900*/ @!P2 LDG.E R17, [R16.64] ; /* 0x000000141011a981 */
/* 0x000ee2000c1e1900 */
/*0910*/ UIADD3 UR19, UR19, 0x4, URZ ; /* 0x0000000413137890 */
/* 0x000fc8000fffe03f */
/*0920*/ UISETP.GE.AND UP1, UPT, UR19, UR6, UPT ; /* 0x000000061300728c */
/* 0x000fe2000bf26270 */
/*0930*/ IMAD R24, R21.reuse, c[0x0][0x178], R24 ; /* 0x00005e0015187a24 */
/* 0x040fe400078e0218 */
/*0940*/ IMAD R18, R21.reuse, c[0x0][0x178], R18 ; /* 0x00005e0015127a24 */
/* 0x040fe400078e0212 */
/*0950*/ IMAD R13, R21.reuse, c[0x0][0x178], R13 ; /* 0x00005e00150d7a24 */
/* 0x040fe400078e020d */
/*0960*/ IMAD R12, R21, c[0x0][0x178], R12 ; /* 0x00005e00150c7a24 */
/* 0x000fe400078e020c */
/*0970*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff157624 */
/* 0x000fe200078e00ff */
/*0980*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fc60007ffe0ff */
/*0990*/ IMAD R26, R21.reuse, 0x4, R26 ; /* 0x00000004151a7824 */
/* 0x040fe200078e021a */
/*09a0*/ LEA R10, R21.reuse, R10, 0x2 ; /* 0x0000000a150a7211 */
/* 0x040fe200078e10ff */
/*09b0*/ IMAD R19, R21.reuse, 0x4, R19 ; /* 0x0000000415137824 */
/* 0x040fe400078e0213 */
/*09c0*/ IMAD R20, R21, 0x4, R20 ; /* 0x0000000415147824 */
/* 0x000fe400078e0214 */
/*09d0*/ @!P0 FFMA R2, R27, R23, R2 ; /* 0x000000171b028223 */
/* 0x004fe20000000002 */
/*09e0*/ PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f018 */
/*09f0*/ @!P2 FFMA R2, R17, R14, R2 ; /* 0x0000000e1102a223 */
/* 0x008fd40000000002 */
/*0a00*/ @!P0 BRA 0x6f0 ; /* 0xfffffce000008947 */
/* 0x000fea000383ffff */
/*0a10*/ @!P4 BRA 0x230 ; /* 0xfffff8100000c947 */
/* 0x000fea000383ffff */
/*0a20*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*0a30*/ IMAD R4, R0, c[0x0][0x178], R3 ; /* 0x00005e0000047a24 */
/* 0x000fc800078e0203 */
/*0a40*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0a50*/ STG.E [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101914 */
/*0a60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a70*/ BRA 0xa70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
__global__ void convolution(float* input, float* kernel, float* output, int width, int height, int kernel_size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int k_radius = kernel_size / 2;
float sum = 0.0;
for (int i = -k_radius; i <= k_radius; i++) {
for (int j = -k_radius; j <= k_radius; j++) {
int cur_x = x + i;
int cur_y = y + j;
if (cur_x < 0 || cur_x >= width || cur_y < 0 || cur_y >= height) {
continue;
}
float val = input[cur_y * width + cur_x];
float kernel_val = kernel[(j + k_radius) * kernel_size + (i + k_radius)];
sum += val * kernel_val;
}
}
output[y * width + x] = sum;
}
__global__ void helloCUDA(float f){
printf ("Hello thread %d, f=%f\n", threadIdx.x, f);
} | .file "tmpxft_001a1093_00000000-6_mykernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii
.type _Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii, @function
_Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii:
.LFB2081:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11convolutionPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii, .-_Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii
.globl _Z11convolutionPfS_S_iii
.type _Z11convolutionPfS_S_iii, @function
_Z11convolutionPfS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z11convolutionPfS_S_iii, .-_Z11convolutionPfS_S_iii
.globl _Z27__device_stub__Z9helloCUDAff
.type _Z27__device_stub__Z9helloCUDAff, @function
_Z27__device_stub__Z9helloCUDAff:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9helloCUDAf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z9helloCUDAff, .-_Z27__device_stub__Z9helloCUDAff
.globl _Z9helloCUDAf
.type _Z9helloCUDAf, @function
_Z9helloCUDAf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9helloCUDAff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9helloCUDAf, .-_Z9helloCUDAf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9helloCUDAf"
.LC1:
.string "_Z11convolutionPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9helloCUDAf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11convolutionPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
__global__ void convolution(float* input, float* kernel, float* output, int width, int height, int kernel_size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int k_radius = kernel_size / 2;
float sum = 0.0;
for (int i = -k_radius; i <= k_radius; i++) {
for (int j = -k_radius; j <= k_radius; j++) {
int cur_x = x + i;
int cur_y = y + j;
if (cur_x < 0 || cur_x >= width || cur_y < 0 || cur_y >= height) {
continue;
}
float val = input[cur_y * width + cur_x];
float kernel_val = kernel[(j + k_radius) * kernel_size + (i + k_radius)];
sum += val * kernel_val;
}
}
output[y * width + x] = sum;
}
__global__ void helloCUDA(float f){
printf ("Hello thread %d, f=%f\n", threadIdx.x, f);
} | #include <hip/hip_runtime.h>
#include "stdio.h"
__global__ void convolution(float* input, float* kernel, float* output, int width, int height, int kernel_size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int k_radius = kernel_size / 2;
float sum = 0.0;
for (int i = -k_radius; i <= k_radius; i++) {
for (int j = -k_radius; j <= k_radius; j++) {
int cur_x = x + i;
int cur_y = y + j;
if (cur_x < 0 || cur_x >= width || cur_y < 0 || cur_y >= height) {
continue;
}
float val = input[cur_y * width + cur_x];
float kernel_val = kernel[(j + k_radius) * kernel_size + (i + k_radius)];
sum += val * kernel_val;
}
}
output[y * width + x] = sum;
}
__global__ void helloCUDA(float f){
printf ("Hello thread %d, f=%f\n", threadIdx.x, f);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
__global__ void convolution(float* input, float* kernel, float* output, int width, int height, int kernel_size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int k_radius = kernel_size / 2;
float sum = 0.0;
for (int i = -k_radius; i <= k_radius; i++) {
for (int j = -k_radius; j <= k_radius; j++) {
int cur_x = x + i;
int cur_y = y + j;
if (cur_x < 0 || cur_x >= width || cur_y < 0 || cur_y >= height) {
continue;
}
float val = input[cur_y * width + cur_x];
float kernel_val = kernel[(j + k_radius) * kernel_size + (i + k_radius)];
sum += val * kernel_val;
}
}
output[y * width + x] = sum;
}
__global__ void helloCUDA(float f){
printf ("Hello thread %d, f=%f\n", threadIdx.x, f);
} | .text
.file "mykernel.hip"
.globl _Z26__device_stub__convolutionPfS_S_iii # -- Begin function _Z26__device_stub__convolutionPfS_S_iii
.p2align 4, 0x90
.type _Z26__device_stub__convolutionPfS_S_iii,@function
_Z26__device_stub__convolutionPfS_S_iii: # @_Z26__device_stub__convolutionPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11convolutionPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__convolutionPfS_S_iii, .Lfunc_end0-_Z26__device_stub__convolutionPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__helloCUDAf # -- Begin function _Z24__device_stub__helloCUDAf
.p2align 4, 0x90
.type _Z24__device_stub__helloCUDAf,@function
_Z24__device_stub__helloCUDAf: # @_Z24__device_stub__helloCUDAf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9helloCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z24__device_stub__helloCUDAf, .Lfunc_end1-_Z24__device_stub__helloCUDAf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11convolutionPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9helloCUDAf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11convolutionPfS_S_iii,@object # @_Z11convolutionPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z11convolutionPfS_S_iii
.p2align 3, 0x0
_Z11convolutionPfS_S_iii:
.quad _Z26__device_stub__convolutionPfS_S_iii
.size _Z11convolutionPfS_S_iii, 8
.type _Z9helloCUDAf,@object # @_Z9helloCUDAf
.globl _Z9helloCUDAf
.p2align 3, 0x0
_Z9helloCUDAf:
.quad _Z24__device_stub__helloCUDAf
.size _Z9helloCUDAf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11convolutionPfS_S_iii"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9helloCUDAf"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__convolutionPfS_S_iii
.addrsig_sym _Z24__device_stub__helloCUDAf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11convolutionPfS_S_iii
.addrsig_sym _Z9helloCUDAf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a1093_00000000-6_mykernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii
.type _Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii, @function
_Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii:
.LFB2081:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11convolutionPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii, .-_Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii
.globl _Z11convolutionPfS_S_iii
.type _Z11convolutionPfS_S_iii, @function
_Z11convolutionPfS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11convolutionPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z11convolutionPfS_S_iii, .-_Z11convolutionPfS_S_iii
.globl _Z27__device_stub__Z9helloCUDAff
.type _Z27__device_stub__Z9helloCUDAff, @function
_Z27__device_stub__Z9helloCUDAff:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9helloCUDAf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z9helloCUDAff, .-_Z27__device_stub__Z9helloCUDAff
.globl _Z9helloCUDAf
.type _Z9helloCUDAf, @function
_Z9helloCUDAf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9helloCUDAff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9helloCUDAf, .-_Z9helloCUDAf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9helloCUDAf"
.LC1:
.string "_Z11convolutionPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9helloCUDAf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11convolutionPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mykernel.hip"
.globl _Z26__device_stub__convolutionPfS_S_iii # -- Begin function _Z26__device_stub__convolutionPfS_S_iii
.p2align 4, 0x90
.type _Z26__device_stub__convolutionPfS_S_iii,@function
_Z26__device_stub__convolutionPfS_S_iii: # @_Z26__device_stub__convolutionPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11convolutionPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__convolutionPfS_S_iii, .Lfunc_end0-_Z26__device_stub__convolutionPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__helloCUDAf # -- Begin function _Z24__device_stub__helloCUDAf
.p2align 4, 0x90
.type _Z24__device_stub__helloCUDAf,@function
_Z24__device_stub__helloCUDAf: # @_Z24__device_stub__helloCUDAf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9helloCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z24__device_stub__helloCUDAf, .Lfunc_end1-_Z24__device_stub__helloCUDAf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11convolutionPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9helloCUDAf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11convolutionPfS_S_iii,@object # @_Z11convolutionPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z11convolutionPfS_S_iii
.p2align 3, 0x0
_Z11convolutionPfS_S_iii:
.quad _Z26__device_stub__convolutionPfS_S_iii
.size _Z11convolutionPfS_S_iii, 8
.type _Z9helloCUDAf,@object # @_Z9helloCUDAf
.globl _Z9helloCUDAf
.p2align 3, 0x0
_Z9helloCUDAf:
.quad _Z24__device_stub__helloCUDAf
.size _Z9helloCUDAf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11convolutionPfS_S_iii"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9helloCUDAf"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__convolutionPfS_S_iii
.addrsig_sym _Z24__device_stub__helloCUDAf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11convolutionPfS_S_iii
.addrsig_sym _Z9helloCUDAf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
int board[16][16] , lock[16][16];
__global__
void possible_move(int sqr , int row,int col ,int move ,int n,int *brd, int *flag){
int tid = threadIdx.x;
if(brd[row*n + tid]==move||brd[tid*n + col]==move||brd[((row/sqr)*sqr+tid/sqr)*n + (col/sqr)*sqr+tid%sqr]==move)
*flag=1;
}
void print_board(int n){
int i ,t1;
for ( i = 0; i < n; i++) {
for (t1 = 0; t1 < n; t1++) {
printf("%d ",board[i][t1]);
}
printf("\n");
}
}
void solve(int n)
{
int i, j ,k,sqr,*ibd,*flag,size,zero;
size = sizeof(int);
sqr=sqrt(n);
zero=0;
cudaMalloc(&ibd,size*n*n);
cudaMalloc(&flag,size);
for(i=0;i<n;i++){
for(j=0;j<n;j++){
if(board[i][j]==0){
for(k=0;k<=n;k++){
cudaMemcpy(flag,&zero,size,cudaMemcpyHostToDevice);
for(int t=0; t<n; t++){
cudaMemcpy(ibd+t*n,(int *)board[t],size*n,cudaMemcpyHostToDevice);
}
possible_move<<<1,n>>>(sqr,i,j,k,n,ibd,flag);
cudaMemcpy(&zero,flag,size,cudaMemcpyDeviceToHost);
if(zero==0)
{board[i][j]=k;break;}
else{
if(k==n){
if(i==0&&j==0)
return;
lock:;
if(j==0){
j=n;
i--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
else{
j--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
if(k==n){
goto lock;
}
}
zero=0;
}
}
}
printf("\nNextmove %d %d\n",i,j);
print_board(n);
}
}
}
int main(){
int n,**s,i,p,t1,t2,t3;
float t4;
printf("Enter Board Size:");
while(1){
scanf("%d",&n);
t4 = sqrt(n);
if(n==(int)t4*(int)t4)
break;
printf("Enter correct Boards size:");
}
//Predefined board Numbers
printf("Enter no. of Predefined numbers:");
scanf("%d",&p );
for(i=0;i<p;i++){
scanf("%d%d%d",&t1,&t2,&t3);
if(t1<=n&&t2<=n&&t3<=n&&t1>0&&t2>0&&t3>0){
board[t1-1][t2-1]=t3;
lock[t1-1][t2-1]=1;
}
}
//Print board
printf("\nInitial Board\n");
print_board(n);
//solve board
solve(n);
printf("\nFinal Board\n");
print_board(n);
return 0;
} | code for sm_80
Function : _Z13possible_moveiiiiiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD R5, R3, c[0x0][0x164], R2 ; /* 0x0000590003057a24 */
/* 0x001fc800078e0202 */
/*0060*/ IMAD.WIDE R4, R5, R0, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fcc00078e0200 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x4b0 ; /* 0x0000042000007945 */
/* 0x000fe20003800000 */
/*0090*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x004fda0003f05270 */
/*00a0*/ @!P0 BRA 0x4a0 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R5, R2, R3, c[0x0][0x168] ; /* 0x00005a0002057624 */
/* 0x000fc800078e0203 */
/*00c0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fcc00078e0200 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 BRA 0x4a0 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*0100*/ IABS R8, c[0x0][0x160] ; /* 0x0000580000087a13 */
/* 0x000fe40000000000 */
/*0110*/ IABS R9, R2 ; /* 0x0000000200097213 */
/* 0x000fe40000000000 */
/*0120*/ I2F.RP R3, R8 ; /* 0x0000000800037306 */
/* 0x000e220000209400 */
/*0130*/ IABS R6, c[0x0][0x164] ; /* 0x0000590000067a13 */
/* 0x000fe40000000000 */
/*0140*/ IABS R10, c[0x0][0x168] ; /* 0x00005a00000a7a13 */
/* 0x000fe40000000000 */
/*0150*/ ISETP.LE.AND P3, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fc60003f63270 */
/*0160*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0170*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*0180*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*01a0*/ IADD3 R7, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x002fca0007ffe0ff */
/*01b0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*01c0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fc800078e0004 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0009 */
/*01e0*/ IMAD.HI.U32 R3, R5, R6, RZ ; /* 0x0000000605037227 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.HI.U32 R4, R5, R7, RZ ; /* 0x0000000705047227 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fc60007ffe1ff */
/*0210*/ IMAD.HI.U32 R5, R5, R10, RZ ; /* 0x0000000a05057227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.MOV R9, RZ, RZ, -R4 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a04 */
/*0230*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a05 */
/*0240*/ IMAD R5, R8.reuse, R9, R7 ; /* 0x0000000908057224 */
/* 0x040fe400078e0207 */
/*0250*/ IMAD R3, R8.reuse, R3, R6 ; /* 0x0000000308037224 */
/* 0x040fe400078e0206 */
/*0260*/ IMAD R6, R8.reuse, R11, R10 ; /* 0x0000000b08067224 */
/* 0x040fe200078e020a */
/*0270*/ ISETP.GT.U32.AND P5, PT, R8.reuse, R5, PT ; /* 0x000000050800720c */
/* 0x040fe40003fa4070 */
/*0280*/ ISETP.GT.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fc40003f04070 */
/*0290*/ ISETP.GT.U32.AND P1, PT, R8, R6, PT ; /* 0x000000060800720c */
/* 0x000fd20003f24070 */
/*02a0*/ @!P5 IMAD.IADD R5, R5, 0x1, -R8.reuse ; /* 0x000000010505d824 */
/* 0x100fe200078e0a08 */
/*02b0*/ @!P5 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404d810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ @!P0 IADD3 R3, R3, -R8.reuse, RZ ; /* 0x8000000803038210 */
/* 0x080fe20007ffe0ff */
/*02d0*/ @!P1 IMAD.IADD R6, R6, 0x1, -R8 ; /* 0x0000000106069824 */
/* 0x000fe200078e0a08 */
/*02e0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fe40003f26070 */
/*02f0*/ LOP3.LUT R5, R2, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580002057a12 */
/* 0x000fe400078e3cff */
/*0300*/ ISETP.GT.U32.AND P0, PT, R8.reuse, R3, PT ; /* 0x000000030800720c */
/* 0x040fe40003f04070 */
/*0310*/ ISETP.GT.U32.AND P2, PT, R8, R6, PT ; /* 0x000000060800720c */
/* 0x000fc40003f44070 */
/*0320*/ ISETP.GE.AND P4, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f86270 */
/*0330*/ ISETP.LE.AND P5, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003fa3270 */
/*0340*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fc80007ffe0ff */
/*0350*/ @!P0 IADD3 R3, R3, -R8, RZ ; /* 0x8000000803038210 */
/* 0x000fe20007ffe0ff */
/*0360*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0004 */
/*0370*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe20003f05270 */
/*0380*/ @!P2 IMAD.IADD R6, R6, 0x1, -R8 ; /* 0x000000010606a824 */
/* 0x000fe200078e0a08 */
/*0390*/ LOP3.LUT R4, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff047a12 */
/* 0x000fe200078e33ff */
/*03a0*/ @!P4 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05c224 */
/* 0x000fe200078e0a05 */
/*03b0*/ @!P3 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff0303b210 */
/* 0x000fe20007ffe1ff */
/*03c0*/ @!P5 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff06d224 */
/* 0x000fc600078e0a06 */
/*03d0*/ SEL R3, R4.reuse, R3, !P0 ; /* 0x0000000304037207 */
/* 0x040fe40004000000 */
/*03e0*/ SEL R8, R4.reuse, R5, !P0 ; /* 0x0000000504087207 */
/* 0x040fe40004000000 */
/*03f0*/ SEL R4, R4, R6, !P0 ; /* 0x0000000604047207 */
/* 0x000fe40004000000 */
/*0400*/ IADD3 R5, R8.reuse, c[0x0][0x164], -R3 ; /* 0x0000590008057a10 */
/* 0x040fe40007ffe803 */
/*0410*/ IADD3 R3, -R8, RZ, RZ ; /* 0x000000ff08037210 */
/* 0x000fe40007ffe1ff */
/*0420*/ IADD3 R4, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc60007ffe1ff */
/*0430*/ IMAD R3, R3, c[0x0][0x160], R2 ; /* 0x0000580003037a24 */
/* 0x000fe400078e0202 */
/*0440*/ IMAD R4, R5, c[0x0][0x170], R4 ; /* 0x00005c0005047a24 */
/* 0x000fc800078e0204 */
/*0450*/ IMAD.IADD R3, R4, 0x1, R3 ; /* 0x0000000104037824 */
/* 0x000fc800078e0203 */
/*0460*/ IMAD.WIDE R2, R3, R0, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fcc00078e0200 */
/*0470*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0480*/ ISETP.NE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x004fda0003f05270 */
/*0490*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*04c0*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x000fe20000000f00 */
/*04d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fca00078e00ff */
/*04e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
int board[16][16] , lock[16][16];
__global__
void possible_move(int sqr , int row,int col ,int move ,int n,int *brd, int *flag){
int tid = threadIdx.x;
if(brd[row*n + tid]==move||brd[tid*n + col]==move||brd[((row/sqr)*sqr+tid/sqr)*n + (col/sqr)*sqr+tid%sqr]==move)
*flag=1;
}
void print_board(int n){
int i ,t1;
for ( i = 0; i < n; i++) {
for (t1 = 0; t1 < n; t1++) {
printf("%d ",board[i][t1]);
}
printf("\n");
}
}
void solve(int n)
{
int i, j ,k,sqr,*ibd,*flag,size,zero;
size = sizeof(int);
sqr=sqrt(n);
zero=0;
cudaMalloc(&ibd,size*n*n);
cudaMalloc(&flag,size);
for(i=0;i<n;i++){
for(j=0;j<n;j++){
if(board[i][j]==0){
for(k=0;k<=n;k++){
cudaMemcpy(flag,&zero,size,cudaMemcpyHostToDevice);
for(int t=0; t<n; t++){
cudaMemcpy(ibd+t*n,(int *)board[t],size*n,cudaMemcpyHostToDevice);
}
possible_move<<<1,n>>>(sqr,i,j,k,n,ibd,flag);
cudaMemcpy(&zero,flag,size,cudaMemcpyDeviceToHost);
if(zero==0)
{board[i][j]=k;break;}
else{
if(k==n){
if(i==0&&j==0)
return;
lock:;
if(j==0){
j=n;
i--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
else{
j--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
if(k==n){
goto lock;
}
}
zero=0;
}
}
}
printf("\nNextmove %d %d\n",i,j);
print_board(n);
}
}
}
int main(){
int n,**s,i,p,t1,t2,t3;
float t4;
printf("Enter Board Size:");
while(1){
scanf("%d",&n);
t4 = sqrt(n);
if(n==(int)t4*(int)t4)
break;
printf("Enter correct Boards size:");
}
//Predefined board Numbers
printf("Enter no. of Predefined numbers:");
scanf("%d",&p );
for(i=0;i<p;i++){
scanf("%d%d%d",&t1,&t2,&t3);
if(t1<=n&&t2<=n&&t3<=n&&t1>0&&t2>0&&t3>0){
board[t1-1][t2-1]=t3;
lock[t1-1][t2-1]=1;
}
}
//Print board
printf("\nInitial Board\n");
print_board(n);
//solve board
solve(n);
printf("\nFinal Board\n");
print_board(n);
return 0;
} | .file "tmpxft_0017779c_00000000-6_gpusudokusolver.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z11print_boardi
.type _Z11print_boardi, @function
_Z11print_boardi:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L9
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movslq %edi, %r13
leaq board(%rip), %rdx
leaq (%rdx,%r13,4), %rbp
movq %r13, %rax
salq $4, %rax
addq %r13, %rax
leaq (%rdx,%rax,4), %r14
negq %r13
salq $2, %r13
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r15
.L5:
leaq 0(%rbp,%r13), %rbx
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z11print_boardi, .-_Z11print_boardi
.globl _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_
.type _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_, @function
_Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13possible_moveiiiiiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_, .-_Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_
.globl _Z13possible_moveiiiiiPiS_
.type _Z13possible_moveiiiiiPiS_, @function
_Z13possible_moveiiiiiPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13possible_moveiiiiiPiS_, .-_Z13possible_moveiiiiiPiS_
.section .rodata.str1.1
.LC3:
.string "\nNextmove %d %d\n"
.text
.globl _Z5solvei
.type _Z5solvei, @function
_Z5solvei:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, 16(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L44
sqrtsd %xmm0, %xmm0
.L23:
cvttsd2sil %xmm0, %eax
movl %eax, 28(%rsp)
movl $0, 44(%rsp)
movl 16(%rsp), %ebx
movl %ebx, %esi
imull %ebx, %esi
sall $2, %esi
movslq %esi, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %ebx, %ebx
jle .L20
leal 0(,%rbx,4), %r12d
movslq %r12d, %r12
movslq %ebx, %rax
leaq 0(,%rax,4), %r15
salq $6, %rax
leaq board(%rip), %rdx
leaq (%rax,%rdx), %r14
movl $0, 24(%rsp)
jmp .L25
.L44:
call sqrt@PLT
jmp .L23
.L28:
movl $2, %ecx
movl $4, %edx
movq 56(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, 44(%rsp)
je .L46
cmpl %r13d, 16(%rsp)
je .L47
.L30:
movl $0, 44(%rsp)
addl $1, %r13d
cmpl %r13d, 16(%rsp)
jl .L26
.L36:
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq board(%rip), %rbx
movl $0, %ebp
.L27:
movq %rbp, %rdi
addq 48(%rsp), %rdi
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
call cudaMemcpy@PLT
addq %r15, %rbp
addq $64, %rbx
cmpq %r14, %rbx
jne .L27
movl 16(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L28
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq 64(%rsp)
.cfi_def_cfa_offset 176
movq 64(%rsp), %r9
movl 32(%rsp), %r8d
movl %r13d, %ecx
movl 36(%rsp), %edx
movl 40(%rsp), %esi
movl 44(%rsp), %edi
call _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L46:
movslq 20(%rsp), %rcx
movslq 24(%rsp), %rdx
salq $4, %rdx
addq %rcx, %rdx
leaq board(%rip), %rax
movl %r13d, (%rax,%rdx,4)
.L26:
movl 20(%rsp), %ebx
movl %ebx, %ecx
movl 24(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ebp
movl %ebp, %edi
call _Z11print_boardi
movl %ebx, %eax
addl $1, %eax
movl %eax, 20(%rsp)
cmpl %eax, %ebp
jle .L48
.L37:
movslq 20(%rsp), %rdx
movslq 24(%rsp), %rax
salq $4, %rax
addq %rdx, %rax
leaq board(%rip), %rdx
movl (%rdx,%rax,4), %r13d
testl %r13d, %r13d
jne .L26
leaq 44(%rsp), %rax
movq %rax, 8(%rsp)
jmp .L36
.L47:
movl 24(%rsp), %esi
movl %esi, %edx
movl 20(%rsp), %eax
orl %eax, %edx
je .L20
movslq 16(%rsp), %rdx
jmp .L32
.L39:
movl 16(%rsp), %eax
jmp .L32
.L33:
subl $1, %eax
movslq %eax, %rdi
movslq %esi, %rcx
salq $4, %rcx
addq %rdi, %rcx
leaq lock(%rip), %rbx
cmpl $1, (%rbx,%rcx,4)
je .L32
movslq %esi, %rcx
salq $4, %rcx
addq %rdi, %rcx
leaq board(%rip), %rbx
movl (%rbx,%rcx,4), %r13d
movl $0, (%rbx,%rcx,4)
.L35:
movl 16(%rsp), %ecx
cmpl %ecx, %r13d
jne .L49
.L32:
testl %eax, %eax
jne .L33
subl $1, %esi
movslq %esi, %rax
salq $4, %rax
addq %rdx, %rax
leaq lock(%rip), %rcx
cmpl $1, (%rcx,%rax,4)
je .L39
movslq %esi, %rax
salq $4, %rax
addq %rdx, %rax
leaq board(%rip), %rcx
movl (%rcx,%rax,4), %r13d
movl $0, (%rcx,%rax,4)
movl 16(%rsp), %eax
jmp .L35
.L49:
movl %esi, 24(%rsp)
movl %eax, 20(%rsp)
jmp .L30
.L48:
addl $1, 24(%rsp)
movl 24(%rsp), %eax
cmpl %eax, 16(%rsp)
jle .L20
.L25:
movl $0, 20(%rsp)
jmp .L37
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z5solvei, .-_Z5solvei
.section .rodata.str1.1
.LC4:
.string "Enter Board Size:"
.LC5:
.string "%d"
.LC6:
.string "Enter correct Boards size:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Enter no. of Predefined numbers:"
.section .rodata.str1.1
.LC8:
.string "%d%d%d"
.LC9:
.string "\nInitial Board\n"
.LC10:
.string "\nFinal Board\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC4(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %r13
leaq .LC5(%rip), %r12
movl $0x000000000, %ebp
leaq .LC6(%rip), %r14
.L56:
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 4(%rsp), %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq %rbp, %xmm1
ucomisd %xmm0, %xmm1
ja .L63
sqrtsd %xmm0, %xmm0
.L54:
cvtsd2ss %xmm0, %xmm0
cvttss2sil %xmm0, %eax
imull %eax, %eax
cmpl %eax, %ebx
je .L55
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L56
.L63:
call sqrt@PLT
jmp .L54
.L55:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $0, 8(%rsp)
jle .L57
movl $0, %ebx
leaq .LC8(%rip), %rbp
jmp .L59
.L58:
addl $1, %ebx
cmpl %ebx, 8(%rsp)
jle .L57
.L59:
leaq 20(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %edx
movl 4(%rsp), %eax
cmpl %eax, %edx
jg .L58
movl 16(%rsp), %ecx
cmpl %ecx, %eax
jl .L58
movl 20(%rsp), %edi
testl %edx, %edx
setg %sil
cmpl %edi, %eax
setge %al
andl %esi, %eax
testl %ecx, %ecx
setg %sil
testb %sil, %al
je .L58
testl %edi, %edi
jle .L58
leal -1(%rdx), %eax
subl $1, %ecx
movslq %ecx, %rcx
cltq
salq $4, %rax
addq %rcx, %rax
leaq board(%rip), %rdx
movl %edi, (%rdx,%rax,4)
leaq lock(%rip), %rdx
movl $1, (%rdx,%rax,4)
jmp .L58
.L57:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %edi
call _Z11print_boardi
movl 4(%rsp), %edi
call _Z5solvei
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %edi
call _Z11print_boardi
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z13possible_moveiiiiiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z13possible_moveiiiiiPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl lock
.bss
.align 32
.type lock, @object
.size lock, 1024
lock:
.zero 1024
.globl board
.align 32
.type board, @object
.size board, 1024
board:
.zero 1024
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
int board[16][16] , lock[16][16];
__global__
void possible_move(int sqr , int row,int col ,int move ,int n,int *brd, int *flag){
int tid = threadIdx.x;
if(brd[row*n + tid]==move||brd[tid*n + col]==move||brd[((row/sqr)*sqr+tid/sqr)*n + (col/sqr)*sqr+tid%sqr]==move)
*flag=1;
}
void print_board(int n){
int i ,t1;
for ( i = 0; i < n; i++) {
for (t1 = 0; t1 < n; t1++) {
printf("%d ",board[i][t1]);
}
printf("\n");
}
}
void solve(int n)
{
int i, j ,k,sqr,*ibd,*flag,size,zero;
size = sizeof(int);
sqr=sqrt(n);
zero=0;
cudaMalloc(&ibd,size*n*n);
cudaMalloc(&flag,size);
for(i=0;i<n;i++){
for(j=0;j<n;j++){
if(board[i][j]==0){
for(k=0;k<=n;k++){
cudaMemcpy(flag,&zero,size,cudaMemcpyHostToDevice);
for(int t=0; t<n; t++){
cudaMemcpy(ibd+t*n,(int *)board[t],size*n,cudaMemcpyHostToDevice);
}
possible_move<<<1,n>>>(sqr,i,j,k,n,ibd,flag);
cudaMemcpy(&zero,flag,size,cudaMemcpyDeviceToHost);
if(zero==0)
{board[i][j]=k;break;}
else{
if(k==n){
if(i==0&&j==0)
return;
lock:;
if(j==0){
j=n;
i--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
else{
j--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
if(k==n){
goto lock;
}
}
zero=0;
}
}
}
printf("\nNextmove %d %d\n",i,j);
print_board(n);
}
}
}
int main(){
int n,**s,i,p,t1,t2,t3;
float t4;
printf("Enter Board Size:");
while(1){
scanf("%d",&n);
t4 = sqrt(n);
if(n==(int)t4*(int)t4)
break;
printf("Enter correct Boards size:");
}
//Predefined board Numbers
printf("Enter no. of Predefined numbers:");
scanf("%d",&p );
for(i=0;i<p;i++){
scanf("%d%d%d",&t1,&t2,&t3);
if(t1<=n&&t2<=n&&t3<=n&&t1>0&&t2>0&&t3>0){
board[t1-1][t2-1]=t3;
lock[t1-1][t2-1]=1;
}
}
//Print board
printf("\nInitial Board\n");
print_board(n);
//solve board
solve(n);
printf("\nFinal Board\n");
print_board(n);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
int board[16][16] , lock[16][16];
__global__
void possible_move(int sqr , int row,int col ,int move ,int n,int *brd, int *flag){
int tid = threadIdx.x;
if(brd[row*n + tid]==move||brd[tid*n + col]==move||brd[((row/sqr)*sqr+tid/sqr)*n + (col/sqr)*sqr+tid%sqr]==move)
*flag=1;
}
void print_board(int n){
int i ,t1;
for ( i = 0; i < n; i++) {
for (t1 = 0; t1 < n; t1++) {
printf("%d ",board[i][t1]);
}
printf("\n");
}
}
void solve(int n)
{
int i, j ,k,sqr,*ibd,*flag,size,zero;
size = sizeof(int);
sqr=sqrt(n);
zero=0;
hipMalloc(&ibd,size*n*n);
hipMalloc(&flag,size);
for(i=0;i<n;i++){
for(j=0;j<n;j++){
if(board[i][j]==0){
for(k=0;k<=n;k++){
hipMemcpy(flag,&zero,size,hipMemcpyHostToDevice);
for(int t=0; t<n; t++){
hipMemcpy(ibd+t*n,(int *)board[t],size*n,hipMemcpyHostToDevice);
}
possible_move<<<1,n>>>(sqr,i,j,k,n,ibd,flag);
hipMemcpy(&zero,flag,size,hipMemcpyDeviceToHost);
if(zero==0)
{board[i][j]=k;break;}
else{
if(k==n){
if(i==0&&j==0)
return;
lock:;
if(j==0){
j=n;
i--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
else{
j--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
if(k==n){
goto lock;
}
}
zero=0;
}
}
}
printf("\nNextmove %d %d\n",i,j);
print_board(n);
}
}
}
int main(){
int n,**s,i,p,t1,t2,t3;
float t4;
printf("Enter Board Size:");
while(1){
scanf("%d",&n);
t4 = sqrt(n);
if(n==(int)t4*(int)t4)
break;
printf("Enter correct Boards size:");
}
//Predefined board Numbers
printf("Enter no. of Predefined numbers:");
scanf("%d",&p );
for(i=0;i<p;i++){
scanf("%d%d%d",&t1,&t2,&t3);
if(t1<=n&&t2<=n&&t3<=n&&t1>0&&t2>0&&t3>0){
board[t1-1][t2-1]=t3;
lock[t1-1][t2-1]=1;
}
}
//Print board
printf("\nInitial Board\n");
print_board(n);
//solve board
solve(n);
printf("\nFinal Board\n");
print_board(n);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
int board[16][16] , lock[16][16];
__global__
void possible_move(int sqr , int row,int col ,int move ,int n,int *brd, int *flag){
int tid = threadIdx.x;
if(brd[row*n + tid]==move||brd[tid*n + col]==move||brd[((row/sqr)*sqr+tid/sqr)*n + (col/sqr)*sqr+tid%sqr]==move)
*flag=1;
}
void print_board(int n){
int i ,t1;
for ( i = 0; i < n; i++) {
for (t1 = 0; t1 < n; t1++) {
printf("%d ",board[i][t1]);
}
printf("\n");
}
}
void solve(int n)
{
int i, j ,k,sqr,*ibd,*flag,size,zero;
size = sizeof(int);
sqr=sqrt(n);
zero=0;
hipMalloc(&ibd,size*n*n);
hipMalloc(&flag,size);
for(i=0;i<n;i++){
for(j=0;j<n;j++){
if(board[i][j]==0){
for(k=0;k<=n;k++){
hipMemcpy(flag,&zero,size,hipMemcpyHostToDevice);
for(int t=0; t<n; t++){
hipMemcpy(ibd+t*n,(int *)board[t],size*n,hipMemcpyHostToDevice);
}
possible_move<<<1,n>>>(sqr,i,j,k,n,ibd,flag);
hipMemcpy(&zero,flag,size,hipMemcpyDeviceToHost);
if(zero==0)
{board[i][j]=k;break;}
else{
if(k==n){
if(i==0&&j==0)
return;
lock:;
if(j==0){
j=n;
i--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
else{
j--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
if(k==n){
goto lock;
}
}
zero=0;
}
}
}
printf("\nNextmove %d %d\n",i,j);
print_board(n);
}
}
}
int main(){
int n,**s,i,p,t1,t2,t3;
float t4;
printf("Enter Board Size:");
while(1){
scanf("%d",&n);
t4 = sqrt(n);
if(n==(int)t4*(int)t4)
break;
printf("Enter correct Boards size:");
}
//Predefined board Numbers
printf("Enter no. of Predefined numbers:");
scanf("%d",&p );
for(i=0;i<p;i++){
scanf("%d%d%d",&t1,&t2,&t3);
if(t1<=n&&t2<=n&&t3<=n&&t1>0&&t2>0&&t3>0){
board[t1-1][t2-1]=t3;
lock[t1-1][t2-1]=1;
}
}
//Print board
printf("\nInitial Board\n");
print_board(n);
//solve board
solve(n);
printf("\nFinal Board\n");
print_board(n);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13possible_moveiiiiiPiS_
.globl _Z13possible_moveiiiiiPiS_
.p2align 8
.type _Z13possible_moveiiiiiPiS_,@function
_Z13possible_moveiiiiiPiS_:
s_clause 0x2
s_load_b32 s9, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b64 s[4:5], s[0:1], 0x18
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s3, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s7, s2, v1
v_cmpx_ne_u32_e64 s2, v1
s_cbranch_execz .LBB0_4
s_load_b32 s6, s[0:1], 0x8
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s3, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s10, s2, v1
v_cmpx_ne_u32_e64 s2, v1
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s14, s12, s13
s_xor_b32 s14, s14, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s14
s_sub_i32 s16, 0, s14
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s16, s16, s15
s_mul_hi_u32 s16, s15, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_add_i32 s15, s15, s16
s_ashr_i32 s16, s9, 31
v_mul_hi_u32 v1, v0, s15
s_add_i32 s17, s9, s16
s_xor_b32 s17, s17, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s18, s17, s15
s_mul_i32 s18, s18, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v1, s14
v_add_nc_u32_e32 v3, 1, v1
s_sub_i32 s17, s17, s18
s_sub_i32 s18, s17, s14
s_cmp_ge_u32 s17, s14
s_cselect_b32 s17, s18, s17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
s_sub_i32 s18, s17, s14
s_cmp_ge_u32 s17, s14
s_cselect_b32 s17, s18, s17
v_subrev_nc_u32_e32 v4, s14, v2
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_ashr_i32 s18, s6, 31
s_xor_b32 s17, s17, s16
s_add_i32 s19, s6, s18
s_sub_i32 s16, s16, s17
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
s_xor_b32 s19, s19, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_hi_u32 s15, s19, s15
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, 1, v1
s_mul_i32 s15, s15, s14
s_sub_i32 s15, s19, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
v_xor_b32_e32 v1, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s13, v1
s_sub_i32 s13, s15, s14
s_cmp_ge_u32 s15, s14
s_cselect_b32 s13, s13, s15
v_add3_u32 v2, s9, s16, v1
v_mul_lo_u32 v1, v1, s12
s_sub_i32 s9, s13, s14
s_cmp_ge_u32 s13, s14
s_cselect_b32 s9, s9, s13
v_mul_lo_u32 v2, v2, s3
s_xor_b32 s3, s9, s18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_sub_nc_u32_e32 v0, v0, v1
s_sub_i32 s3, s18, s3
s_add_i32 s3, s6, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s3, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s2, v0
s_and_not1_b32 s2, s10, exec_lo
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s2, s3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s7, exec_lo
s_and_b32 s3, s10, exec_lo
s_or_b32 s7, s2, s3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x20
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13possible_moveiiiiiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13possible_moveiiiiiPiS_, .Lfunc_end0-_Z13possible_moveiiiiiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13possible_moveiiiiiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z13possible_moveiiiiiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
int board[16][16] , lock[16][16];
__global__
void possible_move(int sqr , int row,int col ,int move ,int n,int *brd, int *flag){
int tid = threadIdx.x;
if(brd[row*n + tid]==move||brd[tid*n + col]==move||brd[((row/sqr)*sqr+tid/sqr)*n + (col/sqr)*sqr+tid%sqr]==move)
*flag=1;
}
void print_board(int n){
int i ,t1;
for ( i = 0; i < n; i++) {
for (t1 = 0; t1 < n; t1++) {
printf("%d ",board[i][t1]);
}
printf("\n");
}
}
void solve(int n)
{
int i, j ,k,sqr,*ibd,*flag,size,zero;
size = sizeof(int);
sqr=sqrt(n);
zero=0;
hipMalloc(&ibd,size*n*n);
hipMalloc(&flag,size);
for(i=0;i<n;i++){
for(j=0;j<n;j++){
if(board[i][j]==0){
for(k=0;k<=n;k++){
hipMemcpy(flag,&zero,size,hipMemcpyHostToDevice);
for(int t=0; t<n; t++){
hipMemcpy(ibd+t*n,(int *)board[t],size*n,hipMemcpyHostToDevice);
}
possible_move<<<1,n>>>(sqr,i,j,k,n,ibd,flag);
hipMemcpy(&zero,flag,size,hipMemcpyDeviceToHost);
if(zero==0)
{board[i][j]=k;break;}
else{
if(k==n){
if(i==0&&j==0)
return;
lock:;
if(j==0){
j=n;
i--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
else{
j--;
if(lock[i][j]==1)
goto lock;
k=board[i][j];
board[i][j]=0;
}
if(k==n){
goto lock;
}
}
zero=0;
}
}
}
printf("\nNextmove %d %d\n",i,j);
print_board(n);
}
}
}
int main(){
int n,**s,i,p,t1,t2,t3;
float t4;
printf("Enter Board Size:");
while(1){
scanf("%d",&n);
t4 = sqrt(n);
if(n==(int)t4*(int)t4)
break;
printf("Enter correct Boards size:");
}
//Predefined board Numbers
printf("Enter no. of Predefined numbers:");
scanf("%d",&p );
for(i=0;i<p;i++){
scanf("%d%d%d",&t1,&t2,&t3);
if(t1<=n&&t2<=n&&t3<=n&&t1>0&&t2>0&&t3>0){
board[t1-1][t2-1]=t3;
lock[t1-1][t2-1]=1;
}
}
//Print board
printf("\nInitial Board\n");
print_board(n);
//solve board
solve(n);
printf("\nFinal Board\n");
print_board(n);
return 0;
} | .text
.file "gpusudokusolver.hip"
.globl _Z28__device_stub__possible_moveiiiiiPiS_ # -- Begin function _Z28__device_stub__possible_moveiiiiiPiS_
.p2align 4, 0x90
.type _Z28__device_stub__possible_moveiiiiiPiS_,@function
_Z28__device_stub__possible_moveiiiiiPiS_: # @_Z28__device_stub__possible_moveiiiiiPiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13possible_moveiiiiiPiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__possible_moveiiiiiPiS_, .Lfunc_end0-_Z28__device_stub__possible_moveiiiiiPiS_
.cfi_endproc
# -- End function
.globl _Z11print_boardi # -- Begin function _Z11print_boardi
.p2align 4, 0x90
.type _Z11print_boardi,@function
_Z11print_boardi: # @_Z11print_boardi
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edi, %ebx
movl $board, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %rbx
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq %rbx, %r15
jne .LBB1_2
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_6: # %._crit_edge12
retq
.Lfunc_end1:
.size _Z11print_boardi, .Lfunc_end1-_Z11print_boardi
.cfi_endproc
# -- End function
.globl _Z5solvei # -- Begin function _Z5solvei
.p2align 4, 0x90
.type _Z5solvei,@function
_Z5solvei: # @_Z5solvei
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
cvtsi2sd %edi, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB2_3
.LBB2_2: # %call.sqrt
callq sqrt
.LBB2_3: # %.split
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $0, 4(%rsp)
leal (,%rbp,4), %ebx
movl %ebx, %eax
imull %ebp, %eax
movslq %eax, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %ebp, %ebp
jle .LBB2_28
# %bb.4: # %.preheader81.lr.ph
cvttsd2si 8(%rsp), %eax # 8-byte Folded Reload
movl %eax, 24(%rsp) # 4-byte Spill
movabsq $4294967296, %rax # imm = 0x100000000
movl %ebx, %ecx
movq %rcx, 80(%rsp) # 8-byte Spill
movl %ebp, %r12d
leaq (%r12,%rax), %rcx
movq %rcx, 72(%rsp) # 8-byte Spill
leaq (,%r12,4), %rcx
movq %rcx, 64(%rsp) # 8-byte Spill
incq %rax
movq %rax, 88(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %ebx, %ebx
movq %rbp, 96(%rsp) # 8-byte Spill
movq %r12, 56(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_5: # %.lr.ph101
# =>This Loop Header: Depth=1
# Child Loop BB2_7 Depth 2
# Child Loop BB2_8 Depth 3
# Child Loop BB2_15 Depth 3
# Child Loop BB2_16 Depth 4
# Child Loop BB2_23 Depth 2
# Child Loop BB2_24 Depth 3
movslq %r14d, %rax
movslq %ebx, %rcx
shlq $6, %rax
cmpl $0, board(%rax,%rcx,4)
je .LBB2_6
.LBB2_22: # %.loopexit79
# in Loop: Header=BB2_5 Depth=1
movl $.L.str.2, %edi
movl %r14d, 8(%rsp) # 4-byte Spill
movl %r14d, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl $board, %r15d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_23: # %.preheader.i
# Parent Loop BB2_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_24 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_24: # Parent Loop BB2_5 Depth=1
# Parent Loop BB2_23 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB2_24
# %bb.25: # %._crit_edge.i
# in Loop: Header=BB2_23 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r13
addq $64, %r15
cmpq %r12, %r13
jne .LBB2_23
# %bb.26: # %_Z11print_boardi.exit
# in Loop: Header=BB2_5 Depth=1
incl %ebx
cmpl %ebp, %ebx
movl 8(%rsp), %r14d # 4-byte Reload
jl .LBB2_5
# %bb.27: # %._crit_edge102
# in Loop: Header=BB2_5 Depth=1
incl %r14d
movl $0, %ebx
cmpl %ebp, %r14d
jl .LBB2_5
jmp .LBB2_28
.p2align 4, 0x90
.LBB2_6: # %.lr.ph97.preheader
# in Loop: Header=BB2_5 Depth=1
xorl %eax, %eax
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_21: # %.loopexit
# in Loop: Header=BB2_7 Depth=2
movl $0, 4(%rsp)
leal 1(%r15), %eax
cmpl %ebp, %r15d
# kill: def $eax killed $eax def $rax
jge .LBB2_22
.LBB2_7: # %.lr.ph97
# Parent Loop BB2_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_8 Depth 3
# Child Loop BB2_15 Depth 3
# Child Loop BB2_16 Depth 4
movq %rax, 104(%rsp) # 8-byte Spill
movl %r14d, 8(%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
movl $4, %edx
leaq 4(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl $board, %r13d
movq %r12, %r14
xorl %ebp, %ebp
movq 80(%rsp), %r15 # 8-byte Reload
movq 64(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_5 Depth=1
# Parent Loop BB2_7 Depth=2
# => This Inner Loop Header: Depth=3
movq 48(%rsp), %rdi
addq %rbp, %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
addq %r12, %rbp
addq $64, %r13
decq %r14
jne .LBB2_8
# %bb.9: # %._crit_edge
# in Loop: Header=BB2_7 Depth=2
movq 88(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 72(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 96(%rsp), %rbp # 8-byte Reload
movl 8(%rsp), %r14d # 4-byte Reload
movq 104(%rsp), %r15 # 8-byte Reload
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_7 Depth=2
movq 48(%rsp), %rax
movq 16(%rsp), %rcx
movl 24(%rsp), %edx # 4-byte Reload
movl %edx, 44(%rsp)
movl %r14d, 40(%rsp)
movl %ebx, 36(%rsp)
movl %r15d, 32(%rsp)
movl %ebp, 28(%rsp)
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 36(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rax
movq %rax, 200(%rsp)
leaq 28(%rsp), %rax
movq %rax, 208(%rsp)
leaq 168(%rsp), %rax
movq %rax, 216(%rsp)
leaq 160(%rsp), %rax
movq %rax, 224(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z13possible_moveiiiiiPiS_, %edi
leaq 176(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11: # in Loop: Header=BB2_7 Depth=2
movq 16(%rsp), %rsi
movl $4, %edx
leaq 4(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp)
movq 56(%rsp), %r12 # 8-byte Reload
je .LBB2_12
# %bb.13: # in Loop: Header=BB2_7 Depth=2
cmpl %ebp, %r15d
jne .LBB2_21
# %bb.14: # in Loop: Header=BB2_7 Depth=2
movl %r14d, %eax
orl %ebx, %eax
jne .LBB2_15
jmp .LBB2_28
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_15 Depth=3
leaq (%rax,%r12,4), %rcx
addq $board, %rcx
movl %ebp, %ebx
.LBB2_20: # in Loop: Header=BB2_15 Depth=3
movl (%rcx), %r15d
movl $0, (%rcx)
cmpl %ebp, %r15d
jne .LBB2_21
.LBB2_15: # %.outer
# Parent Loop BB2_5 Depth=1
# Parent Loop BB2_7 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB2_16 Depth 4
movslq %r14d, %rax
movslq %ebx, %rbx
movq %rax, %rdx
shlq $6, %rdx
leaq (%rdx,%rbx,4), %rcx
addq $board, %rcx
.p2align 4, 0x90
.LBB2_16: # Parent Loop BB2_5 Depth=1
# Parent Loop BB2_7 Depth=2
# Parent Loop BB2_15 Depth=3
# => This Inner Loop Header: Depth=4
subq $1, %rbx
jb .LBB2_17
# %bb.19: # in Loop: Header=BB2_16 Depth=4
addq $-4, %rcx
cmpl $1, lock(%rdx,%rbx,4)
je .LBB2_16
jmp .LBB2_20
.p2align 4, 0x90
.LBB2_17: # in Loop: Header=BB2_15 Depth=3
leal -1(%rax), %r14d
decq %rax
shlq $6, %rax
cmpl $1, lock(%rax,%r12,4)
movl %ebp, %ebx
je .LBB2_15
jmp .LBB2_18
.LBB2_12: # in Loop: Header=BB2_5 Depth=1
movslq %r14d, %rax
movslq %ebx, %rcx
shlq $6, %rax
movl %r15d, board(%rax,%rcx,4)
jmp .LBB2_22
.LBB2_28: # %.loopexit80
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5solvei, .Lfunc_end2-_Z5solvei
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
cvtsi2sdl 12(%rsp), %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB3_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB3_3
.LBB3_2: # %call.sqrt
callq sqrt
.LBB3_3: # %.split
cvtsd2ss %xmm0, %xmm0
cvttss2si %xmm0, %eax
imull %eax, %eax
cmpl %eax, 12(%rsp)
jne .LBB3_4
.LBB3_9: # %._crit_edge
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, 16(%rsp)
jle .LBB3_19
# %bb.10: # %.lr.ph29.preheader
leaq 28(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 20(%rsp), %r15
xorl %ebp, %ebp
jmp .LBB3_11
.p2align 4, 0x90
.LBB3_18: # in Loop: Header=BB3_11 Depth=1
incl %ebp
cmpl 16(%rsp), %ebp
jge .LBB3_19
.LBB3_11: # %.lr.ph29
# =>This Inner Loop Header: Depth=1
movl $.L.str.7, %edi
movq %rbx, %rsi
movq %r14, %rdx
movq %r15, %rcx
xorl %eax, %eax
callq __isoc23_scanf
movslq 28(%rsp), %rax
movl 12(%rsp), %esi
cmpl %esi, %eax
jg .LBB3_18
# %bb.12: # in Loop: Header=BB3_11 Depth=1
movslq 24(%rsp), %rcx
cmpl %esi, %ecx
jg .LBB3_18
# %bb.13: # in Loop: Header=BB3_11 Depth=1
movl 20(%rsp), %edx
testl %edx, %edx
jle .LBB3_18
# %bb.14: # in Loop: Header=BB3_11 Depth=1
testl %ecx, %ecx
jle .LBB3_18
# %bb.15: # in Loop: Header=BB3_11 Depth=1
testl %eax, %eax
jle .LBB3_18
# %bb.16: # in Loop: Header=BB3_11 Depth=1
cmpl %esi, %edx
jg .LBB3_18
# %bb.17: # in Loop: Header=BB3_11 Depth=1
decq %rax
movl %eax, %esi
leaq -1(%rcx), %rdi
movl %edi, %edi
shlq $6, %rsi
movl %edx, board(%rsi,%rdi,4)
shlq $6, %rax
movl $1, lock-4(%rax,%rcx,4)
jmp .LBB3_18
.LBB3_19: # %._crit_edge30
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %ebx
testl %ebx, %ebx
jle .LBB3_24
# %bb.20: # %.preheader.lr.ph.i
movl $board, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_21: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_22 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_22: # Parent Loop BB3_21 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %rbx
jne .LBB3_22
# %bb.23: # %._crit_edge.i
# in Loop: Header=BB3_21 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq %rbx, %r15
jne .LBB3_21
.LBB3_24: # %_Z11print_boardi.exit
movl 12(%rsp), %edi
callq _Z5solvei
movl $.Lstr.1, %edi
callq puts@PLT
movl 12(%rsp), %ebx
testl %ebx, %ebx
jle .LBB3_29
# %bb.25: # %.preheader.lr.ph.i14
movl $board, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_26: # %.preheader.i16
# =>This Loop Header: Depth=1
# Child Loop BB3_27 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_27: # Parent Loop BB3_26 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %rbx
jne .LBB3_27
# %bb.28: # %._crit_edge.i22
# in Loop: Header=BB3_26 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq %rbx, %r15
jne .LBB3_26
.LBB3_29: # %_Z11print_boardi.exit26
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_4: # %.lr.ph.preheader
.cfi_def_cfa_offset 80
leaq 12(%rsp), %rbx
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_7: # %call.sqrt35
# in Loop: Header=BB3_5 Depth=1
callq sqrt
.LBB3_8: # %.lr.ph.split
# in Loop: Header=BB3_5 Depth=1
cvtsd2ss %xmm0, %xmm0
cvttss2si %xmm0, %eax
imull %eax, %eax
cmpl %eax, 12(%rsp)
je .LBB3_9
.LBB3_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
xorps %xmm0, %xmm0
cvtsi2sdl 12(%rsp), %xmm0
ucomisd .LCPI3_0(%rip), %xmm0
jb .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB3_8
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13possible_moveiiiiiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type board,@object # @board
.bss
.globl board
.p2align 4, 0x0
board:
.zero 1024
.size board, 1024
.type lock,@object # @lock
.globl lock
.p2align 4, 0x0
lock:
.zero 1024
.size lock, 1024
.type _Z13possible_moveiiiiiPiS_,@object # @_Z13possible_moveiiiiiPiS_
.section .rodata,"a",@progbits
.globl _Z13possible_moveiiiiiPiS_
.p2align 3, 0x0
_Z13possible_moveiiiiiPiS_:
.quad _Z28__device_stub__possible_moveiiiiiPiS_
.size _Z13possible_moveiiiiiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nNextmove %d %d\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter Board Size:"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Enter correct Boards size:"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Enter no. of Predefined numbers:"
.size .L.str.6, 33
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d%d%d"
.size .L.str.7, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13possible_moveiiiiiPiS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nInitial Board"
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nFinal Board"
.size .Lstr.1, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__possible_moveiiiiiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym board
.addrsig_sym _Z13possible_moveiiiiiPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13possible_moveiiiiiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD R5, R3, c[0x0][0x164], R2 ; /* 0x0000590003057a24 */
/* 0x001fc800078e0202 */
/*0060*/ IMAD.WIDE R4, R5, R0, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fcc00078e0200 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x4b0 ; /* 0x0000042000007945 */
/* 0x000fe20003800000 */
/*0090*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x004fda0003f05270 */
/*00a0*/ @!P0 BRA 0x4a0 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R5, R2, R3, c[0x0][0x168] ; /* 0x00005a0002057624 */
/* 0x000fc800078e0203 */
/*00c0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fcc00078e0200 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 BRA 0x4a0 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*0100*/ IABS R8, c[0x0][0x160] ; /* 0x0000580000087a13 */
/* 0x000fe40000000000 */
/*0110*/ IABS R9, R2 ; /* 0x0000000200097213 */
/* 0x000fe40000000000 */
/*0120*/ I2F.RP R3, R8 ; /* 0x0000000800037306 */
/* 0x000e220000209400 */
/*0130*/ IABS R6, c[0x0][0x164] ; /* 0x0000590000067a13 */
/* 0x000fe40000000000 */
/*0140*/ IABS R10, c[0x0][0x168] ; /* 0x00005a00000a7a13 */
/* 0x000fe40000000000 */
/*0150*/ ISETP.LE.AND P3, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fc60003f63270 */
/*0160*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0170*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*0180*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*01a0*/ IADD3 R7, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x002fca0007ffe0ff */
/*01b0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*01c0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fc800078e0004 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0009 */
/*01e0*/ IMAD.HI.U32 R3, R5, R6, RZ ; /* 0x0000000605037227 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.HI.U32 R4, R5, R7, RZ ; /* 0x0000000705047227 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fc60007ffe1ff */
/*0210*/ IMAD.HI.U32 R5, R5, R10, RZ ; /* 0x0000000a05057227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.MOV R9, RZ, RZ, -R4 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a04 */
/*0230*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a05 */
/*0240*/ IMAD R5, R8.reuse, R9, R7 ; /* 0x0000000908057224 */
/* 0x040fe400078e0207 */
/*0250*/ IMAD R3, R8.reuse, R3, R6 ; /* 0x0000000308037224 */
/* 0x040fe400078e0206 */
/*0260*/ IMAD R6, R8.reuse, R11, R10 ; /* 0x0000000b08067224 */
/* 0x040fe200078e020a */
/*0270*/ ISETP.GT.U32.AND P5, PT, R8.reuse, R5, PT ; /* 0x000000050800720c */
/* 0x040fe40003fa4070 */
/*0280*/ ISETP.GT.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fc40003f04070 */
/*0290*/ ISETP.GT.U32.AND P1, PT, R8, R6, PT ; /* 0x000000060800720c */
/* 0x000fd20003f24070 */
/*02a0*/ @!P5 IMAD.IADD R5, R5, 0x1, -R8.reuse ; /* 0x000000010505d824 */
/* 0x100fe200078e0a08 */
/*02b0*/ @!P5 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404d810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ @!P0 IADD3 R3, R3, -R8.reuse, RZ ; /* 0x8000000803038210 */
/* 0x080fe20007ffe0ff */
/*02d0*/ @!P1 IMAD.IADD R6, R6, 0x1, -R8 ; /* 0x0000000106069824 */
/* 0x000fe200078e0a08 */
/*02e0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fe40003f26070 */
/*02f0*/ LOP3.LUT R5, R2, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580002057a12 */
/* 0x000fe400078e3cff */
/*0300*/ ISETP.GT.U32.AND P0, PT, R8.reuse, R3, PT ; /* 0x000000030800720c */
/* 0x040fe40003f04070 */
/*0310*/ ISETP.GT.U32.AND P2, PT, R8, R6, PT ; /* 0x000000060800720c */
/* 0x000fc40003f44070 */
/*0320*/ ISETP.GE.AND P4, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f86270 */
/*0330*/ ISETP.LE.AND P5, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003fa3270 */
/*0340*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fc80007ffe0ff */
/*0350*/ @!P0 IADD3 R3, R3, -R8, RZ ; /* 0x8000000803038210 */
/* 0x000fe20007ffe0ff */
/*0360*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0004 */
/*0370*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe20003f05270 */
/*0380*/ @!P2 IMAD.IADD R6, R6, 0x1, -R8 ; /* 0x000000010606a824 */
/* 0x000fe200078e0a08 */
/*0390*/ LOP3.LUT R4, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff047a12 */
/* 0x000fe200078e33ff */
/*03a0*/ @!P4 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05c224 */
/* 0x000fe200078e0a05 */
/*03b0*/ @!P3 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff0303b210 */
/* 0x000fe20007ffe1ff */
/*03c0*/ @!P5 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff06d224 */
/* 0x000fc600078e0a06 */
/*03d0*/ SEL R3, R4.reuse, R3, !P0 ; /* 0x0000000304037207 */
/* 0x040fe40004000000 */
/*03e0*/ SEL R8, R4.reuse, R5, !P0 ; /* 0x0000000504087207 */
/* 0x040fe40004000000 */
/*03f0*/ SEL R4, R4, R6, !P0 ; /* 0x0000000604047207 */
/* 0x000fe40004000000 */
/*0400*/ IADD3 R5, R8.reuse, c[0x0][0x164], -R3 ; /* 0x0000590008057a10 */
/* 0x040fe40007ffe803 */
/*0410*/ IADD3 R3, -R8, RZ, RZ ; /* 0x000000ff08037210 */
/* 0x000fe40007ffe1ff */
/*0420*/ IADD3 R4, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc60007ffe1ff */
/*0430*/ IMAD R3, R3, c[0x0][0x160], R2 ; /* 0x0000580003037a24 */
/* 0x000fe400078e0202 */
/*0440*/ IMAD R4, R5, c[0x0][0x170], R4 ; /* 0x00005c0005047a24 */
/* 0x000fc800078e0204 */
/*0450*/ IMAD.IADD R3, R4, 0x1, R3 ; /* 0x0000000104037824 */
/* 0x000fc800078e0203 */
/*0460*/ IMAD.WIDE R2, R3, R0, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fcc00078e0200 */
/*0470*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0480*/ ISETP.NE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x004fda0003f05270 */
/*0490*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*04c0*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x000fe20000000f00 */
/*04d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fca00078e00ff */
/*04e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13possible_moveiiiiiPiS_
.globl _Z13possible_moveiiiiiPiS_
.p2align 8
.type _Z13possible_moveiiiiiPiS_,@function
_Z13possible_moveiiiiiPiS_:
s_clause 0x2
s_load_b32 s9, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b64 s[4:5], s[0:1], 0x18
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s3, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s7, s2, v1
v_cmpx_ne_u32_e64 s2, v1
s_cbranch_execz .LBB0_4
s_load_b32 s6, s[0:1], 0x8
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s3, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s10, s2, v1
v_cmpx_ne_u32_e64 s2, v1
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s14, s12, s13
s_xor_b32 s14, s14, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s14
s_sub_i32 s16, 0, s14
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s16, s16, s15
s_mul_hi_u32 s16, s15, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_add_i32 s15, s15, s16
s_ashr_i32 s16, s9, 31
v_mul_hi_u32 v1, v0, s15
s_add_i32 s17, s9, s16
s_xor_b32 s17, s17, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s18, s17, s15
s_mul_i32 s18, s18, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v1, s14
v_add_nc_u32_e32 v3, 1, v1
s_sub_i32 s17, s17, s18
s_sub_i32 s18, s17, s14
s_cmp_ge_u32 s17, s14
s_cselect_b32 s17, s18, s17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
s_sub_i32 s18, s17, s14
s_cmp_ge_u32 s17, s14
s_cselect_b32 s17, s18, s17
v_subrev_nc_u32_e32 v4, s14, v2
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_ashr_i32 s18, s6, 31
s_xor_b32 s17, s17, s16
s_add_i32 s19, s6, s18
s_sub_i32 s16, s16, s17
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
s_xor_b32 s19, s19, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_hi_u32 s15, s19, s15
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, 1, v1
s_mul_i32 s15, s15, s14
s_sub_i32 s15, s19, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
v_xor_b32_e32 v1, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s13, v1
s_sub_i32 s13, s15, s14
s_cmp_ge_u32 s15, s14
s_cselect_b32 s13, s13, s15
v_add3_u32 v2, s9, s16, v1
v_mul_lo_u32 v1, v1, s12
s_sub_i32 s9, s13, s14
s_cmp_ge_u32 s13, s14
s_cselect_b32 s9, s9, s13
v_mul_lo_u32 v2, v2, s3
s_xor_b32 s3, s9, s18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_sub_nc_u32_e32 v0, v0, v1
s_sub_i32 s3, s18, s3
s_add_i32 s3, s6, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s3, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s2, v0
s_and_not1_b32 s2, s10, exec_lo
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s2, s3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s7, exec_lo
s_and_b32 s3, s10, exec_lo
s_or_b32 s7, s2, s3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x20
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13possible_moveiiiiiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13possible_moveiiiiiPiS_, .Lfunc_end0-_Z13possible_moveiiiiiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13possible_moveiiiiiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z13possible_moveiiiiiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017779c_00000000-6_gpusudokusolver.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z11print_boardi
.type _Z11print_boardi, @function
_Z11print_boardi:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L9
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movslq %edi, %r13
leaq board(%rip), %rdx
leaq (%rdx,%r13,4), %rbp
movq %r13, %rax
salq $4, %rax
addq %r13, %rax
leaq (%rdx,%rax,4), %r14
negq %r13
salq $2, %r13
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r15
.L5:
leaq 0(%rbp,%r13), %rbx
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z11print_boardi, .-_Z11print_boardi
.globl _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_
.type _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_, @function
_Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13possible_moveiiiiiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_, .-_Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_
.globl _Z13possible_moveiiiiiPiS_
.type _Z13possible_moveiiiiiPiS_, @function
_Z13possible_moveiiiiiPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13possible_moveiiiiiPiS_, .-_Z13possible_moveiiiiiPiS_
.section .rodata.str1.1
.LC3:
.string "\nNextmove %d %d\n"
.text
.globl _Z5solvei
.type _Z5solvei, @function
_Z5solvei:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, 16(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L44
sqrtsd %xmm0, %xmm0
.L23:
cvttsd2sil %xmm0, %eax
movl %eax, 28(%rsp)
movl $0, 44(%rsp)
movl 16(%rsp), %ebx
movl %ebx, %esi
imull %ebx, %esi
sall $2, %esi
movslq %esi, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %ebx, %ebx
jle .L20
leal 0(,%rbx,4), %r12d
movslq %r12d, %r12
movslq %ebx, %rax
leaq 0(,%rax,4), %r15
salq $6, %rax
leaq board(%rip), %rdx
leaq (%rax,%rdx), %r14
movl $0, 24(%rsp)
jmp .L25
.L44:
call sqrt@PLT
jmp .L23
.L28:
movl $2, %ecx
movl $4, %edx
movq 56(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, 44(%rsp)
je .L46
cmpl %r13d, 16(%rsp)
je .L47
.L30:
movl $0, 44(%rsp)
addl $1, %r13d
cmpl %r13d, 16(%rsp)
jl .L26
.L36:
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq board(%rip), %rbx
movl $0, %ebp
.L27:
movq %rbp, %rdi
addq 48(%rsp), %rdi
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
call cudaMemcpy@PLT
addq %r15, %rbp
addq $64, %rbx
cmpq %r14, %rbx
jne .L27
movl 16(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L28
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq 64(%rsp)
.cfi_def_cfa_offset 176
movq 64(%rsp), %r9
movl 32(%rsp), %r8d
movl %r13d, %ecx
movl 36(%rsp), %edx
movl 40(%rsp), %esi
movl 44(%rsp), %edi
call _Z40__device_stub__Z13possible_moveiiiiiPiS_iiiiiPiS_
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L46:
movslq 20(%rsp), %rcx
movslq 24(%rsp), %rdx
salq $4, %rdx
addq %rcx, %rdx
leaq board(%rip), %rax
movl %r13d, (%rax,%rdx,4)
.L26:
movl 20(%rsp), %ebx
movl %ebx, %ecx
movl 24(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ebp
movl %ebp, %edi
call _Z11print_boardi
movl %ebx, %eax
addl $1, %eax
movl %eax, 20(%rsp)
cmpl %eax, %ebp
jle .L48
.L37:
movslq 20(%rsp), %rdx
movslq 24(%rsp), %rax
salq $4, %rax
addq %rdx, %rax
leaq board(%rip), %rdx
movl (%rdx,%rax,4), %r13d
testl %r13d, %r13d
jne .L26
leaq 44(%rsp), %rax
movq %rax, 8(%rsp)
jmp .L36
.L47:
movl 24(%rsp), %esi
movl %esi, %edx
movl 20(%rsp), %eax
orl %eax, %edx
je .L20
movslq 16(%rsp), %rdx
jmp .L32
.L39:
movl 16(%rsp), %eax
jmp .L32
.L33:
subl $1, %eax
movslq %eax, %rdi
movslq %esi, %rcx
salq $4, %rcx
addq %rdi, %rcx
leaq lock(%rip), %rbx
cmpl $1, (%rbx,%rcx,4)
je .L32
movslq %esi, %rcx
salq $4, %rcx
addq %rdi, %rcx
leaq board(%rip), %rbx
movl (%rbx,%rcx,4), %r13d
movl $0, (%rbx,%rcx,4)
.L35:
movl 16(%rsp), %ecx
cmpl %ecx, %r13d
jne .L49
.L32:
testl %eax, %eax
jne .L33
subl $1, %esi
movslq %esi, %rax
salq $4, %rax
addq %rdx, %rax
leaq lock(%rip), %rcx
cmpl $1, (%rcx,%rax,4)
je .L39
movslq %esi, %rax
salq $4, %rax
addq %rdx, %rax
leaq board(%rip), %rcx
movl (%rcx,%rax,4), %r13d
movl $0, (%rcx,%rax,4)
movl 16(%rsp), %eax
jmp .L35
.L49:
movl %esi, 24(%rsp)
movl %eax, 20(%rsp)
jmp .L30
.L48:
addl $1, 24(%rsp)
movl 24(%rsp), %eax
cmpl %eax, 16(%rsp)
jle .L20
.L25:
movl $0, 20(%rsp)
jmp .L37
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z5solvei, .-_Z5solvei
.section .rodata.str1.1
.LC4:
.string "Enter Board Size:"
.LC5:
.string "%d"
.LC6:
.string "Enter correct Boards size:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Enter no. of Predefined numbers:"
.section .rodata.str1.1
.LC8:
.string "%d%d%d"
.LC9:
.string "\nInitial Board\n"
.LC10:
.string "\nFinal Board\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC4(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %r13
leaq .LC5(%rip), %r12
movl $0x000000000, %ebp
leaq .LC6(%rip), %r14
.L56:
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 4(%rsp), %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq %rbp, %xmm1
ucomisd %xmm0, %xmm1
ja .L63
sqrtsd %xmm0, %xmm0
.L54:
cvtsd2ss %xmm0, %xmm0
cvttss2sil %xmm0, %eax
imull %eax, %eax
cmpl %eax, %ebx
je .L55
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L56
.L63:
call sqrt@PLT
jmp .L54
.L55:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $0, 8(%rsp)
jle .L57
movl $0, %ebx
leaq .LC8(%rip), %rbp
jmp .L59
.L58:
addl $1, %ebx
cmpl %ebx, 8(%rsp)
jle .L57
.L59:
leaq 20(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %edx
movl 4(%rsp), %eax
cmpl %eax, %edx
jg .L58
movl 16(%rsp), %ecx
cmpl %ecx, %eax
jl .L58
movl 20(%rsp), %edi
testl %edx, %edx
setg %sil
cmpl %edi, %eax
setge %al
andl %esi, %eax
testl %ecx, %ecx
setg %sil
testb %sil, %al
je .L58
testl %edi, %edi
jle .L58
leal -1(%rdx), %eax
subl $1, %ecx
movslq %ecx, %rcx
cltq
salq $4, %rax
addq %rcx, %rax
leaq board(%rip), %rdx
movl %edi, (%rdx,%rax,4)
leaq lock(%rip), %rdx
movl $1, (%rdx,%rax,4)
jmp .L58
.L57:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %edi
call _Z11print_boardi
movl 4(%rsp), %edi
call _Z5solvei
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %edi
call _Z11print_boardi
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z13possible_moveiiiiiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z13possible_moveiiiiiPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl lock
.bss
.align 32
.type lock, @object
.size lock, 1024
lock:
.zero 1024
.globl board
.align 32
.type board, @object
.size board, 1024
board:
.zero 1024
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpusudokusolver.hip"
.globl _Z28__device_stub__possible_moveiiiiiPiS_ # -- Begin function _Z28__device_stub__possible_moveiiiiiPiS_
.p2align 4, 0x90
.type _Z28__device_stub__possible_moveiiiiiPiS_,@function
_Z28__device_stub__possible_moveiiiiiPiS_: # @_Z28__device_stub__possible_moveiiiiiPiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13possible_moveiiiiiPiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__possible_moveiiiiiPiS_, .Lfunc_end0-_Z28__device_stub__possible_moveiiiiiPiS_
.cfi_endproc
# -- End function
.globl _Z11print_boardi # -- Begin function _Z11print_boardi
.p2align 4, 0x90
.type _Z11print_boardi,@function
_Z11print_boardi: # @_Z11print_boardi
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edi, %ebx
movl $board, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %rbx
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq %rbx, %r15
jne .LBB1_2
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_6: # %._crit_edge12
retq
.Lfunc_end1:
.size _Z11print_boardi, .Lfunc_end1-_Z11print_boardi
.cfi_endproc
# -- End function
.globl _Z5solvei # -- Begin function _Z5solvei
.p2align 4, 0x90
.type _Z5solvei,@function
_Z5solvei: # @_Z5solvei
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
cvtsi2sd %edi, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB2_3
.LBB2_2: # %call.sqrt
callq sqrt
.LBB2_3: # %.split
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $0, 4(%rsp)
leal (,%rbp,4), %ebx
movl %ebx, %eax
imull %ebp, %eax
movslq %eax, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %ebp, %ebp
jle .LBB2_28
# %bb.4: # %.preheader81.lr.ph
cvttsd2si 8(%rsp), %eax # 8-byte Folded Reload
movl %eax, 24(%rsp) # 4-byte Spill
movabsq $4294967296, %rax # imm = 0x100000000
movl %ebx, %ecx
movq %rcx, 80(%rsp) # 8-byte Spill
movl %ebp, %r12d
leaq (%r12,%rax), %rcx
movq %rcx, 72(%rsp) # 8-byte Spill
leaq (,%r12,4), %rcx
movq %rcx, 64(%rsp) # 8-byte Spill
incq %rax
movq %rax, 88(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %ebx, %ebx
movq %rbp, 96(%rsp) # 8-byte Spill
movq %r12, 56(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_5: # %.lr.ph101
# =>This Loop Header: Depth=1
# Child Loop BB2_7 Depth 2
# Child Loop BB2_8 Depth 3
# Child Loop BB2_15 Depth 3
# Child Loop BB2_16 Depth 4
# Child Loop BB2_23 Depth 2
# Child Loop BB2_24 Depth 3
movslq %r14d, %rax
movslq %ebx, %rcx
shlq $6, %rax
cmpl $0, board(%rax,%rcx,4)
je .LBB2_6
.LBB2_22: # %.loopexit79
# in Loop: Header=BB2_5 Depth=1
movl $.L.str.2, %edi
movl %r14d, 8(%rsp) # 4-byte Spill
movl %r14d, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl $board, %r15d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_23: # %.preheader.i
# Parent Loop BB2_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_24 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_24: # Parent Loop BB2_5 Depth=1
# Parent Loop BB2_23 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB2_24
# %bb.25: # %._crit_edge.i
# in Loop: Header=BB2_23 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r13
addq $64, %r15
cmpq %r12, %r13
jne .LBB2_23
# %bb.26: # %_Z11print_boardi.exit
# in Loop: Header=BB2_5 Depth=1
incl %ebx
cmpl %ebp, %ebx
movl 8(%rsp), %r14d # 4-byte Reload
jl .LBB2_5
# %bb.27: # %._crit_edge102
# in Loop: Header=BB2_5 Depth=1
incl %r14d
movl $0, %ebx
cmpl %ebp, %r14d
jl .LBB2_5
jmp .LBB2_28
.p2align 4, 0x90
.LBB2_6: # %.lr.ph97.preheader
# in Loop: Header=BB2_5 Depth=1
xorl %eax, %eax
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_21: # %.loopexit
# in Loop: Header=BB2_7 Depth=2
movl $0, 4(%rsp)
leal 1(%r15), %eax
cmpl %ebp, %r15d
# kill: def $eax killed $eax def $rax
jge .LBB2_22
.LBB2_7: # %.lr.ph97
# Parent Loop BB2_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_8 Depth 3
# Child Loop BB2_15 Depth 3
# Child Loop BB2_16 Depth 4
movq %rax, 104(%rsp) # 8-byte Spill
movl %r14d, 8(%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
movl $4, %edx
leaq 4(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl $board, %r13d
movq %r12, %r14
xorl %ebp, %ebp
movq 80(%rsp), %r15 # 8-byte Reload
movq 64(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_5 Depth=1
# Parent Loop BB2_7 Depth=2
# => This Inner Loop Header: Depth=3
movq 48(%rsp), %rdi
addq %rbp, %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
addq %r12, %rbp
addq $64, %r13
decq %r14
jne .LBB2_8
# %bb.9: # %._crit_edge
# in Loop: Header=BB2_7 Depth=2
movq 88(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 72(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 96(%rsp), %rbp # 8-byte Reload
movl 8(%rsp), %r14d # 4-byte Reload
movq 104(%rsp), %r15 # 8-byte Reload
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_7 Depth=2
movq 48(%rsp), %rax
movq 16(%rsp), %rcx
movl 24(%rsp), %edx # 4-byte Reload
movl %edx, 44(%rsp)
movl %r14d, 40(%rsp)
movl %ebx, 36(%rsp)
movl %r15d, 32(%rsp)
movl %ebp, 28(%rsp)
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 36(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rax
movq %rax, 200(%rsp)
leaq 28(%rsp), %rax
movq %rax, 208(%rsp)
leaq 168(%rsp), %rax
movq %rax, 216(%rsp)
leaq 160(%rsp), %rax
movq %rax, 224(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z13possible_moveiiiiiPiS_, %edi
leaq 176(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11: # in Loop: Header=BB2_7 Depth=2
movq 16(%rsp), %rsi
movl $4, %edx
leaq 4(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp)
movq 56(%rsp), %r12 # 8-byte Reload
je .LBB2_12
# %bb.13: # in Loop: Header=BB2_7 Depth=2
cmpl %ebp, %r15d
jne .LBB2_21
# %bb.14: # in Loop: Header=BB2_7 Depth=2
movl %r14d, %eax
orl %ebx, %eax
jne .LBB2_15
jmp .LBB2_28
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_15 Depth=3
leaq (%rax,%r12,4), %rcx
addq $board, %rcx
movl %ebp, %ebx
.LBB2_20: # in Loop: Header=BB2_15 Depth=3
movl (%rcx), %r15d
movl $0, (%rcx)
cmpl %ebp, %r15d
jne .LBB2_21
.LBB2_15: # %.outer
# Parent Loop BB2_5 Depth=1
# Parent Loop BB2_7 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB2_16 Depth 4
movslq %r14d, %rax
movslq %ebx, %rbx
movq %rax, %rdx
shlq $6, %rdx
leaq (%rdx,%rbx,4), %rcx
addq $board, %rcx
.p2align 4, 0x90
.LBB2_16: # Parent Loop BB2_5 Depth=1
# Parent Loop BB2_7 Depth=2
# Parent Loop BB2_15 Depth=3
# => This Inner Loop Header: Depth=4
subq $1, %rbx
jb .LBB2_17
# %bb.19: # in Loop: Header=BB2_16 Depth=4
addq $-4, %rcx
cmpl $1, lock(%rdx,%rbx,4)
je .LBB2_16
jmp .LBB2_20
.p2align 4, 0x90
.LBB2_17: # in Loop: Header=BB2_15 Depth=3
leal -1(%rax), %r14d
decq %rax
shlq $6, %rax
cmpl $1, lock(%rax,%r12,4)
movl %ebp, %ebx
je .LBB2_15
jmp .LBB2_18
.LBB2_12: # in Loop: Header=BB2_5 Depth=1
movslq %r14d, %rax
movslq %ebx, %rcx
shlq $6, %rax
movl %r15d, board(%rax,%rcx,4)
jmp .LBB2_22
.LBB2_28: # %.loopexit80
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5solvei, .Lfunc_end2-_Z5solvei
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
cvtsi2sdl 12(%rsp), %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB3_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB3_3
.LBB3_2: # %call.sqrt
callq sqrt
.LBB3_3: # %.split
cvtsd2ss %xmm0, %xmm0
cvttss2si %xmm0, %eax
imull %eax, %eax
cmpl %eax, 12(%rsp)
jne .LBB3_4
.LBB3_9: # %._crit_edge
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, 16(%rsp)
jle .LBB3_19
# %bb.10: # %.lr.ph29.preheader
leaq 28(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 20(%rsp), %r15
xorl %ebp, %ebp
jmp .LBB3_11
.p2align 4, 0x90
.LBB3_18: # in Loop: Header=BB3_11 Depth=1
incl %ebp
cmpl 16(%rsp), %ebp
jge .LBB3_19
.LBB3_11: # %.lr.ph29
# =>This Inner Loop Header: Depth=1
movl $.L.str.7, %edi
movq %rbx, %rsi
movq %r14, %rdx
movq %r15, %rcx
xorl %eax, %eax
callq __isoc23_scanf
movslq 28(%rsp), %rax
movl 12(%rsp), %esi
cmpl %esi, %eax
jg .LBB3_18
# %bb.12: # in Loop: Header=BB3_11 Depth=1
movslq 24(%rsp), %rcx
cmpl %esi, %ecx
jg .LBB3_18
# %bb.13: # in Loop: Header=BB3_11 Depth=1
movl 20(%rsp), %edx
testl %edx, %edx
jle .LBB3_18
# %bb.14: # in Loop: Header=BB3_11 Depth=1
testl %ecx, %ecx
jle .LBB3_18
# %bb.15: # in Loop: Header=BB3_11 Depth=1
testl %eax, %eax
jle .LBB3_18
# %bb.16: # in Loop: Header=BB3_11 Depth=1
cmpl %esi, %edx
jg .LBB3_18
# %bb.17: # in Loop: Header=BB3_11 Depth=1
decq %rax
movl %eax, %esi
leaq -1(%rcx), %rdi
movl %edi, %edi
shlq $6, %rsi
movl %edx, board(%rsi,%rdi,4)
shlq $6, %rax
movl $1, lock-4(%rax,%rcx,4)
jmp .LBB3_18
.LBB3_19: # %._crit_edge30
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %ebx
testl %ebx, %ebx
jle .LBB3_24
# %bb.20: # %.preheader.lr.ph.i
movl $board, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_21: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_22 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_22: # Parent Loop BB3_21 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %rbx
jne .LBB3_22
# %bb.23: # %._crit_edge.i
# in Loop: Header=BB3_21 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq %rbx, %r15
jne .LBB3_21
.LBB3_24: # %_Z11print_boardi.exit
movl 12(%rsp), %edi
callq _Z5solvei
movl $.Lstr.1, %edi
callq puts@PLT
movl 12(%rsp), %ebx
testl %ebx, %ebx
jle .LBB3_29
# %bb.25: # %.preheader.lr.ph.i14
movl $board, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_26: # %.preheader.i16
# =>This Loop Header: Depth=1
# Child Loop BB3_27 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_27: # Parent Loop BB3_26 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %rbx
jne .LBB3_27
# %bb.28: # %._crit_edge.i22
# in Loop: Header=BB3_26 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq %rbx, %r15
jne .LBB3_26
.LBB3_29: # %_Z11print_boardi.exit26
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_4: # %.lr.ph.preheader
.cfi_def_cfa_offset 80
leaq 12(%rsp), %rbx
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_7: # %call.sqrt35
# in Loop: Header=BB3_5 Depth=1
callq sqrt
.LBB3_8: # %.lr.ph.split
# in Loop: Header=BB3_5 Depth=1
cvtsd2ss %xmm0, %xmm0
cvttss2si %xmm0, %eax
imull %eax, %eax
cmpl %eax, 12(%rsp)
je .LBB3_9
.LBB3_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
xorps %xmm0, %xmm0
cvtsi2sdl 12(%rsp), %xmm0
ucomisd .LCPI3_0(%rip), %xmm0
jb .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB3_8
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13possible_moveiiiiiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type board,@object # @board
.bss
.globl board
.p2align 4, 0x0
board:
.zero 1024
.size board, 1024
.type lock,@object # @lock
.globl lock
.p2align 4, 0x0
lock:
.zero 1024
.size lock, 1024
.type _Z13possible_moveiiiiiPiS_,@object # @_Z13possible_moveiiiiiPiS_
.section .rodata,"a",@progbits
.globl _Z13possible_moveiiiiiPiS_
.p2align 3, 0x0
_Z13possible_moveiiiiiPiS_:
.quad _Z28__device_stub__possible_moveiiiiiPiS_
.size _Z13possible_moveiiiiiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nNextmove %d %d\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter Board Size:"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Enter correct Boards size:"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Enter no. of Predefined numbers:"
.size .L.str.6, 33
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d%d%d"
.size .L.str.7, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13possible_moveiiiiiPiS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nInitial Board"
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nFinal Board"
.size .Lstr.1, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__possible_moveiiiiiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym board
.addrsig_sym _Z13possible_moveiiiiiPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define VERTICES 600
__constant__ float2 d_Vertices[VERTICES];
//tuning parameters
//block_size_x any sensible thread block size
//tile_size any sensible tile size value
//prefetch 0 or 1 for reusing constant memory from previous iteration
//#ifndef prefetch
//#define prefetch 0
//#endif
#ifndef use_bitmap
#define use_bitmap 0
#define coalesce_bitmap 0
#endif
#ifndef block_size_x
#define block_size_x 256
#endif
#ifndef tile_size
#define tile_size 1
#endif
__global__ void cn_PnPoly(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * block_size_x * tile_size + threadIdx.x;
if (ti < n) {
// the crossing number counter
int cn[tile_size];
float2 p[tile_size];
#pragma unroll
for (int k=0; k<tile_size; k++) {
cn[k] = 0;
p[k] = points[ti+k*block_size_x];
}
int k = VERTICES-1;
// #if prefetch == 1
// float2 vj; // = d_Vertices[k];
// float2 vk;
// #endif
// loop through all edges of the polygon
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
// #if prefetch == 1
// float2 vj = d_Vertices[j];
// float2 vk = d_Vertices[k];
// #else
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
// #endif
#if method == 1
float vb = (vj.x - vk.x) / (vj.y - vk.y);
#endif
#pragma unroll
for (int i=0; i<tile_size; i++) {
#if method == 0
if ( ((vj.y>p[i].y) != (vk.y>p[i].y)) &&
(p[i].x < (vk.x-vj.x) * (p[i].y-vj.y) / (vk.y-vj.y) + vj.x) ) {
cn[i] = !cn[i];
}
#elif method == 1
int b = ((vk.y <= p[k].y) && (vj.y > p[k].y)) || ((vk.y > p[k].y) && (vj.y <= p[k].y));
cn[k] += b && (p[k].x < vk.x + vb * (p[k].y - vj.y));
#endif
}
}
#if use_bitmap == 1
int lane_index = threadIdx.x & (32 - 1);
unsigned int bitstring[tile_size];
#if coalesce_bitmap == 1
__shared__ unsigned int block_output[tile_size*block_size_x/32];
int warp_id = threadIdx.x/32;
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
//write at my position in bitstring
bitstring[k] = (cn[k] & 1) << (32-lane_index);
//compute sum of bitstring within warp
#pragma unroll
for (unsigned int s=16; s>0; s>>=1) {
bitstring[k] += __shfl_xor(bitstring[k], s);
}
#if coalesce_bitmap == 1
//store bitstring for this warp in shared buffer
if (lane_index == 0) {
block_output[warp_id+k*block_size_x/32] = bitstring[k];
}
#endif
}
__syncthreads();
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
#if use_bitmap == 0
bitmap[ti+k*block_size_x] = (cn[k] & 1); // 0 if even (out), and 1 if odd (in)
#elif use_bitmap == 1
#if coalesce_bitmap == 0
if (lane_index == 0) {
bitmap[ti/32+k*block_size_x/32] = bitstring[k];
}
#elif coalesce_bitmap == 1
//write back results in coalesced manner
if (threadIdx.x < block_size_x/32) {
bitmap[ti/32+k*block_size_x/32] = block_output[warp_id];
}
#endif
#elif use_bitmap == 2
if (cn[k] & 1 == 1) {
bitmap[ti+k*block_size_x] = 1; // 0 if even (out), and 1 if odd (in)
}
#endif
}
}
}
__global__ void cn_PnPoly_naive(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * blockDim.x + threadIdx.x;
// int ti = blockIdx.y * gridDim.x * blockDim.x + blockIdx.x * blockDim.x + threadIdx.x;
if (ti < n) {
// the crossing number counter
int c = 0;
float2 p = points[ti];
int k = VERTICES-1;
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[ti] = c; // 0 if even (out), and 1 if odd (in)
}
}
/*CPU version*/
float pnpoly_cn(int *bitmap, float2 *v, float2 *p) {
int nvert = VERTICES;
int npoint = 20000;
int i = 0;
for (i = 0; i < npoint; i++) {
int j, k, c = 0;
for (j = 0, k = nvert-1; j < nvert; k = j++) {
if ( ((v[j].y>p[i].y) != (v[k].y>p[i].y)) &&
(p[i].x < (v[k].x-v[j].x) * (p[i].y-v[j].y) / (v[k].y-v[j].y) + v[j].x) )
c = !c;
}
bitmap[i] = c & 1;
}
return 0.0;
}
/*GPU version*/
__global__ void pnpoly_cn_gpu(int *bitmap, float2 *points, int n) {
int i = blockIdx.x * block_size_x + threadIdx.x;
if (i < n) {
float2 p = points[i];
int c = 0;
int k = VERTICES-1;
int j = 0;
for (j = 0; j < VERTICES; k = j++) {
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[i] = c;
}
} | .file "tmpxft_0010f375_00000000-6_pnpoly.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9pnpoly_cnPiP6float2S1_
.type _Z9pnpoly_cnPiP6float2S1_, @function
_Z9pnpoly_cnPiP6float2S1_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rsi, %rcx
movq %rdx, %r9
movq %rdi, %r10
leaq 160000(%rdx), %rbp
movl $0, %ebx
movl $599, %r11d
jmp .L4
.L5:
addq $1, %rax
cmpq $600, %rax
je .L12
.L7:
movl %esi, %edx
movl %eax, %esi
movss 4(%rcx,%rax,8), %xmm3
movslq %edx, %rdx
leaq (%rcx,%rdx,8), %rdx
movss 4(%rdx), %xmm2
comiss %xmm4, %xmm3
seta %r13b
comiss %xmm4, %xmm2
seta %r12b
cmpb %r12b, %r13b
je .L5
movss (%rcx,%rax,8), %xmm5
movss (%rdx), %xmm1
subss %xmm5, %xmm1
movaps %xmm4, %xmm0
subss %xmm3, %xmm0
mulss %xmm1, %xmm0
subss %xmm3, %xmm2
divss %xmm2, %xmm0
addss %xmm5, %xmm0
comiss (%r8), %xmm0
jbe .L5
xorl $1, %edi
jmp .L5
.L12:
movl %edi, (%r10)
addq $8, %r9
addq $4, %r10
cmpq %rbp, %r9
je .L8
.L4:
movq %r9, %r8
movss 4(%r9), %xmm4
movl $0, %eax
movl %ebx, %edi
movl %r11d, %esi
jmp .L7
.L8:
pxor %xmm0, %xmm0
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size _Z9pnpoly_cnPiP6float2S1_, .-_Z9pnpoly_cnPiP6float2S1_
.globl _Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i
.type _Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i, @function
_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9cn_PnPolyPiP6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i, .-_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i
.globl _Z9cn_PnPolyPiP6float2i
.type _Z9cn_PnPolyPiP6float2i, @function
_Z9cn_PnPolyPiP6float2i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z9cn_PnPolyPiP6float2i, .-_Z9cn_PnPolyPiP6float2i
.globl _Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i
.type _Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i, @function
_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i:
.LFB2054:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15cn_PnPoly_naivePiP6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i, .-_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i
.globl _Z15cn_PnPoly_naivePiP6float2i
.type _Z15cn_PnPoly_naivePiP6float2i, @function
_Z15cn_PnPoly_naivePiP6float2i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z15cn_PnPoly_naivePiP6float2i, .-_Z15cn_PnPoly_naivePiP6float2i
.globl _Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i
.type _Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i, @function
_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i:
.LFB2056:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13pnpoly_cn_gpuPiP6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i, .-_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i
.globl _Z13pnpoly_cn_gpuPiP6float2i
.type _Z13pnpoly_cn_gpuPiP6float2i, @function
_Z13pnpoly_cn_gpuPiP6float2i:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13pnpoly_cn_gpuPiP6float2i, .-_Z13pnpoly_cn_gpuPiP6float2i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13pnpoly_cn_gpuPiP6float2i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z15cn_PnPoly_naivePiP6float2i"
.section .rodata.str1.1
.LC3:
.string "_Z9cn_PnPolyPiP6float2i"
.LC4:
.string "d_Vertices"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13pnpoly_cn_gpuPiP6float2i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cn_PnPoly_naivePiP6float2i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cn_PnPolyPiP6float2i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4800, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10d_Vertices(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10d_Vertices
.comm _ZL10d_Vertices,4800,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define VERTICES 600
__constant__ float2 d_Vertices[VERTICES];
//tuning parameters
//block_size_x any sensible thread block size
//tile_size any sensible tile size value
//prefetch 0 or 1 for reusing constant memory from previous iteration
//#ifndef prefetch
//#define prefetch 0
//#endif
#ifndef use_bitmap
#define use_bitmap 0
#define coalesce_bitmap 0
#endif
#ifndef block_size_x
#define block_size_x 256
#endif
#ifndef tile_size
#define tile_size 1
#endif
__global__ void cn_PnPoly(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * block_size_x * tile_size + threadIdx.x;
if (ti < n) {
// the crossing number counter
int cn[tile_size];
float2 p[tile_size];
#pragma unroll
for (int k=0; k<tile_size; k++) {
cn[k] = 0;
p[k] = points[ti+k*block_size_x];
}
int k = VERTICES-1;
// #if prefetch == 1
// float2 vj; // = d_Vertices[k];
// float2 vk;
// #endif
// loop through all edges of the polygon
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
// #if prefetch == 1
// float2 vj = d_Vertices[j];
// float2 vk = d_Vertices[k];
// #else
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
// #endif
#if method == 1
float vb = (vj.x - vk.x) / (vj.y - vk.y);
#endif
#pragma unroll
for (int i=0; i<tile_size; i++) {
#if method == 0
if ( ((vj.y>p[i].y) != (vk.y>p[i].y)) &&
(p[i].x < (vk.x-vj.x) * (p[i].y-vj.y) / (vk.y-vj.y) + vj.x) ) {
cn[i] = !cn[i];
}
#elif method == 1
int b = ((vk.y <= p[k].y) && (vj.y > p[k].y)) || ((vk.y > p[k].y) && (vj.y <= p[k].y));
cn[k] += b && (p[k].x < vk.x + vb * (p[k].y - vj.y));
#endif
}
}
#if use_bitmap == 1
int lane_index = threadIdx.x & (32 - 1);
unsigned int bitstring[tile_size];
#if coalesce_bitmap == 1
__shared__ unsigned int block_output[tile_size*block_size_x/32];
int warp_id = threadIdx.x/32;
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
//write at my position in bitstring
bitstring[k] = (cn[k] & 1) << (32-lane_index);
//compute sum of bitstring within warp
#pragma unroll
for (unsigned int s=16; s>0; s>>=1) {
bitstring[k] += __shfl_xor(bitstring[k], s);
}
#if coalesce_bitmap == 1
//store bitstring for this warp in shared buffer
if (lane_index == 0) {
block_output[warp_id+k*block_size_x/32] = bitstring[k];
}
#endif
}
__syncthreads();
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
#if use_bitmap == 0
bitmap[ti+k*block_size_x] = (cn[k] & 1); // 0 if even (out), and 1 if odd (in)
#elif use_bitmap == 1
#if coalesce_bitmap == 0
if (lane_index == 0) {
bitmap[ti/32+k*block_size_x/32] = bitstring[k];
}
#elif coalesce_bitmap == 1
//write back results in coalesced manner
if (threadIdx.x < block_size_x/32) {
bitmap[ti/32+k*block_size_x/32] = block_output[warp_id];
}
#endif
#elif use_bitmap == 2
if (cn[k] & 1 == 1) {
bitmap[ti+k*block_size_x] = 1; // 0 if even (out), and 1 if odd (in)
}
#endif
}
}
}
__global__ void cn_PnPoly_naive(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * blockDim.x + threadIdx.x;
// int ti = blockIdx.y * gridDim.x * blockDim.x + blockIdx.x * blockDim.x + threadIdx.x;
if (ti < n) {
// the crossing number counter
int c = 0;
float2 p = points[ti];
int k = VERTICES-1;
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[ti] = c; // 0 if even (out), and 1 if odd (in)
}
}
/*CPU version*/
float pnpoly_cn(int *bitmap, float2 *v, float2 *p) {
int nvert = VERTICES;
int npoint = 20000;
int i = 0;
for (i = 0; i < npoint; i++) {
int j, k, c = 0;
for (j = 0, k = nvert-1; j < nvert; k = j++) {
if ( ((v[j].y>p[i].y) != (v[k].y>p[i].y)) &&
(p[i].x < (v[k].x-v[j].x) * (p[i].y-v[j].y) / (v[k].y-v[j].y) + v[j].x) )
c = !c;
}
bitmap[i] = c & 1;
}
return 0.0;
}
/*GPU version*/
__global__ void pnpoly_cn_gpu(int *bitmap, float2 *points, int n) {
int i = blockIdx.x * block_size_x + threadIdx.x;
if (i < n) {
float2 p = points[i];
int c = 0;
int k = VERTICES-1;
int j = 0;
for (j = 0; j < VERTICES; k = j++) {
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[i] = c;
}
} | #include <hip/hip_runtime.h>
#define VERTICES 600
__constant__ float2 d_Vertices[VERTICES];
//tuning parameters
//block_size_x any sensible thread block size
//tile_size any sensible tile size value
//prefetch 0 or 1 for reusing constant memory from previous iteration
//#ifndef prefetch
//#define prefetch 0
//#endif
#ifndef use_bitmap
#define use_bitmap 0
#define coalesce_bitmap 0
#endif
#ifndef block_size_x
#define block_size_x 256
#endif
#ifndef tile_size
#define tile_size 1
#endif
__global__ void cn_PnPoly(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * block_size_x * tile_size + threadIdx.x;
if (ti < n) {
// the crossing number counter
int cn[tile_size];
float2 p[tile_size];
#pragma unroll
for (int k=0; k<tile_size; k++) {
cn[k] = 0;
p[k] = points[ti+k*block_size_x];
}
int k = VERTICES-1;
// #if prefetch == 1
// float2 vj; // = d_Vertices[k];
// float2 vk;
// #endif
// loop through all edges of the polygon
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
// #if prefetch == 1
// float2 vj = d_Vertices[j];
// float2 vk = d_Vertices[k];
// #else
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
// #endif
#if method == 1
float vb = (vj.x - vk.x) / (vj.y - vk.y);
#endif
#pragma unroll
for (int i=0; i<tile_size; i++) {
#if method == 0
if ( ((vj.y>p[i].y) != (vk.y>p[i].y)) &&
(p[i].x < (vk.x-vj.x) * (p[i].y-vj.y) / (vk.y-vj.y) + vj.x) ) {
cn[i] = !cn[i];
}
#elif method == 1
int b = ((vk.y <= p[k].y) && (vj.y > p[k].y)) || ((vk.y > p[k].y) && (vj.y <= p[k].y));
cn[k] += b && (p[k].x < vk.x + vb * (p[k].y - vj.y));
#endif
}
}
#if use_bitmap == 1
int lane_index = threadIdx.x & (32 - 1);
unsigned int bitstring[tile_size];
#if coalesce_bitmap == 1
__shared__ unsigned int block_output[tile_size*block_size_x/32];
int warp_id = threadIdx.x/32;
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
//write at my position in bitstring
bitstring[k] = (cn[k] & 1) << (32-lane_index);
//compute sum of bitstring within warp
#pragma unroll
for (unsigned int s=16; s>0; s>>=1) {
bitstring[k] += __shfl_xor(bitstring[k], s);
}
#if coalesce_bitmap == 1
//store bitstring for this warp in shared buffer
if (lane_index == 0) {
block_output[warp_id+k*block_size_x/32] = bitstring[k];
}
#endif
}
__syncthreads();
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
#if use_bitmap == 0
bitmap[ti+k*block_size_x] = (cn[k] & 1); // 0 if even (out), and 1 if odd (in)
#elif use_bitmap == 1
#if coalesce_bitmap == 0
if (lane_index == 0) {
bitmap[ti/32+k*block_size_x/32] = bitstring[k];
}
#elif coalesce_bitmap == 1
//write back results in coalesced manner
if (threadIdx.x < block_size_x/32) {
bitmap[ti/32+k*block_size_x/32] = block_output[warp_id];
}
#endif
#elif use_bitmap == 2
if (cn[k] & 1 == 1) {
bitmap[ti+k*block_size_x] = 1; // 0 if even (out), and 1 if odd (in)
}
#endif
}
}
}
__global__ void cn_PnPoly_naive(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * blockDim.x + threadIdx.x;
// int ti = blockIdx.y * gridDim.x * blockDim.x + blockIdx.x * blockDim.x + threadIdx.x;
if (ti < n) {
// the crossing number counter
int c = 0;
float2 p = points[ti];
int k = VERTICES-1;
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[ti] = c; // 0 if even (out), and 1 if odd (in)
}
}
/*CPU version*/
float pnpoly_cn(int *bitmap, float2 *v, float2 *p) {
int nvert = VERTICES;
int npoint = 20000;
int i = 0;
for (i = 0; i < npoint; i++) {
int j, k, c = 0;
for (j = 0, k = nvert-1; j < nvert; k = j++) {
if ( ((v[j].y>p[i].y) != (v[k].y>p[i].y)) &&
(p[i].x < (v[k].x-v[j].x) * (p[i].y-v[j].y) / (v[k].y-v[j].y) + v[j].x) )
c = !c;
}
bitmap[i] = c & 1;
}
return 0.0;
}
/*GPU version*/
__global__ void pnpoly_cn_gpu(int *bitmap, float2 *points, int n) {
int i = blockIdx.x * block_size_x + threadIdx.x;
if (i < n) {
float2 p = points[i];
int c = 0;
int k = VERTICES-1;
int j = 0;
for (j = 0; j < VERTICES; k = j++) {
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[i] = c;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define VERTICES 600
__constant__ float2 d_Vertices[VERTICES];
//tuning parameters
//block_size_x any sensible thread block size
//tile_size any sensible tile size value
//prefetch 0 or 1 for reusing constant memory from previous iteration
//#ifndef prefetch
//#define prefetch 0
//#endif
#ifndef use_bitmap
#define use_bitmap 0
#define coalesce_bitmap 0
#endif
#ifndef block_size_x
#define block_size_x 256
#endif
#ifndef tile_size
#define tile_size 1
#endif
__global__ void cn_PnPoly(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * block_size_x * tile_size + threadIdx.x;
if (ti < n) {
// the crossing number counter
int cn[tile_size];
float2 p[tile_size];
#pragma unroll
for (int k=0; k<tile_size; k++) {
cn[k] = 0;
p[k] = points[ti+k*block_size_x];
}
int k = VERTICES-1;
// #if prefetch == 1
// float2 vj; // = d_Vertices[k];
// float2 vk;
// #endif
// loop through all edges of the polygon
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
// #if prefetch == 1
// float2 vj = d_Vertices[j];
// float2 vk = d_Vertices[k];
// #else
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
// #endif
#if method == 1
float vb = (vj.x - vk.x) / (vj.y - vk.y);
#endif
#pragma unroll
for (int i=0; i<tile_size; i++) {
#if method == 0
if ( ((vj.y>p[i].y) != (vk.y>p[i].y)) &&
(p[i].x < (vk.x-vj.x) * (p[i].y-vj.y) / (vk.y-vj.y) + vj.x) ) {
cn[i] = !cn[i];
}
#elif method == 1
int b = ((vk.y <= p[k].y) && (vj.y > p[k].y)) || ((vk.y > p[k].y) && (vj.y <= p[k].y));
cn[k] += b && (p[k].x < vk.x + vb * (p[k].y - vj.y));
#endif
}
}
#if use_bitmap == 1
int lane_index = threadIdx.x & (32 - 1);
unsigned int bitstring[tile_size];
#if coalesce_bitmap == 1
__shared__ unsigned int block_output[tile_size*block_size_x/32];
int warp_id = threadIdx.x/32;
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
//write at my position in bitstring
bitstring[k] = (cn[k] & 1) << (32-lane_index);
//compute sum of bitstring within warp
#pragma unroll
for (unsigned int s=16; s>0; s>>=1) {
bitstring[k] += __shfl_xor(bitstring[k], s);
}
#if coalesce_bitmap == 1
//store bitstring for this warp in shared buffer
if (lane_index == 0) {
block_output[warp_id+k*block_size_x/32] = bitstring[k];
}
#endif
}
__syncthreads();
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
#if use_bitmap == 0
bitmap[ti+k*block_size_x] = (cn[k] & 1); // 0 if even (out), and 1 if odd (in)
#elif use_bitmap == 1
#if coalesce_bitmap == 0
if (lane_index == 0) {
bitmap[ti/32+k*block_size_x/32] = bitstring[k];
}
#elif coalesce_bitmap == 1
//write back results in coalesced manner
if (threadIdx.x < block_size_x/32) {
bitmap[ti/32+k*block_size_x/32] = block_output[warp_id];
}
#endif
#elif use_bitmap == 2
if (cn[k] & 1 == 1) {
bitmap[ti+k*block_size_x] = 1; // 0 if even (out), and 1 if odd (in)
}
#endif
}
}
}
__global__ void cn_PnPoly_naive(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * blockDim.x + threadIdx.x;
// int ti = blockIdx.y * gridDim.x * blockDim.x + blockIdx.x * blockDim.x + threadIdx.x;
if (ti < n) {
// the crossing number counter
int c = 0;
float2 p = points[ti];
int k = VERTICES-1;
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[ti] = c; // 0 if even (out), and 1 if odd (in)
}
}
/*CPU version*/
float pnpoly_cn(int *bitmap, float2 *v, float2 *p) {
int nvert = VERTICES;
int npoint = 20000;
int i = 0;
for (i = 0; i < npoint; i++) {
int j, k, c = 0;
for (j = 0, k = nvert-1; j < nvert; k = j++) {
if ( ((v[j].y>p[i].y) != (v[k].y>p[i].y)) &&
(p[i].x < (v[k].x-v[j].x) * (p[i].y-v[j].y) / (v[k].y-v[j].y) + v[j].x) )
c = !c;
}
bitmap[i] = c & 1;
}
return 0.0;
}
/*GPU version*/
__global__ void pnpoly_cn_gpu(int *bitmap, float2 *points, int n) {
int i = blockIdx.x * block_size_x + threadIdx.x;
if (i < n) {
float2 p = points[i];
int c = 0;
int k = VERTICES-1;
int j = 0;
for (j = 0; j < VERTICES; k = j++) {
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[i] = c;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.globl _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.p2align 8
.type _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi,@function
_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi:
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v0, s15, 8, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v4, 0
s_mov_b64 s[4:5], 4
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, d_Vertices@rel32@lo+8
s_addc_u32 s15, s15, d_Vertices@rel32@hi+16
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, 0
s_movk_i32 s2, 0x257
s_mov_b32 s8, s3
global_load_b64 v[2:3], v[2:3], off
.LBB0_2:
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_Vertices@rel32@lo+4
s_addc_u32 s7, s7, d_Vertices@rel32@hi+12
s_add_u32 s10, s4, s6
s_addc_u32 s11, s5, s7
s_lshl_b64 s[12:13], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s12, s6
s_addc_u32 s7, s13, s7
s_add_u32 s12, s12, s14
s_addc_u32 s13, s13, s15
s_clause 0x1
s_load_b32 s9, s[10:11], 0x0
s_load_b32 s10, s[12:13], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, s9, v3
v_cmp_ngt_f32_e64 s2, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, vcc_lo, s2
s_xor_b32 s11, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s11
s_cbranch_execz .LBB0_6
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, d_Vertices@rel32@lo
s_addc_u32 s13, s13, d_Vertices@rel32@hi+8
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_clause 0x1
s_load_b32 s6, s[6:7], 0x0
s_load_b32 s7, s[12:13], 0x0
v_subrev_f32_e32 v5, s9, v3
v_sub_f32_e64 v7, s10, s9
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v6, s6, s7
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v5, v6
v_div_scale_f32 v6, null, v7, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v6, v8, 1.0
v_fmac_f32_e32 v8, v9, v8
v_div_scale_f32 v9, vcc_lo, v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v8
v_fma_f32 v11, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v8
v_fma_f32 v6, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v8, v10
v_div_fixup_f32 v5, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, s7, v5
v_cmpx_lt_f32_e32 v2, v5
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s6
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s6, s8, 1
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmpk_lg_i32 s4, 0x12c4
s_cbranch_scc0 .LBB0_8
s_mov_b32 s2, s8
s_mov_b32 s8, s6
s_branch .LBB0_2
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_and_b32_e32 v2, 1, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end0-_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.globl _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.p2align 8
.type _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi,@function
_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_9
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_mov_b64 s[4:5], 4
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, d_Vertices@rel32@lo+8
s_addc_u32 s15, s15, d_Vertices@rel32@hi+16
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, 0
s_movk_i32 s2, 0x257
s_mov_b32 s8, s3
global_load_b64 v[3:4], v[3:4], off
.LBB1_2:
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_Vertices@rel32@lo+4
s_addc_u32 s7, s7, d_Vertices@rel32@hi+12
s_add_u32 s10, s4, s6
s_addc_u32 s11, s5, s7
s_lshl_b64 s[12:13], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s12, s6
s_addc_u32 s7, s13, s7
s_add_u32 s12, s12, s14
s_addc_u32 s13, s13, s15
s_clause 0x1
s_load_b32 s9, s[10:11], 0x0
s_load_b32 s10, s[12:13], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, s9, v4
v_cmp_ngt_f32_e64 s2, s10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, vcc_lo, s2
s_xor_b32 s11, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s11
s_cbranch_execz .LBB1_6
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, d_Vertices@rel32@lo
s_addc_u32 s13, s13, d_Vertices@rel32@hi+8
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_clause 0x1
s_load_b32 s6, s[6:7], 0x0
s_load_b32 s7, s[12:13], 0x0
v_subrev_f32_e32 v5, s9, v4
v_sub_f32_e64 v7, s10, s9
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v6, s6, s7
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v5, v6
v_div_scale_f32 v6, null, v7, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v6, v8, 1.0
v_fmac_f32_e32 v8, v9, v8
v_div_scale_f32 v9, vcc_lo, v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v8
v_fma_f32 v11, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v8
v_fma_f32 v6, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v8, v10
v_div_fixup_f32 v5, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, s7, v5
v_cmpx_lt_f32_e32 v3, v5
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s6
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s6, s8, 1
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s4, 0x12c4
s_cbranch_scc1 .LBB1_8
s_mov_b32 s2, s8
s_mov_b32 s8, s6
s_branch .LBB1_2
.LBB1_8:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, .Lfunc_end1-_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.globl _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.p2align 8
.type _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi,@function
_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi:
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v0, s15, 8, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_9
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v4, 0
s_mov_b64 s[4:5], 4
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, d_Vertices@rel32@lo+8
s_addc_u32 s15, s15, d_Vertices@rel32@hi+16
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, 0
s_movk_i32 s2, 0x257
s_mov_b32 s8, s3
global_load_b64 v[2:3], v[2:3], off
.LBB2_2:
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_Vertices@rel32@lo+4
s_addc_u32 s7, s7, d_Vertices@rel32@hi+12
s_add_u32 s10, s4, s6
s_addc_u32 s11, s5, s7
s_lshl_b64 s[12:13], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s12, s6
s_addc_u32 s7, s13, s7
s_add_u32 s12, s12, s14
s_addc_u32 s13, s13, s15
s_clause 0x1
s_load_b32 s9, s[10:11], 0x0
s_load_b32 s10, s[12:13], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, s9, v3
v_cmp_ngt_f32_e64 s2, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, vcc_lo, s2
s_xor_b32 s11, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s11
s_cbranch_execz .LBB2_6
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, d_Vertices@rel32@lo
s_addc_u32 s13, s13, d_Vertices@rel32@hi+8
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_clause 0x1
s_load_b32 s6, s[6:7], 0x0
s_load_b32 s7, s[12:13], 0x0
v_subrev_f32_e32 v5, s9, v3
v_sub_f32_e64 v7, s10, s9
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v6, s6, s7
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v5, v6
v_div_scale_f32 v6, null, v7, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v6, v8, 1.0
v_fmac_f32_e32 v8, v9, v8
v_div_scale_f32 v9, vcc_lo, v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v8
v_fma_f32 v11, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v8
v_fma_f32 v6, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v8, v10
v_div_fixup_f32 v5, v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, s7, v5
v_cmpx_lt_f32_e32 v2, v5
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s6
.LBB2_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s6, s8, 1
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmpk_lg_i32 s4, 0x12c4
s_cbranch_scc0 .LBB2_8
s_mov_b32 s2, s8
s_mov_b32 s8, s6
s_branch .LBB2_2
.LBB2_8:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end2-_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_Vertices
.type d_Vertices,@object
.section .bss,"aw",@nobits
.globl d_Vertices
.p2align 4, 0x0
d_Vertices:
.zero 4800
.size d_Vertices, 4800
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_Vertices
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define VERTICES 600
__constant__ float2 d_Vertices[VERTICES];
//tuning parameters
//block_size_x any sensible thread block size
//tile_size any sensible tile size value
//prefetch 0 or 1 for reusing constant memory from previous iteration
//#ifndef prefetch
//#define prefetch 0
//#endif
#ifndef use_bitmap
#define use_bitmap 0
#define coalesce_bitmap 0
#endif
#ifndef block_size_x
#define block_size_x 256
#endif
#ifndef tile_size
#define tile_size 1
#endif
__global__ void cn_PnPoly(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * block_size_x * tile_size + threadIdx.x;
if (ti < n) {
// the crossing number counter
int cn[tile_size];
float2 p[tile_size];
#pragma unroll
for (int k=0; k<tile_size; k++) {
cn[k] = 0;
p[k] = points[ti+k*block_size_x];
}
int k = VERTICES-1;
// #if prefetch == 1
// float2 vj; // = d_Vertices[k];
// float2 vk;
// #endif
// loop through all edges of the polygon
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
// #if prefetch == 1
// float2 vj = d_Vertices[j];
// float2 vk = d_Vertices[k];
// #else
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
// #endif
#if method == 1
float vb = (vj.x - vk.x) / (vj.y - vk.y);
#endif
#pragma unroll
for (int i=0; i<tile_size; i++) {
#if method == 0
if ( ((vj.y>p[i].y) != (vk.y>p[i].y)) &&
(p[i].x < (vk.x-vj.x) * (p[i].y-vj.y) / (vk.y-vj.y) + vj.x) ) {
cn[i] = !cn[i];
}
#elif method == 1
int b = ((vk.y <= p[k].y) && (vj.y > p[k].y)) || ((vk.y > p[k].y) && (vj.y <= p[k].y));
cn[k] += b && (p[k].x < vk.x + vb * (p[k].y - vj.y));
#endif
}
}
#if use_bitmap == 1
int lane_index = threadIdx.x & (32 - 1);
unsigned int bitstring[tile_size];
#if coalesce_bitmap == 1
__shared__ unsigned int block_output[tile_size*block_size_x/32];
int warp_id = threadIdx.x/32;
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
//write at my position in bitstring
bitstring[k] = (cn[k] & 1) << (32-lane_index);
//compute sum of bitstring within warp
#pragma unroll
for (unsigned int s=16; s>0; s>>=1) {
bitstring[k] += __shfl_xor(bitstring[k], s);
}
#if coalesce_bitmap == 1
//store bitstring for this warp in shared buffer
if (lane_index == 0) {
block_output[warp_id+k*block_size_x/32] = bitstring[k];
}
#endif
}
__syncthreads();
#endif
#pragma unroll
for (int k=0; k<tile_size; k++) {
#if use_bitmap == 0
bitmap[ti+k*block_size_x] = (cn[k] & 1); // 0 if even (out), and 1 if odd (in)
#elif use_bitmap == 1
#if coalesce_bitmap == 0
if (lane_index == 0) {
bitmap[ti/32+k*block_size_x/32] = bitstring[k];
}
#elif coalesce_bitmap == 1
//write back results in coalesced manner
if (threadIdx.x < block_size_x/32) {
bitmap[ti/32+k*block_size_x/32] = block_output[warp_id];
}
#endif
#elif use_bitmap == 2
if (cn[k] & 1 == 1) {
bitmap[ti+k*block_size_x] = 1; // 0 if even (out), and 1 if odd (in)
}
#endif
}
}
}
__global__ void cn_PnPoly_naive(int* bitmap, float2* points, int n) {
int ti = blockIdx.x * blockDim.x + threadIdx.x;
// int ti = blockIdx.y * gridDim.x * blockDim.x + blockIdx.x * blockDim.x + threadIdx.x;
if (ti < n) {
// the crossing number counter
int c = 0;
float2 p = points[ti];
int k = VERTICES-1;
for (int j=0; j<VERTICES; k = j++) { // edge from v to vp
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[ti] = c; // 0 if even (out), and 1 if odd (in)
}
}
/*CPU version*/
float pnpoly_cn(int *bitmap, float2 *v, float2 *p) {
int nvert = VERTICES;
int npoint = 20000;
int i = 0;
for (i = 0; i < npoint; i++) {
int j, k, c = 0;
for (j = 0, k = nvert-1; j < nvert; k = j++) {
if ( ((v[j].y>p[i].y) != (v[k].y>p[i].y)) &&
(p[i].x < (v[k].x-v[j].x) * (p[i].y-v[j].y) / (v[k].y-v[j].y) + v[j].x) )
c = !c;
}
bitmap[i] = c & 1;
}
return 0.0;
}
/*GPU version*/
__global__ void pnpoly_cn_gpu(int *bitmap, float2 *points, int n) {
int i = blockIdx.x * block_size_x + threadIdx.x;
if (i < n) {
float2 p = points[i];
int c = 0;
int k = VERTICES-1;
int j = 0;
for (j = 0; j < VERTICES; k = j++) {
float2 vj = d_Vertices[j];
float2 vk = d_Vertices[k];
if ( ((vj.y>p.y) != (vk.y>p.y)) &&
(p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
c = !c;
}
bitmap[i] = c;
}
} | .text
.file "pnpoly.hip"
.globl _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi # -- Begin function _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.p2align 4, 0x90
.type _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi,@function
_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi: # @_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end0-_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi # -- Begin function _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.p2align 4, 0x90
.type _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi,@function
_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi: # @_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, .Lfunc_end1-_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.cfi_endproc
# -- End function
.globl _Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_ # -- Begin function _Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_
.p2align 4, 0x90
.type _Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_,@function
_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_: # @_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_1 Depth=1
andl $1, %ecx
movl %ecx, (%rdi,%rax,4)
incq %rax
cmpq $20000, %rax # imm = 0x4E20
je .LBB2_7
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movss 4(%rdx,%rax,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $599, %r8d # imm = 0x257
xorl %r9d, %r9d
xorl %ecx, %ecx
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_2 Depth=2
leaq 1(%r8), %r9
cmpq $600, %r9 # imm = 0x258
je .LBB2_6
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %r8d, %r10d
movq %r9, %r8
movss 4(%rsi,%r9,8), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss 4(%rsi,%r10,8), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm0, %xmm3
cmpltps %xmm1, %xmm3
movaps %xmm0, %xmm4
cmpnltps %xmm2, %xmm4
xorps %xmm3, %xmm4
movd %xmm4, %r9d
testb $1, %r9b
jne .LBB2_5
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movss (%rsi,%r10,8), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss (%rsi,%r8,8), %xmm4 # xmm4 = mem[0],zero,zero,zero
subss %xmm4, %xmm3
movaps %xmm0, %xmm5
subss %xmm1, %xmm5
mulss %xmm3, %xmm5
subss %xmm1, %xmm2
divss %xmm2, %xmm5
addss %xmm4, %xmm5
ucomiss (%rdx,%rax,8), %xmm5
jbe .LBB2_5
# %bb.4: # in Loop: Header=BB2_2 Depth=2
xorl %r9d, %r9d
testl %ecx, %ecx
sete %r9b
movl %r9d, %ecx
jmp .LBB2_5
.LBB2_7:
xorps %xmm0, %xmm0
retq
.Lfunc_end2:
.size _Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_, .Lfunc_end2-_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi # -- Begin function _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.p2align 4, 0x90
.type _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi,@function
_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi: # @_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end3-_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_Vertices, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4800, %r9d # imm = 0x12C0
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_Vertices,@object # @d_Vertices
.local d_Vertices
.comm d_Vertices,4800,16
.type _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi,@object # @_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.section .rodata,"a",@progbits
.globl _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.p2align 3, 0x0
_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi:
.quad _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.size _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, 8
.type _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi,@object # @_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.globl _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.p2align 3, 0x0
_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi:
.quad _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.size _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, 8
.type _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi,@object # @_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.globl _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.p2align 3, 0x0
_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi:
.quad _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.size _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi"
.size .L__unnamed_1, 41
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi"
.size .L__unnamed_2, 48
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi"
.size .L__unnamed_3, 46
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "d_Vertices"
.size .L__unnamed_4, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.addrsig_sym _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.addrsig_sym _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_Vertices
.addrsig_sym _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.addrsig_sym _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.addrsig_sym _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010f375_00000000-6_pnpoly.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9pnpoly_cnPiP6float2S1_
.type _Z9pnpoly_cnPiP6float2S1_, @function
_Z9pnpoly_cnPiP6float2S1_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rsi, %rcx
movq %rdx, %r9
movq %rdi, %r10
leaq 160000(%rdx), %rbp
movl $0, %ebx
movl $599, %r11d
jmp .L4
.L5:
addq $1, %rax
cmpq $600, %rax
je .L12
.L7:
movl %esi, %edx
movl %eax, %esi
movss 4(%rcx,%rax,8), %xmm3
movslq %edx, %rdx
leaq (%rcx,%rdx,8), %rdx
movss 4(%rdx), %xmm2
comiss %xmm4, %xmm3
seta %r13b
comiss %xmm4, %xmm2
seta %r12b
cmpb %r12b, %r13b
je .L5
movss (%rcx,%rax,8), %xmm5
movss (%rdx), %xmm1
subss %xmm5, %xmm1
movaps %xmm4, %xmm0
subss %xmm3, %xmm0
mulss %xmm1, %xmm0
subss %xmm3, %xmm2
divss %xmm2, %xmm0
addss %xmm5, %xmm0
comiss (%r8), %xmm0
jbe .L5
xorl $1, %edi
jmp .L5
.L12:
movl %edi, (%r10)
addq $8, %r9
addq $4, %r10
cmpq %rbp, %r9
je .L8
.L4:
movq %r9, %r8
movss 4(%r9), %xmm4
movl $0, %eax
movl %ebx, %edi
movl %r11d, %esi
jmp .L7
.L8:
pxor %xmm0, %xmm0
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size _Z9pnpoly_cnPiP6float2S1_, .-_Z9pnpoly_cnPiP6float2S1_
.globl _Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i
.type _Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i, @function
_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9cn_PnPolyPiP6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i, .-_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i
.globl _Z9cn_PnPolyPiP6float2i
.type _Z9cn_PnPolyPiP6float2i, @function
_Z9cn_PnPolyPiP6float2i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z9cn_PnPolyPiP6float2i, .-_Z9cn_PnPolyPiP6float2i
.globl _Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i
.type _Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i, @function
_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i:
.LFB2054:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15cn_PnPoly_naivePiP6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i, .-_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i
.globl _Z15cn_PnPoly_naivePiP6float2i
.type _Z15cn_PnPoly_naivePiP6float2i, @function
_Z15cn_PnPoly_naivePiP6float2i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z15cn_PnPoly_naivePiP6float2i, .-_Z15cn_PnPoly_naivePiP6float2i
.globl _Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i
.type _Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i, @function
_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i:
.LFB2056:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13pnpoly_cn_gpuPiP6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i, .-_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i
.globl _Z13pnpoly_cn_gpuPiP6float2i
.type _Z13pnpoly_cn_gpuPiP6float2i, @function
_Z13pnpoly_cn_gpuPiP6float2i:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13pnpoly_cn_gpuPiP6float2i, .-_Z13pnpoly_cn_gpuPiP6float2i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13pnpoly_cn_gpuPiP6float2i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z15cn_PnPoly_naivePiP6float2i"
.section .rodata.str1.1
.LC3:
.string "_Z9cn_PnPolyPiP6float2i"
.LC4:
.string "d_Vertices"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13pnpoly_cn_gpuPiP6float2i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cn_PnPoly_naivePiP6float2i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cn_PnPolyPiP6float2i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4800, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10d_Vertices(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10d_Vertices
.comm _ZL10d_Vertices,4800,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pnpoly.hip"
.globl _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi # -- Begin function _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.p2align 4, 0x90
.type _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi,@function
_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi: # @_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end0-_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi # -- Begin function _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.p2align 4, 0x90
.type _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi,@function
_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi: # @_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, .Lfunc_end1-_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.cfi_endproc
# -- End function
.globl _Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_ # -- Begin function _Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_
.p2align 4, 0x90
.type _Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_,@function
_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_: # @_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_1 Depth=1
andl $1, %ecx
movl %ecx, (%rdi,%rax,4)
incq %rax
cmpq $20000, %rax # imm = 0x4E20
je .LBB2_7
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movss 4(%rdx,%rax,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $599, %r8d # imm = 0x257
xorl %r9d, %r9d
xorl %ecx, %ecx
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_2 Depth=2
leaq 1(%r8), %r9
cmpq $600, %r9 # imm = 0x258
je .LBB2_6
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %r8d, %r10d
movq %r9, %r8
movss 4(%rsi,%r9,8), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss 4(%rsi,%r10,8), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm0, %xmm3
cmpltps %xmm1, %xmm3
movaps %xmm0, %xmm4
cmpnltps %xmm2, %xmm4
xorps %xmm3, %xmm4
movd %xmm4, %r9d
testb $1, %r9b
jne .LBB2_5
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movss (%rsi,%r10,8), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss (%rsi,%r8,8), %xmm4 # xmm4 = mem[0],zero,zero,zero
subss %xmm4, %xmm3
movaps %xmm0, %xmm5
subss %xmm1, %xmm5
mulss %xmm3, %xmm5
subss %xmm1, %xmm2
divss %xmm2, %xmm5
addss %xmm4, %xmm5
ucomiss (%rdx,%rax,8), %xmm5
jbe .LBB2_5
# %bb.4: # in Loop: Header=BB2_2 Depth=2
xorl %r9d, %r9d
testl %ecx, %ecx
sete %r9b
movl %r9d, %ecx
jmp .LBB2_5
.LBB2_7:
xorps %xmm0, %xmm0
retq
.Lfunc_end2:
.size _Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_, .Lfunc_end2-_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi # -- Begin function _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.p2align 4, 0x90
.type _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi,@function
_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi: # @_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end3-_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_Vertices, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4800, %r9d # imm = 0x12C0
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_Vertices,@object # @d_Vertices
.local d_Vertices
.comm d_Vertices,4800,16
.type _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi,@object # @_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.section .rodata,"a",@progbits
.globl _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.p2align 3, 0x0
_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi:
.quad _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.size _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, 8
.type _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi,@object # @_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.globl _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.p2align 3, 0x0
_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi:
.quad _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.size _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, 8
.type _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi,@object # @_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.globl _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.p2align 3, 0x0
_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi:
.quad _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.size _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi"
.size .L__unnamed_1, 41
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi"
.size .L__unnamed_2, 48
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi"
.size .L__unnamed_3, 46
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "d_Vertices"
.size .L__unnamed_4, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.addrsig_sym _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.addrsig_sym _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_Vertices
.addrsig_sym _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
.addrsig_sym _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
.addrsig_sym _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <curand_kernel.h>
#include <stdio.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
int id = blockIdx.x*blockDim.x + threadIdx.x;
if (id < n) // Prevents more than N operations
{
y[id] = a*x[id] + y[id];
// printf( " y[id] %f , " , y[id] );
}
}
void random_float(float* random, int size)
{
for (int i=0;i<size;i++)
{
random[i]=((float)rand()/(float)(RAND_MAX));
}
}
int main(void)
{
int N;
float A;
int nDevices;
int max_threads_per_blok = 0;
int max_grid_size = 0;
int max_thread_blocks = 0;
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
cudaGetDeviceCount(&nDevices);
printf("cudaGetDeviceCount: %d\n", nDevices);
printf("There are %d CUDA devices.\n", nDevices);
for (int i = 0; i < nDevices; i++)
{
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printf("Device Number: %d \n", i);
printf("Device name: %s \n ", prop.name);
printf("Block dimensions: %d x %d x %d \n", prop.maxThreadsDim[0],prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("Maximum number of threads per block: %d\n", prop.maxThreadsPerBlock);
max_threads_per_blok= prop.maxThreadsPerBlock;
printf ("Grid dimensions: %d x %d x %d \n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
max_grid_size = prop.maxGridSize[0];
if (max_grid_size < prop.maxGridSize[1])
{
max_grid_size = prop.maxGridSize[1];
}
else if (max_grid_size < prop.maxGridSize[2])
{
max_grid_size = prop.maxGridSize[2];
}
// grid size give threads number in grid
max_thread_blocks = max_grid_size / max_threads_per_blok; // prop.maxGridSize[0] / prop.maxThreadsDim[0] for this operation used x dimension
printf (" Maximum number of thread blocks for x = %d \n", max_thread_blocks);
}
printf("Please input an N value: ");
scanf("%d", &N);
printf("Please input an A value: ");
scanf("%f", &A);
float *h_x, *h_y, *d_x, *d_y;
size_t size = N * sizeof(float);
// Allocate the host input x
h_x = (float *)malloc(size);
// Allocate the host input y
h_y = (float *)malloc(size);
// Verify that allocations succeeded
if (h_x == NULL || h_y == NULL)
{
fprintf(stderr, "Failed to allocate host x and y\n");
exit(EXIT_FAILURE);
}
random_float(h_x, N);
random_float(h_y, N);
d_x = NULL;
err = cudaMalloc((void **)&d_x, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device x (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
d_y = NULL;
err = cudaMalloc((void **)&d_y, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device y (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy x from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy y from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
int number_of_blocks = (N+1023)/1024;
printf("Print max_threads %d \n " , (max_thread_blocks * max_threads_per_blok) );
if( N <= (max_thread_blocks * max_threads_per_blok)) // cannot be greater than the total number of threads
{
int number_of_threads_per_block = (N/number_of_blocks);
//This control is added to avoid missing the number of threads when integer does not give value when number is divided.
if (N % number_of_blocks != 0 && number_of_threads_per_block < 1024)
{
number_of_threads_per_block = number_of_threads_per_block+1;
}
if (number_of_blocks <= max_thread_blocks )
{
printf (" saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n ",number_of_blocks ,number_of_threads_per_block);
saxpy<<<number_of_blocks ,number_of_threads_per_block >>>(N, A, d_x, d_y);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch saxpy kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
}
else
{
printf ("N number is too large, please enter a smaller number\n");
}
err = cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy y from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_x);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device x (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_y);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device y (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_x);
free(h_y);
} | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <curand_kernel.h>
#include <stdio.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
int id = blockIdx.x*blockDim.x + threadIdx.x;
if (id < n) // Prevents more than N operations
{
y[id] = a*x[id] + y[id];
// printf( " y[id] %f , " , y[id] );
}
}
void random_float(float* random, int size)
{
for (int i=0;i<size;i++)
{
random[i]=((float)rand()/(float)(RAND_MAX));
}
}
int main(void)
{
int N;
float A;
int nDevices;
int max_threads_per_blok = 0;
int max_grid_size = 0;
int max_thread_blocks = 0;
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
cudaGetDeviceCount(&nDevices);
printf("cudaGetDeviceCount: %d\n", nDevices);
printf("There are %d CUDA devices.\n", nDevices);
for (int i = 0; i < nDevices; i++)
{
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printf("Device Number: %d \n", i);
printf("Device name: %s \n ", prop.name);
printf("Block dimensions: %d x %d x %d \n", prop.maxThreadsDim[0],prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("Maximum number of threads per block: %d\n", prop.maxThreadsPerBlock);
max_threads_per_blok= prop.maxThreadsPerBlock;
printf ("Grid dimensions: %d x %d x %d \n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
max_grid_size = prop.maxGridSize[0];
if (max_grid_size < prop.maxGridSize[1])
{
max_grid_size = prop.maxGridSize[1];
}
else if (max_grid_size < prop.maxGridSize[2])
{
max_grid_size = prop.maxGridSize[2];
}
// grid size give threads number in grid
max_thread_blocks = max_grid_size / max_threads_per_blok; // prop.maxGridSize[0] / prop.maxThreadsDim[0] for this operation used x dimension
printf (" Maximum number of thread blocks for x = %d \n", max_thread_blocks);
}
printf("Please input an N value: ");
scanf("%d", &N);
printf("Please input an A value: ");
scanf("%f", &A);
float *h_x, *h_y, *d_x, *d_y;
size_t size = N * sizeof(float);
// Allocate the host input x
h_x = (float *)malloc(size);
// Allocate the host input y
h_y = (float *)malloc(size);
// Verify that allocations succeeded
if (h_x == NULL || h_y == NULL)
{
fprintf(stderr, "Failed to allocate host x and y\n");
exit(EXIT_FAILURE);
}
random_float(h_x, N);
random_float(h_y, N);
d_x = NULL;
err = cudaMalloc((void **)&d_x, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device x (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
d_y = NULL;
err = cudaMalloc((void **)&d_y, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device y (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy x from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy y from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
int number_of_blocks = (N+1023)/1024;
printf("Print max_threads %d \n " , (max_thread_blocks * max_threads_per_blok) );
if( N <= (max_thread_blocks * max_threads_per_blok)) // cannot be greater than the total number of threads
{
int number_of_threads_per_block = (N/number_of_blocks);
//This control is added to avoid missing the number of threads when integer does not give value when number is divided.
if (N % number_of_blocks != 0 && number_of_threads_per_block < 1024)
{
number_of_threads_per_block = number_of_threads_per_block+1;
}
if (number_of_blocks <= max_thread_blocks )
{
printf (" saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n ",number_of_blocks ,number_of_threads_per_block);
saxpy<<<number_of_blocks ,number_of_threads_per_block >>>(N, A, d_x, d_y);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch saxpy kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
}
else
{
printf ("N number is too large, please enter a smaller number\n");
}
err = cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy y from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_x);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device x (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_y);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device y (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_x);
free(h_y);
} | .file "tmpxft_000aace2_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12random_floatPfi
.type _Z12random_floatPfi, @function
_Z12random_floatPfi:
.LFB2271:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2271:
.size _Z12random_floatPfi, .-_Z12random_floatPfi
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2297:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaGetDeviceCount: %d\n"
.LC2:
.string "There are %d CUDA devices.\n"
.LC3:
.string "Device Number: %d \n"
.LC4:
.string "Device name: %s \n "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Block dimensions: %d x %d x %d \n"
.align 8
.LC6:
.string "Maximum number of threads per block: %d\n"
.align 8
.LC7:
.string "Grid dimensions: %d x %d x %d \n"
.align 8
.LC8:
.string " Maximum number of thread blocks for x = %d \n"
.section .rodata.str1.1
.LC9:
.string "Please input an N value: "
.LC10:
.string "%d"
.LC11:
.string "Please input an A value: "
.LC12:
.string "%f"
.section .rodata.str1.8
.align 8
.LC13:
.string "Failed to allocate host x and y\n"
.align 8
.LC14:
.string "Failed to allocate device x (error code %s)!\n"
.align 8
.LC15:
.string "Failed to allocate device y (error code %s)!\n"
.align 8
.LC16:
.string "Failed to copy x from host to device (error code %s)!\n"
.align 8
.LC17:
.string "Failed to copy y from host to device (error code %s)!\n"
.section .rodata.str1.1
.LC18:
.string "Print max_threads %d \n "
.section .rodata.str1.8
.align 8
.LC19:
.string " saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n "
.align 8
.LC20:
.string "Failed to launch saxpy kernel (error code %s)!\n"
.align 8
.LC21:
.string "N number is too large, please enter a smaller number\n"
.align 8
.LC22:
.string "Failed to copy y from device to host (error code %s)!\n"
.align 8
.LC23:
.string "Failed to free device x (error code %s)!\n"
.align 8
.LC24:
.string "Failed to free device y (error code %s)!\n"
.text
.globl main
.type main, @function
main:
.LFB2272:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
leaq 36(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 36(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 36(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 36(%rsp)
jle .L37
movl $0, %ebx
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %r12
jmp .L22
.L21:
cltd
idivl %ebp
movl %eax, 12(%rsp)
movl %eax, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 36(%rsp)
jle .L20
.L22:
leaq 80(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 412(%rsp), %r8d
movl 408(%rsp), %ecx
movl 404(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 400(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 400(%rsp), %ebp
movl 424(%rsp), %r8d
movl 420(%rsp), %ecx
movl 416(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 416(%rsp), %edx
movl 420(%rsp), %eax
cmpl %edx, %eax
jg .L21
movl 424(%rsp), %eax
cmpl %eax, %edx
cmovge %edx, %eax
jmp .L21
.L37:
movl $0, 12(%rsp)
movl $0, %ebp
.L20:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
leaq .LC10(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rsi
leaq .LC12(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %r14d
movslq %r14d, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testq %r13, %r13
je .L38
testq %rax, %rax
je .L38
movl %r14d, %esi
movq %r13, %rdi
call _Z12random_floatPfi
movl 28(%rsp), %esi
movq %r12, %rdi
call _Z12random_floatPfi
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movq $0, 48(%rsp)
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L43
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L44
movl 28(%rsp), %r14d
movl 12(%rsp), %eax
imull %eax, %ebp
movl %ebp, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %eax
cmpl %eax, %ebp
jl .L29
leal 2046(%r14), %ebp
addl $1023, %r14d
cmovns %r14d, %ebp
sarl $10, %ebp
cltd
idivl %ebp
movl %eax, %r14d
testl %edx, %edx
je .L30
cmpl $1023, %eax
jle .L45
.L30:
movl 12(%rsp), %eax
cmpl %eax, %ebp
jle .L46
.L31:
movl $2, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L48
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L49
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
leal 1(%rax), %r14d
jmp .L30
.L46:
movl %r14d, %ecx
movl %ebp, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, 68(%rsp)
movl $1, 72(%rsp)
movl %ebp, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L32:
call cudaGetLastError@PLT
testl %eax, %eax
je .L31
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movss 32(%rsp), %xmm0
movl 28(%rsp), %edi
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
jmp .L32
.L29:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2272:
.size main, .-main
.section .rodata.str1.1
.LC25:
.string "_Z5saxpyifPfS_"
.LC26:
.string "precalc_xorwow_matrix"
.LC27:
.string "precalc_xorwow_offset_matrix"
.LC28:
.string "mrg32k3aM1"
.LC29:
.string "mrg32k3aM2"
.LC30:
.string "mrg32k3aM1SubSeq"
.LC31:
.string "mrg32k3aM2SubSeq"
.LC32:
.string "mrg32k3aM1Seq"
.LC33:
.string "mrg32k3aM2Seq"
.LC34:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2300:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC32(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC33(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC34(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <curand_kernel.h>
#include <stdio.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
int id = blockIdx.x*blockDim.x + threadIdx.x;
if (id < n) // Prevents more than N operations
{
y[id] = a*x[id] + y[id];
// printf( " y[id] %f , " , y[id] );
}
}
void random_float(float* random, int size)
{
for (int i=0;i<size;i++)
{
random[i]=((float)rand()/(float)(RAND_MAX));
}
}
int main(void)
{
int N;
float A;
int nDevices;
int max_threads_per_blok = 0;
int max_grid_size = 0;
int max_thread_blocks = 0;
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
cudaGetDeviceCount(&nDevices);
printf("cudaGetDeviceCount: %d\n", nDevices);
printf("There are %d CUDA devices.\n", nDevices);
for (int i = 0; i < nDevices; i++)
{
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printf("Device Number: %d \n", i);
printf("Device name: %s \n ", prop.name);
printf("Block dimensions: %d x %d x %d \n", prop.maxThreadsDim[0],prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("Maximum number of threads per block: %d\n", prop.maxThreadsPerBlock);
max_threads_per_blok= prop.maxThreadsPerBlock;
printf ("Grid dimensions: %d x %d x %d \n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
max_grid_size = prop.maxGridSize[0];
if (max_grid_size < prop.maxGridSize[1])
{
max_grid_size = prop.maxGridSize[1];
}
else if (max_grid_size < prop.maxGridSize[2])
{
max_grid_size = prop.maxGridSize[2];
}
// grid size give threads number in grid
max_thread_blocks = max_grid_size / max_threads_per_blok; // prop.maxGridSize[0] / prop.maxThreadsDim[0] for this operation used x dimension
printf (" Maximum number of thread blocks for x = %d \n", max_thread_blocks);
}
printf("Please input an N value: ");
scanf("%d", &N);
printf("Please input an A value: ");
scanf("%f", &A);
float *h_x, *h_y, *d_x, *d_y;
size_t size = N * sizeof(float);
// Allocate the host input x
h_x = (float *)malloc(size);
// Allocate the host input y
h_y = (float *)malloc(size);
// Verify that allocations succeeded
if (h_x == NULL || h_y == NULL)
{
fprintf(stderr, "Failed to allocate host x and y\n");
exit(EXIT_FAILURE);
}
random_float(h_x, N);
random_float(h_y, N);
d_x = NULL;
err = cudaMalloc((void **)&d_x, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device x (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
d_y = NULL;
err = cudaMalloc((void **)&d_y, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device y (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy x from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy y from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
int number_of_blocks = (N+1023)/1024;
printf("Print max_threads %d \n " , (max_thread_blocks * max_threads_per_blok) );
if( N <= (max_thread_blocks * max_threads_per_blok)) // cannot be greater than the total number of threads
{
int number_of_threads_per_block = (N/number_of_blocks);
//This control is added to avoid missing the number of threads when integer does not give value when number is divided.
if (N % number_of_blocks != 0 && number_of_threads_per_block < 1024)
{
number_of_threads_per_block = number_of_threads_per_block+1;
}
if (number_of_blocks <= max_thread_blocks )
{
printf (" saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n ",number_of_blocks ,number_of_threads_per_block);
saxpy<<<number_of_blocks ,number_of_threads_per_block >>>(N, A, d_x, d_y);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch saxpy kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
}
else
{
printf ("N number is too large, please enter a smaller number\n");
}
err = cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy y from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_x);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device x (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_y);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device y (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_x);
free(h_y);
} | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
int id = blockIdx.x*blockDim.x + threadIdx.x;
if (id < n) // Prevents more than N operations
{
y[id] = a*x[id] + y[id];
// printf( " y[id] %f , " , y[id] );
}
}
void random_float(float* random, int size)
{
for (int i=0;i<size;i++)
{
random[i]=((float)rand()/(float)(RAND_MAX));
}
}
int main(void)
{
int N;
float A;
int nDevices;
int max_threads_per_blok = 0;
int max_grid_size = 0;
int max_thread_blocks = 0;
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
hipGetDeviceCount(&nDevices);
printf("cudaGetDeviceCount: %d\n", nDevices);
printf("There are %d CUDA devices.\n", nDevices);
for (int i = 0; i < nDevices; i++)
{
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printf("Device Number: %d \n", i);
printf("Device name: %s \n ", prop.name);
printf("Block dimensions: %d x %d x %d \n", prop.maxThreadsDim[0],prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("Maximum number of threads per block: %d\n", prop.maxThreadsPerBlock);
max_threads_per_blok= prop.maxThreadsPerBlock;
printf ("Grid dimensions: %d x %d x %d \n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
max_grid_size = prop.maxGridSize[0];
if (max_grid_size < prop.maxGridSize[1])
{
max_grid_size = prop.maxGridSize[1];
}
else if (max_grid_size < prop.maxGridSize[2])
{
max_grid_size = prop.maxGridSize[2];
}
// grid size give threads number in grid
max_thread_blocks = max_grid_size / max_threads_per_blok; // prop.maxGridSize[0] / prop.maxThreadsDim[0] for this operation used x dimension
printf (" Maximum number of thread blocks for x = %d \n", max_thread_blocks);
}
printf("Please input an N value: ");
scanf("%d", &N);
printf("Please input an A value: ");
scanf("%f", &A);
float *h_x, *h_y, *d_x, *d_y;
size_t size = N * sizeof(float);
// Allocate the host input x
h_x = (float *)malloc(size);
// Allocate the host input y
h_y = (float *)malloc(size);
// Verify that allocations succeeded
if (h_x == NULL || h_y == NULL)
{
fprintf(stderr, "Failed to allocate host x and y\n");
exit(EXIT_FAILURE);
}
random_float(h_x, N);
random_float(h_y, N);
d_x = NULL;
err = hipMalloc((void **)&d_x, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device x (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
d_y = NULL;
err = hipMalloc((void **)&d_y, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device y (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy x from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_y, h_y, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy y from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
int number_of_blocks = (N+1023)/1024;
printf("Print max_threads %d \n " , (max_thread_blocks * max_threads_per_blok) );
if( N <= (max_thread_blocks * max_threads_per_blok)) // cannot be greater than the total number of threads
{
int number_of_threads_per_block = (N/number_of_blocks);
//This control is added to avoid missing the number of threads when integer does not give value when number is divided.
if (N % number_of_blocks != 0 && number_of_threads_per_block < 1024)
{
number_of_threads_per_block = number_of_threads_per_block+1;
}
if (number_of_blocks <= max_thread_blocks )
{
printf (" saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n ",number_of_blocks ,number_of_threads_per_block);
saxpy<<<number_of_blocks ,number_of_threads_per_block >>>(N, A, d_x, d_y);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch saxpy kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
}
else
{
printf ("N number is too large, please enter a smaller number\n");
}
err = hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy y from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_x);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device x (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_y);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device y (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_x);
free(h_y);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
int id = blockIdx.x*blockDim.x + threadIdx.x;
if (id < n) // Prevents more than N operations
{
y[id] = a*x[id] + y[id];
// printf( " y[id] %f , " , y[id] );
}
}
void random_float(float* random, int size)
{
for (int i=0;i<size;i++)
{
random[i]=((float)rand()/(float)(RAND_MAX));
}
}
int main(void)
{
int N;
float A;
int nDevices;
int max_threads_per_blok = 0;
int max_grid_size = 0;
int max_thread_blocks = 0;
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
hipGetDeviceCount(&nDevices);
printf("cudaGetDeviceCount: %d\n", nDevices);
printf("There are %d CUDA devices.\n", nDevices);
for (int i = 0; i < nDevices; i++)
{
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printf("Device Number: %d \n", i);
printf("Device name: %s \n ", prop.name);
printf("Block dimensions: %d x %d x %d \n", prop.maxThreadsDim[0],prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("Maximum number of threads per block: %d\n", prop.maxThreadsPerBlock);
max_threads_per_blok= prop.maxThreadsPerBlock;
printf ("Grid dimensions: %d x %d x %d \n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
max_grid_size = prop.maxGridSize[0];
if (max_grid_size < prop.maxGridSize[1])
{
max_grid_size = prop.maxGridSize[1];
}
else if (max_grid_size < prop.maxGridSize[2])
{
max_grid_size = prop.maxGridSize[2];
}
// grid size give threads number in grid
max_thread_blocks = max_grid_size / max_threads_per_blok; // prop.maxGridSize[0] / prop.maxThreadsDim[0] for this operation used x dimension
printf (" Maximum number of thread blocks for x = %d \n", max_thread_blocks);
}
printf("Please input an N value: ");
scanf("%d", &N);
printf("Please input an A value: ");
scanf("%f", &A);
float *h_x, *h_y, *d_x, *d_y;
size_t size = N * sizeof(float);
// Allocate the host input x
h_x = (float *)malloc(size);
// Allocate the host input y
h_y = (float *)malloc(size);
// Verify that allocations succeeded
if (h_x == NULL || h_y == NULL)
{
fprintf(stderr, "Failed to allocate host x and y\n");
exit(EXIT_FAILURE);
}
random_float(h_x, N);
random_float(h_y, N);
d_x = NULL;
err = hipMalloc((void **)&d_x, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device x (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
d_y = NULL;
err = hipMalloc((void **)&d_y, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device y (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy x from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_y, h_y, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy y from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
int number_of_blocks = (N+1023)/1024;
printf("Print max_threads %d \n " , (max_thread_blocks * max_threads_per_blok) );
if( N <= (max_thread_blocks * max_threads_per_blok)) // cannot be greater than the total number of threads
{
int number_of_threads_per_block = (N/number_of_blocks);
//This control is added to avoid missing the number of threads when integer does not give value when number is divided.
if (N % number_of_blocks != 0 && number_of_threads_per_block < 1024)
{
number_of_threads_per_block = number_of_threads_per_block+1;
}
if (number_of_blocks <= max_thread_blocks )
{
printf (" saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n ",number_of_blocks ,number_of_threads_per_block);
saxpy<<<number_of_blocks ,number_of_threads_per_block >>>(N, A, d_x, d_y);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch saxpy kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
}
else
{
printf ("N number is too large, please enter a smaller number\n");
}
err = hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy y from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_x);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device x (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_y);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device y (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_x);
free(h_y);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
int id = blockIdx.x*blockDim.x + threadIdx.x;
if (id < n) // Prevents more than N operations
{
y[id] = a*x[id] + y[id];
// printf( " y[id] %f , " , y[id] );
}
}
void random_float(float* random, int size)
{
for (int i=0;i<size;i++)
{
random[i]=((float)rand()/(float)(RAND_MAX));
}
}
int main(void)
{
int N;
float A;
int nDevices;
int max_threads_per_blok = 0;
int max_grid_size = 0;
int max_thread_blocks = 0;
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
hipGetDeviceCount(&nDevices);
printf("cudaGetDeviceCount: %d\n", nDevices);
printf("There are %d CUDA devices.\n", nDevices);
for (int i = 0; i < nDevices; i++)
{
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printf("Device Number: %d \n", i);
printf("Device name: %s \n ", prop.name);
printf("Block dimensions: %d x %d x %d \n", prop.maxThreadsDim[0],prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("Maximum number of threads per block: %d\n", prop.maxThreadsPerBlock);
max_threads_per_blok= prop.maxThreadsPerBlock;
printf ("Grid dimensions: %d x %d x %d \n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
max_grid_size = prop.maxGridSize[0];
if (max_grid_size < prop.maxGridSize[1])
{
max_grid_size = prop.maxGridSize[1];
}
else if (max_grid_size < prop.maxGridSize[2])
{
max_grid_size = prop.maxGridSize[2];
}
// grid size give threads number in grid
max_thread_blocks = max_grid_size / max_threads_per_blok; // prop.maxGridSize[0] / prop.maxThreadsDim[0] for this operation used x dimension
printf (" Maximum number of thread blocks for x = %d \n", max_thread_blocks);
}
printf("Please input an N value: ");
scanf("%d", &N);
printf("Please input an A value: ");
scanf("%f", &A);
float *h_x, *h_y, *d_x, *d_y;
size_t size = N * sizeof(float);
// Allocate the host input x
h_x = (float *)malloc(size);
// Allocate the host input y
h_y = (float *)malloc(size);
// Verify that allocations succeeded
if (h_x == NULL || h_y == NULL)
{
fprintf(stderr, "Failed to allocate host x and y\n");
exit(EXIT_FAILURE);
}
random_float(h_x, N);
random_float(h_y, N);
d_x = NULL;
err = hipMalloc((void **)&d_x, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device x (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
d_y = NULL;
err = hipMalloc((void **)&d_y, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device y (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy x from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_y, h_y, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy y from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
int number_of_blocks = (N+1023)/1024;
printf("Print max_threads %d \n " , (max_thread_blocks * max_threads_per_blok) );
if( N <= (max_thread_blocks * max_threads_per_blok)) // cannot be greater than the total number of threads
{
int number_of_threads_per_block = (N/number_of_blocks);
//This control is added to avoid missing the number of threads when integer does not give value when number is divided.
if (N % number_of_blocks != 0 && number_of_threads_per_block < 1024)
{
number_of_threads_per_block = number_of_threads_per_block+1;
}
if (number_of_blocks <= max_thread_blocks )
{
printf (" saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n ",number_of_blocks ,number_of_threads_per_block);
saxpy<<<number_of_blocks ,number_of_threads_per_block >>>(N, A, d_x, d_y);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch saxpy kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
}
else
{
printf ("N number is too large, please enter a smaller number\n");
}
err = hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy y from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_x);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device x (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_y);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device y (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_x);
free(h_y);
} | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12random_floatPfi
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z12random_floatPfi
.p2align 4, 0x90
.type _Z12random_floatPfi,@function
_Z12random_floatPfi: # @_Z12random_floatPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z12random_floatPfi, .Lfunc_end1-_Z12random_floatPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
xorl %r12d, %r12d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
movl $0, %ebp
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %r14d, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 436(%rsp), %esi
movl 440(%rsp), %edx
movl 444(%rsp), %ecx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 432(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 432(%rsp), %ebp
movl 448(%rsp), %esi
movl 452(%rsp), %edx
movl 456(%rsp), %ecx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 448(%rsp), %ecx
movl 456(%rsp), %eax
cmpl %eax, %ecx
cmovgl %ecx, %eax
movl 452(%rsp), %edx
cmpl %edx, %ecx
cmovll %edx, %eax
cltd
idivl %ebp
movl %eax, %r12d
movl $.L.str.7, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
incl %r14d
cmpl 4(%rsp), %r14d
jl .LBB2_2
.LBB2_3: # %._crit_edge
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq %rsp, %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
leaq 28(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq (%rsp), %r13
leaq (,%r13,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
testq %rbx, %rbx
je .LBB2_34
# %bb.4: # %._crit_edge
movq %rax, %r14
testq %rax, %rax
je .LBB2_34
# %bb.5:
movq %r15, 40(%rsp) # 8-byte Spill
movl %r13d, %r13d
testl %r13d, %r13d
jle .LBB2_8
# %bb.6: # %.lr.ph.preheader.i
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r13
jne .LBB2_7
.LBB2_8: # %_Z12random_floatPfi.exit
movl (%rsp), %r13d
testl %r13d, %r13d
jle .LBB2_11
# %bb.9: # %.lr.ph.preheader.i91
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_10: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %r13
jne .LBB2_10
.LBB2_11: # %_Z12random_floatPfi.exit97
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.14:
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_15
# %bb.16:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.18:
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.20:
movl (%rsp), %r13d
leal 1023(%r13), %eax
addl $2046, %r13d # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %r13d
imull %r12d, %ebp
movl $.L.str.17, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl (%rsp), %eax
cmpl %ebp, %eax
jle .LBB2_21
# %bb.26:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB2_27
.LBB2_21:
sarl $10, %r13d
cmpl %r12d, %r13d
jg .LBB2_27
# %bb.22:
cltd
idivl %r13d
testl %edx, %edx
setne %cl
cmpl $1024, %eax # imm = 0x400
setl %dl
andb %cl, %dl
movzbl %dl, %r12d
addl %eax, %r12d
movl $.L.str.18, %edi
movl %r13d, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %r12
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_24
# %bb.23:
movl (%rsp), %eax
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl %eax, 36(%rsp)
movss %xmm0, 32(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_24:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_25
.LBB2_27:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_28
# %bb.29:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_30
# %bb.31:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_32
# %bb.33:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_34:
.cfi_def_cfa_offset 1648
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $32, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB2_13
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %esi
jmp .LBB2_13
.LBB2_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
jmp .LBB2_13
.LBB2_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
jmp .LBB2_13
.LBB2_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
jmp .LBB2_13
.LBB2_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.22, %esi
jmp .LBB2_13
.LBB2_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.23, %esi
jmp .LBB2_13
.LBB2_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.19, %esi
.LBB2_13:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaGetDeviceCount: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "There are %d CUDA devices.\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device Number: %d \n"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device name: %s \n "
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Block dimensions: %d x %d x %d \n"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Maximum number of threads per block: %d\n"
.size .L.str.5, 41
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Grid dimensions: %d x %d x %d \n"
.size .L.str.6, 33
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Maximum number of thread blocks for x = %d \n"
.size .L.str.7, 47
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Please input an N value: "
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Please input an A value: "
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%f"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to allocate host x and y\n"
.size .L.str.12, 33
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to allocate device x (error code %s)!\n"
.size .L.str.13, 47
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Failed to allocate device y (error code %s)!\n"
.size .L.str.14, 47
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Failed to copy x from host to device (error code %s)!\n"
.size .L.str.15, 56
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Failed to copy y from host to device (error code %s)!\n"
.size .L.str.16, 56
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Print max_threads %d \n "
.size .L.str.17, 25
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n "
.size .L.str.18, 73
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Failed to launch saxpy kernel (error code %s)!\n"
.size .L.str.19, 48
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Failed to copy y from device to host (error code %s)!\n"
.size .L.str.21, 56
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Failed to free device x (error code %s)!\n"
.size .L.str.22, 43
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Failed to free device y (error code %s)!\n"
.size .L.str.23, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "N number is too large, please enter a smaller number"
.size .Lstr, 53
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aace2_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12random_floatPfi
.type _Z12random_floatPfi, @function
_Z12random_floatPfi:
.LFB2271:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2271:
.size _Z12random_floatPfi, .-_Z12random_floatPfi
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2297:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaGetDeviceCount: %d\n"
.LC2:
.string "There are %d CUDA devices.\n"
.LC3:
.string "Device Number: %d \n"
.LC4:
.string "Device name: %s \n "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Block dimensions: %d x %d x %d \n"
.align 8
.LC6:
.string "Maximum number of threads per block: %d\n"
.align 8
.LC7:
.string "Grid dimensions: %d x %d x %d \n"
.align 8
.LC8:
.string " Maximum number of thread blocks for x = %d \n"
.section .rodata.str1.1
.LC9:
.string "Please input an N value: "
.LC10:
.string "%d"
.LC11:
.string "Please input an A value: "
.LC12:
.string "%f"
.section .rodata.str1.8
.align 8
.LC13:
.string "Failed to allocate host x and y\n"
.align 8
.LC14:
.string "Failed to allocate device x (error code %s)!\n"
.align 8
.LC15:
.string "Failed to allocate device y (error code %s)!\n"
.align 8
.LC16:
.string "Failed to copy x from host to device (error code %s)!\n"
.align 8
.LC17:
.string "Failed to copy y from host to device (error code %s)!\n"
.section .rodata.str1.1
.LC18:
.string "Print max_threads %d \n "
.section .rodata.str1.8
.align 8
.LC19:
.string " saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n "
.align 8
.LC20:
.string "Failed to launch saxpy kernel (error code %s)!\n"
.align 8
.LC21:
.string "N number is too large, please enter a smaller number\n"
.align 8
.LC22:
.string "Failed to copy y from device to host (error code %s)!\n"
.align 8
.LC23:
.string "Failed to free device x (error code %s)!\n"
.align 8
.LC24:
.string "Failed to free device y (error code %s)!\n"
.text
.globl main
.type main, @function
main:
.LFB2272:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
leaq 36(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 36(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 36(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 36(%rsp)
jle .L37
movl $0, %ebx
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %r12
jmp .L22
.L21:
cltd
idivl %ebp
movl %eax, 12(%rsp)
movl %eax, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 36(%rsp)
jle .L20
.L22:
leaq 80(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 412(%rsp), %r8d
movl 408(%rsp), %ecx
movl 404(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 400(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 400(%rsp), %ebp
movl 424(%rsp), %r8d
movl 420(%rsp), %ecx
movl 416(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 416(%rsp), %edx
movl 420(%rsp), %eax
cmpl %edx, %eax
jg .L21
movl 424(%rsp), %eax
cmpl %eax, %edx
cmovge %edx, %eax
jmp .L21
.L37:
movl $0, 12(%rsp)
movl $0, %ebp
.L20:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
leaq .LC10(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rsi
leaq .LC12(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %r14d
movslq %r14d, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testq %r13, %r13
je .L38
testq %rax, %rax
je .L38
movl %r14d, %esi
movq %r13, %rdi
call _Z12random_floatPfi
movl 28(%rsp), %esi
movq %r12, %rdi
call _Z12random_floatPfi
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movq $0, 48(%rsp)
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L43
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L44
movl 28(%rsp), %r14d
movl 12(%rsp), %eax
imull %eax, %ebp
movl %ebp, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %eax
cmpl %eax, %ebp
jl .L29
leal 2046(%r14), %ebp
addl $1023, %r14d
cmovns %r14d, %ebp
sarl $10, %ebp
cltd
idivl %ebp
movl %eax, %r14d
testl %edx, %edx
je .L30
cmpl $1023, %eax
jle .L45
.L30:
movl 12(%rsp), %eax
cmpl %eax, %ebp
jle .L46
.L31:
movl $2, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L48
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L49
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
leal 1(%rax), %r14d
jmp .L30
.L46:
movl %r14d, %ecx
movl %ebp, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, 68(%rsp)
movl $1, 72(%rsp)
movl %ebp, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L32:
call cudaGetLastError@PLT
testl %eax, %eax
je .L31
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movss 32(%rsp), %xmm0
movl 28(%rsp), %edi
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
jmp .L32
.L29:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2272:
.size main, .-main
.section .rodata.str1.1
.LC25:
.string "_Z5saxpyifPfS_"
.LC26:
.string "precalc_xorwow_matrix"
.LC27:
.string "precalc_xorwow_offset_matrix"
.LC28:
.string "mrg32k3aM1"
.LC29:
.string "mrg32k3aM2"
.LC30:
.string "mrg32k3aM1SubSeq"
.LC31:
.string "mrg32k3aM2SubSeq"
.LC32:
.string "mrg32k3aM1Seq"
.LC33:
.string "mrg32k3aM2Seq"
.LC34:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2300:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC32(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC33(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC34(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12random_floatPfi
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z12random_floatPfi
.p2align 4, 0x90
.type _Z12random_floatPfi,@function
_Z12random_floatPfi: # @_Z12random_floatPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z12random_floatPfi, .Lfunc_end1-_Z12random_floatPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
xorl %r12d, %r12d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
movl $0, %ebp
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %r14d, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 436(%rsp), %esi
movl 440(%rsp), %edx
movl 444(%rsp), %ecx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 432(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 432(%rsp), %ebp
movl 448(%rsp), %esi
movl 452(%rsp), %edx
movl 456(%rsp), %ecx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 448(%rsp), %ecx
movl 456(%rsp), %eax
cmpl %eax, %ecx
cmovgl %ecx, %eax
movl 452(%rsp), %edx
cmpl %edx, %ecx
cmovll %edx, %eax
cltd
idivl %ebp
movl %eax, %r12d
movl $.L.str.7, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
incl %r14d
cmpl 4(%rsp), %r14d
jl .LBB2_2
.LBB2_3: # %._crit_edge
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq %rsp, %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
leaq 28(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq (%rsp), %r13
leaq (,%r13,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
testq %rbx, %rbx
je .LBB2_34
# %bb.4: # %._crit_edge
movq %rax, %r14
testq %rax, %rax
je .LBB2_34
# %bb.5:
movq %r15, 40(%rsp) # 8-byte Spill
movl %r13d, %r13d
testl %r13d, %r13d
jle .LBB2_8
# %bb.6: # %.lr.ph.preheader.i
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r13
jne .LBB2_7
.LBB2_8: # %_Z12random_floatPfi.exit
movl (%rsp), %r13d
testl %r13d, %r13d
jle .LBB2_11
# %bb.9: # %.lr.ph.preheader.i91
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_10: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %r13
jne .LBB2_10
.LBB2_11: # %_Z12random_floatPfi.exit97
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.14:
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_15
# %bb.16:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.18:
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.20:
movl (%rsp), %r13d
leal 1023(%r13), %eax
addl $2046, %r13d # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %r13d
imull %r12d, %ebp
movl $.L.str.17, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl (%rsp), %eax
cmpl %ebp, %eax
jle .LBB2_21
# %bb.26:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB2_27
.LBB2_21:
sarl $10, %r13d
cmpl %r12d, %r13d
jg .LBB2_27
# %bb.22:
cltd
idivl %r13d
testl %edx, %edx
setne %cl
cmpl $1024, %eax # imm = 0x400
setl %dl
andb %cl, %dl
movzbl %dl, %r12d
addl %eax, %r12d
movl $.L.str.18, %edi
movl %r13d, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %r12
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_24
# %bb.23:
movl (%rsp), %eax
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl %eax, 36(%rsp)
movss %xmm0, 32(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_24:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_25
.LBB2_27:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_28
# %bb.29:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_30
# %bb.31:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_32
# %bb.33:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_34:
.cfi_def_cfa_offset 1648
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $32, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB2_13
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %esi
jmp .LBB2_13
.LBB2_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
jmp .LBB2_13
.LBB2_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
jmp .LBB2_13
.LBB2_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
jmp .LBB2_13
.LBB2_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.22, %esi
jmp .LBB2_13
.LBB2_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.23, %esi
jmp .LBB2_13
.LBB2_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.19, %esi
.LBB2_13:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaGetDeviceCount: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "There are %d CUDA devices.\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device Number: %d \n"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device name: %s \n "
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Block dimensions: %d x %d x %d \n"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Maximum number of threads per block: %d\n"
.size .L.str.5, 41
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Grid dimensions: %d x %d x %d \n"
.size .L.str.6, 33
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Maximum number of thread blocks for x = %d \n"
.size .L.str.7, 47
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Please input an N value: "
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Please input an A value: "
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%f"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to allocate host x and y\n"
.size .L.str.12, 33
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to allocate device x (error code %s)!\n"
.size .L.str.13, 47
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Failed to allocate device y (error code %s)!\n"
.size .L.str.14, 47
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Failed to copy x from host to device (error code %s)!\n"
.size .L.str.15, 56
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Failed to copy y from host to device (error code %s)!\n"
.size .L.str.16, 56
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Print max_threads %d \n "
.size .L.str.17, 25
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " saxpy <<<number_of_blocks = %d , number_of_threads_per_block = %d >>>\n "
.size .L.str.18, 73
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Failed to launch saxpy kernel (error code %s)!\n"
.size .L.str.19, 48
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Failed to copy y from device to host (error code %s)!\n"
.size .L.str.21, 56
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Failed to free device x (error code %s)!\n"
.size .L.str.22, 43
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Failed to free device y (error code %s)!\n"
.size .L.str.23, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "N number is too large, please enter a smaller number"
.size .Lstr, 53
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // includes, system
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
__global__ void fillArray(int *data, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
data[idx] = idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
int *data_h;
int *data_d;
int i;
const int N = 100;
// allocate host and device memory
data_h = ( int* ) malloc(N * sizeof(int));
cudaMalloc(&data_d, N * sizeof(int));
//Fill the array
fillArray<<<N,1>>>( data_d, N );
//Make sure the device has finished
cudaThreadSynchronize();
//Copy the results to the host
cudaMemcpy(data_h, data_d, N*sizeof(int), cudaMemcpyDeviceToHost);
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data_h[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
free(data_h);
cudaFree(data_d);
return 0;
} | code for sm_80
Function : _Z9fillArrayPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // includes, system
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
__global__ void fillArray(int *data, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
data[idx] = idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
int *data_h;
int *data_d;
int i;
const int N = 100;
// allocate host and device memory
data_h = ( int* ) malloc(N * sizeof(int));
cudaMalloc(&data_d, N * sizeof(int));
//Fill the array
fillArray<<<N,1>>>( data_d, N );
//Make sure the device has finished
cudaThreadSynchronize();
//Copy the results to the host
cudaMemcpy(data_h, data_d, N*sizeof(int), cudaMemcpyDeviceToHost);
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data_h[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
free(data_h);
cudaFree(data_d);
return 0;
} | .file "tmpxft_00046751_00000000-6_integers_soln.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9fillArrayPiiPii
.type _Z29__device_stub__Z9fillArrayPiiPii, @function
_Z29__device_stub__Z9fillArrayPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9fillArrayPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z9fillArrayPiiPii, .-_Z29__device_stub__Z9fillArrayPiiPii
.globl _Z9fillArrayPii
.type _Z9fillArrayPii, @function
_Z9fillArrayPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9fillArrayPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9fillArrayPii, .-_Z9fillArrayPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $100, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $100, %eax
.L13:
subl $1, %eax
jne .L13
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9fillArrayPiiPii
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9fillArrayPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9fillArrayPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // includes, system
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
__global__ void fillArray(int *data, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
data[idx] = idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
int *data_h;
int *data_d;
int i;
const int N = 100;
// allocate host and device memory
data_h = ( int* ) malloc(N * sizeof(int));
cudaMalloc(&data_d, N * sizeof(int));
//Fill the array
fillArray<<<N,1>>>( data_d, N );
//Make sure the device has finished
cudaThreadSynchronize();
//Copy the results to the host
cudaMemcpy(data_h, data_d, N*sizeof(int), cudaMemcpyDeviceToHost);
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data_h[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
free(data_h);
cudaFree(data_d);
return 0;
} | // includes, system
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
__global__ void fillArray(int *data, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
data[idx] = idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
int *data_h;
int *data_d;
int i;
const int N = 100;
// allocate host and device memory
data_h = ( int* ) malloc(N * sizeof(int));
hipMalloc(&data_d, N * sizeof(int));
//Fill the array
fillArray<<<N,1>>>( data_d, N );
//Make sure the device has finished
hipDeviceSynchronize();
//Copy the results to the host
hipMemcpy(data_h, data_d, N*sizeof(int), hipMemcpyDeviceToHost);
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data_h[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
free(data_h);
hipFree(data_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // includes, system
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
__global__ void fillArray(int *data, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
data[idx] = idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
int *data_h;
int *data_d;
int i;
const int N = 100;
// allocate host and device memory
data_h = ( int* ) malloc(N * sizeof(int));
hipMalloc(&data_d, N * sizeof(int));
//Fill the array
fillArray<<<N,1>>>( data_d, N );
//Make sure the device has finished
hipDeviceSynchronize();
//Copy the results to the host
hipMemcpy(data_h, data_d, N*sizeof(int), hipMemcpyDeviceToHost);
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data_h[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
free(data_h);
hipFree(data_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9fillArrayPii
.globl _Z9fillArrayPii
.p2align 8
.type _Z9fillArrayPii,@function
_Z9fillArrayPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9fillArrayPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9fillArrayPii, .Lfunc_end0-_Z9fillArrayPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9fillArrayPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9fillArrayPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // includes, system
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
__global__ void fillArray(int *data, int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
data[idx] = idx;
}
/////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
int *data_h;
int *data_d;
int i;
const int N = 100;
// allocate host and device memory
data_h = ( int* ) malloc(N * sizeof(int));
hipMalloc(&data_d, N * sizeof(int));
//Fill the array
fillArray<<<N,1>>>( data_d, N );
//Make sure the device has finished
hipDeviceSynchronize();
//Copy the results to the host
hipMemcpy(data_h, data_d, N*sizeof(int), hipMemcpyDeviceToHost);
// verify the data is correct
for (i = 0; i < N; i++)
{
assert(data_h[i] == i );
}
// If the program makes it this far, then the results are
// correct and there are no run-time errors. Good work!
printf("Correct!\n");
free(data_h);
hipFree(data_d);
return 0;
} | .text
.file "integers_soln.hip"
.globl _Z24__device_stub__fillArrayPii # -- Begin function _Z24__device_stub__fillArrayPii
.p2align 4, 0x90
.type _Z24__device_stub__fillArrayPii,@function
_Z24__device_stub__fillArrayPii: # @_Z24__device_stub__fillArrayPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9fillArrayPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__fillArrayPii, .Lfunc_end0-_Z24__device_stub__fillArrayPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 99(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $100, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9fillArrayPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9fillArrayPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9fillArrayPii,@object # @_Z9fillArrayPii
.section .rodata,"a",@progbits
.globl _Z9fillArrayPii
.p2align 3, 0x0
_Z9fillArrayPii:
.quad _Z24__device_stub__fillArrayPii
.size _Z9fillArrayPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9fillArrayPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__fillArrayPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9fillArrayPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9fillArrayPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9fillArrayPii
.globl _Z9fillArrayPii
.p2align 8
.type _Z9fillArrayPii,@function
_Z9fillArrayPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9fillArrayPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9fillArrayPii, .Lfunc_end0-_Z9fillArrayPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9fillArrayPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9fillArrayPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00046751_00000000-6_integers_soln.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9fillArrayPiiPii
.type _Z29__device_stub__Z9fillArrayPiiPii, @function
_Z29__device_stub__Z9fillArrayPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9fillArrayPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z9fillArrayPiiPii, .-_Z29__device_stub__Z9fillArrayPiiPii
.globl _Z9fillArrayPii
.type _Z9fillArrayPii, @function
_Z9fillArrayPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9fillArrayPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9fillArrayPii, .-_Z9fillArrayPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $100, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $100, %eax
.L13:
subl $1, %eax
jne .L13
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9fillArrayPiiPii
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9fillArrayPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9fillArrayPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "integers_soln.hip"
.globl _Z24__device_stub__fillArrayPii # -- Begin function _Z24__device_stub__fillArrayPii
.p2align 4, 0x90
.type _Z24__device_stub__fillArrayPii,@function
_Z24__device_stub__fillArrayPii: # @_Z24__device_stub__fillArrayPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9fillArrayPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__fillArrayPii, .Lfunc_end0-_Z24__device_stub__fillArrayPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 99(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $100, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9fillArrayPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9fillArrayPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9fillArrayPii,@object # @_Z9fillArrayPii
.section .rodata,"a",@progbits
.globl _Z9fillArrayPii
.p2align 3, 0x0
_Z9fillArrayPii:
.quad _Z24__device_stub__fillArrayPii
.size _Z9fillArrayPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9fillArrayPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__fillArrayPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9fillArrayPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE 1024
#define ALING 64
__device__ double distance( double* dx, double* dy, double* dz,
const double Ax, const double Ay, const double Az,
const double Bx, const double By, const double Bz){
double x = Ax - Bx;
double y = Ay - By;
double z = Az - Bz;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k ( double *px, double *py, double *pz,
double *fx, double *fy, double *fz, double dt){
extern __shared__ double buff[];
double *sub_px = &buff[0],
*sub_py = &buff[gridDim.x],
*sub_pz = &buff[gridDim.x * 2];
int i = blockDim.x * blockIdx.x + threadIdx.x;
double pX = px[i];
double pY = py[i];
double pZ = pz[i];
double fX = fx[i];
double fY = fy[i];
double fZ = fz[i];
for (int blk = 0; blk < gridDim.x; blk++){
sub_px[threadIdx.x] = px[ blockDim.x * blk + threadIdx.x];
sub_py[threadIdx.x] = py[ blockDim.x * blk + threadIdx.x];
sub_pz[threadIdx.x] = pz[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, pX, pY, pZ, sub_px[j], sub_py[j], sub_pz[j]);
fX += dx * d;
fY += dy * d;
fZ += dz * d;
}
__syncthreads();
}
fx[i] = fX;
fy[i] = fY;
fz[i] = fZ;
}
__global__ void particleParticleVelocityPosition_k ( double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
vx[i] += dt * fx[i];
vy[i] += dt * fy[i];
vz[i] += dt * fz[i];
px[i] += dt * vx[i];
py[i] += dt * vy[i];
pz[i] += dt * vz[i];
}
void particleParticle (double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz,
int nParticles, int timesteps, double dt){
int threads = BLOCK_SIZE,
blocks = nParticles / BLOCK_SIZE;
if (nParticles < 1024){
blocks = 1;
threads = nParticles;
}
fprintf(stdout, "\n B(%d) T(%d) shared memory %d \n", blocks, threads, 3 * threads * sizeof(double));
for (int t = 0; t < timesteps; t++){
particleParticleForces_k<<<blocks, threads, 3 * threads * sizeof(double) >>>(px, py, pz, fx, fy, fz, dt);
particleParticleVelocityPosition_k<<<blocks, threads >>>(px, py, pz, vx, vy, vz, fx, fy, fz, dt);
assert( cudaDeviceSynchronize() == cudaSuccess);
}//end-for (int t = 0; t < timesteps; t++){
}//end-void particleParticle
//-----------------------------------------------------------------------------------------------------
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep);
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles);
//-----------------------------------------------------------------------------------------------------
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f,
*h_px = NULL, *h_py = NULL, *h_pz = NULL,
*h_vx = NULL, *h_vy = NULL, *h_vz = NULL,
*h_fx = NULL, *h_fy = NULL, *h_fz = NULL,
*d_px = NULL, *d_py = NULL, *d_pz = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL,
*d_fx = NULL, *d_fy = NULL, *d_fz = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(double) * 9);
h_px = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_px != NULL);
h_py = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_py != NULL);
h_pz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_pz != NULL);
//-------------------------
h_vx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vx != NULL);
h_vy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vy != NULL);
h_vz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vz != NULL);
//-------------------------
h_fx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fx != NULL);
h_fy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fy != NULL);
h_fz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fz != NULL);
//-------------------------
initialCondition(h_px, h_py, h_pz,
h_vx, h_vy, h_vz,
h_fx, h_fy, h_fz, nParticles);
assert(cudaMalloc((void**) &d_px, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_px, h_px, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_py, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_py, h_py, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_pz, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_pz, h_pz, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
//-----
assert(cudaMalloc((void**) &d_vx, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_vx, h_vx, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_vy, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_vy, h_vy, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_vz, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_vz, h_vz, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
//-----
assert(cudaMalloc((void**) &d_fx, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_fx, h_fx, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_fy, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_fy, h_fy, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_fz, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_fz, h_fz, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
particleParticle(d_px, d_py, d_pz, d_vx, d_vy, d_vz, d_fx, d_fy, d_fz, nParticles, timesteps, dt);
assert(cudaMemcpy(h_px, d_px, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_py, d_py, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_pz, d_pz, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_vx, d_vx, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_vy, d_vy, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_vz, d_vz, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_fx, d_fx, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_fy, d_fy, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_fz, d_fz, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
// printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
if (flagSave == 1)
printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
free(h_px);free(h_py); free(h_pz);
free(h_vx);free(h_vy); free(h_vz);
free(h_fx);free(h_fy); free(h_fz);
cudaFree(d_px);cudaFree(d_py); cudaFree(d_pz);
cudaFree(d_vx);cudaFree(d_vy); cudaFree(d_vz);
cudaFree(d_fx);cudaFree(d_fy); cudaFree(d_fz);
}
/*Declarando as structs de particula e forca*/
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "w+");
for(int i = 0; i < nParticles; i++){
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, px[i], py[i], pz[i], vx[i], vy[i], vz[i], fx[i], fy[i], fz[i]);
}
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles){
srand(42);
memset(vx, 0x00, nParticles * sizeof(double));
memset(vy, 0x00, nParticles * sizeof(double));
memset(vz, 0x00, nParticles * sizeof(double));
memset(fx, 0x00, nParticles * sizeof(double));
memset(fy, 0x00, nParticles * sizeof(double));
memset(fz, 0x00, nParticles * sizeof(double));
for (int i = 0; i < nParticles ; i++){
px[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
py[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
pz[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}//end-for (int i = 0; i < nParticles ; i++){
} | .file "tmpxft_000efef2_00000000-6_main-n-bodies-2.0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distancePdS_S_dddddd
.type _Z8distancePdS_S_dddddd, @function
_Z8distancePdS_S_dddddd:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8distancePdS_S_dddddd, .-_Z8distancePdS_S_dddddd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/marzam/HPC-Aula/main/exemplos/problems-profile/nbody-cuda-profile/main-n-bodies-2.0.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s-%d-log.bin"
.LC2:
.string "Saving file [%s] "
.LC3:
.string "w+"
.section .rodata.str1.8
.align 8
.LC4:
.string "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n"
.section .rodata.str1.1
.LC5:
.string "[OK]\n"
.text
.globl _Z8printLogPdS_S_S_S_S_S_S_S_ii
.type _Z8printLogPdS_S_S_S_S_S_S_S_ii, @function
_Z8printLogPdS_S_S_S_S_S_S_S_ii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 256(%rsp), %r15
movq 264(%rsp), %rbp
movq 272(%rsp), %r14
movl 280(%rsp), %r12d
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbx
movl 288(%rsp), %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rcx
movl $128, %edx
movl $2, %esi
movq %rbx, %rdi
call __sprintf_chk@PLT
movq %rbx, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, (%rsp)
testl %r12d, %r12d
jle .L6
movslq %r12d, %r12
movl $0, %ebx
.L7:
movsd 0(%r13,%rbx,8), %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 264
pushq (%r14,%rbx,8)
.cfi_def_cfa_offset 272
movsd 0(%rbp,%rbx,8), %xmm7
movsd (%r15,%rbx,8), %xmm6
movq 56(%rsp), %rax
movsd (%rax,%rbx,8), %xmm5
movq 48(%rsp), %rax
movsd (%rax,%rbx,8), %xmm4
movq 40(%rsp), %rax
movsd (%rax,%rbx,8), %xmm3
movq 32(%rsp), %rax
movsd (%rax,%rbx,8), %xmm2
movq 24(%rsp), %rax
movsd (%rax,%rbx,8), %xmm1
movl %ebx, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq 16(%rsp), %rdi
movl $8, %eax
call __fprintf_chk@PLT
addq $1, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 256
cmpq %r12, %rbx
jne .L7
.L6:
movq (%rsp), %rdi
call fclose@PLT
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8printLogPdS_S_S_S_S_S_S_S_ii, .-_Z8printLogPdS_S_S_S_S_S_S_S_ii
.globl _Z16initialConditionPdS_S_S_S_S_S_S_S_i
.type _Z16initialConditionPdS_S_S_S_S_S_S_S_i, @function
_Z16initialConditionPdS_S_S_S_S_S_S_S_i:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %r15
movq %r8, %r14
movq %r9, 8(%rsp)
movl $42, %edi
call srand@PLT
movslq 104(%rsp), %rbx
salq $3, %rbx
movq %rbx, %rdx
movl $0, %esi
movq %r15, %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq %r14, %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 80(%rsp), %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 96(%rsp), %rdi
call memset@PLT
cmpl $0, 104(%rsp)
jle .L12
movl $0, %r14d
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, 0(%rbp,%r14)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, (%r12,%r14)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, 0(%r13,%r14)
addq $8, %r14
cmpq %r14, %rbx
jne .L14
.L12:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z16initialConditionPdS_S_S_S_S_S_S_S_i, .-_Z16initialConditionPdS_S_S_S_S_S_S_S_i
.globl _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d
.type _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d, @function
_Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d:
.LFB2086:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24particleParticleForces_kPdS_S_S_S_S_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d, .-_Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d
.globl _Z24particleParticleForces_kPdS_S_S_S_S_d
.type _Z24particleParticleForces_kPdS_S_S_S_S_d, @function
_Z24particleParticleForces_kPdS_S_S_S_S_d:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z24particleParticleForces_kPdS_S_S_S_S_d, .-_Z24particleParticleForces_kPdS_S_S_S_S_d
.globl _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d
.type _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d, @function
_Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d:
.LFB2088:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movsd %xmm0, (%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movq %rsp, %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d, .-_Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d
.globl _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.type _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, @function
_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d:
.LFB2089:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, .-_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.section .rodata.str1.8
.align 8
.LC8:
.string "\n B(%d) T(%d) shared memory %d \n"
.text
.globl _Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.type _Z16particleParticlePdS_S_S_S_S_S_S_S_iid, @function
_Z16particleParticlePdS_S_S_S_S_S_S_S_iid:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, %r15
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movl 168(%rsp), %ebp
movl 176(%rsp), %r14d
movsd %xmm0, 16(%rsp)
movl $1, %r12d
cmpl $1023, %ebp
jle .L34
leal 1023(%rbp), %r12d
testl %ebp, %ebp
cmovns %ebp, %r12d
sarl $10, %r12d
movl $1024, %ebp
.L34:
leal 0(%rbp,%rbp,2), %r13d
movslq %r13d, %r13
salq $3, %r13
movq %r13, %r9
movl %ebp, %r8d
movl %r12d, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testl %r14d, %r14d
jle .L33
movl $0, %ebx
jmp .L38
.L42:
movsd 16(%rsp), %xmm0
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d
jmp .L36
.L37:
addl $1, %ebx
cmpl %ebx, %r14d
je .L33
.L38:
movl %ebp, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r12d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movq %r13, %r8
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L36:
movl %ebp, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r12d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq 168(%rsp)
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
movsd 48(%rsp), %xmm0
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movq 56(%rsp), %rcx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d
addq $32, %rsp
.cfi_def_cfa_offset 144
jmp .L37
.L33:
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z16particleParticlePdS_S_S_S_S_S_S_S_iid, .-_Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.section .rodata.str1.8
.align 8
.LC9:
.string "\nParcile system particle to particle \n"
.section .rodata.str1.1
.LC10:
.string "Memory used %lu bytes \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 40(%rsp)
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq %ebp, %rcx
leaq 0(,%rcx,8), %rbx
addq %rbx, %rcx
salq $3, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r15
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r14
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, (%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 24(%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r13
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r12
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %rbx
pushq %rbp
.cfi_def_cfa_offset 120
pushq %rax
.cfi_def_cfa_offset 128
pushq %r12
.cfi_def_cfa_offset 136
pushq %r13
.cfi_def_cfa_offset 144
movq 56(%rsp), %r9
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %r14, %rsi
movq %r15, %rdi
call _Z16initialConditionPdS_S_S_S_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 120
movl 40(%rsp), %ecx
pushq %rcx
.cfi_def_cfa_offset 128
pushq %rbp
.cfi_def_cfa_offset 136
pushq $0
.cfi_def_cfa_offset 144
pushq $0
.cfi_def_cfa_offset 152
pushq $0
.cfi_def_cfa_offset 160
movsd .LC11(%rip), %xmm0
movl $0, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z16particleParticlePdS_S_S_S_S_S_S_S_iid
addq $48, %rsp
.cfi_def_cfa_offset 112
cmpl $1, 40(%rsp)
je .L46
.L44:
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 120
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
pushq %rbp
.cfi_def_cfa_offset 136
pushq %rbx
.cfi_def_cfa_offset 144
pushq %r12
.cfi_def_cfa_offset 152
pushq %r13
.cfi_def_cfa_offset 160
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %r14, %rsi
movq %r15, %rdi
call _Z8printLogPdS_S_S_S_S_S_S_S_ii
addq $48, %rsp
.cfi_def_cfa_offset 112
jmp .L44
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d"
.align 8
.LC13:
.string "_Z24particleParticleForces_kPdS_S_S_S_S_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z24particleParticleForces_kPdS_S_S_S_S_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -4194304
.long 1105199103
.align 8
.LC7:
.long 0
.long 1072693248
.align 8
.LC11:
.long -2147483648
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE 1024
#define ALING 64
__device__ double distance( double* dx, double* dy, double* dz,
const double Ax, const double Ay, const double Az,
const double Bx, const double By, const double Bz){
double x = Ax - Bx;
double y = Ay - By;
double z = Az - Bz;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k ( double *px, double *py, double *pz,
double *fx, double *fy, double *fz, double dt){
extern __shared__ double buff[];
double *sub_px = &buff[0],
*sub_py = &buff[gridDim.x],
*sub_pz = &buff[gridDim.x * 2];
int i = blockDim.x * blockIdx.x + threadIdx.x;
double pX = px[i];
double pY = py[i];
double pZ = pz[i];
double fX = fx[i];
double fY = fy[i];
double fZ = fz[i];
for (int blk = 0; blk < gridDim.x; blk++){
sub_px[threadIdx.x] = px[ blockDim.x * blk + threadIdx.x];
sub_py[threadIdx.x] = py[ blockDim.x * blk + threadIdx.x];
sub_pz[threadIdx.x] = pz[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, pX, pY, pZ, sub_px[j], sub_py[j], sub_pz[j]);
fX += dx * d;
fY += dy * d;
fZ += dz * d;
}
__syncthreads();
}
fx[i] = fX;
fy[i] = fY;
fz[i] = fZ;
}
__global__ void particleParticleVelocityPosition_k ( double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
vx[i] += dt * fx[i];
vy[i] += dt * fy[i];
vz[i] += dt * fz[i];
px[i] += dt * vx[i];
py[i] += dt * vy[i];
pz[i] += dt * vz[i];
}
void particleParticle (double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz,
int nParticles, int timesteps, double dt){
int threads = BLOCK_SIZE,
blocks = nParticles / BLOCK_SIZE;
if (nParticles < 1024){
blocks = 1;
threads = nParticles;
}
fprintf(stdout, "\n B(%d) T(%d) shared memory %d \n", blocks, threads, 3 * threads * sizeof(double));
for (int t = 0; t < timesteps; t++){
particleParticleForces_k<<<blocks, threads, 3 * threads * sizeof(double) >>>(px, py, pz, fx, fy, fz, dt);
particleParticleVelocityPosition_k<<<blocks, threads >>>(px, py, pz, vx, vy, vz, fx, fy, fz, dt);
assert( cudaDeviceSynchronize() == cudaSuccess);
}//end-for (int t = 0; t < timesteps; t++){
}//end-void particleParticle
//-----------------------------------------------------------------------------------------------------
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep);
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles);
//-----------------------------------------------------------------------------------------------------
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f,
*h_px = NULL, *h_py = NULL, *h_pz = NULL,
*h_vx = NULL, *h_vy = NULL, *h_vz = NULL,
*h_fx = NULL, *h_fy = NULL, *h_fz = NULL,
*d_px = NULL, *d_py = NULL, *d_pz = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL,
*d_fx = NULL, *d_fy = NULL, *d_fz = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(double) * 9);
h_px = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_px != NULL);
h_py = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_py != NULL);
h_pz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_pz != NULL);
//-------------------------
h_vx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vx != NULL);
h_vy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vy != NULL);
h_vz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vz != NULL);
//-------------------------
h_fx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fx != NULL);
h_fy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fy != NULL);
h_fz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fz != NULL);
//-------------------------
initialCondition(h_px, h_py, h_pz,
h_vx, h_vy, h_vz,
h_fx, h_fy, h_fz, nParticles);
assert(cudaMalloc((void**) &d_px, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_px, h_px, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_py, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_py, h_py, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_pz, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_pz, h_pz, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
//-----
assert(cudaMalloc((void**) &d_vx, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_vx, h_vx, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_vy, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_vy, h_vy, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_vz, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_vz, h_vz, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
//-----
assert(cudaMalloc((void**) &d_fx, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_fx, h_fx, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_fy, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_fy, h_fy, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMalloc((void**) &d_fz, nParticles * sizeof(double)) == cudaSuccess);
assert(cudaMemcpy(d_fz, h_fz, nParticles * sizeof(double), cudaMemcpyHostToDevice) == cudaSuccess);
particleParticle(d_px, d_py, d_pz, d_vx, d_vy, d_vz, d_fx, d_fy, d_fz, nParticles, timesteps, dt);
assert(cudaMemcpy(h_px, d_px, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_py, d_py, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_pz, d_pz, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_vx, d_vx, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_vy, d_vy, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_vz, d_vz, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_fx, d_fx, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_fy, d_fy, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
assert(cudaMemcpy(h_fz, d_fz, nParticles * sizeof(double), cudaMemcpyDeviceToHost) == cudaSuccess);
// printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
if (flagSave == 1)
printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
free(h_px);free(h_py); free(h_pz);
free(h_vx);free(h_vy); free(h_vz);
free(h_fx);free(h_fy); free(h_fz);
cudaFree(d_px);cudaFree(d_py); cudaFree(d_pz);
cudaFree(d_vx);cudaFree(d_vy); cudaFree(d_vz);
cudaFree(d_fx);cudaFree(d_fy); cudaFree(d_fz);
}
/*Declarando as structs de particula e forca*/
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "w+");
for(int i = 0; i < nParticles; i++){
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, px[i], py[i], pz[i], vx[i], vy[i], vz[i], fx[i], fy[i], fz[i]);
}
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles){
srand(42);
memset(vx, 0x00, nParticles * sizeof(double));
memset(vy, 0x00, nParticles * sizeof(double));
memset(vz, 0x00, nParticles * sizeof(double));
memset(fx, 0x00, nParticles * sizeof(double));
memset(fy, 0x00, nParticles * sizeof(double));
memset(fz, 0x00, nParticles * sizeof(double));
for (int i = 0; i < nParticles ; i++){
px[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
py[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
pz[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}//end-for (int i = 0; i < nParticles ; i++){
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE 1024
#define ALING 64
__device__ double distance( double* dx, double* dy, double* dz,
const double Ax, const double Ay, const double Az,
const double Bx, const double By, const double Bz){
double x = Ax - Bx;
double y = Ay - By;
double z = Az - Bz;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k ( double *px, double *py, double *pz,
double *fx, double *fy, double *fz, double dt){
extern __shared__ double buff[];
double *sub_px = &buff[0],
*sub_py = &buff[gridDim.x],
*sub_pz = &buff[gridDim.x * 2];
int i = blockDim.x * blockIdx.x + threadIdx.x;
double pX = px[i];
double pY = py[i];
double pZ = pz[i];
double fX = fx[i];
double fY = fy[i];
double fZ = fz[i];
for (int blk = 0; blk < gridDim.x; blk++){
sub_px[threadIdx.x] = px[ blockDim.x * blk + threadIdx.x];
sub_py[threadIdx.x] = py[ blockDim.x * blk + threadIdx.x];
sub_pz[threadIdx.x] = pz[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, pX, pY, pZ, sub_px[j], sub_py[j], sub_pz[j]);
fX += dx * d;
fY += dy * d;
fZ += dz * d;
}
__syncthreads();
}
fx[i] = fX;
fy[i] = fY;
fz[i] = fZ;
}
__global__ void particleParticleVelocityPosition_k ( double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
vx[i] += dt * fx[i];
vy[i] += dt * fy[i];
vz[i] += dt * fz[i];
px[i] += dt * vx[i];
py[i] += dt * vy[i];
pz[i] += dt * vz[i];
}
void particleParticle (double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz,
int nParticles, int timesteps, double dt){
int threads = BLOCK_SIZE,
blocks = nParticles / BLOCK_SIZE;
if (nParticles < 1024){
blocks = 1;
threads = nParticles;
}
fprintf(stdout, "\n B(%d) T(%d) shared memory %d \n", blocks, threads, 3 * threads * sizeof(double));
for (int t = 0; t < timesteps; t++){
particleParticleForces_k<<<blocks, threads, 3 * threads * sizeof(double) >>>(px, py, pz, fx, fy, fz, dt);
particleParticleVelocityPosition_k<<<blocks, threads >>>(px, py, pz, vx, vy, vz, fx, fy, fz, dt);
assert( hipDeviceSynchronize() == hipSuccess);
}//end-for (int t = 0; t < timesteps; t++){
}//end-void particleParticle
//-----------------------------------------------------------------------------------------------------
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep);
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles);
//-----------------------------------------------------------------------------------------------------
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f,
*h_px = NULL, *h_py = NULL, *h_pz = NULL,
*h_vx = NULL, *h_vy = NULL, *h_vz = NULL,
*h_fx = NULL, *h_fy = NULL, *h_fz = NULL,
*d_px = NULL, *d_py = NULL, *d_pz = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL,
*d_fx = NULL, *d_fy = NULL, *d_fz = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(double) * 9);
h_px = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_px != NULL);
h_py = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_py != NULL);
h_pz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_pz != NULL);
//-------------------------
h_vx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vx != NULL);
h_vy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vy != NULL);
h_vz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vz != NULL);
//-------------------------
h_fx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fx != NULL);
h_fy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fy != NULL);
h_fz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fz != NULL);
//-------------------------
initialCondition(h_px, h_py, h_pz,
h_vx, h_vy, h_vz,
h_fx, h_fy, h_fz, nParticles);
assert(hipMalloc((void**) &d_px, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_px, h_px, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_py, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_py, h_py, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_pz, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_pz, h_pz, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
//-----
assert(hipMalloc((void**) &d_vx, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_vx, h_vx, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_vy, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_vy, h_vy, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_vz, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_vz, h_vz, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
//-----
assert(hipMalloc((void**) &d_fx, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_fx, h_fx, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_fy, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_fy, h_fy, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_fz, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_fz, h_fz, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
particleParticle(d_px, d_py, d_pz, d_vx, d_vy, d_vz, d_fx, d_fy, d_fz, nParticles, timesteps, dt);
assert(hipMemcpy(h_px, d_px, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_py, d_py, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_pz, d_pz, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_vx, d_vx, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_vy, d_vy, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_vz, d_vz, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_fx, d_fx, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_fy, d_fy, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_fz, d_fz, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
// printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
if (flagSave == 1)
printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
free(h_px);free(h_py); free(h_pz);
free(h_vx);free(h_vy); free(h_vz);
free(h_fx);free(h_fy); free(h_fz);
hipFree(d_px);hipFree(d_py); hipFree(d_pz);
hipFree(d_vx);hipFree(d_vy); hipFree(d_vz);
hipFree(d_fx);hipFree(d_fy); hipFree(d_fz);
}
/*Declarando as structs de particula e forca*/
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "w+");
for(int i = 0; i < nParticles; i++){
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, px[i], py[i], pz[i], vx[i], vy[i], vz[i], fx[i], fy[i], fz[i]);
}
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles){
srand(42);
memset(vx, 0x00, nParticles * sizeof(double));
memset(vy, 0x00, nParticles * sizeof(double));
memset(vz, 0x00, nParticles * sizeof(double));
memset(fx, 0x00, nParticles * sizeof(double));
memset(fy, 0x00, nParticles * sizeof(double));
memset(fz, 0x00, nParticles * sizeof(double));
for (int i = 0; i < nParticles ; i++){
px[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
py[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
pz[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}//end-for (int i = 0; i < nParticles ; i++){
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE 1024
#define ALING 64
__device__ double distance( double* dx, double* dy, double* dz,
const double Ax, const double Ay, const double Az,
const double Bx, const double By, const double Bz){
double x = Ax - Bx;
double y = Ay - By;
double z = Az - Bz;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k ( double *px, double *py, double *pz,
double *fx, double *fy, double *fz, double dt){
extern __shared__ double buff[];
double *sub_px = &buff[0],
*sub_py = &buff[gridDim.x],
*sub_pz = &buff[gridDim.x * 2];
int i = blockDim.x * blockIdx.x + threadIdx.x;
double pX = px[i];
double pY = py[i];
double pZ = pz[i];
double fX = fx[i];
double fY = fy[i];
double fZ = fz[i];
for (int blk = 0; blk < gridDim.x; blk++){
sub_px[threadIdx.x] = px[ blockDim.x * blk + threadIdx.x];
sub_py[threadIdx.x] = py[ blockDim.x * blk + threadIdx.x];
sub_pz[threadIdx.x] = pz[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, pX, pY, pZ, sub_px[j], sub_py[j], sub_pz[j]);
fX += dx * d;
fY += dy * d;
fZ += dz * d;
}
__syncthreads();
}
fx[i] = fX;
fy[i] = fY;
fz[i] = fZ;
}
__global__ void particleParticleVelocityPosition_k ( double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
vx[i] += dt * fx[i];
vy[i] += dt * fy[i];
vz[i] += dt * fz[i];
px[i] += dt * vx[i];
py[i] += dt * vy[i];
pz[i] += dt * vz[i];
}
void particleParticle (double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz,
int nParticles, int timesteps, double dt){
int threads = BLOCK_SIZE,
blocks = nParticles / BLOCK_SIZE;
if (nParticles < 1024){
blocks = 1;
threads = nParticles;
}
fprintf(stdout, "\n B(%d) T(%d) shared memory %d \n", blocks, threads, 3 * threads * sizeof(double));
for (int t = 0; t < timesteps; t++){
particleParticleForces_k<<<blocks, threads, 3 * threads * sizeof(double) >>>(px, py, pz, fx, fy, fz, dt);
particleParticleVelocityPosition_k<<<blocks, threads >>>(px, py, pz, vx, vy, vz, fx, fy, fz, dt);
assert( hipDeviceSynchronize() == hipSuccess);
}//end-for (int t = 0; t < timesteps; t++){
}//end-void particleParticle
//-----------------------------------------------------------------------------------------------------
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep);
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles);
//-----------------------------------------------------------------------------------------------------
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f,
*h_px = NULL, *h_py = NULL, *h_pz = NULL,
*h_vx = NULL, *h_vy = NULL, *h_vz = NULL,
*h_fx = NULL, *h_fy = NULL, *h_fz = NULL,
*d_px = NULL, *d_py = NULL, *d_pz = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL,
*d_fx = NULL, *d_fy = NULL, *d_fz = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(double) * 9);
h_px = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_px != NULL);
h_py = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_py != NULL);
h_pz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_pz != NULL);
//-------------------------
h_vx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vx != NULL);
h_vy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vy != NULL);
h_vz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vz != NULL);
//-------------------------
h_fx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fx != NULL);
h_fy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fy != NULL);
h_fz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fz != NULL);
//-------------------------
initialCondition(h_px, h_py, h_pz,
h_vx, h_vy, h_vz,
h_fx, h_fy, h_fz, nParticles);
assert(hipMalloc((void**) &d_px, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_px, h_px, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_py, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_py, h_py, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_pz, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_pz, h_pz, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
//-----
assert(hipMalloc((void**) &d_vx, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_vx, h_vx, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_vy, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_vy, h_vy, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_vz, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_vz, h_vz, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
//-----
assert(hipMalloc((void**) &d_fx, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_fx, h_fx, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_fy, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_fy, h_fy, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_fz, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_fz, h_fz, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
particleParticle(d_px, d_py, d_pz, d_vx, d_vy, d_vz, d_fx, d_fy, d_fz, nParticles, timesteps, dt);
assert(hipMemcpy(h_px, d_px, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_py, d_py, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_pz, d_pz, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_vx, d_vx, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_vy, d_vy, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_vz, d_vz, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_fx, d_fx, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_fy, d_fy, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_fz, d_fz, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
// printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
if (flagSave == 1)
printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
free(h_px);free(h_py); free(h_pz);
free(h_vx);free(h_vy); free(h_vz);
free(h_fx);free(h_fy); free(h_fz);
hipFree(d_px);hipFree(d_py); hipFree(d_pz);
hipFree(d_vx);hipFree(d_vy); hipFree(d_vz);
hipFree(d_fx);hipFree(d_fy); hipFree(d_fz);
}
/*Declarando as structs de particula e forca*/
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "w+");
for(int i = 0; i < nParticles; i++){
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, px[i], py[i], pz[i], vx[i], vy[i], vz[i], fx[i], fy[i], fz[i]);
}
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles){
srand(42);
memset(vx, 0x00, nParticles * sizeof(double));
memset(vy, 0x00, nParticles * sizeof(double));
memset(vz, 0x00, nParticles * sizeof(double));
memset(fx, 0x00, nParticles * sizeof(double));
memset(fy, 0x00, nParticles * sizeof(double));
memset(fz, 0x00, nParticles * sizeof(double));
for (int i = 0; i < nParticles ; i++){
px[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
py[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
pz[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}//end-for (int i = 0; i < nParticles ; i++){
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24particleParticleForces_kPdS_S_S_S_S_d
.globl _Z24particleParticleForces_kPdS_S_S_S_S_d
.p2align 8
.type _Z24particleParticleForces_kPdS_S_S_S_S_d,@function
_Z24particleParticleForces_kPdS_S_S_S_S_d:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[4:7], s[0:1], 0x18
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x28
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[13:14], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v14, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v14, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v14, vcc_lo
global_load_b64 v[7:8], v[1:2], off
global_load_b64 v[9:10], v[3:4], off
global_load_b64 v[11:12], v[5:6], off
s_load_b32 s11, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s11, 0
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_lshl_b32 s1, s11, 3
s_lshl_b32 s13, s11, 4
s_cmp_lg_u32 s10, 0
v_dual_mov_b32 v22, 0 :: v_dual_lshlrev_b32 v21, 3, v0
s_cselect_b32 s0, -1, 0
s_mov_b32 s9, 0x3e112e0b
v_cndmask_b32_e64 v23, 0, 1, s0
s_mov_b32 s8, 0xe826d695
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v23
s_waitcnt lgkmcnt(0)
v_add_co_u32 v15, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v14, vcc_lo
v_add_co_u32 v17, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v14, vcc_lo
v_add_co_u32 v19, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v14, vcc_lo
global_load_b64 v[13:14], v[15:16], off
global_load_b64 v[15:16], v[17:18], off
global_load_b64 v[17:18], v[19:20], off
v_add_nc_u32_e32 v19, 0, v21
v_add3_u32 v20, 0, s1, v21
v_add3_u32 v21, 0, s13, v21
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_3:
v_mad_u64_u32 v[23:24], null, s12, s10, v[0:1]
v_mov_b32_e32 v24, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[23:24], 3, v[23:24]
v_add_co_u32 v25, vcc_lo, s4, v23
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v26, vcc_lo, s5, v24, vcc_lo
v_add_co_u32 v27, vcc_lo, s6, v23
v_add_co_ci_u32_e32 v28, vcc_lo, s7, v24, vcc_lo
v_add_co_u32 v23, vcc_lo, s2, v23
v_add_co_ci_u32_e32 v24, vcc_lo, s3, v24, vcc_lo
global_load_b64 v[25:26], v[25:26], off
global_load_b64 v[27:28], v[27:28], off
global_load_b64 v[23:24], v[23:24], off
s_and_b32 vcc_lo, exec_lo, s0
s_waitcnt vmcnt(2)
ds_store_b64 v19, v[25:26]
s_waitcnt vmcnt(1)
ds_store_b64 v20, v[27:28]
s_waitcnt vmcnt(0)
ds_store_b64 v21, v[23:24]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_2
s_mov_b32 s14, 0
s_mov_b32 s15, s10
.LBB0_5:
s_add_i32 s16, s14, s1
v_mov_b32_e32 v23, s14
v_mov_b32_e32 v25, s16
s_add_i32 s16, s14, s13
s_add_i32 s15, s15, -1
v_mov_b32_e32 v27, s16
ds_load_b64 v[23:24], v23
ds_load_b64 v[25:26], v25
s_add_i32 s14, s14, 8
s_cmp_eq_u32 s15, 0
ds_load_b64 v[27:28], v27
s_waitcnt lgkmcnt(2)
v_add_f64 v[23:24], v[13:14], -v[23:24]
s_waitcnt lgkmcnt(1)
v_add_f64 v[25:26], v[15:16], -v[25:26]
s_waitcnt lgkmcnt(0)
v_add_f64 v[27:28], v[17:18], -v[27:28]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[29:30], v[25:26], v[25:26]
v_fma_f64 v[29:30], v[23:24], v[23:24], v[29:30]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[29:30], v[27:28], v[27:28], v[29:30]
v_add_f64 v[29:30], v[29:30], s[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[29:30]
v_cndmask_b32_e64 v31, 0, 1, vcc_lo
v_lshlrev_b32_e32 v31, 8, v31
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[29:30], v[29:30], v31
v_rsq_f64_e32 v[31:32], v[29:30]
s_waitcnt_depctr 0xfff
v_mul_f64 v[33:34], v[29:30], v[31:32]
v_mul_f64 v[31:32], v[31:32], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[35:36], -v[31:32], v[33:34], 0.5
v_fma_f64 v[33:34], v[33:34], v[35:36], v[33:34]
v_fma_f64 v[31:32], v[31:32], v[35:36], v[31:32]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[35:36], -v[33:34], v[33:34], v[29:30]
v_fma_f64 v[33:34], v[35:36], v[31:32], v[33:34]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[35:36], -v[33:34], v[33:34], v[29:30]
v_fma_f64 v[31:32], v[35:36], v[31:32], v[33:34]
v_cndmask_b32_e64 v33, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[29:30], 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[31:32], v[31:32], v33
v_dual_cndmask_b32 v30, v32, v30 :: v_dual_cndmask_b32 v29, v31, v29
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[31:32], null, v[29:30], v[29:30], 1.0
v_div_scale_f64 v[37:38], vcc_lo, 1.0, v[29:30], 1.0
v_rcp_f64_e32 v[33:34], v[31:32]
s_waitcnt_depctr 0xfff
v_fma_f64 v[35:36], -v[31:32], v[33:34], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[33:34], v[33:34], v[35:36], v[33:34]
v_fma_f64 v[35:36], -v[31:32], v[33:34], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[33:34], v[33:34], v[35:36], v[33:34]
v_mul_f64 v[35:36], v[37:38], v[33:34]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[31:32], -v[31:32], v[35:36], v[37:38]
v_div_fmas_f64 v[31:32], v[31:32], v[33:34], v[35:36]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[29:30], v[31:32], v[29:30], 1.0
v_fma_f64 v[7:8], v[23:24], v[29:30], v[7:8]
v_fma_f64 v[9:10], v[25:26], v[29:30], v[9:10]
v_fma_f64 v[11:12], v[27:28], v[29:30], v[11:12]
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_waitcnt vmcnt(2)
global_store_b64 v[1:2], v[7:8], off
s_waitcnt vmcnt(1)
global_store_b64 v[3:4], v[9:10], off
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[11:12], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24particleParticleForces_kPdS_S_S_S_S_d
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 39
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24particleParticleForces_kPdS_S_S_S_S_d, .Lfunc_end0-_Z24particleParticleForces_kPdS_S_S_S_S_d
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.globl _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.p2align 8
.type _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d,@function
_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x5c
s_load_b256 s[16:23], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x40
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s20, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s21, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[6:7], v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[6:7]
v_add_co_u32 v6, vcc_lo, s22, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s23, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s16, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s17, v1, vcc_lo
global_store_b64 v[4:5], v[2:3], off
global_load_b64 v[2:3], v[6:7], off
global_load_b64 v[6:7], v[8:9], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[6:7]
v_add_co_u32 v6, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s19, v1, vcc_lo
global_store_b64 v[8:9], v[2:3], off
global_load_b64 v[2:3], v[6:7], off
global_load_b64 v[6:7], v[10:11], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_store_b64 v[10:11], v[2:3], off
global_load_b64 v[2:3], v[4:5], off
global_load_b64 v[4:5], v[6:7], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[4:5]
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b64 v[6:7], v[2:3], off
global_load_b64 v[2:3], v[8:9], off
global_load_b64 v[6:7], v[4:5], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[6:7]
global_store_b64 v[4:5], v[2:3], off
global_load_b64 v[2:3], v[10:11], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, .Lfunc_end1-_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
- .offset: 176
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24particleParticleForces_kPdS_S_S_S_S_d
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z24particleParticleForces_kPdS_S_S_S_S_d.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 39
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 8
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE 1024
#define ALING 64
__device__ double distance( double* dx, double* dy, double* dz,
const double Ax, const double Ay, const double Az,
const double Bx, const double By, const double Bz){
double x = Ax - Bx;
double y = Ay - By;
double z = Az - Bz;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k ( double *px, double *py, double *pz,
double *fx, double *fy, double *fz, double dt){
extern __shared__ double buff[];
double *sub_px = &buff[0],
*sub_py = &buff[gridDim.x],
*sub_pz = &buff[gridDim.x * 2];
int i = blockDim.x * blockIdx.x + threadIdx.x;
double pX = px[i];
double pY = py[i];
double pZ = pz[i];
double fX = fx[i];
double fY = fy[i];
double fZ = fz[i];
for (int blk = 0; blk < gridDim.x; blk++){
sub_px[threadIdx.x] = px[ blockDim.x * blk + threadIdx.x];
sub_py[threadIdx.x] = py[ blockDim.x * blk + threadIdx.x];
sub_pz[threadIdx.x] = pz[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, pX, pY, pZ, sub_px[j], sub_py[j], sub_pz[j]);
fX += dx * d;
fY += dy * d;
fZ += dz * d;
}
__syncthreads();
}
fx[i] = fX;
fy[i] = fY;
fz[i] = fZ;
}
__global__ void particleParticleVelocityPosition_k ( double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
vx[i] += dt * fx[i];
vy[i] += dt * fy[i];
vz[i] += dt * fz[i];
px[i] += dt * vx[i];
py[i] += dt * vy[i];
pz[i] += dt * vz[i];
}
void particleParticle (double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz,
int nParticles, int timesteps, double dt){
int threads = BLOCK_SIZE,
blocks = nParticles / BLOCK_SIZE;
if (nParticles < 1024){
blocks = 1;
threads = nParticles;
}
fprintf(stdout, "\n B(%d) T(%d) shared memory %d \n", blocks, threads, 3 * threads * sizeof(double));
for (int t = 0; t < timesteps; t++){
particleParticleForces_k<<<blocks, threads, 3 * threads * sizeof(double) >>>(px, py, pz, fx, fy, fz, dt);
particleParticleVelocityPosition_k<<<blocks, threads >>>(px, py, pz, vx, vy, vz, fx, fy, fz, dt);
assert( hipDeviceSynchronize() == hipSuccess);
}//end-for (int t = 0; t < timesteps; t++){
}//end-void particleParticle
//-----------------------------------------------------------------------------------------------------
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep);
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles);
//-----------------------------------------------------------------------------------------------------
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f,
*h_px = NULL, *h_py = NULL, *h_pz = NULL,
*h_vx = NULL, *h_vy = NULL, *h_vz = NULL,
*h_fx = NULL, *h_fy = NULL, *h_fz = NULL,
*d_px = NULL, *d_py = NULL, *d_pz = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL,
*d_fx = NULL, *d_fy = NULL, *d_fz = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(double) * 9);
h_px = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_px != NULL);
h_py = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_py != NULL);
h_pz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_pz != NULL);
//-------------------------
h_vx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vx != NULL);
h_vy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vy != NULL);
h_vz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_vz != NULL);
//-------------------------
h_fx = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fx != NULL);
h_fy = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fy != NULL);
h_fz = (double *) aligned_alloc(ALING, nParticles * sizeof(double));
assert(h_fz != NULL);
//-------------------------
initialCondition(h_px, h_py, h_pz,
h_vx, h_vy, h_vz,
h_fx, h_fy, h_fz, nParticles);
assert(hipMalloc((void**) &d_px, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_px, h_px, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_py, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_py, h_py, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_pz, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_pz, h_pz, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
//-----
assert(hipMalloc((void**) &d_vx, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_vx, h_vx, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_vy, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_vy, h_vy, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_vz, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_vz, h_vz, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
//-----
assert(hipMalloc((void**) &d_fx, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_fx, h_fx, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_fy, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_fy, h_fy, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
assert(hipMalloc((void**) &d_fz, nParticles * sizeof(double)) == hipSuccess);
assert(hipMemcpy(d_fz, h_fz, nParticles * sizeof(double), hipMemcpyHostToDevice) == hipSuccess);
particleParticle(d_px, d_py, d_pz, d_vx, d_vy, d_vz, d_fx, d_fy, d_fz, nParticles, timesteps, dt);
assert(hipMemcpy(h_px, d_px, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_py, d_py, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_pz, d_pz, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_vx, d_vx, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_vy, d_vy, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_vz, d_vz, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_fx, d_fx, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_fy, d_fy, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
assert(hipMemcpy(h_fz, d_fz, nParticles * sizeof(double), hipMemcpyDeviceToHost) == hipSuccess);
// printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
if (flagSave == 1)
printLog(h_px, h_py, h_pz, h_vx, h_vy, h_vz, h_fx, h_fy, h_fz, nParticles, timesteps);
free(h_px);free(h_py); free(h_pz);
free(h_vx);free(h_vy); free(h_vz);
free(h_fx);free(h_fy); free(h_fz);
hipFree(d_px);hipFree(d_py); hipFree(d_pz);
hipFree(d_vx);hipFree(d_vy); hipFree(d_vz);
hipFree(d_fx);hipFree(d_fy); hipFree(d_fz);
}
/*Declarando as structs de particula e forca*/
void printLog(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "w+");
for(int i = 0; i < nParticles; i++){
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, px[i], py[i], pz[i], vx[i], vy[i], vz[i], fx[i], fy[i], fz[i]);
}
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(double *px, double *py, double *pz,
double *vx, double *vy, double *vz,
double *fx, double *fy, double *fz, int nParticles){
srand(42);
memset(vx, 0x00, nParticles * sizeof(double));
memset(vy, 0x00, nParticles * sizeof(double));
memset(vz, 0x00, nParticles * sizeof(double));
memset(fx, 0x00, nParticles * sizeof(double));
memset(fy, 0x00, nParticles * sizeof(double));
memset(fz, 0x00, nParticles * sizeof(double));
for (int i = 0; i < nParticles ; i++){
px[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
py[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
pz[i] = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}//end-for (int i = 0; i < nParticles ; i++){
} | .text
.file "main-n-bodies-2.0.hip"
.globl _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d # -- Begin function _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.p2align 4, 0x90
.type _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d,@function
_Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d: # @_Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24particleParticleForces_kPdS_S_S_S_S_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d, .Lfunc_end0-_Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.cfi_endproc
# -- End function
.globl _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d # -- Begin function _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.p2align 4, 0x90
.type _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d,@function
_Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d: # @_Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end1:
.size _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, .Lfunc_end1-_Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.cfi_endproc
# -- End function
.globl _Z16particleParticlePdS_S_S_S_S_S_S_S_iid # -- Begin function _Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.p2align 4, 0x90
.type _Z16particleParticlePdS_S_S_S_S_S_S_S_iid,@function
_Z16particleParticlePdS_S_S_S_S_S_S_S_iid: # @_Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq %r9, 144(%rsp) # 8-byte Spill
movq %r8, 136(%rsp) # 8-byte Spill
movq %rcx, 128(%rsp) # 8-byte Spill
movq %rdx, 112(%rsp) # 8-byte Spill
movq %rsi, %r13
movq %rdi, %rbp
movl 352(%rsp), %r12d
movl 344(%rsp), %eax
movl $1, %r14d
cmpl $1024, %eax # imm = 0x400
jl .LBB2_2
# %bb.1: # %select.false.sink
leal 1023(%rax), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $10, %r14d
.LBB2_2: # %select.end
cmpl $1024, %eax # imm = 0x400
movl $1024, %r15d # imm = 0x400
cmovll %eax, %r15d
movq stdout(%rip), %rdi
leal (%r15,%r15,2), %eax
movslq %eax, %rbx
shlq $3, %rbx
movl $.L.str, %esi
movl %r14d, %edx
movl %r15d, %ecx
movq %rbx, %r8
xorl %eax, %eax
callq fprintf
testl %r12d, %r12d
jle .LBB2_9
# %bb.3: # %.lr.ph
movl %r14d, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movl %r15d, %r15d
orq %rax, %r15
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_4 Depth=1
decl %r12d
je .LBB2_9
.LBB2_4: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq 112(%rsp), %rax # 8-byte Reload
movq %rax, 88(%rsp)
movq 320(%rsp), %rax
movq %rax, 80(%rsp)
movq 328(%rsp), %rax
movq %rax, 72(%rsp)
movq 336(%rsp), %rax
movq %rax, 64(%rsp)
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z24particleParticleForces_kPdS_S_S_S_S_d, %edi
leaq 176(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6: # in Loop: Header=BB2_4 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_4 Depth=1
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq 112(%rsp), %rax # 8-byte Reload
movq %rax, 88(%rsp)
movq 128(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movq 136(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movq 144(%rsp), %rax # 8-byte Reload
movq %rax, 64(%rsp)
movq 320(%rsp), %rax
movq %rax, 56(%rsp)
movq 328(%rsp), %rax
movq %rax, 48(%rsp)
movq 336(%rsp), %rax
movq %rax, 40(%rsp)
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, %edi
leaq 176(%rsp), %r9
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_8
.LBB2_9: # %._crit_edge
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16particleParticlePdS_S_S_S_S_S_S_S_iid, .Lfunc_end2-_Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI3_1:
.quad 0xbff0000000000000 # double -1
.LCPI3_2:
.quad 0x3ee4f8b580000000 # double 9.9999997473787516E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 80(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $38, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movq %r14, 48(%rsp) # 8-byte Spill
movslq %r14d, %rax
movq %rax, 64(%rsp) # 8-byte Spill
leaq (,%rax,8), %rbx
leaq (%rbx,%rbx,8), %rdx
movl $.L.str.2, %esi
xorl %eax, %eax
callq fprintf
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r12
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r13
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %rbp
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r15
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, 56(%rsp) # 8-byte Spill
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r14
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, 24(%rsp) # 8-byte Spill
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, 8(%rsp) # 8-byte Spill
movl $42, %edi
callq srand
movq %r15, 40(%rsp) # 8-byte Spill
movq %r15, %rdi
movq 56(%rsp), %r15 # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq %r15, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq %r14, 32(%rsp) # 8-byte Spill
movq %r14, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq 24(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq 16(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq 8(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
cmpl $0, 64(%rsp) # 4-byte Folded Reload
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader.i
movl 48(%rsp), %ebx # 4-byte Reload
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r12,%r14,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, (%r13,%r14,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, (%rbp,%r14,8)
incq %r14
cmpq %r14, %rbx
jne .LBB3_2
.LBB3_3: # %_Z16initialConditionPdS_S_S_S_S_S_S_S_i.exit
subq $48, %rsp
.cfi_adjust_cfa_offset 48
movq 128(%rsp), %rbx # 8-byte Reload
movl %ebx, 32(%rsp)
movq 96(%rsp), %r14 # 8-byte Reload
movl %r14d, 24(%rsp)
xorpd %xmm0, %xmm0
movupd %xmm0, (%rsp)
movq $0, 16(%rsp)
movsd .LCPI3_2(%rip), %xmm0 # xmm0 = mem[0],zero
xorl %edi, %edi
xorl %esi, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq _Z16particleParticlePdS_S_S_S_S_S_S_S_iid
addq $48, %rsp
.cfi_adjust_cfa_offset -48
cmpl $1, 72(%rsp) # 4-byte Folded Reload
jne .LBB3_5
# %bb.4:
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq %r12, %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq 48(%rsp), %rcx # 8-byte Reload
movq %r15, %r8
movq 40(%rsp), %r9 # 8-byte Reload
pushq %rbx
.cfi_adjust_cfa_offset 8
pushq %r14
.cfi_adjust_cfa_offset 8
pushq 32(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 48(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 64(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
callq _Z8printLogPdS_S_S_S_S_S_S_S_ii
addq $48, %rsp
.cfi_adjust_cfa_offset -48
.LBB3_5:
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16initialConditionPdS_S_S_S_S_S_S_S_i
.LCPI4_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI4_1:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z16initialConditionPdS_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z16initialConditionPdS_S_S_S_S_S_S_S_i,@function
_Z16initialConditionPdS_S_S_S_S_S_S_S_i: # @_Z16initialConditionPdS_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 16(%rsp) # 8-byte Spill
movq %r8, 8(%rsp) # 8-byte Spill
movq %rcx, %r12
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movslq 104(%rsp), %rbp
movl $42, %edi
callq srand
leaq (,%rbp,8), %r13
movq %r12, %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 8(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 16(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 80(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 88(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 96(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
testq %rbp, %rbp
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r15,%r13,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, (%r14,%r13,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, (%rbx,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16initialConditionPdS_S_S_S_S_S_S_S_i, .Lfunc_end4-_Z16initialConditionPdS_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z8printLogPdS_S_S_S_S_S_S_S_ii # -- Begin function _Z8printLogPdS_S_S_S_S_S_S_S_ii
.p2align 4, 0x90
.type _Z8printLogPdS_S_S_S_S_S_S_S_ii,@function
_Z8printLogPdS_S_S_S_S_S_S_S_ii: # @_Z8printLogPdS_S_S_S_S_S_S_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 24(%rsp) # 8-byte Spill
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movl 248(%rsp), %r14d
movl 256(%rsp), %ecx
leaq 32(%rsp), %rbx
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
xorl %eax, %eax
callq sprintf
movq stdout(%rip), %rdi
movl $.L.str.5, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
callq fflush
movl $.L.str.6, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
testl %r14d, %r14d
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %r14d, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rbp,%r14,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r13,%r14,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r12,%r14,8), %xmm2 # xmm2 = mem[0],zero
movq 8(%rsp), %rax # 8-byte Reload
movsd (%rax,%r14,8), %xmm3 # xmm3 = mem[0],zero
movq 16(%rsp), %rax # 8-byte Reload
movsd (%rax,%r14,8), %xmm4 # xmm4 = mem[0],zero
movq 24(%rsp), %rax # 8-byte Reload
movsd (%rax,%r14,8), %xmm5 # xmm5 = mem[0],zero
movq 224(%rsp), %rax
movsd (%rax,%r14,8), %xmm6 # xmm6 = mem[0],zero
movq 232(%rsp), %rax
movsd (%rax,%r14,8), %xmm7 # xmm7 = mem[0],zero
movq 240(%rsp), %rax
movsd (%rax,%r14,8), %xmm8 # xmm8 = mem[0],zero
movsd %xmm8, (%rsp)
movl $.L.str.7, %esi
movq %rbx, %rdi
movl %r14d, %edx
movb $8, %al
callq fprintf
incq %r14
cmpq %r14, %r15
jne .LBB5_2
.LBB5_3: # %._crit_edge
movq %rbx, %rdi
callq fclose
movq stdout(%rip), %rcx
movl $.L.str.8, %edi
movl $5, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
callq fflush
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z8printLogPdS_S_S_S_S_S_S_S_ii, .Lfunc_end5-_Z8printLogPdS_S_S_S_S_S_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24particleParticleForces_kPdS_S_S_S_S_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24particleParticleForces_kPdS_S_S_S_S_d,@object # @_Z24particleParticleForces_kPdS_S_S_S_S_d
.section .rodata,"a",@progbits
.globl _Z24particleParticleForces_kPdS_S_S_S_S_d
.p2align 3, 0x0
_Z24particleParticleForces_kPdS_S_S_S_S_d:
.quad _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.size _Z24particleParticleForces_kPdS_S_S_S_S_d, 8
.type _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d,@object # @_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.globl _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.p2align 3, 0x0
_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d:
.quad _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.size _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n B(%d) T(%d) shared memory %d \n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nParcile system particle to particle \n"
.size .L.str.1, 39
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Memory used %lu bytes \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s-%d-log.bin"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/marzam/HPC-Aula/main/exemplos/problems-profile/nbody-cuda-profile/main-n-bodies-2.0.hip"
.size .L.str.4, 145
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Saving file [%s] "
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w+"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n"
.size .L.str.7, 65
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "[OK]\n"
.size .L.str.8, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24particleParticleForces_kPdS_S_S_S_S_d"
.size .L__unnamed_1, 42
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d"
.size .L__unnamed_2, 58
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.addrsig_sym _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24particleParticleForces_kPdS_S_S_S_S_d
.addrsig_sym _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000efef2_00000000-6_main-n-bodies-2.0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distancePdS_S_dddddd
.type _Z8distancePdS_S_dddddd, @function
_Z8distancePdS_S_dddddd:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8distancePdS_S_dddddd, .-_Z8distancePdS_S_dddddd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/marzam/HPC-Aula/main/exemplos/problems-profile/nbody-cuda-profile/main-n-bodies-2.0.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s-%d-log.bin"
.LC2:
.string "Saving file [%s] "
.LC3:
.string "w+"
.section .rodata.str1.8
.align 8
.LC4:
.string "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n"
.section .rodata.str1.1
.LC5:
.string "[OK]\n"
.text
.globl _Z8printLogPdS_S_S_S_S_S_S_S_ii
.type _Z8printLogPdS_S_S_S_S_S_S_S_ii, @function
_Z8printLogPdS_S_S_S_S_S_S_S_ii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 256(%rsp), %r15
movq 264(%rsp), %rbp
movq 272(%rsp), %r14
movl 280(%rsp), %r12d
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbx
movl 288(%rsp), %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rcx
movl $128, %edx
movl $2, %esi
movq %rbx, %rdi
call __sprintf_chk@PLT
movq %rbx, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, (%rsp)
testl %r12d, %r12d
jle .L6
movslq %r12d, %r12
movl $0, %ebx
.L7:
movsd 0(%r13,%rbx,8), %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 264
pushq (%r14,%rbx,8)
.cfi_def_cfa_offset 272
movsd 0(%rbp,%rbx,8), %xmm7
movsd (%r15,%rbx,8), %xmm6
movq 56(%rsp), %rax
movsd (%rax,%rbx,8), %xmm5
movq 48(%rsp), %rax
movsd (%rax,%rbx,8), %xmm4
movq 40(%rsp), %rax
movsd (%rax,%rbx,8), %xmm3
movq 32(%rsp), %rax
movsd (%rax,%rbx,8), %xmm2
movq 24(%rsp), %rax
movsd (%rax,%rbx,8), %xmm1
movl %ebx, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq 16(%rsp), %rdi
movl $8, %eax
call __fprintf_chk@PLT
addq $1, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 256
cmpq %r12, %rbx
jne .L7
.L6:
movq (%rsp), %rdi
call fclose@PLT
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8printLogPdS_S_S_S_S_S_S_S_ii, .-_Z8printLogPdS_S_S_S_S_S_S_S_ii
.globl _Z16initialConditionPdS_S_S_S_S_S_S_S_i
.type _Z16initialConditionPdS_S_S_S_S_S_S_S_i, @function
_Z16initialConditionPdS_S_S_S_S_S_S_S_i:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %r15
movq %r8, %r14
movq %r9, 8(%rsp)
movl $42, %edi
call srand@PLT
movslq 104(%rsp), %rbx
salq $3, %rbx
movq %rbx, %rdx
movl $0, %esi
movq %r15, %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq %r14, %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 80(%rsp), %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call memset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 96(%rsp), %rdi
call memset@PLT
cmpl $0, 104(%rsp)
jle .L12
movl $0, %r14d
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, 0(%rbp,%r14)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, (%r12,%r14)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, 0(%r13,%r14)
addq $8, %r14
cmpq %r14, %rbx
jne .L14
.L12:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z16initialConditionPdS_S_S_S_S_S_S_S_i, .-_Z16initialConditionPdS_S_S_S_S_S_S_S_i
.globl _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d
.type _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d, @function
_Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d:
.LFB2086:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24particleParticleForces_kPdS_S_S_S_S_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d, .-_Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d
.globl _Z24particleParticleForces_kPdS_S_S_S_S_d
.type _Z24particleParticleForces_kPdS_S_S_S_S_d, @function
_Z24particleParticleForces_kPdS_S_S_S_S_d:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z24particleParticleForces_kPdS_S_S_S_S_d, .-_Z24particleParticleForces_kPdS_S_S_S_S_d
.globl _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d
.type _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d, @function
_Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d:
.LFB2088:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movsd %xmm0, (%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movq %rsp, %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d, .-_Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d
.globl _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.type _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, @function
_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d:
.LFB2089:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, .-_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.section .rodata.str1.8
.align 8
.LC8:
.string "\n B(%d) T(%d) shared memory %d \n"
.text
.globl _Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.type _Z16particleParticlePdS_S_S_S_S_S_S_S_iid, @function
_Z16particleParticlePdS_S_S_S_S_S_S_S_iid:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, %r15
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movl 168(%rsp), %ebp
movl 176(%rsp), %r14d
movsd %xmm0, 16(%rsp)
movl $1, %r12d
cmpl $1023, %ebp
jle .L34
leal 1023(%rbp), %r12d
testl %ebp, %ebp
cmovns %ebp, %r12d
sarl $10, %r12d
movl $1024, %ebp
.L34:
leal 0(%rbp,%rbp,2), %r13d
movslq %r13d, %r13
salq $3, %r13
movq %r13, %r9
movl %ebp, %r8d
movl %r12d, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testl %r14d, %r14d
jle .L33
movl $0, %ebx
jmp .L38
.L42:
movsd 16(%rsp), %xmm0
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z55__device_stub__Z24particleParticleForces_kPdS_S_S_S_S_dPdS_S_S_S_S_d
jmp .L36
.L37:
addl $1, %ebx
cmpl %ebx, %r14d
je .L33
.L38:
movl %ebp, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r12d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movq %r13, %r8
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L36:
movl %ebp, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r12d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq 168(%rsp)
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
movsd 48(%rsp), %xmm0
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movq 56(%rsp), %rcx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z71__device_stub__Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_dPdS_S_S_S_S_S_S_S_d
addq $32, %rsp
.cfi_def_cfa_offset 144
jmp .L37
.L33:
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z16particleParticlePdS_S_S_S_S_S_S_S_iid, .-_Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.section .rodata.str1.8
.align 8
.LC9:
.string "\nParcile system particle to particle \n"
.section .rodata.str1.1
.LC10:
.string "Memory used %lu bytes \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 40(%rsp)
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq %ebp, %rcx
leaq 0(,%rcx,8), %rbx
addq %rbx, %rcx
salq $3, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r15
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r14
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, (%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 24(%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r13
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r12
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %rbx
pushq %rbp
.cfi_def_cfa_offset 120
pushq %rax
.cfi_def_cfa_offset 128
pushq %r12
.cfi_def_cfa_offset 136
pushq %r13
.cfi_def_cfa_offset 144
movq 56(%rsp), %r9
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %r14, %rsi
movq %r15, %rdi
call _Z16initialConditionPdS_S_S_S_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 120
movl 40(%rsp), %ecx
pushq %rcx
.cfi_def_cfa_offset 128
pushq %rbp
.cfi_def_cfa_offset 136
pushq $0
.cfi_def_cfa_offset 144
pushq $0
.cfi_def_cfa_offset 152
pushq $0
.cfi_def_cfa_offset 160
movsd .LC11(%rip), %xmm0
movl $0, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z16particleParticlePdS_S_S_S_S_S_S_S_iid
addq $48, %rsp
.cfi_def_cfa_offset 112
cmpl $1, 40(%rsp)
je .L46
.L44:
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 120
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
pushq %rbp
.cfi_def_cfa_offset 136
pushq %rbx
.cfi_def_cfa_offset 144
pushq %r12
.cfi_def_cfa_offset 152
pushq %r13
.cfi_def_cfa_offset 160
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %r14, %rsi
movq %r15, %rdi
call _Z8printLogPdS_S_S_S_S_S_S_S_ii
addq $48, %rsp
.cfi_def_cfa_offset 112
jmp .L44
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d"
.align 8
.LC13:
.string "_Z24particleParticleForces_kPdS_S_S_S_S_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z24particleParticleForces_kPdS_S_S_S_S_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -4194304
.long 1105199103
.align 8
.LC7:
.long 0
.long 1072693248
.align 8
.LC11:
.long -2147483648
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main-n-bodies-2.0.hip"
.globl _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d # -- Begin function _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.p2align 4, 0x90
.type _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d,@function
_Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d: # @_Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24particleParticleForces_kPdS_S_S_S_S_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d, .Lfunc_end0-_Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.cfi_endproc
# -- End function
.globl _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d # -- Begin function _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.p2align 4, 0x90
.type _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d,@function
_Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d: # @_Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end1:
.size _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, .Lfunc_end1-_Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.cfi_endproc
# -- End function
.globl _Z16particleParticlePdS_S_S_S_S_S_S_S_iid # -- Begin function _Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.p2align 4, 0x90
.type _Z16particleParticlePdS_S_S_S_S_S_S_S_iid,@function
_Z16particleParticlePdS_S_S_S_S_S_S_S_iid: # @_Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq %r9, 144(%rsp) # 8-byte Spill
movq %r8, 136(%rsp) # 8-byte Spill
movq %rcx, 128(%rsp) # 8-byte Spill
movq %rdx, 112(%rsp) # 8-byte Spill
movq %rsi, %r13
movq %rdi, %rbp
movl 352(%rsp), %r12d
movl 344(%rsp), %eax
movl $1, %r14d
cmpl $1024, %eax # imm = 0x400
jl .LBB2_2
# %bb.1: # %select.false.sink
leal 1023(%rax), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $10, %r14d
.LBB2_2: # %select.end
cmpl $1024, %eax # imm = 0x400
movl $1024, %r15d # imm = 0x400
cmovll %eax, %r15d
movq stdout(%rip), %rdi
leal (%r15,%r15,2), %eax
movslq %eax, %rbx
shlq $3, %rbx
movl $.L.str, %esi
movl %r14d, %edx
movl %r15d, %ecx
movq %rbx, %r8
xorl %eax, %eax
callq fprintf
testl %r12d, %r12d
jle .LBB2_9
# %bb.3: # %.lr.ph
movl %r14d, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movl %r15d, %r15d
orq %rax, %r15
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_4 Depth=1
decl %r12d
je .LBB2_9
.LBB2_4: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq 112(%rsp), %rax # 8-byte Reload
movq %rax, 88(%rsp)
movq 320(%rsp), %rax
movq %rax, 80(%rsp)
movq 328(%rsp), %rax
movq %rax, 72(%rsp)
movq 336(%rsp), %rax
movq %rax, 64(%rsp)
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z24particleParticleForces_kPdS_S_S_S_S_d, %edi
leaq 176(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6: # in Loop: Header=BB2_4 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_4 Depth=1
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq 112(%rsp), %rax # 8-byte Reload
movq %rax, 88(%rsp)
movq 128(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movq 136(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movq 144(%rsp), %rax # 8-byte Reload
movq %rax, 64(%rsp)
movq 320(%rsp), %rax
movq %rax, 56(%rsp)
movq 328(%rsp), %rax
movq %rax, 48(%rsp)
movq 336(%rsp), %rax
movq %rax, 40(%rsp)
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, %edi
leaq 176(%rsp), %r9
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_8
.LBB2_9: # %._crit_edge
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16particleParticlePdS_S_S_S_S_S_S_S_iid, .Lfunc_end2-_Z16particleParticlePdS_S_S_S_S_S_S_S_iid
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI3_1:
.quad 0xbff0000000000000 # double -1
.LCPI3_2:
.quad 0x3ee4f8b580000000 # double 9.9999997473787516E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 80(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $38, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movq %r14, 48(%rsp) # 8-byte Spill
movslq %r14d, %rax
movq %rax, 64(%rsp) # 8-byte Spill
leaq (,%rax,8), %rbx
leaq (%rbx,%rbx,8), %rdx
movl $.L.str.2, %esi
xorl %eax, %eax
callq fprintf
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r12
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r13
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %rbp
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r15
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, 56(%rsp) # 8-byte Spill
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r14
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, 24(%rsp) # 8-byte Spill
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, 8(%rsp) # 8-byte Spill
movl $42, %edi
callq srand
movq %r15, 40(%rsp) # 8-byte Spill
movq %r15, %rdi
movq 56(%rsp), %r15 # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq %r15, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq %r14, 32(%rsp) # 8-byte Spill
movq %r14, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq 24(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq 16(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movq 8(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
cmpl $0, 64(%rsp) # 4-byte Folded Reload
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader.i
movl 48(%rsp), %ebx # 4-byte Reload
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r12,%r14,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, (%r13,%r14,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, (%rbp,%r14,8)
incq %r14
cmpq %r14, %rbx
jne .LBB3_2
.LBB3_3: # %_Z16initialConditionPdS_S_S_S_S_S_S_S_i.exit
subq $48, %rsp
.cfi_adjust_cfa_offset 48
movq 128(%rsp), %rbx # 8-byte Reload
movl %ebx, 32(%rsp)
movq 96(%rsp), %r14 # 8-byte Reload
movl %r14d, 24(%rsp)
xorpd %xmm0, %xmm0
movupd %xmm0, (%rsp)
movq $0, 16(%rsp)
movsd .LCPI3_2(%rip), %xmm0 # xmm0 = mem[0],zero
xorl %edi, %edi
xorl %esi, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq _Z16particleParticlePdS_S_S_S_S_S_S_S_iid
addq $48, %rsp
.cfi_adjust_cfa_offset -48
cmpl $1, 72(%rsp) # 4-byte Folded Reload
jne .LBB3_5
# %bb.4:
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq %r12, %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq 48(%rsp), %rcx # 8-byte Reload
movq %r15, %r8
movq 40(%rsp), %r9 # 8-byte Reload
pushq %rbx
.cfi_adjust_cfa_offset 8
pushq %r14
.cfi_adjust_cfa_offset 8
pushq 32(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 48(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 64(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
callq _Z8printLogPdS_S_S_S_S_S_S_S_ii
addq $48, %rsp
.cfi_adjust_cfa_offset -48
.LBB3_5:
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %edi, %edi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16initialConditionPdS_S_S_S_S_S_S_S_i
.LCPI4_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI4_1:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z16initialConditionPdS_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z16initialConditionPdS_S_S_S_S_S_S_S_i,@function
_Z16initialConditionPdS_S_S_S_S_S_S_S_i: # @_Z16initialConditionPdS_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 16(%rsp) # 8-byte Spill
movq %r8, 8(%rsp) # 8-byte Spill
movq %rcx, %r12
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movslq 104(%rsp), %rbp
movl $42, %edi
callq srand
leaq (,%rbp,8), %r13
movq %r12, %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 8(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 16(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 80(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 88(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq 96(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
testq %rbp, %rbp
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r15,%r13,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, (%r14,%r13,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, (%rbx,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16initialConditionPdS_S_S_S_S_S_S_S_i, .Lfunc_end4-_Z16initialConditionPdS_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z8printLogPdS_S_S_S_S_S_S_S_ii # -- Begin function _Z8printLogPdS_S_S_S_S_S_S_S_ii
.p2align 4, 0x90
.type _Z8printLogPdS_S_S_S_S_S_S_S_ii,@function
_Z8printLogPdS_S_S_S_S_S_S_S_ii: # @_Z8printLogPdS_S_S_S_S_S_S_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 24(%rsp) # 8-byte Spill
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movl 248(%rsp), %r14d
movl 256(%rsp), %ecx
leaq 32(%rsp), %rbx
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
xorl %eax, %eax
callq sprintf
movq stdout(%rip), %rdi
movl $.L.str.5, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
callq fflush
movl $.L.str.6, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
testl %r14d, %r14d
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %r14d, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rbp,%r14,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r13,%r14,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r12,%r14,8), %xmm2 # xmm2 = mem[0],zero
movq 8(%rsp), %rax # 8-byte Reload
movsd (%rax,%r14,8), %xmm3 # xmm3 = mem[0],zero
movq 16(%rsp), %rax # 8-byte Reload
movsd (%rax,%r14,8), %xmm4 # xmm4 = mem[0],zero
movq 24(%rsp), %rax # 8-byte Reload
movsd (%rax,%r14,8), %xmm5 # xmm5 = mem[0],zero
movq 224(%rsp), %rax
movsd (%rax,%r14,8), %xmm6 # xmm6 = mem[0],zero
movq 232(%rsp), %rax
movsd (%rax,%r14,8), %xmm7 # xmm7 = mem[0],zero
movq 240(%rsp), %rax
movsd (%rax,%r14,8), %xmm8 # xmm8 = mem[0],zero
movsd %xmm8, (%rsp)
movl $.L.str.7, %esi
movq %rbx, %rdi
movl %r14d, %edx
movb $8, %al
callq fprintf
incq %r14
cmpq %r14, %r15
jne .LBB5_2
.LBB5_3: # %._crit_edge
movq %rbx, %rdi
callq fclose
movq stdout(%rip), %rcx
movl $.L.str.8, %edi
movl $5, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
callq fflush
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z8printLogPdS_S_S_S_S_S_S_S_ii, .Lfunc_end5-_Z8printLogPdS_S_S_S_S_S_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24particleParticleForces_kPdS_S_S_S_S_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24particleParticleForces_kPdS_S_S_S_S_d,@object # @_Z24particleParticleForces_kPdS_S_S_S_S_d
.section .rodata,"a",@progbits
.globl _Z24particleParticleForces_kPdS_S_S_S_S_d
.p2align 3, 0x0
_Z24particleParticleForces_kPdS_S_S_S_S_d:
.quad _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.size _Z24particleParticleForces_kPdS_S_S_S_S_d, 8
.type _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d,@object # @_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.globl _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.p2align 3, 0x0
_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d:
.quad _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.size _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n B(%d) T(%d) shared memory %d \n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nParcile system particle to particle \n"
.size .L.str.1, 39
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Memory used %lu bytes \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s-%d-log.bin"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/marzam/HPC-Aula/main/exemplos/problems-profile/nbody-cuda-profile/main-n-bodies-2.0.hip"
.size .L.str.4, 145
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Saving file [%s] "
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w+"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n"
.size .L.str.7, 65
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "[OK]\n"
.size .L.str.8, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24particleParticleForces_kPdS_S_S_S_S_d"
.size .L__unnamed_1, 42
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d"
.size .L__unnamed_2, 58
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__particleParticleForces_kPdS_S_S_S_S_d
.addrsig_sym _Z49__device_stub__particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24particleParticleForces_kPdS_S_S_S_S_d
.addrsig_sym _Z34particleParticleVelocityPosition_kPdS_S_S_S_S_S_S_S_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Match1(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
int p1 = threadIdx.x + M1W*blockIdx.x;
float max_score = 0.0f;
int index = -1;
for (int p2=0;p2<NPTS;p2++) {
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += d_pts1[p1*NDIM + d]*d_pts2[p2*NDIM + d];
if (score>max_score) {
max_score = score;
index = p2;
}
}
d_score[p1] = max_score;
d_index[p1] = index;
} | code for sm_80
Function : _Z6Match1PfS_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R6, 0xffffffff ; /* 0xffffffff00067802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0070*/ LEA R0, R0, R3, 0x7 ; /* 0x0000000300007211 */
/* 0x001fc800078e38ff */
/*0080*/ SHF.L.U32 R9, R0, 0x7, RZ ; /* 0x0000000700097819 */
/* 0x000fe400000006ff */
/*0090*/ SHF.L.U32 R10, R7, 0x7, RZ ; /* 0x00000007070a7819 */
/* 0x000fe200000006ff */
/*00a0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ MOV R12, c[0x0][0x168] ; /* 0x00005a00000c7a02 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R13, c[0x0][0x16c] ; /* 0x00005b00000d7a02 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R2, UR6 ; /* 0x0000000600027c02 */
/* 0x000fe20008000f00 */
/*0100*/ IMAD.WIDE R4, R10, 0x4, R12 ; /* 0x000000040a047825 */
/* 0x000fe200078e020c */
/*0110*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fc80008000f00 */
/*0120*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x000fc600078e0202 */
/*0140*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000f28000c1e1900 */
/*0180*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R20, [R4.64+0xc] ; /* 0x00000c0404147981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R22, [R4.64+0x10] ; /* 0x0000100404167981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100402177981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R24, [R4.64+0x14] ; /* 0x0000140404187981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R25, [R2.64+0x14] ; /* 0x0000140402197981 */
/* 0x000f62000c1e1900 */
/*01f0*/ FFMA R16, R16, R17, R27 ; /* 0x0000001110107223 */
/* 0x004fc6000000001b */
/*0200*/ LDG.E R17, [R2.64+0x20] ; /* 0x0000200402117981 */
/* 0x000ea2000c1e1900 */
/*0210*/ FFMA R16, R19, R18, R16 ; /* 0x0000001213107223 */
/* 0x008fc60000000010 */
/*0220*/ LDG.E R18, [R4.64+0x18] ; /* 0x0000180404127981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R19, [R2.64+0x18] ; /* 0x0000180402137981 */
/* 0x000ee2000c1e1900 */
/*0240*/ FFMA R26, R15, R14, R16 ; /* 0x0000000e0f1a7223 */
/* 0x010fc60000000010 */
/*0250*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R15, [R2.64+0x1c] ; /* 0x00001c04020f7981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000ea2000c1e1900 */
/*0280*/ FFMA R20, R20, R21, R26 ; /* 0x0000001514147223 */
/* 0x020fc6000000001a */
/*0290*/ LDG.E R21, [R2.64+0x24] ; /* 0x0000240402157981 */
/* 0x000f62000c1e1900 */
/*02a0*/ FFMA R22, R22, R23, R20 ; /* 0x0000001716167223 */
/* 0x000fc60000000014 */
/*02b0*/ LDG.E R20, [R4.64+0x24] ; /* 0x0000240404147981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R23, [R2.64+0x28] ; /* 0x0000280402177981 */
/* 0x000f62000c1e1900 */
/*02d0*/ FFMA R24, R24, R25, R22 ; /* 0x0000001918187223 */
/* 0x000fc60000000016 */
/*02e0*/ LDG.E R22, [R4.64+0x28] ; /* 0x0000280404167981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R25, [R2.64+0x34] ; /* 0x0000340402197981 */
/* 0x000f68000c1e1900 */
/*0300*/ LDG.E R26, [R4.64+0x3c] ; /* 0x00003c04041a7981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R27, [R2.64+0x3c] ; /* 0x00003c04021b7981 */
/* 0x000f62000c1e1900 */
/*0320*/ FFMA R24, R18, R19, R24 ; /* 0x0000001312187223 */
/* 0x008fc60000000018 */
/*0330*/ LDG.E R18, [R4.64+0x2c] ; /* 0x00002c0404127981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R19, [R2.64+0x2c] ; /* 0x00002c0402137981 */
/* 0x000ee2000c1e1900 */
/*0350*/ FFMA R24, R14, R15, R24 ; /* 0x0000000f0e187223 */
/* 0x010fc60000000018 */
/*0360*/ LDG.E R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R15, [R2.64+0x30] ; /* 0x00003004020f7981 */
/* 0x000f22000c1e1900 */
/*0380*/ FFMA R28, R16, R17, R24 ; /* 0x00000011101c7223 */
/* 0x004fc60000000018 */
/*0390*/ LDG.E R24, [R4.64+0x34] ; /* 0x0000340404187981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R16, [R4.64+0x38] ; /* 0x0000380404107981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R17, [R2.64+0x38] ; /* 0x0000380402117981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ FFMA R20, R20, R21, R28 ; /* 0x0000001514147223 */
/* 0x020fe2000000001c */
/*03d0*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc60007ffe0ff */
/*03e0*/ FFMA R20, R22, R23, R20 ; /* 0x0000001716147223 */
/* 0x000fe20000000014 */
/*03f0*/ ISETP.NE.AND P0, PT, R11, 0x80, PT ; /* 0x000000800b00780c */
/* 0x000fe20003f05270 */
/*0400*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0410*/ IADD3 R12, P1, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x000fc60007f3e0ff */
/*0420*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0430*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0440*/ FFMA R18, R18, R19, R20 ; /* 0x0000001312127223 */
/* 0x008fc80000000014 */
/*0450*/ FFMA R14, R14, R15, R18 ; /* 0x0000000f0e0e7223 */
/* 0x010fc80000000012 */
/*0460*/ FFMA R14, R24, R25, R14 ; /* 0x00000019180e7223 */
/* 0x004fc8000000000e */
/*0470*/ FFMA R14, R16, R17, R14 ; /* 0x00000011100e7223 */
/* 0x000fc8000000000e */
/*0480*/ FFMA R27, R26, R27, R14 ; /* 0x0000001b1a1b7223 */
/* 0x000fe2000000000e */
/*0490*/ @P0 BRA 0xf0 ; /* 0xfffffc5000000947 */
/* 0x000fea000383ffff */
/*04a0*/ FSETP.GT.AND P0, PT, R27, R8, PT ; /* 0x000000081b00720b */
/* 0x000fc80003f04000 */
/*04b0*/ SEL R6, R7.reuse, R6, P0 ; /* 0x0000000607067207 */
/* 0x040fe40000000000 */
/*04c0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ FSEL R8, R27, R8, P0 ; /* 0x000000081b087208 */
/* 0x000fe40000000000 */
/*04e0*/ ISETP.GE.U32.AND P1, PT, R7, 0x4000, PT ; /* 0x000040000700780c */
/* 0x000fda0003f26070 */
/*04f0*/ @!P1 BRA 0x90 ; /* 0xfffffb9000009947 */
/* 0x000fea000383ffff */
/*0500*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0510*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0205 */
/*0520*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*0530*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x000fe8000c101904 */
/*0540*/ STG.E [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x000fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Match1(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
int p1 = threadIdx.x + M1W*blockIdx.x;
float max_score = 0.0f;
int index = -1;
for (int p2=0;p2<NPTS;p2++) {
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += d_pts1[p1*NDIM + d]*d_pts2[p2*NDIM + d];
if (score>max_score) {
max_score = score;
index = p2;
}
}
d_score[p1] = max_score;
d_index[p1] = index;
} | .file "tmpxft_0008da91_00000000-6_Match1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi
.type _Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi, @function
_Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6Match1PfS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi, .-_Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi
.globl _Z6Match1PfS_S_Pi
.type _Z6Match1PfS_S_Pi, @function
_Z6Match1PfS_S_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6Match1PfS_S_Pi, .-_Z6Match1PfS_S_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6Match1PfS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6Match1PfS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Match1(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
int p1 = threadIdx.x + M1W*blockIdx.x;
float max_score = 0.0f;
int index = -1;
for (int p2=0;p2<NPTS;p2++) {
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += d_pts1[p1*NDIM + d]*d_pts2[p2*NDIM + d];
if (score>max_score) {
max_score = score;
index = p2;
}
}
d_score[p1] = max_score;
d_index[p1] = index;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Match1(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
int p1 = threadIdx.x + M1W*blockIdx.x;
float max_score = 0.0f;
int index = -1;
for (int p2=0;p2<NPTS;p2++) {
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += d_pts1[p1*NDIM + d]*d_pts2[p2*NDIM + d];
if (score>max_score) {
max_score = score;
index = p2;
}
}
d_score[p1] = max_score;
d_index[p1] = index;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Match1(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
int p1 = threadIdx.x + M1W*blockIdx.x;
float max_score = 0.0f;
int index = -1;
for (int p2=0;p2<NPTS;p2++) {
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += d_pts1[p1*NDIM + d]*d_pts2[p2*NDIM + d];
if (score>max_score) {
max_score = score;
index = p2;
}
}
d_score[p1] = max_score;
d_index[p1] = index;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6Match1PfS_S_Pi
.globl _Z6Match1PfS_S_Pi
.p2align 8
.type _Z6Match1PfS_S_Pi,@function
_Z6Match1PfS_S_Pi:
v_lshl_add_u32 v0, s15, 7, v0
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 7, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v2, -1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s4, 0
.p2align 6
.LBB0_1:
v_mov_b32_e32 v5, 0
s_mov_b64 s[2:3], 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v6, vcc_lo, v1, s2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v4, vcc_lo
s_add_u32 s8, s6, s2
s_addc_u32 s9, s7, s3
s_add_u32 s2, s2, 4
global_load_b32 v6, v[6:7], off
s_load_b32 s5, s[8:9], 0x0
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x200
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v5, s5, v6
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, v5, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_cndmask_b32_e64 v2, v2, s4, vcc_lo
s_add_i32 s4, s4, 1
s_add_u32 s6, s6, 0x200
s_addc_u32 s7, s7, 0
s_cmpk_eq_i32 s4, 0x4000
s_cbranch_scc0 .LBB0_1
s_load_b128 s[0:3], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[4:5], v3, off
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6Match1PfS_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6Match1PfS_S_Pi, .Lfunc_end0-_Z6Match1PfS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6Match1PfS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6Match1PfS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Match1(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
int p1 = threadIdx.x + M1W*blockIdx.x;
float max_score = 0.0f;
int index = -1;
for (int p2=0;p2<NPTS;p2++) {
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += d_pts1[p1*NDIM + d]*d_pts2[p2*NDIM + d];
if (score>max_score) {
max_score = score;
index = p2;
}
}
d_score[p1] = max_score;
d_index[p1] = index;
} | .text
.file "Match1.hip"
.globl _Z21__device_stub__Match1PfS_S_Pi # -- Begin function _Z21__device_stub__Match1PfS_S_Pi
.p2align 4, 0x90
.type _Z21__device_stub__Match1PfS_S_Pi,@function
_Z21__device_stub__Match1PfS_S_Pi: # @_Z21__device_stub__Match1PfS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6Match1PfS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__Match1PfS_S_Pi, .Lfunc_end0-_Z21__device_stub__Match1PfS_S_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6Match1PfS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6Match1PfS_S_Pi,@object # @_Z6Match1PfS_S_Pi
.section .rodata,"a",@progbits
.globl _Z6Match1PfS_S_Pi
.p2align 3, 0x0
_Z6Match1PfS_S_Pi:
.quad _Z21__device_stub__Match1PfS_S_Pi
.size _Z6Match1PfS_S_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6Match1PfS_S_Pi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__Match1PfS_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6Match1PfS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6Match1PfS_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R6, 0xffffffff ; /* 0xffffffff00067802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0070*/ LEA R0, R0, R3, 0x7 ; /* 0x0000000300007211 */
/* 0x001fc800078e38ff */
/*0080*/ SHF.L.U32 R9, R0, 0x7, RZ ; /* 0x0000000700097819 */
/* 0x000fe400000006ff */
/*0090*/ SHF.L.U32 R10, R7, 0x7, RZ ; /* 0x00000007070a7819 */
/* 0x000fe200000006ff */
/*00a0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ MOV R12, c[0x0][0x168] ; /* 0x00005a00000c7a02 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R13, c[0x0][0x16c] ; /* 0x00005b00000d7a02 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R2, UR6 ; /* 0x0000000600027c02 */
/* 0x000fe20008000f00 */
/*0100*/ IMAD.WIDE R4, R10, 0x4, R12 ; /* 0x000000040a047825 */
/* 0x000fe200078e020c */
/*0110*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fc80008000f00 */
/*0120*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x000fc600078e0202 */
/*0140*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000f28000c1e1900 */
/*0180*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R20, [R4.64+0xc] ; /* 0x00000c0404147981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R22, [R4.64+0x10] ; /* 0x0000100404167981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100402177981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R24, [R4.64+0x14] ; /* 0x0000140404187981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R25, [R2.64+0x14] ; /* 0x0000140402197981 */
/* 0x000f62000c1e1900 */
/*01f0*/ FFMA R16, R16, R17, R27 ; /* 0x0000001110107223 */
/* 0x004fc6000000001b */
/*0200*/ LDG.E R17, [R2.64+0x20] ; /* 0x0000200402117981 */
/* 0x000ea2000c1e1900 */
/*0210*/ FFMA R16, R19, R18, R16 ; /* 0x0000001213107223 */
/* 0x008fc60000000010 */
/*0220*/ LDG.E R18, [R4.64+0x18] ; /* 0x0000180404127981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R19, [R2.64+0x18] ; /* 0x0000180402137981 */
/* 0x000ee2000c1e1900 */
/*0240*/ FFMA R26, R15, R14, R16 ; /* 0x0000000e0f1a7223 */
/* 0x010fc60000000010 */
/*0250*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R15, [R2.64+0x1c] ; /* 0x00001c04020f7981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000ea2000c1e1900 */
/*0280*/ FFMA R20, R20, R21, R26 ; /* 0x0000001514147223 */
/* 0x020fc6000000001a */
/*0290*/ LDG.E R21, [R2.64+0x24] ; /* 0x0000240402157981 */
/* 0x000f62000c1e1900 */
/*02a0*/ FFMA R22, R22, R23, R20 ; /* 0x0000001716167223 */
/* 0x000fc60000000014 */
/*02b0*/ LDG.E R20, [R4.64+0x24] ; /* 0x0000240404147981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R23, [R2.64+0x28] ; /* 0x0000280402177981 */
/* 0x000f62000c1e1900 */
/*02d0*/ FFMA R24, R24, R25, R22 ; /* 0x0000001918187223 */
/* 0x000fc60000000016 */
/*02e0*/ LDG.E R22, [R4.64+0x28] ; /* 0x0000280404167981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R25, [R2.64+0x34] ; /* 0x0000340402197981 */
/* 0x000f68000c1e1900 */
/*0300*/ LDG.E R26, [R4.64+0x3c] ; /* 0x00003c04041a7981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R27, [R2.64+0x3c] ; /* 0x00003c04021b7981 */
/* 0x000f62000c1e1900 */
/*0320*/ FFMA R24, R18, R19, R24 ; /* 0x0000001312187223 */
/* 0x008fc60000000018 */
/*0330*/ LDG.E R18, [R4.64+0x2c] ; /* 0x00002c0404127981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R19, [R2.64+0x2c] ; /* 0x00002c0402137981 */
/* 0x000ee2000c1e1900 */
/*0350*/ FFMA R24, R14, R15, R24 ; /* 0x0000000f0e187223 */
/* 0x010fc60000000018 */
/*0360*/ LDG.E R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R15, [R2.64+0x30] ; /* 0x00003004020f7981 */
/* 0x000f22000c1e1900 */
/*0380*/ FFMA R28, R16, R17, R24 ; /* 0x00000011101c7223 */
/* 0x004fc60000000018 */
/*0390*/ LDG.E R24, [R4.64+0x34] ; /* 0x0000340404187981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R16, [R4.64+0x38] ; /* 0x0000380404107981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R17, [R2.64+0x38] ; /* 0x0000380402117981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ FFMA R20, R20, R21, R28 ; /* 0x0000001514147223 */
/* 0x020fe2000000001c */
/*03d0*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc60007ffe0ff */
/*03e0*/ FFMA R20, R22, R23, R20 ; /* 0x0000001716147223 */
/* 0x000fe20000000014 */
/*03f0*/ ISETP.NE.AND P0, PT, R11, 0x80, PT ; /* 0x000000800b00780c */
/* 0x000fe20003f05270 */
/*0400*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0410*/ IADD3 R12, P1, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x000fc60007f3e0ff */
/*0420*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0430*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0440*/ FFMA R18, R18, R19, R20 ; /* 0x0000001312127223 */
/* 0x008fc80000000014 */
/*0450*/ FFMA R14, R14, R15, R18 ; /* 0x0000000f0e0e7223 */
/* 0x010fc80000000012 */
/*0460*/ FFMA R14, R24, R25, R14 ; /* 0x00000019180e7223 */
/* 0x004fc8000000000e */
/*0470*/ FFMA R14, R16, R17, R14 ; /* 0x00000011100e7223 */
/* 0x000fc8000000000e */
/*0480*/ FFMA R27, R26, R27, R14 ; /* 0x0000001b1a1b7223 */
/* 0x000fe2000000000e */
/*0490*/ @P0 BRA 0xf0 ; /* 0xfffffc5000000947 */
/* 0x000fea000383ffff */
/*04a0*/ FSETP.GT.AND P0, PT, R27, R8, PT ; /* 0x000000081b00720b */
/* 0x000fc80003f04000 */
/*04b0*/ SEL R6, R7.reuse, R6, P0 ; /* 0x0000000607067207 */
/* 0x040fe40000000000 */
/*04c0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ FSEL R8, R27, R8, P0 ; /* 0x000000081b087208 */
/* 0x000fe40000000000 */
/*04e0*/ ISETP.GE.U32.AND P1, PT, R7, 0x4000, PT ; /* 0x000040000700780c */
/* 0x000fda0003f26070 */
/*04f0*/ @!P1 BRA 0x90 ; /* 0xfffffb9000009947 */
/* 0x000fea000383ffff */
/*0500*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0510*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0205 */
/*0520*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*0530*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x000fe8000c101904 */
/*0540*/ STG.E [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x000fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6Match1PfS_S_Pi
.globl _Z6Match1PfS_S_Pi
.p2align 8
.type _Z6Match1PfS_S_Pi,@function
_Z6Match1PfS_S_Pi:
v_lshl_add_u32 v0, s15, 7, v0
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 7, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v2, -1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s4, 0
.p2align 6
.LBB0_1:
v_mov_b32_e32 v5, 0
s_mov_b64 s[2:3], 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v6, vcc_lo, v1, s2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v4, vcc_lo
s_add_u32 s8, s6, s2
s_addc_u32 s9, s7, s3
s_add_u32 s2, s2, 4
global_load_b32 v6, v[6:7], off
s_load_b32 s5, s[8:9], 0x0
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x200
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v5, s5, v6
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, v5, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_cndmask_b32_e64 v2, v2, s4, vcc_lo
s_add_i32 s4, s4, 1
s_add_u32 s6, s6, 0x200
s_addc_u32 s7, s7, 0
s_cmpk_eq_i32 s4, 0x4000
s_cbranch_scc0 .LBB0_1
s_load_b128 s[0:3], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[4:5], v3, off
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6Match1PfS_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6Match1PfS_S_Pi, .Lfunc_end0-_Z6Match1PfS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6Match1PfS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6Match1PfS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008da91_00000000-6_Match1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi
.type _Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi, @function
_Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6Match1PfS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi, .-_Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi
.globl _Z6Match1PfS_S_Pi
.type _Z6Match1PfS_S_Pi, @function
_Z6Match1PfS_S_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6Match1PfS_S_PiPfS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6Match1PfS_S_Pi, .-_Z6Match1PfS_S_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6Match1PfS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6Match1PfS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Match1.hip"
.globl _Z21__device_stub__Match1PfS_S_Pi # -- Begin function _Z21__device_stub__Match1PfS_S_Pi
.p2align 4, 0x90
.type _Z21__device_stub__Match1PfS_S_Pi,@function
_Z21__device_stub__Match1PfS_S_Pi: # @_Z21__device_stub__Match1PfS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6Match1PfS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__Match1PfS_S_Pi, .Lfunc_end0-_Z21__device_stub__Match1PfS_S_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6Match1PfS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6Match1PfS_S_Pi,@object # @_Z6Match1PfS_S_Pi
.section .rodata,"a",@progbits
.globl _Z6Match1PfS_S_Pi
.p2align 3, 0x0
_Z6Match1PfS_S_Pi:
.quad _Z21__device_stub__Match1PfS_S_Pi
.size _Z6Match1PfS_S_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6Match1PfS_S_Pi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__Match1PfS_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6Match1PfS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void print_threadIds_blockIds_gridDim()
{
printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d,\
blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d,\
gridDim.x: %d, gridDim.y: %d, gridDim.z: %d \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nx, ny, nz;
nx = 4;
ny = 4;
nz = 4;
dim3 block(2, 2, 2);
dim3 grid(nx / block.x, ny / block.y, nz / block.z);
print_threadIds_blockIds_gridDim<<<grid, block>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z32print_threadIds_blockIds_gridDimv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x28, RZ ; /* 0xffffffd801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0c7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.Z ; /* 0x0000000000087919 */
/* 0x000e220000002300 */
/*0060*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x10] ; /* 0x00000400ff0d7624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0080*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff0e7624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R11, SR_CTAID.Z ; /* 0x00000000000b7919 */
/* 0x000e620000002700 */
/*00a0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0004e40000000a00 */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00c0*/ S2R R10, SR_CTAID.Y ; /* 0x00000000000a7919 */
/* 0x000e680000002600 */
/*00d0*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000f280000002200 */
/*00e0*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000f280000002100 */
/*00f0*/ STL.64 [R1+0x18], R12 ; /* 0x0000180c01007387 */
/* 0x000fe80000100a00 */
/*0100*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x001fe80000100a00 */
/*0110*/ STL [R1+0x20], R14 ; /* 0x0000200e01007387 */
/* 0x000fe80000100800 */
/*0120*/ STL.64 [R1+0x10], R10 ; /* 0x0000100a01007387 */
/* 0x002fe80000100a00 */
/*0130*/ STL.64 [R1], R4 ; /* 0x0000000401007387 */
/* 0x0101e40000100a00 */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x001fc400078e00ff */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0160*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x00cfca0000000000 */
/*0170*/ MOV R11, 0x1e0 ; /* 0x000001e0000b7802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R20, 0x160 ; /* 0x0000016000147802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void print_threadIds_blockIds_gridDim()
{
printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d,\
blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d,\
gridDim.x: %d, gridDim.y: %d, gridDim.z: %d \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nx, ny, nz;
nx = 4;
ny = 4;
nz = 4;
dim3 block(2, 2, 2);
dim3 grid(nx / block.x, ny / block.y, nz / block.z);
print_threadIds_blockIds_gridDim<<<grid, block>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | .file "tmpxft_0001536f_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv
.type _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv, @function
_Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z32print_threadIds_blockIds_gridDimv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv, .-_Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv
.globl _Z32print_threadIds_blockIds_gridDimv
.type _Z32print_threadIds_blockIds_gridDimv, @function
_Z32print_threadIds_blockIds_gridDimv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z32print_threadIds_blockIds_gridDimv, .-_Z32print_threadIds_blockIds_gridDimv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $2, %ecx
movq 20(%rsp), %rdi
movl $2, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32print_threadIds_blockIds_gridDimv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32print_threadIds_blockIds_gridDimv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void print_threadIds_blockIds_gridDim()
{
printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d,\
blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d,\
gridDim.x: %d, gridDim.y: %d, gridDim.z: %d \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nx, ny, nz;
nx = 4;
ny = 4;
nz = 4;
dim3 block(2, 2, 2);
dim3 grid(nx / block.x, ny / block.y, nz / block.z);
print_threadIds_blockIds_gridDim<<<grid, block>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | #include <stdio.h>
#include "hip/hip_runtime.h"
__global__ void print_threadIds_blockIds_gridDim()
{
printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d,\
blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d,\
gridDim.x: %d, gridDim.y: %d, gridDim.z: %d \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nx, ny, nz;
nx = 4;
ny = 4;
nz = 4;
dim3 block(2, 2, 2);
dim3 grid(nx / block.x, ny / block.y, nz / block.z);
print_threadIds_blockIds_gridDim<<<grid, block>>>();
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
__global__ void print_threadIds_blockIds_gridDim()
{
printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d,\
blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d,\
gridDim.x: %d, gridDim.y: %d, gridDim.z: %d \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nx, ny, nz;
nx = 4;
ny = 4;
nz = 4;
dim3 block(2, 2, 2);
dim3 grid(nx / block.x, ny / block.y, nz / block.z);
print_threadIds_blockIds_gridDim<<<grid, block>>>();
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.file "main.hip"
.globl _Z47__device_stub__print_threadIds_blockIds_gridDimv # -- Begin function _Z47__device_stub__print_threadIds_blockIds_gridDimv
.p2align 4, 0x90
.type _Z47__device_stub__print_threadIds_blockIds_gridDimv,@function
_Z47__device_stub__print_threadIds_blockIds_gridDimv: # @_Z47__device_stub__print_threadIds_blockIds_gridDimv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z32print_threadIds_blockIds_gridDimv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z47__device_stub__print_threadIds_blockIds_gridDimv, .Lfunc_end0-_Z47__device_stub__print_threadIds_blockIds_gridDimv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $8589934594, %rdi # imm = 0x200000002
movl $2, %esi
movq %rdi, %rdx
movl $2, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z32print_threadIds_blockIds_gridDimv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32print_threadIds_blockIds_gridDimv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32print_threadIds_blockIds_gridDimv,@object # @_Z32print_threadIds_blockIds_gridDimv
.section .rodata,"a",@progbits
.globl _Z32print_threadIds_blockIds_gridDimv
.p2align 3, 0x0
_Z32print_threadIds_blockIds_gridDimv:
.quad _Z47__device_stub__print_threadIds_blockIds_gridDimv
.size _Z32print_threadIds_blockIds_gridDimv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32print_threadIds_blockIds_gridDimv"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__print_threadIds_blockIds_gridDimv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32print_threadIds_blockIds_gridDimv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001536f_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv
.type _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv, @function
_Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z32print_threadIds_blockIds_gridDimv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv, .-_Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv
.globl _Z32print_threadIds_blockIds_gridDimv
.type _Z32print_threadIds_blockIds_gridDimv, @function
_Z32print_threadIds_blockIds_gridDimv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z32print_threadIds_blockIds_gridDimv, .-_Z32print_threadIds_blockIds_gridDimv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $2, %ecx
movq 20(%rsp), %rdi
movl $2, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z51__device_stub__Z32print_threadIds_blockIds_gridDimvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32print_threadIds_blockIds_gridDimv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32print_threadIds_blockIds_gridDimv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z47__device_stub__print_threadIds_blockIds_gridDimv # -- Begin function _Z47__device_stub__print_threadIds_blockIds_gridDimv
.p2align 4, 0x90
.type _Z47__device_stub__print_threadIds_blockIds_gridDimv,@function
_Z47__device_stub__print_threadIds_blockIds_gridDimv: # @_Z47__device_stub__print_threadIds_blockIds_gridDimv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z32print_threadIds_blockIds_gridDimv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z47__device_stub__print_threadIds_blockIds_gridDimv, .Lfunc_end0-_Z47__device_stub__print_threadIds_blockIds_gridDimv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $8589934594, %rdi # imm = 0x200000002
movl $2, %esi
movq %rdi, %rdx
movl $2, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z32print_threadIds_blockIds_gridDimv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32print_threadIds_blockIds_gridDimv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32print_threadIds_blockIds_gridDimv,@object # @_Z32print_threadIds_blockIds_gridDimv
.section .rodata,"a",@progbits
.globl _Z32print_threadIds_blockIds_gridDimv
.p2align 3, 0x0
_Z32print_threadIds_blockIds_gridDimv:
.quad _Z47__device_stub__print_threadIds_blockIds_gridDimv
.size _Z32print_threadIds_blockIds_gridDimv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32print_threadIds_blockIds_gridDimv"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__print_threadIds_blockIds_gridDimv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32print_threadIds_blockIds_gridDimv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <math_constants.h>
#include <cmath>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"ERROR: \"%s\" in %s:%d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ inline int access_(int M, int N, int O, int x, int y, int z) {
if (x<0) x=0; else if (x>=M) x=M-1;
if (y<0) y=0; else if (y>=N) y=N-1;
if (z<0) z=0; else if (z>=O) z=O-1;
//return y + M*(x + N*z);
return z*M*N + x*N + y;
}
__device__ int access_unchecked_(int M, int N, int O, int x, int y, int z) {
//return y + M*(x + N*z);
return z*M*N + x*N + y;
}
__device__ inline void indices_cubic_(
int f_i[64],
const int x, const int y, const int z,
const size_t &M, const size_t &N, const size_t &O) {
if (x<=2 || y<=2 || z<=2 || x>=N-3 || y>=M-3 || z>=O-3) {
for (int i=0; i<4; ++i)
for (int j=0; j<4; ++j)
for (int k=0; k<4; ++k)
//f_i[i+4*(j+4*k)] = access_(M,N,O, x+i-1, y+j-1, z+k-1);
f_i[k*16 + i*4 + j] = access_(M,N,O, x+i-1, y+j-1, z+k-1);
} else {
for (int i=0; i<4; ++i)
for (int j=0; j<4; ++j)
for (int k=0; k<4; ++k)
//f_i[i+4*(j+4*k)] = access_unchecked_(M,N,O, x+i-1, y+j-1, z+k-1);
f_i[k*16 + i*4 + j] = access_unchecked_(M,N,O, x+i-1, y+j-1, z+k-1);
}
}
__global__ void interpolate_bicubic_GPU(float *pO, const float *pF,
const float *pZ, const size_t ND, const size_t M, const size_t N, const size_t O) {
int blockId = blockIdx.x*gridDim.y + blockIdx.y;
//int threadId = threadIdx.x + blockDim.z*(threadIdx.y+blockDim.z*threadIdx.z);
int threadId = threadIdx.z*blockDim.x*blockDim.y + threadIdx.x*blockDim.y + threadIdx.y;
//printf("blockID=(%i %i) threadIdx=(%i %i %i) threadId=%i\n", blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, threadIdx.z, threadId);
//const float x = pX[blockId];
//const float y = pY[blockId];
const float x = blockIdx.x;
const float y = blockIdx.y;
const float z = pZ[blockId];
const float x_floor = floor(x);
const float y_floor = floor(y);
const float z_floor = floor(z);
const float dx = x-x_floor;
const float dy = y-y_floor;
const float dz = z-z_floor;
const float dxx = dx*dx;
const float dxxx = dxx*dx;
const float dyy = dy*dy;
const float dyyy = dyy*dy;
const float dzz = dz*dz;
const float dzzz = dzz*dz;
const float wx0 = 0.5f * ( - dx + 2.0f*dxx - dxxx);
const float wx1 = 0.5f * (2.0f - 5.0f*dxx + 3.0f * dxxx);
const float wx2 = 0.5f * ( dx + 4.0f*dxx - 3.0f * dxxx);
const float wx3 = 0.5f * ( - dxx + dxxx);
const float wy0 = 0.5f * ( - dy + 2.0f*dyy - dyyy);
const float wy1 = 0.5f * (2.0f - 5.0f*dyy + 3.0f * dyyy);
const float wy2 = 0.5f * ( dy + 4.0f*dyy - 3.0f * dyyy);
const float wy3 = 0.5f * ( - dyy + dyyy);
const float wz0 = 0.5f * ( - dz + 2.0f*dzz - dzzz);
const float wz1 = 0.5f * (2.0f - 5.0f*dzz + 3.0f * dzzz);
const float wz2 = 0.5f * ( dz + 4.0f*dzz - 3.0f * dzzz);
const float wz3 = 0.5f * ( - dzz + dzzz);
__shared__ int f_i[64];
//indices_cubic_(f_i, int(x_floor-1), int(y_floor-1), int(z_floor-1), M, N, O);
int x_ = x_floor-1;
int y_ = y_floor-1;
int z_ = z_floor-1;
if (x_<=2 || y_<=2 || z_<=2 || x_>=N-3 || y_>=M-3 || z_>=O-3) {
//for (int i=0; i<4; ++i)
// for (int j=0; j<4; ++j)
// for (int k=0; k<4; ++k)
//f_i[i+4*(j+4*k)] = access_(M,N,O, x+i-1, y+j-1, z+k-1);
f_i[threadId] = access_(M, N, O, x_+threadIdx.x-1, y_+threadIdx.y-1, z_+threadIdx.z-1);
} else {
//for (int i=0; i<4; ++i)
// for (int j=0; j<4; ++j)
// for (int k=0; k<4; ++k)
// f_i[i+4*(j+4*k)] = access_unchecked_(M,N,O, x+i-1, y+j-1, z+k-1);
f_i[threadId] = access_unchecked_(M, N, O, x_+threadIdx.x-1, y_+threadIdx.y-1, z_+threadIdx.z-1);
}
__syncthreads();
if (threadId == 0) {
pO[blockId] =
wz0*(
wy0*(wx0 * pF[f_i[0]] + wx1 * pF[f_i[1]] + wx2 * pF[f_i[2]] + wx3 * pF[f_i[3]]) +
wy1*(wx0 * pF[f_i[4]] + wx1 * pF[f_i[5]] + wx2 * pF[f_i[6]] + wx3 * pF[f_i[7]]) +
wy2*(wx0 * pF[f_i[8]] + wx1 * pF[f_i[9]] + wx2 * pF[f_i[10]] + wx3 * pF[f_i[11]]) +
wy3*(wx0 * pF[f_i[12]] + wx1 * pF[f_i[13]] + wx2 * pF[f_i[14]] + wx3 * pF[f_i[15]])
) +
wz1*(
wy0*(wx0 * pF[f_i[16]] + wx1 * pF[f_i[17]] + wx2 * pF[f_i[18]] + wx3 * pF[f_i[19]]) +
wy1*(wx0 * pF[f_i[20]] + wx1 * pF[f_i[21]] + wx2 * pF[f_i[22]] + wx3 * pF[f_i[23]]) +
wy2*(wx0 * pF[f_i[24]] + wx1 * pF[f_i[25]] + wx2 * pF[f_i[26]] + wx3 * pF[f_i[27]]) +
wy3*(wx0 * pF[f_i[28]] + wx1 * pF[f_i[29]] + wx2 * pF[f_i[30]] + wx3 * pF[f_i[31]])
) +
wz2*(
wy0*(wx0 * pF[f_i[32]] + wx1 * pF[f_i[33]] + wx2 * pF[f_i[34]] + wx3 * pF[f_i[35]]) +
wy1*(wx0 * pF[f_i[36]] + wx1 * pF[f_i[37]] + wx2 * pF[f_i[38]] + wx3 * pF[f_i[39]]) +
wy2*(wx0 * pF[f_i[40]] + wx1 * pF[f_i[41]] + wx2 * pF[f_i[42]] + wx3 * pF[f_i[43]]) +
wy3*(wx0 * pF[f_i[44]] + wx1 * pF[f_i[45]] + wx2 * pF[f_i[46]] + wx3 * pF[f_i[47]])
) +
wz3*(
wy0*(wx0 * pF[f_i[48]] + wx1 * pF[f_i[49]] + wx2 * pF[f_i[50]] + wx3 * pF[f_i[51]]) +
wy1*(wx0 * pF[f_i[52]] + wx1 * pF[f_i[53]] + wx2 * pF[f_i[54]] + wx3 * pF[f_i[55]]) +
wy2*(wx0 * pF[f_i[56]] + wx1 * pF[f_i[57]] + wx2 * pF[f_i[58]] + wx3 * pF[f_i[59]]) +
wy3*(wx0 * pF[f_i[60]] + wx1 * pF[f_i[61]] + wx2 * pF[f_i[62]] + wx3 * pF[f_i[63]])
);
}
}
//
// Allocates GPU memory, copies the data to GPU memory, computes interpolation and copies data back to CPU
// pF - pyramid image
// pZ - z indices (what layer of the pyramid should be at x,y point)
// p0 - output image
// h - height of the image
// w - width of the image
// nL - number of levels in the pyramid
// method - one of "nearest", "linear" or "cubic"
//
void ba_interp3_GPU(float *pF, float *pZ, float *&pO, int h, int w, int nL, const char *method) {
cudaError_t cudaerr;
//cudaerr = cudaSetDevice(1);
int M = h;
int N = w;
int O = nL;
int ND = h*w;
//float *pF_f = new float[M*N*O];
//float *pZ_f = new float[M*N];
//float *pO_f = new float[M*N];
//double2float(pF, pF_f, M*N*O);
//double2float(pZ, pZ_f, M*N);
//double2float(pO, pO_f, M*N);
float *pF_d;
float *pZ_d;
float *pO_d;
cudaerr = cudaMalloc((void **) &pF_d, M*N*O*sizeof(float)); gpuErrchk(cudaerr);
cudaerr = cudaMalloc((void **) &pZ_d, M*N*sizeof(float)); gpuErrchk(cudaerr);
cudaerr = cudaMalloc((void **) &pO_d, M*N*sizeof(float)); gpuErrchk(cudaerr);
cudaerr = cudaMemcpy(pF_d, pF, M*N*O*sizeof(float), cudaMemcpyHostToDevice); gpuErrchk(cudaerr);
cudaerr = cudaMemcpy(pZ_d, pZ, M*N*sizeof(float), cudaMemcpyHostToDevice); gpuErrchk(cudaerr);
//cudaerr = cudaMemcpy(pO_d, pO, M*N*sizeof(float), cudaMemcpyHostToDevice); gpuErrchk(cudaerr);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 block_size(4, 4, 4);
dim3 num_blocks(M, N);
if (strcmp(method, "nearest") == 0) {
//interpolate_nearest(pO_f, pF_f, pX_f, pY_f, pZ_f, ND, M, N, O);
} else if (strcmp(method, "linear") == 0) {
//interpolate_linear(pO_f, pF_f, pX_f, pY_f, pZ_f, ND, M, N, O);
} else if (strcmp(method, "cubic") == 0) {
cudaEventRecord(start);
interpolate_bicubic_GPU <<< num_blocks, block_size >>> (pO_d, pF_d, pZ_d, ND, M, N, O);
cudaEventRecord(stop);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
} else {
printf("Unimplemented interpolation method.\n");
}
//cudaerr = cudaGetLastError();
//if (cudaerr != cudaSuccess) {
// printf("Kernel launch failed with error \"%s\".\n", cudaGetErrorString(cudaerr));
//}
cudaerr = cudaMemcpy(pO, pO_d, M*N*sizeof(float), cudaMemcpyDeviceToHost); gpuErrchk(cudaerr);
cudaEventSynchronize(stop);
float msec = 0;
cudaEventElapsedTime(&msec, start, stop);
//printf("interpolate_bicubic took %0.3f msec\n", msec);
// for (int i = 0; i < 25; i++) {
// printf("%0.0f ", pO[i]);
// }
// printf("\n");
cudaFree(pF_d);
cudaFree(pZ_d);
cudaFree(pO_d);
}
#define WARP_SIZE 32
#define BLOCK_SIZE (12*WARP_SIZE)
__global__ void reduce(float *dDst, const float *dSrc, uint dim, bool findMin)
{
__shared__ float cache[BLOCK_SIZE];
uint gix = threadIdx.x + blockDim.x*blockIdx.x;
#define tid threadIdx.x
float acc = CUDART_NAN_F;
while (gix < dim) {
if (findMin)
acc = fmin(acc, dSrc[gix]);
else
acc = fmax(acc, dSrc[gix]);
gix += blockDim.x*gridDim.x;
}
cache[tid] = acc;
uint active = blockDim.x >> 1;
do {
__syncthreads();
if (tid < active)
if (findMin)
cache[tid] = fmin(cache[tid], cache[tid+active]);
else
cache[tid] = fmax(cache[tid], cache[tid+active]);
active >>= 1;
} while (active > 0);
if (tid == 0)
dDst[blockIdx.x] = cache[0];
}
#define CUDART_PI_F 3.141592654f
__global__ void compute_eyefreq_cones(int h, int w, int gaze_x, int gaze_y, float CTO,
float alpha, float epsilon2, float dotpitch,
float viewingdist, float *eyefreq_cones_d) {
int threadX = blockIdx.x*blockDim.x + threadIdx.x;
int threadY = blockIdx.y*blockDim.y + threadIdx.y;
int threadId = threadX*blockDim.y*gridDim.y + threadY;
if (threadX < h && threadY < w) {
float ex = threadX - gaze_x;
float ey = threadY - gaze_y;
// eradius is the radial distance between each point and the point
// of gaze in pixels
float eradius = sqrt(ex*ex + ey*ey)*dotpitch;
// calculate ec, the eccentricity from the foveal center, for each
// point in the image. ec is in degrees.
float ec = 180.0f*atanf(eradius/viewingdist)/CUDART_PI_F;
float eyefreq_cones = alpha*(ec+epsilon2);
eyefreq_cones = epsilon2/eyefreq_cones;
eyefreq_cones = eyefreq_cones * logf(1/CTO);
eyefreq_cones = pow(eyefreq_cones, 0.3f);
eyefreq_cones_d[threadId] = eyefreq_cones;
// if (threadX < 5 && threadY < 5) {
// printf("threadIdx=(%i %i) threadX=%i threadY=%i threadId=%i\n",
// threadIdx.x, threadIdx.y, threadX, threadY, threadId);
// printf("eyefreq_cones_d[%i]=%f\n", threadId, eyefreq_cones);
// }
}
}
__global__ void compute_pyrlevel_cones(int h, int w, float* min_array_d, float* max_array_d, int num_levels,
float* eyefreq_cones_d, float* pyrlevel_cones) {
int threadX = blockIdx.x*blockDim.x + threadIdx.x;
int threadY = blockIdx.y*blockDim.y + threadIdx.y;
int threadId = threadX*blockDim.y*gridDim.y + threadY;
if (threadX < h && threadY < w) {
float eyefreq_cones = eyefreq_cones_d[threadId];
eyefreq_cones = (eyefreq_cones-min_array_d[0])/(max_array_d[0]-min_array_d[0]);
// pyrlevel is the fractional level of the pyramid which must be
// used at each pixel in order to match the foveal resolution
// function defined above.
//pyrlevel = maxfreq ./ eyefreq;
//divide(maxfreq, eyefreq_cones, pyrlevel_cones);
// constrain pyrlevel in order to conform to the levels of the
// pyramid which have been computed.
eyefreq_cones = 1 - eyefreq_cones;
pyrlevel_cones[threadId] = max(0.0f, min((float)num_levels, (num_levels-1)*eyefreq_cones));
}
}
__global__ void compute_eyefreq_rods(int h, int w, int gaze_x, int gaze_y, float *eyefreq_rods_d) {
int threadX = blockIdx.x*blockDim.x + threadIdx.x;
int threadY = blockIdx.y*blockDim.y + threadIdx.y;
int threadId = threadX*blockDim.y*gridDim.y + threadY;
float p[6] = {8.8814e-11, -1.6852e-07, 1.1048e-04, -3.1856e-02, 3.7501e+00, -3.0283e+00};
if (threadX < h && threadY < w) {
float ex = threadX - gaze_x;
float ey = threadY - gaze_y;
// eradius is the radial distance between each point and the point
// of gaze in meters
float dist_px = sqrt(ex*ex + ey*ey);
//eyefreq_rods = polyval(dist_px, p, 5);
float eyefreq_rods = p[0];
for (int i = 1; i <= 5; i++) {
eyefreq_rods = eyefreq_rods * dist_px + p[i];
}
eyefreq_rods_d[threadId] = eyefreq_rods;
}
}
__global__ void compute_pyrlevel_rods(int h, int w, float* max_array_d, int num_levels,
float* eyefreq_rods_d, float* pyrlevel_rods) {
int threadX = blockIdx.x*blockDim.x + threadIdx.x;
int threadY = blockIdx.y*blockDim.y + threadIdx.y;
int threadId = threadX*blockDim.y*gridDim.y + threadY;
if (threadX < h && threadY < w) {
float eyefreq_rods = eyefreq_rods_d[threadId];
eyefreq_rods = eyefreq_rods/max_array_d[0];
eyefreq_rods = 1 - eyefreq_rods;
pyrlevel_rods[threadId] = max(0.0f, min((float) num_levels, num_levels*eyefreq_rods+2));
}
}
void preprocess_GPU(int h, int w, float gaze_x, float gaze_y, int num_levels,
double CTO, double alpha, double epsilon2, double dotpitch, double viewingdist,
float* pyrlevel_cones, float* pyrlevel_rods, bool rods_and_cones){
cudaError_t cudaerr;
float *pyrlevel_cones_d;
float *pyrlevel_rods_d;
float *eyefreq_cones_d;
float *min_array_d;
float *max_array_d;
cudaerr = cudaMalloc((void **) &pyrlevel_cones_d, h*w*sizeof(float)); gpuErrchk(cudaerr);
cudaerr = cudaMalloc((void **) &pyrlevel_rods_d, h*w*sizeof(float)); gpuErrchk(cudaerr);
cudaerr = cudaMalloc((void **) &eyefreq_cones_d, h*w*sizeof(float)); gpuErrchk(cudaerr);
int num_threads = 32;
dim3 block_size(num_threads, num_threads, 1);
dim3 num_blocks((int) ceil(h/(double)num_threads), (int) ceil(w/(double)num_threads), 1);
//printf("height = %i width = %i BLOCK SIZE (64, 64) NUM BLOCKS (%f, %f) \n", h, w, ceil(h/(double)num_threads), ceil(w/(double)num_threads));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
compute_eyefreq_cones <<< num_blocks, block_size >>> (h, w, gaze_x, gaze_y, CTO, alpha, epsilon2, dotpitch, viewingdist, eyefreq_cones_d);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
int nblocks = ceil(h*w/(float)BLOCK_SIZE);
cudaerr = cudaMalloc((void **) &min_array_d, nblocks*sizeof(float)); gpuErrchk(cudaerr);
cudaerr = cudaMalloc((void **) &max_array_d, nblocks*sizeof(float)); gpuErrchk(cudaerr);
reduce<<<nblocks,BLOCK_SIZE>>>(min_array_d, eyefreq_cones_d, h*w, true);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
reduce<<<1,BLOCK_SIZE>>>(min_array_d, min_array_d, nblocks, true);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
reduce<<<nblocks,BLOCK_SIZE>>>(max_array_d, eyefreq_cones_d, h*w, false);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
reduce<<<1,BLOCK_SIZE>>>(max_array_d, max_array_d, nblocks, false);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
compute_pyrlevel_cones <<< num_blocks, block_size >>> (h, w, min_array_d, max_array_d, num_levels, eyefreq_cones_d, pyrlevel_cones_d);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
cudaerr = cudaMemcpy(pyrlevel_cones, pyrlevel_cones_d, h*w*sizeof(float), cudaMemcpyDeviceToHost); gpuErrchk(cudaerr);
if (rods_and_cones) {
compute_eyefreq_rods <<< num_blocks, block_size >>> (h, w, gaze_x, gaze_y, eyefreq_cones_d);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
reduce<<<nblocks,BLOCK_SIZE>>>(max_array_d, eyefreq_cones_d, h*w, false);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
reduce<<<1,BLOCK_SIZE>>>(max_array_d, max_array_d, nblocks, false);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
compute_pyrlevel_rods <<< num_blocks, block_size >>> (h, w, max_array_d, num_levels, eyefreq_cones_d, pyrlevel_rods_d);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
cudaerr = cudaMemcpy(pyrlevel_rods, pyrlevel_rods_d, h*w*sizeof(float), cudaMemcpyDeviceToHost); gpuErrchk(cudaerr);
cudaerr = cudaGetLastError(); gpuErrchk(cudaerr);
}
cudaEventRecord(stop, 0);
cudaFree(pyrlevel_cones_d);
cudaFree(pyrlevel_rods_d);
cudaFree(eyefreq_cones_d);
cudaFree(min_array_d);
cudaFree(max_array_d);
} | #include <hip/hip_runtime.h>
void extern ba_interp3_GPU(float *pF, float *pZ, float *&pO, int h, int w, int nL, const char *method);
void extern preprocess_GPU(int h, int w, float gaze_x, float gaze_y, int num_levels,
double CTO, double alpha, double epsilon2, double dotpitch, double viewingdist,
float* pyrlevel_cones, float* pyrlevel_rods, bool rods_and_cones); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
void extern ba_interp3_GPU(float *pF, float *pZ, float *&pO, int h, int w, int nL, const char *method);
void extern preprocess_GPU(int h, int w, float gaze_x, float gaze_y, int num_levels,
double CTO, double alpha, double epsilon2, double dotpitch, double viewingdist,
float* pyrlevel_cones, float* pyrlevel_rods, bool rods_and_cones); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
void extern ba_interp3_GPU(float *pF, float *pZ, float *&pO, int h, int w, int nL, const char *method);
void extern preprocess_GPU(int h, int w, float gaze_x, float gaze_y, int num_levels,
double CTO, double alpha, double epsilon2, double dotpitch, double viewingdist,
float* pyrlevel_cones, float* pyrlevel_rods, bool rods_and_cones); | .text
.file "ba_interp3.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000542d3_00000000-6_ba_interp3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17access_unchecked_iiiiii
.type _Z17access_unchecked_iiiiii, @function
_Z17access_unchecked_iiiiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z17access_unchecked_iiiiii, .-_Z17access_unchecked_iiiiii
.globl _Z53__device_stub__Z23interpolate_bicubic_GPUPfPKfS1_mmmmPfPKfS1_mmmm
.type _Z53__device_stub__Z23interpolate_bicubic_GPUPfPKfS1_mmmmPfPKfS1_mmmm, @function
_Z53__device_stub__Z23interpolate_bicubic_GPUPfPKfS1_mmmmPfPKfS1_mmmm:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23interpolate_bicubic_GPUPfPKfS1_mmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z53__device_stub__Z23interpolate_bicubic_GPUPfPKfS1_mmmmPfPKfS1_mmmm, .-_Z53__device_stub__Z23interpolate_bicubic_GPUPfPKfS1_mmmmPfPKfS1_mmmm
.globl _Z23interpolate_bicubic_GPUPfPKfS1_mmmm
.type _Z23interpolate_bicubic_GPUPfPKfS1_mmmm, @function
_Z23interpolate_bicubic_GPUPfPKfS1_mmmm:
.LFB2088:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z53__device_stub__Z23interpolate_bicubic_GPUPfPKfS1_mmmmPfPKfS1_mmmm
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z23interpolate_bicubic_GPUPfPKfS1_mmmm, .-_Z23interpolate_bicubic_GPUPfPKfS1_mmmm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/TsotsosLab/STAR-FC/master/src/ba_interp3.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "ERROR: \"%s\" in %s:%d\n"
.LC2:
.string "nearest"
.LC3:
.string "linear"
.LC4:
.string "cubic"
.section .rodata.str1.8
.align 8
.LC5:
.string "Unimplemented interpolation method.\n"
.text
.globl _Z14ba_interp3_GPUPfS_RS_iiiPKc
.type _Z14ba_interp3_GPUPfS_RS_iiiPKc, @function
_Z14ba_interp3_GPUPfS_RS_iiiPKc:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r12d
movl %r8d, %r13d
movl %r9d, %r15d
movq 176(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl %ecx, %r14d
imull %r8d, %r14d
movl %r9d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
movslq %r14d, %r14
leaq 0(,%r14,4), %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L26
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $4, 80(%rsp)
movl $4, 84(%rsp)
movl $4, 88(%rsp)
movl %r12d, 92(%rsp)
movl %r13d, 96(%rsp)
movl $1, 100(%rsp)
leaq .LC2(%rip), %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
je .L19
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
je .L19
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L20
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L21:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
je .L19
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $218, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L25:
movl %eax, %ebp
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $192, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L26:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $193, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L27:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $194, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $197, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $198, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L30:
subq $8, %rsp
.cfi_def_cfa_offset 184
movslq %r15d, %r15
pushq %r15
.cfi_def_cfa_offset 192
movslq %r13d, %r9
movslq %r12d, %r8
movq %r14, %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z53__device_stub__Z23interpolate_bicubic_GPUPfPKfS1_mmmmPfPKfS1_mmmm
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L21
.L20:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L19:
movq 24(%rsp), %rax
movq (%rax), %rdi
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $228, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z14ba_interp3_GPUPfS_RS_iiiPKc, .-_Z14ba_interp3_GPUPfS_RS_iiiPKc
.globl _Z30__device_stub__Z6reducePfPKfjbPfPKfjb
.type _Z30__device_stub__Z6reducePfPKfjbPfPKfjb, @function
_Z30__device_stub__Z6reducePfPKfjbPfPKfjb:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movb %cl, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducePfPKfjb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z30__device_stub__Z6reducePfPKfjbPfPKfjb, .-_Z30__device_stub__Z6reducePfPKfjbPfPKfjb
.globl _Z6reducePfPKfjb
.type _Z6reducePfPKfjb, @function
_Z6reducePfPKfjb:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %cl, %ecx
call _Z30__device_stub__Z6reducePfPKfjbPfPKfjb
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z6reducePfPKfjb, .-_Z6reducePfPKfjb
.globl _Z50__device_stub__Z21compute_eyefreq_conesiiiifffffPfiiiifffffPf
.type _Z50__device_stub__Z21compute_eyefreq_conesiiiifffffPfiiiifffffPf, @function
_Z50__device_stub__Z21compute_eyefreq_conesiiiifffffPfiiiifffffPf:
.LFB2091:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21compute_eyefreq_conesiiiifffffPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z50__device_stub__Z21compute_eyefreq_conesiiiifffffPfiiiifffffPf, .-_Z50__device_stub__Z21compute_eyefreq_conesiiiifffffPfiiiifffffPf
.globl _Z21compute_eyefreq_conesiiiifffffPf
.type _Z21compute_eyefreq_conesiiiifffffPf, @function
_Z21compute_eyefreq_conesiiiifffffPf:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z21compute_eyefreq_conesiiiifffffPfiiiifffffPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z21compute_eyefreq_conesiiiifffffPf, .-_Z21compute_eyefreq_conesiiiifffffPf
.globl _Z51__device_stub__Z22compute_pyrlevel_conesiiPfS_iS_S_iiPfS_iS_S_
.type _Z51__device_stub__Z22compute_pyrlevel_conesiiPfS_iS_S_iiPfS_iS_S_, @function
_Z51__device_stub__Z22compute_pyrlevel_conesiiPfS_iS_S_iiPfS_iS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22compute_pyrlevel_conesiiPfS_iS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z51__device_stub__Z22compute_pyrlevel_conesiiPfS_iS_S_iiPfS_iS_S_, .-_Z51__device_stub__Z22compute_pyrlevel_conesiiPfS_iS_S_iiPfS_iS_S_
.globl _Z22compute_pyrlevel_conesiiPfS_iS_S_
.type _Z22compute_pyrlevel_conesiiPfS_iS_S_, @function
_Z22compute_pyrlevel_conesiiPfS_iS_S_:
.LFB2094:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z22compute_pyrlevel_conesiiPfS_iS_S_iiPfS_iS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z22compute_pyrlevel_conesiiPfS_iS_S_, .-_Z22compute_pyrlevel_conesiiPfS_iS_S_
.globl _Z44__device_stub__Z20compute_eyefreq_rodsiiiiPfiiiiPf
.type _Z44__device_stub__Z20compute_eyefreq_rodsiiiiPfiiiiPf, @function
_Z44__device_stub__Z20compute_eyefreq_rodsiiiiPfiiiiPf:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20compute_eyefreq_rodsiiiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z44__device_stub__Z20compute_eyefreq_rodsiiiiPfiiiiPf, .-_Z44__device_stub__Z20compute_eyefreq_rodsiiiiPfiiiiPf
.globl _Z20compute_eyefreq_rodsiiiiPf
.type _Z20compute_eyefreq_rodsiiiiPf, @function
_Z20compute_eyefreq_rodsiiiiPf:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20compute_eyefreq_rodsiiiiPfiiiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z20compute_eyefreq_rodsiiiiPf, .-_Z20compute_eyefreq_rodsiiiiPf
.globl _Z48__device_stub__Z21compute_pyrlevel_rodsiiPfiS_S_iiPfiS_S_
.type _Z48__device_stub__Z21compute_pyrlevel_rodsiiPfiS_S_iiPfiS_S_, @function
_Z48__device_stub__Z21compute_pyrlevel_rodsiiPfiS_S_iiPfiS_S_:
.LFB2097:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L69
.L65:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21compute_pyrlevel_rodsiiPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L65
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z48__device_stub__Z21compute_pyrlevel_rodsiiPfiS_S_iiPfiS_S_, .-_Z48__device_stub__Z21compute_pyrlevel_rodsiiPfiS_S_iiPfiS_S_
.globl _Z21compute_pyrlevel_rodsiiPfiS_S_
.type _Z21compute_pyrlevel_rodsiiPfiS_S_, @function
_Z21compute_pyrlevel_rodsiiPfiS_S_:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z21compute_pyrlevel_rodsiiPfiS_S_iiPfiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z21compute_pyrlevel_rodsiiPfiS_S_, .-_Z21compute_pyrlevel_rodsiiPfiS_S_
.globl _Z14preprocess_GPUiiffidddddPfS_b
.type _Z14preprocess_GPUiiffidddddPfS_b, @function
_Z14preprocess_GPUiiffidddddPfS_b:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movl %edi, %ebp
movl %esi, %r12d
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
movl %edx, 68(%rsp)
movsd %xmm2, 16(%rsp)
movsd %xmm3, 24(%rsp)
movsd %xmm4, 32(%rsp)
movsd %xmm5, 40(%rsp)
movsd %xmm6, 48(%rsp)
movq %rcx, 56(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 64(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl %edi, %r13d
imull %esi, %r13d
movslq %r13d, %rbx
salq $2, %rbx
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L107
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L108
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L109
movl $32, 136(%rsp)
movl $32, 140(%rsp)
movl $1, 144(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
mulsd .LC7(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC16(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC8(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L77
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC10(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L77:
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC7(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC16(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC8(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L78
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC10(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L78:
cvttsd2sil %xmm4, %eax
movl %eax, 148(%rsp)
cvttsd2sil %xmm1, %eax
movl %eax, 152(%rsp)
movl $1, 156(%rsp)
leaq 120(%rsp), %rdi
call cudaEventCreate@PLT
leaq 128(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 120(%rsp), %rdi
call cudaEventRecord@PLT
movl 144(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 136(%rsp), %rdx
movq 148(%rsp), %rdi
movl 156(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L110
.L79:
call cudaGetLastError@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L111
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
divss .LC11(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC15(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC12(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L81
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC14(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L81:
cvttss2sil %xmm3, %r15d
movslq %r15d, %r14
salq $2, %r14
leaq 104(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L112
leaq 112(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L113
movl $384, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl %r15d, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 172(%rsp), %rdx
movl $1, %ecx
movq 160(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L114
.L84:
call cudaGetLastError@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L115
movl $384, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 172(%rsp), %rdx
movl $1, %ecx
movq 160(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L116
.L86:
call cudaGetLastError@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L117
movl $384, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl %r15d, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 172(%rsp), %rdx
movl $1, %ecx
movq 160(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L118
.L88:
call cudaGetLastError@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L119
movl $384, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 172(%rsp), %rdx
movl $1, %ecx
movq 160(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L120
.L90:
call cudaGetLastError@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L121
movl 144(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 136(%rsp), %rdx
movq 148(%rsp), %rdi
movl 156(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L122
.L92:
call cudaGetLastError@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L123
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L124
cmpb $0, 64(%rsp)
jne .L125
.L95:
movl $0, %esi
movq 128(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L126
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L107:
.cfi_restore_state
movl %eax, %r14d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $406, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L108:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $407, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L109:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $408, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L110:
pxor %xmm0, %xmm0
cvtsd2ss 16(%rsp), %xmm0
cvttss2sil 12(%rsp), %ecx
cvttss2sil 8(%rsp), %edx
movq 96(%rsp), %r8
pxor %xmm4, %xmm4
cvtsd2ss 48(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 40(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 32(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 24(%rsp), %xmm1
movl %r12d, %esi
movl %ebp, %edi
call _Z50__device_stub__Z21compute_eyefreq_conesiiiifffffPfiiiifffffPf
jmp .L79
.L111:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $422, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L112:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $426, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L113:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $427, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L114:
movl $1, %ecx
movl %r13d, %edx
movq 96(%rsp), %rsi
movq 104(%rsp), %rdi
call _Z30__device_stub__Z6reducePfPKfjbPfPKfjb
jmp .L84
.L115:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $430, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L116:
movq 104(%rsp), %rdi
movl $1, %ecx
movl %r15d, %edx
movq %rdi, %rsi
call _Z30__device_stub__Z6reducePfPKfjbPfPKfjb
jmp .L86
.L117:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $433, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L118:
movl $0, %ecx
movl %r13d, %edx
movq 96(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z30__device_stub__Z6reducePfPKfjbPfPKfjb
jmp .L88
.L119:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $436, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L120:
movq 112(%rsp), %rdi
movl $0, %ecx
movl %r15d, %edx
movq %rdi, %rsi
call _Z30__device_stub__Z6reducePfPKfjbPfPKfjb
jmp .L90
.L121:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $439, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L122:
subq $8, %rsp
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
movq 112(%rsp), %r9
movl 84(%rsp), %r8d
movq 128(%rsp), %rcx
movq 120(%rsp), %rdx
movl %r12d, %esi
movl %ebp, %edi
call _Z51__device_stub__Z22compute_pyrlevel_conesiiPfS_iS_S_iiPfS_iS_S_
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L92
.L123:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $442, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L124:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $444, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L125:
movl 144(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 136(%rsp), %rdx
movq 148(%rsp), %rdi
movl 156(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L127
.L96:
call cudaGetLastError@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L128
movl $384, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl %r15d, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 172(%rsp), %rdx
movl $1, %ecx
movq 160(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L129
.L98:
call cudaGetLastError@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L130
movl $384, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 172(%rsp), %rdx
movl $1, %ecx
movq 160(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L131
.L100:
call cudaGetLastError@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L132
movl 144(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 136(%rsp), %rdx
movq 148(%rsp), %rdi
movl 156(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L133
.L102:
call cudaGetLastError@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L134
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L135
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
je .L95
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $460, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L127:
cvttss2sil 12(%rsp), %ecx
cvttss2sil 8(%rsp), %edx
movq 96(%rsp), %r8
movl %r12d, %esi
movl %ebp, %edi
call _Z44__device_stub__Z20compute_eyefreq_rodsiiiiPfiiiiPf
jmp .L96
.L128:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $448, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L129:
movl $0, %ecx
movl %r13d, %edx
movq 96(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z30__device_stub__Z6reducePfPKfjbPfPKfjb
jmp .L98
.L130:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $451, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r13d, %edi
call exit@PLT
.L131:
movq 112(%rsp), %rdi
movl $0, %ecx
movl %r15d, %edx
movq %rdi, %rsi
call _Z30__device_stub__Z6reducePfPKfjbPfPKfjb
jmp .L100
.L132:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $454, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r13d, %edi
call exit@PLT
.L133:
movq 88(%rsp), %r9
movq 96(%rsp), %r8
movl 68(%rsp), %ecx
movq 112(%rsp), %rdx
movl %r12d, %esi
movl %ebp, %edi
call _Z48__device_stub__Z21compute_pyrlevel_rodsiiPfiS_S_iiPfiS_S_
jmp .L102
.L134:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $457, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L135:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $459, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L126:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z14preprocess_GPUiiffidddddPfS_b, .-_Z14preprocess_GPUiiffidddddPfS_b
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z21compute_pyrlevel_rodsiiPfiS_S_"
.align 8
.LC18:
.string "_Z20compute_eyefreq_rodsiiiiPf"
.align 8
.LC19:
.string "_Z22compute_pyrlevel_conesiiPfS_iS_S_"
.align 8
.LC20:
.string "_Z21compute_eyefreq_conesiiiifffffPf"
.section .rodata.str1.1
.LC21:
.string "_Z6reducePfPKfjb"
.section .rodata.str1.8
.align 8
.LC22:
.string "_Z23interpolate_bicubic_GPUPfPKfS1_mmmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2100:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z21compute_pyrlevel_rodsiiPfiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z20compute_eyefreq_rodsiiiiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z22compute_pyrlevel_conesiiPfS_iS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z21compute_eyefreq_conesiiiifffffPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePfPKfjb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z23interpolate_bicubic_GPUPfPKfS1_mmmm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1067450368
.align 8
.LC8:
.long 0
.long 1127219200
.align 8
.LC10:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1136656384
.align 4
.LC12:
.long 1258291200
.align 4
.LC14:
.long 1065353216
.set .LC15,.LC16+4
.section .rodata.cst8
.align 8
.LC16:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ba_interp3.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //xfail:TIMEOUT
//--gridDim=64 --blockDim=128
#include "common.h"
template <unsigned int blockSize, bool nIsPow2> __global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n);
template __global__ void reduceSinglePass<128, true>(const float *g_idata, float *g_odata, unsigned int n);
__device__ unsigned int retirementCount = 0;
template <unsigned int blockSize, bool nIsPow2>
__global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n)
{
//
// PHASE 1: Process all inputs assigned to this block
//
reduceBlocks<blockSize, nIsPow2>(g_idata, g_odata, n);
//
// PHASE 2: Last block finished will process all partial sums
//
if (gridDim.x > 1)
{
const unsigned int tid = threadIdx.x;
__shared__ bool amLast;
extern float __shared__ smem[];
// wait until all outstanding memory instructions in this thread are finished
__threadfence();
// Thread 0 takes a ticket
if (tid==0)
{
unsigned int ticket = atomicInc(&retirementCount, gridDim.x);
// If the ticket ID is equal to the number of blocks, we are the last block!
amLast = (ticket == gridDim.x-1);
}
__syncthreads();
// The last block sums the results of all other blocks
if (amLast)
{
int i = tid;
float mySum = 0;
while (i < gridDim.x)
{
mySum += g_odata[i];
i += blockSize;
}
reduceBlock<blockSize>(smem, mySum, tid);
if (tid==0)
{
g_odata[0] = smem[0];
// reset retirement count so that next run succeeds
retirementCount = 0;
}
}
}
} | code for sm_80
Function : _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R3, 0x100, R2 ; /* 0x0000010003047824 */
/* 0x001fe200078e0202 */
/*0070*/ ISETP.GT.U32.AND P2, PT, R2.reuse, 0x3f, PT ; /* 0x0000003f0200780c */
/* 0x040fe40003f44070 */
/*0080*/ SHF.L.U32 R0, R2, 0x2, RZ ; /* 0x0000000202007819 */
/* 0x000fe400000006ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*00a0*/ @P0 BRA 0x190 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*00d0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00e0*/ IADD3 R6, R8, 0x80, RZ ; /* 0x0000008008067810 */
/* 0x000fd20007ffe0ff */
/*00f0*/ IMAD.WIDE.U32 R4, R8, R7, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc800078e0007 */
/*0100*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e0007 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */
/* 0x000fca00078e00ff */
/*0140*/ LEA R8, R11, R8, 0x8 ; /* 0x000000080b087211 */
/* 0x000fc800078e40ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe20003f06070 */
/*0160*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x004fc80000000000 */
/*0170*/ FADD R9, R9, R6 ; /* 0x0000000609097221 */
/* 0x008fd00000000000 */
/*0180*/ @!P0 BRA 0xd0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ STS [R0+0x10], R9 ; /* 0x0000100900007388 */
/* 0x000fe80000000800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GT.U32.AND P3, PT, R2.reuse, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x040fe40003f64070 */
/*01d0*/ ISETP.NE.AND P4, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f85270 */
/*01e0*/ BSSY B0, 0x380 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*01f0*/ @!P2 LDS R4, [R0+0x110] ; /* 0x000110000004a984 */
/* 0x000e240000000800 */
/*0200*/ @!P2 FADD R9, R9, R4 ; /* 0x000000040909a221 */
/* 0x001fca0000000000 */
/*0210*/ @!P2 STS [R0+0x10], R9 ; /* 0x000010090000a388 */
/* 0x0001e80000000800 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ @P3 BRA 0x370 ; /* 0x0000013000003947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R10, R0, 0x10, RZ ; /* 0x00000010000a7810 */
/* 0x001fca0007ffe0ff */
/*0250*/ LDS R4, [R10+0x80] ; /* 0x000080000a047984 */
/* 0x000e240000000800 */
/*0260*/ FADD R4, R4, R9 ; /* 0x0000000904047221 */
/* 0x001fca0000000000 */
/*0270*/ STS [R10], R4 ; /* 0x000000040a007388 */
/* 0x000fe80000000800 */
/*0280*/ LDS R5, [R10+0x40] ; /* 0x000040000a057984 */
/* 0x000e240000000800 */
/*0290*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*02a0*/ STS [R10], R5 ; /* 0x000000050a007388 */
/* 0x000fe80000000800 */
/*02b0*/ LDS R6, [R10+0x20] ; /* 0x000020000a067984 */
/* 0x000e240000000800 */
/*02c0*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x001fca0000000000 */
/*02d0*/ STS [R10], R6 ; /* 0x000000060a007388 */
/* 0x000fe80000000800 */
/*02e0*/ LDS R7, [R10+0x10] ; /* 0x000010000a077984 */
/* 0x000e240000000800 */
/*02f0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x001fca0000000000 */
/*0300*/ STS [R10], R7 ; /* 0x000000070a007388 */
/* 0x000fe80000000800 */
/*0310*/ LDS R8, [R10+0x8] ; /* 0x000008000a087984 */
/* 0x000e240000000800 */
/*0320*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x001fca0000000000 */
/*0330*/ STS [R10], R8 ; /* 0x000000080a007388 */
/* 0x000fe80000000800 */
/*0340*/ LDS R9, [R10+0x4] ; /* 0x000004000a097984 */
/* 0x000e240000000800 */
/*0350*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x001fca0000000000 */
/*0360*/ STS [R10], R9 ; /* 0x000000090a007388 */
/* 0x0001e40000000800 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0380*/ @!P4 LDS R7, [0x10] ; /* 0x00001000ff07c984 */
/* 0x000e220000000800 */
/*0390*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0f7624 */
/* 0x000fe200078e00ff */
/*03a0*/ @!P4 MOV R4, 0x4 ; /* 0x000000040004c802 */
/* 0x000fc80000000f00 */
/*03b0*/ ISETP.GE.U32.AND P0, PT, R15, 0x2, PT ; /* 0x000000020f00780c */
/* 0x000fe20003f06070 */
/*03c0*/ @!P4 IMAD.WIDE.U32 R4, R3, R4, c[0x0][0x168] ; /* 0x00005a000304c625 */
/* 0x000fca00078e0004 */
/*03d0*/ @!P4 STG.E [R4.64], R7 ; /* 0x000000070400c986 */
/* 0x0011ee000c101904 */
/*03e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x001fe200078e00ff */
/*0400*/ MOV R5, c[0x4][0x4] ; /* 0x0100010000057a02 */
/* 0x000fe20000000f00 */
/*0410*/ MEMBAR.SC.GPU ; /* 0x0000000000007992 */
/* 0x000fec0000002000 */
/*0420*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0430*/ BSSY B0, 0x4c0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0440*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0450*/ @P4 BRA 0x4b0 ; /* 0x0000005000004947 */
/* 0x000fea0003800000 */
/*0460*/ ATOMG.E.INC.STRONG.GPU PT, R3, [R4.64], R15 ; /* 0x0000000f040379a8 */
/* 0x000ea200099ee1c4 */
/*0470*/ IADD3 R6, R15, -0x1, RZ ; /* 0xffffffff0f067810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.NE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x004fc80003f05270 */
/*0490*/ SEL R3, RZ, 0x1, P0 ; /* 0x00000001ff037807 */
/* 0x000fca0000000000 */
/*04a0*/ STS.U8 [RZ], R3 ; /* 0x00000003ff007388 */
/* 0x0001e80000000000 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ LDS.U8 R3, [RZ] ; /* 0x00000000ff037984 */
/* 0x001e240000000000 */
/*04e0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x001fda0003f05270 */
/*04f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0500*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0xc], PT ; /* 0x0000030002007a0c */
/* 0x000fe20003f06070 */
/*0510*/ BSSY B0, 0x8e0 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd600078e00ff */
/*0530*/ @P0 BRA 0x8d0 ; /* 0x0000039000000947 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GE.U32.AND P5, PT, R2, c[0x0][0xc], PT ; /* 0x0000030002007a0c */
/* 0x000fda0003fa6070 */
/*0550*/ @P5 MOV R7, 0x4 ; /* 0x0000000400075802 */
/* 0x000fca0000000f00 */
/*0560*/ @P5 IMAD.WIDE R6, R2, R7, c[0x0][0x168] ; /* 0x00005a0002065625 */
/* 0x000fcc00078e0207 */
/*0570*/ @P5 LDG.E R6, [R6.64] ; /* 0x0000000406065981 */
/* 0x000ea2000c1e1900 */
/*0580*/ @P5 IADD3 R2, R2, 0x80, RZ ; /* 0x0000008002025810 */
/* 0x000fe20007ffe0ff */
/*0590*/ BSSY B1, 0x770 ; /* 0x000001d000017945 */
/* 0x000fe20003800000 */
/*05a0*/ PLOP3.LUT P0, PT, P5, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40002f0e170 */
/*05b0*/ ISETP.GE.U32.AND P1, PT, R2.reuse, c[0x0][0xc], PT ; /* 0x0000030002007a0c */
/* 0x040fe40003f26070 */
/*05c0*/ IADD3 R3, -R2, c[0x0][0xc], RZ ; /* 0x0000030002037a10 */
/* 0x000fc80007ffe1ff */
/*05d0*/ ISETP.LE.U32.OR P1, PT, R3, 0x180, P1 ; /* 0x000001800300780c */
/* 0x000fe20000f23470 */
/*05e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc800078e00ff */
/*05f0*/ @P5 FADD R3, R3, R6 ; /* 0x0000000603035221 */
/* 0x004fd00000000000 */
/*0600*/ @P1 BRA 0x760 ; /* 0x0000015000001947 */
/* 0x000fea0003800000 */
/*0610*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0620*/ IADD3 R15, R15, -0x180, RZ ; /* 0xfffffe800f0f7810 */
/* 0x000fe40007ffe0ff */
/*0630*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0640*/ IADD3 R8, R2.reuse, 0x80, RZ ; /* 0x0000008002087810 */
/* 0x040fe40007ffe0ff */
/*0650*/ IADD3 R10, R2, 0x100, RZ ; /* 0x00000100020a7810 */
/* 0x000fce0007ffe0ff */
/*0660*/ IMAD.WIDE R6, R2.reuse, R13, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x040fe200078e020d */
/*0670*/ IADD3 R12, R2, 0x180, RZ ; /* 0x00000180020c7810 */
/* 0x000fc60007ffe0ff */
/*0680*/ IMAD.WIDE R8, R8, R13.reuse, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x080fe400078e020d */
/*0690*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*06a0*/ IMAD.WIDE R10, R10, R13.reuse, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x080fe400078e020d */
/*06b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*06c0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fe400078e020d */
/*06d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f28000c1e1900 */
/*06e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*06f0*/ IADD3 R2, R2, 0x200, RZ ; /* 0x0000020002027810 */
/* 0x000fc80007ffe0ff */
/*0700*/ ISETP.GE.U32.AND P1, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fe20003f26070 */
/*0710*/ FADD R3, R6, R3 ; /* 0x0000000306037221 */
/* 0x004fc80000000000 */
/*0720*/ FADD R3, R3, R8 ; /* 0x0000000803037221 */
/* 0x008fc80000000000 */
/*0730*/ FADD R3, R3, R10 ; /* 0x0000000a03037221 */
/* 0x010fc80000000000 */
/*0740*/ FADD R3, R3, R12 ; /* 0x0000000c03037221 */
/* 0x020fe20000000000 */
/*0750*/ @!P1 BRA 0x630 ; /* 0xfffffed000009947 */
/* 0x000fea000383ffff */
/*0760*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.GE.U32.AND P1, PT, R2.reuse, c[0x0][0xc], PT ; /* 0x0000030002007a0c */
/* 0x040fe20003f26070 */
/*0780*/ BSSY B1, 0x870 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0790*/ IADD3 R6, -R2, c[0x0][0xc], RZ ; /* 0x0000030002067a10 */
/* 0x000fc80007ffe1ff */
/*07a0*/ ISETP.LE.U32.OR P1, PT, R6, 0x80, P1 ; /* 0x000000800600780c */
/* 0x000fda0000f23470 */
/*07b0*/ @P1 BRA 0x860 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fe40000000f00 */
/*07d0*/ IADD3 R6, R2, 0x80, RZ ; /* 0x0000008002067810 */
/* 0x000fc60007ffe0ff */
/*07e0*/ IMAD.WIDE R8, R2, R7, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fc800078e0207 */
/*07f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe400078e0207 */
/*0800*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0820*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0830*/ IADD3 R2, R2, 0x100, RZ ; /* 0x0000010002027810 */
/* 0x000fe20007ffe0ff */
/*0840*/ FADD R3, R3, R8 ; /* 0x0000000803037221 */
/* 0x004fc80000000000 */
/*0850*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x008fe40000000000 */
/*0860*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0870*/ ISETP.LT.U32.OR P0, PT, R2, c[0x0][0xc], P0 ; /* 0x0000030002007a0c */
/* 0x000fda0000701470 */
/*0880*/ @!P0 BRA 0x8d0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*08a0*/ IMAD.WIDE R6, R2, R7, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fcc00078e0207 */
/*08b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*08c0*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x004fe40000000000 */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08e0*/ STS [R0+0x10], R3 ; /* 0x0000100300007388 */
/* 0x000fe20000000800 */
/*08f0*/ BSSY B0, 0xa90 ; /* 0x0000019000007945 */
/* 0x000fe60003800000 */
/*0900*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0910*/ @!P2 LDS R2, [R0+0x110] ; /* 0x000110000002a984 */
/* 0x000e240000000800 */
/*0920*/ @!P2 FADD R3, R3, R2 ; /* 0x000000020303a221 */
/* 0x001fca0000000000 */
/*0930*/ @!P2 STS [R0+0x10], R3 ; /* 0x000010030000a388 */
/* 0x0001e80000000800 */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ @P3 BRA 0xa80 ; /* 0x0000012000003947 */
/* 0x000fea0003800000 */
/*0960*/ LDS R2, [R0+0x90] ; /* 0x0000900000027984 */
/* 0x001e240000000800 */
/*0970*/ FADD R3, R2, R3 ; /* 0x0000000302037221 */
/* 0x001fca0000000000 */
/*0980*/ STS [R0+0x10], R3 ; /* 0x0000100300007388 */
/* 0x000fe80000000800 */
/*0990*/ LDS R2, [R0+0x50] ; /* 0x0000500000027984 */
/* 0x000e240000000800 */
/*09a0*/ FADD R7, R3, R2 ; /* 0x0000000203077221 */
/* 0x001fca0000000000 */
/*09b0*/ STS [R0+0x10], R7 ; /* 0x0000100700007388 */
/* 0x000fe80000000800 */
/*09c0*/ LDS R2, [R0+0x30] ; /* 0x0000300000027984 */
/* 0x000e240000000800 */
/*09d0*/ FADD R9, R7, R2 ; /* 0x0000000207097221 */
/* 0x001fca0000000000 */
/*09e0*/ STS [R0+0x10], R9 ; /* 0x0000100900007388 */
/* 0x000fe80000000800 */
/*09f0*/ LDS R2, [R0+0x20] ; /* 0x0000200000027984 */
/* 0x000e240000000800 */
/*0a00*/ FADD R11, R9, R2 ; /* 0x00000002090b7221 */
/* 0x001fca0000000000 */
/*0a10*/ STS [R0+0x10], R11 ; /* 0x0000100b00007388 */
/* 0x000fe80000000800 */
/*0a20*/ LDS R2, [R0+0x18] ; /* 0x0000180000027984 */
/* 0x000e240000000800 */
/*0a30*/ FADD R3, R11, R2 ; /* 0x000000020b037221 */
/* 0x001fca0000000000 */
/*0a40*/ STS [R0+0x10], R3 ; /* 0x0000100300007388 */
/* 0x000fe80000000800 */
/*0a50*/ LDS R2, [R0+0x14] ; /* 0x0000140000027984 */
/* 0x000e240000000800 */
/*0a60*/ FADD R7, R3, R2 ; /* 0x0000000203077221 */
/* 0x001fca0000000000 */
/*0a70*/ STS [R0+0x10], R7 ; /* 0x0000100700007388 */
/* 0x0001e40000000800 */
/*0a80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0a90*/ @P4 EXIT ; /* 0x000000000000494d */
/* 0x000fea0003800000 */
/*0aa0*/ LDS R7, [0x10] ; /* 0x00001000ff077984 */
/* 0x000e220000000800 */
/*0ab0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*0ac0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0ad0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*0ae0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //xfail:TIMEOUT
//--gridDim=64 --blockDim=128
#include "common.h"
template <unsigned int blockSize, bool nIsPow2> __global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n);
template __global__ void reduceSinglePass<128, true>(const float *g_idata, float *g_odata, unsigned int n);
__device__ unsigned int retirementCount = 0;
template <unsigned int blockSize, bool nIsPow2>
__global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n)
{
//
// PHASE 1: Process all inputs assigned to this block
//
reduceBlocks<blockSize, nIsPow2>(g_idata, g_odata, n);
//
// PHASE 2: Last block finished will process all partial sums
//
if (gridDim.x > 1)
{
const unsigned int tid = threadIdx.x;
__shared__ bool amLast;
extern float __shared__ smem[];
// wait until all outstanding memory instructions in this thread are finished
__threadfence();
// Thread 0 takes a ticket
if (tid==0)
{
unsigned int ticket = atomicInc(&retirementCount, gridDim.x);
// If the ticket ID is equal to the number of blocks, we are the last block!
amLast = (ticket == gridDim.x-1);
}
__syncthreads();
// The last block sums the results of all other blocks
if (amLast)
{
int i = tid;
float mySum = 0;
while (i < gridDim.x)
{
mySum += g_odata[i];
i += blockSize;
}
reduceBlock<blockSize>(smem, mySum, tid);
if (tid==0)
{
g_odata[0] = smem[0];
// reset retirement count so that next run succeeds
retirementCount = 0;
}
}
}
} | .file "tmpxft_00185b8f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z16reduceSinglePassILj128ELb1EEvPKfPfj,"axG",@progbits,_Z16reduceSinglePassILj128ELb1EEvPKfPfj,comdat
.weak _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.type _Z16reduceSinglePassILj128ELb1EEvPKfPfj, @function
_Z16reduceSinglePassILj128ELb1EEvPKfPfj:
.LFB2104:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16reduceSinglePassILj128ELb1EEvPKfPfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z16reduceSinglePassILj128ELb1EEvPKfPfj, .-_Z16reduceSinglePassILj128ELb1EEvPKfPfj
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16reduceSinglePassILj128ELb1EEvPKfPfj"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "retirementCount"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reduceSinglePassILj128ELb1EEvPKfPfj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15retirementCount(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL15retirementCount
.comm _ZL15retirementCount,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //xfail:TIMEOUT
//--gridDim=64 --blockDim=128
#include "common.h"
template <unsigned int blockSize, bool nIsPow2> __global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n);
template __global__ void reduceSinglePass<128, true>(const float *g_idata, float *g_odata, unsigned int n);
__device__ unsigned int retirementCount = 0;
template <unsigned int blockSize, bool nIsPow2>
__global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n)
{
//
// PHASE 1: Process all inputs assigned to this block
//
reduceBlocks<blockSize, nIsPow2>(g_idata, g_odata, n);
//
// PHASE 2: Last block finished will process all partial sums
//
if (gridDim.x > 1)
{
const unsigned int tid = threadIdx.x;
__shared__ bool amLast;
extern float __shared__ smem[];
// wait until all outstanding memory instructions in this thread are finished
__threadfence();
// Thread 0 takes a ticket
if (tid==0)
{
unsigned int ticket = atomicInc(&retirementCount, gridDim.x);
// If the ticket ID is equal to the number of blocks, we are the last block!
amLast = (ticket == gridDim.x-1);
}
__syncthreads();
// The last block sums the results of all other blocks
if (amLast)
{
int i = tid;
float mySum = 0;
while (i < gridDim.x)
{
mySum += g_odata[i];
i += blockSize;
}
reduceBlock<blockSize>(smem, mySum, tid);
if (tid==0)
{
g_odata[0] = smem[0];
// reset retirement count so that next run succeeds
retirementCount = 0;
}
}
}
} | //xfail:TIMEOUT
//--gridDim=64 --blockDim=128
#include <hip/hip_runtime.h>
#include "common.h"
template <unsigned int blockSize, bool nIsPow2> __global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n);
template __global__ void reduceSinglePass<128, true>(const float *g_idata, float *g_odata, unsigned int n);
__device__ unsigned int retirementCount = 0;
template <unsigned int blockSize, bool nIsPow2>
__global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n)
{
//
// PHASE 1: Process all inputs assigned to this block
//
reduceBlocks<blockSize, nIsPow2>(g_idata, g_odata, n);
//
// PHASE 2: Last block finished will process all partial sums
//
if (gridDim.x > 1)
{
const unsigned int tid = threadIdx.x;
__shared__ bool amLast;
extern float __shared__ smem[];
// wait until all outstanding memory instructions in this thread are finished
__threadfence();
// Thread 0 takes a ticket
if (tid==0)
{
unsigned int ticket = atomicInc(&retirementCount, gridDim.x);
// If the ticket ID is equal to the number of blocks, we are the last block!
amLast = (ticket == gridDim.x-1);
}
__syncthreads();
// The last block sums the results of all other blocks
if (amLast)
{
int i = tid;
float mySum = 0;
while (i < gridDim.x)
{
mySum += g_odata[i];
i += blockSize;
}
reduceBlock<blockSize>(smem, mySum, tid);
if (tid==0)
{
g_odata[0] = smem[0];
// reset retirement count so that next run succeeds
retirementCount = 0;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //xfail:TIMEOUT
//--gridDim=64 --blockDim=128
#include <hip/hip_runtime.h>
#include "common.h"
template <unsigned int blockSize, bool nIsPow2> __global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n);
template __global__ void reduceSinglePass<128, true>(const float *g_idata, float *g_odata, unsigned int n);
__device__ unsigned int retirementCount = 0;
template <unsigned int blockSize, bool nIsPow2>
__global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n)
{
//
// PHASE 1: Process all inputs assigned to this block
//
reduceBlocks<blockSize, nIsPow2>(g_idata, g_odata, n);
//
// PHASE 2: Last block finished will process all partial sums
//
if (gridDim.x > 1)
{
const unsigned int tid = threadIdx.x;
__shared__ bool amLast;
extern float __shared__ smem[];
// wait until all outstanding memory instructions in this thread are finished
__threadfence();
// Thread 0 takes a ticket
if (tid==0)
{
unsigned int ticket = atomicInc(&retirementCount, gridDim.x);
// If the ticket ID is equal to the number of blocks, we are the last block!
amLast = (ticket == gridDim.x-1);
}
__syncthreads();
// The last block sums the results of all other blocks
if (amLast)
{
int i = tid;
float mySum = 0;
while (i < gridDim.x)
{
mySum += g_odata[i];
i += blockSize;
}
reduceBlock<blockSize>(smem, mySum, tid);
if (tid==0)
{
g_odata[0] = smem[0];
// reset retirement count so that next run succeeds
retirementCount = 0;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z16reduceSinglePassILj128ELb1EEvPKfPfj,"axG",@progbits,_Z16reduceSinglePassILj128ELb1EEvPKfPfj,comdat
.protected _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.globl _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.p2align 8
.type _Z16reduceSinglePassILj128ELb1EEvPKfPfj,@function
_Z16reduceSinglePassILj128ELb1EEvPKfPfj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s6, s15
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v1, s6, 8, v0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_lshl_b32 s9, s8, 8
s_mov_b32 s7, 0
.p2align 6
.LBB0_2:
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v4, 0x80, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s9, v1
v_mov_b32_e32 v5, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s7
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s5
v_lshl_add_u32 v4, v0, 2, 4
s_mov_b64 s[2:3], src_shared_base
v_cmp_gt_u32_e64 s2, 64, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
v_cndmask_b32_e64 v2, 0, s3, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b64 s[4:5], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, 4, v5, 0x100
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s5, vcc_lo
flat_load_b32 v5, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v5
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e64 s3, 32, v0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b64 s[10:11], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, 4, v5, 0x80
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
flat_load_b32 v6, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 64, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v6
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v6, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 32, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v6
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v6, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 16, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v6
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v6, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 8, v4
v_add_nc_u32_e32 v4, 4, v4
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v6
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v5, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v5, v3, v5
v_cndmask_b32_e32 v3, 0, v4, vcc_lo
v_cndmask_b32_e64 v4, 0, s11, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v5, v3
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[4:5], s[0:1], 0x8
v_cmp_eq_u32_e64 s0, 0, v0
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v1, 4 :: v_dual_mov_b32 v2, 0
s_lshl_b64 s[6:7], s[6:7], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s4, s6
ds_load_b32 v1, v1
s_addc_u32 s7, s5, s7
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v1, s[6:7]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_lt_u32 s8, 2
s_cbranch_scc1 .LBB0_24
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
buffer_gl1_inv
buffer_gl0_inv
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_13
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s8
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, retirementCount@rel32@lo+4
s_addc_u32 s7, s7, retirementCount@rel32@hi+12
global_atomic_inc_u32 v2, v1, v2, s[6:7] glc
s_add_i32 s6, s8, -1
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s6, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
ds_store_b8 v1, v2
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_u8 v1, v3
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v1
s_cbranch_vccnz .LBB0_24
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s8, v0
s_cbranch_execz .LBB0_18
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s6, 0
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, 0x80, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s8, v1
global_load_b32 v2, v[4:5], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v2
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_16
s_or_b32 exec_lo, exec_lo, s6
.LBB0_18:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_lshl_add_u32 v4, v0, 2, 4
s_mov_b64 s[6:7], src_shared_base
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s2
s_cbranch_execz .LBB0_20
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, 4, v5, 0x100
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_load_b32 v5, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v5
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s3
s_cbranch_execz .LBB0_22
v_lshlrev_b32_e32 v0, 2, v0
s_mov_b64 s[2:3], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, 4, v0, 0x80
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cndmask_b32_e32 v5, 0, v0, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
flat_load_b32 v0, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 64, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v3, v0
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 32, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 16, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 8, v4
v_add_nc_u32_e32 v4, 4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_add_f32 v0, v0, v3 :: v_dual_cndmask_b32 v3, 0, v4
v_cndmask_b32_e64 v4, 0, s3, vcc_lo
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_24
v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, retirementCount@rel32@lo+4
s_addc_u32 s1, s1, retirementCount@rel32@hi+12
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v1, v0, s[4:5]
global_store_b32 v1, v1, s[0:1]
.LBB0_24:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z16reduceSinglePassILj128ELb1EEvPKfPfj,"axG",@progbits,_Z16reduceSinglePassILj128ELb1EEvPKfPfj,comdat
.Lfunc_end0:
.size _Z16reduceSinglePassILj128ELb1EEvPKfPfj, .Lfunc_end0-_Z16reduceSinglePassILj128ELb1EEvPKfPfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected retirementCount
.type retirementCount,@object
.section .bss,"aw",@nobits
.globl retirementCount
.p2align 2, 0x0
retirementCount:
.long 0
.size retirementCount, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym retirementCount
.addrsig_sym smem
.addrsig_sym sdata
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16reduceSinglePassILj128ELb1EEvPKfPfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //xfail:TIMEOUT
//--gridDim=64 --blockDim=128
#include <hip/hip_runtime.h>
#include "common.h"
template <unsigned int blockSize, bool nIsPow2> __global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n);
template __global__ void reduceSinglePass<128, true>(const float *g_idata, float *g_odata, unsigned int n);
__device__ unsigned int retirementCount = 0;
template <unsigned int blockSize, bool nIsPow2>
__global__ void reduceSinglePass(const float *g_idata, float *g_odata, unsigned int n)
{
//
// PHASE 1: Process all inputs assigned to this block
//
reduceBlocks<blockSize, nIsPow2>(g_idata, g_odata, n);
//
// PHASE 2: Last block finished will process all partial sums
//
if (gridDim.x > 1)
{
const unsigned int tid = threadIdx.x;
__shared__ bool amLast;
extern float __shared__ smem[];
// wait until all outstanding memory instructions in this thread are finished
__threadfence();
// Thread 0 takes a ticket
if (tid==0)
{
unsigned int ticket = atomicInc(&retirementCount, gridDim.x);
// If the ticket ID is equal to the number of blocks, we are the last block!
amLast = (ticket == gridDim.x-1);
}
__syncthreads();
// The last block sums the results of all other blocks
if (amLast)
{
int i = tid;
float mySum = 0;
while (i < gridDim.x)
{
mySum += g_odata[i];
i += blockSize;
}
reduceBlock<blockSize>(smem, mySum, tid);
if (tid==0)
{
g_odata[0] = smem[0];
// reset retirement count so that next run succeeds
retirementCount = 0;
}
}
}
} | .text
.file "kernel.hip"
.section .text._Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj,"axG",@progbits,_Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj,comdat
.weak _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj # -- Begin function _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.p2align 4, 0x90
.type _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj,@function
_Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj: # @_Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16reduceSinglePassILj128ELb1EEvPKfPfj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj, .Lfunc_end0-_Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16reduceSinglePassILj128ELb1EEvPKfPfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $retirementCount, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type retirementCount,@object # @retirementCount
.local retirementCount
.comm retirementCount,4,4
.type _Z16reduceSinglePassILj128ELb1EEvPKfPfj,@object # @_Z16reduceSinglePassILj128ELb1EEvPKfPfj
.section .rodata,"a",@progbits
.weak _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.p2align 3, 0x0
_Z16reduceSinglePassILj128ELb1EEvPKfPfj:
.quad _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.size _Z16reduceSinglePassILj128ELb1EEvPKfPfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16reduceSinglePassILj128ELb1EEvPKfPfj"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "retirementCount"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym retirementCount
.addrsig_sym _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R3, 0x100, R2 ; /* 0x0000010003047824 */
/* 0x001fe200078e0202 */
/*0070*/ ISETP.GT.U32.AND P2, PT, R2.reuse, 0x3f, PT ; /* 0x0000003f0200780c */
/* 0x040fe40003f44070 */
/*0080*/ SHF.L.U32 R0, R2, 0x2, RZ ; /* 0x0000000202007819 */
/* 0x000fe400000006ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*00a0*/ @P0 BRA 0x190 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*00d0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00e0*/ IADD3 R6, R8, 0x80, RZ ; /* 0x0000008008067810 */
/* 0x000fd20007ffe0ff */
/*00f0*/ IMAD.WIDE.U32 R4, R8, R7, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc800078e0007 */
/*0100*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e0007 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */
/* 0x000fca00078e00ff */
/*0140*/ LEA R8, R11, R8, 0x8 ; /* 0x000000080b087211 */
/* 0x000fc800078e40ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe20003f06070 */
/*0160*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x004fc80000000000 */
/*0170*/ FADD R9, R9, R6 ; /* 0x0000000609097221 */
/* 0x008fd00000000000 */
/*0180*/ @!P0 BRA 0xd0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ STS [R0+0x10], R9 ; /* 0x0000100900007388 */
/* 0x000fe80000000800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GT.U32.AND P3, PT, R2.reuse, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x040fe40003f64070 */
/*01d0*/ ISETP.NE.AND P4, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f85270 */
/*01e0*/ BSSY B0, 0x380 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*01f0*/ @!P2 LDS R4, [R0+0x110] ; /* 0x000110000004a984 */
/* 0x000e240000000800 */
/*0200*/ @!P2 FADD R9, R9, R4 ; /* 0x000000040909a221 */
/* 0x001fca0000000000 */
/*0210*/ @!P2 STS [R0+0x10], R9 ; /* 0x000010090000a388 */
/* 0x0001e80000000800 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ @P3 BRA 0x370 ; /* 0x0000013000003947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R10, R0, 0x10, RZ ; /* 0x00000010000a7810 */
/* 0x001fca0007ffe0ff */
/*0250*/ LDS R4, [R10+0x80] ; /* 0x000080000a047984 */
/* 0x000e240000000800 */
/*0260*/ FADD R4, R4, R9 ; /* 0x0000000904047221 */
/* 0x001fca0000000000 */
/*0270*/ STS [R10], R4 ; /* 0x000000040a007388 */
/* 0x000fe80000000800 */
/*0280*/ LDS R5, [R10+0x40] ; /* 0x000040000a057984 */
/* 0x000e240000000800 */
/*0290*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*02a0*/ STS [R10], R5 ; /* 0x000000050a007388 */
/* 0x000fe80000000800 */
/*02b0*/ LDS R6, [R10+0x20] ; /* 0x000020000a067984 */
/* 0x000e240000000800 */
/*02c0*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x001fca0000000000 */
/*02d0*/ STS [R10], R6 ; /* 0x000000060a007388 */
/* 0x000fe80000000800 */
/*02e0*/ LDS R7, [R10+0x10] ; /* 0x000010000a077984 */
/* 0x000e240000000800 */
/*02f0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x001fca0000000000 */
/*0300*/ STS [R10], R7 ; /* 0x000000070a007388 */
/* 0x000fe80000000800 */
/*0310*/ LDS R8, [R10+0x8] ; /* 0x000008000a087984 */
/* 0x000e240000000800 */
/*0320*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x001fca0000000000 */
/*0330*/ STS [R10], R8 ; /* 0x000000080a007388 */
/* 0x000fe80000000800 */
/*0340*/ LDS R9, [R10+0x4] ; /* 0x000004000a097984 */
/* 0x000e240000000800 */
/*0350*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x001fca0000000000 */
/*0360*/ STS [R10], R9 ; /* 0x000000090a007388 */
/* 0x0001e40000000800 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0380*/ @!P4 LDS R7, [0x10] ; /* 0x00001000ff07c984 */
/* 0x000e220000000800 */
/*0390*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0f7624 */
/* 0x000fe200078e00ff */
/*03a0*/ @!P4 MOV R4, 0x4 ; /* 0x000000040004c802 */
/* 0x000fc80000000f00 */
/*03b0*/ ISETP.GE.U32.AND P0, PT, R15, 0x2, PT ; /* 0x000000020f00780c */
/* 0x000fe20003f06070 */
/*03c0*/ @!P4 IMAD.WIDE.U32 R4, R3, R4, c[0x0][0x168] ; /* 0x00005a000304c625 */
/* 0x000fca00078e0004 */
/*03d0*/ @!P4 STG.E [R4.64], R7 ; /* 0x000000070400c986 */
/* 0x0011ee000c101904 */
/*03e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x001fe200078e00ff */
/*0400*/ MOV R5, c[0x4][0x4] ; /* 0x0100010000057a02 */
/* 0x000fe20000000f00 */
/*0410*/ MEMBAR.SC.GPU ; /* 0x0000000000007992 */
/* 0x000fec0000002000 */
/*0420*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0430*/ BSSY B0, 0x4c0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0440*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0450*/ @P4 BRA 0x4b0 ; /* 0x0000005000004947 */
/* 0x000fea0003800000 */
/*0460*/ ATOMG.E.INC.STRONG.GPU PT, R3, [R4.64], R15 ; /* 0x0000000f040379a8 */
/* 0x000ea200099ee1c4 */
/*0470*/ IADD3 R6, R15, -0x1, RZ ; /* 0xffffffff0f067810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.NE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x004fc80003f05270 */
/*0490*/ SEL R3, RZ, 0x1, P0 ; /* 0x00000001ff037807 */
/* 0x000fca0000000000 */
/*04a0*/ STS.U8 [RZ], R3 ; /* 0x00000003ff007388 */
/* 0x0001e80000000000 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ LDS.U8 R3, [RZ] ; /* 0x00000000ff037984 */
/* 0x001e240000000000 */
/*04e0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x001fda0003f05270 */
/*04f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0500*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0xc], PT ; /* 0x0000030002007a0c */
/* 0x000fe20003f06070 */
/*0510*/ BSSY B0, 0x8e0 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd600078e00ff */
/*0530*/ @P0 BRA 0x8d0 ; /* 0x0000039000000947 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GE.U32.AND P5, PT, R2, c[0x0][0xc], PT ; /* 0x0000030002007a0c */
/* 0x000fda0003fa6070 */
/*0550*/ @P5 MOV R7, 0x4 ; /* 0x0000000400075802 */
/* 0x000fca0000000f00 */
/*0560*/ @P5 IMAD.WIDE R6, R2, R7, c[0x0][0x168] ; /* 0x00005a0002065625 */
/* 0x000fcc00078e0207 */
/*0570*/ @P5 LDG.E R6, [R6.64] ; /* 0x0000000406065981 */
/* 0x000ea2000c1e1900 */
/*0580*/ @P5 IADD3 R2, R2, 0x80, RZ ; /* 0x0000008002025810 */
/* 0x000fe20007ffe0ff */
/*0590*/ BSSY B1, 0x770 ; /* 0x000001d000017945 */
/* 0x000fe20003800000 */
/*05a0*/ PLOP3.LUT P0, PT, P5, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40002f0e170 */
/*05b0*/ ISETP.GE.U32.AND P1, PT, R2.reuse, c[0x0][0xc], PT ; /* 0x0000030002007a0c */
/* 0x040fe40003f26070 */
/*05c0*/ IADD3 R3, -R2, c[0x0][0xc], RZ ; /* 0x0000030002037a10 */
/* 0x000fc80007ffe1ff */
/*05d0*/ ISETP.LE.U32.OR P1, PT, R3, 0x180, P1 ; /* 0x000001800300780c */
/* 0x000fe20000f23470 */
/*05e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc800078e00ff */
/*05f0*/ @P5 FADD R3, R3, R6 ; /* 0x0000000603035221 */
/* 0x004fd00000000000 */
/*0600*/ @P1 BRA 0x760 ; /* 0x0000015000001947 */
/* 0x000fea0003800000 */
/*0610*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0620*/ IADD3 R15, R15, -0x180, RZ ; /* 0xfffffe800f0f7810 */
/* 0x000fe40007ffe0ff */
/*0630*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0640*/ IADD3 R8, R2.reuse, 0x80, RZ ; /* 0x0000008002087810 */
/* 0x040fe40007ffe0ff */
/*0650*/ IADD3 R10, R2, 0x100, RZ ; /* 0x00000100020a7810 */
/* 0x000fce0007ffe0ff */
/*0660*/ IMAD.WIDE R6, R2.reuse, R13, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x040fe200078e020d */
/*0670*/ IADD3 R12, R2, 0x180, RZ ; /* 0x00000180020c7810 */
/* 0x000fc60007ffe0ff */
/*0680*/ IMAD.WIDE R8, R8, R13.reuse, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x080fe400078e020d */
/*0690*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*06a0*/ IMAD.WIDE R10, R10, R13.reuse, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x080fe400078e020d */
/*06b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*06c0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fe400078e020d */
/*06d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f28000c1e1900 */
/*06e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*06f0*/ IADD3 R2, R2, 0x200, RZ ; /* 0x0000020002027810 */
/* 0x000fc80007ffe0ff */
/*0700*/ ISETP.GE.U32.AND P1, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fe20003f26070 */
/*0710*/ FADD R3, R6, R3 ; /* 0x0000000306037221 */
/* 0x004fc80000000000 */
/*0720*/ FADD R3, R3, R8 ; /* 0x0000000803037221 */
/* 0x008fc80000000000 */
/*0730*/ FADD R3, R3, R10 ; /* 0x0000000a03037221 */
/* 0x010fc80000000000 */
/*0740*/ FADD R3, R3, R12 ; /* 0x0000000c03037221 */
/* 0x020fe20000000000 */
/*0750*/ @!P1 BRA 0x630 ; /* 0xfffffed000009947 */
/* 0x000fea000383ffff */
/*0760*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.GE.U32.AND P1, PT, R2.reuse, c[0x0][0xc], PT ; /* 0x0000030002007a0c */
/* 0x040fe20003f26070 */
/*0780*/ BSSY B1, 0x870 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0790*/ IADD3 R6, -R2, c[0x0][0xc], RZ ; /* 0x0000030002067a10 */
/* 0x000fc80007ffe1ff */
/*07a0*/ ISETP.LE.U32.OR P1, PT, R6, 0x80, P1 ; /* 0x000000800600780c */
/* 0x000fda0000f23470 */
/*07b0*/ @P1 BRA 0x860 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fe40000000f00 */
/*07d0*/ IADD3 R6, R2, 0x80, RZ ; /* 0x0000008002067810 */
/* 0x000fc60007ffe0ff */
/*07e0*/ IMAD.WIDE R8, R2, R7, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fc800078e0207 */
/*07f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe400078e0207 */
/*0800*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0820*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0830*/ IADD3 R2, R2, 0x100, RZ ; /* 0x0000010002027810 */
/* 0x000fe20007ffe0ff */
/*0840*/ FADD R3, R3, R8 ; /* 0x0000000803037221 */
/* 0x004fc80000000000 */
/*0850*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x008fe40000000000 */
/*0860*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0870*/ ISETP.LT.U32.OR P0, PT, R2, c[0x0][0xc], P0 ; /* 0x0000030002007a0c */
/* 0x000fda0000701470 */
/*0880*/ @!P0 BRA 0x8d0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*08a0*/ IMAD.WIDE R6, R2, R7, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fcc00078e0207 */
/*08b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*08c0*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x004fe40000000000 */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08e0*/ STS [R0+0x10], R3 ; /* 0x0000100300007388 */
/* 0x000fe20000000800 */
/*08f0*/ BSSY B0, 0xa90 ; /* 0x0000019000007945 */
/* 0x000fe60003800000 */
/*0900*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0910*/ @!P2 LDS R2, [R0+0x110] ; /* 0x000110000002a984 */
/* 0x000e240000000800 */
/*0920*/ @!P2 FADD R3, R3, R2 ; /* 0x000000020303a221 */
/* 0x001fca0000000000 */
/*0930*/ @!P2 STS [R0+0x10], R3 ; /* 0x000010030000a388 */
/* 0x0001e80000000800 */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ @P3 BRA 0xa80 ; /* 0x0000012000003947 */
/* 0x000fea0003800000 */
/*0960*/ LDS R2, [R0+0x90] ; /* 0x0000900000027984 */
/* 0x001e240000000800 */
/*0970*/ FADD R3, R2, R3 ; /* 0x0000000302037221 */
/* 0x001fca0000000000 */
/*0980*/ STS [R0+0x10], R3 ; /* 0x0000100300007388 */
/* 0x000fe80000000800 */
/*0990*/ LDS R2, [R0+0x50] ; /* 0x0000500000027984 */
/* 0x000e240000000800 */
/*09a0*/ FADD R7, R3, R2 ; /* 0x0000000203077221 */
/* 0x001fca0000000000 */
/*09b0*/ STS [R0+0x10], R7 ; /* 0x0000100700007388 */
/* 0x000fe80000000800 */
/*09c0*/ LDS R2, [R0+0x30] ; /* 0x0000300000027984 */
/* 0x000e240000000800 */
/*09d0*/ FADD R9, R7, R2 ; /* 0x0000000207097221 */
/* 0x001fca0000000000 */
/*09e0*/ STS [R0+0x10], R9 ; /* 0x0000100900007388 */
/* 0x000fe80000000800 */
/*09f0*/ LDS R2, [R0+0x20] ; /* 0x0000200000027984 */
/* 0x000e240000000800 */
/*0a00*/ FADD R11, R9, R2 ; /* 0x00000002090b7221 */
/* 0x001fca0000000000 */
/*0a10*/ STS [R0+0x10], R11 ; /* 0x0000100b00007388 */
/* 0x000fe80000000800 */
/*0a20*/ LDS R2, [R0+0x18] ; /* 0x0000180000027984 */
/* 0x000e240000000800 */
/*0a30*/ FADD R3, R11, R2 ; /* 0x000000020b037221 */
/* 0x001fca0000000000 */
/*0a40*/ STS [R0+0x10], R3 ; /* 0x0000100300007388 */
/* 0x000fe80000000800 */
/*0a50*/ LDS R2, [R0+0x14] ; /* 0x0000140000027984 */
/* 0x000e240000000800 */
/*0a60*/ FADD R7, R3, R2 ; /* 0x0000000203077221 */
/* 0x001fca0000000000 */
/*0a70*/ STS [R0+0x10], R7 ; /* 0x0000100700007388 */
/* 0x0001e40000000800 */
/*0a80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0a90*/ @P4 EXIT ; /* 0x000000000000494d */
/* 0x000fea0003800000 */
/*0aa0*/ LDS R7, [0x10] ; /* 0x00001000ff077984 */
/* 0x000e220000000800 */
/*0ab0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*0ac0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0ad0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*0ae0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z16reduceSinglePassILj128ELb1EEvPKfPfj,"axG",@progbits,_Z16reduceSinglePassILj128ELb1EEvPKfPfj,comdat
.protected _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.globl _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.p2align 8
.type _Z16reduceSinglePassILj128ELb1EEvPKfPfj,@function
_Z16reduceSinglePassILj128ELb1EEvPKfPfj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s6, s15
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v1, s6, 8, v0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_lshl_b32 s9, s8, 8
s_mov_b32 s7, 0
.p2align 6
.LBB0_2:
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v4, 0x80, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s9, v1
v_mov_b32_e32 v5, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s7
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s5
v_lshl_add_u32 v4, v0, 2, 4
s_mov_b64 s[2:3], src_shared_base
v_cmp_gt_u32_e64 s2, 64, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
v_cndmask_b32_e64 v2, 0, s3, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b64 s[4:5], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, 4, v5, 0x100
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s5, vcc_lo
flat_load_b32 v5, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v5
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e64 s3, 32, v0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b64 s[10:11], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, 4, v5, 0x80
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
flat_load_b32 v6, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 64, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v6
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v6, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 32, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v6
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v6, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 16, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v6
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v6, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 8, v4
v_add_nc_u32_e32 v4, 4, v4
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v6
v_cndmask_b32_e64 v6, 0, s11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v5, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v5, v3, v5
v_cndmask_b32_e32 v3, 0, v4, vcc_lo
v_cndmask_b32_e64 v4, 0, s11, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v5, v3
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[4:5], s[0:1], 0x8
v_cmp_eq_u32_e64 s0, 0, v0
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v1, 4 :: v_dual_mov_b32 v2, 0
s_lshl_b64 s[6:7], s[6:7], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s4, s6
ds_load_b32 v1, v1
s_addc_u32 s7, s5, s7
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v1, s[6:7]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_lt_u32 s8, 2
s_cbranch_scc1 .LBB0_24
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
buffer_gl1_inv
buffer_gl0_inv
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_13
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s8
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, retirementCount@rel32@lo+4
s_addc_u32 s7, s7, retirementCount@rel32@hi+12
global_atomic_inc_u32 v2, v1, v2, s[6:7] glc
s_add_i32 s6, s8, -1
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s6, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
ds_store_b8 v1, v2
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_u8 v1, v3
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v1
s_cbranch_vccnz .LBB0_24
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s8, v0
s_cbranch_execz .LBB0_18
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s6, 0
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, 0x80, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s8, v1
global_load_b32 v2, v[4:5], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v2
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_16
s_or_b32 exec_lo, exec_lo, s6
.LBB0_18:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_lshl_add_u32 v4, v0, 2, 4
s_mov_b64 s[6:7], src_shared_base
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s2
s_cbranch_execz .LBB0_20
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, 4, v5, 0x100
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_load_b32 v5, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v5
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s3
s_cbranch_execz .LBB0_22
v_lshlrev_b32_e32 v0, 2, v0
s_mov_b64 s[2:3], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, 4, v0, 0x80
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cndmask_b32_e32 v5, 0, v0, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
flat_load_b32 v0, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 64, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v3, v0
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 32, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 16, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 8, v4
v_add_nc_u32_e32 v4, 4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_add_f32 v0, v0, v3 :: v_dual_cndmask_b32 v3, 0, v4
v_cndmask_b32_e64 v4, 0, s3, vcc_lo
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_24
v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, retirementCount@rel32@lo+4
s_addc_u32 s1, s1, retirementCount@rel32@hi+12
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v1, v0, s[4:5]
global_store_b32 v1, v1, s[0:1]
.LBB0_24:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z16reduceSinglePassILj128ELb1EEvPKfPfj,"axG",@progbits,_Z16reduceSinglePassILj128ELb1EEvPKfPfj,comdat
.Lfunc_end0:
.size _Z16reduceSinglePassILj128ELb1EEvPKfPfj, .Lfunc_end0-_Z16reduceSinglePassILj128ELb1EEvPKfPfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected retirementCount
.type retirementCount,@object
.section .bss,"aw",@nobits
.globl retirementCount
.p2align 2, 0x0
retirementCount:
.long 0
.size retirementCount, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym retirementCount
.addrsig_sym smem
.addrsig_sym sdata
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16reduceSinglePassILj128ELb1EEvPKfPfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00185b8f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z16reduceSinglePassILj128ELb1EEvPKfPfj,"axG",@progbits,_Z16reduceSinglePassILj128ELb1EEvPKfPfj,comdat
.weak _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.type _Z16reduceSinglePassILj128ELb1EEvPKfPfj, @function
_Z16reduceSinglePassILj128ELb1EEvPKfPfj:
.LFB2104:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16reduceSinglePassILj128ELb1EEvPKfPfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z16reduceSinglePassILj128ELb1EEvPKfPfj, .-_Z16reduceSinglePassILj128ELb1EEvPKfPfj
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16reduceSinglePassILj128ELb1EEvPKfPfj"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "retirementCount"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reduceSinglePassILj128ELb1EEvPKfPfj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15retirementCount(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL15retirementCount
.comm _ZL15retirementCount,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.section .text._Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj,"axG",@progbits,_Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj,comdat
.weak _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj # -- Begin function _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.p2align 4, 0x90
.type _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj,@function
_Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj: # @_Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16reduceSinglePassILj128ELb1EEvPKfPfj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj, .Lfunc_end0-_Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16reduceSinglePassILj128ELb1EEvPKfPfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $retirementCount, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type retirementCount,@object # @retirementCount
.local retirementCount
.comm retirementCount,4,4
.type _Z16reduceSinglePassILj128ELb1EEvPKfPfj,@object # @_Z16reduceSinglePassILj128ELb1EEvPKfPfj
.section .rodata,"a",@progbits
.weak _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.p2align 3, 0x0
_Z16reduceSinglePassILj128ELb1EEvPKfPfj:
.quad _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.size _Z16reduceSinglePassILj128ELb1EEvPKfPfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16reduceSinglePassILj128ELb1EEvPKfPfj"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "retirementCount"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__reduceSinglePassILj128ELb1EEvPKfPfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym retirementCount
.addrsig_sym _Z16reduceSinglePassILj128ELb1EEvPKfPfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//double* x, * devx, * val, * gra, * r, * graMax;
//double* hes_value;
////int size;
//int* pos_x, * pos_y;
//int* csr;
double* x;
//thrust::pair<int, int> *device_pos;
//typedef double (*fp)(double);
//typedef void (*val_fp)(double*, double*, int);
//typedef void (*valsum_fp)(double*, double*,int);
//typedef void (*gra_fp)(double*, double*, int);
//typedef void (*gramin_fp)(double*, double*,int);
//typedef void (*hes_fp)( double*, thrust::pair<int, int>*, double*, int);
//typedef void (*print_fp)(double*, int);
int numSMs;
__device__ void wait() {
for (int i = 1; i <= 10000000; i++);
}
__device__ double sqr(double x) {
return x * x;
}
__global__ void calculate_val(double* devx, double* val, int size) {
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < size;
index += blockDim.x * gridDim.x)
{
int pre = index - 1;
if (pre < 0) pre += size;
int next = index + 1;
if (next >= size) next -= size;
val[index] = sqr(sin(devx[pre] * devx[index])) * sqr(sin(devx[next] * devx[index]));
}
// wait();
} | code for sm_80
Function : _Z13calculate_valPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0050*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R2, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IADD3 R4, R2, 0x4, RZ ; /* 0x0000000402047810 */
/* 0x000fe40007ffe0ff */
/*00a0*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x001fc600078e00ff */
/*00c0*/ SEL R0, RZ, c[0x0][0x170], P0 ; /* 0x00005c00ff007a07 */
/* 0x000fe20000000000 */
/*00d0*/ IMAD.WIDE R14, R3, R8, c[0x0][0x160] ; /* 0x00005800030e7625 */
/* 0x000fc600078e0208 */
/*00e0*/ IADD3 R0, R3, -0x1, R0 ; /* 0xffffffff03007810 */
/* 0x000fe40007ffe000 */
/*00f0*/ LDG.E.64 R6, [R14.64] ; /* 0x000000060e067981 */
/* 0x000ea6000c1e1b00 */
/*0100*/ IMAD.WIDE R8, R0, R8, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fcc00078e0208 */
/*0110*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ BSSY B0, 0x300 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0130*/ DMUL R12, R6, R8 ; /* 0x00000008060c7228 */
/* 0x004e140000000000 */
/*0140*/ LOP3.LUT R0, R13, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0d007812 */
/* 0x001fe400078ec0ff */
/*0150*/ ISETP.EQ.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f22270 */
/*0160*/ ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fe40003f05270 */
/*0170*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */
/* 0x000fd60000011403 */
/*0180*/ @!P0 BRA P1, 0x2d0 ; /* 0x0000014000008947 */
/* 0x000fea0000800000 */
/*0190*/ DMUL R10, R12, c[0x2][0x0] ; /* 0x008000000c0a7a28 */
/* 0x000e080000000000 */
/*01a0*/ DSETP.GE.AND P0, PT, |R12|, 2.14748364800000000000e+09, PT ; /* 0x41e000000c00742a */
/* 0x000fe40003f06200 */
/*01b0*/ F2I.F64 R0, R10 ; /* 0x0000000a00007311 */
/* 0x001e300000301100 */
/*01c0*/ I2F.F64 R18, R0 ; /* 0x0000000000127312 */
/* 0x001e220000201c00 */
/*01d0*/ STL [R1+0x4], R0 ; /* 0x0000040001007387 */
/* 0x0003e20000100800 */
/*01e0*/ DFMA R8, -R18, c[0x2][0x8], R12 ; /* 0x0080020012087a2b */
/* 0x001e0c000000010c */
/*01f0*/ DFMA R8, -R18, c[0x2][0x10], R8 ; /* 0x0080040012087a2b */
/* 0x001e0c0000000108 */
/*0200*/ DFMA R18, -R18, c[0x2][0x18], R8 ; /* 0x0080060012127a2b */
/* 0x0012220000000108 */
/*0210*/ @!P0 BRA 0x2f0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0220*/ BSSY B1, 0x290 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0230*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000c */
/*0240*/ MOV R0, 0x280 ; /* 0x0000028000007802 */
/* 0x002fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*0270*/ CALL.REL.NOINC 0x910 ; /* 0x0000069000007944 */
/* 0x001fea0003c00000 */
/*0280*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0290*/ LDL R0, [R1+0x4] ; /* 0x0000040001007983 */
/* 0x0001620000100800 */
/*02a0*/ IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0010 */
/*02b0*/ IMAD.MOV.U32 R19, RZ, RZ, R17 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0011 */
/*02c0*/ BRA 0x2f0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*02d0*/ DMUL R18, RZ, R12 ; /* 0x0000000cff127228 */
/* 0x0000620000000000 */
/*02e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fca00078e00ff */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ IMAD.SHL.U32 R5, R0.reuse, 0x8, RZ ; /* 0x0000000800057824 */
/* 0x060fe400078e00ff */
/*0310*/ IMAD.MOV.U32 R16, RZ, RZ, 0x8 ; /* 0x00000008ff107424 */
/* 0x000fe200078e00ff */
/*0320*/ R2P PR, R0, 0x3 ; /* 0x0000000300007804 */
/* 0x000fe20000000000 */
/*0330*/ IMAD.MOV.U32 R20, RZ, RZ, 0x79785eba ; /* 0x79785ebaff147424 */
/* 0x000fe200078e00ff */
/*0340*/ LOP3.LUT R5, R5, 0x8, RZ, 0xc0, !PT ; /* 0x0000000805057812 */
/* 0x000fe200078ec0ff */
/*0350*/ DMUL R8, R18, R18 ; /* 0x0000001212087228 */
/* 0x003e220000000000 */
/*0360*/ LDG.E.64 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f26000c1e1b00 */
/*0370*/ IMAD.WIDE R12, R5, R16, c[0x4][0x0] ; /* 0x01000000050c7625 */
/* 0x000fca00078e0210 */
/*0380*/ LDG.E.64.CONSTANT R26, [R12.64+0x8] ; /* 0x000008060c1a7981 */
/* 0x000e22000c1e9b00 */
/*0390*/ IADD3 R0, R3, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x000fc60007ffe0ff */
/*03a0*/ LDG.E.64.CONSTANT R10, [R12.64+0x10] ; /* 0x000010060c0a7981 */
/* 0x000ee2000c1e9b00 */
/*03b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3de5db65 ; /* 0x3de5db65ff057424 */
/* 0x000fe200078e00ff */
/*03c0*/ ISETP.GE.AND P2, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f46270 */
/*03d0*/ LDG.E.64.CONSTANT R24, [R12.64+0x18] ; /* 0x000018060c187981 */
/* 0x000f22000c1e9b00 */
/*03e0*/ FSEL R20, -R20, 4.2945490664224492434e-19, !P0 ; /* 0x20fd816414147808 */
/* 0x000fe40004000100 */
/*03f0*/ FSEL R21, R5, -0.082518599927425384521, !P0 ; /* 0xbda8ff8305157808 */
/* 0x000fe20004000000 */
/*0400*/ LDG.E.64.CONSTANT R22, [R12.64+0x20] ; /* 0x000020060c167981 */
/* 0x000f22000c1e9b00 */
/*0410*/ SEL R5, RZ, c[0x0][0x170], !P2 ; /* 0x00005c00ff057a07 */
/* 0x000fc60005000000 */
/*0420*/ LDG.E.64.CONSTANT R28, [R12.64+0x30] ; /* 0x000030060c1c7981 */
/* 0x000f24000c1e9b00 */
/*0430*/ IMAD.IADD R5, R0, 0x1, -R5 ; /* 0x0000000100057824 */
/* 0x000fc800078e0a05 */
/*0440*/ IMAD.WIDE R16, R5, R16, c[0x0][0x160] ; /* 0x0000580005107625 */
/* 0x000fcc00078e0210 */
/*0450*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f22000c1e1b00 */
/*0460*/ DFMA R26, R8, R20, R26 ; /* 0x00000014081a722b */
/* 0x0010c6000000001a */
/*0470*/ LDG.E.64.CONSTANT R20, [R12.64+0x28] ; /* 0x000028060c147981 */
/* 0x001ea6000c1e9b00 */
/*0480*/ DFMA R10, R8, R26, R10 ; /* 0x0000001a080a722b */
/* 0x008f0c000000000a */
/*0490*/ DFMA R10, R8, R10, R24 ; /* 0x0000000a080a722b */
/* 0x010e0c0000000018 */
/*04a0*/ DFMA R10, R8.reuse, R10, R22 ; /* 0x0000000a080a722b */
/* 0x041ea20000000016 */
/*04b0*/ BSSY B0, 0x6d0 ; /* 0x0000021000007945 */
/* 0x000fea0003800000 */
/*04c0*/ DFMA R10, R8, R10, R20 ; /* 0x0000000a080a722b */
/* 0x004e0c0000000014 */
/*04d0*/ DFMA R28, R8, R10, R28 ; /* 0x0000000a081c722b */
/* 0x001e08000000001c */
/*04e0*/ DMUL R10, R14, R16 ; /* 0x000000100e0a7228 */
/* 0x000e480000000000 */
/*04f0*/ DFMA R18, R28, R18, R18 ; /* 0x000000121c12722b */
/* 0x001fcc0000000012 */
/*0500*/ LOP3.LUT R0, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0b007812 */
/* 0x002fe200078ec0ff */
/*0510*/ @P0 DFMA R18, R8, R28, 1 ; /* 0x3ff000000812042b */
/* 0x000e22000000001c */
/*0520*/ ISETP.EQ.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f42270 */
/*0530*/ ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fc60003f05270 */
/*0540*/ @P1 DFMA R18, R18, -1, RZ ; /* 0xbff000001212182b */
/* 0x001e1400000000ff */
/*0550*/ @!P0 BRA P2, 0x6a0 ; /* 0x0000014000008947 */
/* 0x000fea0001000000 */
/*0560*/ DMUL R12, R10, c[0x2][0x0] ; /* 0x008000000a0c7a28 */
/* 0x001e080000000000 */
/*0570*/ DSETP.GE.AND P0, PT, |R10|, 2.14748364800000000000e+09, PT ; /* 0x41e000000a00742a */
/* 0x000fe40003f06200 */
/*0580*/ F2I.F64 R0, R12 ; /* 0x0000000c00007311 */
/* 0x001e300000301100 */
/*0590*/ I2F.F64 R14, R0 ; /* 0x00000000000e7312 */
/* 0x001e220000201c00 */
/*05a0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e20000100800 */
/*05b0*/ DFMA R8, -R14, c[0x2][0x8], R10 ; /* 0x008002000e087a2b */
/* 0x001e0c000000010a */
/*05c0*/ DFMA R8, -R14, c[0x2][0x10], R8 ; /* 0x008004000e087a2b */
/* 0x001e0c0000000108 */
/*05d0*/ DFMA R8, -R14, c[0x2][0x18], R8 ; /* 0x008006000e087a2b */
/* 0x0012220000000108 */
/*05e0*/ @!P0 BRA 0x6c0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*05f0*/ BSSY B1, 0x660 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0600*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*0610*/ MOV R0, 0x650 ; /* 0x0000065000007802 */
/* 0x002fe20000000f00 */
/*0620*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*0630*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0640*/ CALL.REL.NOINC 0x910 ; /* 0x000002c000007944 */
/* 0x001fea0003c00000 */
/*0650*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0660*/ LDL R0, [R1] ; /* 0x0000000001007983 */
/* 0x0001620000100800 */
/*0670*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0010 */
/*0680*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*0690*/ BRA 0x6c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06a0*/ DMUL R8, RZ, R10 ; /* 0x0000000aff087228 */
/* 0x0010620000000000 */
/*06b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fca00078e00ff */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.SHL.U32 R5, R0, 0x8, RZ ; /* 0x0000000800057824 */
/* 0x020fe400078e00ff */
/*06e0*/ IMAD.MOV.U32 R28, RZ, RZ, 0x8 ; /* 0x00000008ff1c7424 */
/* 0x000fc600078e00ff */
/*06f0*/ LOP3.LUT R5, R5, 0x8, RZ, 0xc0, !PT ; /* 0x0000000805057812 */
/* 0x000fca00078ec0ff */
/*0700*/ IMAD.WIDE R28, R5, R28, c[0x4][0x0] ; /* 0x01000000051c7625 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64.CONSTANT R22, [R28.64+0x8] ; /* 0x000008061c167981 */
/* 0x000ea8000c1e9b00 */
/*0720*/ LDG.E.64.CONSTANT R20, [R28.64+0x10] ; /* 0x000010061c147981 */
/* 0x000ee8000c1e9b00 */
/*0730*/ LDG.E.64.CONSTANT R16, [R28.64+0x18] ; /* 0x000018061c107981 */
/* 0x000f28000c1e9b00 */
/*0740*/ LDG.E.64.CONSTANT R14, [R28.64+0x20] ; /* 0x000020061c0e7981 */
/* 0x002f28000c1e9b00 */
/*0750*/ LDG.E.64.CONSTANT R12, [R28.64+0x28] ; /* 0x000028061c0c7981 */
/* 0x000f28000c1e9b00 */
/*0760*/ LDG.E.64.CONSTANT R10, [R28.64+0x30] ; /* 0x000030061c0a7981 */
/* 0x001f22000c1e9b00 */
/*0770*/ R2P PR, R0, 0x3 ; /* 0x0000000300007804 */
/* 0x000fe20000000000 */
/*0780*/ IMAD.MOV.U32 R26, RZ, RZ, 0x79785eba ; /* 0x79785ebaff1a7424 */
/* 0x000fe200078e00ff */
/*0790*/ DMUL R24, R8, R8 ; /* 0x0000000808187228 */
/* 0x000ea20000000000 */
/*07a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3de5db65 ; /* 0x3de5db65ff007424 */
/* 0x000fc600078e00ff */
/*07b0*/ FSEL R26, -R26, 4.2945490664224492434e-19, !P0 ; /* 0x20fd81641a1a7808 */
/* 0x000fe20004000100 */
/*07c0*/ DMUL R18, R18, R18 ; /* 0x0000001212127228 */
/* 0x000fe20000000000 */
/*07d0*/ FSEL R27, R0, -0.082518599927425384521, !P0 ; /* 0xbda8ff83001b7808 */
/* 0x000fe20004000000 */
/*07e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*07f0*/ DFMA R22, R24, R26, R22 ; /* 0x0000001a1816722b */
/* 0x004ecc0000000016 */
/*0800*/ DFMA R20, R24, R22, R20 ; /* 0x000000161814722b */
/* 0x008f0c0000000014 */
/*0810*/ DFMA R16, R24, R20, R16 ; /* 0x000000141810722b */
/* 0x010e0c0000000010 */
/*0820*/ DFMA R14, R24, R16, R14 ; /* 0x00000010180e722b */
/* 0x001e0c000000000e */
/*0830*/ DFMA R12, R24, R14, R12 ; /* 0x0000000e180c722b */
/* 0x001e0c000000000c */
/*0840*/ DFMA R10, R24, R12, R10 ; /* 0x0000000c180a722b */
/* 0x001e0c000000000a */
/*0850*/ DFMA R8, R10, R8, R8 ; /* 0x000000080a08722b */
/* 0x001fc80000000008 */
/*0860*/ @P0 DFMA R8, R24, R10, 1 ; /* 0x3ff000001808042b */
/* 0x000064000000000a */
/*0870*/ LEA R10, P0, R3, c[0x0][0x168], 0x3 ; /* 0x00005a00030a7a11 */
/* 0x001fc800078018ff */
/*0880*/ @P1 DFMA R8, R8, -1, RZ ; /* 0xbff000000808182b */
/* 0x002e2200000000ff */
/*0890*/ LEA.HI.X R11, R3, c[0x0][0x16c], R6, 0x3, P0 ; /* 0x00005b00030b7a11 */
/* 0x000fe200000f1c06 */
/*08a0*/ IMAD R3, R0, c[0x0][0xc], R3 ; /* 0x0000030000037a24 */
/* 0x000fc800078e0203 */
/*08b0*/ DMUL R8, R8, R8 ; /* 0x0000000808087228 */
/* 0x001e220000000000 */
/*08c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fca0003f06270 */
/*08d0*/ DMUL R8, R8, R18 ; /* 0x0000001208087228 */
/* 0x001e0e0000000000 */
/*08e0*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0011e2000c101b06 */
/*08f0*/ @!P0 BRA 0xa0 ; /* 0xfffff7a000008947 */
/* 0x000fea000383ffff */
/*0900*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0910*/ SHF.R.U32.HI R8, RZ, 0x14, R5.reuse ; /* 0x00000014ff087819 */
/* 0x100fe20000011605 */
/*0920*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fc600078e0005 */
/*0930*/ LOP3.LUT R8, R8, 0x7ff, RZ, 0xc0, !PT ; /* 0x000007ff08087812 */
/* 0x000fc800078ec0ff */
/*0940*/ ISETP.NE.AND P0, PT, R8, 0x7ff, PT ; /* 0x000007ff0800780c */
/* 0x000fda0003f05270 */
/*0950*/ @!P0 BRA 0x1270 ; /* 0x0000091000008947 */
/* 0x000fea0003800000 */
/*0960*/ IADD3 R11, R8, -0x400, RZ ; /* 0xfffffc00080b7810 */
/* 0x000fe20007ffe0ff */
/*0970*/ BSSY B2, 0xc90 ; /* 0x0000031000027945 */
/* 0x000fe20003800000 */
/*0980*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe4000001ff00 */
/*0990*/ SHF.R.U32.HI R10, RZ, 0x6, R11 ; /* 0x00000006ff0a7819 */
/* 0x000fc8000001160b */
/*09a0*/ IADD3 R9, -R10.reuse, 0x10, RZ ; /* 0x000000100a097810 */
/* 0x040fe40007ffe1ff */
/*09b0*/ IADD3 R8, -R10.reuse, 0x13, RZ ; /* 0x000000130a087810 */
/* 0x040fe40007ffe1ff */
/*09c0*/ ISETP.GT.AND P0, PT, R9, 0xe, PT ; /* 0x0000000e0900780c */
/* 0x000fe40003f04270 */
/*09d0*/ IADD3 R10, -R10, 0xf, RZ ; /* 0x0000000f0a0a7810 */
/* 0x000fe40007ffe1ff */
/*09e0*/ SEL R8, R8, 0x12, !P0 ; /* 0x0000001208087807 */
/* 0x000fc60004000000 */
/*09f0*/ IMAD.MOV.U32 R23, RZ, RZ, R10 ; /* 0x000000ffff177224 */
/* 0x000fe200078e000a */
/*0a00*/ ISETP.GT.AND P0, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fe40003f04270 */
/*0a10*/ LOP3.LUT P2, R9, R11, 0x3f, RZ, 0xc0, !PT ; /* 0x0000003f0b097812 */
/* 0x000fe4000784c0ff */
/*0a20*/ IADD3 R11, R1, 0x8, RZ ; /* 0x00000008010b7810 */
/* 0x000fd20007ffe0ff */
/*0a30*/ @P0 BRA 0xc80 ; /* 0x0000024000000947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.MOV.U32 R21, RZ, RZ, 0x8 ; /* 0x00000008ff157424 */
/* 0x000fe200078e00ff */
/*0a50*/ SHF.L.U64.HI R17, R16.reuse, 0xb, R17 ; /* 0x0000000b10117819 */
/* 0x040fe20000010211 */
/*0a60*/ IMAD.SHL.U32 R25, R16, 0x800, RZ ; /* 0x0000080010197824 */
/* 0x000fe200078e00ff */
/*0a70*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0a80*/ IMAD.WIDE R20, R10, R21, c[0x4][0x8] ; /* 0x010002000a147625 */
/* 0x000fc800078e0215 */
/*0a90*/ IMAD.MOV.U32 R27, RZ, RZ, R21 ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e0015 */
/*0aa0*/ LOP3.LUT R21, R17, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000011157812 */
/* 0x000fe200078efcff */
/*0ab0*/ IMAD.MOV.U32 R22, RZ, RZ, R11 ; /* 0x000000ffff167224 */
/* 0x000fe400078e000b */
/*0ac0*/ IMAD.MOV.U32 R23, RZ, RZ, R10 ; /* 0x000000ffff177224 */
/* 0x000fe400078e000a */
/*0ad0*/ IMAD.MOV.U32 R16, RZ, RZ, R20 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0014 */
/*0ae0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0af0*/ IMAD.MOV.U32 R17, RZ, RZ, R27 ; /* 0x000000ffff117224 */
/* 0x000fcc00078e001b */
/*0b00*/ LDG.E.64.CONSTANT R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e9b00 */
/*0b10*/ IADD3 R23, R23, 0x1, RZ ; /* 0x0000000117177810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ IMAD.WIDE.U32 R12, P3, R16, R25, R12 ; /* 0x00000019100c7225 */
/* 0x004fc8000786000c */
/*0b30*/ IMAD R29, R16, R21, RZ ; /* 0x00000015101d7224 */
/* 0x000fe400078e02ff */
/*0b40*/ IMAD R24, R17, R25, RZ ; /* 0x0000001911187224 */
/* 0x000fc600078e02ff */
/*0b50*/ IADD3 R13, P0, R29, R13, RZ ; /* 0x0000000d1d0d7210 */
/* 0x000fe20007f1e0ff */
/*0b60*/ IMAD.HI.U32 R29, R16, R21, RZ ; /* 0x00000015101d7227 */
/* 0x000fc600078e00ff */
/*0b70*/ IADD3 R13, P1, R24, R13, RZ ; /* 0x0000000d180d7210 */
/* 0x000fe20007f3e0ff */
/*0b80*/ IMAD.HI.U32 R24, R17, R25, RZ ; /* 0x0000001911187227 */
/* 0x000fc800078e00ff */
/*0b90*/ IMAD.X R29, RZ, RZ, R29, P3 ; /* 0x000000ffff1d7224 */
/* 0x000fe200018e061d */
/*0ba0*/ ISETP.GE.AND P3, PT, R23, R8, PT ; /* 0x000000081700720c */
/* 0x000fe20003f66270 */
/*0bb0*/ IMAD.HI.U32 R16, R17.reuse, R21, RZ ; /* 0x0000001511107227 */
/* 0x040fe200078e00ff */
/*0bc0*/ STL.64 [R22], R12 ; /* 0x0000000c16007387 */
/* 0x0001e40000100a00 */
/*0bd0*/ IADD3.X R24, P0, R24, R29, RZ, P0, !PT ; /* 0x0000001d18187210 */
/* 0x000fe2000071e4ff */
/*0be0*/ IMAD R17, R17, R21, RZ ; /* 0x0000001511117224 */
/* 0x000fc800078e02ff */
/*0bf0*/ IMAD.X R16, RZ, RZ, R16, P0 ; /* 0x000000ffff107224 */
/* 0x000fe200000e0610 */
/*0c00*/ IADD3.X R24, P1, R17, R24, RZ, P1, !PT ; /* 0x0000001811187210 */
/* 0x000fe40000f3e4ff */
/*0c10*/ IADD3 R20, P0, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fe40007f1e0ff */
/*0c20*/ IADD3 R22, R22, 0x8, RZ ; /* 0x0000000816167810 */
/* 0x001fe20007ffe0ff */
/*0c30*/ IMAD.X R17, RZ, RZ, R16, P1 ; /* 0x000000ffff117224 */
/* 0x000fe400008e0610 */
/*0c40*/ IMAD.X R27, RZ, RZ, R27, P0 ; /* 0x000000ffff1b7224 */
/* 0x000fe400000e061b */
/*0c50*/ IMAD.MOV.U32 R12, RZ, RZ, R24 ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e0018 */
/*0c60*/ IMAD.MOV.U32 R13, RZ, RZ, R17 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0011 */
/*0c70*/ @!P3 BRA 0xad0 ; /* 0xfffffe500000b947 */
/* 0x000fea000383ffff */
/*0c80*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c90*/ IMAD.IADD R10, R23, 0x1, -R10 ; /* 0x00000001170a7824 */
/* 0x000fc800078e0a0a */
/*0ca0*/ IMAD R27, R10, 0x8, R11 ; /* 0x000000080a1b7824 */
/* 0x000fca00078e020b */
/*0cb0*/ STL.64 [R27], R12 ; /* 0x0000000c1b007387 */
/* 0x0001e80000100a00 */
/*0cc0*/ @P2 LDL.64 R20, [R1+0x10] ; /* 0x0000100001142983 */
/* 0x000ea80000100a00 */
/*0cd0*/ LDL.64 R16, [R1+0x18] ; /* 0x0000180001107983 */
/* 0x000ee80000100a00 */
/*0ce0*/ LDL.64 R10, [R1+0x20] ; /* 0x00002000010a7983 */
/* 0x000e220000100a00 */
/*0cf0*/ @P2 IADD3 R23, -R9, 0x40, RZ ; /* 0x0000004009172810 */
/* 0x000fe20007ffe1ff */
/*0d00*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*0d10*/ @P2 SHF.R.U64 R8, R20, R23.reuse, R21.reuse ; /* 0x0000001714082219 */
/* 0x184fe40000001215 */
/*0d20*/ @P2 SHF.R.U32.HI R20, RZ, R23, R21 ; /* 0x00000017ff142219 */
/* 0x000fe40000011615 */
/*0d30*/ @P2 SHF.L.U64.HI R21, R16.reuse, R9.reuse, R17.reuse ; /* 0x0000000910152219 */
/* 0x1c8fe40000010211 */
/*0d40*/ @P2 SHF.L.U32 R25, R16.reuse, R9, RZ ; /* 0x0000000910192219 */
/* 0x040fe400000006ff */
/*0d50*/ @P2 SHF.R.U64 R22, R16, R23, R17 ; /* 0x0000001710162219 */
/* 0x000fe40000001211 */
/*0d60*/ @P2 SHF.L.U32 R13, R10, R9, RZ ; /* 0x000000090a0d2219 */
/* 0x001fc400000006ff */
/*0d70*/ @P2 SHF.R.U32.HI R23, RZ, R23, R17 ; /* 0x00000017ff172219 */
/* 0x000fe40000011611 */
/*0d80*/ @P2 LOP3.LUT R17, R20, R21, RZ, 0xfc, !PT ; /* 0x0000001514112212 */
/* 0x000fe400078efcff */
/*0d90*/ @P2 SHF.L.U64.HI R20, R10, R9, R11 ; /* 0x000000090a142219 */
/* 0x000fe4000001020b */
/*0da0*/ @P2 LOP3.LUT R16, R8, R25, RZ, 0xfc, !PT ; /* 0x0000001908102212 */
/* 0x000fe400078efcff */
/*0db0*/ @P2 LOP3.LUT R10, R13, R22, RZ, 0xfc, !PT ; /* 0x000000160d0a2212 */
/* 0x000fe400078efcff */
/*0dc0*/ SHF.L.U64.HI R8, R16.reuse, 0x2, R17.reuse ; /* 0x0000000210087819 */
/* 0x140fe20000010211 */
/*0dd0*/ IMAD.SHL.U32 R16, R16, 0x4, RZ ; /* 0x0000000410107824 */
/* 0x000fe200078e00ff */
/*0de0*/ SHF.R.U32.HI R12, RZ, 0x1e, R17 ; /* 0x0000001eff0c7819 */
/* 0x000fe20000011611 */
/*0df0*/ IMAD.SHL.U32 R21, R10, 0x4, RZ ; /* 0x000000040a157824 */
/* 0x000fe200078e00ff */
/*0e00*/ @P2 LOP3.LUT R11, R20, R23, RZ, 0xfc, !PT ; /* 0x00000017140b2212 */
/* 0x000fc400078efcff */
/*0e10*/ IADD3 RZ, P0, RZ, -R16, RZ ; /* 0x80000010ffff7210 */
/* 0x000fe40007f1e0ff */
/*0e20*/ LOP3.LUT R9, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff097212 */
/* 0x000fe400078e33ff */
/*0e30*/ LOP3.LUT R21, R12, R21, RZ, 0xfc, !PT ; /* 0x000000150c157212 */
/* 0x000fe400078efcff */
/*0e40*/ SHF.L.U64.HI R20, R10, 0x2, R11 ; /* 0x000000020a147819 */
/* 0x000fe4000001020b */
/*0e50*/ IADD3.X R9, P0, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff097210 */
/* 0x000fe4000071e4ff */
/*0e60*/ LOP3.LUT R12, RZ, R21, RZ, 0x33, !PT ; /* 0x00000015ff0c7212 */
/* 0x000fc400078e33ff */
/*0e70*/ LOP3.LUT R13, RZ, R20, RZ, 0x33, !PT ; /* 0x00000014ff0d7212 */
/* 0x000fe400078e33ff */
/*0e80*/ IADD3.X R12, P0, RZ, R12, RZ, P0, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe4000071e4ff */
/*0e90*/ SHF.R.U32.HI R10, RZ, 0x1d, R11 ; /* 0x0000001dff0a7819 */
/* 0x000fc6000001160b */
/*0ea0*/ IMAD.X R13, RZ, RZ, R13, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe200000e060d */
/*0eb0*/ LOP3.LUT P1, RZ, R10, 0x1, RZ, 0xc0, !PT ; /* 0x000000010aff7812 */
/* 0x000fc8000782c0ff */
/*0ec0*/ SEL R17, R20, R13, !P1 ; /* 0x0000000d14117207 */
/* 0x000fe40004800000 */
/*0ed0*/ SEL R21, R21, R12, !P1 ; /* 0x0000000c15157207 */
/* 0x000fe40004800000 */
/*0ee0*/ ISETP.NE.U32.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc80003f05070 */
/*0ef0*/ SEL R12, R21, R17, !P0 ; /* 0x00000011150c7207 */
/* 0x000fcc0004000000 */
/*0f00*/ FLO.U32 R12, R12 ; /* 0x0000000c000c7300 */
/* 0x000e2400000e0000 */
/*0f10*/ IADD3 R13, -R12.reuse, 0x1f, RZ ; /* 0x0000001f0c0d7810 */
/* 0x041fe40007ffe1ff */
/*0f20*/ IADD3 R20, -R12, 0x3f, RZ ; /* 0x0000003f0c147810 */
/* 0x000fc60007ffe1ff */
/*0f30*/ @P0 IMAD.MOV R20, RZ, RZ, R13 ; /* 0x000000ffff140224 */
/* 0x000fca00078e020d */
/*0f40*/ ISETP.NE.U32.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fc80003f05070 */
/*0f50*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe20003f05300 */
/*0f60*/ @P1 IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff101224 */
/* 0x000fe200078e0a10 */
/*0f70*/ SEL R8, R8, R9, !P1 ; /* 0x0000000908087207 */
/* 0x000fe40004800000 */
/*0f80*/ IADD3 R9, -R20, 0x40, RZ ; /* 0x0000004014097810 */
/* 0x000fe40007ffe1ff */
/*0f90*/ SHF.L.U32 R13, R21.reuse, R20.reuse, RZ ; /* 0x00000014150d7219 */
/* 0x0c0fe400000006ff */
/*0fa0*/ SHF.R.U64 R16, R16, R9, R8 ; /* 0x0000000910107219 */
/* 0x000fe40000001208 */
/*0fb0*/ SHF.L.U64.HI R23, R21, R20, R17 ; /* 0x0000001415177219 */
/* 0x000fc60000010211 */
/*0fc0*/ @P0 LOP3.LUT R21, R16, R13, RZ, 0xfc, !PT ; /* 0x0000000d10150212 */
/* 0x000fe400078efcff */
/*0fd0*/ SHF.R.U32.HI R8, RZ, R9, R8 ; /* 0x00000009ff087219 */
/* 0x000fc60000011608 */
/*0fe0*/ IMAD.WIDE.U32 R12, R21, 0x2168c235, RZ ; /* 0x2168c235150c7825 */
/* 0x000fe200078e00ff */
/*0ff0*/ @P0 LOP3.LUT R17, R8, R23, RZ, 0xfc, !PT ; /* 0x0000001708110212 */
/* 0x000fc600078efcff */
/*1000*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000d */
/*1010*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc800078e00ff */
/*1020*/ IMAD.WIDE.U32 R8, R21, -0x36f0255e, R8 ; /* 0xc90fdaa215087825 */
/* 0x000fc800078e0008 */
/*1030*/ IMAD.HI.U32 R13, R17, -0x36f0255e, RZ ; /* 0xc90fdaa2110d7827 */
/* 0x000fc800078e00ff */
/*1040*/ IMAD.WIDE.U32 R8, P2, R17, 0x2168c235, R8 ; /* 0x2168c23511087825 */
/* 0x000fe20007840008 */
/*1050*/ IADD3 RZ, P0, R12, R12, RZ ; /* 0x0000000c0cff7210 */
/* 0x000fc60007f1e0ff */
/*1060*/ IMAD R17, R17, -0x36f0255e, RZ ; /* 0xc90fdaa211117824 */
/* 0x000fe400078e02ff */
/*1070*/ IMAD.X R12, RZ, RZ, R13, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fc600010e060d */
/*1080*/ IADD3 R9, P2, R17, R9, RZ ; /* 0x0000000911097210 */
/* 0x000fe40007f5e0ff */
/*1090*/ IADD3.X RZ, P0, R8, R8, RZ, P0, !PT ; /* 0x0000000808ff7210 */
/* 0x000fe4000071e4ff */
/*10a0*/ ISETP.GT.U32.AND P3, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f64070 */
/*10b0*/ IMAD.X R12, RZ, RZ, R12, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e060c */
/*10c0*/ IADD3.X R8, P2, R9, R9, RZ, P0, !PT ; /* 0x0000000909087210 */
/* 0x000fc8000075e4ff */
/*10d0*/ ISETP.GT.AND.EX P0, PT, R12.reuse, RZ, PT, P3 ; /* 0x000000ff0c00720c */
/* 0x040fe20003f04330 */
/*10e0*/ IMAD.X R13, R12, 0x1, R12, P2 ; /* 0x000000010c0d7824 */
/* 0x000fe200010e060c */
/*10f0*/ LOP3.LUT P2, RZ, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005ff7812 */
/* 0x000fe4000784c0ff */
/*1100*/ SEL R8, R8, R9, P0 ; /* 0x0000000908087207 */
/* 0x000fe40000000000 */
/*1110*/ LOP3.LUT R10, R10, 0x1, RZ, 0xc0, !PT ; /* 0x000000010a0a7812 */
/* 0x000fe400078ec0ff */
/*1120*/ SEL R9, R13, R12, P0 ; /* 0x0000000c0d097207 */
/* 0x000fe40000000000 */
/*1130*/ IADD3 R16, P3, R8, 0x1, RZ ; /* 0x0000000108107810 */
/* 0x000fc40007f7e0ff */
/*1140*/ LEA.HI R10, R11, R10, RZ, 0x2 ; /* 0x0000000a0b0a7211 */
/* 0x000fc600078f10ff */
/*1150*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe400018e0609 */
/*1160*/ IMAD.MOV R8, RZ, RZ, -R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a0a */
/*1170*/ IADD3 R13, R7, -c[0x0][0x20], RZ ; /* 0x80000800070d7a10 */
/* 0x000fe40007ffe0ff */
/*1180*/ SHF.R.U64 R16, R16, 0xa, R9 ; /* 0x0000000a10107819 */
/* 0x000fe20000001209 */
/*1190*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e0008 */
/*11a0*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fe40004000000 */
/*11b0*/ IADD3 R16, P2, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fe40007f5e0ff */
/*11c0*/ STL [R13], R10 ; /* 0x0000000a0d007387 */
/* 0x0001e40000100800 */
/*11d0*/ LEA.HI.X R7, R9, RZ, RZ, 0x16, P2 ; /* 0x000000ff09077211 */
/* 0x000fe200010fb4ff */
/*11e0*/ IMAD.IADD R9, R11, 0x1, R20 ; /* 0x000000010b097824 */
/* 0x000fc600078e0214 */
/*11f0*/ SHF.R.U64 R16, R16, 0x1, R7.reuse ; /* 0x0000000110107819 */
/* 0x100fe20000001207 */
/*1200*/ IMAD.SHL.U32 R9, R9, 0x100000, RZ ; /* 0x0010000009097824 */
/* 0x000fe200078e00ff */
/*1210*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fe400078ec0ff */
/*1220*/ SHF.R.U32.HI R8, RZ, 0x1, R7 ; /* 0x00000001ff087819 */
/* 0x000fe40000011607 */
/*1230*/ IADD3 R16, P0, P2, R16, -UR4, RZ ; /* 0x8000000410107c10 */
/* 0x000fe4000fa1e0ff */
/*1240*/ @P1 LOP3.LUT R5, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000005051812 */
/* 0x000fe400078e3cff */
/*1250*/ IADD3.X R8, R8, 0x3fe00000, ~R9, P0, P2 ; /* 0x3fe0000008087810 */
/* 0x000fc800007e4c09 */
/*1260*/ LOP3.LUT R17, R8, R5, RZ, 0xfc, !PT ; /* 0x0000000508117212 */
/* 0x000fe400078efcff */
/*1270*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0000 */
/*1280*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*1290*/ RET.REL.NODEC R8 0x0 ; /* 0xffffed6008007950 */
/* 0x000fea0003c3ffff */
/*12a0*/ BRA 0x12a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//double* x, * devx, * val, * gra, * r, * graMax;
//double* hes_value;
////int size;
//int* pos_x, * pos_y;
//int* csr;
double* x;
//thrust::pair<int, int> *device_pos;
//typedef double (*fp)(double);
//typedef void (*val_fp)(double*, double*, int);
//typedef void (*valsum_fp)(double*, double*,int);
//typedef void (*gra_fp)(double*, double*, int);
//typedef void (*gramin_fp)(double*, double*,int);
//typedef void (*hes_fp)( double*, thrust::pair<int, int>*, double*, int);
//typedef void (*print_fp)(double*, int);
int numSMs;
__device__ void wait() {
for (int i = 1; i <= 10000000; i++);
}
__device__ double sqr(double x) {
return x * x;
}
__global__ void calculate_val(double* devx, double* val, int size) {
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < size;
index += blockDim.x * gridDim.x)
{
int pre = index - 1;
if (pre < 0) pre += size;
int next = index + 1;
if (next >= size) next -= size;
val[index] = sqr(sin(devx[pre] * devx[index])) * sqr(sin(devx[next] * devx[index]));
}
// wait();
} | .file "tmpxft_000a30c1_00000000-6_calculate_val.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4waitv
.type _Z4waitv, @function
_Z4waitv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4waitv, .-_Z4waitv
.globl _Z3sqrd
.type _Z3sqrd, @function
_Z3sqrd:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z3sqrd, .-_Z3sqrd
.globl _Z36__device_stub__Z13calculate_valPdS_iPdS_i
.type _Z36__device_stub__Z13calculate_valPdS_iPdS_i, @function
_Z36__device_stub__Z13calculate_valPdS_iPdS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13calculate_valPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z36__device_stub__Z13calculate_valPdS_iPdS_i, .-_Z36__device_stub__Z13calculate_valPdS_iPdS_i
.globl _Z13calculate_valPdS_i
.type _Z13calculate_valPdS_i, @function
_Z13calculate_valPdS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13calculate_valPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13calculate_valPdS_i, .-_Z13calculate_valPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13calculate_valPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13calculate_valPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl numSMs
.bss
.align 4
.type numSMs, @object
.size numSMs, 4
numSMs:
.zero 4
.globl x
.align 8
.type x, @object
.size x, 8
x:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//double* x, * devx, * val, * gra, * r, * graMax;
//double* hes_value;
////int size;
//int* pos_x, * pos_y;
//int* csr;
double* x;
//thrust::pair<int, int> *device_pos;
//typedef double (*fp)(double);
//typedef void (*val_fp)(double*, double*, int);
//typedef void (*valsum_fp)(double*, double*,int);
//typedef void (*gra_fp)(double*, double*, int);
//typedef void (*gramin_fp)(double*, double*,int);
//typedef void (*hes_fp)( double*, thrust::pair<int, int>*, double*, int);
//typedef void (*print_fp)(double*, int);
int numSMs;
__device__ void wait() {
for (int i = 1; i <= 10000000; i++);
}
__device__ double sqr(double x) {
return x * x;
}
__global__ void calculate_val(double* devx, double* val, int size) {
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < size;
index += blockDim.x * gridDim.x)
{
int pre = index - 1;
if (pre < 0) pre += size;
int next = index + 1;
if (next >= size) next -= size;
val[index] = sqr(sin(devx[pre] * devx[index])) * sqr(sin(devx[next] * devx[index]));
}
// wait();
} | #include <hip/hip_runtime.h>
#include "includes.h"
//double* x, * devx, * val, * gra, * r, * graMax;
//double* hes_value;
////int size;
//int* pos_x, * pos_y;
//int* csr;
double* x;
//thrust::pair<int, int> *device_pos;
//typedef double (*fp)(double);
//typedef void (*val_fp)(double*, double*, int);
//typedef void (*valsum_fp)(double*, double*,int);
//typedef void (*gra_fp)(double*, double*, int);
//typedef void (*gramin_fp)(double*, double*,int);
//typedef void (*hes_fp)( double*, thrust::pair<int, int>*, double*, int);
//typedef void (*print_fp)(double*, int);
int numSMs;
__device__ void wait() {
for (int i = 1; i <= 10000000; i++);
}
__device__ double sqr(double x) {
return x * x;
}
__global__ void calculate_val(double* devx, double* val, int size) {
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < size;
index += blockDim.x * gridDim.x)
{
int pre = index - 1;
if (pre < 0) pre += size;
int next = index + 1;
if (next >= size) next -= size;
val[index] = sqr(sin(devx[pre] * devx[index])) * sqr(sin(devx[next] * devx[index]));
}
// wait();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//double* x, * devx, * val, * gra, * r, * graMax;
//double* hes_value;
////int size;
//int* pos_x, * pos_y;
//int* csr;
double* x;
//thrust::pair<int, int> *device_pos;
//typedef double (*fp)(double);
//typedef void (*val_fp)(double*, double*, int);
//typedef void (*valsum_fp)(double*, double*,int);
//typedef void (*gra_fp)(double*, double*, int);
//typedef void (*gramin_fp)(double*, double*,int);
//typedef void (*hes_fp)( double*, thrust::pair<int, int>*, double*, int);
//typedef void (*print_fp)(double*, int);
int numSMs;
__device__ void wait() {
for (int i = 1; i <= 10000000; i++);
}
__device__ double sqr(double x) {
return x * x;
}
__global__ void calculate_val(double* devx, double* val, int size) {
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < size;
index += blockDim.x * gridDim.x)
{
int pre = index - 1;
if (pre < 0) pre += size;
int next = index + 1;
if (next >= size) next -= size;
val[index] = sqr(sin(devx[pre] * devx[index])) * sqr(sin(devx[next] * devx[index]));
}
// wait();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13calculate_valPdS_i
.globl _Z13calculate_valPdS_i
.p2align 8
.type _Z13calculate_valPdS_i,@function
_Z13calculate_valPdS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s33, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s4, 0xffff
s_mov_b32 s4, exec_lo
s_mul_i32 s15, s15, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v0
v_cmpx_gt_i32_e64 s33, v1
s_cbranch_execz .LBB0_11
s_load_b32 s47, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_add3_u32 v14, v0, s15, 1
s_mov_b32 s46, 0
s_mov_b32 s3, 0x3ff921fb
s_mov_b32 s8, 0x54442d18
s_mov_b32 s11, 0x3c91a626
s_mov_b32 s12, 0x33145c07
s_mov_b32 s15, 0x3fe45f30
s_mov_b32 s14, 0x6dc9c883
s_mov_b32 s9, 0xbff921fb
s_mov_b32 s17, 0xbc91a626
s_mov_b32 s16, 0x33145c00
s_mov_b32 s19, 0xb97b839a
s_mov_b32 s18, 0x252049c0
s_mov_b32 s21, 0x3e21eeb6
s_mov_b32 s20, 0x9037ab78
s_mov_b32 s23, 0xbda907db
s_mov_b32 s22, 0x46cc5e42
s_mov_b32 s25, 0xbe927e4f
s_waitcnt lgkmcnt(0)
s_mul_i32 s47, s47, s10
s_mov_b32 s24, 0xa17f65f6
s_mov_b32 s27, 0x3efa01a0
s_mov_b32 s26, 0x19f4ec90
s_mov_b32 s29, 0xbf56c16c
s_mov_b32 s28, 0x16c16967
s_mov_b32 s31, 0x3fa55555
s_mov_b32 s30, 0x55555555
s_mov_b32 s35, 0xbe5ae600
s_mov_b32 s34, 0xb42fdfa7
s_mov_b32 s37, 0x3de5e0b2
s_mov_b32 s36, 0xf9a43bb8
s_mov_b32 s39, 0x3ec71de3
s_mov_b32 s38, 0x796cde01
s_mov_b32 s41, 0xbf2a01a0
s_mov_b32 s40, 0x19e83e5c
s_mov_b32 s43, 0x3f811111
s_mov_b32 s42, 0x11110bb3
s_mov_b32 s45, 0xbfc55555
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_mul_f64 v[17:18], v[4:5], v[4:5]
v_mul_f64 v[19:20], v[10:11], v[10:11]
v_mul_f64 v[37:38], v[6:7], 0.5
s_delay_alu instid0(VALU_DEP_4)
v_mul_f64 v[39:40], v[12:13], 0.5
s_mov_b32 s44, s30
v_cmp_class_f64_e64 s1, v[2:3], 0x1f8
v_cmp_class_f64_e64 s2, v[8:9], 0x1f8
v_lshlrev_b32_e32 v2, 30, v15
v_lshlrev_b32_e32 v8, 30, v16
v_add_nc_u32_e32 v14, s47, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v3
v_xor_b32_e32 v3, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, 0x80000000, v2
v_and_b32_e32 v3, 0x80000000, v3
v_fma_f64 v[21:22], v[17:18], s[36:37], s[34:35]
v_fma_f64 v[23:24], v[19:20], s[36:37], s[34:35]
v_fma_f64 v[25:26], v[17:18], s[22:23], s[20:21]
v_mul_f64 v[27:28], v[17:18], 0.5
v_fma_f64 v[29:30], v[19:20], s[22:23], s[20:21]
v_mul_f64 v[31:32], v[19:20], 0.5
v_mul_f64 v[41:42], v[4:5], -v[17:18]
v_mul_f64 v[43:44], v[10:11], -v[19:20]
v_fma_f64 v[21:22], v[17:18], v[21:22], s[38:39]
v_fma_f64 v[23:24], v[19:20], v[23:24], s[38:39]
v_fma_f64 v[25:26], v[17:18], v[25:26], s[24:25]
v_add_f64 v[33:34], -v[27:28], 1.0
v_fma_f64 v[29:30], v[19:20], v[29:30], s[24:25]
v_add_f64 v[35:36], -v[31:32], 1.0
v_fma_f64 v[21:22], v[17:18], v[21:22], s[40:41]
v_fma_f64 v[23:24], v[19:20], v[23:24], s[40:41]
v_fma_f64 v[25:26], v[17:18], v[25:26], s[26:27]
v_add_f64 v[45:46], -v[33:34], 1.0
v_fma_f64 v[29:30], v[19:20], v[29:30], s[26:27]
v_add_f64 v[47:48], -v[35:36], 1.0
v_fma_f64 v[21:22], v[17:18], v[21:22], s[42:43]
v_fma_f64 v[23:24], v[19:20], v[23:24], s[42:43]
v_fma_f64 v[25:26], v[17:18], v[25:26], s[28:29]
v_add_f64 v[27:28], v[45:46], -v[27:28]
v_fma_f64 v[29:30], v[19:20], v[29:30], s[28:29]
v_add_f64 v[31:32], v[47:48], -v[31:32]
v_fma_f64 v[21:22], v[41:42], v[21:22], v[37:38]
v_fma_f64 v[23:24], v[43:44], v[23:24], v[39:40]
v_mul_f64 v[37:38], v[17:18], v[17:18]
v_mul_f64 v[39:40], v[19:20], v[19:20]
v_fma_f64 v[25:26], v[17:18], v[25:26], s[30:31]
v_fma_f64 v[27:28], v[4:5], -v[6:7], v[27:28]
v_fma_f64 v[29:30], v[19:20], v[29:30], s[30:31]
v_fma_f64 v[6:7], v[17:18], v[21:22], -v[6:7]
v_fma_f64 v[17:18], v[10:11], -v[12:13], v[31:32]
v_fma_f64 v[12:13], v[19:20], v[23:24], -v[12:13]
v_fma_f64 v[19:20], v[37:38], v[25:26], v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[6:7], v[41:42], s[44:45], v[6:7]
v_fma_f64 v[17:18], v[39:40], v[29:30], v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[12:13], v[43:44], s[44:45], v[12:13]
v_add_f64 v[19:20], v[33:34], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[4:5], v[4:5], -v[6:7]
v_add_f64 v[6:7], v[35:36], v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_and_b32_e32 v12, 1, v15
v_and_b32_e32 v13, 1, v16
v_cmp_eq_u32_e32 vcc_lo, 0, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s0, 0, v13
v_dual_cndmask_b32 v5, v20, v5 :: v_dual_cndmask_b32 v4, v19, v4
v_cndmask_b32_e64 v7, v7, v11, s0
v_cndmask_b32_e64 v6, v6, v10, s0
v_add_co_u32 v0, s0, s6, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v5, v5, v2
v_xor_b32_e32 v7, v7, v3
v_cndmask_b32_e64 v2, 0, v4, s1
v_cndmask_b32_e64 v4, 0, v6, s2
v_add_co_ci_u32_e64 v1, s0, s7, v1, s0
v_cndmask_b32_e64 v3, 0x7ff80000, v5, s1
v_cndmask_b32_e64 v5, 0x7ff80000, v7, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[2:3], v[2:3], v[2:3]
v_mul_f64 v[4:5], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
v_add_nc_u32_e32 v4, -1, v14
v_cmp_le_i32_e32 vcc_lo, s33, v4
s_or_b32 s46, vcc_lo, s46
global_store_b64 v[0:1], v[2:3], off
s_and_not1_b32 exec_lo, exec_lo, s46
s_cbranch_execz .LBB0_11
.LBB0_3:
v_add_nc_u32_e32 v0, -1, v14
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v0
v_cndmask_b32_e64 v1, 0, s33, vcc_lo
v_add3_u32 v2, v1, v14, -2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[8:9], v[4:5], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f64_e64 0x41d00000, |v[2:3]|
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_5
v_ldexp_f64 v[4:5], |v[2:3]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
v_trig_preop_f64 v[6:7], |v[2:3]|, 0
v_dual_mov_b32 v29, 0 :: v_dual_and_b32 v10, 0x7fffffff, v3
v_trig_preop_f64 v[21:22], |v[2:3]|, 2
s_mov_b32 s2, s8
s_mov_b32 s13, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v10, v5, vcc_lo
v_cndmask_b32_e32 v4, v2, v4, vcc_lo
v_trig_preop_f64 v[10:11], |v[2:3]|, 1
v_mul_f64 v[12:13], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[15:16], v[10:11], v[4:5]
v_fma_f64 v[6:7], v[6:7], v[4:5], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[10:11], v[4:5], -v[15:16]
v_add_f64 v[17:18], v[15:16], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[19:20], v[17:18], -v[15:16]
v_add_f64 v[25:26], v[12:13], v[17:18]
v_add_f64 v[23:24], v[17:18], -v[19:20]
v_add_f64 v[6:7], v[6:7], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ldexp_f64 v[19:20], v[25:26], -2
v_add_f64 v[12:13], v[25:26], -v[12:13]
v_add_f64 v[15:16], v[15:16], -v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[19:20]|
v_add_f64 v[12:13], v[17:18], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], v[15:16]
v_fract_f64_e32 v[15:16], v[19:20]
v_dual_cndmask_b32 v15, 0, v15 :: v_dual_cndmask_b32 v16, 0, v16
v_mul_f64 v[27:28], v[21:22], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[15:16], v[15:16], 2
v_add_f64 v[23:24], v[27:28], v[10:11]
v_fma_f64 v[4:5], v[21:22], v[4:5], -v[27:28]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[17:18], v[23:24], v[6:7]
v_add_f64 v[19:20], v[12:13], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[25:26], v[19:20], v[15:16]
v_add_f64 v[12:13], v[19:20], -v[12:13]
v_cmp_gt_f64_e32 vcc_lo, 0, v[25:26]
v_add_f64 v[25:26], v[23:24], -v[27:28]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[17:18], -v[12:13]
v_cndmask_b32_e64 v30, 0, 0x40100000, vcc_lo
v_add_f64 v[34:35], v[23:24], -v[25:26]
v_add_f64 v[10:11], v[10:11], -v[25:26]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[15:16], v[15:16], v[29:30]
v_add_f64 v[30:31], v[17:18], -v[23:24]
v_add_f64 v[25:26], v[27:28], -v[34:35]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[32:33], v[19:20], v[15:16]
v_add_f64 v[36:37], v[17:18], -v[30:31]
v_add_f64 v[6:7], v[6:7], -v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[10:11], v[25:26]
v_cvt_i32_f64_e32 v32, v[32:33]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[23:24], v[23:24], -v[36:37]
v_cvt_f64_i32_e32 v[30:31], v32
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[23:24]
v_add_f64 v[15:16], v[15:16], -v[30:31]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[10:11], v[6:7]
v_add_f64 v[10:11], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[6:7], v[10:11], -v[15:16]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[12:13], v[4:5]
v_add_f64 v[6:7], v[19:20], -v[6:7]
v_cndmask_b32_e64 v30, 0, 0x3ff00000, vcc_lo
v_add_co_ci_u32_e64 v15, s0, 0, v32, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[6:7], v[10:11], -v[29:30]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[6:7], v[4:5]
v_mul_f64 v[12:13], v[10:11], s[2:3]
v_add_f64 v[6:7], v[10:11], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[10:11], s[2:3], -v[12:13]
v_add_f64 v[4:5], v[4:5], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[10:11], s[12:13], v[16:17]
v_fma_f64 v[6:7], v[4:5], s[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[12:13], v[6:7]
v_add_f64 v[10:11], v[4:5], -v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[10:11]
.LBB0_5:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_7
v_mul_f64 v[4:5], |v[2:3]|, s[14:15]
s_mov_b32 s10, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[10:11], v[4:5]
v_fma_f64 v[4:5], v[10:11], s[8:9], |v[2:3]|
v_mul_f64 v[6:7], v[10:11], s[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], v[10:11], s[16:17], v[4:5]
v_add_f64 v[12:13], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], -v[12:13]
v_add_f64 v[12:13], v[12:13], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_fma_f64 v[6:7], v[10:11], s[10:11], v[6:7]
v_add_f64 v[4:5], v[12:13], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[6:7]
v_fma_f64 v[6:7], v[10:11], s[18:19], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[15:16], v[6:7]
v_add_f64 v[12:13], v[4:5], -v[15:16]
v_cvt_i32_f64_e32 v15, v[10:11]
s_delay_alu instid0(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[12:13]
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_le_i32_e32 vcc_lo, s33, v14
s_mov_b32 s1, exec_lo
v_cndmask_b32_e64 v10, 0, s33, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v14, v10
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_b64 v[10:11], v[10:11], off
s_waitcnt vmcnt(0)
v_mul_f64 v[8:9], v[8:9], v[10:11]
v_cmpx_ngt_f64_e64 0x41d00000, |v[8:9]|
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_9
v_ldexp_f64 v[10:11], |v[8:9]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[8:9]|
v_trig_preop_f64 v[12:13], |v[8:9]|, 0
v_and_b32_e32 v16, 0x7fffffff, v9
v_trig_preop_f64 v[26:27], |v[8:9]|, 2
v_mov_b32_e32 v34, 0
s_mov_b32 s2, s8
s_mov_b32 s13, s11
v_cndmask_b32_e32 v11, v16, v11, vcc_lo
v_cndmask_b32_e32 v10, v8, v10, vcc_lo
v_trig_preop_f64 v[16:17], |v[8:9]|, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[18:19], v[12:13], v[10:11]
v_mul_f64 v[20:21], v[16:17], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[12:13], v[10:11], -v[18:19]
v_fma_f64 v[16:17], v[16:17], v[10:11], -v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[22:23], v[20:21], v[12:13]
v_add_f64 v[24:25], v[22:23], -v[20:21]
v_add_f64 v[30:31], v[18:19], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[28:29], v[22:23], -v[24:25]
v_add_f64 v[12:13], v[12:13], -v[24:25]
v_ldexp_f64 v[24:25], v[30:31], -2
v_add_f64 v[18:19], v[30:31], -v[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[20:21], -v[28:29]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[24:25]|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[22:23], -v[18:19]
v_add_f64 v[12:13], v[12:13], v[20:21]
v_fract_f64_e32 v[20:21], v[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20
v_mul_f64 v[32:33], v[26:27], v[10:11]
v_ldexp_f64 v[20:21], v[20:21], 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[28:29], v[32:33], v[16:17]
v_fma_f64 v[10:11], v[26:27], v[10:11], -v[32:33]
v_add_f64 v[22:23], v[28:29], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[24:25], v[18:19], v[22:23]
v_add_f64 v[30:31], v[24:25], v[20:21]
v_add_f64 v[18:19], v[24:25], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_gt_f64_e32 vcc_lo, 0, v[30:31]
v_add_f64 v[30:31], v[28:29], -v[32:33]
v_cndmask_b32_e64 v35, 0, 0x40100000, vcc_lo
v_add_f64 v[39:40], v[28:29], -v[30:31]
v_add_f64 v[16:17], v[16:17], -v[30:31]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[20:21], v[20:21], v[34:35]
v_add_f64 v[35:36], v[22:23], -v[28:29]
v_add_f64 v[30:31], v[32:33], -v[39:40]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[37:38], v[24:25], v[20:21]
v_add_f64 v[41:42], v[22:23], -v[35:36]
v_add_f64 v[12:13], v[12:13], -v[35:36]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[16:17], v[16:17], v[30:31]
v_cvt_i32_f64_e32 v37, v[37:38]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[28:29], v[28:29], -v[41:42]
v_cvt_f64_i32_e32 v[35:36], v37
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[12:13], v[28:29]
v_add_f64 v[20:21], v[20:21], -v[35:36]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[16:17], v[12:13]
v_add_f64 v[16:17], v[22:23], -v[18:19]
v_add_f64 v[26:27], v[24:25], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], v[12:13]
v_add_f64 v[12:13], v[26:27], -v[20:21]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[26:27]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[16:17], v[10:11]
v_add_f64 v[12:13], v[24:25], -v[12:13]
v_cndmask_b32_e64 v35, 0, 0x3ff00000, vcc_lo
v_add_co_ci_u32_e64 v16, s0, 0, v37, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], v[12:13]
v_add_f64 v[12:13], v[26:27], -v[34:35]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[17:18], v[12:13], v[10:11]
v_mul_f64 v[19:20], v[17:18], s[2:3]
v_add_f64 v[12:13], v[17:18], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[21:22], v[17:18], s[2:3], -v[19:20]
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[17:18], s[12:13], v[21:22]
v_fma_f64 v[12:13], v[10:11], s[2:3], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[19:20], v[12:13]
v_add_f64 v[17:18], v[10:11], -v[19:20]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[12:13], v[12:13], -v[17:18]
.LBB0_9:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_2
v_mul_f64 v[10:11], |v[8:9]|, s[14:15]
s_mov_b32 s10, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[16:17], v[10:11]
v_fma_f64 v[10:11], v[16:17], s[8:9], |v[8:9]|
v_mul_f64 v[12:13], v[16:17], s[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[16:17], s[16:17], v[10:11]
v_add_f64 v[18:19], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[18:19]
v_add_f64 v[18:19], v[18:19], -v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], v[12:13]
v_fma_f64 v[12:13], v[16:17], s[10:11], v[12:13]
v_add_f64 v[10:11], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_fma_f64 v[12:13], v[16:17], s[18:19], v[10:11]
v_cvt_i32_f64_e32 v16, v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[20:21], v[12:13]
v_add_f64 v[18:19], v[10:11], -v[20:21]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[12:13], v[12:13], -v[18:19]
s_branch .LBB0_2
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13calculate_valPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 49
.amdhsa_next_free_sgpr 48
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13calculate_valPdS_i, .Lfunc_end0-_Z13calculate_valPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13calculate_valPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 50
.sgpr_spill_count: 0
.symbol: _Z13calculate_valPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 49
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//double* x, * devx, * val, * gra, * r, * graMax;
//double* hes_value;
////int size;
//int* pos_x, * pos_y;
//int* csr;
double* x;
//thrust::pair<int, int> *device_pos;
//typedef double (*fp)(double);
//typedef void (*val_fp)(double*, double*, int);
//typedef void (*valsum_fp)(double*, double*,int);
//typedef void (*gra_fp)(double*, double*, int);
//typedef void (*gramin_fp)(double*, double*,int);
//typedef void (*hes_fp)( double*, thrust::pair<int, int>*, double*, int);
//typedef void (*print_fp)(double*, int);
int numSMs;
__device__ void wait() {
for (int i = 1; i <= 10000000; i++);
}
__device__ double sqr(double x) {
return x * x;
}
__global__ void calculate_val(double* devx, double* val, int size) {
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < size;
index += blockDim.x * gridDim.x)
{
int pre = index - 1;
if (pre < 0) pre += size;
int next = index + 1;
if (next >= size) next -= size;
val[index] = sqr(sin(devx[pre] * devx[index])) * sqr(sin(devx[next] * devx[index]));
}
// wait();
} | .text
.file "calculate_val.hip"
.globl _Z28__device_stub__calculate_valPdS_i # -- Begin function _Z28__device_stub__calculate_valPdS_i
.p2align 4, 0x90
.type _Z28__device_stub__calculate_valPdS_i,@function
_Z28__device_stub__calculate_valPdS_i: # @_Z28__device_stub__calculate_valPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13calculate_valPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__calculate_valPdS_i, .Lfunc_end0-_Z28__device_stub__calculate_valPdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13calculate_valPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type x,@object # @x
.bss
.globl x
.p2align 3, 0x0
x:
.quad 0
.size x, 8
.type numSMs,@object # @numSMs
.globl numSMs
.p2align 2, 0x0
numSMs:
.long 0 # 0x0
.size numSMs, 4
.type _Z13calculate_valPdS_i,@object # @_Z13calculate_valPdS_i
.section .rodata,"a",@progbits
.globl _Z13calculate_valPdS_i
.p2align 3, 0x0
_Z13calculate_valPdS_i:
.quad _Z28__device_stub__calculate_valPdS_i
.size _Z13calculate_valPdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13calculate_valPdS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__calculate_valPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13calculate_valPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a30c1_00000000-6_calculate_val.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4waitv
.type _Z4waitv, @function
_Z4waitv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4waitv, .-_Z4waitv
.globl _Z3sqrd
.type _Z3sqrd, @function
_Z3sqrd:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z3sqrd, .-_Z3sqrd
.globl _Z36__device_stub__Z13calculate_valPdS_iPdS_i
.type _Z36__device_stub__Z13calculate_valPdS_iPdS_i, @function
_Z36__device_stub__Z13calculate_valPdS_iPdS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13calculate_valPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z36__device_stub__Z13calculate_valPdS_iPdS_i, .-_Z36__device_stub__Z13calculate_valPdS_iPdS_i
.globl _Z13calculate_valPdS_i
.type _Z13calculate_valPdS_i, @function
_Z13calculate_valPdS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13calculate_valPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13calculate_valPdS_i, .-_Z13calculate_valPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13calculate_valPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13calculate_valPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl numSMs
.bss
.align 4
.type numSMs, @object
.size numSMs, 4
numSMs:
.zero 4
.globl x
.align 8
.type x, @object
.size x, 8
x:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calculate_val.hip"
.globl _Z28__device_stub__calculate_valPdS_i # -- Begin function _Z28__device_stub__calculate_valPdS_i
.p2align 4, 0x90
.type _Z28__device_stub__calculate_valPdS_i,@function
_Z28__device_stub__calculate_valPdS_i: # @_Z28__device_stub__calculate_valPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13calculate_valPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__calculate_valPdS_i, .Lfunc_end0-_Z28__device_stub__calculate_valPdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13calculate_valPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type x,@object # @x
.bss
.globl x
.p2align 3, 0x0
x:
.quad 0
.size x, 8
.type numSMs,@object # @numSMs
.globl numSMs
.p2align 2, 0x0
numSMs:
.long 0 # 0x0
.size numSMs, 4
.type _Z13calculate_valPdS_i,@object # @_Z13calculate_valPdS_i
.section .rodata,"a",@progbits
.globl _Z13calculate_valPdS_i
.p2align 3, 0x0
_Z13calculate_valPdS_i:
.quad _Z28__device_stub__calculate_valPdS_i
.size _Z13calculate_valPdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13calculate_valPdS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__calculate_valPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13calculate_valPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <stdio.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
}
int main()
{
system("PAUSE");
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <stdio.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
}
int main()
{
system("PAUSE");
return 0;
} | #include "hip/hip_runtime.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <stdio.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
}
int main()
{
system("PAUSE");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <stdio.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
}
int main()
{
system("PAUSE");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <stdio.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
}
int main()
{
system("PAUSE");
return 0;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
callq system
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "PAUSE"
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cudaSSqrt_kernel(unsigned int size, float* data)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride)
data[i] = sqrt(data[i]);
} | code for sm_80
Function : _Z16cudaSSqrt_kerneljPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00b0*/ BSSY B0, 0x1b0 ; /* 0x000000f000007945 */
/* 0x000fe80003800000 */
/*00c0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06070 */
/*00e0*/ IADD3 R4, R8, -0xd000000, RZ ; /* 0xf300000008047810 */
/* 0x004fe20007ffe0ff */
/*00f0*/ MUFU.RSQ R7, R8 ; /* 0x0000000800077308 */
/* 0x0000660000001400 */
/*0100*/ ISETP.GT.U32.AND P1, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f24070 */
/*0110*/ @!P1 BRA 0x160 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0120*/ MOV R10, 0x140 ; /* 0x00000140000a7802 */
/* 0x003fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x1e0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0140*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe20000000f00 */
/*0150*/ BRA 0x1a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0160*/ FMUL.FTZ R5, R8, R7 ; /* 0x0000000708057220 */
/* 0x003fe40000410000 */
/*0170*/ FMUL.FTZ R6, R7, 0.5 ; /* 0x3f00000007067820 */
/* 0x000fe40000410000 */
/*0180*/ FFMA R4, -R5, R5, R8 ; /* 0x0000000505047223 */
/* 0x000fc80000000108 */
/*0190*/ FFMA R5, R4, R6, R5 ; /* 0x0000000604057223 */
/* 0x000fe40000000005 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*01c0*/ @!P0 BRA 0x70 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000782c0ff */
/*01f0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0008 */
/*0200*/ @!P1 BRA 0x320 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0210*/ FSETP.GEU.FTZ.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fe40003f3e000 */
/*0220*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fd60000000f00 */
/*0230*/ @!P1 MOV R5, 0x7fffffff ; /* 0x7fffffff00059802 */
/* 0x000fe20000000f00 */
/*0240*/ @!P1 BRA 0x320 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0250*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f3c200 */
/*0260*/ @P1 FADD.FTZ R5, R4, 1 ; /* 0x3f80000004051421 */
/* 0x000fe20000010000 */
/*0270*/ @P1 BRA 0x320 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0280*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f3d200 */
/*0290*/ @P1 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004061823 */
/* 0x000fc800000000ff */
/*02a0*/ @P1 MUFU.RSQ R5, R6 ; /* 0x0000000600051308 */
/* 0x000e240000001400 */
/*02b0*/ @P1 FMUL.FTZ R7, R6, R5 ; /* 0x0000000506071220 */
/* 0x001fe40000410000 */
/*02c0*/ @P1 FMUL.FTZ R9, R5, 0.5 ; /* 0x3f00000005091820 */
/* 0x000fe40000410000 */
/*02d0*/ @P1 FADD.FTZ R8, -R7.reuse, -RZ ; /* 0x800000ff07081221 */
/* 0x040fe40000010100 */
/*02e0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff059224 */
/* 0x000fe400078e0004 */
/*02f0*/ @P1 FFMA R8, R7, R8, R6 ; /* 0x0000000807081223 */
/* 0x000fc80000000006 */
/*0300*/ @P1 FFMA R8, R8, R9, R7 ; /* 0x0000000908081223 */
/* 0x000fc80000000007 */
/*0310*/ @P1 FMUL.FTZ R5, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008051820 */
/* 0x000fca0000410000 */
/*0320*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x000fe20000000f00 */
/*0330*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0340*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fca0000000f00 */
/*0350*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffca004007950 */
/* 0x000fea0003c3ffff */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cudaSSqrt_kernel(unsigned int size, float* data)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride)
data[i] = sqrt(data[i]);
} | .file "tmpxft_000e5f99_00000000-6_cudaSSqrt_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf
.type _Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf, @function
_Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16cudaSSqrt_kerneljPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf, .-_Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf
.globl _Z16cudaSSqrt_kerneljPf
.type _Z16cudaSSqrt_kerneljPf, @function
_Z16cudaSSqrt_kerneljPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16cudaSSqrt_kerneljPf, .-_Z16cudaSSqrt_kerneljPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16cudaSSqrt_kerneljPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16cudaSSqrt_kerneljPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cudaSSqrt_kernel(unsigned int size, float* data)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride)
data[i] = sqrt(data[i]);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSSqrt_kernel(unsigned int size, float* data)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride)
data[i] = sqrt(data[i]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSSqrt_kernel(unsigned int size, float* data)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride)
data[i] = sqrt(data[i]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16cudaSSqrt_kerneljPf
.globl _Z16cudaSSqrt_kerneljPf
.p2align 8
.type _Z16cudaSSqrt_kerneljPf,@function
_Z16cudaSSqrt_kerneljPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s6, s5
s_mov_b32 s5, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_sqrt_f32_e32 v5, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, -1, v5
v_add_nc_u32_e32 v7, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v6, v5, v0
v_fma_f32 v9, -v7, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v5, v5, v6, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v5, v5, v7, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, 0x37800000, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_class_f32_e64 s0, v0, 0x260
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v0, v5, v0, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16cudaSSqrt_kerneljPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16cudaSSqrt_kerneljPf, .Lfunc_end0-_Z16cudaSSqrt_kerneljPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16cudaSSqrt_kerneljPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16cudaSSqrt_kerneljPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSSqrt_kernel(unsigned int size, float* data)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride)
data[i] = sqrt(data[i]);
} | .text
.file "cudaSSqrt_kernel.hip"
.globl _Z31__device_stub__cudaSSqrt_kerneljPf # -- Begin function _Z31__device_stub__cudaSSqrt_kerneljPf
.p2align 4, 0x90
.type _Z31__device_stub__cudaSSqrt_kerneljPf,@function
_Z31__device_stub__cudaSSqrt_kerneljPf: # @_Z31__device_stub__cudaSSqrt_kerneljPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16cudaSSqrt_kerneljPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__cudaSSqrt_kerneljPf, .Lfunc_end0-_Z31__device_stub__cudaSSqrt_kerneljPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16cudaSSqrt_kerneljPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16cudaSSqrt_kerneljPf,@object # @_Z16cudaSSqrt_kerneljPf
.section .rodata,"a",@progbits
.globl _Z16cudaSSqrt_kerneljPf
.p2align 3, 0x0
_Z16cudaSSqrt_kerneljPf:
.quad _Z31__device_stub__cudaSSqrt_kerneljPf
.size _Z16cudaSSqrt_kerneljPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16cudaSSqrt_kerneljPf"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__cudaSSqrt_kerneljPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16cudaSSqrt_kerneljPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16cudaSSqrt_kerneljPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00b0*/ BSSY B0, 0x1b0 ; /* 0x000000f000007945 */
/* 0x000fe80003800000 */
/*00c0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06070 */
/*00e0*/ IADD3 R4, R8, -0xd000000, RZ ; /* 0xf300000008047810 */
/* 0x004fe20007ffe0ff */
/*00f0*/ MUFU.RSQ R7, R8 ; /* 0x0000000800077308 */
/* 0x0000660000001400 */
/*0100*/ ISETP.GT.U32.AND P1, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f24070 */
/*0110*/ @!P1 BRA 0x160 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0120*/ MOV R10, 0x140 ; /* 0x00000140000a7802 */
/* 0x003fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x1e0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0140*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe20000000f00 */
/*0150*/ BRA 0x1a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0160*/ FMUL.FTZ R5, R8, R7 ; /* 0x0000000708057220 */
/* 0x003fe40000410000 */
/*0170*/ FMUL.FTZ R6, R7, 0.5 ; /* 0x3f00000007067820 */
/* 0x000fe40000410000 */
/*0180*/ FFMA R4, -R5, R5, R8 ; /* 0x0000000505047223 */
/* 0x000fc80000000108 */
/*0190*/ FFMA R5, R4, R6, R5 ; /* 0x0000000604057223 */
/* 0x000fe40000000005 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*01c0*/ @!P0 BRA 0x70 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000782c0ff */
/*01f0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0008 */
/*0200*/ @!P1 BRA 0x320 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0210*/ FSETP.GEU.FTZ.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fe40003f3e000 */
/*0220*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fd60000000f00 */
/*0230*/ @!P1 MOV R5, 0x7fffffff ; /* 0x7fffffff00059802 */
/* 0x000fe20000000f00 */
/*0240*/ @!P1 BRA 0x320 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0250*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f3c200 */
/*0260*/ @P1 FADD.FTZ R5, R4, 1 ; /* 0x3f80000004051421 */
/* 0x000fe20000010000 */
/*0270*/ @P1 BRA 0x320 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0280*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f3d200 */
/*0290*/ @P1 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004061823 */
/* 0x000fc800000000ff */
/*02a0*/ @P1 MUFU.RSQ R5, R6 ; /* 0x0000000600051308 */
/* 0x000e240000001400 */
/*02b0*/ @P1 FMUL.FTZ R7, R6, R5 ; /* 0x0000000506071220 */
/* 0x001fe40000410000 */
/*02c0*/ @P1 FMUL.FTZ R9, R5, 0.5 ; /* 0x3f00000005091820 */
/* 0x000fe40000410000 */
/*02d0*/ @P1 FADD.FTZ R8, -R7.reuse, -RZ ; /* 0x800000ff07081221 */
/* 0x040fe40000010100 */
/*02e0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff059224 */
/* 0x000fe400078e0004 */
/*02f0*/ @P1 FFMA R8, R7, R8, R6 ; /* 0x0000000807081223 */
/* 0x000fc80000000006 */
/*0300*/ @P1 FFMA R8, R8, R9, R7 ; /* 0x0000000908081223 */
/* 0x000fc80000000007 */
/*0310*/ @P1 FMUL.FTZ R5, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008051820 */
/* 0x000fca0000410000 */
/*0320*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x000fe20000000f00 */
/*0330*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0340*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fca0000000f00 */
/*0350*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffca004007950 */
/* 0x000fea0003c3ffff */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16cudaSSqrt_kerneljPf
.globl _Z16cudaSSqrt_kerneljPf
.p2align 8
.type _Z16cudaSSqrt_kerneljPf,@function
_Z16cudaSSqrt_kerneljPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s6, s5
s_mov_b32 s5, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_sqrt_f32_e32 v5, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, -1, v5
v_add_nc_u32_e32 v7, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v6, v5, v0
v_fma_f32 v9, -v7, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v5, v5, v6, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v5, v5, v7, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, 0x37800000, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_class_f32_e64 s0, v0, 0x260
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v0, v5, v0, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16cudaSSqrt_kerneljPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16cudaSSqrt_kerneljPf, .Lfunc_end0-_Z16cudaSSqrt_kerneljPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16cudaSSqrt_kerneljPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16cudaSSqrt_kerneljPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e5f99_00000000-6_cudaSSqrt_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf
.type _Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf, @function
_Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16cudaSSqrt_kerneljPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf, .-_Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf
.globl _Z16cudaSSqrt_kerneljPf
.type _Z16cudaSSqrt_kerneljPf, @function
_Z16cudaSSqrt_kerneljPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16cudaSSqrt_kerneljPfjPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16cudaSSqrt_kerneljPf, .-_Z16cudaSSqrt_kerneljPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16cudaSSqrt_kerneljPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16cudaSSqrt_kerneljPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaSSqrt_kernel.hip"
.globl _Z31__device_stub__cudaSSqrt_kerneljPf # -- Begin function _Z31__device_stub__cudaSSqrt_kerneljPf
.p2align 4, 0x90
.type _Z31__device_stub__cudaSSqrt_kerneljPf,@function
_Z31__device_stub__cudaSSqrt_kerneljPf: # @_Z31__device_stub__cudaSSqrt_kerneljPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16cudaSSqrt_kerneljPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__cudaSSqrt_kerneljPf, .Lfunc_end0-_Z31__device_stub__cudaSSqrt_kerneljPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16cudaSSqrt_kerneljPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16cudaSSqrt_kerneljPf,@object # @_Z16cudaSSqrt_kerneljPf
.section .rodata,"a",@progbits
.globl _Z16cudaSSqrt_kerneljPf
.p2align 3, 0x0
_Z16cudaSSqrt_kerneljPf:
.quad _Z31__device_stub__cudaSSqrt_kerneljPf
.size _Z16cudaSSqrt_kerneljPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16cudaSSqrt_kerneljPf"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__cudaSSqrt_kerneljPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16cudaSSqrt_kerneljPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //xfail:REPAIR_ERROR
//--blockDim=8 --gridDim=1 --no-inline
// The statically given values for A are not preserved when we translate CUDA
// since the host is free to change the contents of A.
// cf. testsuite/OpenCL/globalarray/pass2
__constant__ int A[8] = {0,1,2,3,4,5,6,7};
__global__ void globalarray(float* p) {
int i = threadIdx.x;
int a = A[i];
if(a != threadIdx.x) {
p[0] = threadIdx.x;
}
} | code for sm_80
Function : _Z11globalarrayPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0020*/ IMAD.SHL.U32 R0, R5, 0x4, RZ ; /* 0x0000000405007824 */
/* 0x001fcc00078e00ff */
/*0030*/ LDC R0, c[0x3][R0] ; /* 0x00c0000000007b82 */
/* 0x000e240000000800 */
/*0040*/ ISETP.NE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x001fda0003f05270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ I2F.U32 R5, R5 ; /* 0x0000000500057306 */
/* 0x000e220000201000 */
/*0070*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //xfail:REPAIR_ERROR
//--blockDim=8 --gridDim=1 --no-inline
// The statically given values for A are not preserved when we translate CUDA
// since the host is free to change the contents of A.
// cf. testsuite/OpenCL/globalarray/pass2
__constant__ int A[8] = {0,1,2,3,4,5,6,7};
__global__ void globalarray(float* p) {
int i = threadIdx.x;
int a = A[i];
if(a != threadIdx.x) {
p[0] = threadIdx.x;
}
} | .file "tmpxft_001100fe_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11globalarrayPfPf
.type _Z31__device_stub__Z11globalarrayPfPf, @function
_Z31__device_stub__Z11globalarrayPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11globalarrayPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z11globalarrayPfPf, .-_Z31__device_stub__Z11globalarrayPfPf
.globl _Z11globalarrayPf
.type _Z11globalarrayPf, @function
_Z11globalarrayPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11globalarrayPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11globalarrayPf, .-_Z11globalarrayPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11globalarrayPf"
.LC1:
.string "A"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11globalarrayPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $32, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1A(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1A
.comm _ZL1A,32,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //xfail:REPAIR_ERROR
//--blockDim=8 --gridDim=1 --no-inline
// The statically given values for A are not preserved when we translate CUDA
// since the host is free to change the contents of A.
// cf. testsuite/OpenCL/globalarray/pass2
__constant__ int A[8] = {0,1,2,3,4,5,6,7};
__global__ void globalarray(float* p) {
int i = threadIdx.x;
int a = A[i];
if(a != threadIdx.x) {
p[0] = threadIdx.x;
}
} | #include <hip/hip_runtime.h>
//xfail:REPAIR_ERROR
//--blockDim=8 --gridDim=1 --no-inline
// The statically given values for A are not preserved when we translate CUDA
// since the host is free to change the contents of A.
// cf. testsuite/OpenCL/globalarray/pass2
__constant__ int A[8] = {0,1,2,3,4,5,6,7};
__global__ void globalarray(float* p) {
int i = threadIdx.x;
int a = A[i];
if(a != threadIdx.x) {
p[0] = threadIdx.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//xfail:REPAIR_ERROR
//--blockDim=8 --gridDim=1 --no-inline
// The statically given values for A are not preserved when we translate CUDA
// since the host is free to change the contents of A.
// cf. testsuite/OpenCL/globalarray/pass2
__constant__ int A[8] = {0,1,2,3,4,5,6,7};
__global__ void globalarray(float* p) {
int i = threadIdx.x;
int a = A[i];
if(a != threadIdx.x) {
p[0] = threadIdx.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11globalarrayPf
.globl _Z11globalarrayPf
.p2align 8
.type _Z11globalarrayPf,@function
_Z11globalarrayPf:
v_lshlrev_b32_e32 v1, 2, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, A@rel32@lo+4
s_addc_u32 s3, s3, A@rel32@hi+12
global_load_b32 v1, v1, s[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v1, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_cvt_f32_u32_e32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11globalarrayPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11globalarrayPf, .Lfunc_end0-_Z11globalarrayPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected A
.type A,@object
.data
.globl A
.p2align 4, 0x0
A:
.long 0
.long 1
.long 2
.long 3
.long 4
.long 5
.long 6
.long 7
.size A, 32
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym A
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11globalarrayPf
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z11globalarrayPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//xfail:REPAIR_ERROR
//--blockDim=8 --gridDim=1 --no-inline
// The statically given values for A are not preserved when we translate CUDA
// since the host is free to change the contents of A.
// cf. testsuite/OpenCL/globalarray/pass2
__constant__ int A[8] = {0,1,2,3,4,5,6,7};
__global__ void globalarray(float* p) {
int i = threadIdx.x;
int a = A[i];
if(a != threadIdx.x) {
p[0] = threadIdx.x;
}
} | .text
.file "kernel.hip"
.globl _Z26__device_stub__globalarrayPf # -- Begin function _Z26__device_stub__globalarrayPf
.p2align 4, 0x90
.type _Z26__device_stub__globalarrayPf,@function
_Z26__device_stub__globalarrayPf: # @_Z26__device_stub__globalarrayPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11globalarrayPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__globalarrayPf, .Lfunc_end0-_Z26__device_stub__globalarrayPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11globalarrayPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $A, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $32, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type A,@object # @A
.local A
.comm A,32,16
.type _Z11globalarrayPf,@object # @_Z11globalarrayPf
.section .rodata,"a",@progbits
.globl _Z11globalarrayPf
.p2align 3, 0x0
_Z11globalarrayPf:
.quad _Z26__device_stub__globalarrayPf
.size _Z11globalarrayPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11globalarrayPf"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "A"
.size .L__unnamed_2, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__globalarrayPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A
.addrsig_sym _Z11globalarrayPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11globalarrayPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0020*/ IMAD.SHL.U32 R0, R5, 0x4, RZ ; /* 0x0000000405007824 */
/* 0x001fcc00078e00ff */
/*0030*/ LDC R0, c[0x3][R0] ; /* 0x00c0000000007b82 */
/* 0x000e240000000800 */
/*0040*/ ISETP.NE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x001fda0003f05270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ I2F.U32 R5, R5 ; /* 0x0000000500057306 */
/* 0x000e220000201000 */
/*0070*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11globalarrayPf
.globl _Z11globalarrayPf
.p2align 8
.type _Z11globalarrayPf,@function
_Z11globalarrayPf:
v_lshlrev_b32_e32 v1, 2, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, A@rel32@lo+4
s_addc_u32 s3, s3, A@rel32@hi+12
global_load_b32 v1, v1, s[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v1, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_cvt_f32_u32_e32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11globalarrayPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11globalarrayPf, .Lfunc_end0-_Z11globalarrayPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected A
.type A,@object
.data
.globl A
.p2align 4, 0x0
A:
.long 0
.long 1
.long 2
.long 3
.long 4
.long 5
.long 6
.long 7
.size A, 32
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym A
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11globalarrayPf
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z11globalarrayPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001100fe_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11globalarrayPfPf
.type _Z31__device_stub__Z11globalarrayPfPf, @function
_Z31__device_stub__Z11globalarrayPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11globalarrayPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z11globalarrayPfPf, .-_Z31__device_stub__Z11globalarrayPfPf
.globl _Z11globalarrayPf
.type _Z11globalarrayPf, @function
_Z11globalarrayPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11globalarrayPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11globalarrayPf, .-_Z11globalarrayPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11globalarrayPf"
.LC1:
.string "A"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11globalarrayPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $32, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1A(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1A
.comm _ZL1A,32,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z26__device_stub__globalarrayPf # -- Begin function _Z26__device_stub__globalarrayPf
.p2align 4, 0x90
.type _Z26__device_stub__globalarrayPf,@function
_Z26__device_stub__globalarrayPf: # @_Z26__device_stub__globalarrayPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11globalarrayPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__globalarrayPf, .Lfunc_end0-_Z26__device_stub__globalarrayPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11globalarrayPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $A, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $32, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type A,@object # @A
.local A
.comm A,32,16
.type _Z11globalarrayPf,@object # @_Z11globalarrayPf
.section .rodata,"a",@progbits
.globl _Z11globalarrayPf
.p2align 3, 0x0
_Z11globalarrayPf:
.quad _Z26__device_stub__globalarrayPf
.size _Z11globalarrayPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11globalarrayPf"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "A"
.size .L__unnamed_2, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__globalarrayPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A
.addrsig_sym _Z11globalarrayPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void upscale(float *input, float *output, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
int ipidx = translate_idx(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy);
output[ii]=input[ipidx];
} | code for sm_80
Function : _Z7upscalePfS_liiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0050*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe400078e0200 */
/*00a0*/ IMAD R3, R2, UR4, R5 ; /* 0x0000000402037c24 */
/* 0x002fca000f8e0205 */
/*00b0*/ IADD3 R0, P1, R0, R3, RZ ; /* 0x0000000300007210 */
/* 0x000fc80007f3e0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*00d0*/ IMAD.X R5, RZ, RZ, RZ, P1 ; /* 0x000000ffff057224 */
/* 0x000fca00008e06ff */
/*00e0*/ ISETP.GE.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06300 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IABS R4, c[0x0][0x18c] ; /* 0x0000630000047a13 */
/* 0x000fe20000000000 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*0130*/ I2F.RP R7, R4 ; /* 0x0000000400077306 */
/* 0x000e220000209400 */
/*0140*/ IABS R6, c[0x0][0x188] ; /* 0x0000620000067a13 */
/* 0x000fce0000000000 */
/*0150*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0160*/ IADD3 R2, R7, 0xffffffe, RZ ; /* 0x0ffffffe07027810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a03 */
/*01a0*/ IMAD R9, R9, R4, RZ ; /* 0x0000000409097224 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fe200078e0002 */
/*01c0*/ LOP3.LUT R2, R0, c[0x0][0x18c], RZ, 0x3c, !PT ; /* 0x0000630000027a12 */
/* 0x000fc600078e3cff */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0008 */
/*01e0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*01f0*/ I2F.RP R8, R6 ; /* 0x0000000600087306 */
/* 0x000e220000209400 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.HI.U32 R7, R3, R9, RZ ; /* 0x0000000903077227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*0230*/ IMAD R3, R4.reuse, R3, R9 ; /* 0x0000000304037224 */
/* 0x040fe200078e0209 */
/*0240*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e280000001000 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f24070 */
/*0260*/ @!P1 IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a04 */
/*0270*/ @!P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107079810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3 R9, R8, 0xffffffe, RZ ; /* 0x0ffffffe08097810 */
/* 0x001fe40007ffe0ff */
/*0290*/ ISETP.GE.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fe40003f06070 */
/*02a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R9 ; /* 0x0000000900037305 */
/* 0x000e22000021f000 */
/*02b0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fe40003f25270 */
/*02c0*/ IABS R8, c[0x0][0x184] ; /* 0x0000610000087a13 */
/* 0x000fd00000000000 */
/*02d0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD.MOV R11, RZ, RZ, -R3 ; /* 0x000000ffff0b7224 */
/* 0x001fc800078e0a03 */
/*02f0*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0300*/ @!P1 LOP3.LUT R7, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff079a12 */
/* 0x000fe200078e33ff */
/*0310*/ IMAD R9, R11, R6, RZ ; /* 0x000000060b097224 */
/* 0x000fe200078e02ff */
/*0320*/ IABS R11, c[0x0][0x178] ; /* 0x00005e00000b7a13 */
/* 0x000fe40000000000 */
/*0330*/ IABS R10, R7 ; /* 0x00000007000a7213 */
/* 0x000fe20000000000 */
/*0340*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fe200078e0002 */
/*0350*/ I2F.RP R16, R11 ; /* 0x0000000b00107306 */
/* 0x000e260000209400 */
/*0360*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fc800078e000a */
/*0370*/ IMAD.HI.U32 R14, R2, R3, RZ ; /* 0x00000003020e7227 */
/* 0x000fe200078e00ff */
/*0380*/ I2F.RP R9, R8 ; /* 0x0000000800097306 */
/* 0x000e660000209400 */
/*0390*/ IMAD.MOV R2, RZ, RZ, -R14 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a0e */
/*03a0*/ IMAD R3, R6.reuse, R2, R3 ; /* 0x0000000206037224 */
/* 0x040fe200078e0203 */
/*03b0*/ LOP3.LUT R2, R7, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x0000620007027a12 */
/* 0x000fe200078e3cff */
/*03c0*/ MUFU.RCP R16, R16 ; /* 0x0000001000107308 */
/* 0x001e260000001000 */
/*03d0*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe40003f24070 */
/*03e0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*03f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0400*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x002e700000001000 */
/*0410*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a06 */
/*0420*/ @!P1 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e9810 */
/* 0x000fc40007ffe0ff */
/*0430*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fe40003f25270 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f06070 */
/*0450*/ IADD3 R12, R16, 0xffffffe, RZ ; /* 0x0ffffffe100c7810 */
/* 0x001fe40007ffe0ff */
/*0460*/ IADD3 R10, R9, 0xffffffe, RZ ; /* 0x0ffffffe090a7810 */
/* 0x002fe40007ffe0ff */
/*0470*/ F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; /* 0x0000000c000d7305 */
/* 0x00006e000021f000 */
/*0480*/ @P0 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e0810 */
/* 0x000fe20007ffe0ff */
/*0490*/ F2I.FTZ.U32.TRUNC.NTZ R3, R10 ; /* 0x0000000a00037305 */
/* 0x0004e2000021f000 */
/*04a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x001fc600078e00ff */
/*04b0*/ @!P2 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0ea224 */
/* 0x000fe200078e0a0e */
/*04c0*/ @!P1 LOP3.LUT R14, RZ, c[0x0][0x188], RZ, 0x33, !PT ; /* 0x00006200ff0e9a12 */
/* 0x000fe200078e33ff */
/*04d0*/ IMAD.MOV R16, RZ, RZ, -R13 ; /* 0x000000ffff107224 */
/* 0x002fc600078e0a0d */
/*04e0*/ IABS R10, R14 ; /* 0x0000000e000a7213 */
/* 0x004fe20000000000 */
/*04f0*/ IMAD R17, R16, R11, RZ ; /* 0x0000000b10117224 */
/* 0x000fe400078e02ff */
/*0500*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x008fe400078e0a03 */
/*0510*/ IMAD.HI.U32 R13, R13, R17, R12 ; /* 0x000000110d0d7227 */
/* 0x000fc800078e000c */
/*0520*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0530*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fe200078e0002 */
/*0540*/ IABS R9, c[0x0][0x17c] ; /* 0x00005f0000097a13 */
/* 0x000fc60000000000 */
/*0550*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0560*/ I2F.RP R15, R9 ; /* 0x00000009000f7306 */
/* 0x000e260000209400 */
/*0570*/ IMAD.HI.U32 R10, R2, R3, RZ ; /* 0x00000003020a7227 */
/* 0x000fc800078e00ff */
/*0580*/ IMAD.MOV R2, RZ, RZ, -R10 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a0a */
/*0590*/ IMAD R3, R8, R2, R3 ; /* 0x0000000208037224 */
/* 0x000fe200078e0203 */
/*05a0*/ LOP3.LUT R2, R14, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x000061000e027a12 */
/* 0x000fc800078e3cff */
/*05b0*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fe20003f24070 */
/*05c0*/ MUFU.RCP R15, R15 ; /* 0x0000000f000f7308 */
/* 0x001e220000001000 */
/*05d0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f46270 */
/*05e0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a08 */
/*05f0*/ @!P1 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a9810 */
/* 0x000fe40007ffe0ff */
/*0600*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fe40003f25270 */
/*0610*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*0620*/ IADD3 R2, R15, 0xffffffe, RZ ; /* 0x0ffffffe0f027810 */
/* 0x001fc80007ffe0ff */
/*0630*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000e2e000021f000 */
/*0640*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fca0007ffe0ff */
/*0650*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*0660*/ @!P1 LOP3.LUT R10, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff0a9a12 */
/* 0x000fe200078e33ff */
/*0670*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x001fc800078e0a03 */
/*0680*/ IMAD.MOV R15, RZ, RZ, -R10 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0a0a */
/*0690*/ IMAD R17, R2, R9, RZ ; /* 0x0000000902117224 */
/* 0x000fe400078e02ff */
/*06a0*/ IMAD R15, R15, c[0x0][0x184], R14.reuse ; /* 0x000061000f0f7a24 */
/* 0x100fe400078e020e */
/*06b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*06c0*/ IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0e */
/*06d0*/ IABS R18, R15 ; /* 0x0000000f00127213 */
/* 0x000fe20000000000 */
/*06e0*/ IMAD.HI.U32 R17, R3, R17, R2 ; /* 0x0000001103117227 */
/* 0x000fe200078e0002 */
/*06f0*/ LOP3.LUT R15, R15, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e000f0f7a12 */
/* 0x000fc600078e3cff */
/*0700*/ IMAD.HI.U32 R12, R13, R18, RZ ; /* 0x000000120d0c7227 */
/* 0x000fe200078e00ff */
/*0710*/ ISETP.GE.AND P6, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003fc6270 */
/*0720*/ IMAD.MOV R16, RZ, RZ, -R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0a0c */
/*0730*/ IMAD.HI.U32 R13, R13, R8, RZ ; /* 0x000000080d0d7227 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD R18, R11, R16, R18 ; /* 0x000000100b127224 */
/* 0x000fe400078e0212 */
/*0750*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a0d */
/*0760*/ IMAD.HI.U32 R2, R17, R6, RZ ; /* 0x0000000611027227 */
/* 0x000fe200078e00ff */
/*0770*/ ISETP.GT.U32.AND P0, PT, R11, R18, PT ; /* 0x000000120b00720c */
/* 0x000fc60003f04070 */
/*0780*/ IMAD R16, R11.reuse, R3, R8 ; /* 0x000000030b107224 */
/* 0x040fe400078e0208 */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe400078e00ff */
/*07a0*/ IMAD R8, R14, c[0x0][0x188], R7.reuse ; /* 0x000062000e087a24 */
/* 0x100fe200078e0207 */
/*07b0*/ ISETP.GT.U32.AND P2, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f44070 */
/*07c0*/ IMAD.MOV R20, RZ, RZ, -R2 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0a02 */
/*07d0*/ LOP3.LUT R3, R3, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0003037a12 */
/* 0x000fe200078e3cff */
/*07e0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*07f0*/ IABS R24, R8 ; /* 0x0000000800187213 */
/* 0x000fe20000000000 */
/*0800*/ @!P0 IMAD.IADD R18, R18, 0x1, -R11 ; /* 0x0000000112128824 */
/* 0x000fe200078e0a0b */
/*0810*/ ISETP.GE.AND P3, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f66270 */
/*0820*/ IMAD R20, R9, R20, R6 ; /* 0x0000001409147224 */
/* 0x000fe200078e0206 */
/*0830*/ @!P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c8810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD R7, R7, c[0x0][0x18c], R0 ; /* 0x0000630007077a24 */
/* 0x000fe200078e0200 */
/*0850*/ ISETP.GE.U32.AND P4, PT, R18, R11, PT ; /* 0x0000000b1200720c */
/* 0x000fe20003f86070 */
/*0860*/ IMAD.HI.U32 R3, R17, R4, RZ ; /* 0x0000000411037227 */
/* 0x000fe200078e00ff */
/*0870*/ ISETP.GT.U32.AND P5, PT, R9, R20, PT ; /* 0x000000140900720c */
/* 0x000fc40003fa4070 */
/*0880*/ IABS R22, R7 ; /* 0x0000000700167213 */
/* 0x000fe20000000000 */
/*0890*/ IMAD.HI.U32 R6, R17, R24, RZ ; /* 0x0000001811067227 */
/* 0x000fe200078e00ff */
/*08a0*/ @!P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0da810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ LOP3.LUT R8, R8, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0008087a12 */
/* 0x000fe200078e3cff */
/*08c0*/ @!P2 IMAD.IADD R16, R16, 0x1, -R11 ; /* 0x000000011010a824 */
/* 0x000fe200078e0a0b */
/*08d0*/ LOP3.LUT R7, R7, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0007077a12 */
/* 0x000fe200078e3cff */
/*08e0*/ IMAD.MOV R14, RZ, RZ, -R3 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0a03 */
/*08f0*/ IMAD.MOV R18, RZ, RZ, -R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0a06 */
/*0900*/ ISETP.GE.U32.AND P1, PT, R16, R11, PT ; /* 0x0000000b1000720c */
/* 0x000fe20003f26070 */
/*0910*/ IMAD R14, R9.reuse, R14, R4 ; /* 0x0000000e090e7224 */
/* 0x040fe200078e0204 */
/*0920*/ @P4 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c4810 */
/* 0x000fe20007ffe0ff */
/*0930*/ IMAD R18, R9, R18, R24 ; /* 0x0000001209127224 */
/* 0x000fe200078e0218 */
/*0940*/ LOP3.LUT R11, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff0b7a12 */
/* 0x000fe200078e33ff */
/*0950*/ IMAD.HI.U32 R4, R17, R22, RZ ; /* 0x0000001611047227 */
/* 0x000fe200078e00ff */
/*0960*/ ISETP.GT.U32.AND P2, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fc40003f44070 */
/*0970*/ ISETP.GT.U32.AND P4, PT, R9.reuse, R18, PT ; /* 0x000000120900720c */
/* 0x040fe20003f84070 */
/*0980*/ IMAD.MOV R16, RZ, RZ, -R4 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0a04 */
/*0990*/ @!P5 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202d810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0f7624 */
/* 0x000fe400078e00ff */
/*09b0*/ IMAD R16, R9, R16, R22 ; /* 0x0000001009107224 */
/* 0x000fe200078e0216 */
/*09c0*/ @P1 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d1810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ @!P6 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0ce224 */
/* 0x000fe200078e0a0c */
/*09e0*/ LOP3.LUT R15, R15, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f000f0f7a12 */
/* 0x000fe200078e3cff */
/*09f0*/ @!P5 IMAD.IADD R20, R20, 0x1, -R9 ; /* 0x000000011414d824 */
/* 0x000fe200078e0a09 */
/*0a00*/ ISETP.GT.U32.AND P1, PT, R9, R16, PT ; /* 0x000000100900720c */
/* 0x000fe20003f24070 */
/*0a10*/ @!P3 IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0db224 */
/* 0x000fe200078e0a0d */
/*0a20*/ ISETP.NE.AND P6, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003fc5270 */
/*0a30*/ @!P4 IMAD.IADD R18, R18, 0x1, -R9.reuse ; /* 0x000000011212c824 */
/* 0x100fe200078e0a09 */
/*0a40*/ ISETP.GE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f66270 */
/*0a50*/ @!P2 IMAD.IADD R14, R14, 0x1, -R9 ; /* 0x000000010e0ea824 */
/* 0x000fe200078e0a09 */
/*0a60*/ SEL R15, R11.reuse, R12, !P6 ; /* 0x0000000c0b0f7207 */
/* 0x040fe20007000000 */
/*0a70*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0c7624 */
/* 0x000fe200078e00ff */
/*0a80*/ SEL R11, R11, R13, !P6 ; /* 0x0000000d0b0b7207 */
/* 0x000fc40007000000 */
/*0a90*/ ISETP.GE.U32.AND P0, PT, R20, R9.reuse, PT ; /* 0x000000091400720c */
/* 0x080fe40003f06070 */
/*0aa0*/ ISETP.GE.U32.AND P6, PT, R18, R9, PT ; /* 0x000000091200720c */
/* 0x000fe20003fc6070 */
/*0ab0*/ @!P1 IMAD.IADD R16, R16, 0x1, -R9 ; /* 0x0000000110109824 */
/* 0x000fe200078e0a09 */
/*0ac0*/ @!P4 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606c810 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ IMAD R11, R10, R11, R15 ; /* 0x0000000b0a0b7224 */
/* 0x000fe200078e020f */
/*0ae0*/ ISETP.GE.U32.AND P4, PT, R14, R9.reuse, PT ; /* 0x000000090e00720c */
/* 0x080fe40003f86070 */
/*0af0*/ ISETP.GE.U32.AND P5, PT, R16, R9, PT ; /* 0x000000091000720c */
/* 0x000fe40003fa6070 */
/*0b00*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fc40007ffe0ff */
/*0b10*/ LOP3.LUT R12, R12, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f000c0c7a12 */
/* 0x000fe400078e3cff */
/*0b20*/ ISETP.GE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f26270 */
/*0b30*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0b40*/ @P6 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106066810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f06270 */
/*0b60*/ @!P3 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02b224 */
/* 0x000fe200078e0a02 */
/*0b70*/ ISETP.GE.AND P6, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc40003fc6270 */
/*0b80*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ @P5 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104045810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ @!P1 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0a06 */
/*0bb0*/ @P4 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103034810 */
/* 0x000fe40007ffe0ff */
/*0bc0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*0bd0*/ LOP3.LUT R7, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff077a12 */
/* 0x000fe200078e33ff */
/*0be0*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0a03 */
/*0bf0*/ @!P6 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04e224 */
/* 0x000fe200078e0a04 */
/*0c00*/ SEL R2, R7, R2, !P2 ; /* 0x0000000207027207 */
/* 0x000fc40005000000 */
/*0c10*/ SEL R9, R7.reuse, R6, !P2 ; /* 0x0000000607097207 */
/* 0x040fe40005000000 */
/*0c20*/ SEL R3, R7.reuse, R3, !P2 ; /* 0x0000000307037207 */
/* 0x040fe40005000000 */
/*0c30*/ SEL R4, R7, R4, !P2 ; /* 0x0000000407047207 */
/* 0x000fe20005000000 */
/*0c40*/ IMAD R9, R11, R2, R9 ; /* 0x000000020b097224 */
/* 0x000fe400078e0209 */
/*0c50*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0c60*/ IMAD R3, R9, R3, R4 ; /* 0x0000000309037224 */
/* 0x000fc800078e0204 */
/*0c70*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*0c80*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0c90*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0ca0*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f1405 */
/*0cb0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0cc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void upscale(float *input, float *output, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
int ipidx = translate_idx(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy);
output[ii]=input[ipidx];
} | .file "tmpxft_00070969_00000000-6_upscale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13translate_idxiiiiiii
.type _Z13translate_idxiiiiiii, @function
_Z13translate_idxiiiiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13translate_idxiiiiiii, .-_Z13translate_idxiiiiiii
.globl _Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii
.type _Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii, @function
_Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7upscalePfS_liiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii, .-_Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii
.globl _Z7upscalePfS_liiiiii
.type _Z7upscalePfS_liiiiii, @function
_Z7upscalePfS_liiiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z35__device_stub__Z7upscalePfS_liiiiiiPfS_liiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7upscalePfS_liiiiii, .-_Z7upscalePfS_liiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7upscalePfS_liiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7upscalePfS_liiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void upscale(float *input, float *output, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
int ipidx = translate_idx(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy);
output[ii]=input[ipidx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void upscale(float *input, float *output, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
int ipidx = translate_idx(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy);
output[ii]=input[ipidx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void upscale(float *input, float *output, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
int ipidx = translate_idx(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy);
output[ii]=input[ipidx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7upscalePfS_liiiiii
.globl _Z7upscalePfS_liiiiii
.p2align 8
.type _Z7upscalePfS_liiiiii,@function
_Z7upscalePfS_liiiiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s5, s[0:1], 0x30
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_mul_i32 s5, s5, s15
s_lshr_b32 s4, s4, 16
s_mul_i32 s5, s5, s6
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
v_mad_u64_u32 v[3:4], null, s5, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s4, v3, v2
v_add_co_ci_u32_e64 v1, null, 0, 0, s4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s6, s[0:1], 0x2c
v_ashrrev_i32_e32 v4, 31, v0
s_load_b64 s[10:11], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v0, v4
v_xor_b32_e32 v5, v5, v4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s6, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s6, s4
v_xor_b32_e32 v4, s4, v4
s_xor_b32 s5, s2, s4
s_ashr_i32 s14, s10, 31
v_cvt_f32_u32_e32 v2, s5
s_sub_i32 s2, 0, s5
s_add_i32 s10, s10, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s10, s10, s14
v_rcp_iflag_f32_e32 v2, v2
v_cvt_f32_u32_e32 v9, s10
s_sub_i32 s19, 0, s10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, s2, v2
s_load_b64 s[2:3], s[0:1], 0x24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_hi_u32 v2, v5, v2
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s3, 31
s_ashr_i32 s12, s2, 31
s_add_i32 s8, s3, s7
s_xor_b32 s15, s12, s14
s_xor_b32 s8, s8, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v6, s8
v_mul_lo_u32 v3, v2, s5
s_sub_i32 s9, 0, s8
v_rcp_iflag_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v2
v_subrev_nc_u32_e32 v7, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x4f7ffffe, v6
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 1, v2
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v3, v6
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v5, s9, v3
s_add_i32 s9, s2, s12
s_xor_b32 s13, s9, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v4
v_cvt_f32_u32_e32 v7, s13
s_sub_i32 s9, 0, s13
v_mul_hi_u32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v2, v2, v4
v_rcp_iflag_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v2
v_add_nc_u32_e32 v3, v3, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v7, 0x4f7ffffe, v7 :: v_dual_add_nc_u32 v6, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v6, v4
v_xor_b32_e32 v4, s7, v4
v_mul_hi_u32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v3, s8
v_sub_nc_u32_e32 v5, v5, v6
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v8, s8, v5
v_cmp_le_u32_e32 vcc_lo, s8, v5
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v5, v8 :: v_dual_add_nc_u32 v6, 1, v3
v_cmp_le_u32_e32 vcc_lo, s8, v5
v_cvt_u32_f32_e32 v5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_mul_lo_u32 v6, s9, v5
s_ashr_i32 s9, s11, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s11, s11, s9
v_xor_b32_e32 v3, v3, v4
s_xor_b32 s11, s11, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v8, s11
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v4
s_sub_i32 s16, 0, s11
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v5, v6
v_add_nc_u32_e32 v7, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v7, v4
v_rcp_iflag_f32_e32 v7, v8
v_rcp_iflag_f32_e32 v8, v9
v_xor_b32_e32 v4, s12, v4
v_mul_hi_u32 v5, v6, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v7, 0x4f7ffffe, v7 :: v_dual_mul_f32 v8, 0x4f7ffffe, v8
v_mul_lo_u32 v9, v5, s13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v7, v7
v_cvt_u32_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v6, v6, v9
v_add_nc_u32_e32 v9, 1, v5
v_readfirstlane_b32 s17, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_readfirstlane_b32 s18, v8
v_subrev_nc_u32_e32 v7, s13, v6
v_cmp_le_u32_e32 vcc_lo, s13, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
s_mul_i32 s16, s16, s17
s_mul_i32 s19, s19, s18
s_mul_hi_u32 s16, s17, s16
s_mul_hi_u32 s19, s18, s19
v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v6, v6, v7
s_add_i32 s18, s18, s19
s_add_i32 s17, s17, s16
s_mul_hi_u32 s12, s13, s18
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, 1, v5
v_cmp_le_u32_e32 vcc_lo, s13, v6
v_mul_lo_u32 v6, v3, s3
s_mul_i32 s20, s12, s10
s_add_i32 s21, s12, 1
s_sub_i32 s13, s13, s20
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
s_sub_i32 s20, s13, s10
s_cmp_ge_u32 s13, s10
s_mul_hi_u32 s16, s8, s17
s_cselect_b32 s12, s21, s12
v_xor_b32_e32 v5, v5, v4
s_mul_i32 s22, s16, s11
s_mul_hi_u32 s19, s5, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v4
v_mul_lo_u32 v4, v5, s2
s_cselect_b32 s2, s20, s13
s_add_i32 s13, s12, 1
s_cmp_ge_u32 s2, s10
s_mul_i32 s2, s19, s11
s_cselect_b32 s12, s13, s12
s_sub_i32 s3, s8, s22
s_xor_b32 s8, s12, s15
v_sub_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v4, v2, s6
v_sub_nc_u32_e32 v2, v2, v6
s_xor_b32 s7, s7, s9
s_add_i32 s6, s16, 1
v_ashrrev_i32_e32 v7, 31, v3
s_sub_i32 s12, s3, s11
v_ashrrev_i32_e32 v6, 31, v2
s_sub_i32 s8, s8, s15
v_sub_nc_u32_e32 v4, v0, v4
v_add_nc_u32_e32 v3, v3, v7
s_cmp_ge_u32 s3, s11
v_add_nc_u32_e32 v2, v2, v6
s_cselect_b32 s6, s6, s16
v_ashrrev_i32_e32 v8, 31, v4
v_xor_b32_e32 v3, v3, v7
s_cselect_b32 s3, s12, s3
v_xor_b32_e32 v2, v2, v6
s_add_i32 s12, s6, 1
v_add_nc_u32_e32 v4, v4, v8
v_mul_hi_u32 v9, v3, s18
s_cmp_ge_u32 s3, s11
v_mul_hi_u32 v10, v2, s17
s_cselect_b32 s3, s12, s6
v_xor_b32_e32 v4, v4, v8
s_sub_i32 s5, s5, s2
s_xor_b32 s3, s3, s7
s_xor_b32 s4, s4, s9
v_add_nc_u32_e32 v14, 1, v9
v_mul_lo_u32 v11, v9, s10
v_mul_hi_u32 v12, v4, s17
v_mul_lo_u32 v13, v10, s11
s_add_i32 s2, s19, 1
s_sub_i32 s6, s5, s11
s_sub_i32 s3, s3, s7
s_cmp_ge_u32 s5, s11
v_xor_b32_e32 v7, s14, v7
v_sub_nc_u32_e32 v3, v3, v11
v_mul_lo_u32 v11, v12, s11
v_sub_nc_u32_e32 v2, v2, v13
v_add_nc_u32_e32 v13, 1, v10
s_cselect_b32 s7, s2, s19
v_subrev_nc_u32_e32 v16, s10, v3
v_cmp_le_u32_e32 vcc_lo, s10, v3
v_add_nc_u32_e32 v15, 1, v12
v_xor_b32_e32 v6, s9, v6
v_sub_nc_u32_e32 v4, v4, v11
v_xor_b32_e32 v8, s9, v8
v_cndmask_b32_e32 v9, v9, v14, vcc_lo
v_cndmask_b32_e32 v3, v3, v16, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v11, 1, v9
v_cmp_le_u32_e64 s2, s10, v3
v_cndmask_b32_e32 v10, v10, v13, vcc_lo
v_subrev_nc_u32_e32 v13, s11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v9, v11, s2
v_cmp_le_u32_e64 s2, s11, v4
v_dual_cndmask_b32 v2, v2, v13 :: v_dual_add_nc_u32 v11, 1, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v3, v7
v_cndmask_b32_e64 v9, v12, v15, s2
v_subrev_nc_u32_e32 v12, s11, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s11, v2
v_sub_nc_u32_e32 v2, v3, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v4, v12, s2
v_dual_cndmask_b32 v10, v10, v11 :: v_dual_add_nc_u32 v11, 1, v9
v_mad_u64_u32 v[3:4], null, s8, v5, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s11, v7
v_xor_b32_e32 v10, v10, v6
s_cselect_b32 s2, s6, s5
s_add_i32 s5, s7, 1
s_cmp_ge_u32 s2, s11
v_cndmask_b32_e32 v4, v9, v11, vcc_lo
v_sub_nc_u32_e32 v2, v10, v6
s_cselect_b32 s2, s5, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_xor_b32 s5, s2, s4
v_xor_b32_e32 v6, v4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v3, s3, v[2:3]
s_sub_i32 s4, s5, s4
s_load_b128 s[0:3], s[0:1], 0x0
v_sub_nc_u32_e32 v2, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v4, s4, v[2:3]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7upscalePfS_liiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7upscalePfS_liiiiii, .Lfunc_end0-_Z7upscalePfS_liiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7upscalePfS_liiiiii
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z7upscalePfS_liiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void upscale(float *input, float *output, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
int ipidx = translate_idx(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy);
output[ii]=input[ipidx];
} | .text
.file "upscale.hip"
.globl _Z22__device_stub__upscalePfS_liiiiii # -- Begin function _Z22__device_stub__upscalePfS_liiiiii
.p2align 4, 0x90
.type _Z22__device_stub__upscalePfS_liiiiii,@function
_Z22__device_stub__upscalePfS_liiiiii: # @_Z22__device_stub__upscalePfS_liiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7upscalePfS_liiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z22__device_stub__upscalePfS_liiiiii, .Lfunc_end0-_Z22__device_stub__upscalePfS_liiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7upscalePfS_liiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7upscalePfS_liiiiii,@object # @_Z7upscalePfS_liiiiii
.section .rodata,"a",@progbits
.globl _Z7upscalePfS_liiiiii
.p2align 3, 0x0
_Z7upscalePfS_liiiiii:
.quad _Z22__device_stub__upscalePfS_liiiiii
.size _Z7upscalePfS_liiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7upscalePfS_liiiiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__upscalePfS_liiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7upscalePfS_liiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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