system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a8ca4_00000000-6_init_cs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7init_csPiS_iiPiS_ii
.type _Z30__device_stub__Z7init_csPiS_iiPiS_ii, @function
_Z30__device_stub__Z7init_csPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7init_csPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7init_csPiS_iiPiS_ii, .-_Z30__device_stub__Z7init_csPiS_iiPiS_ii
.globl _Z7init_csPiS_ii
.type _Z7init_csPiS_ii, @function
_Z7init_csPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7init_csPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7init_csPiS_ii, .-_Z7init_csPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7init_csPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7init_csPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "init_cs.hip"
.globl _Z22__device_stub__init_csPiS_ii # -- Begin function _Z22__device_stub__init_csPiS_ii
.p2align 4, 0x90
.type _Z22__device_stub__init_csPiS_ii,@function
_Z22__device_stub__init_csPiS_ii: # @_Z22__device_stub__init_csPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7init_csPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__init_csPiS_ii, .Lfunc_end0-_Z22__device_stub__init_csPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7init_csPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7init_csPiS_ii,@object # @_Z7init_csPiS_ii
.section .rodata,"a",@progbits
.globl _Z7init_csPiS_ii
.p2align 3, 0x0
_Z7init_csPiS_ii:
.quad _Z22__device_stub__init_csPiS_ii
.size _Z7init_csPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7init_csPiS_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__init_csPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7init_csPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
} | code for sm_80
Function : _Z18vecMultiplyReversePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe200078e0207 */
/*0080*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000eaa000c1e1900 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ LOP3.LUT R0, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106007812 */
/* 0x040fe200078ec0ff */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc600078e0207 */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00d0*/ @!P0 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09098210 */
/* 0x004fc80007ffe1ff */
/*00e0*/ IADD3 R9, R2, R9, RZ ; /* 0x0000000902097210 */
/* 0x008fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
} | .file "tmpxft_000f1af0_00000000-6_vecMultiplyReverse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
.type _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_, @function
_Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18vecMultiplyReversePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_, .-_Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
.globl _Z18vecMultiplyReversePiS_S_
.type _Z18vecMultiplyReversePiS_S_, @function
_Z18vecMultiplyReversePiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18vecMultiplyReversePiS_S_, .-_Z18vecMultiplyReversePiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18vecMultiplyReversePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vecMultiplyReversePiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18vecMultiplyReversePiS_S_
.globl _Z18vecMultiplyReversePiS_S_
.p2align 8
.type _Z18vecMultiplyReversePiS_S_,@function
_Z18vecMultiplyReversePiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v5, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v4, v5
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vecMultiplyReversePiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18vecMultiplyReversePiS_S_, .Lfunc_end0-_Z18vecMultiplyReversePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vecMultiplyReversePiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vecMultiplyReversePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
} | .text
.file "vecMultiplyReverse.hip"
.globl _Z33__device_stub__vecMultiplyReversePiS_S_ # -- Begin function _Z33__device_stub__vecMultiplyReversePiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__vecMultiplyReversePiS_S_,@function
_Z33__device_stub__vecMultiplyReversePiS_S_: # @_Z33__device_stub__vecMultiplyReversePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18vecMultiplyReversePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__vecMultiplyReversePiS_S_, .Lfunc_end0-_Z33__device_stub__vecMultiplyReversePiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vecMultiplyReversePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18vecMultiplyReversePiS_S_,@object # @_Z18vecMultiplyReversePiS_S_
.section .rodata,"a",@progbits
.globl _Z18vecMultiplyReversePiS_S_
.p2align 3, 0x0
_Z18vecMultiplyReversePiS_S_:
.quad _Z33__device_stub__vecMultiplyReversePiS_S_
.size _Z18vecMultiplyReversePiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18vecMultiplyReversePiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__vecMultiplyReversePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18vecMultiplyReversePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18vecMultiplyReversePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe200078e0207 */
/*0080*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000eaa000c1e1900 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ LOP3.LUT R0, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106007812 */
/* 0x040fe200078ec0ff */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc600078e0207 */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00d0*/ @!P0 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09098210 */
/* 0x004fc80007ffe1ff */
/*00e0*/ IADD3 R9, R2, R9, RZ ; /* 0x0000000902097210 */
/* 0x008fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18vecMultiplyReversePiS_S_
.globl _Z18vecMultiplyReversePiS_S_
.p2align 8
.type _Z18vecMultiplyReversePiS_S_,@function
_Z18vecMultiplyReversePiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v5, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v4, v5
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vecMultiplyReversePiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18vecMultiplyReversePiS_S_, .Lfunc_end0-_Z18vecMultiplyReversePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vecMultiplyReversePiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vecMultiplyReversePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f1af0_00000000-6_vecMultiplyReverse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
.type _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_, @function
_Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18vecMultiplyReversePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_, .-_Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
.globl _Z18vecMultiplyReversePiS_S_
.type _Z18vecMultiplyReversePiS_S_, @function
_Z18vecMultiplyReversePiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18vecMultiplyReversePiS_S_, .-_Z18vecMultiplyReversePiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18vecMultiplyReversePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vecMultiplyReversePiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecMultiplyReverse.hip"
.globl _Z33__device_stub__vecMultiplyReversePiS_S_ # -- Begin function _Z33__device_stub__vecMultiplyReversePiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__vecMultiplyReversePiS_S_,@function
_Z33__device_stub__vecMultiplyReversePiS_S_: # @_Z33__device_stub__vecMultiplyReversePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18vecMultiplyReversePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__vecMultiplyReversePiS_S_, .Lfunc_end0-_Z33__device_stub__vecMultiplyReversePiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vecMultiplyReversePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18vecMultiplyReversePiS_S_,@object # @_Z18vecMultiplyReversePiS_S_
.section .rodata,"a",@progbits
.globl _Z18vecMultiplyReversePiS_S_
.p2align 3, 0x0
_Z18vecMultiplyReversePiS_S_:
.quad _Z33__device_stub__vecMultiplyReversePiS_S_
.size _Z18vecMultiplyReversePiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18vecMultiplyReversePiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__vecMultiplyReversePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18vecMultiplyReversePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void DTW_Diag_Step(float* d0, float* d1, float* d2, float* csm0, float* csm1, float* csm2, float* X, float* Y, int dim, int diagLen, int* box, int reverse, int i, int debug, float* U, float* L, float* UL, float* S) {
//Other local variables
int i1, i2, j1, j2; // Endpoints of the diagonal
int thisi, thisj; // Current indices on the diagonal
// Optimal score and particular score for up/right/left
float score, left, up, diag;
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int xi, yj;
//Process each diagonal
score = -1;
if (idx < diagLen) {
// Figure out indices in X and Y on diagonal
int M = box[1] - box[0] + 1;
int N = box[3] - box[2] + 1;
i1 = i;
j1 = 0;
if (i >= M) {
i1 = M-1;
j1 = i - (M-1);
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi >= i2 && thisj <= j2) {
xi = thisi;
yj = thisj;
if (reverse == 1) {
xi = M-1-xi;
yj = N-1-yj;
}
xi += box[0];
yj += box[2];
// Step 1: Update csm2
csm2[idx] = 0.0;
for (int d = 0; d < dim; d++) {
float diff = X[xi*dim+d] - Y[yj*dim+d];
csm2[idx] += diff*diff;
}
csm2[idx] = sqrt(csm2[idx]);
// Step 2: Figure out the optimal cost
if (thisi == 0 && thisj == 0) {
score = 0;
if (debug == -1) {
S[0] = 0;
U[0] = -1;
L[0] = -1;
UL[0] = -1;
}
}
else {
left = -1;
up = -1;
diag = -1;
if (j1 == 0) {
if (idx > 0) {
left = d1[idx-1] + csm1[idx-1];
}
if (idx > 0 && thisi > 0) {
diag = d0[idx-1] + csm0[idx-1];
}
if (thisi > 0) {
up = d1[idx] + csm1[idx];
}
}
else if (i1 == M-1 && j1 == 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx] + csm0[idx];
up = d1[idx+1] + csm1[idx+1];
}
}
else if (i1 == M-1 && j1 > 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx+1] + csm0[idx+1];
up = d1[idx+1] + csm1[idx+1];
}
}
if (left > -1) {
score = left;
}
if (up > -1 && (up < score || score == -1)) {
score = up;
}
if (diag > -1 && (diag < score || score == -1)) {
score = diag;
}
if (debug == 1) {
U[thisi*N + thisj] = up;
L[thisi*N + thisj] = left;
UL[thisi*N + thisj] = diag;
S[thisi*N + thisj] = score;
}
}
}
d2[idx] = score;
}
} | .file "tmpxft_00109636_00000000-6_DTWGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.type _Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, @function
_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $344, %rsp
.cfi_def_cfa_offset 352
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 352(%rsp), %rax
movq %rax, 56(%rsp)
movq 360(%rsp), %rax
movq %rax, 48(%rsp)
movq 384(%rsp), %rax
movq %rax, 40(%rsp)
movq 416(%rsp), %rax
movq %rax, 32(%rsp)
movq 424(%rsp), %rax
movq %rax, 24(%rsp)
movq 432(%rsp), %rax
movq %rax, 16(%rsp)
movq 440(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 40(%rsp), %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
leaq 32(%rsp), %rax
movq %rax, 288(%rsp)
leaq 24(%rsp), %rax
movq %rax, 296(%rsp)
leaq 16(%rsp), %rax
movq %rax, 304(%rsp)
leaq 8(%rsp), %rax
movq %rax, 312(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 360
pushq 120(%rsp)
.cfi_def_cfa_offset 368
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 352
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .-_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.globl _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.type _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, @function
_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 104(%rsp)
.cfi_def_cfa_offset 24
pushq 104(%rsp)
.cfi_def_cfa_offset 32
pushq 104(%rsp)
.cfi_def_cfa_offset 40
pushq 104(%rsp)
.cfi_def_cfa_offset 48
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .-_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void DTW_Diag_Step(float* d0, float* d1, float* d2, float* csm0, float* csm1, float* csm2, float* X, float* Y, int dim, int diagLen, int* box, int reverse, int i, int debug, float* U, float* L, float* UL, float* S) {
//Other local variables
int i1, i2, j1, j2; // Endpoints of the diagonal
int thisi, thisj; // Current indices on the diagonal
// Optimal score and particular score for up/right/left
float score, left, up, diag;
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int xi, yj;
//Process each diagonal
score = -1;
if (idx < diagLen) {
// Figure out indices in X and Y on diagonal
int M = box[1] - box[0] + 1;
int N = box[3] - box[2] + 1;
i1 = i;
j1 = 0;
if (i >= M) {
i1 = M-1;
j1 = i - (M-1);
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi >= i2 && thisj <= j2) {
xi = thisi;
yj = thisj;
if (reverse == 1) {
xi = M-1-xi;
yj = N-1-yj;
}
xi += box[0];
yj += box[2];
// Step 1: Update csm2
csm2[idx] = 0.0;
for (int d = 0; d < dim; d++) {
float diff = X[xi*dim+d] - Y[yj*dim+d];
csm2[idx] += diff*diff;
}
csm2[idx] = sqrt(csm2[idx]);
// Step 2: Figure out the optimal cost
if (thisi == 0 && thisj == 0) {
score = 0;
if (debug == -1) {
S[0] = 0;
U[0] = -1;
L[0] = -1;
UL[0] = -1;
}
}
else {
left = -1;
up = -1;
diag = -1;
if (j1 == 0) {
if (idx > 0) {
left = d1[idx-1] + csm1[idx-1];
}
if (idx > 0 && thisi > 0) {
diag = d0[idx-1] + csm0[idx-1];
}
if (thisi > 0) {
up = d1[idx] + csm1[idx];
}
}
else if (i1 == M-1 && j1 == 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx] + csm0[idx];
up = d1[idx+1] + csm1[idx+1];
}
}
else if (i1 == M-1 && j1 > 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx+1] + csm0[idx+1];
up = d1[idx+1] + csm1[idx+1];
}
}
if (left > -1) {
score = left;
}
if (up > -1 && (up < score || score == -1)) {
score = up;
}
if (diag > -1 && (diag < score || score == -1)) {
score = diag;
}
if (debug == 1) {
U[thisi*N + thisj] = up;
L[thisi*N + thisj] = left;
UL[thisi*N + thisj] = diag;
S[thisi*N + thisj] = score;
}
}
}
d2[idx] = score;
}
} | #include <hip/hip_runtime.h>
__global__ void DTW_Diag_Step(float* d0, float* d1, float* d2, float* csm0, float* csm1, float* csm2, float* X, float* Y, int dim, int diagLen, int* box, int reverse, int i, int debug, float* U, float* L, float* UL, float* S) {
//Other local variables
int i1, i2, j1, j2; // Endpoints of the diagonal
int thisi, thisj; // Current indices on the diagonal
// Optimal score and particular score for up/right/left
float score, left, up, diag;
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int xi, yj;
//Process each diagonal
score = -1;
if (idx < diagLen) {
// Figure out indices in X and Y on diagonal
int M = box[1] - box[0] + 1;
int N = box[3] - box[2] + 1;
i1 = i;
j1 = 0;
if (i >= M) {
i1 = M-1;
j1 = i - (M-1);
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi >= i2 && thisj <= j2) {
xi = thisi;
yj = thisj;
if (reverse == 1) {
xi = M-1-xi;
yj = N-1-yj;
}
xi += box[0];
yj += box[2];
// Step 1: Update csm2
csm2[idx] = 0.0;
for (int d = 0; d < dim; d++) {
float diff = X[xi*dim+d] - Y[yj*dim+d];
csm2[idx] += diff*diff;
}
csm2[idx] = sqrt(csm2[idx]);
// Step 2: Figure out the optimal cost
if (thisi == 0 && thisj == 0) {
score = 0;
if (debug == -1) {
S[0] = 0;
U[0] = -1;
L[0] = -1;
UL[0] = -1;
}
}
else {
left = -1;
up = -1;
diag = -1;
if (j1 == 0) {
if (idx > 0) {
left = d1[idx-1] + csm1[idx-1];
}
if (idx > 0 && thisi > 0) {
diag = d0[idx-1] + csm0[idx-1];
}
if (thisi > 0) {
up = d1[idx] + csm1[idx];
}
}
else if (i1 == M-1 && j1 == 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx] + csm0[idx];
up = d1[idx+1] + csm1[idx+1];
}
}
else if (i1 == M-1 && j1 > 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx+1] + csm0[idx+1];
up = d1[idx+1] + csm1[idx+1];
}
}
if (left > -1) {
score = left;
}
if (up > -1 && (up < score || score == -1)) {
score = up;
}
if (diag > -1 && (diag < score || score == -1)) {
score = diag;
}
if (debug == 1) {
U[thisi*N + thisj] = up;
L[thisi*N + thisj] = left;
UL[thisi*N + thisj] = diag;
S[thisi*N + thisj] = score;
}
}
}
d2[idx] = score;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void DTW_Diag_Step(float* d0, float* d1, float* d2, float* csm0, float* csm1, float* csm2, float* X, float* Y, int dim, int diagLen, int* box, int reverse, int i, int debug, float* U, float* L, float* UL, float* S) {
//Other local variables
int i1, i2, j1, j2; // Endpoints of the diagonal
int thisi, thisj; // Current indices on the diagonal
// Optimal score and particular score for up/right/left
float score, left, up, diag;
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int xi, yj;
//Process each diagonal
score = -1;
if (idx < diagLen) {
// Figure out indices in X and Y on diagonal
int M = box[1] - box[0] + 1;
int N = box[3] - box[2] + 1;
i1 = i;
j1 = 0;
if (i >= M) {
i1 = M-1;
j1 = i - (M-1);
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi >= i2 && thisj <= j2) {
xi = thisi;
yj = thisj;
if (reverse == 1) {
xi = M-1-xi;
yj = N-1-yj;
}
xi += box[0];
yj += box[2];
// Step 1: Update csm2
csm2[idx] = 0.0;
for (int d = 0; d < dim; d++) {
float diff = X[xi*dim+d] - Y[yj*dim+d];
csm2[idx] += diff*diff;
}
csm2[idx] = sqrt(csm2[idx]);
// Step 2: Figure out the optimal cost
if (thisi == 0 && thisj == 0) {
score = 0;
if (debug == -1) {
S[0] = 0;
U[0] = -1;
L[0] = -1;
UL[0] = -1;
}
}
else {
left = -1;
up = -1;
diag = -1;
if (j1 == 0) {
if (idx > 0) {
left = d1[idx-1] + csm1[idx-1];
}
if (idx > 0 && thisi > 0) {
diag = d0[idx-1] + csm0[idx-1];
}
if (thisi > 0) {
up = d1[idx] + csm1[idx];
}
}
else if (i1 == M-1 && j1 == 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx] + csm0[idx];
up = d1[idx+1] + csm1[idx+1];
}
}
else if (i1 == M-1 && j1 > 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx+1] + csm0[idx+1];
up = d1[idx+1] + csm1[idx+1];
}
}
if (left > -1) {
score = left;
}
if (up > -1 && (up < score || score == -1)) {
score = up;
}
if (diag > -1 && (diag < score || score == -1)) {
score = diag;
}
if (debug == 1) {
U[thisi*N + thisj] = up;
L[thisi*N + thisj] = left;
UL[thisi*N + thisj] = diag;
S[thisi*N + thisj] = score;
}
}
}
d2[idx] = score;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.globl _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.p2align 8
.type _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_,@function
_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8c
s_load_b32 s3, s[0:1], 0x44
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_36
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x48
s_load_b32 s24, s[0:1], 0x54
v_mov_b32_e32 v3, -1.0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_load_b128 s[4:7], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s26, s5, s4
s_sub_i32 s21, s7, s6
s_sub_i32 s2, s24, s26
s_cmp_gt_i32 s24, s26
s_cselect_b32 s25, s2, 0
s_min_i32 s3, s26, s24
s_sub_i32 s2, s24, s21
s_min_i32 s5, s21, s24
v_sub_nc_u32_e32 v0, s3, v1
v_add_nc_u32_e32 v9, s25, v1
s_cmp_gt_i32 s24, s21
s_cselect_b32 s2, s2, 0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, s5, v9
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s20, s2
s_cbranch_execz .LBB0_35
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x28
s_load_b32 s2, s[0:1], 0x40
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_cmp_lt_i32 s2, 1
global_store_b32 v[3:4], v5, off
s_cbranch_scc1 .LBB0_5
global_load_b32 v10, v[3:4], off
s_clause 0x1
s_load_b32 s5, s[0:1], 0x50
s_load_b128 s[8:11], s[0:1], 0x30
v_sub_nc_u32_e32 v5, s21, v9
v_sub_nc_u32_e32 v6, s26, v0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s5, 1
s_cselect_b32 vcc_lo, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v9, v5 :: v_dual_cndmask_b32 v6, v0, v6
v_add_nc_u32_e32 v5, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, s4, v6
v_mul_lo_u32 v5, v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v6, s2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v5, vcc_lo, s10, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
.p2align 6
.LBB0_4:
global_load_b32 v11, v[7:8], off
global_load_b32 v12, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v11, v11, v12
v_fmac_f32_e32 v10, v11, v11
global_store_b32 v[3:4], v10, off
s_cbranch_scc0 .LBB0_4
.LBB0_5:
global_load_b32 v5, v[3:4], off
s_clause 0x1
s_load_b32 s22, s[0:1], 0x58
s_load_b256 s[4:11], s[0:1], 0x60
s_mov_b32 s27, -1
s_waitcnt vmcnt(0)
v_mul_f32_e32 v6, 0x4f800000, v5
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_sqrt_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v6
v_add_nc_u32_e32 v8, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v7, v6, v5
v_fma_f32 v11, -v8, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v10
v_cndmask_b32_e64 v6, v6, v7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v11
v_cndmask_b32_e64 v6, v6, v8, s2
v_cmp_ne_u32_e64 s2, 0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, s3, v1
v_cmp_class_f32_e64 s3, v5, 0x260
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v5, v6, v5, s3
s_mov_b32 s3, 0
global_store_b32 v[3:4], v5, off
s_and_saveexec_b32 s12, s2
s_xor_b32 s23, exec_lo, s12
s_cbranch_execz .LBB0_30
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b128 s[12:15], s[0:1], 0x18
s_cmp_lg_u32 s25, 0
s_mov_b32 s2, 0
s_cbranch_scc0 .LBB0_12
s_cmp_ge_i32 s24, s26
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s25, 1
s_cselect_b32 s24, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s24, s3, s24
s_and_not1_b32 vcc_lo, exec_lo, s24
s_cbranch_vccz .LBB0_13
s_cmp_gt_i32 s25, 1
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_mov_b32 s3, 0
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB0_14
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s2, 0
s_mov_b32 s24, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s18, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s19, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s14, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v5, v3
v_cmpx_lt_i32_e32 0, v0
s_xor_b32 s24, exec_lo, s24
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v3, 1, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v11, vcc_lo, s17, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s12, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
global_load_b32 v8, v[10:11], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v8, v5
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s24
s_branch .LBB0_15
.LBB0_12:
s_branch .LBB0_20
.LBB0_13:
s_cbranch_execnz .LBB0_16
s_branch .LBB0_19
.LBB0_14:
v_mov_b32_e32 v7, -1.0
s_mov_b32 s2, 0
.LBB0_15:
s_mov_b32 s24, -1.0
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_19
.LBB0_16:
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s18, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s19, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s14, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v6, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v3, v4
v_cmpx_lt_i32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_18
v_add_co_u32 v3, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s17, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s12, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
s_or_b32 s2, s2, exec_lo
global_load_b32 v4, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_nc_u32_e32 v3, 1, v1
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v4, v5
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s24, -1.0
.LBB0_19:
s_mov_b32 s27, 0
s_mov_b32 s3, s2
.LBB0_20:
v_mov_b32_e32 v5, s24
s_and_b32 vcc_lo, exec_lo, s27
s_cbranch_vccz .LBB0_26
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_dual_mov_b32 v8, -1.0 :: v_dual_mov_b32 v7, -1.0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_23
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s2, s18, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s19, v4, s2
v_add_co_u32 v3, s2, s14, v3
v_add_co_ci_u32_e64 v4, s2, s15, v4, s2
global_load_b32 v5, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v5, v3
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_lt_i32_e64 s3, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s24, vcc_lo, s3
s_and_saveexec_b32 s2, s24
s_cbranch_execz .LBB0_25
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s16, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s17, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s12, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v5, v3
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s2
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v5, v8
s_mov_b32 s24, -1.0
.LBB0_26:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v6, s24
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_28
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s18, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s19, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s14, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v6, v5, v3 :: v_dual_mov_b32 v5, v8
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s2
v_max_f32_e32 v3, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s3, -1.0, v6
v_max_f32_e32 v3, -1.0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v6, v3
v_cmp_eq_f32_e64 s2, -1.0, v3
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_and_b32 vcc_lo, s3, s2
v_cmp_lt_f32_e64 s3, -1.0, v5
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, v5, v3
v_cmp_eq_f32_e64 s2, -1.0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 vcc_lo, s3, s2
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s22, 1
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_cbranch_scc1 .LBB0_30
v_mul_lo_u32 v4, v0, s21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v8, v4, v0, v9
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v10, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v14, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
global_store_b32 v[10:11], v6, off
global_store_b32 v[12:13], v7, off
global_store_b32 v[14:15], v5, off
global_store_b32 v[8:9], v3, off
.LBB0_30:
s_and_not1_saveexec_b32 s2, s23
s_cbranch_execz .LBB0_34
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s22, -1
s_cbranch_scc1 .LBB0_33
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, -1.0
s_clause 0x3
global_store_b32 v0, v0, s[10:11]
global_store_b32 v0, v3, s[4:5]
global_store_b32 v0, v3, s[6:7]
global_store_b32 v0, v3, s[8:9]
.LBB0_33:
v_mov_b32_e32 v3, 0
.LBB0_34:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_35:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s20
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_36:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 384
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .Lfunc_end0-_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 120
.size: 8
.value_kind: global_buffer
- .offset: 128
.size: 4
.value_kind: hidden_block_count_x
- .offset: 132
.size: 4
.value_kind: hidden_block_count_y
- .offset: 136
.size: 4
.value_kind: hidden_block_count_z
- .offset: 140
.size: 2
.value_kind: hidden_group_size_x
- .offset: 142
.size: 2
.value_kind: hidden_group_size_y
- .offset: 144
.size: 2
.value_kind: hidden_group_size_z
- .offset: 146
.size: 2
.value_kind: hidden_remainder_x
- .offset: 148
.size: 2
.value_kind: hidden_remainder_y
- .offset: 150
.size: 2
.value_kind: hidden_remainder_z
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 176
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 184
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 192
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 384
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void DTW_Diag_Step(float* d0, float* d1, float* d2, float* csm0, float* csm1, float* csm2, float* X, float* Y, int dim, int diagLen, int* box, int reverse, int i, int debug, float* U, float* L, float* UL, float* S) {
//Other local variables
int i1, i2, j1, j2; // Endpoints of the diagonal
int thisi, thisj; // Current indices on the diagonal
// Optimal score and particular score for up/right/left
float score, left, up, diag;
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int xi, yj;
//Process each diagonal
score = -1;
if (idx < diagLen) {
// Figure out indices in X and Y on diagonal
int M = box[1] - box[0] + 1;
int N = box[3] - box[2] + 1;
i1 = i;
j1 = 0;
if (i >= M) {
i1 = M-1;
j1 = i - (M-1);
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi >= i2 && thisj <= j2) {
xi = thisi;
yj = thisj;
if (reverse == 1) {
xi = M-1-xi;
yj = N-1-yj;
}
xi += box[0];
yj += box[2];
// Step 1: Update csm2
csm2[idx] = 0.0;
for (int d = 0; d < dim; d++) {
float diff = X[xi*dim+d] - Y[yj*dim+d];
csm2[idx] += diff*diff;
}
csm2[idx] = sqrt(csm2[idx]);
// Step 2: Figure out the optimal cost
if (thisi == 0 && thisj == 0) {
score = 0;
if (debug == -1) {
S[0] = 0;
U[0] = -1;
L[0] = -1;
UL[0] = -1;
}
}
else {
left = -1;
up = -1;
diag = -1;
if (j1 == 0) {
if (idx > 0) {
left = d1[idx-1] + csm1[idx-1];
}
if (idx > 0 && thisi > 0) {
diag = d0[idx-1] + csm0[idx-1];
}
if (thisi > 0) {
up = d1[idx] + csm1[idx];
}
}
else if (i1 == M-1 && j1 == 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx] + csm0[idx];
up = d1[idx+1] + csm1[idx+1];
}
}
else if (i1 == M-1 && j1 > 1) {
left = d1[idx] + csm1[idx];
if (thisi > 0) {
diag = d0[idx+1] + csm0[idx+1];
up = d1[idx+1] + csm1[idx+1];
}
}
if (left > -1) {
score = left;
}
if (up > -1 && (up < score || score == -1)) {
score = up;
}
if (diag > -1 && (diag < score || score == -1)) {
score = diag;
}
if (debug == 1) {
U[thisi*N + thisj] = up;
L[thisi*N + thisj] = left;
UL[thisi*N + thisj] = diag;
S[thisi*N + thisj] = score;
}
}
}
d2[idx] = score;
}
} | .text
.file "DTWGPU.hip"
.globl _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_ # -- Begin function _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.p2align 4, 0x90
.type _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_,@function
_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_: # @_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .Lfunc_end0-_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_,@object # @_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.p2align 3, 0x0
_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
.quad _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.size _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00109636_00000000-6_DTWGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.type _Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, @function
_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $344, %rsp
.cfi_def_cfa_offset 352
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 352(%rsp), %rax
movq %rax, 56(%rsp)
movq 360(%rsp), %rax
movq %rax, 48(%rsp)
movq 384(%rsp), %rax
movq %rax, 40(%rsp)
movq 416(%rsp), %rax
movq %rax, 32(%rsp)
movq 424(%rsp), %rax
movq %rax, 24(%rsp)
movq 432(%rsp), %rax
movq %rax, 16(%rsp)
movq 440(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 40(%rsp), %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
leaq 32(%rsp), %rax
movq %rax, 288(%rsp)
leaq 24(%rsp), %rax
movq %rax, 296(%rsp)
leaq 16(%rsp), %rax
movq %rax, 304(%rsp)
leaq 8(%rsp), %rax
movq %rax, 312(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 360
pushq 120(%rsp)
.cfi_def_cfa_offset 368
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 352
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .-_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.globl _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.type _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, @function
_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 104(%rsp)
.cfi_def_cfa_offset 24
pushq 104(%rsp)
.cfi_def_cfa_offset 32
pushq 104(%rsp)
.cfi_def_cfa_offset 40
pushq 104(%rsp)
.cfi_def_cfa_offset 48
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .-_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DTWGPU.hip"
.globl _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_ # -- Begin function _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.p2align 4, 0x90
.type _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_,@function
_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_: # @_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .Lfunc_end0-_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_,@object # @_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.p2align 3, 0x0
_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
.quad _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.size _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Babak Poursartip
// 09/14/2020
// Udemy Cuda
// unique index calculation
#include <cstdio>
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_3d_3d(int *input) {
int threadsPerBlock = blockDim.x * blockDim.y * blockDim.z;
int threadPositionInBlock = threadIdx.x +
blockDim.x * threadIdx.y +
blockDim.x * blockDim.y * threadIdx.z;
int blockPositionInGrid = blockIdx.x +
gridDim.x * blockIdx.y +
gridDim.x * gridDim.y * blockIdx.z;
int tid = blockPositionInGrid * threadsPerBlock + threadPositionInBlock;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, tid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
tid);
}
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_2d_2d(int *input) {
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, gid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
gid);
}
// ===========================================
int main() {
printf(" starts ...");
int nCol = 6;
int nRow = 8;
int array_size = nCol*nRow;
int array_byte_size = sizeof(int) * array_size;
int h_data[array_size];
for (int i = 0; i< array_size; ++i)
{
h_data[i] = i;
}
printf(" data on the host: \n");
for (int i = 0; i < array_size; ++i)
{
printf(" %d", h_data[i]);
if((i%8)==0) printf("\n");
}
printf("\n\n");
int *d_data; // array on the device
cudaMalloc((void **)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 grid(nCol, 1, 1);
dim3 block(nRow, 1, 1);
printf(" data on the device: \n");
//unique_gid_calculation_2d_2d<<<grid, block>>>(d_data);
unique_gid_calculation_3d_3d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
printf(" finished.");
return 0;
} | code for sm_80
Function : _Z28unique_gid_calculation_2d_2dPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x38, RZ ; /* 0xffffffc801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0060*/ MOV R14, c[0x0][0x14] ; /* 0x00000500000e7a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff107624 */
/* 0x000fe200078e00ff */
/*0080*/ MOV R17, c[0x0][0x8] ; /* 0x0000020000117a02 */
/* 0x000fe20000000f00 */
/*0090*/ S2R R10, SR_TID.Y ; /* 0x00000000000a7919 */
/* 0x000e620000002200 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x10] ; /* 0x00000400ff057624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ea40000002100 */
/*00e0*/ IADD3.X R7, RZ, c[0x0][0x24], RZ, P0, !PT ; /* 0x00000900ff077a10 */
/* 0x000fc400007fe4ff */
/*00f0*/ S2R R12, SR_CTAID.Z ; /* 0x00000000000c7919 */
/* 0x000ee80000002700 */
/*0100*/ S2R R11, SR_TID.Z ; /* 0x00000000000b7919 */
/* 0x000f280000002300 */
/*0110*/ STL.64 [R1+0x8], R14 ; /* 0x0000080e01007387 */
/* 0x000fe20000100a00 */
/*0120*/ IMAD R3, R9, c[0x0][0xc], R8 ; /* 0x0000030009037a24 */
/* 0x001fc600078e0208 */
/*0130*/ STL.64 [R1+0x10], R16 ; /* 0x0000101001007387 */
/* 0x000fe20000100a00 */
/*0140*/ IMAD R0, R3, c[0x0][0x4], R10 ; /* 0x0000010003007a24 */
/* 0x002fc600078e020a */
/*0150*/ STL.64 [R1+0x18], R8 ; /* 0x0000180801007387 */
/* 0x000fe20000100a00 */
/*0160*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*0170*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x004fe400078e020d */
/*0180*/ STL.64 [R1], R4 ; /* 0x0000000401007387 */
/* 0x0003e80000100a00 */
/*0190*/ STL.64 [R1+0x20], R12 ; /* 0x0000200c01007387 */
/* 0x0085e80000100a00 */
/*01a0*/ STL.64 [R1+0x28], R10 ; /* 0x0000280a01007387 */
/* 0x0105e80000100a00 */
/*01b0*/ STL [R1+0x30], R0 ; /* 0x0000300001007387 */
/* 0x0005e20000100800 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x002fc400078e00ff */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*01e0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fca0000000000 */
/*01f0*/ MOV R11, 0x260 ; /* 0x00000260000b7802 */
/* 0x004fe40000000f00 */
/*0200*/ MOV R20, 0x1e0 ; /* 0x000001e000147802 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0230*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0240*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0250*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z28unique_gid_calculation_3d_3dPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.Y ; /* 0x00000000000b7919 */
/* 0x000e220000002600 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff0e7624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x38, RZ ; /* 0xffffffc801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R8, SR_CTAID.Z ; /* 0x0000000000087919 */
/* 0x000e220000002700 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R16, c[0x0][0x4] ; /* 0x0000010000107a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff117624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002500 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R5, c[0x0][0x10] ; /* 0x0000040000057a02 */
/* 0x000fc40000000f00 */
/*00c0*/ S2R R13, SR_TID.Z ; /* 0x00000000000d7919 */
/* 0x000ea20000002300 */
/*00d0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc60007f1e0ff */
/*00e0*/ S2R R12, SR_TID.Y ; /* 0x00000000000c7919 */
/* 0x000ee20000002200 */
/*00f0*/ IADD3.X R7, RZ, c[0x0][0x24], RZ, P0, !PT ; /* 0x00000900ff077a10 */
/* 0x000fc600007fe4ff */
/*0100*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000f280000002100 */
/*0110*/ STL.64 [R1+0x8], R14 ; /* 0x0000080e01007387 */
/* 0x000fe20000100a00 */
/*0120*/ IMAD R3, R8, c[0x0][0x10], R11 ; /* 0x0000040008037a24 */
/* 0x001fc600078e020b */
/*0130*/ STL.64 [R1+0x10], R16 ; /* 0x0000101001007387 */
/* 0x000fe20000100a00 */
/*0140*/ IMAD R0, R3, c[0x0][0xc], R10 ; /* 0x0000030003007a24 */
/* 0x002fc600078e020a */
/*0150*/ STL.64 [R1+0x18], R10 ; /* 0x0000180a01007387 */
/* 0x000fe20000100a00 */
/*0160*/ IMAD R3, R0, c[0x0][0x8], R13 ; /* 0x0000020000037a24 */
/* 0x004fc600078e020d */
/*0170*/ STL.64 [R1], R4 ; /* 0x0000000401007387 */
/* 0x0001e20000100a00 */
/*0180*/ IMAD R0, R3, c[0x0][0x4], R12 ; /* 0x0000010003007a24 */
/* 0x008fc600078e020c */
/*0190*/ STL.64 [R1+0x28], R12 ; /* 0x0000280c01007387 */
/* 0x0003e20000100a00 */
/*01a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000ea20000000a00 */
/*01b0*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x010fe400078e0209 */
/*01c0*/ STL.64 [R1+0x20], R8 ; /* 0x0000200801007387 */
/* 0x0003e80000100a00 */
/*01d0*/ STL [R1+0x30], R0 ; /* 0x0000300001007387 */
/* 0x0003e20000100800 */
/*01e0*/ MOV R4, c[0x4][0x8] ; /* 0x0100020000047a02 */
/* 0x001fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc400078e00ff */
/*0200*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fca0000000000 */
/*0210*/ MOV R11, 0x280 ; /* 0x00000280000b7802 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R20, 0x200 ; /* 0x0000020000147802 */
/* 0x000fc40000000f00 */
/*0230*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0250*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0260*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0270*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Babak Poursartip
// 09/14/2020
// Udemy Cuda
// unique index calculation
#include <cstdio>
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_3d_3d(int *input) {
int threadsPerBlock = blockDim.x * blockDim.y * blockDim.z;
int threadPositionInBlock = threadIdx.x +
blockDim.x * threadIdx.y +
blockDim.x * blockDim.y * threadIdx.z;
int blockPositionInGrid = blockIdx.x +
gridDim.x * blockIdx.y +
gridDim.x * gridDim.y * blockIdx.z;
int tid = blockPositionInGrid * threadsPerBlock + threadPositionInBlock;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, tid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
tid);
}
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_2d_2d(int *input) {
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, gid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
gid);
}
// ===========================================
int main() {
printf(" starts ...");
int nCol = 6;
int nRow = 8;
int array_size = nCol*nRow;
int array_byte_size = sizeof(int) * array_size;
int h_data[array_size];
for (int i = 0; i< array_size; ++i)
{
h_data[i] = i;
}
printf(" data on the host: \n");
for (int i = 0; i < array_size; ++i)
{
printf(" %d", h_data[i]);
if((i%8)==0) printf("\n");
}
printf("\n\n");
int *d_data; // array on the device
cudaMalloc((void **)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 grid(nCol, 1, 1);
dim3 block(nRow, 1, 1);
printf(" data on the device: \n");
//unique_gid_calculation_2d_2d<<<grid, block>>>(d_data);
unique_gid_calculation_3d_3d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
printf(" finished.");
return 0;
} | .file "tmpxft_000a210a_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi
.type _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi, @function
_Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z28unique_gid_calculation_3d_3dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi, .-_Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi
.globl _Z28unique_gid_calculation_3d_3dPi
.type _Z28unique_gid_calculation_3d_3dPi, @function
_Z28unique_gid_calculation_3d_3dPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z28unique_gid_calculation_3d_3dPi, .-_Z28unique_gid_calculation_3d_3dPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " starts ..."
.LC1:
.string " data on the host: \n"
.LC2:
.string " %d"
.LC3:
.string "\n"
.LC4:
.string "\n\n"
.LC5:
.string " data on the device: \n"
.LC6:
.string " finished."
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $240, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %eax
.L12:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $48, %rax
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
leaq .LC3(%rip), %r12
jmp .L14
.L13:
addq $1, %rbx
cmpq $48, %rbx
je .L20
.L14:
movl 32(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $7, %bl
jne .L13
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L20:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $192, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $192, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $240, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq (%rsp), %rdi
call _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi
.type _Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi, @function
_Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z28unique_gid_calculation_2d_2dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi, .-_Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi
.globl _Z28unique_gid_calculation_2d_2dPi
.type _Z28unique_gid_calculation_2d_2dPi, @function
_Z28unique_gid_calculation_2d_2dPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z28unique_gid_calculation_2d_2dPi, .-_Z28unique_gid_calculation_2d_2dPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z28unique_gid_calculation_2d_2dPi"
.align 8
.LC8:
.string "_Z28unique_gid_calculation_3d_3dPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z28unique_gid_calculation_2d_2dPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z28unique_gid_calculation_3d_3dPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Babak Poursartip
// 09/14/2020
// Udemy Cuda
// unique index calculation
#include <cstdio>
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_3d_3d(int *input) {
int threadsPerBlock = blockDim.x * blockDim.y * blockDim.z;
int threadPositionInBlock = threadIdx.x +
blockDim.x * threadIdx.y +
blockDim.x * blockDim.y * threadIdx.z;
int blockPositionInGrid = blockIdx.x +
gridDim.x * blockIdx.y +
gridDim.x * gridDim.y * blockIdx.z;
int tid = blockPositionInGrid * threadsPerBlock + threadPositionInBlock;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, tid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
tid);
}
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_2d_2d(int *input) {
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, gid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
gid);
}
// ===========================================
int main() {
printf(" starts ...");
int nCol = 6;
int nRow = 8;
int array_size = nCol*nRow;
int array_byte_size = sizeof(int) * array_size;
int h_data[array_size];
for (int i = 0; i< array_size; ++i)
{
h_data[i] = i;
}
printf(" data on the host: \n");
for (int i = 0; i < array_size; ++i)
{
printf(" %d", h_data[i]);
if((i%8)==0) printf("\n");
}
printf("\n\n");
int *d_data; // array on the device
cudaMalloc((void **)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 grid(nCol, 1, 1);
dim3 block(nRow, 1, 1);
printf(" data on the device: \n");
//unique_gid_calculation_2d_2d<<<grid, block>>>(d_data);
unique_gid_calculation_3d_3d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
printf(" finished.");
return 0;
} | // Babak Poursartip
// 09/14/2020
// Udemy Cuda
// unique index calculation
#include <hip/hip_runtime.h>
#include <cstdio>
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_3d_3d(int *input) {
int threadsPerBlock = blockDim.x * blockDim.y * blockDim.z;
int threadPositionInBlock = threadIdx.x +
blockDim.x * threadIdx.y +
blockDim.x * blockDim.y * threadIdx.z;
int blockPositionInGrid = blockIdx.x +
gridDim.x * blockIdx.y +
gridDim.x * gridDim.y * blockIdx.z;
int tid = blockPositionInGrid * threadsPerBlock + threadPositionInBlock;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, tid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
tid);
}
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_2d_2d(int *input) {
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, gid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
gid);
}
// ===========================================
int main() {
printf(" starts ...");
int nCol = 6;
int nRow = 8;
int array_size = nCol*nRow;
int array_byte_size = sizeof(int) * array_size;
int h_data[array_size];
for (int i = 0; i< array_size; ++i)
{
h_data[i] = i;
}
printf(" data on the host: \n");
for (int i = 0; i < array_size; ++i)
{
printf(" %d", h_data[i]);
if((i%8)==0) printf("\n");
}
printf("\n\n");
int *d_data; // array on the device
hipMalloc((void **)&d_data, array_byte_size);
hipMemcpy(d_data, h_data, array_byte_size, hipMemcpyHostToDevice);
dim3 grid(nCol, 1, 1);
dim3 block(nRow, 1, 1);
printf(" data on the device: \n");
//unique_gid_calculation_2d_2d<<<grid, block>>>(d_data);
unique_gid_calculation_3d_3d<<<grid, block>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
printf(" finished.");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Babak Poursartip
// 09/14/2020
// Udemy Cuda
// unique index calculation
#include <hip/hip_runtime.h>
#include <cstdio>
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_3d_3d(int *input) {
int threadsPerBlock = blockDim.x * blockDim.y * blockDim.z;
int threadPositionInBlock = threadIdx.x +
blockDim.x * threadIdx.y +
blockDim.x * blockDim.y * threadIdx.z;
int blockPositionInGrid = blockIdx.x +
gridDim.x * blockIdx.y +
gridDim.x * gridDim.y * blockIdx.z;
int tid = blockPositionInGrid * threadsPerBlock + threadPositionInBlock;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, tid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
tid);
}
// ===========================================
// 2d grid, 2d block
__global__ void unique_gid_calculation_2d_2d(int *input) {
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_in_a_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_in_a_block;
int num_threads_in_a_row = num_threads_in_a_block * gridDim.x;
int row_offset = num_threads_in_a_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("gridDim.x: %d, gridDim.y: %d, gridDim.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, gid: %d \n",
gridDim.x, gridDim.y, gridDim.z,
blockDim.x, blockDim.y, blockDim.z,
blockIdx.x, blockIdx.y, blockIdx.z,
threadIdx.x, threadIdx.y, threadIdx.z,
gid);
}
// ===========================================
int main() {
printf(" starts ...");
int nCol = 6;
int nRow = 8;
int array_size = nCol*nRow;
int array_byte_size = sizeof(int) * array_size;
int h_data[array_size];
for (int i = 0; i< array_size; ++i)
{
h_data[i] = i;
}
printf(" data on the host: \n");
for (int i = 0; i < array_size; ++i)
{
printf(" %d", h_data[i]);
if((i%8)==0) printf("\n");
}
printf("\n\n");
int *d_data; // array on the device
hipMalloc((void **)&d_data, array_byte_size);
hipMemcpy(d_data, h_data, array_byte_size, hipMemcpyHostToDevice);
dim3 grid(nCol, 1, 1);
dim3 block(nRow, 1, 1);
printf(" data on the device: \n");
//unique_gid_calculation_2d_2d<<<grid, block>>>(d_data);
unique_gid_calculation_3d_3d<<<grid, block>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
printf(" finished.");
return 0;
} | .text
.file "main.hip"
.globl _Z43__device_stub__unique_gid_calculation_3d_3dPi # -- Begin function _Z43__device_stub__unique_gid_calculation_3d_3dPi
.p2align 4, 0x90
.type _Z43__device_stub__unique_gid_calculation_3d_3dPi,@function
_Z43__device_stub__unique_gid_calculation_3d_3dPi: # @_Z43__device_stub__unique_gid_calculation_3d_3dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z28unique_gid_calculation_3d_3dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z43__device_stub__unique_gid_calculation_3d_3dPi, .Lfunc_end0-_Z43__device_stub__unique_gid_calculation_3d_3dPi
.cfi_endproc
# -- End function
.globl _Z43__device_stub__unique_gid_calculation_2d_2dPi # -- Begin function _Z43__device_stub__unique_gid_calculation_2d_2dPi
.p2align 4, 0x90
.type _Z43__device_stub__unique_gid_calculation_2d_2dPi,@function
_Z43__device_stub__unique_gid_calculation_2d_2dPi: # @_Z43__device_stub__unique_gid_calculation_2d_2dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z28unique_gid_calculation_2d_2dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z43__device_stub__unique_gid_calculation_2d_2dPi, .Lfunc_end1-_Z43__device_stub__unique_gid_calculation_2d_2dPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -16
xorl %ebx, %ebx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 80(%rsp,%rbx,4)
incq %rbx
cmpq $48, %rbx
jne .LBB2_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
incq %rbx
cmpq $48, %rbx
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
testb $7, %bl
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_5
.LBB2_6:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $192, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $192, %edx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $4294967302, %rdi # imm = 0x100000006
leaq 2(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z28unique_gid_calculation_3d_3dPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
callq hipDeviceReset
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28unique_gid_calculation_3d_3dPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28unique_gid_calculation_2d_2dPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28unique_gid_calculation_3d_3dPi,@object # @_Z28unique_gid_calculation_3d_3dPi
.section .rodata,"a",@progbits
.globl _Z28unique_gid_calculation_3d_3dPi
.p2align 3, 0x0
_Z28unique_gid_calculation_3d_3dPi:
.quad _Z43__device_stub__unique_gid_calculation_3d_3dPi
.size _Z28unique_gid_calculation_3d_3dPi, 8
.type _Z28unique_gid_calculation_2d_2dPi,@object # @_Z28unique_gid_calculation_2d_2dPi
.globl _Z28unique_gid_calculation_2d_2dPi
.p2align 3, 0x0
_Z28unique_gid_calculation_2d_2dPi:
.quad _Z43__device_stub__unique_gid_calculation_2d_2dPi
.size _Z28unique_gid_calculation_2d_2dPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " starts ..."
.size .L.str, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %d"
.size .L.str.2, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " finished."
.size .L.str.6, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28unique_gid_calculation_3d_3dPi"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z28unique_gid_calculation_2d_2dPi"
.size .L__unnamed_2, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " data on the host: "
.size .Lstr, 20
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " data on the device: "
.size .Lstr.2, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__unique_gid_calculation_3d_3dPi
.addrsig_sym _Z43__device_stub__unique_gid_calculation_2d_2dPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28unique_gid_calculation_3d_3dPi
.addrsig_sym _Z28unique_gid_calculation_2d_2dPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a210a_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi
.type _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi, @function
_Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z28unique_gid_calculation_3d_3dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi, .-_Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi
.globl _Z28unique_gid_calculation_3d_3dPi
.type _Z28unique_gid_calculation_3d_3dPi, @function
_Z28unique_gid_calculation_3d_3dPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z28unique_gid_calculation_3d_3dPi, .-_Z28unique_gid_calculation_3d_3dPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " starts ..."
.LC1:
.string " data on the host: \n"
.LC2:
.string " %d"
.LC3:
.string "\n"
.LC4:
.string "\n\n"
.LC5:
.string " data on the device: \n"
.LC6:
.string " finished."
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $240, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %eax
.L12:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $48, %rax
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
leaq .LC3(%rip), %r12
jmp .L14
.L13:
addq $1, %rbx
cmpq $48, %rbx
je .L20
.L14:
movl 32(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $7, %bl
jne .L13
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L20:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $192, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $192, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $240, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq (%rsp), %rdi
call _Z48__device_stub__Z28unique_gid_calculation_3d_3dPiPi
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi
.type _Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi, @function
_Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z28unique_gid_calculation_2d_2dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi, .-_Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi
.globl _Z28unique_gid_calculation_2d_2dPi
.type _Z28unique_gid_calculation_2d_2dPi, @function
_Z28unique_gid_calculation_2d_2dPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z28unique_gid_calculation_2d_2dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z28unique_gid_calculation_2d_2dPi, .-_Z28unique_gid_calculation_2d_2dPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z28unique_gid_calculation_2d_2dPi"
.align 8
.LC8:
.string "_Z28unique_gid_calculation_3d_3dPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z28unique_gid_calculation_2d_2dPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z28unique_gid_calculation_3d_3dPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z43__device_stub__unique_gid_calculation_3d_3dPi # -- Begin function _Z43__device_stub__unique_gid_calculation_3d_3dPi
.p2align 4, 0x90
.type _Z43__device_stub__unique_gid_calculation_3d_3dPi,@function
_Z43__device_stub__unique_gid_calculation_3d_3dPi: # @_Z43__device_stub__unique_gid_calculation_3d_3dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z28unique_gid_calculation_3d_3dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z43__device_stub__unique_gid_calculation_3d_3dPi, .Lfunc_end0-_Z43__device_stub__unique_gid_calculation_3d_3dPi
.cfi_endproc
# -- End function
.globl _Z43__device_stub__unique_gid_calculation_2d_2dPi # -- Begin function _Z43__device_stub__unique_gid_calculation_2d_2dPi
.p2align 4, 0x90
.type _Z43__device_stub__unique_gid_calculation_2d_2dPi,@function
_Z43__device_stub__unique_gid_calculation_2d_2dPi: # @_Z43__device_stub__unique_gid_calculation_2d_2dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z28unique_gid_calculation_2d_2dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z43__device_stub__unique_gid_calculation_2d_2dPi, .Lfunc_end1-_Z43__device_stub__unique_gid_calculation_2d_2dPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -16
xorl %ebx, %ebx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 80(%rsp,%rbx,4)
incq %rbx
cmpq $48, %rbx
jne .LBB2_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
incq %rbx
cmpq $48, %rbx
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
testb $7, %bl
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_5
.LBB2_6:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $192, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $192, %edx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $4294967302, %rdi # imm = 0x100000006
leaq 2(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z28unique_gid_calculation_3d_3dPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
callq hipDeviceReset
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28unique_gid_calculation_3d_3dPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28unique_gid_calculation_2d_2dPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28unique_gid_calculation_3d_3dPi,@object # @_Z28unique_gid_calculation_3d_3dPi
.section .rodata,"a",@progbits
.globl _Z28unique_gid_calculation_3d_3dPi
.p2align 3, 0x0
_Z28unique_gid_calculation_3d_3dPi:
.quad _Z43__device_stub__unique_gid_calculation_3d_3dPi
.size _Z28unique_gid_calculation_3d_3dPi, 8
.type _Z28unique_gid_calculation_2d_2dPi,@object # @_Z28unique_gid_calculation_2d_2dPi
.globl _Z28unique_gid_calculation_2d_2dPi
.p2align 3, 0x0
_Z28unique_gid_calculation_2d_2dPi:
.quad _Z43__device_stub__unique_gid_calculation_2d_2dPi
.size _Z28unique_gid_calculation_2d_2dPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " starts ..."
.size .L.str, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %d"
.size .L.str.2, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " finished."
.size .L.str.6, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28unique_gid_calculation_3d_3dPi"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z28unique_gid_calculation_2d_2dPi"
.size .L__unnamed_2, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " data on the host: "
.size .Lstr, 20
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " data on the device: "
.size .Lstr.2, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__unique_gid_calculation_3d_3dPi
.addrsig_sym _Z43__device_stub__unique_gid_calculation_2d_2dPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28unique_gid_calculation_3d_3dPi
.addrsig_sym _Z28unique_gid_calculation_2d_2dPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
__constant__ int inc;
__device__ int sum;
__global__ void atomicAdd()
{
int s = atomicAdd(&sum, inc);
assert((s - 1) % inc == 0);
if (threadIdx.x == 0)
{
printf("blockIdx.x = %d, sum = %d\n", blockIdx.x, s);
}
}
int main(int argc, char *argv[])
{
// Initialize inc and sum.
int h_inc = 3;
int h_sum = 1;
// Copy inc and sum from host memory to device memory synchronously.
cudaMemcpyToSymbol(inc, &h_inc, sizeof(int));
cudaMemcpyToSymbol(sum, &h_sum, sizeof(int));
// Invoke the kernel on device asynchronously.
atomicAdd<<<2, 2>>>();
// Copy sum from device memory to host memory synchronously.
cudaMemcpyFromSymbol(&h_sum, sum, sizeof(int));
// Print the result.
printf("sum = %d\n", h_sum);
// Cleanup.
cudaDeviceReset();
} | code for sm_80
Function : _Z9atomicAddv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e220000000000 */
/*0020*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ FLO.U32 R4, UR6 ; /* 0x0000000600047d00 */
/* 0x000e2200080e0000 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fcc0007ffe0ff */
/*0070*/ POPC R0, UR6 ; /* 0x0000000600007d09 */
/* 0x000e620008000000 */
/*0080*/ ISETP.EQ.U32.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x001fe20003f02070 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff037624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R5, R0, c[0x3][0x0], RZ ; /* 0x00c0000000057a24 */
/* 0x002fd400078e02ff */
/*00b0*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R3, [R2.64], R5 ; /* 0x00000005020309a8 */
/* 0x000ea200081ee1c4 */
/*00c0*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc60007f3e0ff */
/*00d0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*00e0*/ S2R R10, SR_LTMASK ; /* 0x00000000000a7919 */
/* 0x000e620000003900 */
/*00f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fe40003f05270 */
/*0100*/ LOP3.LUT R10, R10, UR6, RZ, 0xc0, !PT ; /* 0x000000060a0a7c12 */
/* 0x002fe2000f8ec0ff */
/*0110*/ SHFL.IDX PT, R9, R3, R4, 0x1f ; /* 0x00001f0403097589 */
/* 0x00407400000e0000 */
/*0120*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0130*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000ea20000002500 */
/*0140*/ POPC R10, R10 ; /* 0x0000000a000a7309 */
/* 0x000ee20000000000 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fc400008e06ff */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x001fe200078e00ff */
/*0180*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0001220000000a00 */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD R9, R10, c[0x3][0x0], R9 ; /* 0x00c000000a097a24 */
/* 0x00afca00078e0209 */
/*01b0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0041e40000100a00 */
/*01c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*01d0*/ MOV R11, 0x240 ; /* 0x00000240000b7802 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R20, 0x1c0 ; /* 0x000001c000147802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0200*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0210*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0220*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0230*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x010fea0003c00000 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
__constant__ int inc;
__device__ int sum;
__global__ void atomicAdd()
{
int s = atomicAdd(&sum, inc);
assert((s - 1) % inc == 0);
if (threadIdx.x == 0)
{
printf("blockIdx.x = %d, sum = %d\n", blockIdx.x, s);
}
}
int main(int argc, char *argv[])
{
// Initialize inc and sum.
int h_inc = 3;
int h_sum = 1;
// Copy inc and sum from host memory to device memory synchronously.
cudaMemcpyToSymbol(inc, &h_inc, sizeof(int));
cudaMemcpyToSymbol(sum, &h_sum, sizeof(int));
// Invoke the kernel on device asynchronously.
atomicAdd<<<2, 2>>>();
// Copy sum from device memory to host memory synchronously.
cudaMemcpyFromSymbol(&h_sum, sum, sizeof(int));
// Print the result.
printf("sum = %d\n", h_sum);
// Cleanup.
cudaDeviceReset();
} | .file "tmpxft_0015f1e1_00000000-6_atomicAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9atomicAddvv
.type _Z27__device_stub__Z9atomicAddvv, @function
_Z27__device_stub__Z9atomicAddvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9atomicAddv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9atomicAddvv, .-_Z27__device_stub__Z9atomicAddvv
.globl _Z9atomicAddv
.type _Z9atomicAddv, @function
_Z9atomicAddv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9atomicAddvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9atomicAddv, .-_Z9atomicAddv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sum = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $3, 8(%rsp)
movl $1, 12(%rsp)
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3inc(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3sum(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 12(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3sum(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z27__device_stub__Z9atomicAddvv
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9atomicAddv"
.LC2:
.string "inc"
.LC3:
.string "sum"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9atomicAddv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3inc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3sum(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3sum
.comm _ZL3sum,4,4
.local _ZL3inc
.comm _ZL3inc,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
__constant__ int inc;
__device__ int sum;
__global__ void atomicAdd()
{
int s = atomicAdd(&sum, inc);
assert((s - 1) % inc == 0);
if (threadIdx.x == 0)
{
printf("blockIdx.x = %d, sum = %d\n", blockIdx.x, s);
}
}
int main(int argc, char *argv[])
{
// Initialize inc and sum.
int h_inc = 3;
int h_sum = 1;
// Copy inc and sum from host memory to device memory synchronously.
cudaMemcpyToSymbol(inc, &h_inc, sizeof(int));
cudaMemcpyToSymbol(sum, &h_sum, sizeof(int));
// Invoke the kernel on device asynchronously.
atomicAdd<<<2, 2>>>();
// Copy sum from device memory to host memory synchronously.
cudaMemcpyFromSymbol(&h_sum, sum, sizeof(int));
// Print the result.
printf("sum = %d\n", h_sum);
// Cleanup.
cudaDeviceReset();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
__constant__ int inc;
__device__ int sum;
__global__ void atomicAdd()
{
int s = atomicAdd(&sum, inc);
assert((s - 1) % inc == 0);
if (threadIdx.x == 0)
{
printf("blockIdx.x = %d, sum = %d\n", blockIdx.x, s);
}
}
int main(int argc, char *argv[])
{
// Initialize inc and sum.
int h_inc = 3;
int h_sum = 1;
// Copy inc and sum from host memory to device memory synchronously.
hipMemcpyToSymbol(HIP_SYMBOL(inc), &h_inc, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(sum), &h_sum, sizeof(int));
// Invoke the kernel on device asynchronously.
atomicAdd<<<2, 2>>>();
// Copy sum from device memory to host memory synchronously.
hipMemcpyFromSymbol(&h_sum, HIP_SYMBOL(sum), sizeof(int));
// Print the result.
printf("sum = %d\n", h_sum);
// Cleanup.
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
__constant__ int inc;
__device__ int sum;
__global__ void atomicAdd()
{
int s = atomicAdd(&sum, inc);
assert((s - 1) % inc == 0);
if (threadIdx.x == 0)
{
printf("blockIdx.x = %d, sum = %d\n", blockIdx.x, s);
}
}
int main(int argc, char *argv[])
{
// Initialize inc and sum.
int h_inc = 3;
int h_sum = 1;
// Copy inc and sum from host memory to device memory synchronously.
hipMemcpyToSymbol(HIP_SYMBOL(inc), &h_inc, sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(sum), &h_sum, sizeof(int));
// Invoke the kernel on device asynchronously.
atomicAdd<<<2, 2>>>();
// Copy sum from device memory to host memory synchronously.
hipMemcpyFromSymbol(&h_sum, HIP_SYMBOL(sum), sizeof(int));
// Print the result.
printf("sum = %d\n", h_sum);
// Cleanup.
hipDeviceReset();
} | .text
.file "atomicAdd.hip"
.globl _Z24__device_stub__atomicAddv # -- Begin function _Z24__device_stub__atomicAddv
.p2align 4, 0x90
.type _Z24__device_stub__atomicAddv,@function
_Z24__device_stub__atomicAddv: # @_Z24__device_stub__atomicAddv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9atomicAddv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__atomicAddv, .Lfunc_end0-_Z24__device_stub__atomicAddv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $3, 12(%rsp)
movl $1, 8(%rsp)
leaq 12(%rsp), %rsi
movl $inc, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 8(%rsp), %rsi
movl $sum, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967298, %rdi # imm = 0x100000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9atomicAddv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
leaq 8(%rsp), %rdi
movl $sum, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl 8(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq hipDeviceReset
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9atomicAddv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $inc, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $sum, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type inc,@object # @inc
.local inc
.comm inc,4,4
.type sum,@object # @sum
.local sum
.comm sum,4,4
.type _Z9atomicAddv,@object # @_Z9atomicAddv
.section .rodata,"a",@progbits
.globl _Z9atomicAddv
.p2align 3, 0x0
_Z9atomicAddv:
.quad _Z24__device_stub__atomicAddv
.size _Z9atomicAddv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum = %d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9atomicAddv"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "inc"
.size .L__unnamed_2, 4
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "sum"
.size .L__unnamed_3, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__atomicAddv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym inc
.addrsig_sym sum
.addrsig_sym _Z9atomicAddv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015f1e1_00000000-6_atomicAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9atomicAddvv
.type _Z27__device_stub__Z9atomicAddvv, @function
_Z27__device_stub__Z9atomicAddvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9atomicAddv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9atomicAddvv, .-_Z27__device_stub__Z9atomicAddvv
.globl _Z9atomicAddv
.type _Z9atomicAddv, @function
_Z9atomicAddv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9atomicAddvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9atomicAddv, .-_Z9atomicAddv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sum = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $3, 8(%rsp)
movl $1, 12(%rsp)
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3inc(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3sum(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 12(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3sum(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z27__device_stub__Z9atomicAddvv
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9atomicAddv"
.LC2:
.string "inc"
.LC3:
.string "sum"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9atomicAddv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3inc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3sum(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3sum
.comm _ZL3sum,4,4
.local _ZL3inc
.comm _ZL3inc,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "atomicAdd.hip"
.globl _Z24__device_stub__atomicAddv # -- Begin function _Z24__device_stub__atomicAddv
.p2align 4, 0x90
.type _Z24__device_stub__atomicAddv,@function
_Z24__device_stub__atomicAddv: # @_Z24__device_stub__atomicAddv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9atomicAddv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__atomicAddv, .Lfunc_end0-_Z24__device_stub__atomicAddv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $3, 12(%rsp)
movl $1, 8(%rsp)
leaq 12(%rsp), %rsi
movl $inc, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 8(%rsp), %rsi
movl $sum, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967298, %rdi # imm = 0x100000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9atomicAddv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
leaq 8(%rsp), %rdi
movl $sum, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl 8(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq hipDeviceReset
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9atomicAddv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $inc, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $sum, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type inc,@object # @inc
.local inc
.comm inc,4,4
.type sum,@object # @sum
.local sum
.comm sum,4,4
.type _Z9atomicAddv,@object # @_Z9atomicAddv
.section .rodata,"a",@progbits
.globl _Z9atomicAddv
.p2align 3, 0x0
_Z9atomicAddv:
.quad _Z24__device_stub__atomicAddv
.size _Z9atomicAddv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum = %d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9atomicAddv"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "inc"
.size .L__unnamed_2, 4
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "sum"
.size .L__unnamed_3, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__atomicAddv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym inc
.addrsig_sym sum
.addrsig_sym _Z9atomicAddv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Modified from global reduction code in
// https://sodocumentation.net/cuda/topic/6566/parallel-reduction--e-g--how-to-sum-an-array-
// System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <math.h>
// CUDA runtime
#include <cuda_runtime.h>
#define BILLION 1000000000L
// Note this cannot be executed on the CPU - just on the GPU
__device__ double f( double a )
{
return (4.0 / (1.0 + a*a));
}
__global__ void PiEstSingleBlock(long N, double *piest) {
int idx = threadIdx.x;
int blockSize = blockDim.x; // We are exploiting the fact that there is just one thread group
double h;
double sum = 0.0;
h = 1.0/(double)N;
// Do the parallel partial sums for pi
for (long i = idx+1; i <= N; i += blockSize)
sum += f(h * ((double)i - 0.5));
__shared__ double p[1024]; // The maximum number of threads is 1024
// We can make this storage dynamic in size to paramterise
// over the number of threads used.
// Now add the partial sums together
p[idx] = h*sum;
__syncthreads();
for (int size = blockSize/2; size>0; size/=2) { //uniform
if (idx<size)
p[idx] += p[idx+size];
__syncthreads();
}
if (idx == 0)
*piest = p[0];
}
int main(void) {
struct timespec start , stop ; // variables for timing
double accum ; // elapsed time variable
const unsigned int blockSize=1024;
dim3 numThreads;
double pi25DT=3.141592653589793238462643;
double x;
double *mypi;
long N = 1000000;
double sum, h;
h = 1.0/(double)N; // For CPU version of loop
numThreads.x = blockSize;
cudaMallocManaged(&mypi, sizeof(double));
clock_gettime ( CLOCK_REALTIME ,&start );
PiEstSingleBlock<<<1,numThreads>>>(N, mypi);
cudaDeviceSynchronize(); // Cannot get sensible timing without synchronising host and device
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("Pi estimate %.16f error is %.16f", mypi[0],pi25DT-mypi[0]);
printf("\n");
printf("Time to compute mypi is %lf sec.\n",accum);
clock_gettime ( CLOCK_REALTIME ,&start );
sum = 0.0;
for (long i=1; i <= N; i++){
x = h * ((double)i - 0.5);
sum += 4.0/(1.0+x*x);
}
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("CPU pi is %.16f error is %.16f\n",h*sum,pi25DT-h*sum);
printf("Time to compute CPU pi is %lf sec.\n",accum);
} | code for sm_80
Function : _Z16PiEstSingleBlocklPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64.S64 R2, c[0x0][0x160] ; /* 0x0000580000027b12 */
/* 0x000e220000301c00 */
/*0020*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff177624 */
/* 0x000fce00078e00ff */
/*0030*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x001e220000001800 */
/*0040*/ IADD3 R4, R3, 0x300402, RZ ; /* 0x0030040203047810 */
/* 0x000fc80007ffe0ff */
/*0050*/ FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ; /* 0x004004020400780b */
/* 0x000fe40003f0e200 */
/*0060*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000104 */
/*0070*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0080*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*0090*/ DFMA R8, -R2, R6, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c0000000106 */
/*00a0*/ DFMA R4, R6, R8, R6 ; /* 0x000000080604722b */
/* 0x0010620000000006 */
/*00b0*/ @P0 BRA 0x100 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00c0*/ LOP3.LUT R0, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03007812 */
/* 0x000fc800078ec0ff */
/*00d0*/ IADD3 R6, R0, -0x100000, RZ ; /* 0xfff0000000067810 */
/* 0x001fe40007ffe0ff */
/*00e0*/ MOV R0, 0x100 ; /* 0x0000010000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ CALL.REL.NOINC 0x530 ; /* 0x0000043000007944 */
/* 0x002fea0003c00000 */
/*0100*/ S2R R22, SR_TID.X ; /* 0x0000000000167919 */
/* 0x000ea20000002100 */
/*0110*/ BSSY B0, 0x380 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0120*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0130*/ IADD3 R21, R22, 0x1, RZ ; /* 0x0000000116157810 */
/* 0x004fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R21, c[0x0][0x160], PT ; /* 0x0000580015007a0c */
/* 0x000fe40003f04070 */
/*0150*/ SHF.R.S32.HI R20, RZ, 0x1f, R21 ; /* 0x0000001fff147819 */
/* 0x000fc80000011415 */
/*0160*/ ISETP.GT.AND.EX P0, PT, R20, c[0x0][0x164], PT, P0 ; /* 0x0000590014007a0c */
/* 0x000fda0003f04300 */
/*0170*/ @P0 BRA 0x370 ; /* 0x000001f000000947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff137624 */
/* 0x000fe200078e00ff */
/*0190*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*01a0*/ IMAD.MOV.U32 R12, RZ, RZ, R21 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0015 */
/*01b0*/ IADD3 R21, P0, R21, c[0x0][0x0], RZ ; /* 0x0000000015157a10 */
/* 0x000fe20007f1e0ff */
/*01c0*/ IMAD.MOV.U32 R13, RZ, RZ, R20 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0014 */
/*01d0*/ BSSY B1, 0x350 ; /* 0x0000017000017945 */
/* 0x000fe40003800000 */
/*01e0*/ LEA.HI.X.SX32 R20, R19, R20, 0x1, P0 ; /* 0x0000001413147211 */
/* 0x000fe200000f0eff */
/*01f0*/ I2F.F64.S64 R6, R12 ; /* 0x0000000c00067312 */
/* 0x001e220000301c00 */
/*0200*/ ISETP.GT.U32.AND P0, PT, R21, c[0x0][0x160], PT ; /* 0x0000580015007a0c */
/* 0x000fc80003f04070 */
/*0210*/ ISETP.GT.AND.EX P0, PT, R20, c[0x0][0x164], PT, P0 ; /* 0x0000590014007a0c */
/* 0x000fe20003f04300 */
/*0220*/ DADD R6, R6, -0.5 ; /* 0xbfe0000006067429 */
/* 0x001e0c0000000000 */
/*0230*/ DMUL R6, R6, R4 ; /* 0x0000000406067228 */
/* 0x003e0c0000000000 */
/*0240*/ DFMA R8, R6, R6, 1 ; /* 0x3ff000000608742b */
/* 0x0010640000000006 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x001fc800078e00ff */
/*0260*/ MUFU.RCP64H R7, R9 ; /* 0x0000000900077308 */
/* 0x002e240000001800 */
/*0270*/ DFMA R10, -R8, R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000106 */
/*0280*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0290*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x001e0c0000000006 */
/*02a0*/ DFMA R6, -R8, R10, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c000000010a */
/*02b0*/ DFMA R6, R10, R6, R10 ; /* 0x000000060a06722b */
/* 0x001e0c000000000a */
/*02c0*/ DMUL R10, R6, 4 ; /* 0x40100000060a7828 */
/* 0x001e0c0000000000 */
/*02d0*/ DFMA R12, -R8, R10, 4 ; /* 0x40100000080c742b */
/* 0x001e0c000000010a */
/*02e0*/ DFMA R6, R6, R12, R10 ; /* 0x0000000c0606722b */
/* 0x001e14000000000a */
/*02f0*/ FFMA R0, RZ, R9, R7 ; /* 0x00000009ff007223 */
/* 0x001fca0000000007 */
/*0300*/ FSETP.GT.AND P1, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f24200 */
/*0310*/ @P1 BRA 0x340 ; /* 0x0000002000001947 */
/* 0x004fea0003800000 */
/*0320*/ MOV R24, 0x340 ; /* 0x0000034000187802 */
/* 0x000fe40000000f00 */
/*0330*/ CALL.REL.NOINC 0x790 ; /* 0x0000045000007944 */
/* 0x000fea0003c00000 */
/*0340*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0350*/ DADD R2, R6, R2 ; /* 0x0000000006027229 */
/* 0x0000a20000000002 */
/*0360*/ @!P0 BRA 0x1a0 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0390*/ DMUL R2, R4, R2 ; /* 0x0000000204027228 */
/* 0x006e620000000000 */
/*03a0*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc60003f05270 */
/*03b0*/ ISETP.GE.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fc60003f26270 */
/*03c0*/ STS.64 [R22.X8], R2 ; /* 0x0000000216007388 */
/* 0x0023e80000008a00 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03e0*/ @!P1 BRA 0x4c0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.SHL.U32 R0, R22, 0x8, RZ ; /* 0x0000000816007824 */
/* 0x000fe400078e00ff */
/*0400*/ LEA.HI R2, R23, R23, RZ, 0x1 ; /* 0x0000001717027211 */
/* 0x002fc800078f08ff */
/*0410*/ SHF.R.S32.HI R7, RZ, 0x1, R2 ; /* 0x00000001ff077819 */
/* 0x001fc80000011402 */
/*0420*/ ISETP.GE.AND P1, PT, R22, R7, PT ; /* 0x000000071600720c */
/* 0x000fda0003f26270 */
/*0430*/ @!P1 IMAD R4, R7, 0x8, R0 ; /* 0x0000000807049824 */
/* 0x000fe200078e0200 */
/*0440*/ @!P1 LDS.64 R2, [R22.X8] ; /* 0x0000000016029984 */
/* 0x000fea0000008a00 */
/*0450*/ @!P1 LDS.64 R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000a00 */
/*0460*/ @!P1 DADD R2, R2, R4 ; /* 0x0000000002029229 */
/* 0x001e0e0000000004 */
/*0470*/ @!P1 STS.64 [R22.X8], R2 ; /* 0x0000000216009388 */
/* 0x0011e80000008a00 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0490*/ ISETP.GT.AND P1, PT, R23, 0x3, PT ; /* 0x000000031700780c */
/* 0x000fe20003f24270 */
/*04a0*/ IMAD.MOV.U32 R23, RZ, RZ, R7 ; /* 0x000000ffff177224 */
/* 0x000fd800078e0007 */
/*04b0*/ @P1 BRA 0x400 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*04c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04d0*/ LDS.64 R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x002e620000000a00 */
/*04e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*04f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0510*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ DSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7ff000000200742a */
/* 0x000e1c0003f0c200 */
/*0540*/ @P0 BRA 0x740 ; /* 0x000001f000000947 */
/* 0x001fea0003800000 */
/*0550*/ LOP3.LUT R7, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03077812 */
/* 0x000fc800078ec0ff */
/*0560*/ IADD3 R4, R7, -0x1, RZ ; /* 0xffffffff07047810 */
/* 0x000fc80007ffe0ff */
/*0570*/ ISETP.GE.U32.AND P0, PT, R4, 0x7fefffff, PT ; /* 0x7fefffff0400780c */
/* 0x000fda0003f06070 */
/*0580*/ @P0 LOP3.LUT R5, R3, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000003050812 */
/* 0x000fe200078e3cff */
/*0590*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe200078e00ff */
/*05a0*/ @P0 BRA 0x760 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R7, 0x1000001, PT ; /* 0x010000010700780c */
/* 0x000fda0003f06070 */
/*05c0*/ @!P0 BRA 0x6a0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R5, R3, -0x3fe00000, RZ ; /* 0xc020000003057810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0002 */
/*05f0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x000e260000001800 */
/*0600*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0610*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0620*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0630*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000108 */
/*0640*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e0c0000000008 */
/*0650*/ DMUL R6, R6, 2.2250738585072013831e-308 ; /* 0x0010000006067828 */
/* 0x001e0c0000000000 */
/*0660*/ DFMA R2, -R2, R6, 1 ; /* 0x3ff000000202742b */
/* 0x001e0c0000000106 */
/*0670*/ DFMA R2, R2, R2, R2 ; /* 0x000000020202722b */
/* 0x001e0c0000000002 */
/*0680*/ DFMA R4, R6, R2, R6 ; /* 0x000000020604722b */
/* 0x0010620000000006 */
/*0690*/ BRA 0x760 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*06a0*/ DMUL R2, R2, 8.11296384146066816958e+31 ; /* 0x4690000002027828 */
/* 0x000e220000000000 */
/*06b0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0006 */
/*06c0*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x001e240000001800 */
/*06d0*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000104 */
/*06e0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*06f0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*0700*/ DFMA R4, -R2, R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000106 */
/*0710*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e0c0000000006 */
/*0720*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x001e220000000000 */
/*0730*/ BRA 0x760 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT R5, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000003057812 */
/* 0x000fe200078efcff */
/*0750*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0760*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*0770*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0780*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff87002007950 */
/* 0x000fea0003c3ffff */
/*0790*/ FSETP.GEU.AND P1, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f2e200 */
/*07a0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*07b0*/ LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09067812 */
/* 0x040fe200078ec0ff */
/*07c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x40100000 ; /* 0x40100000ff007424 */
/* 0x000fe200078e00ff */
/*07d0*/ LOP3.LUT R25, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009197812 */
/* 0x000fe200078ec0ff */
/*07e0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff127424 */
/* 0x000fe200078e00ff */
/*07f0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0800*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0810*/ ISETP.LE.U32.AND P2, PT, R25, 0x40100000, PT ; /* 0x401000001900780c */
/* 0x000fe20003f43070 */
/*0820*/ BSSY B2, 0xc30 ; /* 0x0000040000027945 */
/* 0x000fe20003800000 */
/*0830*/ IADD3 R16, R0, -0x1, RZ ; /* 0xffffffff00107810 */
/* 0x000fc60007ffe0ff */
/*0840*/ @!P1 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008069828 */
/* 0x000e0c0000000000 */
/*0850*/ MUFU.RCP64H R13, R7 ; /* 0x00000007000d7308 */
/* 0x001e280000001800 */
/*0860*/ @!P1 LOP3.LUT R25, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007199812 */
/* 0x000fe400078ec0ff */
/*0870*/ ISETP.GT.U32.AND P1, PT, R16, 0x7feffffe, PT ; /* 0x7feffffe1000780c */
/* 0x000fe40003f24070 */
/*0880*/ IADD3 R26, R25, -0x1, RZ ; /* 0xffffffff191a7810 */
/* 0x000fc80007ffe0ff */
/*0890*/ ISETP.GT.U32.OR P1, PT, R26, 0x7feffffe, P1 ; /* 0x7feffffe1a00780c */
/* 0x000fe20000f24470 */
/*08a0*/ DFMA R10, R12, -R6, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c0000000806 */
/*08b0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*08c0*/ DFMA R12, R12, R10, R12 ; /* 0x0000000a0c0c722b */
/* 0x001064000000000c */
/*08d0*/ SEL R11, R18, 0x63400000, !P2 ; /* 0x63400000120b7807 */
/* 0x001fe20005000000 */
/*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*08f0*/ DFMA R14, R12, -R6, 1 ; /* 0x3ff000000c0e742b */
/* 0x002e0c0000000806 */
/*0900*/ DFMA R12, R12, R14, R12 ; /* 0x0000000e0c0c722b */
/* 0x001e0c000000000c */
/*0910*/ DMUL R14, R12, R10 ; /* 0x0000000a0c0e7228 */
/* 0x001e0c0000000000 */
/*0920*/ DFMA R16, R14, -R6, R10 ; /* 0x800000060e10722b */
/* 0x001e0c000000000a */
/*0930*/ DFMA R16, R12, R16, R14 ; /* 0x000000100c10722b */
/* 0x001062000000000e */
/*0940*/ @P1 BRA 0xb10 ; /* 0x000001c000001947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT R12, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090c7812 */
/* 0x001fe200078ec0ff */
/*0960*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e00ff */
/*0970*/ IADD3 R0, -R12.reuse, 0x40100000, RZ ; /* 0x401000000c007810 */
/* 0x040fe40007ffe1ff */
/*0980*/ ISETP.LE.U32.AND P1, PT, R12, 0x40100000, PT ; /* 0x401000000c00780c */
/* 0x000fe40003f23070 */
/*0990*/ IMNMX R0, R0, -0x46a00000, !PT ; /* 0xb960000000007817 */
/* 0x000fe40007800200 */
/*09a0*/ SEL R13, R18, 0x63400000, !P1 ; /* 0x63400000120d7807 */
/* 0x000fe40004800000 */
/*09b0*/ IMNMX R0, R0, 0x46a00000, PT ; /* 0x46a0000000007817 */
/* 0x000fca0003800200 */
/*09c0*/ IMAD.IADD R0, R0, 0x1, -R13 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a0d */
/*09d0*/ IADD3 R15, R0, 0x7fe00000, RZ ; /* 0x7fe00000000f7810 */
/* 0x000fcc0007ffe0ff */
/*09e0*/ DMUL R12, R16, R14 ; /* 0x0000000e100c7228 */
/* 0x002e140000000000 */
/*09f0*/ FSETP.GTU.AND P1, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f2c200 */
/*0a00*/ @P1 BRA 0xc20 ; /* 0x0000021000001947 */
/* 0x000fea0003800000 */
/*0a10*/ DFMA R6, R16, -R6, R10 ; /* 0x800000061006722b */
/* 0x000e22000000000a */
/*0a20*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd200078e00ff */
/*0a30*/ FSETP.NEU.AND P1, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f2d000 */
/*0a40*/ LOP3.LUT R9, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007097812 */
/* 0x000fc800078e4809 */
/*0a50*/ LOP3.LUT R15, R9, R15, RZ, 0xfc, !PT ; /* 0x0000000f090f7212 */
/* 0x000fce00078efcff */
/*0a60*/ @!P1 BRA 0xc20 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0a70*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a00 */
/*0a80*/ DMUL.RP R14, R16, R14 ; /* 0x0000000e100e7228 */
/* 0x000e220000008000 */
/*0a90*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fcc00078e00ff */
/*0aa0*/ DFMA R6, R12, -R6, R16 ; /* 0x800000060c06722b */
/* 0x000e460000000010 */
/*0ab0*/ LOP3.LUT R9, R15, R9, RZ, 0x3c, !PT ; /* 0x000000090f097212 */
/* 0x001fc600078e3cff */
/*0ac0*/ IADD3 R6, -R0, -0x43300000, RZ ; /* 0xbcd0000000067810 */
/* 0x002fc80007ffe1ff */
/*0ad0*/ FSETP.NEU.AND P1, PT, |R7|, R6, PT ; /* 0x000000060700720b */
/* 0x000fc80003f2d200 */
/*0ae0*/ FSEL R12, R14, R12, !P1 ; /* 0x0000000c0e0c7208 */
/* 0x000fe40004800000 */
/*0af0*/ FSEL R13, R9, R13, !P1 ; /* 0x0000000d090d7208 */
/* 0x000fe20004800000 */
/*0b00*/ BRA 0xc20 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0b10*/ DSETP.NAN.AND P1, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f28000 */
/*0b20*/ @P1 BRA 0xc00 ; /* 0x000000d000001947 */
/* 0x004fea0003800000 */
/*0b30*/ ISETP.NE.AND P1, PT, R0, R25, PT ; /* 0x000000190000720c */
/* 0x000fe20003f25270 */
/*0b40*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x001fe400078e00ff */
/*0b50*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0b60*/ @!P1 BRA 0xc20 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0b70*/ ISETP.NE.AND P1, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fe40003f25270 */
/*0b80*/ LOP3.LUT R8, R9, 0x40100000, RZ, 0x3c, !PT ; /* 0x4010000009087812 */
/* 0x000fe400078e3cff */
/*0b90*/ ISETP.EQ.OR P1, PT, R25, RZ, !P1 ; /* 0x000000ff1900720c */
/* 0x000fe40004f22670 */
/*0ba0*/ LOP3.LUT R13, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000080d7812 */
/* 0x000fd600078ec0ff */
/*0bb0*/ @P1 LOP3.LUT R0, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d001812 */
/* 0x000fe200078efcff */
/*0bc0*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c9224 */
/* 0x000fe400078e00ff */
/*0bd0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c1224 */
/* 0x000fe400078e00ff */
/*0be0*/ @P1 IMAD.MOV.U32 R13, RZ, RZ, R0 ; /* 0x000000ffff0d1224 */
/* 0x000fe200078e0000 */
/*0bf0*/ BRA 0xc20 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c00*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x001fe200078efcff */
/*0c10*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0c20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c30*/ IMAD.MOV.U32 R25, RZ, RZ, 0x0 ; /* 0x00000000ff197424 */
/* 0x000fe400078e00ff */
/*0c40*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000c */
/*0c50*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0c60*/ RET.REL.NODEC R24 0x0 ; /* 0xfffff39018007950 */
/* 0x000fec0003c3ffff */
/*0c70*/ BRA 0xc70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Modified from global reduction code in
// https://sodocumentation.net/cuda/topic/6566/parallel-reduction--e-g--how-to-sum-an-array-
// System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <math.h>
// CUDA runtime
#include <cuda_runtime.h>
#define BILLION 1000000000L
// Note this cannot be executed on the CPU - just on the GPU
__device__ double f( double a )
{
return (4.0 / (1.0 + a*a));
}
__global__ void PiEstSingleBlock(long N, double *piest) {
int idx = threadIdx.x;
int blockSize = blockDim.x; // We are exploiting the fact that there is just one thread group
double h;
double sum = 0.0;
h = 1.0/(double)N;
// Do the parallel partial sums for pi
for (long i = idx+1; i <= N; i += blockSize)
sum += f(h * ((double)i - 0.5));
__shared__ double p[1024]; // The maximum number of threads is 1024
// We can make this storage dynamic in size to paramterise
// over the number of threads used.
// Now add the partial sums together
p[idx] = h*sum;
__syncthreads();
for (int size = blockSize/2; size>0; size/=2) { //uniform
if (idx<size)
p[idx] += p[idx+size];
__syncthreads();
}
if (idx == 0)
*piest = p[0];
}
int main(void) {
struct timespec start , stop ; // variables for timing
double accum ; // elapsed time variable
const unsigned int blockSize=1024;
dim3 numThreads;
double pi25DT=3.141592653589793238462643;
double x;
double *mypi;
long N = 1000000;
double sum, h;
h = 1.0/(double)N; // For CPU version of loop
numThreads.x = blockSize;
cudaMallocManaged(&mypi, sizeof(double));
clock_gettime ( CLOCK_REALTIME ,&start );
PiEstSingleBlock<<<1,numThreads>>>(N, mypi);
cudaDeviceSynchronize(); // Cannot get sensible timing without synchronising host and device
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("Pi estimate %.16f error is %.16f", mypi[0],pi25DT-mypi[0]);
printf("\n");
printf("Time to compute mypi is %lf sec.\n",accum);
clock_gettime ( CLOCK_REALTIME ,&start );
sum = 0.0;
for (long i=1; i <= N; i++){
x = h * ((double)i - 0.5);
sum += 4.0/(1.0+x*x);
}
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("CPU pi is %.16f error is %.16f\n",h*sum,pi25DT-h*sum);
printf("Time to compute CPU pi is %lf sec.\n",accum);
} | .file "tmpxft_001481ce_00000000-6_cupi.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1fd
.type _Z1fd, @function
_Z1fd:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z1fd, .-_Z1fd
.globl _Z37__device_stub__Z16PiEstSingleBlocklPdlPd
.type _Z37__device_stub__Z16PiEstSingleBlocklPdlPd, @function
_Z37__device_stub__Z16PiEstSingleBlocklPdlPd:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16PiEstSingleBlocklPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z37__device_stub__Z16PiEstSingleBlocklPdlPd, .-_Z37__device_stub__Z16PiEstSingleBlocklPdlPd
.globl _Z16PiEstSingleBlocklPd
.type _Z16PiEstSingleBlocklPd, @function
_Z16PiEstSingleBlocklPd:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16PiEstSingleBlocklPdlPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z16PiEstSingleBlocklPd, .-_Z16PiEstSingleBlocklPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Pi estimate %.16f error is %.16f"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Time to compute mypi is %lf sec.\n"
.align 8
.LC10:
.string "CPU pi is %.16f error is %.16f\n"
.align 8
.LC11:
.string "Time to compute CPU pi is %lf sec.\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1024, 36(%rsp)
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
call cudaDeviceSynchronize@PLT
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rsp)
movq 24(%rsp), %rax
movsd (%rax), %xmm0
movsd .LC2(%rip), %xmm1
subsd %xmm0, %xmm1
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $1, %eax
movq $0x000000000, (%rsp)
movsd .LC6(%rip), %xmm5
movsd .LC7(%rip), %xmm4
movsd .LC8(%rip), %xmm3
movsd .LC9(%rip), %xmm2
.L15:
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd %xmm5, %xmm0
mulsd %xmm4, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm3, %xmm0
movapd %xmm2, %xmm1
divsd %xmm0, %xmm1
addsd (%rsp), %xmm1
movsd %xmm1, (%rsp)
addq $1, %rax
cmpq $1000001, %rax
jne .L15
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movsd (%rsp), %xmm7
mulsd .LC7(%rip), %xmm7
movapd %xmm7, %xmm0
movsd .LC2(%rip), %xmm1
subsd %xmm7, %xmm1
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rsi
movl $1000000, %edi
call _Z37__device_stub__Z16PiEstSingleBlocklPdlPd
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z16PiEstSingleBlocklPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z16PiEstSingleBlocklPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1104006501
.align 8
.LC2:
.long 1413754136
.long 1074340347
.align 8
.LC6:
.long 0
.long 1071644672
.align 8
.LC7:
.long -1598689907
.long 1051772663
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC9:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Modified from global reduction code in
// https://sodocumentation.net/cuda/topic/6566/parallel-reduction--e-g--how-to-sum-an-array-
// System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <math.h>
// CUDA runtime
#include <cuda_runtime.h>
#define BILLION 1000000000L
// Note this cannot be executed on the CPU - just on the GPU
__device__ double f( double a )
{
return (4.0 / (1.0 + a*a));
}
__global__ void PiEstSingleBlock(long N, double *piest) {
int idx = threadIdx.x;
int blockSize = blockDim.x; // We are exploiting the fact that there is just one thread group
double h;
double sum = 0.0;
h = 1.0/(double)N;
// Do the parallel partial sums for pi
for (long i = idx+1; i <= N; i += blockSize)
sum += f(h * ((double)i - 0.5));
__shared__ double p[1024]; // The maximum number of threads is 1024
// We can make this storage dynamic in size to paramterise
// over the number of threads used.
// Now add the partial sums together
p[idx] = h*sum;
__syncthreads();
for (int size = blockSize/2; size>0; size/=2) { //uniform
if (idx<size)
p[idx] += p[idx+size];
__syncthreads();
}
if (idx == 0)
*piest = p[0];
}
int main(void) {
struct timespec start , stop ; // variables for timing
double accum ; // elapsed time variable
const unsigned int blockSize=1024;
dim3 numThreads;
double pi25DT=3.141592653589793238462643;
double x;
double *mypi;
long N = 1000000;
double sum, h;
h = 1.0/(double)N; // For CPU version of loop
numThreads.x = blockSize;
cudaMallocManaged(&mypi, sizeof(double));
clock_gettime ( CLOCK_REALTIME ,&start );
PiEstSingleBlock<<<1,numThreads>>>(N, mypi);
cudaDeviceSynchronize(); // Cannot get sensible timing without synchronising host and device
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("Pi estimate %.16f error is %.16f", mypi[0],pi25DT-mypi[0]);
printf("\n");
printf("Time to compute mypi is %lf sec.\n",accum);
clock_gettime ( CLOCK_REALTIME ,&start );
sum = 0.0;
for (long i=1; i <= N; i++){
x = h * ((double)i - 0.5);
sum += 4.0/(1.0+x*x);
}
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("CPU pi is %.16f error is %.16f\n",h*sum,pi25DT-h*sum);
printf("Time to compute CPU pi is %lf sec.\n",accum);
} | // Modified from global reduction code in
// https://sodocumentation.net/cuda/topic/6566/parallel-reduction--e-g--how-to-sum-an-array-
// System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <math.h>
// CUDA runtime
#include <hip/hip_runtime.h>
#define BILLION 1000000000L
// Note this cannot be executed on the CPU - just on the GPU
__device__ double f( double a )
{
return (4.0 / (1.0 + a*a));
}
__global__ void PiEstSingleBlock(long N, double *piest) {
int idx = threadIdx.x;
int blockSize = blockDim.x; // We are exploiting the fact that there is just one thread group
double h;
double sum = 0.0;
h = 1.0/(double)N;
// Do the parallel partial sums for pi
for (long i = idx+1; i <= N; i += blockSize)
sum += f(h * ((double)i - 0.5));
__shared__ double p[1024]; // The maximum number of threads is 1024
// We can make this storage dynamic in size to paramterise
// over the number of threads used.
// Now add the partial sums together
p[idx] = h*sum;
__syncthreads();
for (int size = blockSize/2; size>0; size/=2) { //uniform
if (idx<size)
p[idx] += p[idx+size];
__syncthreads();
}
if (idx == 0)
*piest = p[0];
}
int main(void) {
struct timespec start , stop ; // variables for timing
double accum ; // elapsed time variable
const unsigned int blockSize=1024;
dim3 numThreads;
double pi25DT=3.141592653589793238462643;
double x;
double *mypi;
long N = 1000000;
double sum, h;
h = 1.0/(double)N; // For CPU version of loop
numThreads.x = blockSize;
hipMallocManaged(&mypi, sizeof(double));
clock_gettime ( CLOCK_REALTIME ,&start );
PiEstSingleBlock<<<1,numThreads>>>(N, mypi);
hipDeviceSynchronize(); // Cannot get sensible timing without synchronising host and device
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("Pi estimate %.16f error is %.16f", mypi[0],pi25DT-mypi[0]);
printf("\n");
printf("Time to compute mypi is %lf sec.\n",accum);
clock_gettime ( CLOCK_REALTIME ,&start );
sum = 0.0;
for (long i=1; i <= N; i++){
x = h * ((double)i - 0.5);
sum += 4.0/(1.0+x*x);
}
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("CPU pi is %.16f error is %.16f\n",h*sum,pi25DT-h*sum);
printf("Time to compute CPU pi is %lf sec.\n",accum);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Modified from global reduction code in
// https://sodocumentation.net/cuda/topic/6566/parallel-reduction--e-g--how-to-sum-an-array-
// System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <math.h>
// CUDA runtime
#include <hip/hip_runtime.h>
#define BILLION 1000000000L
// Note this cannot be executed on the CPU - just on the GPU
__device__ double f( double a )
{
return (4.0 / (1.0 + a*a));
}
__global__ void PiEstSingleBlock(long N, double *piest) {
int idx = threadIdx.x;
int blockSize = blockDim.x; // We are exploiting the fact that there is just one thread group
double h;
double sum = 0.0;
h = 1.0/(double)N;
// Do the parallel partial sums for pi
for (long i = idx+1; i <= N; i += blockSize)
sum += f(h * ((double)i - 0.5));
__shared__ double p[1024]; // The maximum number of threads is 1024
// We can make this storage dynamic in size to paramterise
// over the number of threads used.
// Now add the partial sums together
p[idx] = h*sum;
__syncthreads();
for (int size = blockSize/2; size>0; size/=2) { //uniform
if (idx<size)
p[idx] += p[idx+size];
__syncthreads();
}
if (idx == 0)
*piest = p[0];
}
int main(void) {
struct timespec start , stop ; // variables for timing
double accum ; // elapsed time variable
const unsigned int blockSize=1024;
dim3 numThreads;
double pi25DT=3.141592653589793238462643;
double x;
double *mypi;
long N = 1000000;
double sum, h;
h = 1.0/(double)N; // For CPU version of loop
numThreads.x = blockSize;
hipMallocManaged(&mypi, sizeof(double));
clock_gettime ( CLOCK_REALTIME ,&start );
PiEstSingleBlock<<<1,numThreads>>>(N, mypi);
hipDeviceSynchronize(); // Cannot get sensible timing without synchronising host and device
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("Pi estimate %.16f error is %.16f", mypi[0],pi25DT-mypi[0]);
printf("\n");
printf("Time to compute mypi is %lf sec.\n",accum);
clock_gettime ( CLOCK_REALTIME ,&start );
sum = 0.0;
for (long i=1; i <= N; i++){
x = h * ((double)i - 0.5);
sum += 4.0/(1.0+x*x);
}
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("CPU pi is %.16f error is %.16f\n",h*sum,pi25DT-h*sum);
printf("Time to compute CPU pi is %lf sec.\n",accum);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16PiEstSingleBlocklPd
.globl _Z16PiEstSingleBlocklPd
.p2align 8
.type _Z16PiEstSingleBlocklPd,@function
_Z16PiEstSingleBlocklPd:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x1c
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[1:2], s3
v_cvt_f64_u32_e32 v[3:4], s2
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], 32
v_add_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[3:4], null, v[1:2], v[1:2], 1.0
v_rcp_f64_e32 v[5:6], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_div_scale_f64 v[7:8], vcc_lo, 1.0, v[1:2], 1.0
v_mul_f64 v[9:10], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], -v[3:4], v[9:10], v[7:8]
v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[9:10]
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[1:2], v[3:4], v[1:2], 1.0
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, 1, v0
v_cmpx_ge_i64_e64 s[2:3], v[3:4]
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_mov_b32 s7, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s6, s7
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_cvt_f64_i32_e32 v[7:8], v4
v_cvt_f64_u32_e32 v[9:10], v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[7:8], v[7:8], 32
v_add_f64 v[7:8], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], -0.5
v_mul_f64 v[7:8], v[1:2], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[7:8], 1.0
v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], 4.0
v_div_scale_f64 v[15:16], vcc_lo, 4.0, v[7:8], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[15:16], v[11:12]
v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
v_add_co_u32 v3, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[7:8], v[9:10], v[7:8], 4.0
v_add_f64 v[5:6], v[5:6], v[7:8]
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s5
v_mul_f64 v[2:3], v[1:2], v[5:6]
v_lshlrev_b32_e32 v1, 3, v0
s_cmp_lt_u32 s4, 2
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s2, s4, 1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.LBB0_7:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s2, v0, 3
ds_load_b64 v[2:3], v2
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_branch .LBB0_6
.LBB0_9:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16PiEstSingleBlocklPd
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16PiEstSingleBlocklPd, .Lfunc_end0-_Z16PiEstSingleBlocklPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16PiEstSingleBlocklPd
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z16PiEstSingleBlocklPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Modified from global reduction code in
// https://sodocumentation.net/cuda/topic/6566/parallel-reduction--e-g--how-to-sum-an-array-
// System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <math.h>
// CUDA runtime
#include <hip/hip_runtime.h>
#define BILLION 1000000000L
// Note this cannot be executed on the CPU - just on the GPU
__device__ double f( double a )
{
return (4.0 / (1.0 + a*a));
}
__global__ void PiEstSingleBlock(long N, double *piest) {
int idx = threadIdx.x;
int blockSize = blockDim.x; // We are exploiting the fact that there is just one thread group
double h;
double sum = 0.0;
h = 1.0/(double)N;
// Do the parallel partial sums for pi
for (long i = idx+1; i <= N; i += blockSize)
sum += f(h * ((double)i - 0.5));
__shared__ double p[1024]; // The maximum number of threads is 1024
// We can make this storage dynamic in size to paramterise
// over the number of threads used.
// Now add the partial sums together
p[idx] = h*sum;
__syncthreads();
for (int size = blockSize/2; size>0; size/=2) { //uniform
if (idx<size)
p[idx] += p[idx+size];
__syncthreads();
}
if (idx == 0)
*piest = p[0];
}
int main(void) {
struct timespec start , stop ; // variables for timing
double accum ; // elapsed time variable
const unsigned int blockSize=1024;
dim3 numThreads;
double pi25DT=3.141592653589793238462643;
double x;
double *mypi;
long N = 1000000;
double sum, h;
h = 1.0/(double)N; // For CPU version of loop
numThreads.x = blockSize;
hipMallocManaged(&mypi, sizeof(double));
clock_gettime ( CLOCK_REALTIME ,&start );
PiEstSingleBlock<<<1,numThreads>>>(N, mypi);
hipDeviceSynchronize(); // Cannot get sensible timing without synchronising host and device
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("Pi estimate %.16f error is %.16f", mypi[0],pi25DT-mypi[0]);
printf("\n");
printf("Time to compute mypi is %lf sec.\n",accum);
clock_gettime ( CLOCK_REALTIME ,&start );
sum = 0.0;
for (long i=1; i <= N; i++){
x = h * ((double)i - 0.5);
sum += 4.0/(1.0+x*x);
}
clock_gettime ( CLOCK_REALTIME ,&stop );
accum =( stop.tv_sec - start.tv_sec )+
( stop.tv_nsec - start.tv_nsec )/(double)BILLION ;
printf("CPU pi is %.16f error is %.16f\n",h*sum,pi25DT-h*sum);
printf("Time to compute CPU pi is %lf sec.\n",accum);
} | .text
.file "cupi.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__PiEstSingleBlocklPd # -- Begin function _Z31__device_stub__PiEstSingleBlocklPd
.p2align 4, 0x90
.type _Z31__device_stub__PiEstSingleBlocklPd,@function
_Z31__device_stub__PiEstSingleBlocklPd: # @_Z31__device_stub__PiEstSingleBlocklPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16PiEstSingleBlocklPd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__PiEstSingleBlocklPd, .Lfunc_end0-_Z31__device_stub__PiEstSingleBlocklPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI1_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI1_2:
.quad 0xbfe0000000000000 # double -0.5
.LCPI1_3:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.LCPI1_5:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq $1000000, 112(%rsp) # imm = 0xF4240
movq %rax, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 8(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movq %rsp, %r9
movl $_Z16PiEstSingleBlocklPd, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq %rsp, %rsi
xorl %edi, %edi
callq clock_gettime
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 32(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 40(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movq 24(%rsp), %rax
movsd (%rax), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
movl $10, %edi
callq putchar@PLT
movl $.L.str.2, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
xorpd %xmm6, %xmm6
movl $1, %eax
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_4(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI1_5(%rip), %xmm3 # xmm3 = mem[0],zero
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
xorps %xmm4, %xmm4
cvtsi2sd %rax, %xmm4
addsd %xmm0, %xmm4
mulsd %xmm1, %xmm4
mulsd %xmm4, %xmm4
addsd %xmm2, %xmm4
movapd %xmm3, %xmm5
divsd %xmm4, %xmm5
addsd %xmm5, %xmm6
incq %rax
cmpq $1000001, %rax # imm = 0xF4241
jne .LBB1_3
# %bb.4:
movq %rsp, %rsi
xorl %edi, %edi
movsd %xmm6, 48(%rsp) # 8-byte Spill
callq clock_gettime
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 32(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 40(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
divsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI1_3(%rip), %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movl $.L.str.3, %edi
movb $2, %al
callq printf
movl $.L.str.4, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16PiEstSingleBlocklPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16PiEstSingleBlocklPd,@object # @_Z16PiEstSingleBlocklPd
.section .rodata,"a",@progbits
.globl _Z16PiEstSingleBlocklPd
.p2align 3, 0x0
_Z16PiEstSingleBlocklPd:
.quad _Z31__device_stub__PiEstSingleBlocklPd
.size _Z16PiEstSingleBlocklPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Pi estimate %.16f error is %.16f"
.size .L.str, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time to compute mypi is %lf sec.\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU pi is %.16f error is %.16f\n"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time to compute CPU pi is %lf sec.\n"
.size .L.str.4, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16PiEstSingleBlocklPd"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__PiEstSingleBlocklPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16PiEstSingleBlocklPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16PiEstSingleBlocklPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64.S64 R2, c[0x0][0x160] ; /* 0x0000580000027b12 */
/* 0x000e220000301c00 */
/*0020*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff177624 */
/* 0x000fce00078e00ff */
/*0030*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x001e220000001800 */
/*0040*/ IADD3 R4, R3, 0x300402, RZ ; /* 0x0030040203047810 */
/* 0x000fc80007ffe0ff */
/*0050*/ FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ; /* 0x004004020400780b */
/* 0x000fe40003f0e200 */
/*0060*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000104 */
/*0070*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0080*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*0090*/ DFMA R8, -R2, R6, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c0000000106 */
/*00a0*/ DFMA R4, R6, R8, R6 ; /* 0x000000080604722b */
/* 0x0010620000000006 */
/*00b0*/ @P0 BRA 0x100 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00c0*/ LOP3.LUT R0, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03007812 */
/* 0x000fc800078ec0ff */
/*00d0*/ IADD3 R6, R0, -0x100000, RZ ; /* 0xfff0000000067810 */
/* 0x001fe40007ffe0ff */
/*00e0*/ MOV R0, 0x100 ; /* 0x0000010000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ CALL.REL.NOINC 0x530 ; /* 0x0000043000007944 */
/* 0x002fea0003c00000 */
/*0100*/ S2R R22, SR_TID.X ; /* 0x0000000000167919 */
/* 0x000ea20000002100 */
/*0110*/ BSSY B0, 0x380 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0120*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0130*/ IADD3 R21, R22, 0x1, RZ ; /* 0x0000000116157810 */
/* 0x004fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R21, c[0x0][0x160], PT ; /* 0x0000580015007a0c */
/* 0x000fe40003f04070 */
/*0150*/ SHF.R.S32.HI R20, RZ, 0x1f, R21 ; /* 0x0000001fff147819 */
/* 0x000fc80000011415 */
/*0160*/ ISETP.GT.AND.EX P0, PT, R20, c[0x0][0x164], PT, P0 ; /* 0x0000590014007a0c */
/* 0x000fda0003f04300 */
/*0170*/ @P0 BRA 0x370 ; /* 0x000001f000000947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff137624 */
/* 0x000fe200078e00ff */
/*0190*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*01a0*/ IMAD.MOV.U32 R12, RZ, RZ, R21 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0015 */
/*01b0*/ IADD3 R21, P0, R21, c[0x0][0x0], RZ ; /* 0x0000000015157a10 */
/* 0x000fe20007f1e0ff */
/*01c0*/ IMAD.MOV.U32 R13, RZ, RZ, R20 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0014 */
/*01d0*/ BSSY B1, 0x350 ; /* 0x0000017000017945 */
/* 0x000fe40003800000 */
/*01e0*/ LEA.HI.X.SX32 R20, R19, R20, 0x1, P0 ; /* 0x0000001413147211 */
/* 0x000fe200000f0eff */
/*01f0*/ I2F.F64.S64 R6, R12 ; /* 0x0000000c00067312 */
/* 0x001e220000301c00 */
/*0200*/ ISETP.GT.U32.AND P0, PT, R21, c[0x0][0x160], PT ; /* 0x0000580015007a0c */
/* 0x000fc80003f04070 */
/*0210*/ ISETP.GT.AND.EX P0, PT, R20, c[0x0][0x164], PT, P0 ; /* 0x0000590014007a0c */
/* 0x000fe20003f04300 */
/*0220*/ DADD R6, R6, -0.5 ; /* 0xbfe0000006067429 */
/* 0x001e0c0000000000 */
/*0230*/ DMUL R6, R6, R4 ; /* 0x0000000406067228 */
/* 0x003e0c0000000000 */
/*0240*/ DFMA R8, R6, R6, 1 ; /* 0x3ff000000608742b */
/* 0x0010640000000006 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x001fc800078e00ff */
/*0260*/ MUFU.RCP64H R7, R9 ; /* 0x0000000900077308 */
/* 0x002e240000001800 */
/*0270*/ DFMA R10, -R8, R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000106 */
/*0280*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0290*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x001e0c0000000006 */
/*02a0*/ DFMA R6, -R8, R10, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c000000010a */
/*02b0*/ DFMA R6, R10, R6, R10 ; /* 0x000000060a06722b */
/* 0x001e0c000000000a */
/*02c0*/ DMUL R10, R6, 4 ; /* 0x40100000060a7828 */
/* 0x001e0c0000000000 */
/*02d0*/ DFMA R12, -R8, R10, 4 ; /* 0x40100000080c742b */
/* 0x001e0c000000010a */
/*02e0*/ DFMA R6, R6, R12, R10 ; /* 0x0000000c0606722b */
/* 0x001e14000000000a */
/*02f0*/ FFMA R0, RZ, R9, R7 ; /* 0x00000009ff007223 */
/* 0x001fca0000000007 */
/*0300*/ FSETP.GT.AND P1, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f24200 */
/*0310*/ @P1 BRA 0x340 ; /* 0x0000002000001947 */
/* 0x004fea0003800000 */
/*0320*/ MOV R24, 0x340 ; /* 0x0000034000187802 */
/* 0x000fe40000000f00 */
/*0330*/ CALL.REL.NOINC 0x790 ; /* 0x0000045000007944 */
/* 0x000fea0003c00000 */
/*0340*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0350*/ DADD R2, R6, R2 ; /* 0x0000000006027229 */
/* 0x0000a20000000002 */
/*0360*/ @!P0 BRA 0x1a0 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0390*/ DMUL R2, R4, R2 ; /* 0x0000000204027228 */
/* 0x006e620000000000 */
/*03a0*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc60003f05270 */
/*03b0*/ ISETP.GE.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fc60003f26270 */
/*03c0*/ STS.64 [R22.X8], R2 ; /* 0x0000000216007388 */
/* 0x0023e80000008a00 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03e0*/ @!P1 BRA 0x4c0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.SHL.U32 R0, R22, 0x8, RZ ; /* 0x0000000816007824 */
/* 0x000fe400078e00ff */
/*0400*/ LEA.HI R2, R23, R23, RZ, 0x1 ; /* 0x0000001717027211 */
/* 0x002fc800078f08ff */
/*0410*/ SHF.R.S32.HI R7, RZ, 0x1, R2 ; /* 0x00000001ff077819 */
/* 0x001fc80000011402 */
/*0420*/ ISETP.GE.AND P1, PT, R22, R7, PT ; /* 0x000000071600720c */
/* 0x000fda0003f26270 */
/*0430*/ @!P1 IMAD R4, R7, 0x8, R0 ; /* 0x0000000807049824 */
/* 0x000fe200078e0200 */
/*0440*/ @!P1 LDS.64 R2, [R22.X8] ; /* 0x0000000016029984 */
/* 0x000fea0000008a00 */
/*0450*/ @!P1 LDS.64 R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000a00 */
/*0460*/ @!P1 DADD R2, R2, R4 ; /* 0x0000000002029229 */
/* 0x001e0e0000000004 */
/*0470*/ @!P1 STS.64 [R22.X8], R2 ; /* 0x0000000216009388 */
/* 0x0011e80000008a00 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0490*/ ISETP.GT.AND P1, PT, R23, 0x3, PT ; /* 0x000000031700780c */
/* 0x000fe20003f24270 */
/*04a0*/ IMAD.MOV.U32 R23, RZ, RZ, R7 ; /* 0x000000ffff177224 */
/* 0x000fd800078e0007 */
/*04b0*/ @P1 BRA 0x400 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*04c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04d0*/ LDS.64 R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x002e620000000a00 */
/*04e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*04f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0510*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ DSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7ff000000200742a */
/* 0x000e1c0003f0c200 */
/*0540*/ @P0 BRA 0x740 ; /* 0x000001f000000947 */
/* 0x001fea0003800000 */
/*0550*/ LOP3.LUT R7, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03077812 */
/* 0x000fc800078ec0ff */
/*0560*/ IADD3 R4, R7, -0x1, RZ ; /* 0xffffffff07047810 */
/* 0x000fc80007ffe0ff */
/*0570*/ ISETP.GE.U32.AND P0, PT, R4, 0x7fefffff, PT ; /* 0x7fefffff0400780c */
/* 0x000fda0003f06070 */
/*0580*/ @P0 LOP3.LUT R5, R3, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000003050812 */
/* 0x000fe200078e3cff */
/*0590*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe200078e00ff */
/*05a0*/ @P0 BRA 0x760 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R7, 0x1000001, PT ; /* 0x010000010700780c */
/* 0x000fda0003f06070 */
/*05c0*/ @!P0 BRA 0x6a0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R5, R3, -0x3fe00000, RZ ; /* 0xc020000003057810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0002 */
/*05f0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x000e260000001800 */
/*0600*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0610*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0620*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0630*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000108 */
/*0640*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e0c0000000008 */
/*0650*/ DMUL R6, R6, 2.2250738585072013831e-308 ; /* 0x0010000006067828 */
/* 0x001e0c0000000000 */
/*0660*/ DFMA R2, -R2, R6, 1 ; /* 0x3ff000000202742b */
/* 0x001e0c0000000106 */
/*0670*/ DFMA R2, R2, R2, R2 ; /* 0x000000020202722b */
/* 0x001e0c0000000002 */
/*0680*/ DFMA R4, R6, R2, R6 ; /* 0x000000020604722b */
/* 0x0010620000000006 */
/*0690*/ BRA 0x760 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*06a0*/ DMUL R2, R2, 8.11296384146066816958e+31 ; /* 0x4690000002027828 */
/* 0x000e220000000000 */
/*06b0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0006 */
/*06c0*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x001e240000001800 */
/*06d0*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000104 */
/*06e0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*06f0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*0700*/ DFMA R4, -R2, R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000106 */
/*0710*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e0c0000000006 */
/*0720*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x001e220000000000 */
/*0730*/ BRA 0x760 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT R5, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000003057812 */
/* 0x000fe200078efcff */
/*0750*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0760*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*0770*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0780*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff87002007950 */
/* 0x000fea0003c3ffff */
/*0790*/ FSETP.GEU.AND P1, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f2e200 */
/*07a0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*07b0*/ LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09067812 */
/* 0x040fe200078ec0ff */
/*07c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x40100000 ; /* 0x40100000ff007424 */
/* 0x000fe200078e00ff */
/*07d0*/ LOP3.LUT R25, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009197812 */
/* 0x000fe200078ec0ff */
/*07e0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff127424 */
/* 0x000fe200078e00ff */
/*07f0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0800*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0810*/ ISETP.LE.U32.AND P2, PT, R25, 0x40100000, PT ; /* 0x401000001900780c */
/* 0x000fe20003f43070 */
/*0820*/ BSSY B2, 0xc30 ; /* 0x0000040000027945 */
/* 0x000fe20003800000 */
/*0830*/ IADD3 R16, R0, -0x1, RZ ; /* 0xffffffff00107810 */
/* 0x000fc60007ffe0ff */
/*0840*/ @!P1 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008069828 */
/* 0x000e0c0000000000 */
/*0850*/ MUFU.RCP64H R13, R7 ; /* 0x00000007000d7308 */
/* 0x001e280000001800 */
/*0860*/ @!P1 LOP3.LUT R25, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007199812 */
/* 0x000fe400078ec0ff */
/*0870*/ ISETP.GT.U32.AND P1, PT, R16, 0x7feffffe, PT ; /* 0x7feffffe1000780c */
/* 0x000fe40003f24070 */
/*0880*/ IADD3 R26, R25, -0x1, RZ ; /* 0xffffffff191a7810 */
/* 0x000fc80007ffe0ff */
/*0890*/ ISETP.GT.U32.OR P1, PT, R26, 0x7feffffe, P1 ; /* 0x7feffffe1a00780c */
/* 0x000fe20000f24470 */
/*08a0*/ DFMA R10, R12, -R6, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c0000000806 */
/*08b0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*08c0*/ DFMA R12, R12, R10, R12 ; /* 0x0000000a0c0c722b */
/* 0x001064000000000c */
/*08d0*/ SEL R11, R18, 0x63400000, !P2 ; /* 0x63400000120b7807 */
/* 0x001fe20005000000 */
/*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*08f0*/ DFMA R14, R12, -R6, 1 ; /* 0x3ff000000c0e742b */
/* 0x002e0c0000000806 */
/*0900*/ DFMA R12, R12, R14, R12 ; /* 0x0000000e0c0c722b */
/* 0x001e0c000000000c */
/*0910*/ DMUL R14, R12, R10 ; /* 0x0000000a0c0e7228 */
/* 0x001e0c0000000000 */
/*0920*/ DFMA R16, R14, -R6, R10 ; /* 0x800000060e10722b */
/* 0x001e0c000000000a */
/*0930*/ DFMA R16, R12, R16, R14 ; /* 0x000000100c10722b */
/* 0x001062000000000e */
/*0940*/ @P1 BRA 0xb10 ; /* 0x000001c000001947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT R12, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090c7812 */
/* 0x001fe200078ec0ff */
/*0960*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e00ff */
/*0970*/ IADD3 R0, -R12.reuse, 0x40100000, RZ ; /* 0x401000000c007810 */
/* 0x040fe40007ffe1ff */
/*0980*/ ISETP.LE.U32.AND P1, PT, R12, 0x40100000, PT ; /* 0x401000000c00780c */
/* 0x000fe40003f23070 */
/*0990*/ IMNMX R0, R0, -0x46a00000, !PT ; /* 0xb960000000007817 */
/* 0x000fe40007800200 */
/*09a0*/ SEL R13, R18, 0x63400000, !P1 ; /* 0x63400000120d7807 */
/* 0x000fe40004800000 */
/*09b0*/ IMNMX R0, R0, 0x46a00000, PT ; /* 0x46a0000000007817 */
/* 0x000fca0003800200 */
/*09c0*/ IMAD.IADD R0, R0, 0x1, -R13 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a0d */
/*09d0*/ IADD3 R15, R0, 0x7fe00000, RZ ; /* 0x7fe00000000f7810 */
/* 0x000fcc0007ffe0ff */
/*09e0*/ DMUL R12, R16, R14 ; /* 0x0000000e100c7228 */
/* 0x002e140000000000 */
/*09f0*/ FSETP.GTU.AND P1, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f2c200 */
/*0a00*/ @P1 BRA 0xc20 ; /* 0x0000021000001947 */
/* 0x000fea0003800000 */
/*0a10*/ DFMA R6, R16, -R6, R10 ; /* 0x800000061006722b */
/* 0x000e22000000000a */
/*0a20*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd200078e00ff */
/*0a30*/ FSETP.NEU.AND P1, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f2d000 */
/*0a40*/ LOP3.LUT R9, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007097812 */
/* 0x000fc800078e4809 */
/*0a50*/ LOP3.LUT R15, R9, R15, RZ, 0xfc, !PT ; /* 0x0000000f090f7212 */
/* 0x000fce00078efcff */
/*0a60*/ @!P1 BRA 0xc20 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0a70*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a00 */
/*0a80*/ DMUL.RP R14, R16, R14 ; /* 0x0000000e100e7228 */
/* 0x000e220000008000 */
/*0a90*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fcc00078e00ff */
/*0aa0*/ DFMA R6, R12, -R6, R16 ; /* 0x800000060c06722b */
/* 0x000e460000000010 */
/*0ab0*/ LOP3.LUT R9, R15, R9, RZ, 0x3c, !PT ; /* 0x000000090f097212 */
/* 0x001fc600078e3cff */
/*0ac0*/ IADD3 R6, -R0, -0x43300000, RZ ; /* 0xbcd0000000067810 */
/* 0x002fc80007ffe1ff */
/*0ad0*/ FSETP.NEU.AND P1, PT, |R7|, R6, PT ; /* 0x000000060700720b */
/* 0x000fc80003f2d200 */
/*0ae0*/ FSEL R12, R14, R12, !P1 ; /* 0x0000000c0e0c7208 */
/* 0x000fe40004800000 */
/*0af0*/ FSEL R13, R9, R13, !P1 ; /* 0x0000000d090d7208 */
/* 0x000fe20004800000 */
/*0b00*/ BRA 0xc20 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0b10*/ DSETP.NAN.AND P1, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f28000 */
/*0b20*/ @P1 BRA 0xc00 ; /* 0x000000d000001947 */
/* 0x004fea0003800000 */
/*0b30*/ ISETP.NE.AND P1, PT, R0, R25, PT ; /* 0x000000190000720c */
/* 0x000fe20003f25270 */
/*0b40*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x001fe400078e00ff */
/*0b50*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0b60*/ @!P1 BRA 0xc20 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0b70*/ ISETP.NE.AND P1, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fe40003f25270 */
/*0b80*/ LOP3.LUT R8, R9, 0x40100000, RZ, 0x3c, !PT ; /* 0x4010000009087812 */
/* 0x000fe400078e3cff */
/*0b90*/ ISETP.EQ.OR P1, PT, R25, RZ, !P1 ; /* 0x000000ff1900720c */
/* 0x000fe40004f22670 */
/*0ba0*/ LOP3.LUT R13, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000080d7812 */
/* 0x000fd600078ec0ff */
/*0bb0*/ @P1 LOP3.LUT R0, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d001812 */
/* 0x000fe200078efcff */
/*0bc0*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c9224 */
/* 0x000fe400078e00ff */
/*0bd0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c1224 */
/* 0x000fe400078e00ff */
/*0be0*/ @P1 IMAD.MOV.U32 R13, RZ, RZ, R0 ; /* 0x000000ffff0d1224 */
/* 0x000fe200078e0000 */
/*0bf0*/ BRA 0xc20 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c00*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x001fe200078efcff */
/*0c10*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0c20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c30*/ IMAD.MOV.U32 R25, RZ, RZ, 0x0 ; /* 0x00000000ff197424 */
/* 0x000fe400078e00ff */
/*0c40*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000c */
/*0c50*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0c60*/ RET.REL.NODEC R24 0x0 ; /* 0xfffff39018007950 */
/* 0x000fec0003c3ffff */
/*0c70*/ BRA 0xc70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16PiEstSingleBlocklPd
.globl _Z16PiEstSingleBlocklPd
.p2align 8
.type _Z16PiEstSingleBlocklPd,@function
_Z16PiEstSingleBlocklPd:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x1c
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[1:2], s3
v_cvt_f64_u32_e32 v[3:4], s2
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], 32
v_add_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[3:4], null, v[1:2], v[1:2], 1.0
v_rcp_f64_e32 v[5:6], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_div_scale_f64 v[7:8], vcc_lo, 1.0, v[1:2], 1.0
v_mul_f64 v[9:10], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], -v[3:4], v[9:10], v[7:8]
v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[9:10]
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[1:2], v[3:4], v[1:2], 1.0
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, 1, v0
v_cmpx_ge_i64_e64 s[2:3], v[3:4]
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_mov_b32 s7, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s6, s7
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_cvt_f64_i32_e32 v[7:8], v4
v_cvt_f64_u32_e32 v[9:10], v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[7:8], v[7:8], 32
v_add_f64 v[7:8], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], -0.5
v_mul_f64 v[7:8], v[1:2], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[7:8], 1.0
v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], 4.0
v_div_scale_f64 v[15:16], vcc_lo, 4.0, v[7:8], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[15:16], v[11:12]
v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
v_add_co_u32 v3, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[7:8], v[9:10], v[7:8], 4.0
v_add_f64 v[5:6], v[5:6], v[7:8]
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s5
v_mul_f64 v[2:3], v[1:2], v[5:6]
v_lshlrev_b32_e32 v1, 3, v0
s_cmp_lt_u32 s4, 2
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s2, s4, 1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.LBB0_7:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s2, v0, 3
ds_load_b64 v[2:3], v2
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_branch .LBB0_6
.LBB0_9:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16PiEstSingleBlocklPd
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16PiEstSingleBlocklPd, .Lfunc_end0-_Z16PiEstSingleBlocklPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16PiEstSingleBlocklPd
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z16PiEstSingleBlocklPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001481ce_00000000-6_cupi.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1fd
.type _Z1fd, @function
_Z1fd:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z1fd, .-_Z1fd
.globl _Z37__device_stub__Z16PiEstSingleBlocklPdlPd
.type _Z37__device_stub__Z16PiEstSingleBlocklPdlPd, @function
_Z37__device_stub__Z16PiEstSingleBlocklPdlPd:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16PiEstSingleBlocklPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z37__device_stub__Z16PiEstSingleBlocklPdlPd, .-_Z37__device_stub__Z16PiEstSingleBlocklPdlPd
.globl _Z16PiEstSingleBlocklPd
.type _Z16PiEstSingleBlocklPd, @function
_Z16PiEstSingleBlocklPd:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16PiEstSingleBlocklPdlPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z16PiEstSingleBlocklPd, .-_Z16PiEstSingleBlocklPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Pi estimate %.16f error is %.16f"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Time to compute mypi is %lf sec.\n"
.align 8
.LC10:
.string "CPU pi is %.16f error is %.16f\n"
.align 8
.LC11:
.string "Time to compute CPU pi is %lf sec.\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1024, 36(%rsp)
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
call cudaDeviceSynchronize@PLT
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rsp)
movq 24(%rsp), %rax
movsd (%rax), %xmm0
movsd .LC2(%rip), %xmm1
subsd %xmm0, %xmm1
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $1, %eax
movq $0x000000000, (%rsp)
movsd .LC6(%rip), %xmm5
movsd .LC7(%rip), %xmm4
movsd .LC8(%rip), %xmm3
movsd .LC9(%rip), %xmm2
.L15:
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd %xmm5, %xmm0
mulsd %xmm4, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm3, %xmm0
movapd %xmm2, %xmm1
divsd %xmm0, %xmm1
addsd (%rsp), %xmm1
movsd %xmm1, (%rsp)
addq $1, %rax
cmpq $1000001, %rax
jne .L15
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movsd (%rsp), %xmm7
mulsd .LC7(%rip), %xmm7
movapd %xmm7, %xmm0
movsd .LC2(%rip), %xmm1
subsd %xmm7, %xmm1
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rsi
movl $1000000, %edi
call _Z37__device_stub__Z16PiEstSingleBlocklPdlPd
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z16PiEstSingleBlocklPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z16PiEstSingleBlocklPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1104006501
.align 8
.LC2:
.long 1413754136
.long 1074340347
.align 8
.LC6:
.long 0
.long 1071644672
.align 8
.LC7:
.long -1598689907
.long 1051772663
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC9:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cupi.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__PiEstSingleBlocklPd # -- Begin function _Z31__device_stub__PiEstSingleBlocklPd
.p2align 4, 0x90
.type _Z31__device_stub__PiEstSingleBlocklPd,@function
_Z31__device_stub__PiEstSingleBlocklPd: # @_Z31__device_stub__PiEstSingleBlocklPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16PiEstSingleBlocklPd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__PiEstSingleBlocklPd, .Lfunc_end0-_Z31__device_stub__PiEstSingleBlocklPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI1_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI1_2:
.quad 0xbfe0000000000000 # double -0.5
.LCPI1_3:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.LCPI1_5:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq $1000000, 112(%rsp) # imm = 0xF4240
movq %rax, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 8(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movq %rsp, %r9
movl $_Z16PiEstSingleBlocklPd, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq %rsp, %rsi
xorl %edi, %edi
callq clock_gettime
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 32(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 40(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movq 24(%rsp), %rax
movsd (%rax), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
movl $10, %edi
callq putchar@PLT
movl $.L.str.2, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
xorpd %xmm6, %xmm6
movl $1, %eax
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_4(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI1_5(%rip), %xmm3 # xmm3 = mem[0],zero
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
xorps %xmm4, %xmm4
cvtsi2sd %rax, %xmm4
addsd %xmm0, %xmm4
mulsd %xmm1, %xmm4
mulsd %xmm4, %xmm4
addsd %xmm2, %xmm4
movapd %xmm3, %xmm5
divsd %xmm4, %xmm5
addsd %xmm5, %xmm6
incq %rax
cmpq $1000001, %rax # imm = 0xF4241
jne .LBB1_3
# %bb.4:
movq %rsp, %rsi
xorl %edi, %edi
movsd %xmm6, 48(%rsp) # 8-byte Spill
callq clock_gettime
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 32(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 40(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
divsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI1_3(%rip), %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movl $.L.str.3, %edi
movb $2, %al
callq printf
movl $.L.str.4, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16PiEstSingleBlocklPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16PiEstSingleBlocklPd,@object # @_Z16PiEstSingleBlocklPd
.section .rodata,"a",@progbits
.globl _Z16PiEstSingleBlocklPd
.p2align 3, 0x0
_Z16PiEstSingleBlocklPd:
.quad _Z31__device_stub__PiEstSingleBlocklPd
.size _Z16PiEstSingleBlocklPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Pi estimate %.16f error is %.16f"
.size .L.str, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time to compute mypi is %lf sec.\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU pi is %.16f error is %.16f\n"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time to compute CPU pi is %lf sec.\n"
.size .L.str.4, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16PiEstSingleBlocklPd"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__PiEstSingleBlocklPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16PiEstSingleBlocklPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /// Convolution 1D Parallel.
///
/// Implementation of a 1-dimensional convolution in CUDA, with a placeholding
/// mask and shared memory usage.
///
/// Authors:
/// Lucas Oliveira David.
/// Paulo Finardi.
///
/// Note (in Brazilian Portuguese):
/// Como nosso trabalho final e' relacionado `a redes convolucionais,
/// possuindo um operador convolucao implementado em CUDA, ambos os alunos
/// fizeram esta ultima tarefa juntos.
///
/// ___________________________________________________________________________
/// | Performance Analysis |
/// ___________________________________________________________________________
/// | input | CPU_Serial | GPU_NOShared | GPU_Shared | Speedup (CPU/GPUSM) |
/// ___________________________________________________________________________
/// | arq1.in | 0.080165 | 0.110547 | 0.104868 | 0.7644371972384331 |
/// ___________________________________________________________________________
/// | arq2.in | 9.934354 | 8.289333 | 8.235395 | 1.2062996371151598 |
/// ___________________________________________________________________________
/// | arq3.in | 100.419526 | 96.001373 | 91.386422 | 1.0988451435378443 |
/// ___________________________________________________________________________
///
/// License: MIT (c) 2016
///
#include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#include <math.h>
#include<cuda_runtime_api.h>
#define MASK_WIDTH 101
#define OUT_TILE_WIDTH 512
__global__ void _k_conv1d(int *N, int *M, int *out, int n)
{
__shared__ int mask_s[MASK_WIDTH];
__shared__ int N_s[OUT_TILE_WIDTH + MASK_WIDTH - 1];
int i_out = blockIdx.x*OUT_TILE_WIDTH + threadIdx.x,
i_in = i_out - (MASK_WIDTH -1) / 2,
i_shared = threadIdx.x;
while (i_shared < OUT_TILE_WIDTH + MASK_WIDTH -1)
{
// Loads N into the shared memory.
if (i_in > -1 && i_in < n)
N_s[i_shared] = N[i_in];
else
N_s[i_shared] = 0;
i_in += OUT_TILE_WIDTH;
i_shared += OUT_TILE_WIDTH;
}
i_shared = threadIdx.x;
while (i_shared < MASK_WIDTH)
{
mask_s[i_shared] = M[i_shared];
i_shared += OUT_TILE_WIDTH;
}
__syncthreads();
if (i_out < n)
{
int output = 0;
for(int j = 0; j < MASK_WIDTH; j++)
output += N_s[threadIdx.x + j] * mask_s[j];
out[i_out] = output;
}
}
int main()
{
int n;
scanf("%d",&n);
int size = n*sizeof(int);
int *input = (int *)malloc(size);
int *mask = (int *)malloc(sizeof(int)*MASK_WIDTH);
int *output = (int *)malloc(size);
int *d_input;
int *d_mask;
int *d_output;
cudaMalloc((void **)&d_input, size);
cudaMalloc((void **)&d_mask, sizeof(int)*MASK_WIDTH);
cudaMalloc((void **)&d_output, size);
for(int i = 0; i < n; i++)
scanf("%d", &input[i]);
for(int i = 0; i < MASK_WIDTH; i++)
mask[i] = i;
cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_mask, mask, sizeof(int)*MASK_WIDTH, cudaMemcpyHostToDevice);
dim3 dimGrid((n-1) / OUT_TILE_WIDTH + 1, 1, 1);
dim3 dimBlock(OUT_TILE_WIDTH, 1, 1);
_k_conv1d<<<dimGrid, dimBlock>>>(d_input, d_mask, d_output, n);
cudaDeviceSynchronize();
cudaMemcpy(output, d_output, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < n; i++)
printf("%d ", output[i]);
printf("\n");
cudaFree(d_input);
cudaFree(d_mask);
free(input);
free(output);
free(mask);
return 0;
} | .file "tmpxft_00102c39_00000000-6_convolution1D_parallel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9_k_conv1dPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
.globl _Z9_k_conv1dPiS_S_i
.type _Z9_k_conv1dPiS_S_i, @function
_Z9_k_conv1dPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9_k_conv1dPiS_S_i, .-_Z9_k_conv1dPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 20(%rsp), %eax
leal 0(,%rax,4), %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, 8(%rsp)
movl $404, %edi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $404, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
cmpl $0, 20(%rsp)
jle .L12
movl $0, %ebp
leaq .LC0(%rip), %r15
.L13:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
cmpl %ebp, 20(%rsp)
jg .L13
.L12:
movl $0, %eax
.L14:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $101, %rax
jne .L14
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $404, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rsp), %edx
leal 510(%rdx), %eax
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $0, 20(%rsp)
jle .L16
movl $0, %ebp
leaq .LC1(%rip), %r12
.L17:
movl 0(%r13,%rbp,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpl %ebp, 20(%rsp)
jg .L17
.L16:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl 20(%rsp), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9_k_conv1dPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9_k_conv1dPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /// Convolution 1D Parallel.
///
/// Implementation of a 1-dimensional convolution in CUDA, with a placeholding
/// mask and shared memory usage.
///
/// Authors:
/// Lucas Oliveira David.
/// Paulo Finardi.
///
/// Note (in Brazilian Portuguese):
/// Como nosso trabalho final e' relacionado `a redes convolucionais,
/// possuindo um operador convolucao implementado em CUDA, ambos os alunos
/// fizeram esta ultima tarefa juntos.
///
/// ___________________________________________________________________________
/// | Performance Analysis |
/// ___________________________________________________________________________
/// | input | CPU_Serial | GPU_NOShared | GPU_Shared | Speedup (CPU/GPUSM) |
/// ___________________________________________________________________________
/// | arq1.in | 0.080165 | 0.110547 | 0.104868 | 0.7644371972384331 |
/// ___________________________________________________________________________
/// | arq2.in | 9.934354 | 8.289333 | 8.235395 | 1.2062996371151598 |
/// ___________________________________________________________________________
/// | arq3.in | 100.419526 | 96.001373 | 91.386422 | 1.0988451435378443 |
/// ___________________________________________________________________________
///
/// License: MIT (c) 2016
///
#include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#include <math.h>
#include<cuda_runtime_api.h>
#define MASK_WIDTH 101
#define OUT_TILE_WIDTH 512
__global__ void _k_conv1d(int *N, int *M, int *out, int n)
{
__shared__ int mask_s[MASK_WIDTH];
__shared__ int N_s[OUT_TILE_WIDTH + MASK_WIDTH - 1];
int i_out = blockIdx.x*OUT_TILE_WIDTH + threadIdx.x,
i_in = i_out - (MASK_WIDTH -1) / 2,
i_shared = threadIdx.x;
while (i_shared < OUT_TILE_WIDTH + MASK_WIDTH -1)
{
// Loads N into the shared memory.
if (i_in > -1 && i_in < n)
N_s[i_shared] = N[i_in];
else
N_s[i_shared] = 0;
i_in += OUT_TILE_WIDTH;
i_shared += OUT_TILE_WIDTH;
}
i_shared = threadIdx.x;
while (i_shared < MASK_WIDTH)
{
mask_s[i_shared] = M[i_shared];
i_shared += OUT_TILE_WIDTH;
}
__syncthreads();
if (i_out < n)
{
int output = 0;
for(int j = 0; j < MASK_WIDTH; j++)
output += N_s[threadIdx.x + j] * mask_s[j];
out[i_out] = output;
}
}
int main()
{
int n;
scanf("%d",&n);
int size = n*sizeof(int);
int *input = (int *)malloc(size);
int *mask = (int *)malloc(sizeof(int)*MASK_WIDTH);
int *output = (int *)malloc(size);
int *d_input;
int *d_mask;
int *d_output;
cudaMalloc((void **)&d_input, size);
cudaMalloc((void **)&d_mask, sizeof(int)*MASK_WIDTH);
cudaMalloc((void **)&d_output, size);
for(int i = 0; i < n; i++)
scanf("%d", &input[i]);
for(int i = 0; i < MASK_WIDTH; i++)
mask[i] = i;
cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_mask, mask, sizeof(int)*MASK_WIDTH, cudaMemcpyHostToDevice);
dim3 dimGrid((n-1) / OUT_TILE_WIDTH + 1, 1, 1);
dim3 dimBlock(OUT_TILE_WIDTH, 1, 1);
_k_conv1d<<<dimGrid, dimBlock>>>(d_input, d_mask, d_output, n);
cudaDeviceSynchronize();
cudaMemcpy(output, d_output, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < n; i++)
printf("%d ", output[i]);
printf("\n");
cudaFree(d_input);
cudaFree(d_mask);
free(input);
free(output);
free(mask);
return 0;
} | /// Convolution 1D Parallel.
///
/// Implementation of a 1-dimensional convolution in CUDA, with a placeholding
/// mask and shared memory usage.
///
/// Authors:
/// Lucas Oliveira David.
/// Paulo Finardi.
///
/// Note (in Brazilian Portuguese):
/// Como nosso trabalho final e' relacionado `a redes convolucionais,
/// possuindo um operador convolucao implementado em CUDA, ambos os alunos
/// fizeram esta ultima tarefa juntos.
///
/// ___________________________________________________________________________
/// | Performance Analysis |
/// ___________________________________________________________________________
/// | input | CPU_Serial | GPU_NOShared | GPU_Shared | Speedup (CPU/GPUSM) |
/// ___________________________________________________________________________
/// | arq1.in | 0.080165 | 0.110547 | 0.104868 | 0.7644371972384331 |
/// ___________________________________________________________________________
/// | arq2.in | 9.934354 | 8.289333 | 8.235395 | 1.2062996371151598 |
/// ___________________________________________________________________________
/// | arq3.in | 100.419526 | 96.001373 | 91.386422 | 1.0988451435378443 |
/// ___________________________________________________________________________
///
/// License: MIT (c) 2016
///
#include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include <math.h>
#include<hip/hip_runtime_api.h>
#define MASK_WIDTH 101
#define OUT_TILE_WIDTH 512
__global__ void _k_conv1d(int *N, int *M, int *out, int n)
{
__shared__ int mask_s[MASK_WIDTH];
__shared__ int N_s[OUT_TILE_WIDTH + MASK_WIDTH - 1];
int i_out = blockIdx.x*OUT_TILE_WIDTH + threadIdx.x,
i_in = i_out - (MASK_WIDTH -1) / 2,
i_shared = threadIdx.x;
while (i_shared < OUT_TILE_WIDTH + MASK_WIDTH -1)
{
// Loads N into the shared memory.
if (i_in > -1 && i_in < n)
N_s[i_shared] = N[i_in];
else
N_s[i_shared] = 0;
i_in += OUT_TILE_WIDTH;
i_shared += OUT_TILE_WIDTH;
}
i_shared = threadIdx.x;
while (i_shared < MASK_WIDTH)
{
mask_s[i_shared] = M[i_shared];
i_shared += OUT_TILE_WIDTH;
}
__syncthreads();
if (i_out < n)
{
int output = 0;
for(int j = 0; j < MASK_WIDTH; j++)
output += N_s[threadIdx.x + j] * mask_s[j];
out[i_out] = output;
}
}
int main()
{
int n;
scanf("%d",&n);
int size = n*sizeof(int);
int *input = (int *)malloc(size);
int *mask = (int *)malloc(sizeof(int)*MASK_WIDTH);
int *output = (int *)malloc(size);
int *d_input;
int *d_mask;
int *d_output;
hipMalloc((void **)&d_input, size);
hipMalloc((void **)&d_mask, sizeof(int)*MASK_WIDTH);
hipMalloc((void **)&d_output, size);
for(int i = 0; i < n; i++)
scanf("%d", &input[i]);
for(int i = 0; i < MASK_WIDTH; i++)
mask[i] = i;
hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
hipMemcpy(d_mask, mask, sizeof(int)*MASK_WIDTH, hipMemcpyHostToDevice);
dim3 dimGrid((n-1) / OUT_TILE_WIDTH + 1, 1, 1);
dim3 dimBlock(OUT_TILE_WIDTH, 1, 1);
_k_conv1d<<<dimGrid, dimBlock>>>(d_input, d_mask, d_output, n);
hipDeviceSynchronize();
hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
for(int i = 0; i < n; i++)
printf("%d ", output[i]);
printf("\n");
hipFree(d_input);
hipFree(d_mask);
free(input);
free(output);
free(mask);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /// Convolution 1D Parallel.
///
/// Implementation of a 1-dimensional convolution in CUDA, with a placeholding
/// mask and shared memory usage.
///
/// Authors:
/// Lucas Oliveira David.
/// Paulo Finardi.
///
/// Note (in Brazilian Portuguese):
/// Como nosso trabalho final e' relacionado `a redes convolucionais,
/// possuindo um operador convolucao implementado em CUDA, ambos os alunos
/// fizeram esta ultima tarefa juntos.
///
/// ___________________________________________________________________________
/// | Performance Analysis |
/// ___________________________________________________________________________
/// | input | CPU_Serial | GPU_NOShared | GPU_Shared | Speedup (CPU/GPUSM) |
/// ___________________________________________________________________________
/// | arq1.in | 0.080165 | 0.110547 | 0.104868 | 0.7644371972384331 |
/// ___________________________________________________________________________
/// | arq2.in | 9.934354 | 8.289333 | 8.235395 | 1.2062996371151598 |
/// ___________________________________________________________________________
/// | arq3.in | 100.419526 | 96.001373 | 91.386422 | 1.0988451435378443 |
/// ___________________________________________________________________________
///
/// License: MIT (c) 2016
///
#include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include <math.h>
#include<hip/hip_runtime_api.h>
#define MASK_WIDTH 101
#define OUT_TILE_WIDTH 512
__global__ void _k_conv1d(int *N, int *M, int *out, int n)
{
__shared__ int mask_s[MASK_WIDTH];
__shared__ int N_s[OUT_TILE_WIDTH + MASK_WIDTH - 1];
int i_out = blockIdx.x*OUT_TILE_WIDTH + threadIdx.x,
i_in = i_out - (MASK_WIDTH -1) / 2,
i_shared = threadIdx.x;
while (i_shared < OUT_TILE_WIDTH + MASK_WIDTH -1)
{
// Loads N into the shared memory.
if (i_in > -1 && i_in < n)
N_s[i_shared] = N[i_in];
else
N_s[i_shared] = 0;
i_in += OUT_TILE_WIDTH;
i_shared += OUT_TILE_WIDTH;
}
i_shared = threadIdx.x;
while (i_shared < MASK_WIDTH)
{
mask_s[i_shared] = M[i_shared];
i_shared += OUT_TILE_WIDTH;
}
__syncthreads();
if (i_out < n)
{
int output = 0;
for(int j = 0; j < MASK_WIDTH; j++)
output += N_s[threadIdx.x + j] * mask_s[j];
out[i_out] = output;
}
}
int main()
{
int n;
scanf("%d",&n);
int size = n*sizeof(int);
int *input = (int *)malloc(size);
int *mask = (int *)malloc(sizeof(int)*MASK_WIDTH);
int *output = (int *)malloc(size);
int *d_input;
int *d_mask;
int *d_output;
hipMalloc((void **)&d_input, size);
hipMalloc((void **)&d_mask, sizeof(int)*MASK_WIDTH);
hipMalloc((void **)&d_output, size);
for(int i = 0; i < n; i++)
scanf("%d", &input[i]);
for(int i = 0; i < MASK_WIDTH; i++)
mask[i] = i;
hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
hipMemcpy(d_mask, mask, sizeof(int)*MASK_WIDTH, hipMemcpyHostToDevice);
dim3 dimGrid((n-1) / OUT_TILE_WIDTH + 1, 1, 1);
dim3 dimBlock(OUT_TILE_WIDTH, 1, 1);
_k_conv1d<<<dimGrid, dimBlock>>>(d_input, d_mask, d_output, n);
hipDeviceSynchronize();
hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
for(int i = 0; i < n; i++)
printf("%d ", output[i]);
printf("\n");
hipFree(d_input);
hipFree(d_mask);
free(input);
free(output);
free(mask);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9_k_conv1dPiS_S_i
.globl _Z9_k_conv1dPiS_S_i
.p2align 8
.type _Z9_k_conv1dPiS_S_i,@function
_Z9_k_conv1dPiS_S_i:
s_load_b32 s3, s[0:1], 0x18
s_lshl_b32 s6, s15, 9
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e32 0x264, v0
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
v_add_nc_u32_e32 v4, 0xfffffe00, v0
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v4, 0x200, v4
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
v_add_nc_u32_e32 v3, 0x800, v3
v_cmp_lt_u32_e32 vcc_lo, 0x63, v4
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v1, s6, v4, 0x1ce
v_mov_b32_e32 v5, 0
v_cmp_lt_i32_e32 vcc_lo, -1, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, vcc_lo, s2
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x65, v0
s_cbranch_execz .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2 offset:2448
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, s6, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_11
v_lshlrev_b32_e32 v2, 2, v0
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
.LBB0_9:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v4, s2 :: v_dual_add_nc_u32 v3, s2, v2
s_add_i32 s2, s2, 4
ds_load_b32 v5, v3
ds_load_b32 v6, v4 offset:2448
s_cmpk_eq_i32 s2, 0x194
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v6, v5, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_cbranch_scc0 .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9_k_conv1dPiS_S_i
.amdhsa_group_segment_fixed_size 2852
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9_k_conv1dPiS_S_i, .Lfunc_end0-_Z9_k_conv1dPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2852
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9_k_conv1dPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9_k_conv1dPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /// Convolution 1D Parallel.
///
/// Implementation of a 1-dimensional convolution in CUDA, with a placeholding
/// mask and shared memory usage.
///
/// Authors:
/// Lucas Oliveira David.
/// Paulo Finardi.
///
/// Note (in Brazilian Portuguese):
/// Como nosso trabalho final e' relacionado `a redes convolucionais,
/// possuindo um operador convolucao implementado em CUDA, ambos os alunos
/// fizeram esta ultima tarefa juntos.
///
/// ___________________________________________________________________________
/// | Performance Analysis |
/// ___________________________________________________________________________
/// | input | CPU_Serial | GPU_NOShared | GPU_Shared | Speedup (CPU/GPUSM) |
/// ___________________________________________________________________________
/// | arq1.in | 0.080165 | 0.110547 | 0.104868 | 0.7644371972384331 |
/// ___________________________________________________________________________
/// | arq2.in | 9.934354 | 8.289333 | 8.235395 | 1.2062996371151598 |
/// ___________________________________________________________________________
/// | arq3.in | 100.419526 | 96.001373 | 91.386422 | 1.0988451435378443 |
/// ___________________________________________________________________________
///
/// License: MIT (c) 2016
///
#include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include <math.h>
#include<hip/hip_runtime_api.h>
#define MASK_WIDTH 101
#define OUT_TILE_WIDTH 512
__global__ void _k_conv1d(int *N, int *M, int *out, int n)
{
__shared__ int mask_s[MASK_WIDTH];
__shared__ int N_s[OUT_TILE_WIDTH + MASK_WIDTH - 1];
int i_out = blockIdx.x*OUT_TILE_WIDTH + threadIdx.x,
i_in = i_out - (MASK_WIDTH -1) / 2,
i_shared = threadIdx.x;
while (i_shared < OUT_TILE_WIDTH + MASK_WIDTH -1)
{
// Loads N into the shared memory.
if (i_in > -1 && i_in < n)
N_s[i_shared] = N[i_in];
else
N_s[i_shared] = 0;
i_in += OUT_TILE_WIDTH;
i_shared += OUT_TILE_WIDTH;
}
i_shared = threadIdx.x;
while (i_shared < MASK_WIDTH)
{
mask_s[i_shared] = M[i_shared];
i_shared += OUT_TILE_WIDTH;
}
__syncthreads();
if (i_out < n)
{
int output = 0;
for(int j = 0; j < MASK_WIDTH; j++)
output += N_s[threadIdx.x + j] * mask_s[j];
out[i_out] = output;
}
}
int main()
{
int n;
scanf("%d",&n);
int size = n*sizeof(int);
int *input = (int *)malloc(size);
int *mask = (int *)malloc(sizeof(int)*MASK_WIDTH);
int *output = (int *)malloc(size);
int *d_input;
int *d_mask;
int *d_output;
hipMalloc((void **)&d_input, size);
hipMalloc((void **)&d_mask, sizeof(int)*MASK_WIDTH);
hipMalloc((void **)&d_output, size);
for(int i = 0; i < n; i++)
scanf("%d", &input[i]);
for(int i = 0; i < MASK_WIDTH; i++)
mask[i] = i;
hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
hipMemcpy(d_mask, mask, sizeof(int)*MASK_WIDTH, hipMemcpyHostToDevice);
dim3 dimGrid((n-1) / OUT_TILE_WIDTH + 1, 1, 1);
dim3 dimBlock(OUT_TILE_WIDTH, 1, 1);
_k_conv1d<<<dimGrid, dimBlock>>>(d_input, d_mask, d_output, n);
hipDeviceSynchronize();
hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);
for(int i = 0; i < n; i++)
printf("%d ", output[i]);
printf("\n");
hipFree(d_input);
hipFree(d_mask);
free(input);
free(output);
free(mask);
return 0;
} | .text
.file "convolution1D_parallel.hip"
.globl _Z24__device_stub___k_conv1dPiS_S_i # -- Begin function _Z24__device_stub___k_conv1dPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub___k_conv1dPiS_S_i,@function
_Z24__device_stub___k_conv1dPiS_S_i: # @_Z24__device_stub___k_conv1dPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9_k_conv1dPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub___k_conv1dPiS_S_i, .Lfunc_end0-_Z24__device_stub___k_conv1dPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $404, %edi # imm = 0x194
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $404, %esi # imm = 0x194
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
cmpl $0, 4(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbp
movslq 4(%rsp), %rax
addq $4, %r13
cmpq %rax, %rbp
jl .LBB1_2
.LBB1_3: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $101, %rax
jne .LBB1_4
# %bb.5:
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $404, %edx # imm = 0x194
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edi
leal -1(%rdi), %eax
addl $510, %edi # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9_k_conv1dPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp)
jle .LBB1_10
# %bb.8: # %.lr.ph37.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph37
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
movslq 4(%rsp), %rax
cmpq %rax, %r12
jl .LBB1_9
.LBB1_10: # %._crit_edge
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9_k_conv1dPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9_k_conv1dPiS_S_i,@object # @_Z9_k_conv1dPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9_k_conv1dPiS_S_i
.p2align 3, 0x0
_Z9_k_conv1dPiS_S_i:
.quad _Z24__device_stub___k_conv1dPiS_S_i
.size _Z9_k_conv1dPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9_k_conv1dPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub___k_conv1dPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9_k_conv1dPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00102c39_00000000-6_convolution1D_parallel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9_k_conv1dPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
.globl _Z9_k_conv1dPiS_S_i
.type _Z9_k_conv1dPiS_S_i, @function
_Z9_k_conv1dPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9_k_conv1dPiS_S_i, .-_Z9_k_conv1dPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 20(%rsp), %eax
leal 0(,%rax,4), %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, 8(%rsp)
movl $404, %edi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $404, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
cmpl $0, 20(%rsp)
jle .L12
movl $0, %ebp
leaq .LC0(%rip), %r15
.L13:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
cmpl %ebp, 20(%rsp)
jg .L13
.L12:
movl $0, %eax
.L14:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $101, %rax
jne .L14
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $404, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rsp), %edx
leal 510(%rdx), %eax
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $0, 20(%rsp)
jle .L16
movl $0, %ebp
leaq .LC1(%rip), %r12
.L17:
movl 0(%r13,%rbp,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpl %ebp, 20(%rsp)
jg .L17
.L16:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl 20(%rsp), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9_k_conv1dPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9_k_conv1dPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolution1D_parallel.hip"
.globl _Z24__device_stub___k_conv1dPiS_S_i # -- Begin function _Z24__device_stub___k_conv1dPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub___k_conv1dPiS_S_i,@function
_Z24__device_stub___k_conv1dPiS_S_i: # @_Z24__device_stub___k_conv1dPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9_k_conv1dPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub___k_conv1dPiS_S_i, .Lfunc_end0-_Z24__device_stub___k_conv1dPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $404, %edi # imm = 0x194
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $404, %esi # imm = 0x194
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
cmpl $0, 4(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbp
movslq 4(%rsp), %rax
addq $4, %r13
cmpq %rax, %rbp
jl .LBB1_2
.LBB1_3: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $101, %rax
jne .LBB1_4
# %bb.5:
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $404, %edx # imm = 0x194
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edi
leal -1(%rdi), %eax
addl $510, %edi # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9_k_conv1dPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp)
jle .LBB1_10
# %bb.8: # %.lr.ph37.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph37
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
movslq 4(%rsp), %rax
cmpq %rax, %r12
jl .LBB1_9
.LBB1_10: # %._crit_edge
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9_k_conv1dPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9_k_conv1dPiS_S_i,@object # @_Z9_k_conv1dPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9_k_conv1dPiS_S_i
.p2align 3, 0x0
_Z9_k_conv1dPiS_S_i:
.quad _Z24__device_stub___k_conv1dPiS_S_i
.size _Z9_k_conv1dPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9_k_conv1dPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub___k_conv1dPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9_k_conv1dPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //并行版本输入多维
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#define DIMENSION 2
#define INPUT_NEURAL_NUM DIMENSION+1
#define HIDDEN_NEURAL_NUM 5
#define OUTPUT_NEURAL_NUM DIMENSION
#define NEURAL_NUM HIDDEN_NEURAL_NUM + INPUT_NEURAL_NUM + OUTPUT_NEURAL_NUM
#define EPOCH 200
#define THREAD_EPOCH 200
#define STEPS 10
#define MUTATION_P 0.03
#define CROSS_P 0.7
#define PER_BENCHMARK_TIMES 3
#define BENCHMARK_NUM 10
#define NEURAL_NETWORK_NUM (DIMENSION*PER_BENCHMARK_TIMES*BENCHMARK_NUM) //每一个染色体上进行的神经网络
#define PI 3.1415926535897932384626433832795029
#define E 2.7182818284590452353602874713526625
#define SINGLE_WEIGHT (NEURAL_NUM)*(NEURAL_NUM - 1)
#define MAX 100
#define MIN -100
#define DEVICE_NUM 1
#define BLOCK 8*4
#define THREAD 192*4
#define NUM_CHROMO (BLOCK*THREAD/(BENCHMARK_NUM*PER_BENCHMARK_TIMES))
#define G 0.002
#define W_MAX 0.01
#define W_MIN -0.01
#define DELTA_X_MAX 0.1
#define DELTA_X_MIN -0.1
struct NN
{
float w[SINGLE_WEIGHT];
float input_w[INPUT_NEURAL_NUM]; ////
float old_neural[NEURAL_NUM];
float new_neural[NEURAL_NUM];
};
struct CHROMO
{
NN nn_initial;
NN nn[PER_BENCHMARK_TIMES*BENCHMARK_NUM];
float a[BENCHMARK_NUM*PER_BENCHMARK_TIMES], b[BENCHMARK_NUM*PER_BENCHMARK_TIMES], c[BENCHMARK_NUM*PER_BENCHMARK_TIMES], d[BENCHMARK_NUM*PER_BENCHMARK_TIMES];
float A, B, C, D;
float initial_position[BENCHMARK_NUM*PER_BENCHMARK_TIMES][DIMENSION];
float position[BENCHMARK_NUM*PER_BENCHMARK_TIMES][DIMENSION];
};
struct IN_FITNESS
{
float f[THREAD_EPOCH];
};
struct IN_POSITION
{
float p[THREAD_EPOCH][DIMENSION];
};
void Sort(float *arr, int length, int *index)
{
int i, j, tin;
tin = 0;
float temp = 0.0;
for (i = 0; i < length - 1; i++)
{
for (j = 0; j < length - i - 1; j++)
{
if (arr[j] > arr[j + 1])
{
temp = arr[j];
arr[j] = arr[j + 1];
arr[j + 1] = temp;
tin = index[j];
index[j] = index[j + 1];
index[j + 1] = tin;
}
}
}
}
//锦标赛选择
void selection_tournment(struct CHROMO ch[NUM_CHROMO], float GA_Fitness[NUM_CHROMO], int g)
{
int m, i, j, l, n, k, maxindex;
m = NUM_CHROMO;
int sel_num, sel_init, sel_final;
sel_init = floor(NUM_CHROMO*0.15);
sel_final = floor(NUM_CHROMO*0.666);
sel_num = (int)(floor)(sel_final - sel_init) / (float)EPOCH*(g + 1) + sel_init;
int *select;
select = (int(*))malloc(sel_num * sizeof(int));
int mark2[NUM_CHROMO] = { 0 };//标记个体有没有被选中
int index[NUM_CHROMO] = { 0 };//
float min;
for (i = 0; i < m; i++) // m = CHROMOSOME_NUM
{
for (j = 0; j < sel_num; j++)
{
int r2 = rand() % m + 1; //1-m之间哪个个体（整数）
while (mark2[r2 - 1] == 1)
{
r2 = rand() % m + 1;
}
mark2[r2 - 1] = 1;
select[j] = r2 - 1;
}
min = GA_Fitness[select[0]];
maxindex = select[0];
for (k = 1; k < sel_num; k++)
{
if (GA_Fitness[select[k]] < min)
{
min = GA_Fitness[select[k]];
maxindex = select[k];
}
}
index[i] = maxindex;
for (n = 0; n < NUM_CHROMO; n++)
{
mark2[n] = 0;
}
for (n = 0; n < sel_num; n++)
{
select[n] = 0;
}
for (l = 0; l < SINGLE_WEIGHT; l++)
{
ch[i].nn_initial.w[l] = ch[index[i]].nn_initial.w[l];
}
for (l = 0; l < INPUT_NEURAL_NUM; l++)
{
ch[i].nn_initial.input_w[l] = ch[index[i]].nn_initial.input_w[l];
}
ch[i].A = ch[index[i]].A;
ch[i].B = ch[index[i]].B;
ch[i].C = ch[index[i]].C;
ch[i].D = ch[index[i]].D;
}
free(select);
}
//交叉
void crossover(struct CHROMO ch[NUM_CHROMO])
{
//const double a = 0.0;
//const double b = 1.0;
time_t tttt;
srand((unsigned int)time(&tttt));
int two;
int one;
int first = 0;
float r, r2;
//int point;
float t;
int i;
for (two = 0; two < NUM_CHROMO; two++)
{
r = (float)rand() / RAND_MAX;
if (r < CROSS_P)
{
++first;
if (first % 2 == 0)//交叉
{
//point = rand() % TOTAL_WEIGHT + 1; //随机选择交叉点
for (i = 0; i < SINGLE_WEIGHT; i++)
{
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].nn_initial.w[i];
ch[one].nn_initial.w[i] = ch[two].nn_initial.w[i];
ch[two].nn_initial.w[i] = t;
}
}
for (i = 0; i < INPUT_NEURAL_NUM; i++)
{
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].nn_initial.input_w[i];
ch[one].nn_initial.input_w[i] = ch[two].nn_initial.input_w[i];
ch[two].nn_initial.input_w[i] = t;
}
}
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].A;
ch[one].A = ch[two].A;
ch[two].A = t;
}
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].B;
ch[one].B = ch[two].B;
ch[two].B = t;
}
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].C;
ch[one].C = ch[two].C;
ch[two].C = t;
}
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].D;
ch[one].D = ch[two].D;
ch[two].D = t;
}
}
else
{
one = two;
}
}
}
}
//变异
void mutation(struct CHROMO ch[NUM_CHROMO])
{
float r;
time_t tttt;
srand((unsigned int)time(&tttt));
int i, j;
for (i = 0; i < NUM_CHROMO; i++)
{
for (j = 0; j < INPUT_NEURAL_NUM; j++)
{
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].nn_initial.input_w[j] = (float)rand() / (RAND_MAX + 1.0) * (W_MAX - W_MIN) - W_MAX;
}
}
for (j = 0; j < SINGLE_WEIGHT; j++)
{
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].nn_initial.w[j] = (float)rand() / (RAND_MAX + 1.0) * (W_MAX - W_MIN) - W_MAX;
}
}
r = (float)rand() / (RAND_MAX + 1.0);
/*
if (r < MUTATION_P)
{
ch[i].A = (float)rand() / RAND_MAX * 2.0 - 1.0;
}
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].B = (float)rand() / RAND_MAX * 2.0 - 1.0;
}
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].C = (float)rand() / RAND_MAX * 2.0 - 1.0;
}
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].D = (float)rand() / RAND_MAX * 2.0 - 1.0;
}
*/
if (r < MUTATION_P)
{
ch[i].A = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
ch[i].B = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
ch[i].C = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
ch[i].D = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
}
}
}
void initial_chromo(struct CHROMO chromo[NUM_CHROMO])
{
time_t ti;
srand((unsigned int)time(&ti));
for (int i = 0; i < NUM_CHROMO; i++)
{
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
chromo[i].nn_initial.input_w[j] = (float)rand() / RAND_MAX *(W_MAX - W_MIN) - W_MAX;
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
chromo[i].nn_initial.w[j] = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
}
chromo[i].A = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo[i].B = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo[i].C = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo[i].D = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
for (int num_fun = 0; num_fun < BENCHMARK_NUM*PER_BENCHMARK_TIMES; num_fun++)
{
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
chromo[i].nn[num_fun].w[j] = chromo[i].nn_initial.w[j];
}
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
chromo[i].nn[num_fun].input_w[j] = chromo[i].nn_initial.input_w[j];
}
for (int j = 0; j < NEURAL_NUM; j++)
{
chromo[i].nn[num_fun].old_neural[j] = 0.5;
chromo[i].nn[num_fun].new_neural[j] = 0.0;
}
for (int d = 0; d < DIMENSION; d++)
{
chromo[i].initial_position[num_fun][d] = (float)rand() / RAND_MAX * (MAX - MIN) - MAX;
chromo[i].position[num_fun][d] = chromo[i].initial_position[num_fun][d];
}
chromo[i].a[num_fun] = chromo[i].A;
chromo[i].b[num_fun] = chromo[i].B;
chromo[i].c[num_fun] = chromo[i].C;
chromo[i].d[num_fun] = chromo[i].D;
}
}
}
void initial_chromo(struct CHROMO &chromo)
{
time_t tttt;
srand((unsigned int)time(&tttt));
int i = 0;
for (i = 0; i<INPUT_NEURAL_NUM; i++)
{
chromo.nn_initial.input_w[i] = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
}
for (i = 0; i<SINGLE_WEIGHT; i++)
{
chromo.nn_initial.w[i] = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
}
chromo.A = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo.B = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo.C = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo.D = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
for (int num_fun = 0; num_fun < BENCHMARK_NUM*PER_BENCHMARK_TIMES; num_fun++)
{
for (i = 0; i < SINGLE_WEIGHT; i++)
{
chromo.nn[num_fun].w[i] = chromo.nn_initial.w[i];
}
for (i = 0; i < INPUT_NEURAL_NUM; i++)
{
chromo.nn[num_fun].input_w[i] = chromo.nn_initial.input_w[i];
}
for (i = 0; i < NEURAL_NUM; i++)
{
chromo.nn[num_fun].old_neural[i] = 0.5;
chromo.nn[num_fun].new_neural[i] = 0.0;
}
for (i = 0; i < DIMENSION; i++)
{
chromo.initial_position[num_fun][i] = (float)rand() / RAND_MAX * (MAX - MIN) - MAX;
chromo.position[num_fun][i] = chromo.initial_position[num_fun][i];
}
chromo.a[num_fun] = chromo.A;
chromo.b[num_fun] = chromo.B;
chromo.c[num_fun] = chromo.C;
chromo.d[num_fun] = chromo.D;
}
}
float my_function(struct CHROMO ch[NUM_CHROMO], float fitness[NUM_CHROMO*PER_BENCHMARK_TIMES*BENCHMARK_NUM], struct CHROMO &GA_best_ch, int g)
{
int temp_nn_index[NUM_CHROMO*PER_BENCHMARK_TIMES];//下标
float nn_fitness[BENCHMARK_NUM*PER_BENCHMARK_TIMES][NUM_CHROMO]; //实际通过cec计算得出的适应值
float nn_fitness_one_f[NUM_CHROMO];//所有染色体在同一个函数上的排序
int record_sort_index[NUM_CHROMO]; //1个函数下的NUM_CHROMO*PER_BENCHMARK_TIMES个排名名次
float record_nn_fitness_sort_index[BENCHMARK_NUM*PER_BENCHMARK_TIMES][NUM_CHROMO]; //10个函数下的CHROMOSOME_NUM个NN 名次
float fitness_ranking[BENCHMARK_NUM + 1][NUM_CHROMO];
float GA_fitness[NUM_CHROMO];
float min_fit;
FILE* f_temp_ch;
FILE* f_temp_result = fopen("temp_result.txt", "a");
//FILE* all_f_g = fopen("all_f_g.txt", "a");
FILE* one_g_chromo[NUM_CHROMO + 1];
char fileName[256];
for (int i = 0; i < NUM_CHROMO; i++)
{
sprintf(fileName, "NN/g%d/ch_%d.txt", g + 1, i);
one_g_chromo[i] = fopen(fileName, "w");
if (one_g_chromo[i] == NULL)
{
printf("\n Error: Cannot open ch_%d filoe \n",i);
}
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
fprintf(one_g_chromo[i], "%f\n", ch[i].nn_initial.input_w[j]);
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
fprintf(one_g_chromo[i], "%f\n", ch[i].nn_initial.w[j]);
}
fprintf(one_g_chromo[i], "A:%f\n B:%f\n C:%f\n D:%f\n", ch[i].A, ch[i].B, ch[i].C, ch[i].D);
fclose(one_g_chromo[i]);
}
for (int i = 0; i < BENCHMARK_NUM + 1; i++)
{
for (int j = 0; j < NUM_CHROMO; j++)
{
fitness_ranking[i][j] = 0.0;
}
}
for (int fun_num = 0; fun_num < BENCHMARK_NUM*PER_BENCHMARK_TIMES; fun_num++)
{
for (int i = 0; i < NUM_CHROMO; i++)
{
nn_fitness[fun_num][i] = 0.0;
}
}
//排100个，分别排3次的话
for (int fun_num = 0; fun_num < BENCHMARK_NUM*PER_BENCHMARK_TIMES; fun_num++)
{
for (int i = 0; i < NUM_CHROMO; i++)
{
nn_fitness[fun_num][i] = fitness[fun_num + i *BENCHMARK_NUM*PER_BENCHMARK_TIMES];
//printf("nn_fitness[%d][%d]=%f \t ",fun_num,i,nn_fitness[fun_num][i]);
}
}
//10个函数分别排3次
for (int fun_num = 0; fun_num < BENCHMARK_NUM*PER_BENCHMARK_TIMES; fun_num++)
{
for (int i = 0; i < NUM_CHROMO; i++)
{
nn_fitness_one_f[i] = nn_fitness[fun_num][i]; //NUM_CHROMO个染色体在一个函数上
temp_nn_index[i] = i;
}
Sort(nn_fitness_one_f, NUM_CHROMO, temp_nn_index);
for (int i = 0; i < NUM_CHROMO; i++)
{
record_sort_index[temp_nn_index[i]] = i + 1;
}
for (int i = 0; i < NUM_CHROMO; i++)
{
record_nn_fitness_sort_index[fun_num][i] = (float)record_sort_index[i]; //NUM_CHROMO * BENCHMARK_NUM*PER_BENCHMARK_TIMES个名次 //printf("sort_index[%d][%d]=%f \t ",fun_num,i,record_nn_fitness_sort_index[fun_num][i]);
}
}
for (int i = 0; i < NUM_CHROMO; i++)
{
for (int fun_num = 0; fun_num < BENCHMARK_NUM; fun_num++)
{
for (int k = 0; k < PER_BENCHMARK_TIMES; k++)
{
fitness_ranking[fun_num][i] += record_nn_fitness_sort_index[fun_num + BENCHMARK_NUM * k][i];
}
fitness_ranking[fun_num][i] /= PER_BENCHMARK_TIMES;
}
}
//平均排名
for (int i = 0; i < NUM_CHROMO; i++)
{
float sum = 0;
for (int j = 0; j < BENCHMARK_NUM; j++)
{
sum += fitness_ranking[j][i];
}
fitness_ranking[BENCHMARK_NUM][i] = sum / BENCHMARK_NUM;
GA_fitness[i] = sum / BENCHMARK_NUM;
printf("the %dth chromosome in all function's avg ranking is :%f \n", i + 1, GA_fitness[i]);
//fprintf(all_f_g, "g=%d,f[%d]=%f:\n", g + 1, i + 1, GA_fitness[i]);
}
sprintf(fileName, "NN/g%d/GA_fitness.txt", g + 1);
one_g_chromo[NUM_CHROMO] = fopen(fileName, "a");
if (one_g_chromo[NUM_CHROMO] == NULL)
{
printf("\n Error: Cannot open GA_fitness file \n");
}
for (int i = 0; i < NUM_CHROMO; i++)
{
fprintf(one_g_chromo[NUM_CHROMO], "%f\n", GA_fitness[i]);
}
fclose(one_g_chromo[NUM_CHROMO]);
min_fit = GA_fitness[0]; //当代 找最小排名及对应的网络
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
GA_best_ch.nn_initial.input_w[j] = ch[0].nn_initial.input_w[j];
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
GA_best_ch.nn_initial.w[j] = ch[0].nn_initial.w[j];
}
GA_best_ch.A = ch[0].A;
GA_best_ch.B = ch[0].B;
GA_best_ch.C = ch[0].C;
GA_best_ch.D = ch[0].D;
for (int i = 1; i < NUM_CHROMO; i++)
{
if (GA_fitness[i] < min_fit)
{
min_fit = GA_fitness[i];
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
GA_best_ch.nn_initial.input_w[j] = ch[i].nn_initial.input_w[j];
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
GA_best_ch.nn_initial.w[j] = ch[i].nn_initial.w[j];
}
GA_best_ch.A = ch[i].A;
GA_best_ch.B = ch[i].B;
GA_best_ch.C = ch[i].C;
GA_best_ch.D = ch[i].D;
}
}
sprintf(fileName, "NN/g%d/temp_bestch.txt", g + 1);
f_temp_ch = fopen(fileName, "w");
fprintf(f_temp_ch, "g=%d,the best chromosome:\n", g + 1);
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
fprintf(f_temp_ch, "%f\n", GA_best_ch.nn_initial.input_w[j]);
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
fprintf(f_temp_ch, "%f\n", GA_best_ch.nn_initial.w[j]);
}
fprintf(f_temp_ch, "A:%f\n B:%f\n C:%f\n D:%f\n", GA_best_ch.A, GA_best_ch.B, GA_best_ch.C, GA_best_ch.D);//当代最佳chromosome
printf("the generation %d min ranking is:%f \n", g + 1, min_fit);
fprintf(f_temp_result, "g=%d,the best:%f\n", g + 1, min_fit);//当代最佳适应值
selection_tournment(ch, GA_fitness, g);
crossover(ch);
mutation(ch);
for (int i = 0; i < NUM_CHROMO; i++)
{
for (int j = 0; j < (PER_BENCHMARK_TIMES*BENCHMARK_NUM); j++)
{
for (int d = 0; d < SINGLE_WEIGHT; d++)
{
ch[i].nn[j].w[d] = ch[i].nn_initial.w[d];
}
for (int k = 0; k < DIMENSION; k++)
{
ch[i].position[j][k] = ch[i].initial_position[j][k];
}
for (int tt = 0; tt < INPUT_NEURAL_NUM; tt++)
{
ch[i].nn[j].input_w[tt] = ch[i].nn_initial.input_w[tt];
}
for (int d = 0; d < NEURAL_NUM; d++)
{
ch[i].nn[j].old_neural[d] = 0.5;
}
ch[i].a[j] = ch[i].A;
ch[i].b[j] = ch[i].B;
ch[i].c[j] = ch[i].C;
ch[i].d[j] = ch[i].D;
}
}
fclose(f_temp_ch);
fclose(f_temp_result);
//fclose(all_f_g);
/*
for (int i = 0; i < NUM_CHROMO + 1; i++)
{
fclose(one_g_chromo[i]);
}
*/
return min_fit;
}
__device__ float hebb(float a, float b, float c, float d, float x, float y)
{
return G*(a*x + b * y + c * x*y + d);
}
__device__ float sigmoid(float x)
{
if (x < -80)
return 0;
else if (x > 80)
return 1;
else
return 1.0F / (1.0F + exp(-1 * x));
}
__device__ void nn_forward_and_update_paramenter(struct CHROMO ch[], int num, float f, int num_fun3, int num_epoch) ////
{
float inputs[INPUT_NEURAL_NUM];
float delta_w[SINGLE_WEIGHT];
int t = 0;
//输入
inputs[0] = f / num_epoch;
inputs[1] = ch[num].position[num_fun3][0] / MAX;
inputs[2] = ch[num].position[num_fun3][1] / MAX;
for (int i = 0; i < SINGLE_WEIGHT; i++)
{
delta_w[i] = 0;
}
//前向传递
for (int i = 0; i < NEURAL_NUM; i++)
{
for (int j = 0; j < NEURAL_NUM; j++)
{
if (i != j)
{
ch[num].nn[num_fun3].new_neural[i] += (ch[num].nn[num_fun3].w[t] * ch[num].nn[num_fun3].old_neural[j]);
t++;
}
}
//printf("dimension %d,neural %d:%f\n",k, i, ch[num].nn[num_fun3][k].new_neural[i]);
if (i < INPUT_NEURAL_NUM)
{
ch[num].nn[num_fun3].new_neural[i] = sigmoid(ch[num].nn[num_fun3].new_neural[i] + ch[num].nn[num_fun3].input_w[i] * inputs[i]);
}
else
{
ch[num].nn[num_fun3].new_neural[i] = sigmoid(ch[num].nn[num_fun3].new_neural[i]);
}
}
//printf("\n");
//计算delta_w
t = 0;
for (int i = 0; i < NEURAL_NUM; i++)
{
for (int j = 0; j < NEURAL_NUM; j++)
{
if (i != j)
{
delta_w[t] = hebb(ch[num].a[num_fun3], ch[num].b[num_fun3], ch[num].c[num_fun3], ch[num].d[num_fun3], ch[num].nn[num_fun3].old_neural[j], ch[num].nn[num_fun3].old_neural[i]);
t++;
}
}
}
//更新神经元
for (int i = 0; i < NEURAL_NUM; i++)
{
ch[num].nn[num_fun3].old_neural[i] = ch[num].nn[num_fun3].new_neural[i];
ch[num].nn[num_fun3].new_neural[i] = 0;
}
//更新权重
t = 0;
for (int i = 0; i < NEURAL_NUM; i++)
{
for (int j = 0; j < NEURAL_NUM; j++)
{
if (i != j)
{
ch[num].nn[num_fun3].w[t] = (ch[num].nn[num_fun3].w[t] + delta_w[t])*0.99;
t++;
}
}
}
}
__device__ float benchmark(int funnum, float x[][DIMENSION], int num) //some simple functions
{
int a = funnum;
float f, sum1, sum2;
int i;
f = 0.0;
i = 0;
sum1 = 0.0;
sum2 = 0.0;
switch (a)
{
case 0: //sphere function
{
f = 0.0;
for (i = 0; i < DIMENSION; i++)
{
f += x[num][i] * x[num][i];
}
return(f);
}
case 1: //elliptic function
{ f = 0.0;
for (i = 0; i < DIMENSION; i++)
{
f += pow(pow(10.0, 6.0), i / (DIMENSION - 1))*x[num][i] * x[num][i];
}
return(f);
}
case 2: //rastrigin's function
{ f = 0.0;
for (i = 0; i < DIMENSION; i++)
{
f += (x[num][i] * x[num][i] - 10.0*cos(2.0*PI*x[num][i]) + 10.0);
}
return(f);
}
case 3: //ackley function
{
for (i = 0; i < DIMENSION; i++)
{
sum1 += x[num][i] * x[num][i];
sum2 += cos(2.0*PI*x[num][i]);
}
sum1 = -0.2*sqrt(sum1 / DIMENSION);
sum2 = sum2 / DIMENSION;
f = E - 20.0*exp(sum1) - exp(sum2) + 20.0;
return(f);
}
case 4: //rosenbrock function
{
for (i = 0; i < DIMENSION - 1; i++)
{
sum1 = x[num][i] * x[num][i] - x[num][i + 1];
sum2 = x[num][i] - 1;
f += 100.0*sum1*sum1 + sum2 * sum2;
}
return(f);
}
case 5: //bent cigar function
{
for (i = 1; i < DIMENSION; i++)
{
f += pow(10.0, 6.0)*x[num][i] * x[num][i];
}
f += x[num][0] * x[num][0];
return f;
}
case 6: //zakharov function
{
for (i = 0; i < DIMENSION; i++)
{
float z = x[num][i];
sum1 += pow(z, 2);
sum2 += 0.5*z;
}
f = sum1 + pow(sum2, 2) + pow(sum2, 4);
return(f);
}
case 7: //schwefel function
{
for (i = 0; i < DIMENSION; i++)
{
for (int j = 0; j < i; j++)
{
sum1 += x[num][i] * x[num][i];
}
sum1 = sum1 * sum1;
f += sum1;
}
return(f);
}
case 8: //griewank's function
{
for (i = 0; i < DIMENSION; i++)
{
sum1 += x[num][i] * x[num][i];
sum2 *= cos(x[num][i] / sqrt(1.0 + i));
}
f = sum1 / 4000.0 - sum2 + 1.0;
return(f);
}
default: //discus function
f = pow(10.0, 6.0)*x[num][0] * x[num][0];
for (i = 1; i < DIMENSION; i++)
{
f += x[num][i] * x[num][i];
}
return(f);
}
}
__device__ float thread_sort(int sort_num, struct IN_FITNESS in_f[], int num, float p)
{
float a = 0, count = 0;
for (int i = 0; i < sort_num - 1; i++)
{
for (int j = 0; j < sort_num - i - 1; j++)
{
if (in_f[num].f[j] > in_f[num].f[j + 1])
{
a = in_f[num].f[j];
in_f[num].f[j] = in_f[num].f[j + 1];
in_f[num].f[j + 1] = a;
}
}
}
for (int i = 0; i < sort_num; i++)
{
if (p == in_f[num].f[i])
{
return count + 1;
}
else
{
count++;
}
}
return 0;
}
__global__ void kernel(struct CHROMO ch[NUM_CHROMO], float fitness[BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO], struct IN_FITNESS in_f[BENCHMARK_NUM*NUM_CHROMO*PER_BENCHMARK_TIMES], struct IN_POSITION in_p[BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO])
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int i,d;
if (idx <BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO)
{
float value_position;
int num_epoch = 0;
float ff = 0;
int num = (idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES)) % BENCHMARK_NUM;
for (num_epoch = 0; num_epoch<THREAD_EPOCH; num_epoch++)
{
for (d = 0; d < DIMENSION; d++)
{
in_p[idx].p[num_epoch][d] = ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].position[idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES)][d];
}
in_f[idx].f[num_epoch] = benchmark(num, ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].position, idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES));
//printf("ff:%f \n", in_f[idx].f[num_epoch]);
ff = thread_sort((num_epoch + 1), in_f, idx, in_f[idx].f[num_epoch]);
//printf("epoch %d ff: %f\n ", num_epoch, ff);
for (i = 0; i < STEPS; i++)
{
nn_forward_and_update_paramenter(ch, idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES), ff, idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES), (num_epoch + 1));
}
for (d = 0; d < DIMENSION; d++)
{
ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].position[idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES)][d] += (ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].nn[idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].old_neural[NEURAL_NUM - (d + 1)] * (DELTA_X_MAX - DELTA_X_MIN) - DELTA_X_MAX)* MAX;
}
}
fitness[idx] = benchmark(num, ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].position, idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES));
printf("in fitness[%d]: %f\n", idx, fitness[idx]);
}
}
int main()
{
struct CHROMO *h_ch = (struct CHROMO *)malloc(sizeof(CHROMO)*NUM_CHROMO); //主机端的染色体数组
struct CHROMO *d_ch; //设备端的
struct IN_FITNESS *h_in_fitness = (struct IN_FITNESS *)malloc(sizeof(IN_FITNESS)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
struct IN_FITNESS *d_in_fitness;
struct IN_POSITION *h_in_position = (struct IN_POSITION *)malloc(sizeof(IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
struct IN_POSITION *d_in_position = (struct IN_POSITION *)malloc(sizeof(IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
float *d_fitness; //设备端的一维适应值数组
float *h_fitness = (float *)malloc(sizeof(float)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);//主机端的
int i, g, j, d;
struct CHROMO GA_best_ch; //每代最佳的染色体
struct CHROMO history_best_ch; //历史最佳的染色体
float min_fit; //每代最佳的适应值
float the_min_fit_inallG; //历史最佳的适应值
int record_g = 0;
int device_id = DEVICE_NUM;
FILE* f_results = fopen("GA200results.txt", "a");
FILE* f_history_ch = fopen("history_bestch.txt", "a");
//FILE *f_position = fopen("f_position.txt", "a");
if (f_results == NULL || f_history_ch == NULL)
{
printf("failed to open f file\n");
system("pause");
}
srand((unsigned)time(NULL));
for (i = 0; i < BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
h_fitness[i] = 0;
}
for (i = 0; i < BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
for (j = 0; j < THREAD_EPOCH; j++)
{
h_in_fitness[i].f[j] = 0.0;
}
}
for (i = 0; i<BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
for (j = 0; j<THREAD_EPOCH; j++)
{
for (d = 0; d<DIMENSION; d++)
{
h_in_position[i].p[j][d] = 0.0;
}
}
}
initial_chromo(h_ch);
initial_chromo(GA_best_ch);
initial_chromo(history_best_ch);
//dim3 grid(BLOCK);
//dim3 threads(THREAD);
cudaSetDevice(device_id);
for (g = 0; g < EPOCH; g++)
{
cudaMalloc((void **)&d_fitness, sizeof(float)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
cudaMalloc((struct CHROMO **)&d_ch, sizeof(struct CHROMO) * NUM_CHROMO);
cudaMalloc((struct IN_FITNESS **)&d_in_fitness, sizeof(struct IN_FITNESS)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
cudaMalloc((struct IN_POSITION **)&d_in_position, sizeof(struct IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
cudaMemcpy(d_ch, h_ch, sizeof(struct CHROMO) * NUM_CHROMO, cudaMemcpyHostToDevice);
cudaMemcpy(d_fitness, h_fitness, sizeof(float)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, cudaMemcpyHostToDevice);
cudaMemcpy(d_in_fitness, h_in_fitness, sizeof(struct IN_FITNESS)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, cudaMemcpyHostToDevice);
cudaMemcpy(d_in_position, h_in_position, sizeof(struct IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, cudaMemcpyHostToDevice);
kernel <<<BLOCK, THREAD >>> (d_ch, d_fitness, d_in_fitness, d_in_position);
cudaDeviceSynchronize();
cudaMemcpy(h_fitness, d_fitness, sizeof(float)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, cudaMemcpyDeviceToHost);
cudaMemcpy(h_in_position, d_in_position, sizeof(struct IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, cudaMemcpyDeviceToHost);
//cudaMemcpy(h_ch, d_ch, sizeof(struct CHROMO)*NUM_CHROMO, cudaMemcpyDeviceToHost);
/*
fprintf(f_position, "第%d代:\n", g + 1);
for (i = 0; i < BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
fprintf(f_position, "第%d个染色体\n", i + 1);
for (j = 0; j < THREAD_EPOCH; j++)
{
fprintf(f_position, "第%d次移动\t\t\t", j + 1);
for (d = 0; d < DIMENSION; d++)
{
fprintf(f_position, "%f\t\t", h_in_position[i].p[j][d]);
}
}
}
*/
/*
for (i = 0; i < BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
printf("out fitness[%d] = %f\n", i, h_fitness[i]);
}
*/
min_fit = my_function(h_ch, h_fitness, GA_best_ch, g);
if (g == 0)
{
the_min_fit_inallG = min_fit;
for (i = 0; i < INPUT_NEURAL_NUM; i++)
{
history_best_ch.nn_initial.input_w[i] = GA_best_ch.nn_initial.input_w[i];
fprintf(f_history_ch, "%f\n", history_best_ch.nn_initial.input_w[i]);
}
for (j = 0; j < SINGLE_WEIGHT; j++)
{
history_best_ch.nn_initial.w[j] = GA_best_ch.nn_initial.w[j];
fprintf(f_history_ch, "%f\n", history_best_ch.nn_initial.w[j]);
}
history_best_ch.A = GA_best_ch.A;
history_best_ch.B = GA_best_ch.B;
history_best_ch.C = GA_best_ch.C;
history_best_ch.D = GA_best_ch.D;
fprintf(f_history_ch, "A:%f\n B:%f\n C:%f\n D:%f\n", history_best_ch.A, history_best_ch.B, history_best_ch.C, history_best_ch.D);
record_g = g;
}
if (min_fit < the_min_fit_inallG)
{
the_min_fit_inallG = min_fit;
for (i = 0; i < INPUT_NEURAL_NUM; i++)
{
history_best_ch.nn_initial.input_w[i] = GA_best_ch.nn_initial.input_w[i];
fprintf(f_history_ch, "%f\n", history_best_ch.nn_initial.input_w[i]);
}
for (j = 0; j < SINGLE_WEIGHT; j++)
{
history_best_ch.nn_initial.w[j] = GA_best_ch.nn_initial.w[j];
fprintf(f_history_ch, "%f\n", history_best_ch.nn_initial.w[j]);
}
history_best_ch.A = GA_best_ch.A;
history_best_ch.B = GA_best_ch.B;
history_best_ch.C = GA_best_ch.C;
history_best_ch.D = GA_best_ch.D;
fprintf(f_history_ch, "A:%f\n B:%f\n C:%f\n D:%f\n", history_best_ch.A, history_best_ch.B, history_best_ch.C, history_best_ch.D);
record_g = g;
}
printf("the history min ranking is:%f \n", the_min_fit_inallG);
fprintf(f_results, "history best is in g=%d:%f\n", record_g + 1, the_min_fit_inallG);
cudaFree(d_fitness);
cudaFree(d_ch);
cudaFree(d_in_fitness);
cudaFree(d_in_position);
}//GA代
fclose(f_history_ch);
//fclose(f_position);
fclose(f_results);
free(h_ch);
free(h_fitness);
free(h_in_fitness);
free(h_in_position);
return 0;
} | //并行版本输入多维
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#define DIMENSION 2
#define INPUT_NEURAL_NUM DIMENSION+1
#define HIDDEN_NEURAL_NUM 5
#define OUTPUT_NEURAL_NUM DIMENSION
#define NEURAL_NUM HIDDEN_NEURAL_NUM + INPUT_NEURAL_NUM + OUTPUT_NEURAL_NUM
#define EPOCH 200
#define THREAD_EPOCH 200
#define STEPS 10
#define MUTATION_P 0.03
#define CROSS_P 0.7
#define PER_BENCHMARK_TIMES 3
#define BENCHMARK_NUM 10
#define NEURAL_NETWORK_NUM (DIMENSION*PER_BENCHMARK_TIMES*BENCHMARK_NUM) //每一个染色体上进行的神经网络
#define PI 3.1415926535897932384626433832795029
#define E 2.7182818284590452353602874713526625
#define SINGLE_WEIGHT (NEURAL_NUM)*(NEURAL_NUM - 1)
#define MAX 100
#define MIN -100
#define DEVICE_NUM 1
#define BLOCK 8*4
#define THREAD 192*4
#define NUM_CHROMO (BLOCK*THREAD/(BENCHMARK_NUM*PER_BENCHMARK_TIMES))
#define G 0.002
#define W_MAX 0.01
#define W_MIN -0.01
#define DELTA_X_MAX 0.1
#define DELTA_X_MIN -0.1
struct NN
{
float w[SINGLE_WEIGHT];
float input_w[INPUT_NEURAL_NUM]; ////
float old_neural[NEURAL_NUM];
float new_neural[NEURAL_NUM];
};
struct CHROMO
{
NN nn_initial;
NN nn[PER_BENCHMARK_TIMES*BENCHMARK_NUM];
float a[BENCHMARK_NUM*PER_BENCHMARK_TIMES], b[BENCHMARK_NUM*PER_BENCHMARK_TIMES], c[BENCHMARK_NUM*PER_BENCHMARK_TIMES], d[BENCHMARK_NUM*PER_BENCHMARK_TIMES];
float A, B, C, D;
float initial_position[BENCHMARK_NUM*PER_BENCHMARK_TIMES][DIMENSION];
float position[BENCHMARK_NUM*PER_BENCHMARK_TIMES][DIMENSION];
};
struct IN_FITNESS
{
float f[THREAD_EPOCH];
};
struct IN_POSITION
{
float p[THREAD_EPOCH][DIMENSION];
};
void Sort(float *arr, int length, int *index)
{
int i, j, tin;
tin = 0;
float temp = 0.0;
for (i = 0; i < length - 1; i++)
{
for (j = 0; j < length - i - 1; j++)
{
if (arr[j] > arr[j + 1])
{
temp = arr[j];
arr[j] = arr[j + 1];
arr[j + 1] = temp;
tin = index[j];
index[j] = index[j + 1];
index[j + 1] = tin;
}
}
}
}
//锦标赛选择
void selection_tournment(struct CHROMO ch[NUM_CHROMO], float GA_Fitness[NUM_CHROMO], int g)
{
int m, i, j, l, n, k, maxindex;
m = NUM_CHROMO;
int sel_num, sel_init, sel_final;
sel_init = floor(NUM_CHROMO*0.15);
sel_final = floor(NUM_CHROMO*0.666);
sel_num = (int)(floor)(sel_final - sel_init) / (float)EPOCH*(g + 1) + sel_init;
int *select;
select = (int(*))malloc(sel_num * sizeof(int));
int mark2[NUM_CHROMO] = { 0 };//标记个体有没有被选中
int index[NUM_CHROMO] = { 0 };//
float min;
for (i = 0; i < m; i++) // m = CHROMOSOME_NUM
{
for (j = 0; j < sel_num; j++)
{
int r2 = rand() % m + 1; //1-m之间哪个个体（整数）
while (mark2[r2 - 1] == 1)
{
r2 = rand() % m + 1;
}
mark2[r2 - 1] = 1;
select[j] = r2 - 1;
}
min = GA_Fitness[select[0]];
maxindex = select[0];
for (k = 1; k < sel_num; k++)
{
if (GA_Fitness[select[k]] < min)
{
min = GA_Fitness[select[k]];
maxindex = select[k];
}
}
index[i] = maxindex;
for (n = 0; n < NUM_CHROMO; n++)
{
mark2[n] = 0;
}
for (n = 0; n < sel_num; n++)
{
select[n] = 0;
}
for (l = 0; l < SINGLE_WEIGHT; l++)
{
ch[i].nn_initial.w[l] = ch[index[i]].nn_initial.w[l];
}
for (l = 0; l < INPUT_NEURAL_NUM; l++)
{
ch[i].nn_initial.input_w[l] = ch[index[i]].nn_initial.input_w[l];
}
ch[i].A = ch[index[i]].A;
ch[i].B = ch[index[i]].B;
ch[i].C = ch[index[i]].C;
ch[i].D = ch[index[i]].D;
}
free(select);
}
//交叉
void crossover(struct CHROMO ch[NUM_CHROMO])
{
//const double a = 0.0;
//const double b = 1.0;
time_t tttt;
srand((unsigned int)time(&tttt));
int two;
int one;
int first = 0;
float r, r2;
//int point;
float t;
int i;
for (two = 0; two < NUM_CHROMO; two++)
{
r = (float)rand() / RAND_MAX;
if (r < CROSS_P)
{
++first;
if (first % 2 == 0)//交叉
{
//point = rand() % TOTAL_WEIGHT + 1; //随机选择交叉点
for (i = 0; i < SINGLE_WEIGHT; i++)
{
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].nn_initial.w[i];
ch[one].nn_initial.w[i] = ch[two].nn_initial.w[i];
ch[two].nn_initial.w[i] = t;
}
}
for (i = 0; i < INPUT_NEURAL_NUM; i++)
{
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].nn_initial.input_w[i];
ch[one].nn_initial.input_w[i] = ch[two].nn_initial.input_w[i];
ch[two].nn_initial.input_w[i] = t;
}
}
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].A;
ch[one].A = ch[two].A;
ch[two].A = t;
}
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].B;
ch[one].B = ch[two].B;
ch[two].B = t;
}
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].C;
ch[one].C = ch[two].C;
ch[two].C = t;
}
r2 = (float)rand() / (RAND_MAX + 1.0);
if (r2 < 0.5)
{
t = ch[one].D;
ch[one].D = ch[two].D;
ch[two].D = t;
}
}
else
{
one = two;
}
}
}
}
//变异
void mutation(struct CHROMO ch[NUM_CHROMO])
{
float r;
time_t tttt;
srand((unsigned int)time(&tttt));
int i, j;
for (i = 0; i < NUM_CHROMO; i++)
{
for (j = 0; j < INPUT_NEURAL_NUM; j++)
{
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].nn_initial.input_w[j] = (float)rand() / (RAND_MAX + 1.0) * (W_MAX - W_MIN) - W_MAX;
}
}
for (j = 0; j < SINGLE_WEIGHT; j++)
{
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].nn_initial.w[j] = (float)rand() / (RAND_MAX + 1.0) * (W_MAX - W_MIN) - W_MAX;
}
}
r = (float)rand() / (RAND_MAX + 1.0);
/*
if (r < MUTATION_P)
{
ch[i].A = (float)rand() / RAND_MAX * 2.0 - 1.0;
}
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].B = (float)rand() / RAND_MAX * 2.0 - 1.0;
}
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].C = (float)rand() / RAND_MAX * 2.0 - 1.0;
}
r = (float)rand() / (RAND_MAX + 1.0);
if (r < MUTATION_P)
{
ch[i].D = (float)rand() / RAND_MAX * 2.0 - 1.0;
}
*/
if (r < MUTATION_P)
{
ch[i].A = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
ch[i].B = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
ch[i].C = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
ch[i].D = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
}
}
}
void initial_chromo(struct CHROMO chromo[NUM_CHROMO])
{
time_t ti;
srand((unsigned int)time(&ti));
for (int i = 0; i < NUM_CHROMO; i++)
{
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
chromo[i].nn_initial.input_w[j] = (float)rand() / RAND_MAX *(W_MAX - W_MIN) - W_MAX;
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
chromo[i].nn_initial.w[j] = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
}
chromo[i].A = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo[i].B = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo[i].C = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo[i].D = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
for (int num_fun = 0; num_fun < BENCHMARK_NUM*PER_BENCHMARK_TIMES; num_fun++)
{
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
chromo[i].nn[num_fun].w[j] = chromo[i].nn_initial.w[j];
}
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
chromo[i].nn[num_fun].input_w[j] = chromo[i].nn_initial.input_w[j];
}
for (int j = 0; j < NEURAL_NUM; j++)
{
chromo[i].nn[num_fun].old_neural[j] = 0.5;
chromo[i].nn[num_fun].new_neural[j] = 0.0;
}
for (int d = 0; d < DIMENSION; d++)
{
chromo[i].initial_position[num_fun][d] = (float)rand() / RAND_MAX * (MAX - MIN) - MAX;
chromo[i].position[num_fun][d] = chromo[i].initial_position[num_fun][d];
}
chromo[i].a[num_fun] = chromo[i].A;
chromo[i].b[num_fun] = chromo[i].B;
chromo[i].c[num_fun] = chromo[i].C;
chromo[i].d[num_fun] = chromo[i].D;
}
}
}
void initial_chromo(struct CHROMO &chromo)
{
time_t tttt;
srand((unsigned int)time(&tttt));
int i = 0;
for (i = 0; i<INPUT_NEURAL_NUM; i++)
{
chromo.nn_initial.input_w[i] = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
}
for (i = 0; i<SINGLE_WEIGHT; i++)
{
chromo.nn_initial.w[i] = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
}
chromo.A = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo.B = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo.C = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
chromo.D = (float)rand() / RAND_MAX * (W_MAX - W_MIN) - W_MAX;
for (int num_fun = 0; num_fun < BENCHMARK_NUM*PER_BENCHMARK_TIMES; num_fun++)
{
for (i = 0; i < SINGLE_WEIGHT; i++)
{
chromo.nn[num_fun].w[i] = chromo.nn_initial.w[i];
}
for (i = 0; i < INPUT_NEURAL_NUM; i++)
{
chromo.nn[num_fun].input_w[i] = chromo.nn_initial.input_w[i];
}
for (i = 0; i < NEURAL_NUM; i++)
{
chromo.nn[num_fun].old_neural[i] = 0.5;
chromo.nn[num_fun].new_neural[i] = 0.0;
}
for (i = 0; i < DIMENSION; i++)
{
chromo.initial_position[num_fun][i] = (float)rand() / RAND_MAX * (MAX - MIN) - MAX;
chromo.position[num_fun][i] = chromo.initial_position[num_fun][i];
}
chromo.a[num_fun] = chromo.A;
chromo.b[num_fun] = chromo.B;
chromo.c[num_fun] = chromo.C;
chromo.d[num_fun] = chromo.D;
}
}
float my_function(struct CHROMO ch[NUM_CHROMO], float fitness[NUM_CHROMO*PER_BENCHMARK_TIMES*BENCHMARK_NUM], struct CHROMO &GA_best_ch, int g)
{
int temp_nn_index[NUM_CHROMO*PER_BENCHMARK_TIMES];//下标
float nn_fitness[BENCHMARK_NUM*PER_BENCHMARK_TIMES][NUM_CHROMO]; //实际通过cec计算得出的适应值
float nn_fitness_one_f[NUM_CHROMO];//所有染色体在同一个函数上的排序
int record_sort_index[NUM_CHROMO]; //1个函数下的NUM_CHROMO*PER_BENCHMARK_TIMES个排名名次
float record_nn_fitness_sort_index[BENCHMARK_NUM*PER_BENCHMARK_TIMES][NUM_CHROMO]; //10个函数下的CHROMOSOME_NUM个NN 名次
float fitness_ranking[BENCHMARK_NUM + 1][NUM_CHROMO];
float GA_fitness[NUM_CHROMO];
float min_fit;
FILE* f_temp_ch;
FILE* f_temp_result = fopen("temp_result.txt", "a");
//FILE* all_f_g = fopen("all_f_g.txt", "a");
FILE* one_g_chromo[NUM_CHROMO + 1];
char fileName[256];
for (int i = 0; i < NUM_CHROMO; i++)
{
sprintf(fileName, "NN/g%d/ch_%d.txt", g + 1, i);
one_g_chromo[i] = fopen(fileName, "w");
if (one_g_chromo[i] == NULL)
{
printf("\n Error: Cannot open ch_%d filoe \n",i);
}
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
fprintf(one_g_chromo[i], "%f\n", ch[i].nn_initial.input_w[j]);
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
fprintf(one_g_chromo[i], "%f\n", ch[i].nn_initial.w[j]);
}
fprintf(one_g_chromo[i], "A:%f\n B:%f\n C:%f\n D:%f\n", ch[i].A, ch[i].B, ch[i].C, ch[i].D);
fclose(one_g_chromo[i]);
}
for (int i = 0; i < BENCHMARK_NUM + 1; i++)
{
for (int j = 0; j < NUM_CHROMO; j++)
{
fitness_ranking[i][j] = 0.0;
}
}
for (int fun_num = 0; fun_num < BENCHMARK_NUM*PER_BENCHMARK_TIMES; fun_num++)
{
for (int i = 0; i < NUM_CHROMO; i++)
{
nn_fitness[fun_num][i] = 0.0;
}
}
//排100个，分别排3次的话
for (int fun_num = 0; fun_num < BENCHMARK_NUM*PER_BENCHMARK_TIMES; fun_num++)
{
for (int i = 0; i < NUM_CHROMO; i++)
{
nn_fitness[fun_num][i] = fitness[fun_num + i *BENCHMARK_NUM*PER_BENCHMARK_TIMES];
//printf("nn_fitness[%d][%d]=%f \t ",fun_num,i,nn_fitness[fun_num][i]);
}
}
//10个函数分别排3次
for (int fun_num = 0; fun_num < BENCHMARK_NUM*PER_BENCHMARK_TIMES; fun_num++)
{
for (int i = 0; i < NUM_CHROMO; i++)
{
nn_fitness_one_f[i] = nn_fitness[fun_num][i]; //NUM_CHROMO个染色体在一个函数上
temp_nn_index[i] = i;
}
Sort(nn_fitness_one_f, NUM_CHROMO, temp_nn_index);
for (int i = 0; i < NUM_CHROMO; i++)
{
record_sort_index[temp_nn_index[i]] = i + 1;
}
for (int i = 0; i < NUM_CHROMO; i++)
{
record_nn_fitness_sort_index[fun_num][i] = (float)record_sort_index[i]; //NUM_CHROMO * BENCHMARK_NUM*PER_BENCHMARK_TIMES个名次 //printf("sort_index[%d][%d]=%f \t ",fun_num,i,record_nn_fitness_sort_index[fun_num][i]);
}
}
for (int i = 0; i < NUM_CHROMO; i++)
{
for (int fun_num = 0; fun_num < BENCHMARK_NUM; fun_num++)
{
for (int k = 0; k < PER_BENCHMARK_TIMES; k++)
{
fitness_ranking[fun_num][i] += record_nn_fitness_sort_index[fun_num + BENCHMARK_NUM * k][i];
}
fitness_ranking[fun_num][i] /= PER_BENCHMARK_TIMES;
}
}
//平均排名
for (int i = 0; i < NUM_CHROMO; i++)
{
float sum = 0;
for (int j = 0; j < BENCHMARK_NUM; j++)
{
sum += fitness_ranking[j][i];
}
fitness_ranking[BENCHMARK_NUM][i] = sum / BENCHMARK_NUM;
GA_fitness[i] = sum / BENCHMARK_NUM;
printf("the %dth chromosome in all function's avg ranking is :%f \n", i + 1, GA_fitness[i]);
//fprintf(all_f_g, "g=%d,f[%d]=%f:\n", g + 1, i + 1, GA_fitness[i]);
}
sprintf(fileName, "NN/g%d/GA_fitness.txt", g + 1);
one_g_chromo[NUM_CHROMO] = fopen(fileName, "a");
if (one_g_chromo[NUM_CHROMO] == NULL)
{
printf("\n Error: Cannot open GA_fitness file \n");
}
for (int i = 0; i < NUM_CHROMO; i++)
{
fprintf(one_g_chromo[NUM_CHROMO], "%f\n", GA_fitness[i]);
}
fclose(one_g_chromo[NUM_CHROMO]);
min_fit = GA_fitness[0]; //当代 找最小排名及对应的网络
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
GA_best_ch.nn_initial.input_w[j] = ch[0].nn_initial.input_w[j];
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
GA_best_ch.nn_initial.w[j] = ch[0].nn_initial.w[j];
}
GA_best_ch.A = ch[0].A;
GA_best_ch.B = ch[0].B;
GA_best_ch.C = ch[0].C;
GA_best_ch.D = ch[0].D;
for (int i = 1; i < NUM_CHROMO; i++)
{
if (GA_fitness[i] < min_fit)
{
min_fit = GA_fitness[i];
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
GA_best_ch.nn_initial.input_w[j] = ch[i].nn_initial.input_w[j];
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
GA_best_ch.nn_initial.w[j] = ch[i].nn_initial.w[j];
}
GA_best_ch.A = ch[i].A;
GA_best_ch.B = ch[i].B;
GA_best_ch.C = ch[i].C;
GA_best_ch.D = ch[i].D;
}
}
sprintf(fileName, "NN/g%d/temp_bestch.txt", g + 1);
f_temp_ch = fopen(fileName, "w");
fprintf(f_temp_ch, "g=%d,the best chromosome:\n", g + 1);
for (int j = 0; j < INPUT_NEURAL_NUM; j++)
{
fprintf(f_temp_ch, "%f\n", GA_best_ch.nn_initial.input_w[j]);
}
for (int j = 0; j < SINGLE_WEIGHT; j++)
{
fprintf(f_temp_ch, "%f\n", GA_best_ch.nn_initial.w[j]);
}
fprintf(f_temp_ch, "A:%f\n B:%f\n C:%f\n D:%f\n", GA_best_ch.A, GA_best_ch.B, GA_best_ch.C, GA_best_ch.D);//当代最佳chromosome
printf("the generation %d min ranking is:%f \n", g + 1, min_fit);
fprintf(f_temp_result, "g=%d,the best:%f\n", g + 1, min_fit);//当代最佳适应值
selection_tournment(ch, GA_fitness, g);
crossover(ch);
mutation(ch);
for (int i = 0; i < NUM_CHROMO; i++)
{
for (int j = 0; j < (PER_BENCHMARK_TIMES*BENCHMARK_NUM); j++)
{
for (int d = 0; d < SINGLE_WEIGHT; d++)
{
ch[i].nn[j].w[d] = ch[i].nn_initial.w[d];
}
for (int k = 0; k < DIMENSION; k++)
{
ch[i].position[j][k] = ch[i].initial_position[j][k];
}
for (int tt = 0; tt < INPUT_NEURAL_NUM; tt++)
{
ch[i].nn[j].input_w[tt] = ch[i].nn_initial.input_w[tt];
}
for (int d = 0; d < NEURAL_NUM; d++)
{
ch[i].nn[j].old_neural[d] = 0.5;
}
ch[i].a[j] = ch[i].A;
ch[i].b[j] = ch[i].B;
ch[i].c[j] = ch[i].C;
ch[i].d[j] = ch[i].D;
}
}
fclose(f_temp_ch);
fclose(f_temp_result);
//fclose(all_f_g);
/*
for (int i = 0; i < NUM_CHROMO + 1; i++)
{
fclose(one_g_chromo[i]);
}
*/
return min_fit;
}
__device__ float hebb(float a, float b, float c, float d, float x, float y)
{
return G*(a*x + b * y + c * x*y + d);
}
__device__ float sigmoid(float x)
{
if (x < -80)
return 0;
else if (x > 80)
return 1;
else
return 1.0F / (1.0F + exp(-1 * x));
}
__device__ void nn_forward_and_update_paramenter(struct CHROMO ch[], int num, float f, int num_fun3, int num_epoch) ////
{
float inputs[INPUT_NEURAL_NUM];
float delta_w[SINGLE_WEIGHT];
int t = 0;
//输入
inputs[0] = f / num_epoch;
inputs[1] = ch[num].position[num_fun3][0] / MAX;
inputs[2] = ch[num].position[num_fun3][1] / MAX;
for (int i = 0; i < SINGLE_WEIGHT; i++)
{
delta_w[i] = 0;
}
//前向传递
for (int i = 0; i < NEURAL_NUM; i++)
{
for (int j = 0; j < NEURAL_NUM; j++)
{
if (i != j)
{
ch[num].nn[num_fun3].new_neural[i] += (ch[num].nn[num_fun3].w[t] * ch[num].nn[num_fun3].old_neural[j]);
t++;
}
}
//printf("dimension %d,neural %d:%f\n",k, i, ch[num].nn[num_fun3][k].new_neural[i]);
if (i < INPUT_NEURAL_NUM)
{
ch[num].nn[num_fun3].new_neural[i] = sigmoid(ch[num].nn[num_fun3].new_neural[i] + ch[num].nn[num_fun3].input_w[i] * inputs[i]);
}
else
{
ch[num].nn[num_fun3].new_neural[i] = sigmoid(ch[num].nn[num_fun3].new_neural[i]);
}
}
//printf("\n");
//计算delta_w
t = 0;
for (int i = 0; i < NEURAL_NUM; i++)
{
for (int j = 0; j < NEURAL_NUM; j++)
{
if (i != j)
{
delta_w[t] = hebb(ch[num].a[num_fun3], ch[num].b[num_fun3], ch[num].c[num_fun3], ch[num].d[num_fun3], ch[num].nn[num_fun3].old_neural[j], ch[num].nn[num_fun3].old_neural[i]);
t++;
}
}
}
//更新神经元
for (int i = 0; i < NEURAL_NUM; i++)
{
ch[num].nn[num_fun3].old_neural[i] = ch[num].nn[num_fun3].new_neural[i];
ch[num].nn[num_fun3].new_neural[i] = 0;
}
//更新权重
t = 0;
for (int i = 0; i < NEURAL_NUM; i++)
{
for (int j = 0; j < NEURAL_NUM; j++)
{
if (i != j)
{
ch[num].nn[num_fun3].w[t] = (ch[num].nn[num_fun3].w[t] + delta_w[t])*0.99;
t++;
}
}
}
}
__device__ float benchmark(int funnum, float x[][DIMENSION], int num) //some simple functions
{
int a = funnum;
float f, sum1, sum2;
int i;
f = 0.0;
i = 0;
sum1 = 0.0;
sum2 = 0.0;
switch (a)
{
case 0: //sphere function
{
f = 0.0;
for (i = 0; i < DIMENSION; i++)
{
f += x[num][i] * x[num][i];
}
return(f);
}
case 1: //elliptic function
{ f = 0.0;
for (i = 0; i < DIMENSION; i++)
{
f += pow(pow(10.0, 6.0), i / (DIMENSION - 1))*x[num][i] * x[num][i];
}
return(f);
}
case 2: //rastrigin's function
{ f = 0.0;
for (i = 0; i < DIMENSION; i++)
{
f += (x[num][i] * x[num][i] - 10.0*cos(2.0*PI*x[num][i]) + 10.0);
}
return(f);
}
case 3: //ackley function
{
for (i = 0; i < DIMENSION; i++)
{
sum1 += x[num][i] * x[num][i];
sum2 += cos(2.0*PI*x[num][i]);
}
sum1 = -0.2*sqrt(sum1 / DIMENSION);
sum2 = sum2 / DIMENSION;
f = E - 20.0*exp(sum1) - exp(sum2) + 20.0;
return(f);
}
case 4: //rosenbrock function
{
for (i = 0; i < DIMENSION - 1; i++)
{
sum1 = x[num][i] * x[num][i] - x[num][i + 1];
sum2 = x[num][i] - 1;
f += 100.0*sum1*sum1 + sum2 * sum2;
}
return(f);
}
case 5: //bent cigar function
{
for (i = 1; i < DIMENSION; i++)
{
f += pow(10.0, 6.0)*x[num][i] * x[num][i];
}
f += x[num][0] * x[num][0];
return f;
}
case 6: //zakharov function
{
for (i = 0; i < DIMENSION; i++)
{
float z = x[num][i];
sum1 += pow(z, 2);
sum2 += 0.5*z;
}
f = sum1 + pow(sum2, 2) + pow(sum2, 4);
return(f);
}
case 7: //schwefel function
{
for (i = 0; i < DIMENSION; i++)
{
for (int j = 0; j < i; j++)
{
sum1 += x[num][i] * x[num][i];
}
sum1 = sum1 * sum1;
f += sum1;
}
return(f);
}
case 8: //griewank's function
{
for (i = 0; i < DIMENSION; i++)
{
sum1 += x[num][i] * x[num][i];
sum2 *= cos(x[num][i] / sqrt(1.0 + i));
}
f = sum1 / 4000.0 - sum2 + 1.0;
return(f);
}
default: //discus function
f = pow(10.0, 6.0)*x[num][0] * x[num][0];
for (i = 1; i < DIMENSION; i++)
{
f += x[num][i] * x[num][i];
}
return(f);
}
}
__device__ float thread_sort(int sort_num, struct IN_FITNESS in_f[], int num, float p)
{
float a = 0, count = 0;
for (int i = 0; i < sort_num - 1; i++)
{
for (int j = 0; j < sort_num - i - 1; j++)
{
if (in_f[num].f[j] > in_f[num].f[j + 1])
{
a = in_f[num].f[j];
in_f[num].f[j] = in_f[num].f[j + 1];
in_f[num].f[j + 1] = a;
}
}
}
for (int i = 0; i < sort_num; i++)
{
if (p == in_f[num].f[i])
{
return count + 1;
}
else
{
count++;
}
}
return 0;
}
__global__ void kernel(struct CHROMO ch[NUM_CHROMO], float fitness[BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO], struct IN_FITNESS in_f[BENCHMARK_NUM*NUM_CHROMO*PER_BENCHMARK_TIMES], struct IN_POSITION in_p[BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO])
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int i,d;
if (idx <BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO)
{
float value_position;
int num_epoch = 0;
float ff = 0;
int num = (idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES)) % BENCHMARK_NUM;
for (num_epoch = 0; num_epoch<THREAD_EPOCH; num_epoch++)
{
for (d = 0; d < DIMENSION; d++)
{
in_p[idx].p[num_epoch][d] = ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].position[idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES)][d];
}
in_f[idx].f[num_epoch] = benchmark(num, ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].position, idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES));
//printf("ff:%f \n", in_f[idx].f[num_epoch]);
ff = thread_sort((num_epoch + 1), in_f, idx, in_f[idx].f[num_epoch]);
//printf("epoch %d ff: %f\n ", num_epoch, ff);
for (i = 0; i < STEPS; i++)
{
nn_forward_and_update_paramenter(ch, idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES), ff, idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES), (num_epoch + 1));
}
for (d = 0; d < DIMENSION; d++)
{
ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].position[idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES)][d] += (ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].nn[idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].old_neural[NEURAL_NUM - (d + 1)] * (DELTA_X_MAX - DELTA_X_MIN) - DELTA_X_MAX)* MAX;
}
}
fitness[idx] = benchmark(num, ch[idx / (BENCHMARK_NUM*PER_BENCHMARK_TIMES)].position, idx % (BENCHMARK_NUM*PER_BENCHMARK_TIMES));
printf("in fitness[%d]: %f\n", idx, fitness[idx]);
}
}
int main()
{
struct CHROMO *h_ch = (struct CHROMO *)malloc(sizeof(CHROMO)*NUM_CHROMO); //主机端的染色体数组
struct CHROMO *d_ch; //设备端的
struct IN_FITNESS *h_in_fitness = (struct IN_FITNESS *)malloc(sizeof(IN_FITNESS)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
struct IN_FITNESS *d_in_fitness;
struct IN_POSITION *h_in_position = (struct IN_POSITION *)malloc(sizeof(IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
struct IN_POSITION *d_in_position = (struct IN_POSITION *)malloc(sizeof(IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
float *d_fitness; //设备端的一维适应值数组
float *h_fitness = (float *)malloc(sizeof(float)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);//主机端的
int i, g, j, d;
struct CHROMO GA_best_ch; //每代最佳的染色体
struct CHROMO history_best_ch; //历史最佳的染色体
float min_fit; //每代最佳的适应值
float the_min_fit_inallG; //历史最佳的适应值
int record_g = 0;
int device_id = DEVICE_NUM;
FILE* f_results = fopen("GA200results.txt", "a");
FILE* f_history_ch = fopen("history_bestch.txt", "a");
//FILE *f_position = fopen("f_position.txt", "a");
if (f_results == NULL || f_history_ch == NULL)
{
printf("failed to open f file\n");
system("pause");
}
srand((unsigned)time(NULL));
for (i = 0; i < BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
h_fitness[i] = 0;
}
for (i = 0; i < BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
for (j = 0; j < THREAD_EPOCH; j++)
{
h_in_fitness[i].f[j] = 0.0;
}
}
for (i = 0; i<BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
for (j = 0; j<THREAD_EPOCH; j++)
{
for (d = 0; d<DIMENSION; d++)
{
h_in_position[i].p[j][d] = 0.0;
}
}
}
initial_chromo(h_ch);
initial_chromo(GA_best_ch);
initial_chromo(history_best_ch);
//dim3 grid(BLOCK);
//dim3 threads(THREAD);
hipSetDevice(device_id);
for (g = 0; g < EPOCH; g++)
{
hipMalloc((void **)&d_fitness, sizeof(float)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
hipMalloc((struct CHROMO **)&d_ch, sizeof(struct CHROMO) * NUM_CHROMO);
hipMalloc((struct IN_FITNESS **)&d_in_fitness, sizeof(struct IN_FITNESS)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
hipMalloc((struct IN_POSITION **)&d_in_position, sizeof(struct IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO);
hipMemcpy(d_ch, h_ch, sizeof(struct CHROMO) * NUM_CHROMO, hipMemcpyHostToDevice);
hipMemcpy(d_fitness, h_fitness, sizeof(float)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, hipMemcpyHostToDevice);
hipMemcpy(d_in_fitness, h_in_fitness, sizeof(struct IN_FITNESS)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, hipMemcpyHostToDevice);
hipMemcpy(d_in_position, h_in_position, sizeof(struct IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, hipMemcpyHostToDevice);
kernel <<<BLOCK, THREAD >>> (d_ch, d_fitness, d_in_fitness, d_in_position);
hipDeviceSynchronize();
hipMemcpy(h_fitness, d_fitness, sizeof(float)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, hipMemcpyDeviceToHost);
hipMemcpy(h_in_position, d_in_position, sizeof(struct IN_POSITION)*BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO, hipMemcpyDeviceToHost);
//cudaMemcpy(h_ch, d_ch, sizeof(struct CHROMO)*NUM_CHROMO, cudaMemcpyDeviceToHost);
/*
fprintf(f_position, "第%d代:\n", g + 1);
for (i = 0; i < BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
fprintf(f_position, "第%d个染色体\n", i + 1);
for (j = 0; j < THREAD_EPOCH; j++)
{
fprintf(f_position, "第%d次移动\t\t\t", j + 1);
for (d = 0; d < DIMENSION; d++)
{
fprintf(f_position, "%f\t\t", h_in_position[i].p[j][d]);
}
}
}
*/
/*
for (i = 0; i < BENCHMARK_NUM*PER_BENCHMARK_TIMES*NUM_CHROMO; i++)
{
printf("out fitness[%d] = %f\n", i, h_fitness[i]);
}
*/
min_fit = my_function(h_ch, h_fitness, GA_best_ch, g);
if (g == 0)
{
the_min_fit_inallG = min_fit;
for (i = 0; i < INPUT_NEURAL_NUM; i++)
{
history_best_ch.nn_initial.input_w[i] = GA_best_ch.nn_initial.input_w[i];
fprintf(f_history_ch, "%f\n", history_best_ch.nn_initial.input_w[i]);
}
for (j = 0; j < SINGLE_WEIGHT; j++)
{
history_best_ch.nn_initial.w[j] = GA_best_ch.nn_initial.w[j];
fprintf(f_history_ch, "%f\n", history_best_ch.nn_initial.w[j]);
}
history_best_ch.A = GA_best_ch.A;
history_best_ch.B = GA_best_ch.B;
history_best_ch.C = GA_best_ch.C;
history_best_ch.D = GA_best_ch.D;
fprintf(f_history_ch, "A:%f\n B:%f\n C:%f\n D:%f\n", history_best_ch.A, history_best_ch.B, history_best_ch.C, history_best_ch.D);
record_g = g;
}
if (min_fit < the_min_fit_inallG)
{
the_min_fit_inallG = min_fit;
for (i = 0; i < INPUT_NEURAL_NUM; i++)
{
history_best_ch.nn_initial.input_w[i] = GA_best_ch.nn_initial.input_w[i];
fprintf(f_history_ch, "%f\n", history_best_ch.nn_initial.input_w[i]);
}
for (j = 0; j < SINGLE_WEIGHT; j++)
{
history_best_ch.nn_initial.w[j] = GA_best_ch.nn_initial.w[j];
fprintf(f_history_ch, "%f\n", history_best_ch.nn_initial.w[j]);
}
history_best_ch.A = GA_best_ch.A;
history_best_ch.B = GA_best_ch.B;
history_best_ch.C = GA_best_ch.C;
history_best_ch.D = GA_best_ch.D;
fprintf(f_history_ch, "A:%f\n B:%f\n C:%f\n D:%f\n", history_best_ch.A, history_best_ch.B, history_best_ch.C, history_best_ch.D);
record_g = g;
}
printf("the history min ranking is:%f \n", the_min_fit_inallG);
fprintf(f_results, "history best is in g=%d:%f\n", record_g + 1, the_min_fit_inallG);
hipFree(d_fitness);
hipFree(d_ch);
hipFree(d_in_fitness);
hipFree(d_in_position);
}//GA代
fclose(f_history_ch);
//fclose(f_position);
fclose(f_results);
free(h_ch);
free(h_fitness);
free(h_in_fitness);
free(h_in_position);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void computePCfeatures(const double *Params, const int *counter, const float *dataraw, const int *st, const int *id, const float *x, const float *W, const float *U, const float *mu, const int *iW, const int *iC, const float *wPCA, float *featPC){
volatile __shared__ float sPCA[81 * NrankMax], sW[81 * NrankMax], sU[NchanMax * NrankMax];
volatile __shared__ int iU[NchanMax];
int bid, nt0, t, tidx, tidy, k, NT, ind, Nchan, NchanU, Nfilt, Nrank;
float X = 0.0f, Y = 0.0f;
NT = (int) Params[0];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
if (tidy==0)
iU[tidx] = iC[tidx + NchanU * iW[bid]];
__syncthreads();
sU[tidx + tidy*NchanU]= U[iU[tidx] + Nchan * bid + Nchan * Nfilt * tidy];
while (tidx<nt0){
sW[tidx + tidy*nt0] = W[tidx + bid*nt0 + Nfilt * nt0 * tidy];
sPCA[tidx + tidy*nt0] = wPCA[tidx + nt0 * tidy];
tidx += blockDim.x;
}
tidx = threadIdx.x;
__syncthreads();
// first, compute wPCA projections of the filter
Y = 0.0f;
for (k =0; k<Nrank; k++){
X = 0.0f;
for (t=0;t<nt0;t++)
X += sW[t + k*nt0] * sPCA[t + tidy * nt0];
Y += X * sU[tidx + k*NchanU];
}
//now for each matching spike, compute the features
for(ind=0; ind<counter[0];ind++)
if (id[ind]==bid){
X = Y * x[ind]; // - mu[bid]);
for (t=0;t<nt0; t++)
X += dataraw[st[ind] + t + NT * iU[tidx]] * sPCA[t + nt0*tidy];
featPC[tidx + tidy*NchanU + ind * NchanU*Nrank] = X;
}
} | .file "tmpxft_0012e629_00000000-6_computePCfeatures.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.type _Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, @function
_Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 304(%rsp), %rax
movq %rax, 56(%rsp)
movq 312(%rsp), %rax
movq %rax, 48(%rsp)
movq 320(%rsp), %rax
movq %rax, 40(%rsp)
movq 328(%rsp), %rax
movq %rax, 32(%rsp)
movq 336(%rsp), %rax
movq %rax, 24(%rsp)
movq 344(%rsp), %rax
movq %rax, 16(%rsp)
movq 352(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 312
pushq 120(%rsp)
.cfi_def_cfa_offset 320
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, .-_Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.globl _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.type _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, @function
_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, .-_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void computePCfeatures(const double *Params, const int *counter, const float *dataraw, const int *st, const int *id, const float *x, const float *W, const float *U, const float *mu, const int *iW, const int *iC, const float *wPCA, float *featPC){
volatile __shared__ float sPCA[81 * NrankMax], sW[81 * NrankMax], sU[NchanMax * NrankMax];
volatile __shared__ int iU[NchanMax];
int bid, nt0, t, tidx, tidy, k, NT, ind, Nchan, NchanU, Nfilt, Nrank;
float X = 0.0f, Y = 0.0f;
NT = (int) Params[0];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
if (tidy==0)
iU[tidx] = iC[tidx + NchanU * iW[bid]];
__syncthreads();
sU[tidx + tidy*NchanU]= U[iU[tidx] + Nchan * bid + Nchan * Nfilt * tidy];
while (tidx<nt0){
sW[tidx + tidy*nt0] = W[tidx + bid*nt0 + Nfilt * nt0 * tidy];
sPCA[tidx + tidy*nt0] = wPCA[tidx + nt0 * tidy];
tidx += blockDim.x;
}
tidx = threadIdx.x;
__syncthreads();
// first, compute wPCA projections of the filter
Y = 0.0f;
for (k =0; k<Nrank; k++){
X = 0.0f;
for (t=0;t<nt0;t++)
X += sW[t + k*nt0] * sPCA[t + tidy * nt0];
Y += X * sU[tidx + k*NchanU];
}
//now for each matching spike, compute the features
for(ind=0; ind<counter[0];ind++)
if (id[ind]==bid){
X = Y * x[ind]; // - mu[bid]);
for (t=0;t<nt0; t++)
X += dataraw[st[ind] + t + NT * iU[tidx]] * sPCA[t + nt0*tidy];
featPC[tidx + tidy*NchanU + ind * NchanU*Nrank] = X;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void computePCfeatures(const double *Params, const int *counter, const float *dataraw, const int *st, const int *id, const float *x, const float *W, const float *U, const float *mu, const int *iW, const int *iC, const float *wPCA, float *featPC){
volatile __shared__ float sPCA[81 * NrankMax], sW[81 * NrankMax], sU[NchanMax * NrankMax];
volatile __shared__ int iU[NchanMax];
int bid, nt0, t, tidx, tidy, k, NT, ind, Nchan, NchanU, Nfilt, Nrank;
float X = 0.0f, Y = 0.0f;
NT = (int) Params[0];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
if (tidy==0)
iU[tidx] = iC[tidx + NchanU * iW[bid]];
__syncthreads();
sU[tidx + tidy*NchanU]= U[iU[tidx] + Nchan * bid + Nchan * Nfilt * tidy];
while (tidx<nt0){
sW[tidx + tidy*nt0] = W[tidx + bid*nt0 + Nfilt * nt0 * tidy];
sPCA[tidx + tidy*nt0] = wPCA[tidx + nt0 * tidy];
tidx += blockDim.x;
}
tidx = threadIdx.x;
__syncthreads();
// first, compute wPCA projections of the filter
Y = 0.0f;
for (k =0; k<Nrank; k++){
X = 0.0f;
for (t=0;t<nt0;t++)
X += sW[t + k*nt0] * sPCA[t + tidy * nt0];
Y += X * sU[tidx + k*NchanU];
}
//now for each matching spike, compute the features
for(ind=0; ind<counter[0];ind++)
if (id[ind]==bid){
X = Y * x[ind]; // - mu[bid]);
for (t=0;t<nt0; t++)
X += dataraw[st[ind] + t + NT * iU[tidx]] * sPCA[t + nt0*tidy];
featPC[tidx + tidy*NchanU + ind * NchanU*Nrank] = X;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void computePCfeatures(const double *Params, const int *counter, const float *dataraw, const int *st, const int *id, const float *x, const float *W, const float *U, const float *mu, const int *iW, const int *iC, const float *wPCA, float *featPC){
volatile __shared__ float sPCA[81 * NrankMax], sW[81 * NrankMax], sU[NchanMax * NrankMax];
volatile __shared__ int iU[NchanMax];
int bid, nt0, t, tidx, tidy, k, NT, ind, Nchan, NchanU, Nfilt, Nrank;
float X = 0.0f, Y = 0.0f;
NT = (int) Params[0];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
if (tidy==0)
iU[tidx] = iC[tidx + NchanU * iW[bid]];
__syncthreads();
sU[tidx + tidy*NchanU]= U[iU[tidx] + Nchan * bid + Nchan * Nfilt * tidy];
while (tidx<nt0){
sW[tidx + tidy*nt0] = W[tidx + bid*nt0 + Nfilt * nt0 * tidy];
sPCA[tidx + tidy*nt0] = wPCA[tidx + nt0 * tidy];
tidx += blockDim.x;
}
tidx = threadIdx.x;
__syncthreads();
// first, compute wPCA projections of the filter
Y = 0.0f;
for (k =0; k<Nrank; k++){
X = 0.0f;
for (t=0;t<nt0;t++)
X += sW[t + k*nt0] * sPCA[t + tidy * nt0];
Y += X * sU[tidx + k*NchanU];
}
//now for each matching spike, compute the features
for(ind=0; ind<counter[0];ind++)
if (id[ind]==bid){
X = Y * x[ind]; // - mu[bid]);
for (t=0;t<nt0; t++)
X += dataraw[st[ind] + t + NT * iU[tidx]] * sPCA[t + nt0*tidy];
featPC[tidx + tidy*NchanU + ind * NchanU*Nrank] = X;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.globl _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.p2align 8
.type _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf,@function
_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf:
s_load_b64 s[12:13], s[0:1], 0x0
v_bfe_u32 v7, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s2, s15
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b128 s[8:11], s[12:13], 0x48
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v5, s[10:11]
s_clause 0x2
s_load_b64 s[10:11], s[12:13], 0x30
s_load_b128 s[4:7], s[12:13], 0x0
s_load_b64 s[12:13], s[12:13], 0x20
v_cmpx_eq_u32_e32 0, v7
s_cbranch_execz .LBB0_2
s_load_b128 s[16:19], s[0:1], 0x48
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[20:21], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s16, s16, s20
s_addc_u32 s17, s17, s21
s_load_b32 s3, s[16:17], 0x0
s_mov_b64 s[16:17], src_shared_base
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s3, v5, v[4:5]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s18, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
global_load_b32 v2, v[0:1], off
v_lshl_add_u32 v0, v4, 2, 0x920
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cndmask_b32_e64 v1, 0, s17, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[0:1], v2 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
v_lshl_add_u32 v0, v4, 2, 0x920
s_mov_b64 s[14:15], src_shared_base
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cvt_i32_f64_e32 v8, s[6:7]
v_cvt_i32_f64_e32 v3, s[8:9]
s_load_b64 s[6:7], s[0:1], 0x38
v_cvt_i32_f64_e32 v12, s[12:13]
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cndmask_b32_e64 v1, 0, s15, vcc_lo
s_mov_b32 s16, exec_lo
flat_load_b32 v2, v[0:1] glc dlc
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v7, v8, s[2:3]
v_readfirstlane_b32 s3, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v6, v7, s3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[10:11], null, v9, v3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[2:3], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v11, v[2:3], off
v_mad_u64_u32 v[2:3], null, v7, v5, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v3, v2, 2, 0x7a0
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v9, 0, v3, vcc_lo
v_cndmask_b32_e64 v10, 0, s15, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[9:10], v11 dlc
s_waitcnt_vscnt null, 0x0
v_cmpx_lt_i32_e64 v4, v12
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x30
s_load_b64 s[8:9], s[0:1], 0x58
v_mad_u64_u32 v[9:10], null, v7, v8, s[2:3]
v_mov_b32_e32 v7, v4
s_add_u32 s12, s0, 0x68
s_addc_u32 s13, s1, 0
s_mov_b32 s17, 0
s_mov_b64 s[14:15], src_shared_base
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v3, v9, s3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v7, v3
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v12, v[8:9], off
v_add_nc_u32_e32 v8, v7, v6
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b32_e32 v13, 2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_cmp_ne_u32_e32 vcc_lo, -1, v13
v_cndmask_b32_e32 v10, 0, v13, vcc_lo
v_cndmask_b32_e64 v11, 0, s15, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[10:11], v12 dlc
s_waitcnt_vscnt null, 0x0
global_load_b32 v10, v[8:9], off
v_add_nc_u32_e32 v8, 0x3d0, v13
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v8
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cndmask_b32_e64 v9, 0, s15, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[8:9], v10 dlc
s_waitcnt_vscnt null, 0x0
s_load_b32 s14, s[12:13], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s14, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, s14, v7
v_cmp_le_i32_e32 vcc_lo, s3, v7
s_or_b32 s17, vcc_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s16
v_cvt_i32_f64_e32 v7, s[10:11]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, 1, v7
s_cbranch_vccnz .LBB0_11
v_lshl_add_u32 v8, v6, 2, 0x3d0
v_mov_b32_e32 v3, 0
s_cmp_gt_i32 s3, 0
s_mov_b32 s8, 0
s_cselect_b32 s9, -1, 0
s_lshl_b32 s10, s3, 2
s_mov_b32 s11, 0
s_mov_b64 s[6:7], src_shared_base
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
v_mad_u64_u32 v[10:11], null, s11, v5, v[4:5]
s_add_i32 s11, s11, 1
s_add_i32 s8, s8, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v10, v10, 2, 0x7a0
v_cmp_ne_u32_e32 vcc_lo, -1, v10
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cndmask_b32_e64 v11, 0, s7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s11, v7
flat_load_b32 v10, v[10:11] glc dlc
s_waitcnt vmcnt(0)
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v9, v10
s_cbranch_vccnz .LBB0_12
.LBB0_8:
v_mov_b32_e32 v9, 0
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_7
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, v8
s_mov_b32 s6, s8
s_mov_b32 s12, s3
.p2align 6
.LBB0_10:
s_cmp_lg_u32 s6, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v10
s_cselect_b32 s13, s6, 0
s_cselect_b32 s14, s7, 0
v_dual_mov_b32 v13, s13 :: v_dual_mov_b32 v14, s14
v_cndmask_b32_e64 v12, 0, s7, vcc_lo
v_cndmask_b32_e32 v11, 0, v10, vcc_lo
s_add_i32 s12, s12, -1
flat_load_b32 v13, v[13:14] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v11, v[11:12] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v10, 4, v10
s_add_i32 s6, s6, 4
s_cmp_lg_u32 s12, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v9, v13, v11
s_cbranch_scc1 .LBB0_10
s_branch .LBB0_7
.LBB0_11:
v_mov_b32_e32 v3, 0
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[6:7], s[0:1], 0x8
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v8, v4, s[6:7]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v8
s_cbranch_vccnz .LBB0_20
v_cvt_i32_f64_e32 v9, s[4:5]
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b64 s[12:13], s[0:1], 0x60
v_mul_lo_u32 v5, v5, v7
v_lshl_add_u32 v6, v6, 2, 0x3d0
s_cmp_gt_i32 s3, 0
s_mov_b32 s15, 0
s_cselect_b32 s18, -1, 0
s_mov_b64 s[0:1], src_shared_base
s_mov_b32 s14, s15
s_branch .LBB0_16
.LBB0_14:
v_mad_u64_u32 v[10:11], null, v5, s14, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s12, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
global_store_b32 v[10:11], v7, off
.LBB0_15:
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s14, v8
s_cbranch_vccz .LBB0_20
.LBB0_16:
s_lshl_b64 s[16:17], s[14:15], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s20, s8, s16
s_addc_u32 s21, s9, s17
s_load_b32 s0, s[20:21], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s0, s2
s_cbranch_scc1 .LBB0_15
s_add_u32 s20, s10, s16
s_addc_u32 s21, s11, s17
s_and_not1_b32 vcc_lo, exec_lo, s18
global_load_b32 v7, v4, s[20:21]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, v3, v7
s_cbranch_vccnz .LBB0_14
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
v_mov_b32_e32 v10, v6
s_load_b32 s16, s[16:17], 0x0
s_mov_b32 s19, s3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s17, s16, 31
.p2align 6
.LBB0_19:
flat_load_b32 v11, v[0:1] glc dlc
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v10
s_add_i32 s19, s19, -1
v_cndmask_b32_e64 v13, 0, s1, vcc_lo
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v11, v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_u32 v11, s0, s16, v11
s_add_u32 s16, s16, 1
v_add_co_ci_u32_e64 v12, s0, s17, v12, s0
s_addc_u32 s17, s17, 0
s_cmp_lg_u32 s19, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[14:15], 2, v[11:12]
v_cndmask_b32_e32 v12, 0, v10, vcc_lo
v_add_co_u32 v14, vcc_lo, s4, v14
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
global_load_b32 v11, v[14:15], off
flat_load_b32 v12, v[12:13] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_fmac_f32 v7, v11, v12 :: v_dual_add_nc_u32 v10, 4, v10
s_cbranch_scc1 .LBB0_19
s_branch .LBB0_14
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.amdhsa_group_segment_fixed_size 2464
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 360
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, .Lfunc_end0-_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .offset: 104
.size: 4
.value_kind: hidden_block_count_x
- .offset: 108
.size: 4
.value_kind: hidden_block_count_y
- .offset: 112
.size: 4
.value_kind: hidden_block_count_z
- .offset: 116
.size: 2
.value_kind: hidden_group_size_x
- .offset: 118
.size: 2
.value_kind: hidden_group_size_y
- .offset: 120
.size: 2
.value_kind: hidden_group_size_z
- .offset: 122
.size: 2
.value_kind: hidden_remainder_x
- .offset: 124
.size: 2
.value_kind: hidden_remainder_y
- .offset: 126
.size: 2
.value_kind: hidden_remainder_z
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 168
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2464
.kernarg_segment_align: 8
.kernarg_segment_size: 360
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void computePCfeatures(const double *Params, const int *counter, const float *dataraw, const int *st, const int *id, const float *x, const float *W, const float *U, const float *mu, const int *iW, const int *iC, const float *wPCA, float *featPC){
volatile __shared__ float sPCA[81 * NrankMax], sW[81 * NrankMax], sU[NchanMax * NrankMax];
volatile __shared__ int iU[NchanMax];
int bid, nt0, t, tidx, tidy, k, NT, ind, Nchan, NchanU, Nfilt, Nrank;
float X = 0.0f, Y = 0.0f;
NT = (int) Params[0];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
if (tidy==0)
iU[tidx] = iC[tidx + NchanU * iW[bid]];
__syncthreads();
sU[tidx + tidy*NchanU]= U[iU[tidx] + Nchan * bid + Nchan * Nfilt * tidy];
while (tidx<nt0){
sW[tidx + tidy*nt0] = W[tidx + bid*nt0 + Nfilt * nt0 * tidy];
sPCA[tidx + tidy*nt0] = wPCA[tidx + nt0 * tidy];
tidx += blockDim.x;
}
tidx = threadIdx.x;
__syncthreads();
// first, compute wPCA projections of the filter
Y = 0.0f;
for (k =0; k<Nrank; k++){
X = 0.0f;
for (t=0;t<nt0;t++)
X += sW[t + k*nt0] * sPCA[t + tidy * nt0];
Y += X * sU[tidx + k*NchanU];
}
//now for each matching spike, compute the features
for(ind=0; ind<counter[0];ind++)
if (id[ind]==bid){
X = Y * x[ind]; // - mu[bid]);
for (t=0;t<nt0; t++)
X += dataraw[st[ind] + t + NT * iU[tidx]] * sPCA[t + nt0*tidy];
featPC[tidx + tidy*NchanU + ind * NchanU*Nrank] = X;
}
} | .text
.file "computePCfeatures.hip"
.globl _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf # -- Begin function _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.p2align 4, 0x90
.type _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf,@function
_Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf: # @_Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, .Lfunc_end0-_Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf,@object # @_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.section .rodata,"a",@progbits
.globl _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.p2align 3, 0x0
_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf:
.quad _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.size _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf"
.size .L__unnamed_1, 60
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012e629_00000000-6_computePCfeatures.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.type _Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, @function
_Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 304(%rsp), %rax
movq %rax, 56(%rsp)
movq 312(%rsp), %rax
movq %rax, 48(%rsp)
movq 320(%rsp), %rax
movq %rax, 40(%rsp)
movq 328(%rsp), %rax
movq %rax, 32(%rsp)
movq 336(%rsp), %rax
movq %rax, 24(%rsp)
movq 344(%rsp), %rax
movq %rax, 16(%rsp)
movq 352(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 312
pushq 120(%rsp)
.cfi_def_cfa_offset 320
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, .-_Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.globl _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.type _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, @function
_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z73__device_stub__Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_PfPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, .-_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computePCfeatures.hip"
.globl _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf # -- Begin function _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.p2align 4, 0x90
.type _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf,@function
_Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf: # @_Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, .Lfunc_end0-_Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf,@object # @_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.section .rodata,"a",@progbits
.globl _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.p2align 3, 0x0
_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf:
.quad _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.size _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf"
.size .L__unnamed_1, 60
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17computePCfeaturesPKdPKiPKfS2_S2_S4_S4_S4_S4_S2_S2_S4_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
class MyClass;
__global__ void kernel(int *a, unsigned int N);
class MyClass {
public:
MyClass(int len) {
length = len;
cudaMalloc((void **)&d_data, sizeof(int)*length);
cudaMemset((void *)d_data, 0, sizeof(int)*length);
};
~MyClass() {
cudaFree((void *)d_data);
printf("%s\n","cudafree" );
};
void run(dim3 grid,dim3 block) {
kernel<<<grid, block>>>(d_data, length);
};
void set(int* h_data)
{
cudaMemcpy(d_data,h_data,sizeof(int)*length,cudaMemcpyHostToDevice);
}
int* getData(void) {
return d_data;
};
int getLength(void)
{
return length;
}
void show(void)
{
int h_data[length];
cudaMemcpy(h_data, getData(), sizeof(int)*length, cudaMemcpyDeviceToHost);
for (int i=0; i<length; i++) {
std::cout << h_data[i] << " ";
}
std::cout << std::endl;
}
public:
int *d_data;
int length;
};
__global__ void kernel(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += i;
}
}
__global__ void kernel1(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += 2*i;
}
}
class MyClass1:public MyClass
{
public:
MyClass1(int len):MyClass(len){};
void run(dim3 grid,dim3 block)
{
kernel1<<<grid, block>>>(d_data, length);
};
};
int main(void) {
int arraySize = 20;
int* testArr = new int[arraySize];
for (int i = 0; i < arraySize; ++i)
{
testArr[i] = i;
}
// MyClass c(arraySize); //直接声明的对象是定义在栈上的，会被自动释放
// c.run();
// c.show();
dim3 grid(1);
dim3 block(arraySize);
MyClass1 *c = new MyClass1(arraySize);
c->set(testArr);
c->run(grid,block);
c->show();
delete c; //用指针指向new出来的对象是存放在堆上的，必须要手动delete对象，否则对象不会被释放掉。
} | code for sm_80
Function : _Z7kernel1Pij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ LEA R5, R0, R5, 0x1 ; /* 0x0000000500057211 */
/* 0x004fca00078e08ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6kernelPij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
class MyClass;
__global__ void kernel(int *a, unsigned int N);
class MyClass {
public:
MyClass(int len) {
length = len;
cudaMalloc((void **)&d_data, sizeof(int)*length);
cudaMemset((void *)d_data, 0, sizeof(int)*length);
};
~MyClass() {
cudaFree((void *)d_data);
printf("%s\n","cudafree" );
};
void run(dim3 grid,dim3 block) {
kernel<<<grid, block>>>(d_data, length);
};
void set(int* h_data)
{
cudaMemcpy(d_data,h_data,sizeof(int)*length,cudaMemcpyHostToDevice);
}
int* getData(void) {
return d_data;
};
int getLength(void)
{
return length;
}
void show(void)
{
int h_data[length];
cudaMemcpy(h_data, getData(), sizeof(int)*length, cudaMemcpyDeviceToHost);
for (int i=0; i<length; i++) {
std::cout << h_data[i] << " ";
}
std::cout << std::endl;
}
public:
int *d_data;
int length;
};
__global__ void kernel(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += i;
}
}
__global__ void kernel1(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += 2*i;
}
}
class MyClass1:public MyClass
{
public:
MyClass1(int len):MyClass(len){};
void run(dim3 grid,dim3 block)
{
kernel1<<<grid, block>>>(d_data, length);
};
};
int main(void) {
int arraySize = 20;
int* testArr = new int[arraySize];
for (int i = 0; i < arraySize; ++i)
{
testArr[i] = i;
}
// MyClass c(arraySize); //直接声明的对象是定义在栈上的，会被自动释放
// c.run();
// c.show();
dim3 grid(1);
dim3 block(arraySize);
MyClass1 *c = new MyClass1(arraySize);
c->set(testArr);
c->run(grid,block);
c->show();
delete c; //用指针指向new出来的对象是存放在堆上的，必须要手动delete对象，否则对象不会被释放掉。
} | .file "tmpxft_000d6cd5_00000000-6_cuda_cpp_class.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3690:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3690:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPijPij
.type _Z26__device_stub__Z6kernelPijPij, @function
_Z26__device_stub__Z6kernelPijPij:
.LFB3712:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3712:
.size _Z26__device_stub__Z6kernelPijPij, .-_Z26__device_stub__Z6kernelPijPij
.globl _Z6kernelPij
.type _Z6kernelPij, @function
_Z6kernelPij:
.LFB3713:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPijPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3713:
.size _Z6kernelPij, .-_Z6kernelPij
.globl _Z27__device_stub__Z7kernel1PijPij
.type _Z27__device_stub__Z7kernel1PijPij, @function
_Z27__device_stub__Z7kernel1PijPij:
.LFB3714:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel1Pij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3714:
.size _Z27__device_stub__Z7kernel1PijPij, .-_Z27__device_stub__Z7kernel1PijPij
.globl _Z7kernel1Pij
.type _Z7kernel1Pij, @function
_Z7kernel1Pij:
.LFB3715:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel1PijPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3715:
.size _Z7kernel1Pij, .-_Z7kernel1Pij
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "cudafree"
.LC2:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB3684:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3684
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $80, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %rbx
movl $0, %eax
.L20:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L20
movl $16, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
movl $20, 8(%rax)
movl $80, %esi
movq %rax, %rdi
.LEHB1:
call cudaMalloc@PLT
movslq 8(%r12), %rdx
salq $2, %rdx
movq (%r12), %rdi
movl $0, %esi
call cudaMemset@PLT
.LEHE1:
movslq 8(%r12), %rdx
salq $2, %rdx
movq (%r12), %rdi
movl $1, %ecx
movq %rbx, %rsi
.LEHB2:
call cudaMemcpy@PLT
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $20, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L21:
movq %rsp, -88(%rbp)
movslq 8(%r12), %rdx
salq $2, %rdx
leaq 15(%rdx), %rax
movq %rax, %rsi
andq $-16, %rsi
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L22:
cmpq %rcx, %rsp
je .L23
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L22
.L39:
movl 8(%r12), %esi
movq (%r12), %rdi
call _Z27__device_stub__Z7kernel1PijPij
jmp .L21
.L23:
movq %rsi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L24
orq $0, -8(%rsp,%rax)
.L24:
movq %rsp, %r15
movq (%r12), %rsi
movl $2, %ecx
movq %r15, %rdi
call cudaMemcpy@PLT
cmpl $0, 8(%r12)
jle .L25
movl $0, %ebx
leaq _ZSt4cout(%rip), %r14
leaq .LC0(%rip), %r13
.L26:
movl (%r15,%rbx,4), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, 8(%r12)
jg .L26
.L25:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L40
cmpb $0, 56(%rbx)
je .L29
movzbl 67(%rbx), %esi
.L30:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE2:
movq -88(%rbp), %rsp
movq (%r12), %rdi
call cudaFree@PLT
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L40:
.cfi_restore_state
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L42
.LEHB3:
call _ZSt16__throw_bad_castv@PLT
.L42:
call __stack_chk_fail@PLT
.L29:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L34:
endbr64
movq %rax, %rbx
movl $16, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L32
call __stack_chk_fail@PLT
.L32:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE3:
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3684:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3684:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3684-.LLSDACSB3684
.LLSDACSB3684:
.uleb128 .LEHB0-.LFB3684
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3684
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB3684
.uleb128 0
.uleb128 .LEHB2-.LFB3684
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3684
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3684:
.text
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7kernel1Pij"
.LC4:
.string "_Z6kernelPij"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3717:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1Pij(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPij(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3717:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
class MyClass;
__global__ void kernel(int *a, unsigned int N);
class MyClass {
public:
MyClass(int len) {
length = len;
cudaMalloc((void **)&d_data, sizeof(int)*length);
cudaMemset((void *)d_data, 0, sizeof(int)*length);
};
~MyClass() {
cudaFree((void *)d_data);
printf("%s\n","cudafree" );
};
void run(dim3 grid,dim3 block) {
kernel<<<grid, block>>>(d_data, length);
};
void set(int* h_data)
{
cudaMemcpy(d_data,h_data,sizeof(int)*length,cudaMemcpyHostToDevice);
}
int* getData(void) {
return d_data;
};
int getLength(void)
{
return length;
}
void show(void)
{
int h_data[length];
cudaMemcpy(h_data, getData(), sizeof(int)*length, cudaMemcpyDeviceToHost);
for (int i=0; i<length; i++) {
std::cout << h_data[i] << " ";
}
std::cout << std::endl;
}
public:
int *d_data;
int length;
};
__global__ void kernel(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += i;
}
}
__global__ void kernel1(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += 2*i;
}
}
class MyClass1:public MyClass
{
public:
MyClass1(int len):MyClass(len){};
void run(dim3 grid,dim3 block)
{
kernel1<<<grid, block>>>(d_data, length);
};
};
int main(void) {
int arraySize = 20;
int* testArr = new int[arraySize];
for (int i = 0; i < arraySize; ++i)
{
testArr[i] = i;
}
// MyClass c(arraySize); //直接声明的对象是定义在栈上的，会被自动释放
// c.run();
// c.show();
dim3 grid(1);
dim3 block(arraySize);
MyClass1 *c = new MyClass1(arraySize);
c->set(testArr);
c->run(grid,block);
c->show();
delete c; //用指针指向new出来的对象是存放在堆上的，必须要手动delete对象，否则对象不会被释放掉。
} | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
class MyClass;
__global__ void kernel(int *a, unsigned int N);
class MyClass {
public:
MyClass(int len) {
length = len;
hipMalloc((void **)&d_data, sizeof(int)*length);
hipMemset((void *)d_data, 0, sizeof(int)*length);
};
~MyClass() {
hipFree((void *)d_data);
printf("%s\n","cudafree" );
};
void run(dim3 grid,dim3 block) {
kernel<<<grid, block>>>(d_data, length);
};
void set(int* h_data)
{
hipMemcpy(d_data,h_data,sizeof(int)*length,hipMemcpyHostToDevice);
}
int* getData(void) {
return d_data;
};
int getLength(void)
{
return length;
}
void show(void)
{
int h_data[length];
hipMemcpy(h_data, getData(), sizeof(int)*length, hipMemcpyDeviceToHost);
for (int i=0; i<length; i++) {
std::cout << h_data[i] << " ";
}
std::cout << std::endl;
}
public:
int *d_data;
int length;
};
__global__ void kernel(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += i;
}
}
__global__ void kernel1(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += 2*i;
}
}
class MyClass1:public MyClass
{
public:
MyClass1(int len):MyClass(len){};
void run(dim3 grid,dim3 block)
{
kernel1<<<grid, block>>>(d_data, length);
};
};
int main(void) {
int arraySize = 20;
int* testArr = new int[arraySize];
for (int i = 0; i < arraySize; ++i)
{
testArr[i] = i;
}
// MyClass c(arraySize); //直接声明的对象是定义在栈上的，会被自动释放
// c.run();
// c.show();
dim3 grid(1);
dim3 block(arraySize);
MyClass1 *c = new MyClass1(arraySize);
c->set(testArr);
c->run(grid,block);
c->show();
delete c; //用指针指向new出来的对象是存放在堆上的，必须要手动delete对象，否则对象不会被释放掉。
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
class MyClass;
__global__ void kernel(int *a, unsigned int N);
class MyClass {
public:
MyClass(int len) {
length = len;
hipMalloc((void **)&d_data, sizeof(int)*length);
hipMemset((void *)d_data, 0, sizeof(int)*length);
};
~MyClass() {
hipFree((void *)d_data);
printf("%s\n","cudafree" );
};
void run(dim3 grid,dim3 block) {
kernel<<<grid, block>>>(d_data, length);
};
void set(int* h_data)
{
hipMemcpy(d_data,h_data,sizeof(int)*length,hipMemcpyHostToDevice);
}
int* getData(void) {
return d_data;
};
int getLength(void)
{
return length;
}
void show(void)
{
int h_data[length];
hipMemcpy(h_data, getData(), sizeof(int)*length, hipMemcpyDeviceToHost);
for (int i=0; i<length; i++) {
std::cout << h_data[i] << " ";
}
std::cout << std::endl;
}
public:
int *d_data;
int length;
};
__global__ void kernel(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += i;
}
}
__global__ void kernel1(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += 2*i;
}
}
class MyClass1:public MyClass
{
public:
MyClass1(int len):MyClass(len){};
void run(dim3 grid,dim3 block)
{
kernel1<<<grid, block>>>(d_data, length);
};
};
int main(void) {
int arraySize = 20;
int* testArr = new int[arraySize];
for (int i = 0; i < arraySize; ++i)
{
testArr[i] = i;
}
// MyClass c(arraySize); //直接声明的对象是定义在栈上的，会被自动释放
// c.run();
// c.show();
dim3 grid(1);
dim3 block(arraySize);
MyClass1 *c = new MyClass1(arraySize);
c->set(testArr);
c->run(grid,block);
c->show();
delete c; //用指针指向new出来的对象是存放在堆上的，必须要手动delete对象，否则对象不会被释放掉。
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPij
.globl _Z6kernelPij
.p2align 8
.type _Z6kernelPij,@function
_Z6kernelPij:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v1
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPij, .Lfunc_end0-_Z6kernelPij
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel1Pij
.globl _Z7kernel1Pij
.p2align 8
.type _Z7kernel1Pij,@function
_Z7kernel1Pij:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_lshl_add_u32 v0, v1, 1, v0
global_store_b32 v[2:3], v0, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1Pij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel1Pij, .Lfunc_end1-_Z7kernel1Pij
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPij
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1Pij
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1Pij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
class MyClass;
__global__ void kernel(int *a, unsigned int N);
class MyClass {
public:
MyClass(int len) {
length = len;
hipMalloc((void **)&d_data, sizeof(int)*length);
hipMemset((void *)d_data, 0, sizeof(int)*length);
};
~MyClass() {
hipFree((void *)d_data);
printf("%s\n","cudafree" );
};
void run(dim3 grid,dim3 block) {
kernel<<<grid, block>>>(d_data, length);
};
void set(int* h_data)
{
hipMemcpy(d_data,h_data,sizeof(int)*length,hipMemcpyHostToDevice);
}
int* getData(void) {
return d_data;
};
int getLength(void)
{
return length;
}
void show(void)
{
int h_data[length];
hipMemcpy(h_data, getData(), sizeof(int)*length, hipMemcpyDeviceToHost);
for (int i=0; i<length; i++) {
std::cout << h_data[i] << " ";
}
std::cout << std::endl;
}
public:
int *d_data;
int length;
};
__global__ void kernel(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += i;
}
}
__global__ void kernel1(int *a, unsigned int N)
{
const unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
if (i<N) {
a[i] += 2*i;
}
}
class MyClass1:public MyClass
{
public:
MyClass1(int len):MyClass(len){};
void run(dim3 grid,dim3 block)
{
kernel1<<<grid, block>>>(d_data, length);
};
};
int main(void) {
int arraySize = 20;
int* testArr = new int[arraySize];
for (int i = 0; i < arraySize; ++i)
{
testArr[i] = i;
}
// MyClass c(arraySize); //直接声明的对象是定义在栈上的，会被自动释放
// c.run();
// c.show();
dim3 grid(1);
dim3 block(arraySize);
MyClass1 *c = new MyClass1(arraySize);
c->set(testArr);
c->run(grid,block);
c->show();
delete c; //用指针指向new出来的对象是存放在堆上的，必须要手动delete对象，否则对象不会被释放掉。
} | .text
.file "cuda_cpp_class.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPij # -- Begin function _Z21__device_stub__kernelPij
.p2align 4, 0x90
.type _Z21__device_stub__kernelPij,@function
_Z21__device_stub__kernelPij: # @_Z21__device_stub__kernelPij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPij, .Lfunc_end0-_Z21__device_stub__kernelPij
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel1Pij # -- Begin function _Z22__device_stub__kernel1Pij
.p2align 4, 0x90
.type _Z22__device_stub__kernel1Pij,@function
_Z22__device_stub__kernel1Pij: # @_Z22__device_stub__kernel1Pij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel1Pij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel1Pij, .Lfunc_end1-_Z22__device_stub__kernel1Pij
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $80, %edi
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB2_1
# %bb.2:
movl $16, %edi
callq _Znwm
movq %rax, %rbx
movl $20, 8(%rax)
.Ltmp0:
movl $80, %esi
movq %rax, %rdi
callq hipMalloc
.Ltmp1:
# %bb.3: # %.noexc
movq (%rbx), %rdi
movslq 8(%rbx), %rdx
shlq $2, %rdx
.Ltmp2:
xorl %esi, %esi
callq hipMemset
.Ltmp3:
# %bb.4: # %_ZN8MyClass1C2Ei.exit
movq (%rbx), %rdi
movslq 8(%rbx), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rsi # imm = 0x100000001
leaq 19(%rsi), %rcx
movq %rbx, %rdi
movl $1, %edx
movl $1, %r8d
callq _ZN8MyClass13runE4dim3S0_
movq %rbx, %rdi
callq _ZN7MyClass4showEv
movq (%rbx), %rdi
.Ltmp5:
callq hipFree
.Ltmp6:
# %bb.5: # %_ZN7MyClassD2Ev.exit
movl $.L.str.2, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 32
.Ltmp7:
movq %rax, %rdi
callq __clang_call_terminate
.LBB2_6:
.Ltmp4:
movq %rax, %r14
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp3 # Call between .Ltmp3 and .Ltmp5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 1 # On action: 1
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end2-.Ltmp6 # Call between .Ltmp6 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZN8MyClass13runE4dim3S0_,"axG",@progbits,_ZN8MyClass13runE4dim3S0_,comdat
.weak _ZN8MyClass13runE4dim3S0_ # -- Begin function _ZN8MyClass13runE4dim3S0_
.p2align 4, 0x90
.type _ZN8MyClass13runE4dim3S0_,@function
_ZN8MyClass13runE4dim3S0_: # @_ZN8MyClass13runE4dim3S0_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq %rsi, %rdi
movl %edx, %esi
movq %rcx, %rdx
movl %r8d, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rbx), %rax
movl 8(%rbx), %ecx
movq %rax, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel1Pij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN8MyClass13runE4dim3S0_, .Lfunc_end3-_ZN8MyClass13runE4dim3S0_
.cfi_endproc
# -- End function
.section .text._ZN7MyClass4showEv,"axG",@progbits,_ZN7MyClass4showEv,comdat
.weak _ZN7MyClass4showEv # -- Begin function _ZN7MyClass4showEv
.p2align 4, 0x90
.type _ZN7MyClass4showEv,@function
_ZN7MyClass4showEv: # @_ZN7MyClass4showEv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rdi, %rbx
movslq 8(%rdi), %rdx
movl %edx, %eax
movq %rsp, %r14
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %r14
movq %r14, %rsp
movq (%rdi), %rsi
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rbx)
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
movslq 8(%rbx), %rax
cmpq %rax, %r15
jl .LBB4_2
.LBB4_3: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB4_7
.LBB4_6:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq -24(%rbp), %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB4_8:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _ZN7MyClass4showEv, .Lfunc_end4-_ZN7MyClass4showEv
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end5:
.size __clang_call_terminate, .Lfunc_end5-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPij, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1Pij, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPij,@object # @_Z6kernelPij
.section .rodata,"a",@progbits
.globl _Z6kernelPij
.p2align 3, 0x0
_Z6kernelPij:
.quad _Z21__device_stub__kernelPij
.size _Z6kernelPij, 8
.type _Z7kernel1Pij,@object # @_Z7kernel1Pij
.globl _Z7kernel1Pij
.p2align 3, 0x0
_Z7kernel1Pij:
.quad _Z22__device_stub__kernel1Pij
.size _Z7kernel1Pij, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudafree"
.size .L.str.2, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPij"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel1Pij"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPij
.addrsig_sym _Z22__device_stub__kernel1Pij
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelPij
.addrsig_sym _Z7kernel1Pij
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernel1Pij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ LEA R5, R0, R5, 0x1 ; /* 0x0000000500057211 */
/* 0x004fca00078e08ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6kernelPij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPij
.globl _Z6kernelPij
.p2align 8
.type _Z6kernelPij,@function
_Z6kernelPij:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v1
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPij, .Lfunc_end0-_Z6kernelPij
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel1Pij
.globl _Z7kernel1Pij
.p2align 8
.type _Z7kernel1Pij,@function
_Z7kernel1Pij:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_lshl_add_u32 v0, v1, 1, v0
global_store_b32 v[2:3], v0, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1Pij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel1Pij, .Lfunc_end1-_Z7kernel1Pij
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPij
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1Pij
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1Pij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d6cd5_00000000-6_cuda_cpp_class.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3690:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3690:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPijPij
.type _Z26__device_stub__Z6kernelPijPij, @function
_Z26__device_stub__Z6kernelPijPij:
.LFB3712:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3712:
.size _Z26__device_stub__Z6kernelPijPij, .-_Z26__device_stub__Z6kernelPijPij
.globl _Z6kernelPij
.type _Z6kernelPij, @function
_Z6kernelPij:
.LFB3713:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPijPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3713:
.size _Z6kernelPij, .-_Z6kernelPij
.globl _Z27__device_stub__Z7kernel1PijPij
.type _Z27__device_stub__Z7kernel1PijPij, @function
_Z27__device_stub__Z7kernel1PijPij:
.LFB3714:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel1Pij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3714:
.size _Z27__device_stub__Z7kernel1PijPij, .-_Z27__device_stub__Z7kernel1PijPij
.globl _Z7kernel1Pij
.type _Z7kernel1Pij, @function
_Z7kernel1Pij:
.LFB3715:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel1PijPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3715:
.size _Z7kernel1Pij, .-_Z7kernel1Pij
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "cudafree"
.LC2:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB3684:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3684
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $80, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %rbx
movl $0, %eax
.L20:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L20
movl $16, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
movl $20, 8(%rax)
movl $80, %esi
movq %rax, %rdi
.LEHB1:
call cudaMalloc@PLT
movslq 8(%r12), %rdx
salq $2, %rdx
movq (%r12), %rdi
movl $0, %esi
call cudaMemset@PLT
.LEHE1:
movslq 8(%r12), %rdx
salq $2, %rdx
movq (%r12), %rdi
movl $1, %ecx
movq %rbx, %rsi
.LEHB2:
call cudaMemcpy@PLT
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $20, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L21:
movq %rsp, -88(%rbp)
movslq 8(%r12), %rdx
salq $2, %rdx
leaq 15(%rdx), %rax
movq %rax, %rsi
andq $-16, %rsi
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L22:
cmpq %rcx, %rsp
je .L23
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L22
.L39:
movl 8(%r12), %esi
movq (%r12), %rdi
call _Z27__device_stub__Z7kernel1PijPij
jmp .L21
.L23:
movq %rsi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L24
orq $0, -8(%rsp,%rax)
.L24:
movq %rsp, %r15
movq (%r12), %rsi
movl $2, %ecx
movq %r15, %rdi
call cudaMemcpy@PLT
cmpl $0, 8(%r12)
jle .L25
movl $0, %ebx
leaq _ZSt4cout(%rip), %r14
leaq .LC0(%rip), %r13
.L26:
movl (%r15,%rbx,4), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, 8(%r12)
jg .L26
.L25:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L40
cmpb $0, 56(%rbx)
je .L29
movzbl 67(%rbx), %esi
.L30:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE2:
movq -88(%rbp), %rsp
movq (%r12), %rdi
call cudaFree@PLT
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L40:
.cfi_restore_state
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L42
.LEHB3:
call _ZSt16__throw_bad_castv@PLT
.L42:
call __stack_chk_fail@PLT
.L29:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L34:
endbr64
movq %rax, %rbx
movl $16, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L32
call __stack_chk_fail@PLT
.L32:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE3:
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3684:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3684:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3684-.LLSDACSB3684
.LLSDACSB3684:
.uleb128 .LEHB0-.LFB3684
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3684
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB3684
.uleb128 0
.uleb128 .LEHB2-.LFB3684
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3684
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3684:
.text
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7kernel1Pij"
.LC4:
.string "_Z6kernelPij"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3717:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1Pij(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPij(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3717:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_cpp_class.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPij # -- Begin function _Z21__device_stub__kernelPij
.p2align 4, 0x90
.type _Z21__device_stub__kernelPij,@function
_Z21__device_stub__kernelPij: # @_Z21__device_stub__kernelPij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPij, .Lfunc_end0-_Z21__device_stub__kernelPij
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel1Pij # -- Begin function _Z22__device_stub__kernel1Pij
.p2align 4, 0x90
.type _Z22__device_stub__kernel1Pij,@function
_Z22__device_stub__kernel1Pij: # @_Z22__device_stub__kernel1Pij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel1Pij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel1Pij, .Lfunc_end1-_Z22__device_stub__kernel1Pij
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $80, %edi
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB2_1
# %bb.2:
movl $16, %edi
callq _Znwm
movq %rax, %rbx
movl $20, 8(%rax)
.Ltmp0:
movl $80, %esi
movq %rax, %rdi
callq hipMalloc
.Ltmp1:
# %bb.3: # %.noexc
movq (%rbx), %rdi
movslq 8(%rbx), %rdx
shlq $2, %rdx
.Ltmp2:
xorl %esi, %esi
callq hipMemset
.Ltmp3:
# %bb.4: # %_ZN8MyClass1C2Ei.exit
movq (%rbx), %rdi
movslq 8(%rbx), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rsi # imm = 0x100000001
leaq 19(%rsi), %rcx
movq %rbx, %rdi
movl $1, %edx
movl $1, %r8d
callq _ZN8MyClass13runE4dim3S0_
movq %rbx, %rdi
callq _ZN7MyClass4showEv
movq (%rbx), %rdi
.Ltmp5:
callq hipFree
.Ltmp6:
# %bb.5: # %_ZN7MyClassD2Ev.exit
movl $.L.str.2, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 32
.Ltmp7:
movq %rax, %rdi
callq __clang_call_terminate
.LBB2_6:
.Ltmp4:
movq %rax, %r14
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp3 # Call between .Ltmp3 and .Ltmp5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 1 # On action: 1
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end2-.Ltmp6 # Call between .Ltmp6 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZN8MyClass13runE4dim3S0_,"axG",@progbits,_ZN8MyClass13runE4dim3S0_,comdat
.weak _ZN8MyClass13runE4dim3S0_ # -- Begin function _ZN8MyClass13runE4dim3S0_
.p2align 4, 0x90
.type _ZN8MyClass13runE4dim3S0_,@function
_ZN8MyClass13runE4dim3S0_: # @_ZN8MyClass13runE4dim3S0_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq %rsi, %rdi
movl %edx, %esi
movq %rcx, %rdx
movl %r8d, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rbx), %rax
movl 8(%rbx), %ecx
movq %rax, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel1Pij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN8MyClass13runE4dim3S0_, .Lfunc_end3-_ZN8MyClass13runE4dim3S0_
.cfi_endproc
# -- End function
.section .text._ZN7MyClass4showEv,"axG",@progbits,_ZN7MyClass4showEv,comdat
.weak _ZN7MyClass4showEv # -- Begin function _ZN7MyClass4showEv
.p2align 4, 0x90
.type _ZN7MyClass4showEv,@function
_ZN7MyClass4showEv: # @_ZN7MyClass4showEv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rdi, %rbx
movslq 8(%rdi), %rdx
movl %edx, %eax
movq %rsp, %r14
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %r14
movq %r14, %rsp
movq (%rdi), %rsi
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rbx)
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
movslq 8(%rbx), %rax
cmpq %rax, %r15
jl .LBB4_2
.LBB4_3: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB4_7
.LBB4_6:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq -24(%rbp), %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB4_8:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _ZN7MyClass4showEv, .Lfunc_end4-_ZN7MyClass4showEv
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end5:
.size __clang_call_terminate, .Lfunc_end5-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPij, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1Pij, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPij,@object # @_Z6kernelPij
.section .rodata,"a",@progbits
.globl _Z6kernelPij
.p2align 3, 0x0
_Z6kernelPij:
.quad _Z21__device_stub__kernelPij
.size _Z6kernelPij, 8
.type _Z7kernel1Pij,@object # @_Z7kernel1Pij
.globl _Z7kernel1Pij
.p2align 3, 0x0
_Z7kernel1Pij:
.quad _Z22__device_stub__kernel1Pij
.size _Z7kernel1Pij, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudafree"
.size .L.str.2, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPij"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel1Pij"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPij
.addrsig_sym _Z22__device_stub__kernel1Pij
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelPij
.addrsig_sym _Z7kernel1Pij
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define _SIZE_T_DEFINED
#ifndef __CUDACC__
#define __CUDACC__
#endif
#ifndef __cplusplus
#define __cplusplus
#endif
#include "cuda_runtime.h"
#include <stdio.h>
#include <cmath>
extern "C" {
// Takes 2 variables,
// int* topology should point to an integer array.
// float* out will be mapped to a huge output array.
// int N is the length of the topology array.
__global__ void kernel(int* topology, float* membank, float* weights, int TOPOLOGY_WIDTH, int NODE_WIDTH)
{
// Get the thread index.
int threadIndex = threadIdx.x + (blockDim.x * blockIdx.x);
// Calculate the layer.
int layer = ( threadIndex / NODE_WIDTH );
// Calculate the offset.
int node = ( threadIndex % NODE_WIDTH );
// Validate the datas.
if ( layer > 0 && layer < TOPOLOGY_WIDTH + 1 ) {
if ( node < topology[layer]) {
// This is a valid case.
// So first we need to start the loop.
int terminate = 1000;
float nodeOut = 0;
bool stop = false;
while ( !stop && terminate-- > 0) {
// Set stop to true so that only a failure will make us iterate again.
stop = true;
// Now we iterate over each node above us.
int max = layer - 1;
for ( int i = 0; i < topology[max]; i++ ) {
int arrayIndex = (max) * NODE_WIDTH + i;
// Check the respsective sources.
if ( membank[arrayIndex] == 0 ) {
// If something hasn't been pushed to it yet, let's abort.
stop = false;
break;
} else {
// Otherwise, there is a value here! So let's add it to our collective.
nodeOut += membank[arrayIndex] * weights[arrayIndex];
}
}
if ( !stop ) continue;
// Compute sigmoid.
//nodeOut = nodeOut;//1.0 / ( 1.0 + exp(-nodeOut));
// If we don't want to stop, it means we've added all of the nodes
// we needed to. So let's push our value.
membank[(layer) * NODE_WIDTH + node] = nodeOut;
}
}
}
__syncthreads();
__shared__ float total;
total = 0;
for ( int i = 0; i < topology[TOPOLOGY_WIDTH - 1]; i++ ) {
int arrayIndex = ( ( TOPOLOGY_WIDTH - 1 ) * NODE_WIDTH ) + i;
total = membank[arrayIndex] * weights[arrayIndex];
}
__syncthreads();
membank[0] = total;
}
int main()
{
return 0;
}
} | code for sm_80
Function : kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x17c] ; /* 0x00005f0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x4b0 ; /* 0x0000046000007945 */
/* 0x000fe20003800000 */
/*0050*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0070*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0090*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*00a0*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R2, R7, R5, R4 ; /* 0x0000000507027224 */
/* 0x000fca00078e0204 */
/*0130*/ ISETP.GT.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f44070 */
/*0140*/ @!P2 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a07 */
/*0150*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*0180*/ LOP3.LUT R2, R0, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0000027a12 */
/* 0x000fc800078e3cff */
/*0190*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01b0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0003 */
/*01c0*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*01d0*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff04aa12 */
/* 0x000fc800078e33ff */
/*01e0*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f04270 */
/*01f0*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0a04 */
/*0200*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fe20000701670 */
/*0210*/ IMAD R5, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003057a24 */
/* 0x000fd800078e0200 */
/*0220*/ @P0 BRA 0x4a0 ; /* 0x0000027000000947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.WIDE R8, R4, R3, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fca00078e0203 */
/*0250*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x000ea4000c1e1900 */
/*0260*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f06270 */
/*0270*/ @P0 BRA 0x4a0 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*0280*/ IMAD R2, R4.reuse, c[0x0][0x17c], R5 ; /* 0x00005f0004027a24 */
/* 0x040fe200078e0205 */
/*0290*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3e7 ; /* 0x000003e7ff007424 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0203 */
/*02d0*/ LDG.E R13, [R8.64+-0x4] ; /* 0xfffffc04080d7981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ BSSY B1, 0x440 ; /* 0x0000015000017945 */
/* 0x000fe20003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ ISETP.GE.AND P1, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x004fda0003f26270 */
/*0310*/ @!P1 BRA 0x430 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0320*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD R10, R11, c[0x0][0x17c], R6 ; /* 0x00005f000b0a7a24 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R4, R10, R5, c[0x0][0x168] ; /* 0x00005a000a047625 */
/* 0x000fca00078e0205 */
/*0360*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0380*/ FSETP.NEU.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x004fda0003f2d000 */
/*0390*/ @!P1 BRA 0x430 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*03a0*/ SHF.R.S32.HI R5, RZ, 0x1f, R10 ; /* 0x0000001fff057819 */
/* 0x000fe4000001140a */
/*03b0*/ LEA R4, P0, R10, c[0x0][0x170], 0x2 ; /* 0x00005c000a047a11 */
/* 0x000fc800078010ff */
/*03c0*/ LEA.HI.X R5, R10, c[0x0][0x174], R5, 0x2, P0 ; /* 0x00005d000a057a11 */
/* 0x000fca00000f1405 */
/*03d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*03f0*/ ISETP.GE.AND P0, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe20003f06270 */
/*0400*/ FFMA R7, R12, R4, R7 ; /* 0x000000040c077223 */
/* 0x004fd80000000007 */
/*0410*/ @!P0 BRA 0x330 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0420*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd00003f0e170 */
/*0430*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0440*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e2000c101904 */
/*0450*/ ISETP.GT.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f24270 */
/*0460*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007ffe0ff */
/*0470*/ @!P0 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff048224 */
/* 0x000fc800078e0200 */
/*0480*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fcc00078e0004 */
/*0490*/ @P0 BRA P1, 0x2d0 ; /* 0xfffffe3000000947 */
/* 0x001fea000083ffff */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04c0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe400078e00ff */
/*04d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc600078e00ff */
/*04e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fca0007ffe0ff */
/*04f0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*0500*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0510*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*0520*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f06270 */
/*0530*/ @!P0 BRA 0x880 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*0540*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*0550*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0560*/ LOP3.LUT R7, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302077812 */
/* 0x000fe400078ec0ff */
/*0570*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f06070 */
/*0580*/ @!P0 BRA 0x7a0 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0590*/ IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102027824 */
/* 0x000fe400078e0a07 */
/*05a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*05b0*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f04270 */
/*05c0*/ @!P0 BRA 0x6e0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe40003f24270 */
/*05e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*05f0*/ @!P1 BRA 0x670 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0600*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0610*/ IADD3 R2, R2, -0x10, RZ ; /* 0xfffffff002027810 */
/* 0x000fe20007ffe0ff */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*0630*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0640*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fda0003f24270 */
/*0650*/ @P1 BRA 0x610 ; /* 0xffffffb000001947 */
/* 0x000fea000383ffff */
/*0660*/ IADD3 R3, R3, 0xc, RZ ; /* 0x0000000c03037810 */
/* 0x000fe40007ffe0ff */
/*0670*/ ISETP.GT.AND P1, PT, R2, 0x4, PT ; /* 0x000000040200780c */
/* 0x000fda0003f24270 */
/*0680*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*0690*/ @P1 IADD3 R2, R2, -0x8, RZ ; /* 0xfffffff802021810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ @P1 IADD3 R3, R6.reuse, 0x4, RZ ; /* 0x0000000406031810 */
/* 0x040fe40007ffe0ff */
/*06b0*/ @P1 IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806061810 */
/* 0x000fce0007ffe0ff */
/*06c0*/ ISETP.NE.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0000705670 */
/*06d0*/ @!P0 BRA 0x730 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*06e0*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*0700*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0710*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0720*/ @P0 BRA 0x6e0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0730*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fca00078e0203 */
/*0740*/ IADD3 R4, R3, 0x3, RZ ; /* 0x0000000303047810 */
/* 0x000fca0007ffe0ff */
/*0750*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0209 */
/*0760*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0209 */
/*0770*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0780*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0790*/ FMUL R8, R4, R3 ; /* 0x0000000304087220 */
/* 0x004fe40000400000 */
/*07a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*07b0*/ @!P0 BRA 0x870 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*07c0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*07e0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0800*/ @P0 BRA 0x7c0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0810*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fc800078e0203 */
/*0820*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0209 */
/*0830*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe400078e0209 */
/*0840*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0860*/ FMUL R8, R4, R3 ; /* 0x0000000304087220 */
/* 0x004fca0000400000 */
/*0870*/ STS [RZ], R8 ; /* 0x00000008ff007388 */
/* 0x0001e40000000800 */
/*0880*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0890*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*08a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc600078e00ff */
/*08b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e680000000800 */
/*08c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define _SIZE_T_DEFINED
#ifndef __CUDACC__
#define __CUDACC__
#endif
#ifndef __cplusplus
#define __cplusplus
#endif
#include "cuda_runtime.h"
#include <stdio.h>
#include <cmath>
extern "C" {
// Takes 2 variables,
// int* topology should point to an integer array.
// float* out will be mapped to a huge output array.
// int N is the length of the topology array.
__global__ void kernel(int* topology, float* membank, float* weights, int TOPOLOGY_WIDTH, int NODE_WIDTH)
{
// Get the thread index.
int threadIndex = threadIdx.x + (blockDim.x * blockIdx.x);
// Calculate the layer.
int layer = ( threadIndex / NODE_WIDTH );
// Calculate the offset.
int node = ( threadIndex % NODE_WIDTH );
// Validate the datas.
if ( layer > 0 && layer < TOPOLOGY_WIDTH + 1 ) {
if ( node < topology[layer]) {
// This is a valid case.
// So first we need to start the loop.
int terminate = 1000;
float nodeOut = 0;
bool stop = false;
while ( !stop && terminate-- > 0) {
// Set stop to true so that only a failure will make us iterate again.
stop = true;
// Now we iterate over each node above us.
int max = layer - 1;
for ( int i = 0; i < topology[max]; i++ ) {
int arrayIndex = (max) * NODE_WIDTH + i;
// Check the respsective sources.
if ( membank[arrayIndex] == 0 ) {
// If something hasn't been pushed to it yet, let's abort.
stop = false;
break;
} else {
// Otherwise, there is a value here! So let's add it to our collective.
nodeOut += membank[arrayIndex] * weights[arrayIndex];
}
}
if ( !stop ) continue;
// Compute sigmoid.
//nodeOut = nodeOut;//1.0 / ( 1.0 + exp(-nodeOut));
// If we don't want to stop, it means we've added all of the nodes
// we needed to. So let's push our value.
membank[(layer) * NODE_WIDTH + node] = nodeOut;
}
}
}
__syncthreads();
__shared__ float total;
total = 0;
for ( int i = 0; i < topology[TOPOLOGY_WIDTH - 1]; i++ ) {
int arrayIndex = ( ( TOPOLOGY_WIDTH - 1 ) * NODE_WIDTH ) + i;
total = membank[arrayIndex] * weights[arrayIndex];
}
__syncthreads();
membank[0] = total;
}
int main()
{
return 0;
}
} | .file "tmpxft_0005db43_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii
.type _Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii, @function
_Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii, .-_Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii
.globl kernel
.type kernel, @function
kernel:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define _SIZE_T_DEFINED
#ifndef __CUDACC__
#define __CUDACC__
#endif
#ifndef __cplusplus
#define __cplusplus
#endif
#include "cuda_runtime.h"
#include <stdio.h>
#include <cmath>
extern "C" {
// Takes 2 variables,
// int* topology should point to an integer array.
// float* out will be mapped to a huge output array.
// int N is the length of the topology array.
__global__ void kernel(int* topology, float* membank, float* weights, int TOPOLOGY_WIDTH, int NODE_WIDTH)
{
// Get the thread index.
int threadIndex = threadIdx.x + (blockDim.x * blockIdx.x);
// Calculate the layer.
int layer = ( threadIndex / NODE_WIDTH );
// Calculate the offset.
int node = ( threadIndex % NODE_WIDTH );
// Validate the datas.
if ( layer > 0 && layer < TOPOLOGY_WIDTH + 1 ) {
if ( node < topology[layer]) {
// This is a valid case.
// So first we need to start the loop.
int terminate = 1000;
float nodeOut = 0;
bool stop = false;
while ( !stop && terminate-- > 0) {
// Set stop to true so that only a failure will make us iterate again.
stop = true;
// Now we iterate over each node above us.
int max = layer - 1;
for ( int i = 0; i < topology[max]; i++ ) {
int arrayIndex = (max) * NODE_WIDTH + i;
// Check the respsective sources.
if ( membank[arrayIndex] == 0 ) {
// If something hasn't been pushed to it yet, let's abort.
stop = false;
break;
} else {
// Otherwise, there is a value here! So let's add it to our collective.
nodeOut += membank[arrayIndex] * weights[arrayIndex];
}
}
if ( !stop ) continue;
// Compute sigmoid.
//nodeOut = nodeOut;//1.0 / ( 1.0 + exp(-nodeOut));
// If we don't want to stop, it means we've added all of the nodes
// we needed to. So let's push our value.
membank[(layer) * NODE_WIDTH + node] = nodeOut;
}
}
}
__syncthreads();
__shared__ float total;
total = 0;
for ( int i = 0; i < topology[TOPOLOGY_WIDTH - 1]; i++ ) {
int arrayIndex = ( ( TOPOLOGY_WIDTH - 1 ) * NODE_WIDTH ) + i;
total = membank[arrayIndex] * weights[arrayIndex];
}
__syncthreads();
membank[0] = total;
}
int main()
{
return 0;
}
} | #define _SIZE_T_DEFINED
#ifndef __HIPCC__
#define __HIPCC__
#endif
#ifndef __cplusplus
#define __cplusplus
#endif
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <cmath>
extern "C" {
// Takes 2 variables,
// int* topology should point to an integer array.
// float* out will be mapped to a huge output array.
// int N is the length of the topology array.
__global__ void kernel(int* topology, float* membank, float* weights, int TOPOLOGY_WIDTH, int NODE_WIDTH)
{
// Get the thread index.
int threadIndex = threadIdx.x + (blockDim.x * blockIdx.x);
// Calculate the layer.
int layer = ( threadIndex / NODE_WIDTH );
// Calculate the offset.
int node = ( threadIndex % NODE_WIDTH );
// Validate the datas.
if ( layer > 0 && layer < TOPOLOGY_WIDTH + 1 ) {
if ( node < topology[layer]) {
// This is a valid case.
// So first we need to start the loop.
int terminate = 1000;
float nodeOut = 0;
bool stop = false;
while ( !stop && terminate-- > 0) {
// Set stop to true so that only a failure will make us iterate again.
stop = true;
// Now we iterate over each node above us.
int max = layer - 1;
for ( int i = 0; i < topology[max]; i++ ) {
int arrayIndex = (max) * NODE_WIDTH + i;
// Check the respsective sources.
if ( membank[arrayIndex] == 0 ) {
// If something hasn't been pushed to it yet, let's abort.
stop = false;
break;
} else {
// Otherwise, there is a value here! So let's add it to our collective.
nodeOut += membank[arrayIndex] * weights[arrayIndex];
}
}
if ( !stop ) continue;
// Compute sigmoid.
//nodeOut = nodeOut;//1.0 / ( 1.0 + exp(-nodeOut));
// If we don't want to stop, it means we've added all of the nodes
// we needed to. So let's push our value.
membank[(layer) * NODE_WIDTH + node] = nodeOut;
}
}
}
__syncthreads();
__shared__ float total;
total = 0;
for ( int i = 0; i < topology[TOPOLOGY_WIDTH - 1]; i++ ) {
int arrayIndex = ( ( TOPOLOGY_WIDTH - 1 ) * NODE_WIDTH ) + i;
total = membank[arrayIndex] * weights[arrayIndex];
}
__syncthreads();
membank[0] = total;
}
int main()
{
return 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define _SIZE_T_DEFINED
#ifndef __HIPCC__
#define __HIPCC__
#endif
#ifndef __cplusplus
#define __cplusplus
#endif
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <cmath>
extern "C" {
// Takes 2 variables,
// int* topology should point to an integer array.
// float* out will be mapped to a huge output array.
// int N is the length of the topology array.
__global__ void kernel(int* topology, float* membank, float* weights, int TOPOLOGY_WIDTH, int NODE_WIDTH)
{
// Get the thread index.
int threadIndex = threadIdx.x + (blockDim.x * blockIdx.x);
// Calculate the layer.
int layer = ( threadIndex / NODE_WIDTH );
// Calculate the offset.
int node = ( threadIndex % NODE_WIDTH );
// Validate the datas.
if ( layer > 0 && layer < TOPOLOGY_WIDTH + 1 ) {
if ( node < topology[layer]) {
// This is a valid case.
// So first we need to start the loop.
int terminate = 1000;
float nodeOut = 0;
bool stop = false;
while ( !stop && terminate-- > 0) {
// Set stop to true so that only a failure will make us iterate again.
stop = true;
// Now we iterate over each node above us.
int max = layer - 1;
for ( int i = 0; i < topology[max]; i++ ) {
int arrayIndex = (max) * NODE_WIDTH + i;
// Check the respsective sources.
if ( membank[arrayIndex] == 0 ) {
// If something hasn't been pushed to it yet, let's abort.
stop = false;
break;
} else {
// Otherwise, there is a value here! So let's add it to our collective.
nodeOut += membank[arrayIndex] * weights[arrayIndex];
}
}
if ( !stop ) continue;
// Compute sigmoid.
//nodeOut = nodeOut;//1.0 / ( 1.0 + exp(-nodeOut));
// If we don't want to stop, it means we've added all of the nodes
// we needed to. So let's push our value.
membank[(layer) * NODE_WIDTH + node] = nodeOut;
}
}
}
__syncthreads();
__shared__ float total;
total = 0;
for ( int i = 0; i < topology[TOPOLOGY_WIDTH - 1]; i++ ) {
int arrayIndex = ( ( TOPOLOGY_WIDTH - 1 ) * NODE_WIDTH ) + i;
total = membank[arrayIndex] * weights[arrayIndex];
}
__syncthreads();
membank[0] = total;
}
int main()
{
return 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel
.globl kernel
.p2align 8
.type kernel,@function
kernel:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s11, 31
s_and_b32 s0, s0, 0xffff
s_add_i32 s3, s11, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s0, v[0:1]
s_sub_i32 s0, 0, s3
v_mul_lo_u32 v0, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v2, v3
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s3
v_sub_nc_u32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
v_cmp_ge_i32_e64 s0, s10, v0
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_mul_lo_u32 v4, v0, s11
v_sub_nc_u32_e32 v2, v2, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_15
v_dual_mov_b32 v4, v1 :: v_dual_add_nc_u32 v3, -1, v0
s_mov_b32 s3, 0
s_movk_i32 s13, 0x3e8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_mul_lo_u32 v3, v3, s11
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v11, v[4:5], off
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_u32 v5, s0, s8, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_add_co_ci_u32_e64 v6, s0, s9, v6, s0
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v11
s_branch .LBB0_6
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s15
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s14
v_and_b32_e32 v7, 1, v12
s_add_i32 s13, s13, -1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 1, v7
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s14, exec_lo, s0
s_or_b32 s3, s14, s3
s_and_not1_b32 s12, s12, exec_lo
s_and_b32 s1, s1, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s12, s1
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_13
.LBB0_6:
s_or_b32 s0, s0, exec_lo
s_cmp_eq_u32 s13, 0
s_cbranch_scc1 .LBB0_12
v_mov_b32_e32 v12, 1
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v13, 1 :: v_dual_mov_b32 v8, v6
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v10, v4
v_mov_b32_e32 v9, v3
s_mov_b32 s16, 1
s_mov_b32 s15, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_ge_i32_e64 s1, s16, v11
s_xor_b32 s0, s0, -1
s_add_i32 s16, s16, 1
v_mov_b32_e32 v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 s1, s0, s1
v_add_co_u32 v9, s0, v9, 4
v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
v_add_co_u32 v7, s0, v7, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
s_and_b32 s0, exec_lo, s1
s_or_b32 s15, s0, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_3
.LBB0_10:
global_load_b32 v14, v[9:10], off
v_mov_b32_e32 v12, 0
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e64 s0, 0, v14
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_9
global_load_b32 v12, v[7:8], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v1, v14, v12 :: v_dual_mov_b32 v12, v13
s_branch .LBB0_9
.LBB0_12:
s_mov_b32 s1, -1
s_branch .LBB0_5
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
s_xor_b32 s0, s12, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_15
v_mad_u64_u32 v[3:4], null, v0, s11, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s0, s10, -1
s_waitcnt_vscnt null, 0x0
s_ashr_i32 s1, s0, 31
s_barrier
s_lshl_b64 s[2:3], s[0:1], 2
buffer_gl0_inv
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
v_mov_b32_e32 v0, 0
s_load_b32 s1, s[2:3], 0x0
ds_store_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s1, 1
s_cbranch_scc1 .LBB0_17
s_mul_i32 s0, s0, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s1, s0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s6, s0
s_addc_u32 s3, s7, s1
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v2
ds_store_b32 v0, v1
.LBB0_17:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernel, .Lfunc_end0-kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define _SIZE_T_DEFINED
#ifndef __HIPCC__
#define __HIPCC__
#endif
#ifndef __cplusplus
#define __cplusplus
#endif
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <cmath>
extern "C" {
// Takes 2 variables,
// int* topology should point to an integer array.
// float* out will be mapped to a huge output array.
// int N is the length of the topology array.
__global__ void kernel(int* topology, float* membank, float* weights, int TOPOLOGY_WIDTH, int NODE_WIDTH)
{
// Get the thread index.
int threadIndex = threadIdx.x + (blockDim.x * blockIdx.x);
// Calculate the layer.
int layer = ( threadIndex / NODE_WIDTH );
// Calculate the offset.
int node = ( threadIndex % NODE_WIDTH );
// Validate the datas.
if ( layer > 0 && layer < TOPOLOGY_WIDTH + 1 ) {
if ( node < topology[layer]) {
// This is a valid case.
// So first we need to start the loop.
int terminate = 1000;
float nodeOut = 0;
bool stop = false;
while ( !stop && terminate-- > 0) {
// Set stop to true so that only a failure will make us iterate again.
stop = true;
// Now we iterate over each node above us.
int max = layer - 1;
for ( int i = 0; i < topology[max]; i++ ) {
int arrayIndex = (max) * NODE_WIDTH + i;
// Check the respsective sources.
if ( membank[arrayIndex] == 0 ) {
// If something hasn't been pushed to it yet, let's abort.
stop = false;
break;
} else {
// Otherwise, there is a value here! So let's add it to our collective.
nodeOut += membank[arrayIndex] * weights[arrayIndex];
}
}
if ( !stop ) continue;
// Compute sigmoid.
//nodeOut = nodeOut;//1.0 / ( 1.0 + exp(-nodeOut));
// If we don't want to stop, it means we've added all of the nodes
// we needed to. So let's push our value.
membank[(layer) * NODE_WIDTH + node] = nodeOut;
}
}
}
__syncthreads();
__shared__ float total;
total = 0;
for ( int i = 0; i < topology[TOPOLOGY_WIDTH - 1]; i++ ) {
int arrayIndex = ( ( TOPOLOGY_WIDTH - 1 ) * NODE_WIDTH ) + i;
total = membank[arrayIndex] * weights[arrayIndex];
}
__syncthreads();
membank[0] = total;
}
int main()
{
return 0;
}
} | .text
.file "kernel.hip"
.globl __device_stub__kernel # -- Begin function __device_stub__kernel
.p2align 4, 0x90
.type __device_stub__kernel,@function
__device_stub__kernel: # @__device_stub__kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__kernel, .Lfunc_end0-__device_stub__kernel
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.section .rodata,"a",@progbits
.globl kernel
.p2align 3, 0x0
kernel:
.quad __device_stub__kernel
.size kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x17c] ; /* 0x00005f0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x4b0 ; /* 0x0000046000007945 */
/* 0x000fe20003800000 */
/*0050*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0070*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0090*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*00a0*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R2, R7, R5, R4 ; /* 0x0000000507027224 */
/* 0x000fca00078e0204 */
/*0130*/ ISETP.GT.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f44070 */
/*0140*/ @!P2 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a07 */
/*0150*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*0180*/ LOP3.LUT R2, R0, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0000027a12 */
/* 0x000fc800078e3cff */
/*0190*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01b0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0003 */
/*01c0*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*01d0*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff04aa12 */
/* 0x000fc800078e33ff */
/*01e0*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f04270 */
/*01f0*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0a04 */
/*0200*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fe20000701670 */
/*0210*/ IMAD R5, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003057a24 */
/* 0x000fd800078e0200 */
/*0220*/ @P0 BRA 0x4a0 ; /* 0x0000027000000947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.WIDE R8, R4, R3, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fca00078e0203 */
/*0250*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x000ea4000c1e1900 */
/*0260*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f06270 */
/*0270*/ @P0 BRA 0x4a0 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*0280*/ IMAD R2, R4.reuse, c[0x0][0x17c], R5 ; /* 0x00005f0004027a24 */
/* 0x040fe200078e0205 */
/*0290*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3e7 ; /* 0x000003e7ff007424 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0203 */
/*02d0*/ LDG.E R13, [R8.64+-0x4] ; /* 0xfffffc04080d7981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ BSSY B1, 0x440 ; /* 0x0000015000017945 */
/* 0x000fe20003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ ISETP.GE.AND P1, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x004fda0003f26270 */
/*0310*/ @!P1 BRA 0x430 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0320*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD R10, R11, c[0x0][0x17c], R6 ; /* 0x00005f000b0a7a24 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R4, R10, R5, c[0x0][0x168] ; /* 0x00005a000a047625 */
/* 0x000fca00078e0205 */
/*0360*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0380*/ FSETP.NEU.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x004fda0003f2d000 */
/*0390*/ @!P1 BRA 0x430 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*03a0*/ SHF.R.S32.HI R5, RZ, 0x1f, R10 ; /* 0x0000001fff057819 */
/* 0x000fe4000001140a */
/*03b0*/ LEA R4, P0, R10, c[0x0][0x170], 0x2 ; /* 0x00005c000a047a11 */
/* 0x000fc800078010ff */
/*03c0*/ LEA.HI.X R5, R10, c[0x0][0x174], R5, 0x2, P0 ; /* 0x00005d000a057a11 */
/* 0x000fca00000f1405 */
/*03d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*03f0*/ ISETP.GE.AND P0, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe20003f06270 */
/*0400*/ FFMA R7, R12, R4, R7 ; /* 0x000000040c077223 */
/* 0x004fd80000000007 */
/*0410*/ @!P0 BRA 0x330 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0420*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd00003f0e170 */
/*0430*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0440*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e2000c101904 */
/*0450*/ ISETP.GT.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f24270 */
/*0460*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007ffe0ff */
/*0470*/ @!P0 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff048224 */
/* 0x000fc800078e0200 */
/*0480*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fcc00078e0004 */
/*0490*/ @P0 BRA P1, 0x2d0 ; /* 0xfffffe3000000947 */
/* 0x001fea000083ffff */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04c0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe400078e00ff */
/*04d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc600078e00ff */
/*04e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fca0007ffe0ff */
/*04f0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*0500*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0510*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*0520*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f06270 */
/*0530*/ @!P0 BRA 0x880 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*0540*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*0550*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0560*/ LOP3.LUT R7, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302077812 */
/* 0x000fe400078ec0ff */
/*0570*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f06070 */
/*0580*/ @!P0 BRA 0x7a0 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0590*/ IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102027824 */
/* 0x000fe400078e0a07 */
/*05a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*05b0*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f04270 */
/*05c0*/ @!P0 BRA 0x6e0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe40003f24270 */
/*05e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*05f0*/ @!P1 BRA 0x670 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0600*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0610*/ IADD3 R2, R2, -0x10, RZ ; /* 0xfffffff002027810 */
/* 0x000fe20007ffe0ff */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*0630*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0640*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fda0003f24270 */
/*0650*/ @P1 BRA 0x610 ; /* 0xffffffb000001947 */
/* 0x000fea000383ffff */
/*0660*/ IADD3 R3, R3, 0xc, RZ ; /* 0x0000000c03037810 */
/* 0x000fe40007ffe0ff */
/*0670*/ ISETP.GT.AND P1, PT, R2, 0x4, PT ; /* 0x000000040200780c */
/* 0x000fda0003f24270 */
/*0680*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*0690*/ @P1 IADD3 R2, R2, -0x8, RZ ; /* 0xfffffff802021810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ @P1 IADD3 R3, R6.reuse, 0x4, RZ ; /* 0x0000000406031810 */
/* 0x040fe40007ffe0ff */
/*06b0*/ @P1 IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806061810 */
/* 0x000fce0007ffe0ff */
/*06c0*/ ISETP.NE.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0000705670 */
/*06d0*/ @!P0 BRA 0x730 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*06e0*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*0700*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0710*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0720*/ @P0 BRA 0x6e0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0730*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fca00078e0203 */
/*0740*/ IADD3 R4, R3, 0x3, RZ ; /* 0x0000000303047810 */
/* 0x000fca0007ffe0ff */
/*0750*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0209 */
/*0760*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0209 */
/*0770*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0780*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0790*/ FMUL R8, R4, R3 ; /* 0x0000000304087220 */
/* 0x004fe40000400000 */
/*07a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*07b0*/ @!P0 BRA 0x870 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*07c0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*07e0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0800*/ @P0 BRA 0x7c0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0810*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fc800078e0203 */
/*0820*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0209 */
/*0830*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe400078e0209 */
/*0840*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0860*/ FMUL R8, R4, R3 ; /* 0x0000000304087220 */
/* 0x004fca0000400000 */
/*0870*/ STS [RZ], R8 ; /* 0x00000008ff007388 */
/* 0x0001e40000000800 */
/*0880*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0890*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*08a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc600078e00ff */
/*08b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e680000000800 */
/*08c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel
.globl kernel
.p2align 8
.type kernel,@function
kernel:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s11, 31
s_and_b32 s0, s0, 0xffff
s_add_i32 s3, s11, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s0, v[0:1]
s_sub_i32 s0, 0, s3
v_mul_lo_u32 v0, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v2, v3
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s3
v_sub_nc_u32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
v_cmp_ge_i32_e64 s0, s10, v0
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_mul_lo_u32 v4, v0, s11
v_sub_nc_u32_e32 v2, v2, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_15
v_dual_mov_b32 v4, v1 :: v_dual_add_nc_u32 v3, -1, v0
s_mov_b32 s3, 0
s_movk_i32 s13, 0x3e8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_mul_lo_u32 v3, v3, s11
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v11, v[4:5], off
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_u32 v5, s0, s8, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_add_co_ci_u32_e64 v6, s0, s9, v6, s0
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v11
s_branch .LBB0_6
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s15
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s14
v_and_b32_e32 v7, 1, v12
s_add_i32 s13, s13, -1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 1, v7
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s14, exec_lo, s0
s_or_b32 s3, s14, s3
s_and_not1_b32 s12, s12, exec_lo
s_and_b32 s1, s1, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s12, s1
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_13
.LBB0_6:
s_or_b32 s0, s0, exec_lo
s_cmp_eq_u32 s13, 0
s_cbranch_scc1 .LBB0_12
v_mov_b32_e32 v12, 1
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v13, 1 :: v_dual_mov_b32 v8, v6
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v10, v4
v_mov_b32_e32 v9, v3
s_mov_b32 s16, 1
s_mov_b32 s15, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_ge_i32_e64 s1, s16, v11
s_xor_b32 s0, s0, -1
s_add_i32 s16, s16, 1
v_mov_b32_e32 v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 s1, s0, s1
v_add_co_u32 v9, s0, v9, 4
v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
v_add_co_u32 v7, s0, v7, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
s_and_b32 s0, exec_lo, s1
s_or_b32 s15, s0, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_3
.LBB0_10:
global_load_b32 v14, v[9:10], off
v_mov_b32_e32 v12, 0
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e64 s0, 0, v14
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_9
global_load_b32 v12, v[7:8], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v1, v14, v12 :: v_dual_mov_b32 v12, v13
s_branch .LBB0_9
.LBB0_12:
s_mov_b32 s1, -1
s_branch .LBB0_5
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
s_xor_b32 s0, s12, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_15
v_mad_u64_u32 v[3:4], null, v0, s11, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s0, s10, -1
s_waitcnt_vscnt null, 0x0
s_ashr_i32 s1, s0, 31
s_barrier
s_lshl_b64 s[2:3], s[0:1], 2
buffer_gl0_inv
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
v_mov_b32_e32 v0, 0
s_load_b32 s1, s[2:3], 0x0
ds_store_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s1, 1
s_cbranch_scc1 .LBB0_17
s_mul_i32 s0, s0, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s1, s0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s6, s0
s_addc_u32 s3, s7, s1
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v2
ds_store_b32 v0, v1
.LBB0_17:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernel, .Lfunc_end0-kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005db43_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii
.type _Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii, @function
_Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii, .-_Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii
.globl kernel
.type kernel, @function
kernel:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kernelPiPfS0_iiPiPfS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl __device_stub__kernel # -- Begin function __device_stub__kernel
.p2align 4, 0x90
.type __device_stub__kernel,@function
__device_stub__kernel: # @__device_stub__kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__kernel, .Lfunc_end0-__device_stub__kernel
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.section .rodata,"a",@progbits
.globl kernel
.p2align 3, 0x0
kernel:
.quad __device_stub__kernel
.size kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void prova3() {
//auto A = NQfrontier<32>(F_array, 5, Adj_array);
//for (auto it : A)
//Ouptput[threadIdx.x] = it.start;
// printf("threadIdx.x %d \t %d\n", threadIdx.x, it.end);
//printf("threadIdx.x %d \t %d\n", threadIdx.x, (*A.begin()).start);
} | code for sm_80
Function : _Z6prova3v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void prova3() {
//auto A = NQfrontier<32>(F_array, 5, Adj_array);
//for (auto it : A)
//Ouptput[threadIdx.x] = it.start;
// printf("threadIdx.x %d \t %d\n", threadIdx.x, it.end);
//printf("threadIdx.x %d \t %d\n", threadIdx.x, (*A.begin()).start);
} | .file "tmpxft_0014b550_00000000-6_prova3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6prova3vv
.type _Z24__device_stub__Z6prova3vv, @function
_Z24__device_stub__Z6prova3vv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6prova3v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z6prova3vv, .-_Z24__device_stub__Z6prova3vv
.globl _Z6prova3v
.type _Z6prova3v, @function
_Z6prova3v:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6prova3vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6prova3v, .-_Z6prova3v
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6prova3v"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6prova3v(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void prova3() {
//auto A = NQfrontier<32>(F_array, 5, Adj_array);
//for (auto it : A)
//Ouptput[threadIdx.x] = it.start;
// printf("threadIdx.x %d \t %d\n", threadIdx.x, it.end);
//printf("threadIdx.x %d \t %d\n", threadIdx.x, (*A.begin()).start);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void prova3() {
//auto A = NQfrontier<32>(F_array, 5, Adj_array);
//for (auto it : A)
//Ouptput[threadIdx.x] = it.start;
// printf("threadIdx.x %d \t %d\n", threadIdx.x, it.end);
//printf("threadIdx.x %d \t %d\n", threadIdx.x, (*A.begin()).start);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void prova3() {
//auto A = NQfrontier<32>(F_array, 5, Adj_array);
//for (auto it : A)
//Ouptput[threadIdx.x] = it.start;
// printf("threadIdx.x %d \t %d\n", threadIdx.x, it.end);
//printf("threadIdx.x %d \t %d\n", threadIdx.x, (*A.begin()).start);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6prova3v
.globl _Z6prova3v
.p2align 8
.type _Z6prova3v,@function
_Z6prova3v:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6prova3v
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6prova3v, .Lfunc_end0-_Z6prova3v
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6prova3v
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6prova3v.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void prova3() {
//auto A = NQfrontier<32>(F_array, 5, Adj_array);
//for (auto it : A)
//Ouptput[threadIdx.x] = it.start;
// printf("threadIdx.x %d \t %d\n", threadIdx.x, it.end);
//printf("threadIdx.x %d \t %d\n", threadIdx.x, (*A.begin()).start);
} | .text
.file "prova3.hip"
.globl _Z21__device_stub__prova3v # -- Begin function _Z21__device_stub__prova3v
.p2align 4, 0x90
.type _Z21__device_stub__prova3v,@function
_Z21__device_stub__prova3v: # @_Z21__device_stub__prova3v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6prova3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__prova3v, .Lfunc_end0-_Z21__device_stub__prova3v
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6prova3v, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6prova3v,@object # @_Z6prova3v
.section .rodata,"a",@progbits
.globl _Z6prova3v
.p2align 3, 0x0
_Z6prova3v:
.quad _Z21__device_stub__prova3v
.size _Z6prova3v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6prova3v"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__prova3v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6prova3v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6prova3v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6prova3v
.globl _Z6prova3v
.p2align 8
.type _Z6prova3v,@function
_Z6prova3v:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6prova3v
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6prova3v, .Lfunc_end0-_Z6prova3v
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6prova3v
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6prova3v.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014b550_00000000-6_prova3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6prova3vv
.type _Z24__device_stub__Z6prova3vv, @function
_Z24__device_stub__Z6prova3vv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6prova3v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z6prova3vv, .-_Z24__device_stub__Z6prova3vv
.globl _Z6prova3v
.type _Z6prova3v, @function
_Z6prova3v:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6prova3vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6prova3v, .-_Z6prova3v
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6prova3v"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6prova3v(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prova3.hip"
.globl _Z21__device_stub__prova3v # -- Begin function _Z21__device_stub__prova3v
.p2align 4, 0x90
.type _Z21__device_stub__prova3v,@function
_Z21__device_stub__prova3v: # @_Z21__device_stub__prova3v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6prova3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__prova3v, .Lfunc_end0-_Z21__device_stub__prova3v
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6prova3v, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6prova3v,@object # @_Z6prova3v
.section .rodata,"a",@progbits
.globl _Z6prova3v
.p2align 3, 0x0
_Z6prova3v:
.quad _Z21__device_stub__prova3v
.size _Z6prova3v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6prova3v"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__prova3v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6prova3v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ void updateCMax(const int nbrOfGrids, const double *d_u1, const double *d_u2, const double *d_u3, const double *d_gama, double *d_cMax)
{
*d_cMax = 0; int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double ro, p, u;
__shared__ double c;
for (int i = index; i < nbrOfGrids; i += stride){
if (d_u1[i] == 0)
continue;
ro = d_u1[i];
u = d_u2[i] / ro;
p = (d_u3[i] - ro * u * u / 2) * (*d_gama - 1);
c = sqrt(*d_gama * abs(p) / ro);
if (*d_cMax < c + abs(u))
*d_cMax = c + abs(u);
}
}
__global__ void initDeviceMemory(const int nbrOfGrids, double *d_u1, double *d_u2, double *d_u3, double *d_vol, double *d_h, double *d_length, double *d_gama, double *d_cfl, double *d_nu, double *d_tau, double *d_cMax, double *d_t) {
*d_t = 0; // time
*d_length = 1; // length of shock tube
*d_gama = 1.4; // ratio of specific heats
*d_cfl = 0.9; // Courant-Friedrichs-Lewy number
*d_nu = 0.0; // artificial viscosity coefficient
*d_h = *d_length / (nbrOfGrids - 1); // space grid size
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < nbrOfGrids; i+= stride){
double e, ro, p, u = 0;
if (i < nbrOfGrids){
if (i >= int(nbrOfGrids / 2)) { ro = 0.125, p = 0.1; }
else { ro = 1, p = 1; }
e = p / (*d_gama - 1) + ro * u * u / 2;
d_u1[i] = ro;
d_u2[i] = ro * u;
d_u3[i] = e;
d_u3[i] = e;
d_vol[i] = 1;
}
}
updateCMax(nbrOfGrids, d_u1, d_u2, d_u3, d_gama, d_cMax);
*d_tau = (*d_cfl) * (*d_h) / (*d_cMax); // initial time grid size, It will be modified to tMax if this > tMax
} | .file "tmpxft_0016c335_00000000-6_initDeviceMemory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10updateCMaxiPKdS0_S0_S0_Pd
.type _Z10updateCMaxiPKdS0_S0_S0_Pd, @function
_Z10updateCMaxiPKdS0_S0_S0_Pd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10updateCMaxiPKdS0_S0_S0_Pd, .-_Z10updateCMaxiPKdS0_S0_S0_Pd
.globl _Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_
.type _Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_, @function
_Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movl %edi, 108(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 304(%rsp), %rax
movq %rax, 56(%rsp)
movq 312(%rsp), %rax
movq %rax, 48(%rsp)
movq 320(%rsp), %rax
movq %rax, 40(%rsp)
movq 328(%rsp), %rax
movq %rax, 32(%rsp)
movq 336(%rsp), %rax
movq %rax, 24(%rsp)
movq 344(%rsp), %rax
movq %rax, 16(%rsp)
movq 352(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 108(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 312
pushq 120(%rsp)
.cfi_def_cfa_offset 320
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_, .-_Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_
.globl _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.type _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, @function
_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, .-_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ void updateCMax(const int nbrOfGrids, const double *d_u1, const double *d_u2, const double *d_u3, const double *d_gama, double *d_cMax)
{
*d_cMax = 0; int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double ro, p, u;
__shared__ double c;
for (int i = index; i < nbrOfGrids; i += stride){
if (d_u1[i] == 0)
continue;
ro = d_u1[i];
u = d_u2[i] / ro;
p = (d_u3[i] - ro * u * u / 2) * (*d_gama - 1);
c = sqrt(*d_gama * abs(p) / ro);
if (*d_cMax < c + abs(u))
*d_cMax = c + abs(u);
}
}
__global__ void initDeviceMemory(const int nbrOfGrids, double *d_u1, double *d_u2, double *d_u3, double *d_vol, double *d_h, double *d_length, double *d_gama, double *d_cfl, double *d_nu, double *d_tau, double *d_cMax, double *d_t) {
*d_t = 0; // time
*d_length = 1; // length of shock tube
*d_gama = 1.4; // ratio of specific heats
*d_cfl = 0.9; // Courant-Friedrichs-Lewy number
*d_nu = 0.0; // artificial viscosity coefficient
*d_h = *d_length / (nbrOfGrids - 1); // space grid size
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < nbrOfGrids; i+= stride){
double e, ro, p, u = 0;
if (i < nbrOfGrids){
if (i >= int(nbrOfGrids / 2)) { ro = 0.125, p = 0.1; }
else { ro = 1, p = 1; }
e = p / (*d_gama - 1) + ro * u * u / 2;
d_u1[i] = ro;
d_u2[i] = ro * u;
d_u3[i] = e;
d_u3[i] = e;
d_vol[i] = 1;
}
}
updateCMax(nbrOfGrids, d_u1, d_u2, d_u3, d_gama, d_cMax);
*d_tau = (*d_cfl) * (*d_h) / (*d_cMax); // initial time grid size, It will be modified to tMax if this > tMax
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void updateCMax(const int nbrOfGrids, const double *d_u1, const double *d_u2, const double *d_u3, const double *d_gama, double *d_cMax)
{
*d_cMax = 0; int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double ro, p, u;
__shared__ double c;
for (int i = index; i < nbrOfGrids; i += stride){
if (d_u1[i] == 0)
continue;
ro = d_u1[i];
u = d_u2[i] / ro;
p = (d_u3[i] - ro * u * u / 2) * (*d_gama - 1);
c = sqrt(*d_gama * abs(p) / ro);
if (*d_cMax < c + abs(u))
*d_cMax = c + abs(u);
}
}
__global__ void initDeviceMemory(const int nbrOfGrids, double *d_u1, double *d_u2, double *d_u3, double *d_vol, double *d_h, double *d_length, double *d_gama, double *d_cfl, double *d_nu, double *d_tau, double *d_cMax, double *d_t) {
*d_t = 0; // time
*d_length = 1; // length of shock tube
*d_gama = 1.4; // ratio of specific heats
*d_cfl = 0.9; // Courant-Friedrichs-Lewy number
*d_nu = 0.0; // artificial viscosity coefficient
*d_h = *d_length / (nbrOfGrids - 1); // space grid size
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < nbrOfGrids; i+= stride){
double e, ro, p, u = 0;
if (i < nbrOfGrids){
if (i >= int(nbrOfGrids / 2)) { ro = 0.125, p = 0.1; }
else { ro = 1, p = 1; }
e = p / (*d_gama - 1) + ro * u * u / 2;
d_u1[i] = ro;
d_u2[i] = ro * u;
d_u3[i] = e;
d_u3[i] = e;
d_vol[i] = 1;
}
}
updateCMax(nbrOfGrids, d_u1, d_u2, d_u3, d_gama, d_cMax);
*d_tau = (*d_cfl) * (*d_h) / (*d_cMax); // initial time grid size, It will be modified to tMax if this > tMax
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void updateCMax(const int nbrOfGrids, const double *d_u1, const double *d_u2, const double *d_u3, const double *d_gama, double *d_cMax)
{
*d_cMax = 0; int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double ro, p, u;
__shared__ double c;
for (int i = index; i < nbrOfGrids; i += stride){
if (d_u1[i] == 0)
continue;
ro = d_u1[i];
u = d_u2[i] / ro;
p = (d_u3[i] - ro * u * u / 2) * (*d_gama - 1);
c = sqrt(*d_gama * abs(p) / ro);
if (*d_cMax < c + abs(u))
*d_cMax = c + abs(u);
}
}
__global__ void initDeviceMemory(const int nbrOfGrids, double *d_u1, double *d_u2, double *d_u3, double *d_vol, double *d_h, double *d_length, double *d_gama, double *d_cfl, double *d_nu, double *d_tau, double *d_cMax, double *d_t) {
*d_t = 0; // time
*d_length = 1; // length of shock tube
*d_gama = 1.4; // ratio of specific heats
*d_cfl = 0.9; // Courant-Friedrichs-Lewy number
*d_nu = 0.0; // artificial viscosity coefficient
*d_h = *d_length / (nbrOfGrids - 1); // space grid size
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < nbrOfGrids; i+= stride){
double e, ro, p, u = 0;
if (i < nbrOfGrids){
if (i >= int(nbrOfGrids / 2)) { ro = 0.125, p = 0.1; }
else { ro = 1, p = 1; }
e = p / (*d_gama - 1) + ro * u * u / 2;
d_u1[i] = ro;
d_u2[i] = ro * u;
d_u3[i] = e;
d_u3[i] = e;
d_vol[i] = 1;
}
}
updateCMax(nbrOfGrids, d_u1, d_u2, d_u3, d_gama, d_cMax);
*d_tau = (*d_cfl) * (*d_h) / (*d_cMax); // initial time grid size, It will be modified to tMax if this > tMax
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.globl _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.p2align 8
.type _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_,@function
_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x60
s_load_b256 s[4:11], s[0:1], 0x28
s_load_b64 s[16:17], s[0:1], 0x48
s_mov_b32 s12, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v1, 0
s_mov_b32 s13, s12
v_dual_mov_b32 v2, 0x3ff00000 :: v_dual_mov_b32 v7, s12
v_dual_mov_b32 v3, 0x66666666 :: v_dual_mov_b32 v8, s13
v_mov_b32_e32 v4, 0x3ff66666
v_mov_b32_e32 v9, 0xcccccccd
v_mov_b32_e32 v10, 0x3feccccc
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x4
global_store_b64 v6, v[7:8], s[2:3]
global_store_b64 v6, v[1:2], s[6:7]
global_store_b64 v6, v[3:4], s[8:9]
global_store_b64 v6, v[9:10], s[10:11]
global_store_b64 v6, v[7:8], s[16:17]
global_load_b64 v[1:2], v6, s[6:7]
s_clause 0x1
s_load_b32 s3, s[0:1], 0x0
s_load_b128 s[16:19], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, -1
s_add_u32 s20, s0, 0x68
v_cvt_f64_i32_e32 v[3:4], s2
s_addc_u32 s21, s1, 0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], v[1:2]
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_div_scale_f64 v[11:12], vcc_lo, v[1:2], v[3:4], v[1:2]
v_mul_f64 v[13:14], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12]
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[1:2], v[7:8], v[3:4], v[1:2]
global_store_b64 v6, v[1:2], s[4:5]
s_clause 0x2
s_load_b32 s2, s[0:1], 0x74
s_load_b32 s24, s[0:1], 0x68
s_load_b64 s[6:7], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[22:23], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_lshr_b32 s2, s3, 31
v_dual_mov_b32 v7, 0x3ff00000 :: v_dual_mov_b32 v4, 0
s_add_i32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_ashr_i32 s25, s2, 1
s_lshl_b32 s26, s13, 3
s_mov_b32 s27, s12
.LBB0_2:
global_load_b64 v[8:9], v6, s[8:9]
v_cmp_gt_i32_e32 vcc_lo, s25, v1
v_add_nc_u32_e32 v1, s13, v1
v_dual_mov_b32 v5, v4 :: v_dual_cndmask_b32 v12, 0x3fb99999, v7
v_cndmask_b32_e64 v11, 0x9999999a, 0, vcc_lo
v_cndmask_b32_e32 v10, 0x3fc00000, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s3, v1
s_or_b32 s12, s2, s12
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[8:9], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[13:14], null, v[8:9], v[8:9], v[11:12]
v_div_scale_f64 v[19:20], vcc_lo, v[11:12], v[8:9], v[11:12]
v_rcp_f64_e32 v[15:16], v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_mul_f64 v[17:18], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[13:14], v[17:18], v[19:20]
v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[8:9], v[13:14], v[8:9], v[11:12]
v_add_co_u32 v13, vcc_lo, s16, v2
v_add_co_ci_u32_e32 v14, vcc_lo, s17, v3, vcc_lo
v_add_co_u32 v15, vcc_lo, s18, v2
v_add_co_ci_u32_e32 v16, vcc_lo, s19, v3, vcc_lo
v_add_co_u32 v17, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v19, vcc_lo, s22, v2
v_add_co_ci_u32_e32 v20, vcc_lo, s23, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s26
v_add_co_ci_u32_e32 v3, vcc_lo, s27, v3, vcc_lo
v_add_f64 v[11:12], v[8:9], 0
v_mov_b32_e32 v9, 0
global_store_b64 v[13:14], v[9:10], off
global_store_b64 v[15:16], v[4:5], off
v_mov_b32_e32 v5, v7
global_store_b64 v[17:18], v[11:12], off
global_store_b64 v[19:20], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s14
s_load_b64 s[12:13], s[0:1], 0x58
v_mov_b32_e32 v1, 0
s_cmp_lt_u32 s15, s24
v_mov_b32_e32 v11, 0
s_cselect_b32 s2, 12, 18
s_mov_b32 s14, exec_lo
v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v3, s2
s_waitcnt lgkmcnt(0)
global_store_b64 v11, v[1:2], s[12:13]
global_load_u16 v3, v3, s[20:21]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1]
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_9
v_mul_lo_u32 v3, s24, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[3:4]
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, v1, v3
v_add_co_u32 v5, s2, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s2, v6, v8, s2
v_cmp_le_i32_e32 vcc_lo, s3, v1
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_9
.LBB0_6:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s17, v6, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f64_e32 0, v[9:10]
s_cbranch_execz .LBB0_5
v_add_co_u32 v12, vcc_lo, s18, v5
v_add_co_ci_u32_e32 v13, vcc_lo, s19, v6, vcc_lo
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[14:15], null, v[9:10], v[9:10], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[16:17], v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
v_add_co_u32 v18, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v19, vcc_lo, s7, v6, vcc_lo
v_div_scale_f64 v[24:25], vcc_lo, v[12:13], v[9:10], v[12:13]
global_load_b64 v[20:21], v11, s[8:9]
global_load_b64 v[18:19], v[18:19], off
v_fma_f64 v[22:23], -v[14:15], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
v_mul_f64 v[22:23], v[24:25], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[14:15], v[22:23], v[24:25]
v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
global_load_b64 v[16:17], v11, s[12:13]
v_div_fixup_f64 v[12:13], v[14:15], v[9:10], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[9:10], v[12:13]
v_mul_f64 v[14:15], v[12:13], v[14:15]
s_waitcnt vmcnt(2)
v_add_f64 v[22:23], v[20:21], -1.0
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], -0.5, v[18:19]
v_mul_f64 v[14:15], v[22:23], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[20:21], |v[14:15]|
v_div_scale_f64 v[18:19], null, v[9:10], v[9:10], v[14:15]
v_div_scale_f64 v[24:25], vcc_lo, v[14:15], v[9:10], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[20:21], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[22:23], v[24:25], v[20:21]
v_fma_f64 v[18:19], -v[18:19], v[22:23], v[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[18:19], v[18:19], v[20:21], v[22:23]
v_div_fixup_f64 v[9:10], v[18:19], v[9:10], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[9:10]
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
v_lshlrev_b32_e32 v0, 8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ldexp_f64 v[9:10], v[9:10], v0
v_cndmask_b32_e64 v0, 0, 0xffffff80, vcc_lo
v_rsq_f64_e32 v[14:15], v[9:10]
v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[18:19], v[9:10], v[14:15]
v_mul_f64 v[14:15], v[14:15], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], -v[14:15], v[18:19], 0.5
v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], -v[18:19], v[18:19], v[9:10]
v_fma_f64 v[18:19], v[20:21], v[14:15], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], -v[18:19], v[18:19], v[9:10]
v_fma_f64 v[14:15], v[20:21], v[14:15], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[14:15], v[14:15], v0
v_dual_cndmask_b32 v9, v14, v9 :: v_dual_cndmask_b32 v10, v15, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], |v[12:13]|, v[9:10]
s_waitcnt vmcnt(0)
v_cmp_lt_f64_e32 vcc_lo, v[16:17], v[9:10]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
global_store_b64 v11, v[9:10], s[12:13]
s_branch .LBB0_5
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v12, 0
s_load_b64 s[0:1], s[0:1], 0x50
s_clause 0x2
global_load_b64 v[0:1], v12, s[4:5]
global_load_b64 v[2:3], v12, s[10:11]
global_load_b64 v[4:5], v12, s[12:13]
s_waitcnt vmcnt(1)
v_mul_f64 v[0:1], v[2:3], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[2:3], null, v[4:5], v[4:5], v[0:1]
v_rcp_f64_e32 v[6:7], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[4:5], v[0:1]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[10:11], v[8:9]
v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[2:3], v[4:5], v[0:1]
s_waitcnt lgkmcnt(0)
global_store_b64 v12, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 360
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .offset: 104
.size: 4
.value_kind: hidden_block_count_x
- .offset: 108
.size: 4
.value_kind: hidden_block_count_y
- .offset: 112
.size: 4
.value_kind: hidden_block_count_z
- .offset: 116
.size: 2
.value_kind: hidden_group_size_x
- .offset: 118
.size: 2
.value_kind: hidden_group_size_y
- .offset: 120
.size: 2
.value_kind: hidden_group_size_z
- .offset: 122
.size: 2
.value_kind: hidden_remainder_x
- .offset: 124
.size: 2
.value_kind: hidden_remainder_y
- .offset: 126
.size: 2
.value_kind: hidden_remainder_z
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 168
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 360
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void updateCMax(const int nbrOfGrids, const double *d_u1, const double *d_u2, const double *d_u3, const double *d_gama, double *d_cMax)
{
*d_cMax = 0; int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double ro, p, u;
__shared__ double c;
for (int i = index; i < nbrOfGrids; i += stride){
if (d_u1[i] == 0)
continue;
ro = d_u1[i];
u = d_u2[i] / ro;
p = (d_u3[i] - ro * u * u / 2) * (*d_gama - 1);
c = sqrt(*d_gama * abs(p) / ro);
if (*d_cMax < c + abs(u))
*d_cMax = c + abs(u);
}
}
__global__ void initDeviceMemory(const int nbrOfGrids, double *d_u1, double *d_u2, double *d_u3, double *d_vol, double *d_h, double *d_length, double *d_gama, double *d_cfl, double *d_nu, double *d_tau, double *d_cMax, double *d_t) {
*d_t = 0; // time
*d_length = 1; // length of shock tube
*d_gama = 1.4; // ratio of specific heats
*d_cfl = 0.9; // Courant-Friedrichs-Lewy number
*d_nu = 0.0; // artificial viscosity coefficient
*d_h = *d_length / (nbrOfGrids - 1); // space grid size
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < nbrOfGrids; i+= stride){
double e, ro, p, u = 0;
if (i < nbrOfGrids){
if (i >= int(nbrOfGrids / 2)) { ro = 0.125, p = 0.1; }
else { ro = 1, p = 1; }
e = p / (*d_gama - 1) + ro * u * u / 2;
d_u1[i] = ro;
d_u2[i] = ro * u;
d_u3[i] = e;
d_u3[i] = e;
d_vol[i] = 1;
}
}
updateCMax(nbrOfGrids, d_u1, d_u2, d_u3, d_gama, d_cMax);
*d_tau = (*d_cfl) * (*d_h) / (*d_cMax); // initial time grid size, It will be modified to tMax if this > tMax
} | .text
.file "initDeviceMemory.hip"
.globl _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_,@function
_Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_: # @_Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_,@object # @_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_:
.quad _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.size _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016c335_00000000-6_initDeviceMemory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10updateCMaxiPKdS0_S0_S0_Pd
.type _Z10updateCMaxiPKdS0_S0_S0_Pd, @function
_Z10updateCMaxiPKdS0_S0_S0_Pd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10updateCMaxiPKdS0_S0_S0_Pd, .-_Z10updateCMaxiPKdS0_S0_S0_Pd
.globl _Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_
.type _Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_, @function
_Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movl %edi, 108(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 304(%rsp), %rax
movq %rax, 56(%rsp)
movq 312(%rsp), %rax
movq %rax, 48(%rsp)
movq 320(%rsp), %rax
movq %rax, 40(%rsp)
movq 328(%rsp), %rax
movq %rax, 32(%rsp)
movq 336(%rsp), %rax
movq %rax, 24(%rsp)
movq 344(%rsp), %rax
movq %rax, 16(%rsp)
movq 352(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 108(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 312
pushq 120(%rsp)
.cfi_def_cfa_offset 320
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_, .-_Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_
.globl _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.type _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, @function
_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z59__device_stub__Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_S_
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, .-_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "initDeviceMemory.hip"
.globl _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_,@function
_Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_: # @_Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_,@object # @_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_:
.quad _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.size _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16initDeviceMemoryiPdS_S_S_S_S_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define ABS(X) X < 0 ? -X : X
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter);
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter);
/* We define a maximum number of iterations the kernel can do, so that
* it isn't rudely interrupted by the watchdog timer */
static const long max_iterations = 1L<<30;
static const int block_size = 128;
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter) {
float *region, *d_region;
dim3 threadsPerBlock(block_size);
dim3 blocks;
float4 boundary;
int size = res_x * res_y;
size_t host_bytes = (size_t) size * sizeof(float);
size_t job_bytes;
size_t jobsize;
cudaStream_t copy_stream; // Stream for copying between host and device
if(cudaStreamCreate(©_stream) != cudaSuccess)
return NULL;
region = (float*) malloc(host_bytes);
if(!region)
goto cleanup3;
/* Find some number of pixels that is a power of two, evenly divides up
* the work, and causes the kernel to compute at most max_iterations */
jobsize = block_size;
for(;!(size & (jobsize - 1)) && (jobsize * iter <= max_iterations); jobsize <<= 1);
jobsize >>= 1;
if(jobsize < block_size)
goto cleanup3;
fprintf(stderr, "%s: %d. %s: %d.\n", "Number of pixels", size,
"Number of pixels per job", jobsize);
blocks = dim3(jobsize / threadsPerBlock.x);
job_bytes = jobsize * sizeof(float);
boundary.x = min_x;
boundary.y = min_y;
boundary.z = max_x;
boundary.w = max_y;
if(cudaMalloc(&d_region, job_bytes) != cudaSuccess)
goto cleanup2;
for(int start = 0; start <= (size - jobsize); start += jobsize) {
mandelbrot<<<blocks, threadsPerBlock>>>(d_region, start, make_int2(res_x, res_y), boundary, iter);
if(cudaMemcpy(®ion[start], d_region, job_bytes, cudaMemcpyDeviceToHost) != cudaSuccess)
goto cleanup1;
}
cudaFree(d_region);
cudaStreamDestroy(copy_stream);
return region;
cleanup1:
cudaFree(d_region);
cleanup2:
free(region);
cleanup3:
cudaStreamDestroy(copy_stream);
return NULL;
}
/* Calculates the mandelbrot set and stores the results in region, which
* should be of length gridDim.x * blockDim.x * gridDim.y * blockDim.y
* The float4 boundary specifies the region of the complex plane to test
* for divergence, with the x, y, z, and w components representing the minimum
* x, minimum y, maximum x, and maximum y values of the rectangular region. */
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int pixel = index + offset;
int pixel_x = pixel % res.x;
int pixel_y = pixel / res.x;
double2 c, z;
int i;
c.x = ((boundary.z - boundary.x) * (((double) pixel_x) + 0.5))/(res.x) + boundary.x;
c.y = ((boundary.y - boundary.w) * (((double) pixel_y) + 0.5))/(res.y) + boundary.w;
z = c;
for(i=1;(i<iter) && (z.x*z.x+z.y*z.y <= 4);i++)
z = make_double2(z.x * z.x - z.y*z.y + c.x,
2*z.x*z.y + c.y);
region[index] = (i >= iter) ? (-1) : i + 2 - log2f(log2f(z.x*z.x+z.y*z.y));
} | code for sm_80
Function : _Z10mandelbrotPfi4int26float4i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0030*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0040*/ BSSY B0, 0x390 ; /* 0x0000034000007945 */
/* 0x000fe20003800000 */
/*0050*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0070*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0e7624 */
/* 0x000fc800078e00ff */
/*0080*/ FADD R14, R14, -c[0x0][0x180] ; /* 0x800060000e0e7621 */
/* 0x000fe40000000000 */
/*0090*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*00b0*/ IADD3 R5, R0, c[0x0][0x168], RZ ; /* 0x00005a0000057a10 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fc60000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*0130*/ IMAD.HI.U32 R4, R3, R6, RZ ; /* 0x0000000603047227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R2, RZ, RZ, -R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a04 */
/*0150*/ IMAD R6, R7.reuse, R2, R6 ; /* 0x0000000207067224 */
/* 0x040fe400078e0206 */
/*0160*/ I2F.F64 R2, c[0x0][0x170] ; /* 0x00005c0000027b12 */
/* 0x000e260000201c00 */
/*0170*/ ISETP.GT.U32.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fda0003f24070 */
/*0180*/ @!P1 IADD3 R6, R6, -R7.reuse, RZ ; /* 0x8000000706069210 */
/* 0x080fe20007ffe0ff */
/*0190*/ MUFU.RCP64H R11, R3 ; /* 0x00000003000b7308 */
/* 0x001e220000001800 */
/*01a0*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe40003f06070 */
/*01c0*/ LOP3.LUT R6, R5, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0005067a12 */
/* 0x000fe400078e3cff */
/*01d0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25270 */
/*01e0*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fce0003f46270 */
/*01f0*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fcc0007ffe0ff */
/*0200*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0a04 */
/*0210*/ @!P1 LOP3.LUT R4, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff049a12 */
/* 0x000fca00078e33ff */
/*0220*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*0230*/ IMAD R5, R6, c[0x0][0x170], R5 ; /* 0x00005c0006057a24 */
/* 0x000fe200078e0205 */
/*0240*/ DFMA R6, -R2, R10, 1 ; /* 0x3ff000000206742b */
/* 0x001e06000000010a */
/*0250*/ I2F.F64 R8, R5 ; /* 0x0000000500087312 */
/* 0x000e660000201c00 */
/*0260*/ DFMA R12, R6, R6, R6 ; /* 0x00000006060c722b */
/* 0x00108a0000000006 */
/*0270*/ F2F.F64.F32 R6, R14 ; /* 0x0000000e00067310 */
/* 0x001e220000201800 */
/*0280*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x004e8c000000000a */
/*0290*/ DFMA R10, -R2, R12, 1 ; /* 0x3ff00000020a742b */
/* 0x004e88000000010c */
/*02a0*/ DADD R8, R8, 0.5 ; /* 0x3fe0000008087429 */
/* 0x002e080000000000 */
/*02b0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x004fc8000000000c */
/*02c0*/ DMUL R12, R6, R8 ; /* 0x00000008060c7228 */
/* 0x001e0c0000000000 */
/*02d0*/ DMUL R6, R12, R10 ; /* 0x0000000a0c067228 */
/* 0x001e080000000000 */
/*02e0*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe40003f2e200 */
/*02f0*/ DFMA R8, -R2, R6, R12 ; /* 0x000000060208722b */
/* 0x001e0c000000010c */
/*0300*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x001e140000000006 */
/*0310*/ FFMA R5, RZ, R3, R7 ; /* 0x00000003ff057223 */
/* 0x001fca0000000007 */
/*0320*/ FSETP.GT.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x000fda0003f04200 */
/*0330*/ @P0 BRA P1, 0x380 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0340*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x000fe20000000f00 */
/*0350*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e000d */
/*0360*/ MOV R12, 0x380 ; /* 0x00000380000c7802 */
/* 0x000fe40000000f00 */
/*0370*/ CALL.REL.NOINC 0xb00 ; /* 0x0000078000007944 */
/* 0x000fea0003c00000 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ I2F.F64 R2, c[0x0][0x174] ; /* 0x00005d0000027b12 */
/* 0x000e220000201c00 */
/*03a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*03b0*/ BSSY B0, 0x560 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*03c0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff107624 */
/* 0x002fc800078e00ff */
/*03d0*/ FADD R16, R16, -c[0x0][0x18c] ; /* 0x8000630010107621 */
/* 0x000fe20000000000 */
/*03e0*/ I2F.F64 R4, R4 ; /* 0x0000000400047312 */
/* 0x000e700000201c00 */
/*03f0*/ MUFU.RCP64H R11, R3 ; /* 0x00000003000b7308 */
/* 0x001e240000001800 */
/*0400*/ DFMA R8, -R2, R10, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c000000010a */
/*0410*/ DFMA R12, R8, R8, R8 ; /* 0x00000008080c722b */
/* 0x0010880000000008 */
/*0420*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x001e240000201800 */
/*0430*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x004e88000000000a */
/*0440*/ DADD R10, R4, 0.5 ; /* 0x3fe00000040a7429 */
/* 0x002e080000000000 */
/*0450*/ DFMA R14, -R2, R12, 1 ; /* 0x3ff00000020e742b */
/* 0x004e48000000010c */
/*0460*/ DMUL R10, R8, R10 ; /* 0x0000000a080a7228 */
/* 0x001fc80000000000 */
/*0470*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x002e0c000000000c */
/*0480*/ DMUL R4, R10, R14 ; /* 0x0000000e0a047228 */
/* 0x001e220000000000 */
/*0490*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x000fca0003f2e200 */
/*04a0*/ DFMA R8, -R2, R4, R10 ; /* 0x000000040208722b */
/* 0x001e0c000000010a */
/*04b0*/ DFMA R8, R14, R8, R4 ; /* 0x000000080e08722b */
/* 0x0010640000000004 */
/*04c0*/ F2F.F64.F32 R4, c[0x0][0x180] ; /* 0x0000600000047b10 */
/* 0x001e300000201800 */
/*04d0*/ FFMA R12, RZ, R3, R9 ; /* 0x00000003ff0c7223 */
/* 0x002fca0000000009 */
/*04e0*/ FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ; /* 0x001000000c00780b */
/* 0x000fe20003f04200 */
/*04f0*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x0010580000000006 */
/*0500*/ @P0 BRA P1, 0x550 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0510*/ MOV R12, 0x530 ; /* 0x00000530000c7802 */
/* 0x003fe40000000f00 */
/*0520*/ CALL.REL.NOINC 0xb00 ; /* 0x000005d000007944 */
/* 0x000fea0003c00000 */
/*0530*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0540*/ MOV R9, R7 ; /* 0x0000000700097202 */
/* 0x000fe40000000f00 */
/*0550*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*0560*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff067624 */
/* 0x000fe200078e00ff */
/*0570*/ F2F.F64.F32 R2, c[0x0][0x18c] ; /* 0x0000630000027b10 */
/* 0x000e220000201800 */
/*0580*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0590*/ IMAD.MOV.U32 R19, RZ, RZ, -0x40800000 ; /* 0xbf800000ff137424 */
/* 0x000fe400078e00ff */
/*05a0*/ ISETP.GE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe20003f06270 */
/*05b0*/ DADD R14, R2, R8 ; /* 0x00000000020e7229 */
/* 0x0010580000000008 */
/*05c0*/ @!P0 BRA 0xac0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*05d0*/ BSSY B0, 0xac0 ; /* 0x000004e000007945 */
/* 0x000fe20003800000 */
/*05e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x001fe200078e00ff */
/*05f0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0610*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x002fe400078e000e */
/*0620*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fcc00078e000f */
/*0630*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x000fc80000000000 */
/*0640*/ DMUL R12, R6, R6 ; /* 0x00000006060c7228 */
/* 0x000e0c0000000000 */
/*0650*/ DADD R16, R10, R12 ; /* 0x000000000a107229 */
/* 0x001e0c000000000c */
/*0660*/ DSETP.GTU.AND P0, PT, R16, 4, PT ; /* 0x401000001000742a */
/* 0x001e1c0003f0c000 */
/*0670*/ @P0 BRA 0x700 ; /* 0x0000008000000947 */
/* 0x001fea0003800000 */
/*0680*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe20007ffe0ff */
/*0690*/ DADD R10, -R10, R12 ; /* 0x000000000a0a7229 */
/* 0x000e06000000010c */
/*06a0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe20003f06270 */
/*06b0*/ DADD R12, R6, R6 ; /* 0x00000000060c7229 */
/* 0x000e480000000006 */
/*06c0*/ DADD R6, R4, R10 ; /* 0x0000000004067229 */
/* 0x001088000000000a */
/*06d0*/ DFMA R8, R12, R8, R14 ; /* 0x000000080c08722b */
/* 0x002048000000000e */
/*06e0*/ @!P0 BRA 0x630 ; /* 0xffffff4000008947 */
/* 0x007fea000383ffff */
/*06f0*/ BRA 0xab0 ; /* 0x000003b000007947 */
/* 0x000fea0003800000 */
/*0700*/ F2F.F32.F64 R3, R16 ; /* 0x0000001000037310 */
/* 0x000e220000301000 */
/*0710*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3dc6b27f ; /* 0x3dc6b27fff0a7424 */
/* 0x000fe200078e00ff */
/*0720*/ IADD3 R2, R2, 0x2, RZ ; /* 0x0000000202027810 */
/* 0x000fcc0007ffe0ff */
/*0730*/ I2F R2, R2 ; /* 0x0000000200027306 */
/* 0x000fe20000201400 */
/*0740*/ FSETP.GEU.AND P0, PT, R3, 1.175494350822287508e-38, PT ; /* 0x008000000300780b */
/* 0x001fda0003f0e000 */
/*0750*/ @!P0 FMUL R3, R3, 8388608 ; /* 0x4b00000003038820 */
/* 0x000fca0000400000 */
/*0760*/ IADD3 R4, R3.reuse, -0x3f3504f3, RZ ; /* 0xc0cafb0d03047810 */
/* 0x040fe40007ffe0ff */
/*0770*/ ISETP.GE.U32.AND P1, PT, R3, 0x7f800000, PT ; /* 0x7f8000000300780c */
/* 0x000fe40003f26070 */
/*0780*/ LOP3.LUT R6, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004067812 */
/* 0x000fc800078ec0ff */
/*0790*/ IADD3 R4, R3, -R6, RZ ; /* 0x8000000603047210 */
/* 0x000fe20007ffe0ff */
/*07a0*/ I2F R5, R6 ; /* 0x0000000600057306 */
/* 0x000e280000201400 */
/*07b0*/ FADD R7, R4, -1 ; /* 0xbf80000004077421 */
/* 0x000fc80000000000 */
/*07c0*/ FFMA R4, R7, R10, -0.16845393180847167969 ; /* 0xbe2c7f3007047423 */
/* 0x000fc8000000000a */
/*07d0*/ FFMA R4, R7, R4, 0.1716887056827545166 ; /* 0x3e2fcf2a07047423 */
/* 0x000fc80000000004 */
/*07e0*/ FFMA R4, R7, R4, -0.17900948226451873779 ; /* 0xbe374e4307047423 */
/* 0x000fc80000000004 */
/*07f0*/ FFMA R4, R7, R4, 0.20512372255325317383 ; /* 0x3e520bf407047423 */
/* 0x000fc80000000004 */
/*0800*/ FFMA R4, R7, R4, -0.24046532809734344482 ; /* 0xbe763c8b07047423 */
/* 0x000fc80000000004 */
/*0810*/ FFMA R4, R7, R4, 0.28857114911079406738 ; /* 0x3e93bf9907047423 */
/* 0x000fc80000000004 */
/*0820*/ FFMA R4, R7, R4, -0.36067417263984680176 ; /* 0xbeb8aa4907047423 */
/* 0x000fc80000000004 */
/*0830*/ FFMA R4, R7, R4, 0.48089820146560668945 ; /* 0x3ef6384a07047423 */
/* 0x000fc80000000004 */
/*0840*/ FFMA R4, R7, R4, -0.72134751081466674805 ; /* 0xbf38aa3b07047423 */
/* 0x000fc80000000004 */
/*0850*/ FMUL R8, R7, R4 ; /* 0x0000000407087220 */
/* 0x000fe20000400000 */
/*0860*/ FSEL R4, RZ, -23, P0 ; /* 0xc1b80000ff047808 */
/* 0x000fe40000000000 */
/*0870*/ FSETP.NEU.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f0d000 */
/*0880*/ FMUL R8, R7, R8 ; /* 0x0000000807087220 */
/* 0x000fe40000400000 */
/*0890*/ FFMA R4, R5, 1.1920928955078125e-07, R4 ; /* 0x3400000005047823 */
/* 0x001fe40000000004 */
/*08a0*/ FFMA R7, R7, 1.4426950216293334961, R8 ; /* 0x3fb8aa3b07077823 */
/* 0x000fe40000000008 */
/*08b0*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, 0x7f800000 ; /* 0x7f800000ff081424 */
/* 0x000fc400078e00ff */
/*08c0*/ FADD R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x000fe40000000000 */
/*08d0*/ @P1 FFMA R4, R3, R8, +INF ; /* 0x7f80000003041423 */
/* 0x000fca0000000008 */
/*08e0*/ FSEL R4, R4, -INF , P0 ; /* 0xff80000004047808 */
/* 0x000fc80000000000 */
/*08f0*/ FSETP.GEU.AND P0, PT, R4, 1.175494350822287508e-38, PT ; /* 0x008000000400780b */
/* 0x000fda0003f0e000 */
/*0900*/ @!P0 FMUL R4, R4, 8388608 ; /* 0x4b00000004048820 */
/* 0x000fca0000400000 */
/*0910*/ IADD3 R3, R4.reuse, -0x3f3504f3, RZ ; /* 0xc0cafb0d04037810 */
/* 0x040fe40007ffe0ff */
/*0920*/ ISETP.GE.U32.AND P1, PT, R4, 0x7f800000, PT ; /* 0x7f8000000400780c */
/* 0x000fe40003f26070 */
/*0930*/ LOP3.LUT R5, R3, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000003057812 */
/* 0x000fca00078ec0ff */
/*0940*/ IMAD.IADD R3, R4, 0x1, -R5 ; /* 0x0000000104037824 */
/* 0x000fc800078e0a05 */
/*0950*/ FADD R7, R3, -1 ; /* 0xbf80000003077421 */
/* 0x000fe20000000000 */
/*0960*/ FSEL R3, RZ, -23, P0 ; /* 0xc1b80000ff037808 */
/* 0x000fe40000000000 */
/*0970*/ FSETP.NEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fe20003f0d000 */
/*0980*/ FFMA R6, R7, R10, -0.16845393180847167969 ; /* 0xbe2c7f3007067423 */
/* 0x000fc8000000000a */
/*0990*/ FFMA R6, R7, R6, 0.1716887056827545166 ; /* 0x3e2fcf2a07067423 */
/* 0x000fc80000000006 */
/*09a0*/ FFMA R6, R7, R6, -0.17900948226451873779 ; /* 0xbe374e4307067423 */
/* 0x000fc80000000006 */
/*09b0*/ FFMA R6, R7, R6, 0.20512372255325317383 ; /* 0x3e520bf407067423 */
/* 0x000fc80000000006 */
/*09c0*/ FFMA R6, R7, R6, -0.24046532809734344482 ; /* 0xbe763c8b07067423 */
/* 0x000fc80000000006 */
/*09d0*/ FFMA R6, R7, R6, 0.28857114911079406738 ; /* 0x3e93bf9907067423 */
/* 0x000fc80000000006 */
/*09e0*/ FFMA R8, R7.reuse, R6, -0.36067417263984680176 ; /* 0xbeb8aa4907087423 */
/* 0x040fe40000000006 */
/*09f0*/ I2F R6, R5 ; /* 0x0000000500067306 */
/* 0x0000640000201400 */
/*0a00*/ FFMA R8, R7, R8, 0.48089820146560668945 ; /* 0x3ef6384a07087423 */
/* 0x000fc80000000008 */
/*0a10*/ FFMA R8, R7, R8, -0.72134751081466674805 ; /* 0xbf38aa3b07087423 */
/* 0x000fe20000000008 */
/*0a20*/ @P1 MOV R5, 0x7f800000 ; /* 0x7f80000000051802 */
/* 0x001fc60000000f00 */
/*0a30*/ FMUL R8, R7, R8 ; /* 0x0000000807087220 */
/* 0x000fc80000400000 */
/*0a40*/ FMUL R8, R7.reuse, R8 ; /* 0x0000000807087220 */
/* 0x040fe40000400000 */
/*0a50*/ FFMA R3, R6, 1.1920928955078125e-07, R3 ; /* 0x3400000006037823 */
/* 0x002fe40000000003 */
/*0a60*/ FFMA R8, R7, 1.4426950216293334961, R8 ; /* 0x3fb8aa3b07087823 */
/* 0x000fc80000000008 */
/*0a70*/ FADD R3, R3, R8 ; /* 0x0000000803037221 */
/* 0x000fe40000000000 */
/*0a80*/ @P1 FFMA R3, R4, R5, +INF ; /* 0x7f80000004031423 */
/* 0x000fca0000000005 */
/*0a90*/ FSEL R3, R3, -INF , P0 ; /* 0xff80000003037808 */
/* 0x000fca0000000000 */
/*0aa0*/ FADD R19, -R3, R2 ; /* 0x0000000203137221 */
/* 0x000fe40000000100 */
/*0ab0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ac0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fc800078e00ff */
/*0ad0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0ae0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c101904 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*0b10*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0b20*/ LOP3.LUT R6, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03067812 */
/* 0x000fe200078ec0ff */
/*0b30*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*0b40*/ FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f4e200 */
/*0b50*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0b60*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0b70*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0b80*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe20000000f00 */
/*0b90*/ BSSY B1, 0x10c0 ; /* 0x0000052000017945 */
/* 0x000fe20003800000 */
/*0ba0*/ LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0d7812 */
/* 0x000fc400078ec0ff */
/*0bb0*/ LOP3.LUT R20, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003147812 */
/* 0x000fe200078ec0ff */
/*0bc0*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e060000000000 */
/*0bd0*/ ISETP.GE.U32.AND P1, PT, R13, R20, PT ; /* 0x000000140d00720c */
/* 0x000fe40003f26070 */
/*0be0*/ @!P2 LOP3.LUT R2, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000902a812 */
/* 0x000fe200078ec0ff */
/*0bf0*/ MUFU.RCP64H R19, R7 ; /* 0x0000000700137308 */
/* 0x001e220000001800 */
/*0c00*/ SEL R3, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x040fe40004800000 */
/*0c10*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*0c20*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*0c30*/ LOP3.LUT R3, R3, 0x800fffff, R11, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef80b */
/*0c40*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc40005800000 */
/*0c50*/ @!P2 MOV R16, RZ ; /* 0x000000ff0010a202 */
/* 0x000fe40000000f00 */
/*0c60*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R11, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef80b */
/*0c70*/ @!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f11a812 */
/* 0x000fe200078efcff */
/*0c80*/ DFMA R22, R18, -R6, 1 ; /* 0x3ff000001216742b */
/* 0x001e220000000806 */
/*0c90*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0ca0*/ @!P2 DFMA R2, R2, 2, -R16 ; /* 0x400000000202a82b */
/* 0x000fc80000000810 */
/*0cb0*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*0cc0*/ DFMA R18, R18, R22, R18 ; /* 0x000000161212722b */
/* 0x0010620000000012 */
/*0cd0*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fe200078ec0ff */
/*0ce0*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0014 */
/*0cf0*/ @!P0 LOP3.LUT R22, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007168812 */
/* 0x000fe400078ec0ff */
/*0d00*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe20007ffe0ff */
/*0d10*/ DFMA R16, R18, -R6, 1 ; /* 0x3ff000001210742b */
/* 0x002e220000000806 */
/*0d20*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe40007ffe0ff */
/*0d30*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0d40*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*0d50*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fca0000704470 */
/*0d60*/ DMUL R18, R16, R2 ; /* 0x0000000210127228 */
/* 0x001e0c0000000000 */
/*0d70*/ DFMA R20, R18, -R6, R2 ; /* 0x800000061214722b */
/* 0x001e0c0000000002 */
/*0d80*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010620000000012 */
/*0d90*/ @P0 BRA 0xf60 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0da0*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x001fc800078ec0ff */
/*0db0*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*0dc0*/ IMAD.IADD R10, R13, 0x1, -R18 ; /* 0x000000010d0a7824 */
/* 0x000fc600078e0a12 */
/*0dd0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0de0*/ IMNMX R10, R10, -0x46a00000, !PT ; /* 0xb96000000a0a7817 */
/* 0x000fc80007800200 */
/*0df0*/ IMNMX R10, R10, 0x46a00000, PT ; /* 0x46a000000a0a7817 */
/* 0x000fc80003800200 */
/*0e00*/ IADD3 R13, -R13, R10, RZ ; /* 0x0000000a0d0d7210 */
/* 0x000fe20007ffe1ff */
/*0e10*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*0e20*/ IADD3 R11, R13, 0x7fe00000, RZ ; /* 0x7fe000000d0b7810 */
/* 0x000fcc0007ffe0ff */
/*0e30*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x002e140000000000 */
/*0e40*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0e50*/ @P0 BRA 0x10b0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0e60*/ DFMA R2, R16, -R6, R2 ; /* 0x800000061002722b */
/* 0x000e220000000002 */
/*0e70*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e00ff */
/*0e80*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0e90*/ LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4809 */
/*0ea0*/ LOP3.LUT R11, R9, R11, RZ, 0xfc, !PT ; /* 0x0000000b090b7212 */
/* 0x000fce00078efcff */
/*0eb0*/ @!P0 BRA 0x10b0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0ec0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0ed0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe20000000f00 */
/*0ee0*/ DMUL.RP R10, R16, R10 ; /* 0x0000000a100a7228 */
/* 0x000e0a0000008000 */
/*0ef0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e4a0000000010 */
/*0f00*/ LOP3.LUT R9, R11, R9, RZ, 0x3c, !PT ; /* 0x000000090b097212 */
/* 0x001fe400078e3cff */
/*0f10*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0f20*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0f30*/ FSEL R18, R10, R18, !P0 ; /* 0x000000120a127208 */
/* 0x000fe40004000000 */
/*0f40*/ FSEL R19, R9, R19, !P0 ; /* 0x0000001309137208 */
/* 0x000fe20004000000 */
/*0f50*/ BRA 0x10b0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0f60*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*0f70*/ @P0 BRA 0x1090 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0f80*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0f90*/ @P0 BRA 0x1060 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0fa0*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0fb0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0fc0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0fd0*/ @!P0 BRA 0x10b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0fe0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0ff0*/ LOP3.LUT R19, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b137812 */
/* 0x000fe400078e4809 */
/*1000*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*1010*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*1020*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe200078e00ff */
/*1030*/ @P0 MOV R18, RZ ; /* 0x000000ff00120202 */
/* 0x000fc60000000f00 */
/*1040*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*1050*/ BRA 0x10b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1060*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*1070*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*1080*/ BRA 0x10b0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1090*/ LOP3.LUT R19, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b137812 */
/* 0x001fe200078efcff */
/*10a0*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe400078e000a */
/*10b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*10c0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe200078e00ff */
/*10d0*/ MOV R6, R18 ; /* 0x0000001200067202 */
/* 0x000fe20000000f00 */
/*10e0*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0013 */
/*10f0*/ RET.REL.NODEC R12 0x0 ; /* 0xffffef000c007950 */
/* 0x000fea0003c3ffff */
/*1100*/ BRA 0x1100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define ABS(X) X < 0 ? -X : X
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter);
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter);
/* We define a maximum number of iterations the kernel can do, so that
* it isn't rudely interrupted by the watchdog timer */
static const long max_iterations = 1L<<30;
static const int block_size = 128;
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter) {
float *region, *d_region;
dim3 threadsPerBlock(block_size);
dim3 blocks;
float4 boundary;
int size = res_x * res_y;
size_t host_bytes = (size_t) size * sizeof(float);
size_t job_bytes;
size_t jobsize;
cudaStream_t copy_stream; // Stream for copying between host and device
if(cudaStreamCreate(©_stream) != cudaSuccess)
return NULL;
region = (float*) malloc(host_bytes);
if(!region)
goto cleanup3;
/* Find some number of pixels that is a power of two, evenly divides up
* the work, and causes the kernel to compute at most max_iterations */
jobsize = block_size;
for(;!(size & (jobsize - 1)) && (jobsize * iter <= max_iterations); jobsize <<= 1);
jobsize >>= 1;
if(jobsize < block_size)
goto cleanup3;
fprintf(stderr, "%s: %d. %s: %d.\n", "Number of pixels", size,
"Number of pixels per job", jobsize);
blocks = dim3(jobsize / threadsPerBlock.x);
job_bytes = jobsize * sizeof(float);
boundary.x = min_x;
boundary.y = min_y;
boundary.z = max_x;
boundary.w = max_y;
if(cudaMalloc(&d_region, job_bytes) != cudaSuccess)
goto cleanup2;
for(int start = 0; start <= (size - jobsize); start += jobsize) {
mandelbrot<<<blocks, threadsPerBlock>>>(d_region, start, make_int2(res_x, res_y), boundary, iter);
if(cudaMemcpy(®ion[start], d_region, job_bytes, cudaMemcpyDeviceToHost) != cudaSuccess)
goto cleanup1;
}
cudaFree(d_region);
cudaStreamDestroy(copy_stream);
return region;
cleanup1:
cudaFree(d_region);
cleanup2:
free(region);
cleanup3:
cudaStreamDestroy(copy_stream);
return NULL;
}
/* Calculates the mandelbrot set and stores the results in region, which
* should be of length gridDim.x * blockDim.x * gridDim.y * blockDim.y
* The float4 boundary specifies the region of the complex plane to test
* for divergence, with the x, y, z, and w components representing the minimum
* x, minimum y, maximum x, and maximum y values of the rectangular region. */
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int pixel = index + offset;
int pixel_x = pixel % res.x;
int pixel_y = pixel / res.x;
double2 c, z;
int i;
c.x = ((boundary.z - boundary.x) * (((double) pixel_x) + 0.5))/(res.x) + boundary.x;
c.y = ((boundary.y - boundary.w) * (((double) pixel_y) + 0.5))/(res.y) + boundary.w;
z = c;
for(i=1;(i<iter) && (z.x*z.x+z.y*z.y <= 4);i++)
z = make_double2(z.x * z.x - z.y*z.y + c.x,
2*z.x*z.y + c.y);
region[index] = (i >= iter) ? (-1) : i + 2 - log2f(log2f(z.x*z.x+z.y*z.y));
} | .file "tmpxft_0010c7d4_00000000-6_mandelbrot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i
.type _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i, @function
_Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10mandelbrotPfi4int26float4i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i, .-_Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i
.globl _Z10mandelbrotPfi4int26float4i
.type _Z10mandelbrotPfi4int26float4i, @function
_Z10mandelbrotPfi4int26float4i:
.LFB2083:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdx, 24(%rsp)
movq %xmm0, (%rsp)
movq %xmm1, 8(%rsp)
movl %ecx, %r8d
movq %rsp, %rcx
leaq 24(%rsp), %rdx
call _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10mandelbrotPfi4int26float4i, .-_Z10mandelbrotPfi4int26float4i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Number of pixels per job"
.LC1:
.string "Number of pixels"
.LC2:
.string "%s: %d. %s: %d.\n"
.text
.globl create_mandelbrot
.type create_mandelbrot, @function
create_mandelbrot:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %ebx
movl %edi, 12(%rsp)
movl %esi, %r15d
movl %esi, 16(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 32(%rsp)
movl %edx, %r14d
movl %edx, 36(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leaq 56(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %r12d
testl %eax, %eax
jne .L11
imull %r15d, %ebx
movslq %ebx, %rbp
leaq 0(,%rbp,4), %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L13
movl %ebx, %r13d
andl $127, %r13d
jne .L13
movslq %r14d, %rsi
movq %rsi, %rax
salq $7, %rax
cmpq $1073741824, %rax
ja .L13
movl $128, %eax
.L15:
movq %rax, %rcx
addq %rax, %rax
leaq -1(%rax), %rdx
testq %rbp, %rdx
jne .L14
movq %rax, %rdx
imulq %rsi, %rdx
cmpq $1073741824, %rdx
jbe .L15
.L14:
movq %rcx, %r14
btrq $63, %r14
movabsq $9223372036854775680, %rax
testq %rax, %rcx
je .L13
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq %r14
.cfi_def_cfa_offset 208
leaq .LC0(%rip), %r9
movl %ebx, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rax
shrq $7, %rax
movl %eax, 100(%rsp)
leaq 0(,%r14,4), %r15
addq $16, %rsp
.cfi_def_cfa_offset 192
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L16
subq %r14, %rbp
movl $0, %ebx
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
jmp .L19
.L17:
leaq (%r12,%rbx,4), %rdi
movl $2, %ecx
movq %r15, %rdx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L25
leal 0(%r13,%r14), %ebx
movl %ebx, %r13d
movslq %ebx, %rbx
cmpq %rbx, %rbp
jb .L26
.L19:
movl $128, 72(%rsp)
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movl 12(%rsp), %eax
movl %eax, 64(%rsp)
movl 16(%rsp), %eax
movl %eax, 68(%rsp)
movss 20(%rsp), %xmm4
movss %xmm4, 96(%rsp)
movss 24(%rsp), %xmm5
movss %xmm5, 100(%rsp)
movss 28(%rsp), %xmm6
movss %xmm6, 104(%rsp)
movss 32(%rsp), %xmm7
movss %xmm7, 108(%rsp)
leaq 64(%rsp), %rdx
movl 36(%rsp), %r8d
movq 40(%rsp), %rcx
movl %r13d, %esi
movq 48(%rsp), %rdi
call _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i
jmp .L17
.L25:
movq 48(%rsp), %rdi
call cudaFree@PLT
.L16:
movq %r12, %rdi
call free@PLT
.L13:
movq 56(%rsp), %rdi
call cudaStreamDestroy@PLT
movl $0, %r12d
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L27
movq %r12, %rax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaStreamDestroy@PLT
jmp .L11
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size create_mandelbrot, .-create_mandelbrot
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z10mandelbrotPfi4int26float4i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mandelbrotPfi4int26float4i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define ABS(X) X < 0 ? -X : X
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter);
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter);
/* We define a maximum number of iterations the kernel can do, so that
* it isn't rudely interrupted by the watchdog timer */
static const long max_iterations = 1L<<30;
static const int block_size = 128;
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter) {
float *region, *d_region;
dim3 threadsPerBlock(block_size);
dim3 blocks;
float4 boundary;
int size = res_x * res_y;
size_t host_bytes = (size_t) size * sizeof(float);
size_t job_bytes;
size_t jobsize;
cudaStream_t copy_stream; // Stream for copying between host and device
if(cudaStreamCreate(©_stream) != cudaSuccess)
return NULL;
region = (float*) malloc(host_bytes);
if(!region)
goto cleanup3;
/* Find some number of pixels that is a power of two, evenly divides up
* the work, and causes the kernel to compute at most max_iterations */
jobsize = block_size;
for(;!(size & (jobsize - 1)) && (jobsize * iter <= max_iterations); jobsize <<= 1);
jobsize >>= 1;
if(jobsize < block_size)
goto cleanup3;
fprintf(stderr, "%s: %d. %s: %d.\n", "Number of pixels", size,
"Number of pixels per job", jobsize);
blocks = dim3(jobsize / threadsPerBlock.x);
job_bytes = jobsize * sizeof(float);
boundary.x = min_x;
boundary.y = min_y;
boundary.z = max_x;
boundary.w = max_y;
if(cudaMalloc(&d_region, job_bytes) != cudaSuccess)
goto cleanup2;
for(int start = 0; start <= (size - jobsize); start += jobsize) {
mandelbrot<<<blocks, threadsPerBlock>>>(d_region, start, make_int2(res_x, res_y), boundary, iter);
if(cudaMemcpy(®ion[start], d_region, job_bytes, cudaMemcpyDeviceToHost) != cudaSuccess)
goto cleanup1;
}
cudaFree(d_region);
cudaStreamDestroy(copy_stream);
return region;
cleanup1:
cudaFree(d_region);
cleanup2:
free(region);
cleanup3:
cudaStreamDestroy(copy_stream);
return NULL;
}
/* Calculates the mandelbrot set and stores the results in region, which
* should be of length gridDim.x * blockDim.x * gridDim.y * blockDim.y
* The float4 boundary specifies the region of the complex plane to test
* for divergence, with the x, y, z, and w components representing the minimum
* x, minimum y, maximum x, and maximum y values of the rectangular region. */
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int pixel = index + offset;
int pixel_x = pixel % res.x;
int pixel_y = pixel / res.x;
double2 c, z;
int i;
c.x = ((boundary.z - boundary.x) * (((double) pixel_x) + 0.5))/(res.x) + boundary.x;
c.y = ((boundary.y - boundary.w) * (((double) pixel_y) + 0.5))/(res.y) + boundary.w;
z = c;
for(i=1;(i<iter) && (z.x*z.x+z.y*z.y <= 4);i++)
z = make_double2(z.x * z.x - z.y*z.y + c.x,
2*z.x*z.y + c.y);
region[index] = (i >= iter) ? (-1) : i + 2 - log2f(log2f(z.x*z.x+z.y*z.y));
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define ABS(X) X < 0 ? -X : X
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter);
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter);
/* We define a maximum number of iterations the kernel can do, so that
* it isn't rudely interrupted by the watchdog timer */
static const long max_iterations = 1L<<30;
static const int block_size = 128;
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter) {
float *region, *d_region;
dim3 threadsPerBlock(block_size);
dim3 blocks;
float4 boundary;
int size = res_x * res_y;
size_t host_bytes = (size_t) size * sizeof(float);
size_t job_bytes;
size_t jobsize;
hipStream_t copy_stream; // Stream for copying between host and device
if(hipStreamCreate(©_stream) != hipSuccess)
return NULL;
region = (float*) malloc(host_bytes);
if(!region)
goto cleanup3;
/* Find some number of pixels that is a power of two, evenly divides up
* the work, and causes the kernel to compute at most max_iterations */
jobsize = block_size;
for(;!(size & (jobsize - 1)) && (jobsize * iter <= max_iterations); jobsize <<= 1);
jobsize >>= 1;
if(jobsize < block_size)
goto cleanup3;
fprintf(stderr, "%s: %d. %s: %d.\n", "Number of pixels", size,
"Number of pixels per job", jobsize);
blocks = dim3(jobsize / threadsPerBlock.x);
job_bytes = jobsize * sizeof(float);
boundary.x = min_x;
boundary.y = min_y;
boundary.z = max_x;
boundary.w = max_y;
if(hipMalloc(&d_region, job_bytes) != hipSuccess)
goto cleanup2;
for(int start = 0; start <= (size - jobsize); start += jobsize) {
mandelbrot<<<blocks, threadsPerBlock>>>(d_region, start, make_int2(res_x, res_y), boundary, iter);
if(hipMemcpy(®ion[start], d_region, job_bytes, hipMemcpyDeviceToHost) != hipSuccess)
goto cleanup1;
}
hipFree(d_region);
hipStreamDestroy(copy_stream);
return region;
cleanup1:
hipFree(d_region);
cleanup2:
free(region);
cleanup3:
hipStreamDestroy(copy_stream);
return NULL;
}
/* Calculates the mandelbrot set and stores the results in region, which
* should be of length gridDim.x * blockDim.x * gridDim.y * blockDim.y
* The float4 boundary specifies the region of the complex plane to test
* for divergence, with the x, y, z, and w components representing the minimum
* x, minimum y, maximum x, and maximum y values of the rectangular region. */
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int pixel = index + offset;
int pixel_x = pixel % res.x;
int pixel_y = pixel / res.x;
double2 c, z;
int i;
c.x = ((boundary.z - boundary.x) * (((double) pixel_x) + 0.5))/(res.x) + boundary.x;
c.y = ((boundary.y - boundary.w) * (((double) pixel_y) + 0.5))/(res.y) + boundary.w;
z = c;
for(i=1;(i<iter) && (z.x*z.x+z.y*z.y <= 4);i++)
z = make_double2(z.x * z.x - z.y*z.y + c.x,
2*z.x*z.y + c.y);
region[index] = (i >= iter) ? (-1) : i + 2 - log2f(log2f(z.x*z.x+z.y*z.y));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define ABS(X) X < 0 ? -X : X
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter);
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter);
/* We define a maximum number of iterations the kernel can do, so that
* it isn't rudely interrupted by the watchdog timer */
static const long max_iterations = 1L<<30;
static const int block_size = 128;
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter) {
float *region, *d_region;
dim3 threadsPerBlock(block_size);
dim3 blocks;
float4 boundary;
int size = res_x * res_y;
size_t host_bytes = (size_t) size * sizeof(float);
size_t job_bytes;
size_t jobsize;
hipStream_t copy_stream; // Stream for copying between host and device
if(hipStreamCreate(©_stream) != hipSuccess)
return NULL;
region = (float*) malloc(host_bytes);
if(!region)
goto cleanup3;
/* Find some number of pixels that is a power of two, evenly divides up
* the work, and causes the kernel to compute at most max_iterations */
jobsize = block_size;
for(;!(size & (jobsize - 1)) && (jobsize * iter <= max_iterations); jobsize <<= 1);
jobsize >>= 1;
if(jobsize < block_size)
goto cleanup3;
fprintf(stderr, "%s: %d. %s: %d.\n", "Number of pixels", size,
"Number of pixels per job", jobsize);
blocks = dim3(jobsize / threadsPerBlock.x);
job_bytes = jobsize * sizeof(float);
boundary.x = min_x;
boundary.y = min_y;
boundary.z = max_x;
boundary.w = max_y;
if(hipMalloc(&d_region, job_bytes) != hipSuccess)
goto cleanup2;
for(int start = 0; start <= (size - jobsize); start += jobsize) {
mandelbrot<<<blocks, threadsPerBlock>>>(d_region, start, make_int2(res_x, res_y), boundary, iter);
if(hipMemcpy(®ion[start], d_region, job_bytes, hipMemcpyDeviceToHost) != hipSuccess)
goto cleanup1;
}
hipFree(d_region);
hipStreamDestroy(copy_stream);
return region;
cleanup1:
hipFree(d_region);
cleanup2:
free(region);
cleanup3:
hipStreamDestroy(copy_stream);
return NULL;
}
/* Calculates the mandelbrot set and stores the results in region, which
* should be of length gridDim.x * blockDim.x * gridDim.y * blockDim.y
* The float4 boundary specifies the region of the complex plane to test
* for divergence, with the x, y, z, and w components representing the minimum
* x, minimum y, maximum x, and maximum y values of the rectangular region. */
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int pixel = index + offset;
int pixel_x = pixel % res.x;
int pixel_y = pixel / res.x;
double2 c, z;
int i;
c.x = ((boundary.z - boundary.x) * (((double) pixel_x) + 0.5))/(res.x) + boundary.x;
c.y = ((boundary.y - boundary.w) * (((double) pixel_y) + 0.5))/(res.y) + boundary.w;
z = c;
for(i=1;(i<iter) && (z.x*z.x+z.y*z.y <= 4);i++)
z = make_double2(z.x * z.x - z.y*z.y + c.x,
2*z.x*z.y + c.y);
region[index] = (i >= iter) ? (-1) : i + 2 - log2f(log2f(z.x*z.x+z.y*z.y));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.globl _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.p2align 8
.type _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi,@function
_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s9, s[0:1], 0x30
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s9, 1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, -1.0
s_cselect_b32 s8, -1, 0
s_cmp_lt_i32 s9, 2
s_cbranch_scc1 .LBB0_15
s_clause 0x3
s_load_b32 s10, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b32 s13, s[0:1], 0x8
s_load_b32 s2, s[2:3], 0x4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s11, s10, 31
v_sub_f32_e64 v8, s5, s7
s_add_i32 s12, s10, s11
v_add_nc_u32_e32 v4, s13, v1
s_xor_b32 s12, s12, s11
v_cvt_f64_i32_e32 v[10:11], s10
v_cvt_f32_u32_e32 v0, s12
s_sub_i32 s3, 0, s12
v_ashrrev_i32_e32 v5, 31, v4
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v0, v0
v_add_nc_u32_e32 v3, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_xor_b32_e32 v6, v3, v5
v_xor_b32_e32 v5, s11, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v0
s_mov_b32 s3, -1
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mad_u64_u32 v[2:3], null, v6, v0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v3, s12
v_add_nc_u32_e32 v2, 1, v3
v_sub_nc_u32_e32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v6, s12, v0
v_cmp_le_u32_e32 vcc_lo, s12, v0
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
v_add_nc_u32_e32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s12, v0
v_cndmask_b32_e32 v0, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v5
v_sub_nc_u32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s10
v_sub_nc_u32_e32 v2, v4, v2
v_cvt_f64_i32_e32 v[4:5], v0
v_sub_f32_e64 v0, s6, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[2:3], v2
v_cvt_f64_f32_e32 v[6:7], v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], 0.5
v_add_f64 v[2:3], v[2:3], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[4:5], v[4:5], v[8:9]
v_mul_f64 v[2:3], v[2:3], v[6:7]
v_cvt_f64_i32_e32 v[6:7], s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[8:9], null, v[10:11], v[10:11], v[2:3]
v_div_scale_f64 v[12:13], null, v[6:7], v[6:7], v[4:5]
v_div_scale_f64 v[22:23], vcc_lo, v[2:3], v[10:11], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[8:9]
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[8:9], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[8:9], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, v[4:5], v[6:7], v[4:5]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], -v[8:9], v[20:21], v[22:23]
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, exec_lo
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[8:9], v[8:9], v[10:11], v[2:3]
v_cvt_f64_f32_e32 v[10:11], s4
v_div_fixup_f64 v[4:5], v[12:13], v[6:7], v[4:5]
v_cvt_f64_f32_e32 v[6:7], s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[2:3], v[4:5], v[6:7]
v_add_f64 v[4:5], v[8:9], v[10:11]
v_mov_b32_e32 v10, 0x40400000
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[2:3], v[2:3]
v_fma_f64 v[6:7], v[4:5], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_f64_e32 4.0, v[6:7]
s_cbranch_execz .LBB0_10
v_mul_f64 v[10:11], v[4:5], v[4:5]
v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
v_dual_mov_b32 v15, v5 :: v_dual_mov_b32 v14, v4
s_add_i32 s5, s9, -2
s_mov_b32 s4, 0
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_3:
v_add_f64 v[12:13], v[14:15], v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[10:11], -v[8:9]
s_and_not1_b32 s6, s6, exec_lo
s_add_i32 s7, s7, 1
s_mov_b32 s11, 0
v_fma_f64 v[6:7], v[6:7], v[12:13], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[4:5], v[8:9]
v_mul_f64 v[8:9], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
v_fma_f64 v[10:11], v[12:13], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_nge_f64_e32 vcc_lo, 4.0, v[10:11]
v_mul_f64 v[10:11], v[12:13], v[12:13]
s_and_b32 s10, vcc_lo, exec_lo
s_or_b32 s6, s6, s10
.LBB0_4:
s_xor_b32 s11, s11, -1
s_and_b32 s12, exec_lo, s6
v_mov_b32_e32 v0, s10
s_or_b32 s4, s12, s4
v_mov_b32_e32 v16, s7
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s10, s11, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s3, s10
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_7
.LBB0_5:
s_or_b32 s6, s6, exec_lo
s_cmp_lg_u32 s5, s7
s_cbranch_scc1 .LBB0_3
s_mov_b32 s10, -1.0
s_mov_b32 s11, -1
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v10, 0x40400000
s_mov_b32 s4, 0
s_and_saveexec_b32 s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s6
v_add_nc_u32_e32 v2, 3, v16
v_add_nc_u32_e32 v0, 1, v16
v_dual_mov_b32 v4, v12 :: v_dual_mov_b32 v5, v13
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_f32_i32_e32 v10, v2
v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
v_cmp_gt_i32_e32 vcc_lo, s9, v0
s_and_b32 s5, vcc_lo, exec_lo
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s3, s8, exec_lo
s_and_b32 s5, s5, exec_lo
s_or_b32 s8, s3, s5
s_or_not1_b32 s3, s4, exec_lo
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_14
v_mov_b32_e32 v0, -1.0
s_and_saveexec_b32 s3, s8
s_cbranch_execz .LBB0_13
v_mul_f64 v[2:3], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[4:5], v[4:5], v[2:3]
v_cvt_f32_f64_e32 v0, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
v_mul_f32_e32 v0, v0, v2
v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_log_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_sub_f32_e32 v0, v0, v2
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v0, v0, v2
v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
v_log_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_sub_f32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v0, v10, v0
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
.LBB0_15:
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, .Lfunc_end0-_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 16
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define ABS(X) X < 0 ? -X : X
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter);
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter);
/* We define a maximum number of iterations the kernel can do, so that
* it isn't rudely interrupted by the watchdog timer */
static const long max_iterations = 1L<<30;
static const int block_size = 128;
extern "C" float *create_mandelbrot(int res_x, int res_y, float min_x, float min_y,
float max_x, float max_y, int iter) {
float *region, *d_region;
dim3 threadsPerBlock(block_size);
dim3 blocks;
float4 boundary;
int size = res_x * res_y;
size_t host_bytes = (size_t) size * sizeof(float);
size_t job_bytes;
size_t jobsize;
hipStream_t copy_stream; // Stream for copying between host and device
if(hipStreamCreate(©_stream) != hipSuccess)
return NULL;
region = (float*) malloc(host_bytes);
if(!region)
goto cleanup3;
/* Find some number of pixels that is a power of two, evenly divides up
* the work, and causes the kernel to compute at most max_iterations */
jobsize = block_size;
for(;!(size & (jobsize - 1)) && (jobsize * iter <= max_iterations); jobsize <<= 1);
jobsize >>= 1;
if(jobsize < block_size)
goto cleanup3;
fprintf(stderr, "%s: %d. %s: %d.\n", "Number of pixels", size,
"Number of pixels per job", jobsize);
blocks = dim3(jobsize / threadsPerBlock.x);
job_bytes = jobsize * sizeof(float);
boundary.x = min_x;
boundary.y = min_y;
boundary.z = max_x;
boundary.w = max_y;
if(hipMalloc(&d_region, job_bytes) != hipSuccess)
goto cleanup2;
for(int start = 0; start <= (size - jobsize); start += jobsize) {
mandelbrot<<<blocks, threadsPerBlock>>>(d_region, start, make_int2(res_x, res_y), boundary, iter);
if(hipMemcpy(®ion[start], d_region, job_bytes, hipMemcpyDeviceToHost) != hipSuccess)
goto cleanup1;
}
hipFree(d_region);
hipStreamDestroy(copy_stream);
return region;
cleanup1:
hipFree(d_region);
cleanup2:
free(region);
cleanup3:
hipStreamDestroy(copy_stream);
return NULL;
}
/* Calculates the mandelbrot set and stores the results in region, which
* should be of length gridDim.x * blockDim.x * gridDim.y * blockDim.y
* The float4 boundary specifies the region of the complex plane to test
* for divergence, with the x, y, z, and w components representing the minimum
* x, minimum y, maximum x, and maximum y values of the rectangular region. */
__global__ void mandelbrot(float *region, int offset, int2 res, float4 boundary, int iter) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int pixel = index + offset;
int pixel_x = pixel % res.x;
int pixel_y = pixel / res.x;
double2 c, z;
int i;
c.x = ((boundary.z - boundary.x) * (((double) pixel_x) + 0.5))/(res.x) + boundary.x;
c.y = ((boundary.y - boundary.w) * (((double) pixel_y) + 0.5))/(res.y) + boundary.w;
z = c;
for(i=1;(i<iter) && (z.x*z.x+z.y*z.y <= 4);i++)
z = make_double2(z.x * z.x - z.y*z.y + c.x,
2*z.x*z.y + c.y);
region[index] = (i >= iter) ? (-1) : i + 2 - log2f(log2f(z.x*z.x+z.y*z.y));
} | .text
.file "mandelbrot.hip"
.globl create_mandelbrot # -- Begin function create_mandelbrot
.p2align 4, 0x90
.type create_mandelbrot,@function
create_mandelbrot: # @create_mandelbrot
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movss %xmm3, 32(%rsp) # 4-byte Spill
movss %xmm2, 24(%rsp) # 4-byte Spill
movd %xmm1, 64(%rsp) # 4-byte Folded Spill
movss %xmm0, 16(%rsp) # 4-byte Spill
movl %esi, %ebp
movl %edi, %r12d
leaq 104(%rsp), %rdi
callq hipStreamCreate
testl %eax, %eax
je .LBB0_2
# %bb.1:
xorl %eax, %eax
jmp .LBB0_23
.LBB0_2:
movl %ebp, %r13d
imull %r12d, %r13d
movslq %r13d, %r15
leaq (,%r15,4), %rdi
callq malloc
testq %rax, %rax
je .LBB0_21
# %bb.3: # %.preheader70
movl $128, %r14d
testb $127, %r15b
jne .LBB0_7
# %bb.4: # %.lr.ph.preheader
movslq %ebx, %rcx
.p2align 4, 0x90
.LBB0_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdx
imulq %rcx, %rdx
cmpq $1073741824, %rdx # imm = 0x40000000
ja .LBB0_7
# %bb.6: # in Loop: Header=BB0_5 Depth=1
leaq -1(,%r14,2), %rdx
addq %r14, %r14
testq %r15, %rdx
je .LBB0_5
.LBB0_7: # %.critedge
cmpq $256, %r14 # imm = 0x100
jae .LBB0_8
.LBB0_21: # %.sink.split
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.LBB0_22: # %.sink.split
movq 104(%rsp), %rdi
callq hipStreamDestroy
movq (%rsp), %rax # 8-byte Reload
.LBB0_23:
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 288
movq %rax, (%rsp) # 8-byte Spill
movq %r14, %r9
shrq %r9
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movl %r13d, %ecx
movq %r9, 88(%rsp) # 8-byte Spill
xorl %eax, %eax
callq fprintf
leaq (%r14,%r14), %r13
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 48(%rsp)
movss 64(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 52(%rsp)
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 56(%rsp)
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 60(%rsp)
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB0_9
.LBB0_20:
movq (%rsp), %rdi # 8-byte Reload
callq free
jmp .LBB0_21
.LBB0_9: # %.preheader
movq %r13, 32(%rsp) # 8-byte Spill
xorl %r13d, %r13d
movabsq $4294967296, %rax # imm = 0x100000000
shrq $8, %r14
movl %r14d, %ecx
orq %rax, %rcx
movq %rcx, 24(%rsp) # 8-byte Spill
movq 88(%rsp), %rcx # 8-byte Reload
subq %rcx, %r15
movd %ebp, %xmm0
movd %r12d, %xmm1
punpckldq %xmm0, %xmm1 # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
movdqa %xmm1, 64(%rsp) # 16-byte Spill
movsd 48(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd 56(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 96(%rsp) # 8-byte Spill
subq $-128, %rax
movq %rax, %r12
xorl %r14d, %r14d
movq %rcx, %rbp
.LBB0_10: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_12
# %bb.11: # in Loop: Header=BB0_10 Depth=1
movq 8(%rsp), %rax
movaps 64(%rsp), %xmm0 # 16-byte Reload
movlps %xmm0, 168(%rsp)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 176(%rsp)
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 184(%rsp)
movq %rax, 160(%rsp)
movl %r13d, 44(%rsp)
movl %ebx, 40(%rsp)
leaq 160(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 176(%rsp), %rax
movq %rax, 216(%rsp)
leaq 40(%rsp), %rax
movq %rax, 224(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, %edi
leaq 192(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_12: # in Loop: Header=BB0_10 Depth=1
movq (%rsp), %rax # 8-byte Reload
leaq (%rax,%r14,4), %rdi
movq 8(%rsp), %rsi
movq 32(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_15
# %bb.13: # in Loop: Header=BB0_10 Depth=1
movq %r13, %rax
addl %ebp, %eax
movq %rax, %r13
movslq %eax, %r14
cmpq %r14, %r15
jae .LBB0_10
# %bb.14:
movl $7, %ecx
jmp .LBB0_16
.LBB0_15:
movl $10, %ecx
.LBB0_16:
cmpl $10, %ecx
movq (%rsp), %rax # 8-byte Reload
je .LBB0_19
# %bb.17:
cmpl $7, %ecx
jne .LBB0_23
# %bb.18:
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB0_22
.LBB0_19:
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB0_20
.Lfunc_end0:
.size create_mandelbrot, .Lfunc_end0-create_mandelbrot
.cfi_endproc
# -- End function
.globl _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi # -- Begin function _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.p2align 4, 0x90
.type _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi,@function
_Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi: # @_Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdx, 72(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 88(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, .Lfunc_end1-_Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s: %d. %s: %d.\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of pixels"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of pixels per job"
.size .L.str.2, 25
.type _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi,@object # @_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.section .rodata,"a",@progbits
.globl _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.p2align 3, 0x0
_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi:
.quad _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.size _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010c7d4_00000000-6_mandelbrot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i
.type _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i, @function
_Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10mandelbrotPfi4int26float4i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i, .-_Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i
.globl _Z10mandelbrotPfi4int26float4i
.type _Z10mandelbrotPfi4int26float4i, @function
_Z10mandelbrotPfi4int26float4i:
.LFB2083:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdx, 24(%rsp)
movq %xmm0, (%rsp)
movq %xmm1, 8(%rsp)
movl %ecx, %r8d
movq %rsp, %rcx
leaq 24(%rsp), %rdx
call _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10mandelbrotPfi4int26float4i, .-_Z10mandelbrotPfi4int26float4i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Number of pixels per job"
.LC1:
.string "Number of pixels"
.LC2:
.string "%s: %d. %s: %d.\n"
.text
.globl create_mandelbrot
.type create_mandelbrot, @function
create_mandelbrot:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %ebx
movl %edi, 12(%rsp)
movl %esi, %r15d
movl %esi, 16(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 32(%rsp)
movl %edx, %r14d
movl %edx, 36(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leaq 56(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %r12d
testl %eax, %eax
jne .L11
imull %r15d, %ebx
movslq %ebx, %rbp
leaq 0(,%rbp,4), %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L13
movl %ebx, %r13d
andl $127, %r13d
jne .L13
movslq %r14d, %rsi
movq %rsi, %rax
salq $7, %rax
cmpq $1073741824, %rax
ja .L13
movl $128, %eax
.L15:
movq %rax, %rcx
addq %rax, %rax
leaq -1(%rax), %rdx
testq %rbp, %rdx
jne .L14
movq %rax, %rdx
imulq %rsi, %rdx
cmpq $1073741824, %rdx
jbe .L15
.L14:
movq %rcx, %r14
btrq $63, %r14
movabsq $9223372036854775680, %rax
testq %rax, %rcx
je .L13
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq %r14
.cfi_def_cfa_offset 208
leaq .LC0(%rip), %r9
movl %ebx, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rax
shrq $7, %rax
movl %eax, 100(%rsp)
leaq 0(,%r14,4), %r15
addq $16, %rsp
.cfi_def_cfa_offset 192
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L16
subq %r14, %rbp
movl $0, %ebx
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
jmp .L19
.L17:
leaq (%r12,%rbx,4), %rdi
movl $2, %ecx
movq %r15, %rdx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L25
leal 0(%r13,%r14), %ebx
movl %ebx, %r13d
movslq %ebx, %rbx
cmpq %rbx, %rbp
jb .L26
.L19:
movl $128, 72(%rsp)
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movl 12(%rsp), %eax
movl %eax, 64(%rsp)
movl 16(%rsp), %eax
movl %eax, 68(%rsp)
movss 20(%rsp), %xmm4
movss %xmm4, 96(%rsp)
movss 24(%rsp), %xmm5
movss %xmm5, 100(%rsp)
movss 28(%rsp), %xmm6
movss %xmm6, 104(%rsp)
movss 32(%rsp), %xmm7
movss %xmm7, 108(%rsp)
leaq 64(%rsp), %rdx
movl 36(%rsp), %r8d
movq 40(%rsp), %rcx
movl %r13d, %esi
movq 48(%rsp), %rdi
call _Z44__device_stub__Z10mandelbrotPfi4int26float4iPfiR4int2R6float4i
jmp .L17
.L25:
movq 48(%rsp), %rdi
call cudaFree@PLT
.L16:
movq %r12, %rdi
call free@PLT
.L13:
movq 56(%rsp), %rdi
call cudaStreamDestroy@PLT
movl $0, %r12d
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L27
movq %r12, %rax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaStreamDestroy@PLT
jmp .L11
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size create_mandelbrot, .-create_mandelbrot
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z10mandelbrotPfi4int26float4i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mandelbrotPfi4int26float4i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mandelbrot.hip"
.globl create_mandelbrot # -- Begin function create_mandelbrot
.p2align 4, 0x90
.type create_mandelbrot,@function
create_mandelbrot: # @create_mandelbrot
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movss %xmm3, 32(%rsp) # 4-byte Spill
movss %xmm2, 24(%rsp) # 4-byte Spill
movd %xmm1, 64(%rsp) # 4-byte Folded Spill
movss %xmm0, 16(%rsp) # 4-byte Spill
movl %esi, %ebp
movl %edi, %r12d
leaq 104(%rsp), %rdi
callq hipStreamCreate
testl %eax, %eax
je .LBB0_2
# %bb.1:
xorl %eax, %eax
jmp .LBB0_23
.LBB0_2:
movl %ebp, %r13d
imull %r12d, %r13d
movslq %r13d, %r15
leaq (,%r15,4), %rdi
callq malloc
testq %rax, %rax
je .LBB0_21
# %bb.3: # %.preheader70
movl $128, %r14d
testb $127, %r15b
jne .LBB0_7
# %bb.4: # %.lr.ph.preheader
movslq %ebx, %rcx
.p2align 4, 0x90
.LBB0_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdx
imulq %rcx, %rdx
cmpq $1073741824, %rdx # imm = 0x40000000
ja .LBB0_7
# %bb.6: # in Loop: Header=BB0_5 Depth=1
leaq -1(,%r14,2), %rdx
addq %r14, %r14
testq %r15, %rdx
je .LBB0_5
.LBB0_7: # %.critedge
cmpq $256, %r14 # imm = 0x100
jae .LBB0_8
.LBB0_21: # %.sink.split
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.LBB0_22: # %.sink.split
movq 104(%rsp), %rdi
callq hipStreamDestroy
movq (%rsp), %rax # 8-byte Reload
.LBB0_23:
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 288
movq %rax, (%rsp) # 8-byte Spill
movq %r14, %r9
shrq %r9
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movl %r13d, %ecx
movq %r9, 88(%rsp) # 8-byte Spill
xorl %eax, %eax
callq fprintf
leaq (%r14,%r14), %r13
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 48(%rsp)
movss 64(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 52(%rsp)
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 56(%rsp)
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 60(%rsp)
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB0_9
.LBB0_20:
movq (%rsp), %rdi # 8-byte Reload
callq free
jmp .LBB0_21
.LBB0_9: # %.preheader
movq %r13, 32(%rsp) # 8-byte Spill
xorl %r13d, %r13d
movabsq $4294967296, %rax # imm = 0x100000000
shrq $8, %r14
movl %r14d, %ecx
orq %rax, %rcx
movq %rcx, 24(%rsp) # 8-byte Spill
movq 88(%rsp), %rcx # 8-byte Reload
subq %rcx, %r15
movd %ebp, %xmm0
movd %r12d, %xmm1
punpckldq %xmm0, %xmm1 # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
movdqa %xmm1, 64(%rsp) # 16-byte Spill
movsd 48(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd 56(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 96(%rsp) # 8-byte Spill
subq $-128, %rax
movq %rax, %r12
xorl %r14d, %r14d
movq %rcx, %rbp
.LBB0_10: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_12
# %bb.11: # in Loop: Header=BB0_10 Depth=1
movq 8(%rsp), %rax
movaps 64(%rsp), %xmm0 # 16-byte Reload
movlps %xmm0, 168(%rsp)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 176(%rsp)
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 184(%rsp)
movq %rax, 160(%rsp)
movl %r13d, 44(%rsp)
movl %ebx, 40(%rsp)
leaq 160(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 176(%rsp), %rax
movq %rax, 216(%rsp)
leaq 40(%rsp), %rax
movq %rax, 224(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, %edi
leaq 192(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_12: # in Loop: Header=BB0_10 Depth=1
movq (%rsp), %rax # 8-byte Reload
leaq (%rax,%r14,4), %rdi
movq 8(%rsp), %rsi
movq 32(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_15
# %bb.13: # in Loop: Header=BB0_10 Depth=1
movq %r13, %rax
addl %ebp, %eax
movq %rax, %r13
movslq %eax, %r14
cmpq %r14, %r15
jae .LBB0_10
# %bb.14:
movl $7, %ecx
jmp .LBB0_16
.LBB0_15:
movl $10, %ecx
.LBB0_16:
cmpl $10, %ecx
movq (%rsp), %rax # 8-byte Reload
je .LBB0_19
# %bb.17:
cmpl $7, %ecx
jne .LBB0_23
# %bb.18:
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB0_22
.LBB0_19:
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB0_20
.Lfunc_end0:
.size create_mandelbrot, .Lfunc_end0-create_mandelbrot
.cfi_endproc
# -- End function
.globl _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi # -- Begin function _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.p2align 4, 0x90
.type _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi,@function
_Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi: # @_Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdx, 72(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 88(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, .Lfunc_end1-_Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s: %d. %s: %d.\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of pixels"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of pixels per job"
.size .L.str.2, 25
.type _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi,@object # @_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.section .rodata,"a",@progbits
.globl _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.p2align 3, 0x0
_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi:
.quad _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.size _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mandelbrotPfi15HIP_vector_typeIiLj2EES0_IfLj4EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
============================================================================
Name : Esercizio2.cu Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <stdio.h>
#include <cuda_runtime.h>
/*
* Mostra DIMs e IDs di grid, block e thread
*/
__global__ void checkIndex(void) {
if ((threadIdx.x + threadIdx.y) % 5 == 0) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
}
int main(int argc, char **argv) {
// definisce grid e struttura dei blocchi
dim3 block(8, 7, 1);
dim3 grid(2, 2, 1);
// controlla dim. dal lato host
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d block.y %d block.z %d\n", block.x, block.y, block.z);
// controlla dim. dal lato device
checkIndex<<<grid, block>>>();
// reset device
cudaDeviceReset();
return(0);
} | code for sm_80
Function : _Z10checkIndexv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0050*/ IMAD.IADD R0, R9, 0x1, R8 ; /* 0x0000000109007824 */
/* 0x001fc800078e0208 */
/*0060*/ IMAD.WIDE.U32 R2, R0, -0x33333333, RZ ; /* 0xcccccccd00027825 */
/* 0x000fca00078e00ff */
/*0070*/ SHF.R.U32.HI R3, RZ, 0x2, R3 ; /* 0x00000002ff037819 */
/* 0x000fca0000011603 */
/*0080*/ IMAD R0, R3, -0x5, R0 ; /* 0xfffffffb03007824 */
/* 0x000fca00078e0200 */
/*0090*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe200078e00ff */
/*00d0*/ MOV R17, c[0x0][0xc] ; /* 0x0000030000117a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fe200078e00ff */
/*00f0*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000e220000002300 */
/*0100*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff107624 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x10] ; /* 0x00000400ff127624 */
/* 0x000fe200078e00ff */
/*0130*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */
/* 0x000e620000002700 */
/*0140*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff137624 */
/* 0x000fe200078e00ff */
/*0150*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0004e20000000a00 */
/*0160*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*0170*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000e620000002600 */
/*0180*/ MOV R4, c[0x4][0x8] ; /* 0x0100020000047a02 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc400078e00ff */
/*01a0*/ STL.128 [R1+0x20], R16 ; /* 0x0000201001007387 */
/* 0x0005e80000100c00 */
/*01b0*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0015e80000100c00 */
/*01c0*/ STL.128 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0025e40000100c00 */
/*01d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x00cfe40000000000 */
/*01e0*/ MOV R11, 0x250 ; /* 0x00000250000b7802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R20, 0x1d0 ; /* 0x000001d000147802 */
/* 0x000fc40000000f00 */
/*0200*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0220*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0230*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0240*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
============================================================================
Name : Esercizio2.cu Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <stdio.h>
#include <cuda_runtime.h>
/*
* Mostra DIMs e IDs di grid, block e thread
*/
__global__ void checkIndex(void) {
if ((threadIdx.x + threadIdx.y) % 5 == 0) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
}
int main(int argc, char **argv) {
// definisce grid e struttura dei blocchi
dim3 block(8, 7, 1);
dim3 grid(2, 2, 1);
// controlla dim. dal lato host
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d block.y %d block.z %d\n", block.x, block.y, block.z);
// controlla dim. dal lato device
checkIndex<<<grid, block>>>();
// reset device
cudaDeviceReset();
return(0);
} | .file "tmpxft_00154783_00000000-6_exercise2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "grid.x %d grid.y %d grid.z %d\n"
.align 8
.LC1:
.string "block.x %d block.y %d block.z %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, %r8d
movl $2, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $7, %ecx
movl $8, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $8, 8(%rsp)
movl $7, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10checkIndexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
============================================================================
Name : Esercizio2.cu Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <stdio.h>
#include <cuda_runtime.h>
/*
* Mostra DIMs e IDs di grid, block e thread
*/
__global__ void checkIndex(void) {
if ((threadIdx.x + threadIdx.y) % 5 == 0) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
}
int main(int argc, char **argv) {
// definisce grid e struttura dei blocchi
dim3 block(8, 7, 1);
dim3 grid(2, 2, 1);
// controlla dim. dal lato host
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d block.y %d block.z %d\n", block.x, block.y, block.z);
// controlla dim. dal lato device
checkIndex<<<grid, block>>>();
// reset device
cudaDeviceReset();
return(0);
} | /*
============================================================================
Name : Esercizio2.cu Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
/*
* Mostra DIMs e IDs di grid, block e thread
*/
__global__ void checkIndex(void) {
if ((threadIdx.x + threadIdx.y) % 5 == 0) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
}
int main(int argc, char **argv) {
// definisce grid e struttura dei blocchi
dim3 block(8, 7, 1);
dim3 grid(2, 2, 1);
// controlla dim. dal lato host
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d block.y %d block.z %d\n", block.x, block.y, block.z);
// controlla dim. dal lato device
checkIndex<<<grid, block>>>();
// reset device
hipDeviceReset();
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
============================================================================
Name : Esercizio2.cu Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
/*
* Mostra DIMs e IDs di grid, block e thread
*/
__global__ void checkIndex(void) {
if ((threadIdx.x + threadIdx.y) % 5 == 0) {
printf("threadIdx:(%d, %d, %d) blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
}
int main(int argc, char **argv) {
// definisce grid e struttura dei blocchi
dim3 block(8, 7, 1);
dim3 grid(2, 2, 1);
// controlla dim. dal lato host
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d block.y %d block.z %d\n", block.x, block.y, block.z);
// controlla dim. dal lato device
checkIndex<<<grid, block>>>();
// reset device
hipDeviceReset();
return(0);
} | .text
.file "exercise2.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str, %edi
movl $2, %esi
movl $2, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $8, %esi
movl $7, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $30064771080, %rdx # imm = 0x700000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid.x %d grid.y %d grid.z %d\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "block.x %d block.y %d block.z %d\n"
.size .L.str.1, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00154783_00000000-6_exercise2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "grid.x %d grid.y %d grid.z %d\n"
.align 8
.LC1:
.string "block.x %d block.y %d block.z %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, %r8d
movl $2, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $7, %ecx
movl $8, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $8, 8(%rsp)
movl $7, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10checkIndexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise2.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str, %edi
movl $2, %esi
movl $2, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $8, %esi
movl $7, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $30064771080, %rdx # imm = 0x700000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid.x %d grid.y %d grid.z %d\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "block.x %d block.y %d block.z %d\n"
.size .L.str.1, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x270f, PT ; /* 0x0000270f0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x2710, PT ; /* 0x000027100000780c */
/* 0x000fe40003f06270 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
} | .file "tmpxft_0003da02_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2710, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x270f, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x270f, PT ; /* 0x0000270f0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x2710, PT ; /* 0x000027100000780c */
/* 0x000fe40003f06270 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2710, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x270f, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003da02_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // heavy assistance provided from nVidia's CUDA documentation and `vectorAdd.cu` piece of sample code
#include <stdio.h>
#include <sys/time.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
int* generate_array(int); // prototypes at the top of a non-header, because I hate C.
char* run_insertion_sort(int); // wraps the cuda_insertion_sort function
// this is quite possibly the stupidest piece of code I've written
// this is a single CUDA block for doing insertion sort
// insertion sort is not a parallelizable algorithm.
__global__ void cuda_insertion_sort(int *array, int num_elements) {
int temp;
for (int i = 1; i < num_elements; i++) {
for(int j = i ; j > 0 ; j--){
if(array[j] < array[j-1]){
temp = array[j];
array[j] = array[j-1];
array[j-1] = temp;
}
}
}
}
int main(void) {
FILE *f;
f = fopen("cuda_insertion.txt", "w");
for(int i = 1000; i < 11000; i+= 1000) {
printf("%d ", i);
fprintf(f, "%d ", i);
char* return_time = run_insertion_sort(i);
fprintf(f, "%s ", return_time);
printf("%s ", return_time);
fflush(stdout);
free(return_time);
printf("\n");
fprintf(f, "\n");
}
cudaError_t err = cudaDeviceReset();
if (err != cudaSuccess) {
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
fflush(f);
fclose(f);
printf("Done\n");
return 0;
}
char* run_insertion_sort(int num_elements) {
// initialize host's elements
cudaError_t err = cudaSuccess;
int* host_array = generate_array(num_elements);
// initialize CUDA device's element
int* cuda_array = NULL;
size_t size = num_elements * sizeof(int);
err = cudaMalloc((void **)&cuda_array, size);
if (err != cudaSuccess) { // check for errors on memory allocation
fprintf(stderr, "Failed to allocate memory for array (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
struct timeval tval_before, tval_after, tval_result; // declare some timing info
gettimeofday(&tval_before, NULL);
// copy the host element onto the CUDA device's element
err = cudaMemcpy(cuda_array, host_array, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess) { // check for errors on memory copy over to device
fprintf(stderr, "Failed to copy array from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cuda_insertion_sort<<<1,1>>>(cuda_array, num_elements); // execute the kernel
err = cudaGetLastError(); // check for any errors during kernel execution
if (err != cudaSuccess) {
fprintf(stderr, "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// copy the result back from the CUDA device
err = cudaMemcpy(host_array, cuda_array, size, cudaMemcpyDeviceToHost); // this is a synchronous function.
gettimeofday(&tval_after, NULL);
timersub(&tval_after, &tval_before, &tval_result); // finish up the timing
if (err != cudaSuccess) { // check for any errors on memory copy back to host
fprintf(stderr, "Failed to copy array from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// and clean up
err = cudaFree(cuda_array);
if (err != cudaSuccess) { // check for any errors on freeing the memory
fprintf(stderr, "Failed to free device array (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
free(host_array);
// return info on the time spent
char* return_string = (char*)malloc(100 * sizeof(char));
sprintf(return_string, "%ld%03ld", (long int)tval_result.tv_sec, (long int)tval_result.tv_usec / 1000);
return return_string;
}
int* generate_array(int array_length) {
int *return_var = (int*)malloc(sizeof(int) * array_length);
for (int i = array_length - 1; i >= 0; i--) {
return_var[array_length - i - 1] = i;
}
return return_var;
} | code for sm_80
Function : _Z19cuda_insertion_sortPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0060*/ UIADD3 UR4, UP0, UR4, -0x4, URZ ; /* 0xfffffffc04047890 */
/* 0x000fe2000ff1e03f */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ UIADD3.X UR5, UR5, -0x1, URZ, UP0, !UPT ; /* 0xffffffff05057890 */
/* 0x000fe400087fe43f */
/*00a0*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x002fc600078e0000 */
/*00c0*/ LOP3.LUT P0, R8, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304087812 */
/* 0x000fda000780c0ff */
/*00d0*/ @!P0 BRA 0x260 ; /* 0x0000018000008947 */
/* 0x005fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0100*/ LDG.E R7, [R2.64+-0x4] ; /* 0xfffffc0602077981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea2000c1e1900 */
/*0120*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe40003f25270 */
/*0130*/ IADD3 R9, R0, -0x1, RZ ; /* 0xffffffff00097810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x004fda0003f06270 */
/*0150*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e8000c101906 */
/*0160*/ @!P0 STG.E [R2.64+-0x4], R6 ; /* 0xfffffc0602008986 */
/* 0x0003e2000c101906 */
/*0170*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff078224 */
/* 0x001fe200078e0006 */
/*0180*/ @!P1 BRA 0x260 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R11, [R2.64+-0x8] ; /* 0xfffff806020b7981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ ISETP.NE.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe40003f25270 */
/*01b0*/ IADD3 R9, R0, -0x2, RZ ; /* 0xfffffffe00097810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.AND P0, PT, R7, R11, PT ; /* 0x0000000b0700720c */
/* 0x004fda0003f06270 */
/*01d0*/ @!P0 STG.E [R2.64+-0x4], R11 ; /* 0xfffffc0b02008986 */
/* 0x0001e8000c101906 */
/*01e0*/ @!P0 STG.E [R2.64+-0x8], R7 ; /* 0xfffff80702008986 */
/* 0x0005e2000c101906 */
/*01f0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b8224 */
/* 0x001fe200078e0007 */
/*0200*/ @!P1 BRA 0x260 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R6, [R2.64+-0xc] ; /* 0xfffff40602067981 */
/* 0x002ee2000c1e1900 */
/*0220*/ IADD3 R9, R0, -0x3, RZ ; /* 0xfffffffd00097810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.GE.AND P0, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x008fda0003f06270 */
/*0240*/ @!P0 STG.E [R2.64+-0x8], R6 ; /* 0xfffff80602008986 */
/* 0x0001e8000c101906 */
/*0250*/ @!P0 STG.E [R2.64+-0xc], R11 ; /* 0xfffff40b02008986 */
/* 0x0001e4000c101906 */
/*0260*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fda0003f06070 */
/*0270*/ @!P0 BRA 0xd00 ; /* 0x00000a8000008947 */
/* 0x000fea0003800000 */
/*0280*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe20003f24270 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x003fc800078e00ff */
/*02a0*/ IMAD.WIDE R6, R9, R6, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x004fc800078e0206 */
/*02b0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*02c0*/ LDG.E R5, [R6.64] ; /* 0x0000000606057981 */
/* 0x000162000c1e1900 */
/*02d0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*02e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*02f0*/ IADD3 R8, R9.reuse, 0x4, RZ ; /* 0x0000000409087810 */
/* 0x040fe20007ffe0ff */
/*0300*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x000fe200078e0202 */
/*0310*/ @!P1 BRA 0x8a0 ; /* 0x0000058000009947 */
/* 0x000fea0003800000 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0330*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x001ea8000c1e1900 */
/*0340*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0602097981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R11, [R2.64+-0x8] ; /* 0xfffff806020b7981 */
/* 0x000f28000c1e1900 */
/*0360*/ LDG.E R13, [R2.64+-0xc] ; /* 0xfffff406020d7981 */
/* 0x000ee8000c1e1900 */
/*0370*/ LDG.E R15, [R2.64+-0x10] ; /* 0xfffff006020f7981 */
/* 0x000ee8000c1e1900 */
/*0380*/ LDG.E R17, [R2.64+-0x14] ; /* 0xffffec0602117981 */
/* 0x000ee8000c1e1900 */
/*0390*/ LDG.E R19, [R2.64+-0x18] ; /* 0xffffe80602137981 */
/* 0x000ee8000c1e1900 */
/*03a0*/ LDG.E R21, [R2.64+-0x1c] ; /* 0xffffe40602157981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R23, [R2.64+-0x20] ; /* 0xffffe00602177981 */
/* 0x000f28000c1e1900 */
/*03c0*/ LDG.E R25, [R2.64+-0x24] ; /* 0xffffdc0602197981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R27, [R2.64+-0x28] ; /* 0xffffd806021b7981 */
/* 0x000f28000c1e1900 */
/*03e0*/ LDG.E R29, [R2.64+-0x2c] ; /* 0xffffd406021d7981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R6, [R2.64+-0x30] ; /* 0xffffd00602067981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R10, [R2.64+-0x34] ; /* 0xffffcc06020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R12, [R2.64+-0x38] ; /* 0xffffc806020c7981 */
/* 0x000f22000c1e1900 */
/*0420*/ ISETP.GE.AND P1, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x024fda0003f26270 */
/*0430*/ @!P1 STG.E [R2.64+0x4], R7 ; /* 0x0000040702009986 */
/* 0x0001e8000c101906 */
/*0440*/ @!P1 STG.E [R2.64], R5 ; /* 0x0000000502009986 */
/* 0x0003e2000c101906 */
/*0450*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff079224 */
/* 0x001fc600078e0005 */
/*0460*/ LDG.E R5, [R2.64+-0x3c] ; /* 0xffffc40602057981 */
/* 0x002ea4000c1e1900 */
/*0470*/ ISETP.GE.AND P1, PT, R7, R9, PT ; /* 0x000000090700720c */
/* 0x008fe40003f26270 */
/*0480*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fd60007ffe0ff */
/*0490*/ @!P1 STG.E [R2.64], R9 ; /* 0x0000000902009986 */
/* 0x0001e8000c101906 */
/*04a0*/ @!P1 STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702009986 */
/* 0x0003e2000c101906 */
/*04b0*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff099224 */
/* 0x001fe200078e0007 */
/*04c0*/ IADD3 R7, P3, R2, -0x40, RZ ; /* 0xffffffc002077810 */
/* 0x002fc80007f7e0ff */
/*04d0*/ ISETP.GE.AND P2, PT, R9, R11, PT ; /* 0x0000000b0900720c */
/* 0x010fe40003f46270 */
/*04e0*/ IADD3.X R14, R3, -0x1, RZ, P3, !PT ; /* 0xffffffff030e7810 */
/* 0x000fd60001ffe4ff */
/*04f0*/ @!P2 STG.E [R2.64+-0x4], R11 ; /* 0xfffffc0b0200a986 */
/* 0x0001e8000c101906 */
/*0500*/ @!P2 STG.E [R2.64+-0x8], R9 ; /* 0xfffff8090200a986 */
/* 0x000fe2000c101906 */
/*0510*/ @!P2 IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0ba224 */
/* 0x001fca00078e0009 */
/*0520*/ ISETP.GE.AND P1, PT, R11, R13, PT ; /* 0x0000000d0b00720c */
/* 0x000fda0003f26270 */
/*0530*/ @!P1 STG.E [R2.64+-0x8], R13 ; /* 0xfffff80d02009986 */
/* 0x0001e8000c101906 */
/*0540*/ @!P1 STG.E [R2.64+-0xc], R11 ; /* 0xfffff40b02009986 */
/* 0x000fe2000c101906 */
/*0550*/ @!P1 IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d9224 */
/* 0x001fca00078e000b */
/*0560*/ ISETP.GE.AND P2, PT, R13, R15, PT ; /* 0x0000000f0d00720c */
/* 0x000fda0003f46270 */
/*0570*/ @!P2 STG.E [R2.64+-0xc], R15 ; /* 0xfffff40f0200a986 */
/* 0x0001e8000c101906 */
/*0580*/ @!P2 STG.E [R2.64+-0x10], R13 ; /* 0xfffff00d0200a986 */
/* 0x000fe2000c101906 */
/*0590*/ @!P2 IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0fa224 */
/* 0x001fca00078e000d */
/*05a0*/ ISETP.GE.AND P1, PT, R15, R17, PT ; /* 0x000000110f00720c */
/* 0x000fda0003f26270 */
/*05b0*/ @!P1 STG.E [R2.64+-0x10], R17 ; /* 0xfffff01102009986 */
/* 0x0001e8000c101906 */
/*05c0*/ @!P1 STG.E [R2.64+-0x14], R15 ; /* 0xffffec0f02009986 */
/* 0x000fe2000c101906 */
/*05d0*/ @!P1 IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff119224 */
/* 0x001fca00078e000f */
/*05e0*/ ISETP.GE.AND P2, PT, R17, R19, PT ; /* 0x000000131100720c */
/* 0x000fda0003f46270 */
/*05f0*/ @!P2 STG.E [R2.64+-0x14], R19 ; /* 0xffffec130200a986 */
/* 0x0001e8000c101906 */
/*0600*/ @!P2 STG.E [R2.64+-0x18], R17 ; /* 0xffffe8110200a986 */
/* 0x000fe2000c101906 */
/*0610*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, R17 ; /* 0x000000ffff13a224 */
/* 0x001fca00078e0011 */
/*0620*/ ISETP.GE.AND P1, PT, R19, R21, PT ; /* 0x000000151300720c */
/* 0x000fda0003f26270 */
/*0630*/ @!P1 STG.E [R2.64+-0x18], R21 ; /* 0xffffe81502009986 */
/* 0x0001e8000c101906 */
/*0640*/ @!P1 STG.E [R2.64+-0x1c], R19 ; /* 0xffffe41302009986 */
/* 0x000fe2000c101906 */
/*0650*/ @!P1 IMAD.MOV.U32 R21, RZ, RZ, R19 ; /* 0x000000ffff159224 */
/* 0x001fca00078e0013 */
/*0660*/ ISETP.GE.AND P2, PT, R21, R23, PT ; /* 0x000000171500720c */
/* 0x000fda0003f46270 */
/*0670*/ @!P2 STG.E [R2.64+-0x1c], R23 ; /* 0xffffe4170200a986 */
/* 0x0001e8000c101906 */
/*0680*/ @!P2 STG.E [R2.64+-0x20], R21 ; /* 0xffffe0150200a986 */
/* 0x000fe2000c101906 */
/*0690*/ @!P2 IMAD.MOV.U32 R23, RZ, RZ, R21 ; /* 0x000000ffff17a224 */
/* 0x001fca00078e0015 */
/*06a0*/ ISETP.GE.AND P1, PT, R23, R25, PT ; /* 0x000000191700720c */
/* 0x000fda0003f26270 */
/*06b0*/ @!P1 STG.E [R2.64+-0x20], R25 ; /* 0xffffe01902009986 */
/* 0x0001e8000c101906 */
/*06c0*/ @!P1 STG.E [R2.64+-0x24], R23 ; /* 0xffffdc1702009986 */
/* 0x000fe2000c101906 */
/*06d0*/ @!P1 IMAD.MOV.U32 R25, RZ, RZ, R23 ; /* 0x000000ffff199224 */
/* 0x001fca00078e0017 */
/*06e0*/ ISETP.GE.AND P2, PT, R25, R27, PT ; /* 0x0000001b1900720c */
/* 0x000fda0003f46270 */
/*06f0*/ @!P2 STG.E [R2.64+-0x24], R27 ; /* 0xffffdc1b0200a986 */
/* 0x0001e8000c101906 */
/*0700*/ @!P2 STG.E [R2.64+-0x28], R25 ; /* 0xffffd8190200a986 */
/* 0x000fe2000c101906 */
/*0710*/ @!P2 IMAD.MOV.U32 R27, RZ, RZ, R25 ; /* 0x000000ffff1ba224 */
/* 0x001fca00078e0019 */
/*0720*/ ISETP.GE.AND P1, PT, R27, R29, PT ; /* 0x0000001d1b00720c */
/* 0x000fda0003f26270 */
/*0730*/ @!P1 STG.E [R2.64+-0x28], R29 ; /* 0xffffd81d02009986 */
/* 0x0001e8000c101906 */
/*0740*/ @!P1 STG.E [R2.64+-0x2c], R27 ; /* 0xffffd41b02009986 */
/* 0x000fe2000c101906 */
/*0750*/ @!P1 IMAD.MOV.U32 R29, RZ, RZ, R27 ; /* 0x000000ffff1d9224 */
/* 0x001fca00078e001b */
/*0760*/ ISETP.GE.AND P2, PT, R29, R6, PT ; /* 0x000000061d00720c */
/* 0x000fda0003f46270 */
/*0770*/ @!P2 STG.E [R2.64+-0x2c], R6 ; /* 0xffffd4060200a986 */
/* 0x0001e8000c101906 */
/*0780*/ @!P2 STG.E [R2.64+-0x30], R29 ; /* 0xffffd01d0200a986 */
/* 0x000fe2000c101906 */
/*0790*/ @!P2 IMAD.MOV.U32 R6, RZ, RZ, R29 ; /* 0x000000ffff06a224 */
/* 0x001fca00078e001d */
/*07a0*/ ISETP.GE.AND P1, PT, R6, R10, PT ; /* 0x0000000a0600720c */
/* 0x000fda0003f26270 */
/*07b0*/ @!P1 STG.E [R2.64+-0x30], R10 ; /* 0xffffd00a02009986 */
/* 0x0001e8000c101906 */
/*07c0*/ @!P1 STG.E [R2.64+-0x34], R6 ; /* 0xffffcc0602009986 */
/* 0x000fe2000c101906 */
/*07d0*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a9224 */
/* 0x001fca00078e0006 */
/*07e0*/ ISETP.GE.AND P2, PT, R10, R12, PT ; /* 0x0000000c0a00720c */
/* 0x000fda0003f46270 */
/*07f0*/ @!P2 STG.E [R2.64+-0x34], R12 ; /* 0xffffcc0c0200a986 */
/* 0x0001e8000c101906 */
/*0800*/ @!P2 STG.E [R2.64+-0x38], R10 ; /* 0xffffc80a0200a986 */
/* 0x000fe2000c101906 */
/*0810*/ @!P2 IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0ca224 */
/* 0x001fe200078e000a */
/*0820*/ ISETP.GT.AND P2, PT, R8, 0x10, PT ; /* 0x000000100800780c */
/* 0x000fc80003f44270 */
/*0830*/ ISETP.GE.AND P1, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x004fda0003f26270 */
/*0840*/ @!P1 STG.E [R2.64+-0x38], R5 ; /* 0xffffc80502009986 */
/* 0x0001e8000c101906 */
/*0850*/ @!P1 STG.E [R2.64+-0x3c], R12 ; /* 0xffffc40c02009986 */
/* 0x0003e2000c101906 */
/*0860*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff059224 */
/* 0x001fe400078e000c */
/*0870*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x002fe400078e0007 */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000e */
/*0890*/ @P2 BRA 0x330 ; /* 0xfffffa9000002947 */
/* 0x000fea000383ffff */
/*08a0*/ IADD3 R9, R8, -0x4, RZ ; /* 0xfffffffc08097810 */
/* 0x000fc80007ffe0ff */
/*08b0*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*08c0*/ @!P1 BRA 0xbb0 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*08d0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x000ea8000c1e1900 */
/*08e0*/ LDG.E R13, [R2.64+-0x4] ; /* 0xfffffc06020d7981 */
/* 0x000ee8000c1e1900 */
/*08f0*/ LDG.E R15, [R2.64+-0x8] ; /* 0xfffff806020f7981 */
/* 0x000f28000c1e1900 */
/*0900*/ LDG.E R17, [R2.64+-0xc] ; /* 0xfffff40602117981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R19, [R2.64+-0x10] ; /* 0xfffff00602137981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IADD3 R6, P2, R2, -0x10, RZ ; /* 0xfffffff002067810 */
/* 0x001fc80007f5e0ff */
/*0930*/ IADD3.X R7, R3, -0x1, RZ, P2, !PT ; /* 0xffffffff03077810 */
/* 0x000fe400017fe4ff */
/*0940*/ ISETP.GE.AND P0, PT, R5, R11, PT ; /* 0x0000000b0500720c */
/* 0x024fda0003f06270 */
/*0950*/ @!P0 STG.E [R2.64+0x4], R11 ; /* 0x0000040b02008986 */
/* 0x0001e8000c101906 */
/*0960*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x000fe2000c101906 */
/*0970*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b8224 */
/* 0x001fca00078e0005 */
/*0980*/ ISETP.GE.AND P1, PT, R11, R13, PT ; /* 0x0000000d0b00720c */
/* 0x008fda0003f26270 */
/*0990*/ @!P1 STG.E [R2.64], R13 ; /* 0x0000000d02009986 */
/* 0x0001e8000c101906 */
/*09a0*/ @!P1 STG.E [R2.64+-0x4], R11 ; /* 0xfffffc0b02009986 */
/* 0x000fe2000c101906 */
/*09b0*/ @!P1 IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d9224 */
/* 0x001fca00078e000b */
/*09c0*/ ISETP.GE.AND P0, PT, R13, R15, PT ; /* 0x0000000f0d00720c */
/* 0x010fda0003f06270 */
/*09d0*/ @!P0 STG.E [R2.64+-0x4], R15 ; /* 0xfffffc0f02008986 */
/* 0x0001e8000c101906 */
/*09e0*/ @!P0 STG.E [R2.64+-0x8], R13 ; /* 0xfffff80d02008986 */
/* 0x000fe2000c101906 */
/*09f0*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f8224 */
/* 0x001fca00078e000d */
/*0a00*/ ISETP.GE.AND P1, PT, R15, R17, PT ; /* 0x000000110f00720c */
/* 0x000fda0003f26270 */
/*0a10*/ @!P1 STG.E [R2.64+-0x8], R17 ; /* 0xfffff81102009986 */
/* 0x0001e8000c101906 */
/*0a20*/ @!P1 STG.E [R2.64+-0xc], R15 ; /* 0xfffff40f02009986 */
/* 0x000fe2000c101906 */
/*0a30*/ @!P1 IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff119224 */
/* 0x001fca00078e000f */
/*0a40*/ ISETP.GE.AND P0, PT, R17, R19, PT ; /* 0x000000131100720c */
/* 0x000fda0003f06270 */
/*0a50*/ @!P0 STG.E [R2.64+-0xc], R19 ; /* 0xfffff41302008986 */
/* 0x0001e8000c101906 */
/*0a60*/ @!P0 STG.E [R2.64+-0x10], R17 ; /* 0xfffff01102008986 */
/* 0x000fe8000c101906 */
/*0a70*/ LDG.E R11, [R6.64+-0x4] ; /* 0xfffffc06060b7981 */
/* 0x000ea8000c1e1900 */
/*0a80*/ LDG.E R10, [R6.64+-0x8] ; /* 0xfffff806060a7981 */
/* 0x000ee8000c1e1900 */
/*0a90*/ LDG.E R5, [R6.64+-0xc] ; /* 0xfffff40606057981 */
/* 0x000f22000c1e1900 */
/*0aa0*/ @!P0 IMAD.MOV.U32 R19, RZ, RZ, R17 ; /* 0x000000ffff138224 */
/* 0x001fe200078e0011 */
/*0ab0*/ IADD3 R8, R9, -0x4, RZ ; /* 0xfffffffc09087810 */
/* 0x000fc80007ffe0ff */
/*0ac0*/ ISETP.GE.AND P0, PT, R19, R11, PT ; /* 0x0000000b1300720c */
/* 0x004fda0003f06270 */
/*0ad0*/ @!P0 STG.E [R6.64], R11 ; /* 0x0000000b06008986 */
/* 0x0001e8000c101906 */
/*0ae0*/ @!P0 STG.E [R6.64+-0x4], R19 ; /* 0xfffffc1306008986 */
/* 0x000fe2000c101906 */
/*0af0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b8224 */
/* 0x001fe200078e0013 */
/*0b00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0b10*/ ISETP.GE.AND P1, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x008fda0003f26270 */
/*0b20*/ @!P1 STG.E [R6.64+-0x4], R10 ; /* 0xfffffc0a06009986 */
/* 0x0001e8000c101906 */
/*0b30*/ @!P1 STG.E [R6.64+-0x8], R11 ; /* 0xfffff80b06009986 */
/* 0x000fe2000c101906 */
/*0b40*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a9224 */
/* 0x001fe200078e000b */
/*0b50*/ IADD3 R2, P1, R6, -0x10, RZ ; /* 0xfffffff006027810 */
/* 0x000fc80007f3e0ff */
/*0b60*/ ISETP.GE.AND P2, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x010fe40003f46270 */
/*0b70*/ IADD3.X R3, R7, -0x1, RZ, P1, !PT ; /* 0xffffffff07037810 */
/* 0x000fd60000ffe4ff */
/*0b80*/ @!P2 STG.E [R6.64+-0xc], R10 ; /* 0xfffff40a0600a986 */
/* 0x000fe8000c101906 */
/*0b90*/ @!P2 STG.E [R6.64+-0x8], R5 ; /* 0xfffff8050600a986 */
/* 0x0001e4000c101906 */
/*0ba0*/ @!P2 IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff05a224 */
/* 0x001fe400078e000a */
/*0bb0*/ ISETP.GT.OR P0, PT, R8, 0x4, P0 ; /* 0x000000040800780c */
/* 0x000fda0000704670 */
/*0bc0*/ @!P0 BRA 0xd00 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x001ea8000c1e1900 */
/*0be0*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0602097981 */
/* 0x000ee8000c1e1900 */
/*0bf0*/ LDG.E R11, [R2.64+-0x8] ; /* 0xfffff806020b7981 */
/* 0x000f28000c1e1900 */
/*0c00*/ LDG.E R6, [R2.64+-0xc] ; /* 0xfffff40602067981 */
/* 0x000ee2000c1e1900 */
/*0c10*/ ISETP.GE.AND P0, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x024fda0003f06270 */
/*0c20*/ @!P0 STG.E [R2.64+0x4], R7 ; /* 0x0000040702008986 */
/* 0x0001e8000c101906 */
/*0c30*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x000fe2000c101906 */
/*0c40*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff078224 */
/* 0x001fca00078e0005 */
/*0c50*/ ISETP.GE.AND P1, PT, R7, R9, PT ; /* 0x000000090700720c */
/* 0x008fda0003f26270 */
/*0c60*/ @!P1 STG.E [R2.64], R9 ; /* 0x0000000902009986 */
/* 0x0001e8000c101906 */
/*0c70*/ @!P1 STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702009986 */
/* 0x000fe2000c101906 */
/*0c80*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff099224 */
/* 0x001fca00078e0007 */
/*0c90*/ ISETP.GE.AND P0, PT, R9, R11, PT ; /* 0x0000000b0900720c */
/* 0x010fda0003f06270 */
/*0ca0*/ @!P0 STG.E [R2.64+-0x4], R11 ; /* 0xfffffc0b02008986 */
/* 0x0001e8000c101906 */
/*0cb0*/ @!P0 STG.E [R2.64+-0x8], R9 ; /* 0xfffff80902008986 */
/* 0x0003e2000c101906 */
/*0cc0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b8224 */
/* 0x001fca00078e0009 */
/*0cd0*/ ISETP.GE.AND P1, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x000fda0003f26270 */
/*0ce0*/ @!P1 STG.E [R2.64+-0x8], R6 ; /* 0xfffff80602009986 */
/* 0x0003e8000c101906 */
/*0cf0*/ @!P1 STG.E [R2.64+-0xc], R11 ; /* 0xfffff40b02009986 */
/* 0x0003e4000c101906 */
/*0d00*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0d10*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x020fc600078e0004 */
/*0d20*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0d30*/ @!P0 BRA 0xa0 ; /* 0xfffff36000008947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // heavy assistance provided from nVidia's CUDA documentation and `vectorAdd.cu` piece of sample code
#include <stdio.h>
#include <sys/time.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
int* generate_array(int); // prototypes at the top of a non-header, because I hate C.
char* run_insertion_sort(int); // wraps the cuda_insertion_sort function
// this is quite possibly the stupidest piece of code I've written
// this is a single CUDA block for doing insertion sort
// insertion sort is not a parallelizable algorithm.
__global__ void cuda_insertion_sort(int *array, int num_elements) {
int temp;
for (int i = 1; i < num_elements; i++) {
for(int j = i ; j > 0 ; j--){
if(array[j] < array[j-1]){
temp = array[j];
array[j] = array[j-1];
array[j-1] = temp;
}
}
}
}
int main(void) {
FILE *f;
f = fopen("cuda_insertion.txt", "w");
for(int i = 1000; i < 11000; i+= 1000) {
printf("%d ", i);
fprintf(f, "%d ", i);
char* return_time = run_insertion_sort(i);
fprintf(f, "%s ", return_time);
printf("%s ", return_time);
fflush(stdout);
free(return_time);
printf("\n");
fprintf(f, "\n");
}
cudaError_t err = cudaDeviceReset();
if (err != cudaSuccess) {
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
fflush(f);
fclose(f);
printf("Done\n");
return 0;
}
char* run_insertion_sort(int num_elements) {
// initialize host's elements
cudaError_t err = cudaSuccess;
int* host_array = generate_array(num_elements);
// initialize CUDA device's element
int* cuda_array = NULL;
size_t size = num_elements * sizeof(int);
err = cudaMalloc((void **)&cuda_array, size);
if (err != cudaSuccess) { // check for errors on memory allocation
fprintf(stderr, "Failed to allocate memory for array (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
struct timeval tval_before, tval_after, tval_result; // declare some timing info
gettimeofday(&tval_before, NULL);
// copy the host element onto the CUDA device's element
err = cudaMemcpy(cuda_array, host_array, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess) { // check for errors on memory copy over to device
fprintf(stderr, "Failed to copy array from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cuda_insertion_sort<<<1,1>>>(cuda_array, num_elements); // execute the kernel
err = cudaGetLastError(); // check for any errors during kernel execution
if (err != cudaSuccess) {
fprintf(stderr, "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// copy the result back from the CUDA device
err = cudaMemcpy(host_array, cuda_array, size, cudaMemcpyDeviceToHost); // this is a synchronous function.
gettimeofday(&tval_after, NULL);
timersub(&tval_after, &tval_before, &tval_result); // finish up the timing
if (err != cudaSuccess) { // check for any errors on memory copy back to host
fprintf(stderr, "Failed to copy array from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// and clean up
err = cudaFree(cuda_array);
if (err != cudaSuccess) { // check for any errors on freeing the memory
fprintf(stderr, "Failed to free device array (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
free(host_array);
// return info on the time spent
char* return_string = (char*)malloc(100 * sizeof(char));
sprintf(return_string, "%ld%03ld", (long int)tval_result.tv_sec, (long int)tval_result.tv_usec / 1000);
return return_string;
}
int* generate_array(int array_length) {
int *return_var = (int*)malloc(sizeof(int) * array_length);
for (int i = array_length - 1; i >= 0; i--) {
return_var[array_length - i - 1] = i;
}
return return_var;
} | .file "tmpxft_0007a484_00000000-6_insertion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14generate_arrayi
.type _Z14generate_arrayi, @function
_Z14generate_arrayi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
subl $1, %ebx
js .L3
movl %ebx, %edi
movq %rax, %rdx
.L5:
movl %edi, (%rdx)
subl $1, %edi
addq $4, %rdx
cmpl $-1, %edi
jne .L5
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z14generate_arrayi, .-_Z14generate_arrayi
.globl _Z40__device_stub__Z19cuda_insertion_sortPiiPii
.type _Z40__device_stub__Z19cuda_insertion_sortPiiPii, @function
_Z40__device_stub__Z19cuda_insertion_sortPiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19cuda_insertion_sortPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z19cuda_insertion_sortPiiPii, .-_Z40__device_stub__Z19cuda_insertion_sortPiiPii
.globl _Z19cuda_insertion_sortPii
.type _Z19cuda_insertion_sortPii, @function
_Z19cuda_insertion_sortPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19cuda_insertion_sortPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z19cuda_insertion_sortPii, .-_Z19cuda_insertion_sortPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate memory for array (error code %s)!\n"
.align 8
.LC1:
.string "Failed to copy array from host to device (error code %s)!\n"
.align 8
.LC2:
.string "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n"
.align 8
.LC3:
.string "Failed to copy array from device to host (error code %s)!\n"
.align 8
.LC4:
.string "Failed to free device array (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%ld%03ld"
.text
.globl _Z18run_insertion_sorti
.type _Z18run_insertion_sorti, @function
_Z18run_insertion_sorti:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _Z14generate_arrayi
movq %rax, %rbp
movq $0, 8(%rsp)
movslq %r12d, %rbx
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L27
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L19:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %r12
subq 32(%rsp), %r12
movq 56(%rsp), %rbx
subq 40(%rsp), %rbx
js .L30
.L21:
testl %r13d, %r13d
jne .L31
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L32
movq %rbp, %rdi
call free@PLT
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movabsq $2361183241434822607, %rdx
movq %rbx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rbx
subq %rbx, %rdx
movq %rdx, %r9
movq %r12, %r8
leaq .LC5(%rip), %rcx
movl $100, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L33
movq %rbp, %rax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z19cuda_insertion_sortPiiPii
jmp .L19
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
subq $1, %r12
addq $1000000, %rbx
jmp .L21
.L31:
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z18run_insertion_sorti, .-_Z18run_insertion_sorti
.section .rodata.str1.1
.LC6:
.string "w"
.LC7:
.string "cuda_insertion.txt"
.LC8:
.string "%d "
.LC9:
.string "%s "
.LC10:
.string "\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Failed to deinitialize the device! error=%s\n"
.section .rodata.str1.1
.LC12:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC6(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl $1000, %ebx
leaq .LC8(%rip), %r15
leaq .LC9(%rip), %r14
leaq .LC10(%rip), %r13
.L35:
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call _Z18run_insertion_sorti
movq %rax, %rbp
movq %rax, %rcx
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1000, %ebx
cmpl $11000, %ebx
jne .L35
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L39
movq %r12, %rdi
call fflush@PLT
movq %r12, %rdi
call fclose@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z19cuda_insertion_sortPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cuda_insertion_sortPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // heavy assistance provided from nVidia's CUDA documentation and `vectorAdd.cu` piece of sample code
#include <stdio.h>
#include <sys/time.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
int* generate_array(int); // prototypes at the top of a non-header, because I hate C.
char* run_insertion_sort(int); // wraps the cuda_insertion_sort function
// this is quite possibly the stupidest piece of code I've written
// this is a single CUDA block for doing insertion sort
// insertion sort is not a parallelizable algorithm.
__global__ void cuda_insertion_sort(int *array, int num_elements) {
int temp;
for (int i = 1; i < num_elements; i++) {
for(int j = i ; j > 0 ; j--){
if(array[j] < array[j-1]){
temp = array[j];
array[j] = array[j-1];
array[j-1] = temp;
}
}
}
}
int main(void) {
FILE *f;
f = fopen("cuda_insertion.txt", "w");
for(int i = 1000; i < 11000; i+= 1000) {
printf("%d ", i);
fprintf(f, "%d ", i);
char* return_time = run_insertion_sort(i);
fprintf(f, "%s ", return_time);
printf("%s ", return_time);
fflush(stdout);
free(return_time);
printf("\n");
fprintf(f, "\n");
}
cudaError_t err = cudaDeviceReset();
if (err != cudaSuccess) {
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
fflush(f);
fclose(f);
printf("Done\n");
return 0;
}
char* run_insertion_sort(int num_elements) {
// initialize host's elements
cudaError_t err = cudaSuccess;
int* host_array = generate_array(num_elements);
// initialize CUDA device's element
int* cuda_array = NULL;
size_t size = num_elements * sizeof(int);
err = cudaMalloc((void **)&cuda_array, size);
if (err != cudaSuccess) { // check for errors on memory allocation
fprintf(stderr, "Failed to allocate memory for array (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
struct timeval tval_before, tval_after, tval_result; // declare some timing info
gettimeofday(&tval_before, NULL);
// copy the host element onto the CUDA device's element
err = cudaMemcpy(cuda_array, host_array, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess) { // check for errors on memory copy over to device
fprintf(stderr, "Failed to copy array from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cuda_insertion_sort<<<1,1>>>(cuda_array, num_elements); // execute the kernel
err = cudaGetLastError(); // check for any errors during kernel execution
if (err != cudaSuccess) {
fprintf(stderr, "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// copy the result back from the CUDA device
err = cudaMemcpy(host_array, cuda_array, size, cudaMemcpyDeviceToHost); // this is a synchronous function.
gettimeofday(&tval_after, NULL);
timersub(&tval_after, &tval_before, &tval_result); // finish up the timing
if (err != cudaSuccess) { // check for any errors on memory copy back to host
fprintf(stderr, "Failed to copy array from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// and clean up
err = cudaFree(cuda_array);
if (err != cudaSuccess) { // check for any errors on freeing the memory
fprintf(stderr, "Failed to free device array (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
free(host_array);
// return info on the time spent
char* return_string = (char*)malloc(100 * sizeof(char));
sprintf(return_string, "%ld%03ld", (long int)tval_result.tv_sec, (long int)tval_result.tv_usec / 1000);
return return_string;
}
int* generate_array(int array_length) {
int *return_var = (int*)malloc(sizeof(int) * array_length);
for (int i = array_length - 1; i >= 0; i--) {
return_var[array_length - i - 1] = i;
}
return return_var;
} | // heavy assistance provided from nVidia's CUDA documentation and `vectorAdd.cu` piece of sample code
#include <stdio.h>
#include <sys/time.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
int* generate_array(int); // prototypes at the top of a non-header, because I hate C.
char* run_insertion_sort(int); // wraps the cuda_insertion_sort function
// this is quite possibly the stupidest piece of code I've written
// this is a single CUDA block for doing insertion sort
// insertion sort is not a parallelizable algorithm.
__global__ void cuda_insertion_sort(int *array, int num_elements) {
int temp;
for (int i = 1; i < num_elements; i++) {
for(int j = i ; j > 0 ; j--){
if(array[j] < array[j-1]){
temp = array[j];
array[j] = array[j-1];
array[j-1] = temp;
}
}
}
}
int main(void) {
FILE *f;
f = fopen("cuda_insertion.txt", "w");
for(int i = 1000; i < 11000; i+= 1000) {
printf("%d ", i);
fprintf(f, "%d ", i);
char* return_time = run_insertion_sort(i);
fprintf(f, "%s ", return_time);
printf("%s ", return_time);
fflush(stdout);
free(return_time);
printf("\n");
fprintf(f, "\n");
}
hipError_t err = hipDeviceReset();
if (err != hipSuccess) {
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
fflush(f);
fclose(f);
printf("Done\n");
return 0;
}
char* run_insertion_sort(int num_elements) {
// initialize host's elements
hipError_t err = hipSuccess;
int* host_array = generate_array(num_elements);
// initialize CUDA device's element
int* cuda_array = NULL;
size_t size = num_elements * sizeof(int);
err = hipMalloc((void **)&cuda_array, size);
if (err != hipSuccess) { // check for errors on memory allocation
fprintf(stderr, "Failed to allocate memory for array (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
struct timeval tval_before, tval_after, tval_result; // declare some timing info
gettimeofday(&tval_before, NULL);
// copy the host element onto the CUDA device's element
err = hipMemcpy(cuda_array, host_array, size, hipMemcpyHostToDevice);
if (err != hipSuccess) { // check for errors on memory copy over to device
fprintf(stderr, "Failed to copy array from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
cuda_insertion_sort<<<1,1>>>(cuda_array, num_elements); // execute the kernel
err = hipGetLastError(); // check for any errors during kernel execution
if (err != hipSuccess) {
fprintf(stderr, "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// copy the result back from the CUDA device
err = hipMemcpy(host_array, cuda_array, size, hipMemcpyDeviceToHost); // this is a synchronous function.
gettimeofday(&tval_after, NULL);
timersub(&tval_after, &tval_before, &tval_result); // finish up the timing
if (err != hipSuccess) { // check for any errors on memory copy back to host
fprintf(stderr, "Failed to copy array from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// and clean up
err = hipFree(cuda_array);
if (err != hipSuccess) { // check for any errors on freeing the memory
fprintf(stderr, "Failed to free device array (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
free(host_array);
// return info on the time spent
char* return_string = (char*)malloc(100 * sizeof(char));
sprintf(return_string, "%ld%03ld", (long int)tval_result.tv_sec, (long int)tval_result.tv_usec / 1000);
return return_string;
}
int* generate_array(int array_length) {
int *return_var = (int*)malloc(sizeof(int) * array_length);
for (int i = array_length - 1; i >= 0; i--) {
return_var[array_length - i - 1] = i;
}
return return_var;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // heavy assistance provided from nVidia's CUDA documentation and `vectorAdd.cu` piece of sample code
#include <stdio.h>
#include <sys/time.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
int* generate_array(int); // prototypes at the top of a non-header, because I hate C.
char* run_insertion_sort(int); // wraps the cuda_insertion_sort function
// this is quite possibly the stupidest piece of code I've written
// this is a single CUDA block for doing insertion sort
// insertion sort is not a parallelizable algorithm.
__global__ void cuda_insertion_sort(int *array, int num_elements) {
int temp;
for (int i = 1; i < num_elements; i++) {
for(int j = i ; j > 0 ; j--){
if(array[j] < array[j-1]){
temp = array[j];
array[j] = array[j-1];
array[j-1] = temp;
}
}
}
}
int main(void) {
FILE *f;
f = fopen("cuda_insertion.txt", "w");
for(int i = 1000; i < 11000; i+= 1000) {
printf("%d ", i);
fprintf(f, "%d ", i);
char* return_time = run_insertion_sort(i);
fprintf(f, "%s ", return_time);
printf("%s ", return_time);
fflush(stdout);
free(return_time);
printf("\n");
fprintf(f, "\n");
}
hipError_t err = hipDeviceReset();
if (err != hipSuccess) {
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
fflush(f);
fclose(f);
printf("Done\n");
return 0;
}
char* run_insertion_sort(int num_elements) {
// initialize host's elements
hipError_t err = hipSuccess;
int* host_array = generate_array(num_elements);
// initialize CUDA device's element
int* cuda_array = NULL;
size_t size = num_elements * sizeof(int);
err = hipMalloc((void **)&cuda_array, size);
if (err != hipSuccess) { // check for errors on memory allocation
fprintf(stderr, "Failed to allocate memory for array (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
struct timeval tval_before, tval_after, tval_result; // declare some timing info
gettimeofday(&tval_before, NULL);
// copy the host element onto the CUDA device's element
err = hipMemcpy(cuda_array, host_array, size, hipMemcpyHostToDevice);
if (err != hipSuccess) { // check for errors on memory copy over to device
fprintf(stderr, "Failed to copy array from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
cuda_insertion_sort<<<1,1>>>(cuda_array, num_elements); // execute the kernel
err = hipGetLastError(); // check for any errors during kernel execution
if (err != hipSuccess) {
fprintf(stderr, "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// copy the result back from the CUDA device
err = hipMemcpy(host_array, cuda_array, size, hipMemcpyDeviceToHost); // this is a synchronous function.
gettimeofday(&tval_after, NULL);
timersub(&tval_after, &tval_before, &tval_result); // finish up the timing
if (err != hipSuccess) { // check for any errors on memory copy back to host
fprintf(stderr, "Failed to copy array from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// and clean up
err = hipFree(cuda_array);
if (err != hipSuccess) { // check for any errors on freeing the memory
fprintf(stderr, "Failed to free device array (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
free(host_array);
// return info on the time spent
char* return_string = (char*)malloc(100 * sizeof(char));
sprintf(return_string, "%ld%03ld", (long int)tval_result.tv_sec, (long int)tval_result.tv_usec / 1000);
return return_string;
}
int* generate_array(int array_length) {
int *return_var = (int*)malloc(sizeof(int) * array_length);
for (int i = array_length - 1; i >= 0; i--) {
return_var[array_length - i - 1] = i;
}
return return_var;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19cuda_insertion_sortPii
.globl _Z19cuda_insertion_sortPii
.p2align 8
.type _Z19cuda_insertion_sortPii,@function
_Z19cuda_insertion_sortPii:
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s5, 2
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 2
s_cbranch_scc1 .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s6, 1
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s6, s6, 1
s_add_i32 s5, s5, 1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s6, s4
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_mov_b64 s[2:3], s[0:1]
s_mov_b32 s7, s5
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_add_i32 s7, s7, -1
s_add_u32 s2, s2, -4
s_addc_u32 s3, s3, -1
s_cmp_lt_i32 s7, 2
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[2:3] offset:-4
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v1, v2
s_cbranch_vccnz .LBB0_4
s_clause 0x1
global_store_b32 v0, v2, s[2:3]
global_store_b32 v0, v1, s[2:3] offset:-4
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19cuda_insertion_sortPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19cuda_insertion_sortPii, .Lfunc_end0-_Z19cuda_insertion_sortPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19cuda_insertion_sortPii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z19cuda_insertion_sortPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // heavy assistance provided from nVidia's CUDA documentation and `vectorAdd.cu` piece of sample code
#include <stdio.h>
#include <sys/time.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
int* generate_array(int); // prototypes at the top of a non-header, because I hate C.
char* run_insertion_sort(int); // wraps the cuda_insertion_sort function
// this is quite possibly the stupidest piece of code I've written
// this is a single CUDA block for doing insertion sort
// insertion sort is not a parallelizable algorithm.
__global__ void cuda_insertion_sort(int *array, int num_elements) {
int temp;
for (int i = 1; i < num_elements; i++) {
for(int j = i ; j > 0 ; j--){
if(array[j] < array[j-1]){
temp = array[j];
array[j] = array[j-1];
array[j-1] = temp;
}
}
}
}
int main(void) {
FILE *f;
f = fopen("cuda_insertion.txt", "w");
for(int i = 1000; i < 11000; i+= 1000) {
printf("%d ", i);
fprintf(f, "%d ", i);
char* return_time = run_insertion_sort(i);
fprintf(f, "%s ", return_time);
printf("%s ", return_time);
fflush(stdout);
free(return_time);
printf("\n");
fprintf(f, "\n");
}
hipError_t err = hipDeviceReset();
if (err != hipSuccess) {
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
fflush(f);
fclose(f);
printf("Done\n");
return 0;
}
char* run_insertion_sort(int num_elements) {
// initialize host's elements
hipError_t err = hipSuccess;
int* host_array = generate_array(num_elements);
// initialize CUDA device's element
int* cuda_array = NULL;
size_t size = num_elements * sizeof(int);
err = hipMalloc((void **)&cuda_array, size);
if (err != hipSuccess) { // check for errors on memory allocation
fprintf(stderr, "Failed to allocate memory for array (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
struct timeval tval_before, tval_after, tval_result; // declare some timing info
gettimeofday(&tval_before, NULL);
// copy the host element onto the CUDA device's element
err = hipMemcpy(cuda_array, host_array, size, hipMemcpyHostToDevice);
if (err != hipSuccess) { // check for errors on memory copy over to device
fprintf(stderr, "Failed to copy array from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
cuda_insertion_sort<<<1,1>>>(cuda_array, num_elements); // execute the kernel
err = hipGetLastError(); // check for any errors during kernel execution
if (err != hipSuccess) {
fprintf(stderr, "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// copy the result back from the CUDA device
err = hipMemcpy(host_array, cuda_array, size, hipMemcpyDeviceToHost); // this is a synchronous function.
gettimeofday(&tval_after, NULL);
timersub(&tval_after, &tval_before, &tval_result); // finish up the timing
if (err != hipSuccess) { // check for any errors on memory copy back to host
fprintf(stderr, "Failed to copy array from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// and clean up
err = hipFree(cuda_array);
if (err != hipSuccess) { // check for any errors on freeing the memory
fprintf(stderr, "Failed to free device array (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
free(host_array);
// return info on the time spent
char* return_string = (char*)malloc(100 * sizeof(char));
sprintf(return_string, "%ld%03ld", (long int)tval_result.tv_sec, (long int)tval_result.tv_usec / 1000);
return return_string;
}
int* generate_array(int array_length) {
int *return_var = (int*)malloc(sizeof(int) * array_length);
for (int i = array_length - 1; i >= 0; i--) {
return_var[array_length - i - 1] = i;
}
return return_var;
} | .text
.file "insertion.hip"
.globl _Z34__device_stub__cuda_insertion_sortPii # -- Begin function _Z34__device_stub__cuda_insertion_sortPii
.p2align 4, 0x90
.type _Z34__device_stub__cuda_insertion_sortPii,@function
_Z34__device_stub__cuda_insertion_sortPii: # @_Z34__device_stub__cuda_insertion_sortPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19cuda_insertion_sortPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__cuda_insertion_sortPii, .Lfunc_end0-_Z34__device_stub__cuda_insertion_sortPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
addl $1000, %ebp # imm = 0x3E8
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %esi
movq %rbx, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq _Z18run_insertion_sorti
movq %rax, %r14
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $.L.str.3, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movq stdout(%rip), %rdi
callq fflush
movq %r14, %rdi
callq free
movl $10, %edi
callq putchar@PLT
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
cmpl $10000, %ebp # imm = 0x2710
jb .LBB1_1
# %bb.2:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq %rbx, %rdi
callq fflush
movq %rbx, %rdi
callq fclose
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z18run_insertion_sorti # -- Begin function _Z18run_insertion_sorti
.p2align 4, 0x90
.type _Z18run_insertion_sorti,@function
_Z18run_insertion_sorti: # @_Z18run_insertion_sorti
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader.i
movl %ebp, %ecx
movq %rbx, %rax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq -1(%rcx), %rdx
movl %edx, (%rax)
addq $4, %rax
cmpq $1, %rcx
movq %rdx, %rcx
jg .LBB2_2
.LBB2_3: # %_Z14generate_arrayi.exit
movq $0, (%rsp)
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.6:
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_7
# %bb.8:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq (%rsp), %rax
movq %rax, 80(%rsp)
movl %ebp, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z19cuda_insertion_sortPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_11
# %bb.12:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl %eax, %ebp
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
jne .LBB2_13
# %bb.14:
movq 16(%rsp), %r12
movq 24(%rsp), %r14
movq 88(%rsp), %r13
movq 96(%rsp), %r15
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_15
# %bb.16:
subq %r15, %r14
leaq 1000000(%r14), %r15
testq %r14, %r14
cmovnsq %r14, %r15
subq %r13, %r12
sarq $63, %r14
addq %r12, %r14
movq %rbx, %rdi
callq free
movl $100, %edi
callq malloc
movq %rax, %rbx
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
movq %r15, %rax
imulq %rcx
movq %rdx, %rcx
shrq $63, %rcx
sarq $7, %rdx
addq %rdx, %rcx
movl $.L.str.12, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq sprintf
movq %rbx, %rax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB2_5
.LBB2_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB2_5
.LBB2_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB2_5
.LBB2_13:
movq stderr(%rip), %rbx
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB2_5
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
.LBB2_5:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z18run_insertion_sorti, .Lfunc_end2-_Z18run_insertion_sorti
.cfi_endproc
# -- End function
.globl _Z14generate_arrayi # -- Begin function _Z14generate_arrayi
.p2align 4, 0x90
.type _Z14generate_arrayi,@function
_Z14generate_arrayi: # @_Z14generate_arrayi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movslq %edi, %r14
leaq (,%r14,4), %rdi
callq malloc
testl %r14d, %r14d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %edx
movq %rax, %rcx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq -1(%rdx), %rsi
movl %esi, (%rcx)
addq $4, %rcx
cmpq $1, %rdx
movq %rsi, %rdx
jg .LBB3_2
.LBB3_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14generate_arrayi, .Lfunc_end3-_Z14generate_arrayi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19cuda_insertion_sortPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19cuda_insertion_sortPii,@object # @_Z19cuda_insertion_sortPii
.section .rodata,"a",@progbits
.globl _Z19cuda_insertion_sortPii
.p2align 3, 0x0
_Z19cuda_insertion_sortPii:
.quad _Z34__device_stub__cuda_insertion_sortPii
.size _Z19cuda_insertion_sortPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cuda_insertion.txt"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s "
.size .L.str.3, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.5, 45
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate memory for array (error code %s)!\n"
.size .L.str.7, 54
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to copy array from host to device (error code %s)!\n"
.size .L.str.8, 59
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n"
.size .L.str.9, 64
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to copy array from device to host (error code %s)!\n"
.size .L.str.10, 59
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to free device array (error code %s)!\n"
.size .L.str.11, 46
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%ld%03ld"
.size .L.str.12, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19cuda_insertion_sortPii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__cuda_insertion_sortPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19cuda_insertion_sortPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19cuda_insertion_sortPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0060*/ UIADD3 UR4, UP0, UR4, -0x4, URZ ; /* 0xfffffffc04047890 */
/* 0x000fe2000ff1e03f */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ UIADD3.X UR5, UR5, -0x1, URZ, UP0, !UPT ; /* 0xffffffff05057890 */
/* 0x000fe400087fe43f */
/*00a0*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x002fc600078e0000 */
/*00c0*/ LOP3.LUT P0, R8, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304087812 */
/* 0x000fda000780c0ff */
/*00d0*/ @!P0 BRA 0x260 ; /* 0x0000018000008947 */
/* 0x005fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0100*/ LDG.E R7, [R2.64+-0x4] ; /* 0xfffffc0602077981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea2000c1e1900 */
/*0120*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe40003f25270 */
/*0130*/ IADD3 R9, R0, -0x1, RZ ; /* 0xffffffff00097810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x004fda0003f06270 */
/*0150*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e8000c101906 */
/*0160*/ @!P0 STG.E [R2.64+-0x4], R6 ; /* 0xfffffc0602008986 */
/* 0x0003e2000c101906 */
/*0170*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff078224 */
/* 0x001fe200078e0006 */
/*0180*/ @!P1 BRA 0x260 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R11, [R2.64+-0x8] ; /* 0xfffff806020b7981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ ISETP.NE.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe40003f25270 */
/*01b0*/ IADD3 R9, R0, -0x2, RZ ; /* 0xfffffffe00097810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.AND P0, PT, R7, R11, PT ; /* 0x0000000b0700720c */
/* 0x004fda0003f06270 */
/*01d0*/ @!P0 STG.E [R2.64+-0x4], R11 ; /* 0xfffffc0b02008986 */
/* 0x0001e8000c101906 */
/*01e0*/ @!P0 STG.E [R2.64+-0x8], R7 ; /* 0xfffff80702008986 */
/* 0x0005e2000c101906 */
/*01f0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b8224 */
/* 0x001fe200078e0007 */
/*0200*/ @!P1 BRA 0x260 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R6, [R2.64+-0xc] ; /* 0xfffff40602067981 */
/* 0x002ee2000c1e1900 */
/*0220*/ IADD3 R9, R0, -0x3, RZ ; /* 0xfffffffd00097810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.GE.AND P0, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x008fda0003f06270 */
/*0240*/ @!P0 STG.E [R2.64+-0x8], R6 ; /* 0xfffff80602008986 */
/* 0x0001e8000c101906 */
/*0250*/ @!P0 STG.E [R2.64+-0xc], R11 ; /* 0xfffff40b02008986 */
/* 0x0001e4000c101906 */
/*0260*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fda0003f06070 */
/*0270*/ @!P0 BRA 0xd00 ; /* 0x00000a8000008947 */
/* 0x000fea0003800000 */
/*0280*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe20003f24270 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x003fc800078e00ff */
/*02a0*/ IMAD.WIDE R6, R9, R6, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x004fc800078e0206 */
/*02b0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*02c0*/ LDG.E R5, [R6.64] ; /* 0x0000000606057981 */
/* 0x000162000c1e1900 */
/*02d0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*02e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*02f0*/ IADD3 R8, R9.reuse, 0x4, RZ ; /* 0x0000000409087810 */
/* 0x040fe20007ffe0ff */
/*0300*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x000fe200078e0202 */
/*0310*/ @!P1 BRA 0x8a0 ; /* 0x0000058000009947 */
/* 0x000fea0003800000 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0330*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x001ea8000c1e1900 */
/*0340*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0602097981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R11, [R2.64+-0x8] ; /* 0xfffff806020b7981 */
/* 0x000f28000c1e1900 */
/*0360*/ LDG.E R13, [R2.64+-0xc] ; /* 0xfffff406020d7981 */
/* 0x000ee8000c1e1900 */
/*0370*/ LDG.E R15, [R2.64+-0x10] ; /* 0xfffff006020f7981 */
/* 0x000ee8000c1e1900 */
/*0380*/ LDG.E R17, [R2.64+-0x14] ; /* 0xffffec0602117981 */
/* 0x000ee8000c1e1900 */
/*0390*/ LDG.E R19, [R2.64+-0x18] ; /* 0xffffe80602137981 */
/* 0x000ee8000c1e1900 */
/*03a0*/ LDG.E R21, [R2.64+-0x1c] ; /* 0xffffe40602157981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R23, [R2.64+-0x20] ; /* 0xffffe00602177981 */
/* 0x000f28000c1e1900 */
/*03c0*/ LDG.E R25, [R2.64+-0x24] ; /* 0xffffdc0602197981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R27, [R2.64+-0x28] ; /* 0xffffd806021b7981 */
/* 0x000f28000c1e1900 */
/*03e0*/ LDG.E R29, [R2.64+-0x2c] ; /* 0xffffd406021d7981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R6, [R2.64+-0x30] ; /* 0xffffd00602067981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R10, [R2.64+-0x34] ; /* 0xffffcc06020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R12, [R2.64+-0x38] ; /* 0xffffc806020c7981 */
/* 0x000f22000c1e1900 */
/*0420*/ ISETP.GE.AND P1, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x024fda0003f26270 */
/*0430*/ @!P1 STG.E [R2.64+0x4], R7 ; /* 0x0000040702009986 */
/* 0x0001e8000c101906 */
/*0440*/ @!P1 STG.E [R2.64], R5 ; /* 0x0000000502009986 */
/* 0x0003e2000c101906 */
/*0450*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff079224 */
/* 0x001fc600078e0005 */
/*0460*/ LDG.E R5, [R2.64+-0x3c] ; /* 0xffffc40602057981 */
/* 0x002ea4000c1e1900 */
/*0470*/ ISETP.GE.AND P1, PT, R7, R9, PT ; /* 0x000000090700720c */
/* 0x008fe40003f26270 */
/*0480*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fd60007ffe0ff */
/*0490*/ @!P1 STG.E [R2.64], R9 ; /* 0x0000000902009986 */
/* 0x0001e8000c101906 */
/*04a0*/ @!P1 STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702009986 */
/* 0x0003e2000c101906 */
/*04b0*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff099224 */
/* 0x001fe200078e0007 */
/*04c0*/ IADD3 R7, P3, R2, -0x40, RZ ; /* 0xffffffc002077810 */
/* 0x002fc80007f7e0ff */
/*04d0*/ ISETP.GE.AND P2, PT, R9, R11, PT ; /* 0x0000000b0900720c */
/* 0x010fe40003f46270 */
/*04e0*/ IADD3.X R14, R3, -0x1, RZ, P3, !PT ; /* 0xffffffff030e7810 */
/* 0x000fd60001ffe4ff */
/*04f0*/ @!P2 STG.E [R2.64+-0x4], R11 ; /* 0xfffffc0b0200a986 */
/* 0x0001e8000c101906 */
/*0500*/ @!P2 STG.E [R2.64+-0x8], R9 ; /* 0xfffff8090200a986 */
/* 0x000fe2000c101906 */
/*0510*/ @!P2 IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0ba224 */
/* 0x001fca00078e0009 */
/*0520*/ ISETP.GE.AND P1, PT, R11, R13, PT ; /* 0x0000000d0b00720c */
/* 0x000fda0003f26270 */
/*0530*/ @!P1 STG.E [R2.64+-0x8], R13 ; /* 0xfffff80d02009986 */
/* 0x0001e8000c101906 */
/*0540*/ @!P1 STG.E [R2.64+-0xc], R11 ; /* 0xfffff40b02009986 */
/* 0x000fe2000c101906 */
/*0550*/ @!P1 IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d9224 */
/* 0x001fca00078e000b */
/*0560*/ ISETP.GE.AND P2, PT, R13, R15, PT ; /* 0x0000000f0d00720c */
/* 0x000fda0003f46270 */
/*0570*/ @!P2 STG.E [R2.64+-0xc], R15 ; /* 0xfffff40f0200a986 */
/* 0x0001e8000c101906 */
/*0580*/ @!P2 STG.E [R2.64+-0x10], R13 ; /* 0xfffff00d0200a986 */
/* 0x000fe2000c101906 */
/*0590*/ @!P2 IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0fa224 */
/* 0x001fca00078e000d */
/*05a0*/ ISETP.GE.AND P1, PT, R15, R17, PT ; /* 0x000000110f00720c */
/* 0x000fda0003f26270 */
/*05b0*/ @!P1 STG.E [R2.64+-0x10], R17 ; /* 0xfffff01102009986 */
/* 0x0001e8000c101906 */
/*05c0*/ @!P1 STG.E [R2.64+-0x14], R15 ; /* 0xffffec0f02009986 */
/* 0x000fe2000c101906 */
/*05d0*/ @!P1 IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff119224 */
/* 0x001fca00078e000f */
/*05e0*/ ISETP.GE.AND P2, PT, R17, R19, PT ; /* 0x000000131100720c */
/* 0x000fda0003f46270 */
/*05f0*/ @!P2 STG.E [R2.64+-0x14], R19 ; /* 0xffffec130200a986 */
/* 0x0001e8000c101906 */
/*0600*/ @!P2 STG.E [R2.64+-0x18], R17 ; /* 0xffffe8110200a986 */
/* 0x000fe2000c101906 */
/*0610*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, R17 ; /* 0x000000ffff13a224 */
/* 0x001fca00078e0011 */
/*0620*/ ISETP.GE.AND P1, PT, R19, R21, PT ; /* 0x000000151300720c */
/* 0x000fda0003f26270 */
/*0630*/ @!P1 STG.E [R2.64+-0x18], R21 ; /* 0xffffe81502009986 */
/* 0x0001e8000c101906 */
/*0640*/ @!P1 STG.E [R2.64+-0x1c], R19 ; /* 0xffffe41302009986 */
/* 0x000fe2000c101906 */
/*0650*/ @!P1 IMAD.MOV.U32 R21, RZ, RZ, R19 ; /* 0x000000ffff159224 */
/* 0x001fca00078e0013 */
/*0660*/ ISETP.GE.AND P2, PT, R21, R23, PT ; /* 0x000000171500720c */
/* 0x000fda0003f46270 */
/*0670*/ @!P2 STG.E [R2.64+-0x1c], R23 ; /* 0xffffe4170200a986 */
/* 0x0001e8000c101906 */
/*0680*/ @!P2 STG.E [R2.64+-0x20], R21 ; /* 0xffffe0150200a986 */
/* 0x000fe2000c101906 */
/*0690*/ @!P2 IMAD.MOV.U32 R23, RZ, RZ, R21 ; /* 0x000000ffff17a224 */
/* 0x001fca00078e0015 */
/*06a0*/ ISETP.GE.AND P1, PT, R23, R25, PT ; /* 0x000000191700720c */
/* 0x000fda0003f26270 */
/*06b0*/ @!P1 STG.E [R2.64+-0x20], R25 ; /* 0xffffe01902009986 */
/* 0x0001e8000c101906 */
/*06c0*/ @!P1 STG.E [R2.64+-0x24], R23 ; /* 0xffffdc1702009986 */
/* 0x000fe2000c101906 */
/*06d0*/ @!P1 IMAD.MOV.U32 R25, RZ, RZ, R23 ; /* 0x000000ffff199224 */
/* 0x001fca00078e0017 */
/*06e0*/ ISETP.GE.AND P2, PT, R25, R27, PT ; /* 0x0000001b1900720c */
/* 0x000fda0003f46270 */
/*06f0*/ @!P2 STG.E [R2.64+-0x24], R27 ; /* 0xffffdc1b0200a986 */
/* 0x0001e8000c101906 */
/*0700*/ @!P2 STG.E [R2.64+-0x28], R25 ; /* 0xffffd8190200a986 */
/* 0x000fe2000c101906 */
/*0710*/ @!P2 IMAD.MOV.U32 R27, RZ, RZ, R25 ; /* 0x000000ffff1ba224 */
/* 0x001fca00078e0019 */
/*0720*/ ISETP.GE.AND P1, PT, R27, R29, PT ; /* 0x0000001d1b00720c */
/* 0x000fda0003f26270 */
/*0730*/ @!P1 STG.E [R2.64+-0x28], R29 ; /* 0xffffd81d02009986 */
/* 0x0001e8000c101906 */
/*0740*/ @!P1 STG.E [R2.64+-0x2c], R27 ; /* 0xffffd41b02009986 */
/* 0x000fe2000c101906 */
/*0750*/ @!P1 IMAD.MOV.U32 R29, RZ, RZ, R27 ; /* 0x000000ffff1d9224 */
/* 0x001fca00078e001b */
/*0760*/ ISETP.GE.AND P2, PT, R29, R6, PT ; /* 0x000000061d00720c */
/* 0x000fda0003f46270 */
/*0770*/ @!P2 STG.E [R2.64+-0x2c], R6 ; /* 0xffffd4060200a986 */
/* 0x0001e8000c101906 */
/*0780*/ @!P2 STG.E [R2.64+-0x30], R29 ; /* 0xffffd01d0200a986 */
/* 0x000fe2000c101906 */
/*0790*/ @!P2 IMAD.MOV.U32 R6, RZ, RZ, R29 ; /* 0x000000ffff06a224 */
/* 0x001fca00078e001d */
/*07a0*/ ISETP.GE.AND P1, PT, R6, R10, PT ; /* 0x0000000a0600720c */
/* 0x000fda0003f26270 */
/*07b0*/ @!P1 STG.E [R2.64+-0x30], R10 ; /* 0xffffd00a02009986 */
/* 0x0001e8000c101906 */
/*07c0*/ @!P1 STG.E [R2.64+-0x34], R6 ; /* 0xffffcc0602009986 */
/* 0x000fe2000c101906 */
/*07d0*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a9224 */
/* 0x001fca00078e0006 */
/*07e0*/ ISETP.GE.AND P2, PT, R10, R12, PT ; /* 0x0000000c0a00720c */
/* 0x000fda0003f46270 */
/*07f0*/ @!P2 STG.E [R2.64+-0x34], R12 ; /* 0xffffcc0c0200a986 */
/* 0x0001e8000c101906 */
/*0800*/ @!P2 STG.E [R2.64+-0x38], R10 ; /* 0xffffc80a0200a986 */
/* 0x000fe2000c101906 */
/*0810*/ @!P2 IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0ca224 */
/* 0x001fe200078e000a */
/*0820*/ ISETP.GT.AND P2, PT, R8, 0x10, PT ; /* 0x000000100800780c */
/* 0x000fc80003f44270 */
/*0830*/ ISETP.GE.AND P1, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x004fda0003f26270 */
/*0840*/ @!P1 STG.E [R2.64+-0x38], R5 ; /* 0xffffc80502009986 */
/* 0x0001e8000c101906 */
/*0850*/ @!P1 STG.E [R2.64+-0x3c], R12 ; /* 0xffffc40c02009986 */
/* 0x0003e2000c101906 */
/*0860*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff059224 */
/* 0x001fe400078e000c */
/*0870*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x002fe400078e0007 */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000e */
/*0890*/ @P2 BRA 0x330 ; /* 0xfffffa9000002947 */
/* 0x000fea000383ffff */
/*08a0*/ IADD3 R9, R8, -0x4, RZ ; /* 0xfffffffc08097810 */
/* 0x000fc80007ffe0ff */
/*08b0*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*08c0*/ @!P1 BRA 0xbb0 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*08d0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x000ea8000c1e1900 */
/*08e0*/ LDG.E R13, [R2.64+-0x4] ; /* 0xfffffc06020d7981 */
/* 0x000ee8000c1e1900 */
/*08f0*/ LDG.E R15, [R2.64+-0x8] ; /* 0xfffff806020f7981 */
/* 0x000f28000c1e1900 */
/*0900*/ LDG.E R17, [R2.64+-0xc] ; /* 0xfffff40602117981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R19, [R2.64+-0x10] ; /* 0xfffff00602137981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IADD3 R6, P2, R2, -0x10, RZ ; /* 0xfffffff002067810 */
/* 0x001fc80007f5e0ff */
/*0930*/ IADD3.X R7, R3, -0x1, RZ, P2, !PT ; /* 0xffffffff03077810 */
/* 0x000fe400017fe4ff */
/*0940*/ ISETP.GE.AND P0, PT, R5, R11, PT ; /* 0x0000000b0500720c */
/* 0x024fda0003f06270 */
/*0950*/ @!P0 STG.E [R2.64+0x4], R11 ; /* 0x0000040b02008986 */
/* 0x0001e8000c101906 */
/*0960*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x000fe2000c101906 */
/*0970*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b8224 */
/* 0x001fca00078e0005 */
/*0980*/ ISETP.GE.AND P1, PT, R11, R13, PT ; /* 0x0000000d0b00720c */
/* 0x008fda0003f26270 */
/*0990*/ @!P1 STG.E [R2.64], R13 ; /* 0x0000000d02009986 */
/* 0x0001e8000c101906 */
/*09a0*/ @!P1 STG.E [R2.64+-0x4], R11 ; /* 0xfffffc0b02009986 */
/* 0x000fe2000c101906 */
/*09b0*/ @!P1 IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d9224 */
/* 0x001fca00078e000b */
/*09c0*/ ISETP.GE.AND P0, PT, R13, R15, PT ; /* 0x0000000f0d00720c */
/* 0x010fda0003f06270 */
/*09d0*/ @!P0 STG.E [R2.64+-0x4], R15 ; /* 0xfffffc0f02008986 */
/* 0x0001e8000c101906 */
/*09e0*/ @!P0 STG.E [R2.64+-0x8], R13 ; /* 0xfffff80d02008986 */
/* 0x000fe2000c101906 */
/*09f0*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f8224 */
/* 0x001fca00078e000d */
/*0a00*/ ISETP.GE.AND P1, PT, R15, R17, PT ; /* 0x000000110f00720c */
/* 0x000fda0003f26270 */
/*0a10*/ @!P1 STG.E [R2.64+-0x8], R17 ; /* 0xfffff81102009986 */
/* 0x0001e8000c101906 */
/*0a20*/ @!P1 STG.E [R2.64+-0xc], R15 ; /* 0xfffff40f02009986 */
/* 0x000fe2000c101906 */
/*0a30*/ @!P1 IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff119224 */
/* 0x001fca00078e000f */
/*0a40*/ ISETP.GE.AND P0, PT, R17, R19, PT ; /* 0x000000131100720c */
/* 0x000fda0003f06270 */
/*0a50*/ @!P0 STG.E [R2.64+-0xc], R19 ; /* 0xfffff41302008986 */
/* 0x0001e8000c101906 */
/*0a60*/ @!P0 STG.E [R2.64+-0x10], R17 ; /* 0xfffff01102008986 */
/* 0x000fe8000c101906 */
/*0a70*/ LDG.E R11, [R6.64+-0x4] ; /* 0xfffffc06060b7981 */
/* 0x000ea8000c1e1900 */
/*0a80*/ LDG.E R10, [R6.64+-0x8] ; /* 0xfffff806060a7981 */
/* 0x000ee8000c1e1900 */
/*0a90*/ LDG.E R5, [R6.64+-0xc] ; /* 0xfffff40606057981 */
/* 0x000f22000c1e1900 */
/*0aa0*/ @!P0 IMAD.MOV.U32 R19, RZ, RZ, R17 ; /* 0x000000ffff138224 */
/* 0x001fe200078e0011 */
/*0ab0*/ IADD3 R8, R9, -0x4, RZ ; /* 0xfffffffc09087810 */
/* 0x000fc80007ffe0ff */
/*0ac0*/ ISETP.GE.AND P0, PT, R19, R11, PT ; /* 0x0000000b1300720c */
/* 0x004fda0003f06270 */
/*0ad0*/ @!P0 STG.E [R6.64], R11 ; /* 0x0000000b06008986 */
/* 0x0001e8000c101906 */
/*0ae0*/ @!P0 STG.E [R6.64+-0x4], R19 ; /* 0xfffffc1306008986 */
/* 0x000fe2000c101906 */
/*0af0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b8224 */
/* 0x001fe200078e0013 */
/*0b00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0b10*/ ISETP.GE.AND P1, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x008fda0003f26270 */
/*0b20*/ @!P1 STG.E [R6.64+-0x4], R10 ; /* 0xfffffc0a06009986 */
/* 0x0001e8000c101906 */
/*0b30*/ @!P1 STG.E [R6.64+-0x8], R11 ; /* 0xfffff80b06009986 */
/* 0x000fe2000c101906 */
/*0b40*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a9224 */
/* 0x001fe200078e000b */
/*0b50*/ IADD3 R2, P1, R6, -0x10, RZ ; /* 0xfffffff006027810 */
/* 0x000fc80007f3e0ff */
/*0b60*/ ISETP.GE.AND P2, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x010fe40003f46270 */
/*0b70*/ IADD3.X R3, R7, -0x1, RZ, P1, !PT ; /* 0xffffffff07037810 */
/* 0x000fd60000ffe4ff */
/*0b80*/ @!P2 STG.E [R6.64+-0xc], R10 ; /* 0xfffff40a0600a986 */
/* 0x000fe8000c101906 */
/*0b90*/ @!P2 STG.E [R6.64+-0x8], R5 ; /* 0xfffff8050600a986 */
/* 0x0001e4000c101906 */
/*0ba0*/ @!P2 IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff05a224 */
/* 0x001fe400078e000a */
/*0bb0*/ ISETP.GT.OR P0, PT, R8, 0x4, P0 ; /* 0x000000040800780c */
/* 0x000fda0000704670 */
/*0bc0*/ @!P0 BRA 0xd00 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x001ea8000c1e1900 */
/*0be0*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0602097981 */
/* 0x000ee8000c1e1900 */
/*0bf0*/ LDG.E R11, [R2.64+-0x8] ; /* 0xfffff806020b7981 */
/* 0x000f28000c1e1900 */
/*0c00*/ LDG.E R6, [R2.64+-0xc] ; /* 0xfffff40602067981 */
/* 0x000ee2000c1e1900 */
/*0c10*/ ISETP.GE.AND P0, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x024fda0003f06270 */
/*0c20*/ @!P0 STG.E [R2.64+0x4], R7 ; /* 0x0000040702008986 */
/* 0x0001e8000c101906 */
/*0c30*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x000fe2000c101906 */
/*0c40*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff078224 */
/* 0x001fca00078e0005 */
/*0c50*/ ISETP.GE.AND P1, PT, R7, R9, PT ; /* 0x000000090700720c */
/* 0x008fda0003f26270 */
/*0c60*/ @!P1 STG.E [R2.64], R9 ; /* 0x0000000902009986 */
/* 0x0001e8000c101906 */
/*0c70*/ @!P1 STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702009986 */
/* 0x000fe2000c101906 */
/*0c80*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff099224 */
/* 0x001fca00078e0007 */
/*0c90*/ ISETP.GE.AND P0, PT, R9, R11, PT ; /* 0x0000000b0900720c */
/* 0x010fda0003f06270 */
/*0ca0*/ @!P0 STG.E [R2.64+-0x4], R11 ; /* 0xfffffc0b02008986 */
/* 0x0001e8000c101906 */
/*0cb0*/ @!P0 STG.E [R2.64+-0x8], R9 ; /* 0xfffff80902008986 */
/* 0x0003e2000c101906 */
/*0cc0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b8224 */
/* 0x001fca00078e0009 */
/*0cd0*/ ISETP.GE.AND P1, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x000fda0003f26270 */
/*0ce0*/ @!P1 STG.E [R2.64+-0x8], R6 ; /* 0xfffff80602009986 */
/* 0x0003e8000c101906 */
/*0cf0*/ @!P1 STG.E [R2.64+-0xc], R11 ; /* 0xfffff40b02009986 */
/* 0x0003e4000c101906 */
/*0d00*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0d10*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x020fc600078e0004 */
/*0d20*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0d30*/ @!P0 BRA 0xa0 ; /* 0xfffff36000008947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19cuda_insertion_sortPii
.globl _Z19cuda_insertion_sortPii
.p2align 8
.type _Z19cuda_insertion_sortPii,@function
_Z19cuda_insertion_sortPii:
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s5, 2
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 2
s_cbranch_scc1 .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s6, 1
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s6, s6, 1
s_add_i32 s5, s5, 1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s6, s4
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_mov_b64 s[2:3], s[0:1]
s_mov_b32 s7, s5
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_add_i32 s7, s7, -1
s_add_u32 s2, s2, -4
s_addc_u32 s3, s3, -1
s_cmp_lt_i32 s7, 2
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[2:3] offset:-4
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v1, v2
s_cbranch_vccnz .LBB0_4
s_clause 0x1
global_store_b32 v0, v2, s[2:3]
global_store_b32 v0, v1, s[2:3] offset:-4
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19cuda_insertion_sortPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19cuda_insertion_sortPii, .Lfunc_end0-_Z19cuda_insertion_sortPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19cuda_insertion_sortPii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z19cuda_insertion_sortPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007a484_00000000-6_insertion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14generate_arrayi
.type _Z14generate_arrayi, @function
_Z14generate_arrayi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
subl $1, %ebx
js .L3
movl %ebx, %edi
movq %rax, %rdx
.L5:
movl %edi, (%rdx)
subl $1, %edi
addq $4, %rdx
cmpl $-1, %edi
jne .L5
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z14generate_arrayi, .-_Z14generate_arrayi
.globl _Z40__device_stub__Z19cuda_insertion_sortPiiPii
.type _Z40__device_stub__Z19cuda_insertion_sortPiiPii, @function
_Z40__device_stub__Z19cuda_insertion_sortPiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19cuda_insertion_sortPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z19cuda_insertion_sortPiiPii, .-_Z40__device_stub__Z19cuda_insertion_sortPiiPii
.globl _Z19cuda_insertion_sortPii
.type _Z19cuda_insertion_sortPii, @function
_Z19cuda_insertion_sortPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19cuda_insertion_sortPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z19cuda_insertion_sortPii, .-_Z19cuda_insertion_sortPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate memory for array (error code %s)!\n"
.align 8
.LC1:
.string "Failed to copy array from host to device (error code %s)!\n"
.align 8
.LC2:
.string "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n"
.align 8
.LC3:
.string "Failed to copy array from device to host (error code %s)!\n"
.align 8
.LC4:
.string "Failed to free device array (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%ld%03ld"
.text
.globl _Z18run_insertion_sorti
.type _Z18run_insertion_sorti, @function
_Z18run_insertion_sorti:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _Z14generate_arrayi
movq %rax, %rbp
movq $0, 8(%rsp)
movslq %r12d, %rbx
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L27
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L19:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %r12
subq 32(%rsp), %r12
movq 56(%rsp), %rbx
subq 40(%rsp), %rbx
js .L30
.L21:
testl %r13d, %r13d
jne .L31
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L32
movq %rbp, %rdi
call free@PLT
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movabsq $2361183241434822607, %rdx
movq %rbx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rbx
subq %rbx, %rdx
movq %rdx, %r9
movq %r12, %r8
leaq .LC5(%rip), %rcx
movl $100, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L33
movq %rbp, %rax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z19cuda_insertion_sortPiiPii
jmp .L19
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
subq $1, %r12
addq $1000000, %rbx
jmp .L21
.L31:
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z18run_insertion_sorti, .-_Z18run_insertion_sorti
.section .rodata.str1.1
.LC6:
.string "w"
.LC7:
.string "cuda_insertion.txt"
.LC8:
.string "%d "
.LC9:
.string "%s "
.LC10:
.string "\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Failed to deinitialize the device! error=%s\n"
.section .rodata.str1.1
.LC12:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC6(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl $1000, %ebx
leaq .LC8(%rip), %r15
leaq .LC9(%rip), %r14
leaq .LC10(%rip), %r13
.L35:
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call _Z18run_insertion_sorti
movq %rax, %rbp
movq %rax, %rcx
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1000, %ebx
cmpl $11000, %ebx
jne .L35
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L39
movq %r12, %rdi
call fflush@PLT
movq %r12, %rdi
call fclose@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z19cuda_insertion_sortPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cuda_insertion_sortPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "insertion.hip"
.globl _Z34__device_stub__cuda_insertion_sortPii # -- Begin function _Z34__device_stub__cuda_insertion_sortPii
.p2align 4, 0x90
.type _Z34__device_stub__cuda_insertion_sortPii,@function
_Z34__device_stub__cuda_insertion_sortPii: # @_Z34__device_stub__cuda_insertion_sortPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19cuda_insertion_sortPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__cuda_insertion_sortPii, .Lfunc_end0-_Z34__device_stub__cuda_insertion_sortPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
addl $1000, %ebp # imm = 0x3E8
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %esi
movq %rbx, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq _Z18run_insertion_sorti
movq %rax, %r14
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $.L.str.3, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movq stdout(%rip), %rdi
callq fflush
movq %r14, %rdi
callq free
movl $10, %edi
callq putchar@PLT
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
cmpl $10000, %ebp # imm = 0x2710
jb .LBB1_1
# %bb.2:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq %rbx, %rdi
callq fflush
movq %rbx, %rdi
callq fclose
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z18run_insertion_sorti # -- Begin function _Z18run_insertion_sorti
.p2align 4, 0x90
.type _Z18run_insertion_sorti,@function
_Z18run_insertion_sorti: # @_Z18run_insertion_sorti
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader.i
movl %ebp, %ecx
movq %rbx, %rax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq -1(%rcx), %rdx
movl %edx, (%rax)
addq $4, %rax
cmpq $1, %rcx
movq %rdx, %rcx
jg .LBB2_2
.LBB2_3: # %_Z14generate_arrayi.exit
movq $0, (%rsp)
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.6:
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_7
# %bb.8:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq (%rsp), %rax
movq %rax, 80(%rsp)
movl %ebp, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z19cuda_insertion_sortPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_11
# %bb.12:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl %eax, %ebp
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
jne .LBB2_13
# %bb.14:
movq 16(%rsp), %r12
movq 24(%rsp), %r14
movq 88(%rsp), %r13
movq 96(%rsp), %r15
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_15
# %bb.16:
subq %r15, %r14
leaq 1000000(%r14), %r15
testq %r14, %r14
cmovnsq %r14, %r15
subq %r13, %r12
sarq $63, %r14
addq %r12, %r14
movq %rbx, %rdi
callq free
movl $100, %edi
callq malloc
movq %rax, %rbx
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
movq %r15, %rax
imulq %rcx
movq %rdx, %rcx
shrq $63, %rcx
sarq $7, %rdx
addq %rdx, %rcx
movl $.L.str.12, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq sprintf
movq %rbx, %rax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB2_5
.LBB2_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB2_5
.LBB2_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB2_5
.LBB2_13:
movq stderr(%rip), %rbx
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB2_5
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
.LBB2_5:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z18run_insertion_sorti, .Lfunc_end2-_Z18run_insertion_sorti
.cfi_endproc
# -- End function
.globl _Z14generate_arrayi # -- Begin function _Z14generate_arrayi
.p2align 4, 0x90
.type _Z14generate_arrayi,@function
_Z14generate_arrayi: # @_Z14generate_arrayi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movslq %edi, %r14
leaq (,%r14,4), %rdi
callq malloc
testl %r14d, %r14d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %edx
movq %rax, %rcx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq -1(%rdx), %rsi
movl %esi, (%rcx)
addq $4, %rcx
cmpq $1, %rdx
movq %rsi, %rdx
jg .LBB3_2
.LBB3_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14generate_arrayi, .Lfunc_end3-_Z14generate_arrayi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19cuda_insertion_sortPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19cuda_insertion_sortPii,@object # @_Z19cuda_insertion_sortPii
.section .rodata,"a",@progbits
.globl _Z19cuda_insertion_sortPii
.p2align 3, 0x0
_Z19cuda_insertion_sortPii:
.quad _Z34__device_stub__cuda_insertion_sortPii
.size _Z19cuda_insertion_sortPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cuda_insertion.txt"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s "
.size .L.str.3, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.5, 45
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate memory for array (error code %s)!\n"
.size .L.str.7, 54
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to copy array from host to device (error code %s)!\n"
.size .L.str.8, 59
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to launch `cuda_insertion_sort` kernel (error code %s)!\n"
.size .L.str.9, 64
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to copy array from device to host (error code %s)!\n"
.size .L.str.10, 59
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to free device array (error code %s)!\n"
.size .L.str.11, 46
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%ld%03ld"
.size .L.str.12, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19cuda_insertion_sortPii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__cuda_insertion_sortPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19cuda_insertion_sortPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kTransposeBig(float *odata, float *idata, int height, int width) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
int r, c;
for (unsigned int i = idx; i < width * height; i += numThreads) {
r = i % width;
c = i / width;
odata[i] = idata[height * r + c];
}
} | code for sm_80
Function : _Z13kTransposeBigPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F.U32.RP R4, c[0x0][0x174] ; /* 0x00005d0000047b06 */
/* 0x000e220000209000 */
/*0090*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe20003f05070 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LOP3.LUT R9, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff097a12 */
/* 0x000fca00078e33ff */
/*00c0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00d0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0100*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*0110*/ IMAD R7, R7, c[0x0][0x174], RZ ; /* 0x00005d0007077a24 */
/* 0x000fc800078e02ff */
/*0120*/ IMAD.HI.U32 R7, R3, R7, R2 ; /* 0x0000000703077227 */
/* 0x000fcc00078e0002 */
/*0130*/ IMAD.HI.U32 R2, R7, R0, RZ ; /* 0x0000000007027227 */
/* 0x000fe200078e00ff */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x001fc800000001ff */
/*0150*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0160*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fca00078e0200 */
/*0170*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, -c[0x0][0x174], RZ ; /* 0x80005d0003031a10 */
/* 0x000fe40007ffe0ff */
/*0190*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P2, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fda0003f46070 */
/*01b0*/ @P2 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102022810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ SEL R2, R9, R2, !P0 ; /* 0x0000000209027207 */
/* 0x000fca0004000000 */
/*01d0*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*01e0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*01f0*/ IMAD R3, R3, c[0x0][0x170], R2 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0202 */
/*0200*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0204 */
/*0210*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IMAD.WIDE.U32 R4, R0, R4, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0004 */
/*0230*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*0250*/ ISETP.GE.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf26070 */
/*0260*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041d8000c101906 */
/*0270*/ @!P1 BRA 0x130 ; /* 0xfffffeb000009947 */
/* 0x000fea000383ffff */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kTransposeBig(float *odata, float *idata, int height, int width) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
int r, c;
for (unsigned int i = idx; i < width * height; i += numThreads) {
r = i % width;
c = i / width;
odata[i] = idata[height * r + c];
}
} | .file "tmpxft_000de68a_00000000-6_kTransposeBig.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii
.type _Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii, @function
_Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kTransposeBigPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii, .-_Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii
.globl _Z13kTransposeBigPfS_ii
.type _Z13kTransposeBigPfS_ii, @function
_Z13kTransposeBigPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kTransposeBigPfS_ii, .-_Z13kTransposeBigPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kTransposeBigPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kTransposeBigPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kTransposeBig(float *odata, float *idata, int height, int width) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
int r, c;
for (unsigned int i = idx; i < width * height; i += numThreads) {
r = i % width;
c = i / width;
odata[i] = idata[height * r + c];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kTransposeBig(float *odata, float *idata, int height, int width) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
int r, c;
for (unsigned int i = idx; i < width * height; i += numThreads) {
r = i % width;
c = i / width;
odata[i] = idata[height * r + c];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kTransposeBig(float *odata, float *idata, int height, int width) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
int r, c;
for (unsigned int i = idx; i < width * height; i += numThreads) {
r = i % width;
c = i / width;
odata[i] = idata[height * r + c];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kTransposeBigPfS_ii
.globl _Z13kTransposeBigPfS_ii
.p2align 8
.type _Z13kTransposeBigPfS_ii,@function
_Z13kTransposeBigPfS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mul_i32 s8, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s9, 0, s3
s_load_b32 s11, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s11, s10
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s9, v0
v_mul_hi_u32 v3, v0, v2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v1, v0
v_mad_u64_u32 v[3:4], null, s9, v6, v[1:2]
v_not_b32_e32 v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, s3, v7, v[1:2]
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v4 :: v_dual_add_nc_u32 v8, 1, v6
v_cndmask_b32_e32 v5, v6, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_add_nc_u32_e32 v4, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v5, v4, vcc_lo
v_mad_u64_u32 v[4:5], null, s9, v3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v4, s2, v[3:4]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[5:6]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v5, v[3:4], off
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_u32_e64 s0, s8, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s10, s0, s10
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kTransposeBigPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kTransposeBigPfS_ii, .Lfunc_end0-_Z13kTransposeBigPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kTransposeBigPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kTransposeBigPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kTransposeBig(float *odata, float *idata, int height, int width) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
int r, c;
for (unsigned int i = idx; i < width * height; i += numThreads) {
r = i % width;
c = i / width;
odata[i] = idata[height * r + c];
}
} | .text
.file "kTransposeBig.hip"
.globl _Z28__device_stub__kTransposeBigPfS_ii # -- Begin function _Z28__device_stub__kTransposeBigPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__kTransposeBigPfS_ii,@function
_Z28__device_stub__kTransposeBigPfS_ii: # @_Z28__device_stub__kTransposeBigPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kTransposeBigPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__kTransposeBigPfS_ii, .Lfunc_end0-_Z28__device_stub__kTransposeBigPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kTransposeBigPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kTransposeBigPfS_ii,@object # @_Z13kTransposeBigPfS_ii
.section .rodata,"a",@progbits
.globl _Z13kTransposeBigPfS_ii
.p2align 3, 0x0
_Z13kTransposeBigPfS_ii:
.quad _Z28__device_stub__kTransposeBigPfS_ii
.size _Z13kTransposeBigPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kTransposeBigPfS_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kTransposeBigPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kTransposeBigPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13kTransposeBigPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F.U32.RP R4, c[0x0][0x174] ; /* 0x00005d0000047b06 */
/* 0x000e220000209000 */
/*0090*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe20003f05070 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LOP3.LUT R9, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff097a12 */
/* 0x000fca00078e33ff */
/*00c0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00d0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0100*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*0110*/ IMAD R7, R7, c[0x0][0x174], RZ ; /* 0x00005d0007077a24 */
/* 0x000fc800078e02ff */
/*0120*/ IMAD.HI.U32 R7, R3, R7, R2 ; /* 0x0000000703077227 */
/* 0x000fcc00078e0002 */
/*0130*/ IMAD.HI.U32 R2, R7, R0, RZ ; /* 0x0000000007027227 */
/* 0x000fe200078e00ff */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x001fc800000001ff */
/*0150*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0160*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fca00078e0200 */
/*0170*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, -c[0x0][0x174], RZ ; /* 0x80005d0003031a10 */
/* 0x000fe40007ffe0ff */
/*0190*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P2, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fda0003f46070 */
/*01b0*/ @P2 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102022810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ SEL R2, R9, R2, !P0 ; /* 0x0000000209027207 */
/* 0x000fca0004000000 */
/*01d0*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*01e0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*01f0*/ IMAD R3, R3, c[0x0][0x170], R2 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0202 */
/*0200*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0204 */
/*0210*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IMAD.WIDE.U32 R4, R0, R4, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0004 */
/*0230*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*0250*/ ISETP.GE.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf26070 */
/*0260*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041d8000c101906 */
/*0270*/ @!P1 BRA 0x130 ; /* 0xfffffeb000009947 */
/* 0x000fea000383ffff */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kTransposeBigPfS_ii
.globl _Z13kTransposeBigPfS_ii
.p2align 8
.type _Z13kTransposeBigPfS_ii,@function
_Z13kTransposeBigPfS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mul_i32 s8, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s9, 0, s3
s_load_b32 s11, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s11, s10
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s9, v0
v_mul_hi_u32 v3, v0, v2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v1, v0
v_mad_u64_u32 v[3:4], null, s9, v6, v[1:2]
v_not_b32_e32 v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, s3, v7, v[1:2]
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v4 :: v_dual_add_nc_u32 v8, 1, v6
v_cndmask_b32_e32 v5, v6, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_add_nc_u32_e32 v4, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v5, v4, vcc_lo
v_mad_u64_u32 v[4:5], null, s9, v3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v4, s2, v[3:4]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[5:6]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v5, v[3:4], off
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_u32_e64 s0, s8, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s10, s0, s10
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kTransposeBigPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kTransposeBigPfS_ii, .Lfunc_end0-_Z13kTransposeBigPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kTransposeBigPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kTransposeBigPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000de68a_00000000-6_kTransposeBig.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii
.type _Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii, @function
_Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kTransposeBigPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii, .-_Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii
.globl _Z13kTransposeBigPfS_ii
.type _Z13kTransposeBigPfS_ii, @function
_Z13kTransposeBigPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13kTransposeBigPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kTransposeBigPfS_ii, .-_Z13kTransposeBigPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kTransposeBigPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kTransposeBigPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kTransposeBig.hip"
.globl _Z28__device_stub__kTransposeBigPfS_ii # -- Begin function _Z28__device_stub__kTransposeBigPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__kTransposeBigPfS_ii,@function
_Z28__device_stub__kTransposeBigPfS_ii: # @_Z28__device_stub__kTransposeBigPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kTransposeBigPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__kTransposeBigPfS_ii, .Lfunc_end0-_Z28__device_stub__kTransposeBigPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kTransposeBigPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kTransposeBigPfS_ii,@object # @_Z13kTransposeBigPfS_ii
.section .rodata,"a",@progbits
.globl _Z13kTransposeBigPfS_ii
.p2align 3, 0x0
_Z13kTransposeBigPfS_ii:
.quad _Z28__device_stub__kTransposeBigPfS_ii
.size _Z13kTransposeBigPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kTransposeBigPfS_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kTransposeBigPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kTransposeBigPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<ctime>
#include<cmath>
#include<stdexcept>
using namespace std;
#define MaxElement 1000
__global__ void Sum(int* Array1, int* Array2, int* Result, int ElementCount){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index < ElementCount)
Result[Index] = Array1[Index] + Array2[Index];
}
void HostVectorSum(int ArraySize=1000, int ThreadsPerBlock=100){
int ArrayMemory = ArraySize * sizeof(int);
int* HostArray1 = (int*) malloc(ArrayMemory);
int* HostArray2 = (int*) malloc(ArrayMemory);
int* HostResult = (int*) malloc(ArrayMemory);
int* DeviceArray1;
int* DeviceArray2;
int* DeviceResult;
srand(time(0));
for(int i=0;i<ArraySize;i++){
HostArray1[i] = rand() % MaxElement;
HostArray2[i] = rand() % MaxElement;
}
cudaMalloc(&DeviceArray1, ArrayMemory);
cudaMalloc(&DeviceArray2, ArrayMemory);
cudaMalloc(&DeviceResult, ArrayMemory);
cudaMemcpy(DeviceArray1, HostArray1, ArrayMemory, cudaMemcpyHostToDevice);
cudaMemcpy(DeviceArray2, HostArray2, ArrayMemory, cudaMemcpyHostToDevice);
int BlocksPerGrid = 1;
if(ArraySize > ThreadsPerBlock)
BlocksPerGrid = ceil(double(ArraySize) / double(ThreadsPerBlock));
Sum<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceArray1, DeviceArray2, DeviceResult, ArraySize);
cudaMemcpy(HostResult, DeviceResult, ArrayMemory, cudaMemcpyDeviceToHost);
cudaFree(DeviceArray1);
cudaFree(DeviceArray2);
cudaFree(DeviceResult);
for(int i=0;i<ArraySize;i++)
printf("Index %d --> %d + %d = %d\n", i+1, HostArray1[i], HostArray2[i], HostResult[i]);
free(HostArray1);
free(HostArray2);
free(HostResult);
}
__global__ void VectorMatrixMultiplication(int* Vector, int* Matrix, int* Result, int Row, int Column){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Index < Column){
int ColumnStartIndex = Index * Row;
for(int i=0;i<Row;i++)
Sum += Vector[i] * Matrix[ColumnStartIndex + i];
Result[Index] = Sum;
}
}
void HostVectorMatrixMultiplication(int Row, int Column){
int* HostArray = (int*) malloc(Row * sizeof(int));
int* HostMatrix = (int*) malloc(Row * Column * sizeof(int));
int* HostResult = (int*) malloc(Column * sizeof(int));
int* DeviceArray;
int* DeviceMatrix;
int* DeviceResult;
srand(time(0));
for(int i=0;i<Row;i++)
HostArray[i] = rand() % MaxElement;
for(int i=0;i<Column;i++)
for(int j=0;j<Row;j++)
HostMatrix[i*Row+j] = rand() % MaxElement;
cudaMalloc(&DeviceArray, Row*sizeof(int));
cudaMalloc(&DeviceMatrix, Row*Column*sizeof(int));
cudaMalloc(&DeviceResult, Column*sizeof(int));
cudaMemcpy(DeviceArray, HostArray, Row*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(DeviceMatrix, HostMatrix, Row*Column*sizeof(int), cudaMemcpyHostToDevice);
VectorMatrixMultiplication<<<Column, 1>>>(DeviceArray, DeviceMatrix, DeviceResult, Row, Column);
cudaMemcpy(HostResult, DeviceResult, Column*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(DeviceArray);
cudaFree(DeviceMatrix);
cudaFree(DeviceResult);
for(int i=0;i<Column;i++)
printf("Index %d --> %d\n", i+1,HostResult[i]);
free(HostArray);
free(HostMatrix);
free(HostResult);
}
__global__ void MatrixMultiplication(int* MatrixA, int* MatrixB, int* Result, int Dimension){
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Column = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Row < Dimension && Column < Dimension){
for(int i=0;i<Dimension;i++)
Sum += MatrixA[Row * Dimension + i] * MatrixB[i * Dimension + Column];
__syncthreads();
Result[Row * Dimension + Column] = Sum;
}
}
void HostMatrixMultiplication(int Dimension){
int MatrixMemory = Dimension * Dimension * sizeof(int);
int* HostMatrixA = (int*) malloc(MatrixMemory);
int* HostMatrixB = (int*) malloc(MatrixMemory);
int* HostResult = (int*) malloc(MatrixMemory);
srand(time(0));
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
HostMatrixA[i * Dimension + j] = rand() % 30;
HostMatrixB[i * Dimension + j] = rand() % 30;
}
}
int* DeviceMatrixA;
int* DeviceMatrixB;
int* DeviceResult;
cudaMalloc(&DeviceMatrixA, MatrixMemory);
cudaMalloc(&DeviceMatrixB, MatrixMemory);
cudaMalloc(&DeviceResult, MatrixMemory);
cudaMemcpy(DeviceMatrixA, HostMatrixA, MatrixMemory, cudaMemcpyHostToDevice);
cudaMemcpy(DeviceMatrixB, HostMatrixB, MatrixMemory, cudaMemcpyHostToDevice);
dim3 ThreadsPerBlock(Dimension, Dimension);
dim3 BlocksPerGrid(1, 1);
MatrixMultiplication<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceMatrixA, DeviceMatrixB, DeviceResult, Dimension);
cudaError_t Exception = cudaGetLastError();
if(Exception != cudaSuccess){
printf("Cuda Error: %s", cudaGetErrorString(Exception));
return;
}
cudaDeviceSynchronize();
cudaMemcpy(HostResult, DeviceResult, MatrixMemory, cudaMemcpyDeviceToHost);
cudaFree(DeviceMatrixA);
cudaFree(DeviceMatrixB);
cudaFree(DeviceResult);
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
printf("%d ", HostResult[i * Dimension + j]);
}
printf("\n");
}
}
int main(){
int Choice;
printf("1.Vector Addition\n2.Vector Matrix Multiplication\n3.Matrix Multiplication\n4.Exit\n");
printf("Enter The Operation To Be Performed: : ");
scanf("%d", &Choice);
if(Choice==1){
int ArraySize;
printf("Enter The Array Size: : ");
scanf("%d", &ArraySize);
HostVectorSum(ArraySize);
}
else if(Choice==2){
int Row, Column;
printf("Enter The Rows And Columns Of The Matrix: : ");
scanf("%d %d", &Row, &Column);
HostVectorMatrixMultiplication(Row, Column);
}
else if(Choice==3){
int Dimension;
printf("Enter The Dimensions Of The Matrix: : ");
scanf("%d", &Dimension);
HostMatrixMultiplication(Dimension);
}
else
return 0;
return 0;
} | .file "tmpxft_001b110c_00000000-6_Assignment2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3SumPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3SumPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3SumPiS_S_iPiS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3SumPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z27__device_stub__Z3SumPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3SumPiS_S_iPiS_S_i
.globl _Z3SumPiS_S_i
.type _Z3SumPiS_S_i, @function
_Z3SumPiS_S_i:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3SumPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z3SumPiS_S_i, .-_Z3SumPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Index %d --> %d + %d = %d\n"
.text
.globl _Z13HostVectorSumii
.type _Z13HostVectorSumii, @function
_Z13HostVectorSumii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebx
movl %edi, 24(%rsp)
movl %esi, 28(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %edi, %rax
movq %rax, 8(%rsp)
leal 0(,%rdi,4), %eax
movslq %eax, %r15
movq %r15, 16(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
jle .L12
movq %r12, %rbx
movq %r13, %rbp
movq 8(%rsp), %rax
leaq (%r12,%rax,4), %r15
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r15, %rbx
jne .L13
.L12:
leaq 40(%rsp), %rdi
movq 16(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %eax
movl 24(%rsp), %esi
movl 28(%rsp), %edi
cmpl %edi, %esi
jle .L14
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %edi, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC0(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L15
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC2(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L15:
cvttsd2sil %xmm3, %eax
.L14:
movl 28(%rsp), %esi
movl %esi, 76(%rsp)
movl $1, 80(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
movl $2, %ecx
movq 16(%rsp), %rdx
movq 56(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
cmpl $0, 24(%rsp)
jle .L17
movl $1, %ebx
leaq .LC3(%rip), %rbp
.L18:
movl -4(%r12,%rbx,4), %ecx
movl -4(%r14,%rbx,4), %r9d
movl -4(%r13,%rbx,4), %r8d
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rax
addq $1, %rbx
cmpq %rax, 8(%rsp)
jne .L18
.L17:
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl 24(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z27__device_stub__Z3SumPiS_S_iPiS_S_i
jmp .L16
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z13HostVectorSumii, .-_Z13HostVectorSumii
.globl _Z52__device_stub__Z26VectorMatrixMultiplicationPiS_S_iiPiS_S_ii
.type _Z52__device_stub__Z26VectorMatrixMultiplicationPiS_S_iiPiS_S_ii, @function
_Z52__device_stub__Z26VectorMatrixMultiplicationPiS_S_iiPiS_S_ii:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26VectorMatrixMultiplicationPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z52__device_stub__Z26VectorMatrixMultiplicationPiS_S_iiPiS_S_ii, .-_Z52__device_stub__Z26VectorMatrixMultiplicationPiS_S_iiPiS_S_ii
.globl _Z26VectorMatrixMultiplicationPiS_S_ii
.type _Z26VectorMatrixMultiplicationPiS_S_ii, @function
_Z26VectorMatrixMultiplicationPiS_S_ii:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26VectorMatrixMultiplicationPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z26VectorMatrixMultiplicationPiS_S_ii, .-_Z26VectorMatrixMultiplicationPiS_S_ii
.section .rodata.str1.1
.LC5:
.string "Index %d --> %d\n"
.text
.globl _Z30HostVectorMatrixMultiplicationii
.type _Z30HostVectorMatrixMultiplicationii, @function
_Z30HostVectorMatrixMultiplicationii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %r12d
movl %esi, %ebx
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movslq %edi, %rax
movq %rax, 8(%rsp)
leaq 0(,%rax,4), %r15
movq %r15, 32(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 24(%rsp)
movl %ebx, %eax
imull %r12d, %eax
cltq
salq $2, %rax
movq %rax, 40(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
movslq %ebx, %rax
movq %rax, 48(%rsp)
salq $2, %rax
movq %rax, 16(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %r12d, %r12d
jle .L35
movq %r14, %rbp
addq %r14, %r15
.L36:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r15, %rbp
jne .L36
.L35:
cmpl $0, 4(%rsp)
jle .L37
movl $0, %r15d
movq %rbx, 56(%rsp)
movl %r12d, %ebx
movq %r13, %r12
movl %r15d, %r13d
jmp .L38
.L40:
movslq %r15d, %rax
leaq (%r12,%rax,4), %rbp
movq 8(%rsp), %rsi
addq %rsi, %rax
leaq (%r12,%rax,4), %r14
.L39:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r14, %rbp
jne .L39
.L41:
addl $1, %r13d
addl %ebx, %r15d
cmpl %r13d, 4(%rsp)
je .L49
.L38:
testl %ebx, %ebx
jg .L40
jmp .L41
.L49:
movq %r12, %r13
movl %ebx, %r12d
movq 56(%rsp), %rbx
.L37:
leaq 72(%rsp), %rdi
movq 32(%rsp), %r14
movq %r14, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq 40(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl 4(%rsp), %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L42:
movl $2, %ecx
movq 16(%rsp), %rdx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
cmpl $0, 4(%rsp)
jle .L43
movl $1, %ebp
leaq .LC5(%rip), %r12
movq 48(%rsp), %r14
.L44:
movl -4(%rbx,%rbp,4), %ecx
movl %ebp, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rax
addq $1, %rbp
cmpq %rax, %r14
jne .L44
.L43:
movq 24(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl 4(%rsp), %r8d
movl %r12d, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z52__device_stub__Z26VectorMatrixMultiplicationPiS_S_iiPiS_S_ii
jmp .L42
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z30HostVectorMatrixMultiplicationii, .-_Z30HostVectorMatrixMultiplicationii
.globl _Z45__device_stub__Z20MatrixMultiplicationPiS_S_iPiS_S_i
.type _Z45__device_stub__Z20MatrixMultiplicationPiS_S_iPiS_S_i, @function
_Z45__device_stub__Z20MatrixMultiplicationPiS_S_iPiS_S_i:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20MatrixMultiplicationPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z45__device_stub__Z20MatrixMultiplicationPiS_S_iPiS_S_i, .-_Z45__device_stub__Z20MatrixMultiplicationPiS_S_iPiS_S_i
.globl _Z20MatrixMultiplicationPiS_S_i
.type _Z20MatrixMultiplicationPiS_S_i, @function
_Z20MatrixMultiplicationPiS_S_i:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20MatrixMultiplicationPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z20MatrixMultiplicationPiS_S_i, .-_Z20MatrixMultiplicationPiS_S_i
.section .rodata.str1.1
.LC6:
.string "Cuda Error: %s"
.LC7:
.string "%d "
.LC8:
.string "\n"
.text
.globl _Z24HostMatrixMultiplicationi
.type _Z24HostMatrixMultiplicationi, @function
_Z24HostMatrixMultiplicationi:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %r15d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl %edi, %eax
imull %edi, %eax
sall $2, %eax
movslq %eax, %rbx
movq %rbx, 32(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %r15d, %r15d
jle .L62
movslq %r15d, %rax
salq $2, %rax
movq %rax, 24(%rsp)
leaq (%rax,%r14), %r12
movl $0, %r13d
movl $0, %r14d
.L63:
movq 8(%rsp), %rax
leaq (%rax,%r13), %rbx
movq 16(%rsp), %rax
leaq (%rax,%r13), %rbp
.L64:
call rand@PLT
movslq %eax, %rdx
imulq $-2004318071, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $4, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $30, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $-2004318071, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $4, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $30, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
jne .L64
addl $1, %r14d
movq 24(%rsp), %rax
addq %rax, %r12
addq %rax, %r13
cmpl %r14d, %r15d
jne .L63
.L62:
leaq 56(%rsp), %rdi
movq 32(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 80(%rsp)
movl %r15d, 84(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L65:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L76
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq 32(%rsp), %rdx
movq 72(%rsp), %rsi
movq 40(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
testl %r15d, %r15d
jle .L61
movslq %r15d, %rax
leaq 0(,%rax,4), %r14
addq %r14, %rbp
negq %rax
salq $2, %rax
movq %rax, 8(%rsp)
movl $0, %r13d
leaq .LC7(%rip), %r12
.L69:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L70:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L70
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r14, %rbp
cmpl %r13d, %r15d
jne .L69
.L61:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
movl %r15d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z45__device_stub__Z20MatrixMultiplicationPiS_S_iPiS_S_i
jmp .L65
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L61
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z24HostMatrixMultiplicationi, .-_Z24HostMatrixMultiplicationi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "1.Vector Addition\n2.Vector Matrix Multiplication\n3.Matrix Multiplication\n4.Exit\n"
.align 8
.LC10:
.string "Enter The Operation To Be Performed: : "
.section .rodata.str1.1
.LC11:
.string "%d"
.LC12:
.string "Enter The Array Size: : "
.section .rodata.str1.8
.align 8
.LC13:
.string "Enter The Rows And Columns Of The Matrix: : "
.section .rodata.str1.1
.LC14:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC15:
.string "Enter The Dimensions Of The Matrix: : "
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC9(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC11(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %eax
cmpl $1, %eax
je .L84
cmpl $2, %eax
je .L85
cmpl $3, %eax
je .L86
.L80:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L87
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC11(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $100, %esi
movl 20(%rsp), %edi
call _Z13HostVectorSumii
jmp .L80
.L85:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 20(%rsp), %rdx
leaq 16(%rsp), %rsi
leaq .LC14(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 20(%rsp), %esi
movl 16(%rsp), %edi
call _Z30HostVectorMatrixMultiplicationii
jmp .L80
.L86:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC11(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 20(%rsp), %edi
call _Z24HostMatrixMultiplicationi
jmp .L80
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC16:
.string "_Z20MatrixMultiplicationPiS_S_i"
.align 8
.LC17:
.string "_Z26VectorMatrixMultiplicationPiS_S_ii"
.section .rodata.str1.1
.LC18:
.string "_Z3SumPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z20MatrixMultiplicationPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z26VectorMatrixMultiplicationPiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z3SumPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1127219200
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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