system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<ctime>
#include<cmath>
#include<stdexcept>
using namespace std;
#define MaxElement 1000
__global__ void Sum(int* Array1, int* Array2, int* Result, int ElementCount){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index < ElementCount)
Result[Index] = Array1[Index] + Array2[Index];
}
void HostVectorSum(int ArraySize=1000, int ThreadsPerBlock=100){
int ArrayMemory = ArraySize * sizeof(int);
int* HostArray1 = (int*) malloc(ArrayMemory);
int* HostArray2 = (int*) malloc(ArrayMemory);
int* HostResult = (int*) malloc(ArrayMemory);
int* DeviceArray1;
int* DeviceArray2;
int* DeviceResult;
srand(time(0));
for(int i=0;i<ArraySize;i++){
HostArray1[i] = rand() % MaxElement;
HostArray2[i] = rand() % MaxElement;
}
cudaMalloc(&DeviceArray1, ArrayMemory);
cudaMalloc(&DeviceArray2, ArrayMemory);
cudaMalloc(&DeviceResult, ArrayMemory);
cudaMemcpy(DeviceArray1, HostArray1, ArrayMemory, cudaMemcpyHostToDevice);
cudaMemcpy(DeviceArray2, HostArray2, ArrayMemory, cudaMemcpyHostToDevice);
int BlocksPerGrid = 1;
if(ArraySize > ThreadsPerBlock)
BlocksPerGrid = ceil(double(ArraySize) / double(ThreadsPerBlock));
Sum<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceArray1, DeviceArray2, DeviceResult, ArraySize);
cudaMemcpy(HostResult, DeviceResult, ArrayMemory, cudaMemcpyDeviceToHost);
cudaFree(DeviceArray1);
cudaFree(DeviceArray2);
cudaFree(DeviceResult);
for(int i=0;i<ArraySize;i++)
printf("Index %d --> %d + %d = %d\n", i+1, HostArray1[i], HostArray2[i], HostResult[i]);
free(HostArray1);
free(HostArray2);
free(HostResult);
}
__global__ void VectorMatrixMultiplication(int* Vector, int* Matrix, int* Result, int Row, int Column){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Index < Column){
int ColumnStartIndex = Index * Row;
for(int i=0;i<Row;i++)
Sum += Vector[i] * Matrix[ColumnStartIndex + i];
Result[Index] = Sum;
}
}
void HostVectorMatrixMultiplication(int Row, int Column){
int* HostArray = (int*) malloc(Row * sizeof(int));
int* HostMatrix = (int*) malloc(Row * Column * sizeof(int));
int* HostResult = (int*) malloc(Column * sizeof(int));
int* DeviceArray;
int* DeviceMatrix;
int* DeviceResult;
srand(time(0));
for(int i=0;i<Row;i++)
HostArray[i] = rand() % MaxElement;
for(int i=0;i<Column;i++)
for(int j=0;j<Row;j++)
HostMatrix[i*Row+j] = rand() % MaxElement;
cudaMalloc(&DeviceArray, Row*sizeof(int));
cudaMalloc(&DeviceMatrix, Row*Column*sizeof(int));
cudaMalloc(&DeviceResult, Column*sizeof(int));
cudaMemcpy(DeviceArray, HostArray, Row*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(DeviceMatrix, HostMatrix, Row*Column*sizeof(int), cudaMemcpyHostToDevice);
VectorMatrixMultiplication<<<Column, 1>>>(DeviceArray, DeviceMatrix, DeviceResult, Row, Column);
cudaMemcpy(HostResult, DeviceResult, Column*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(DeviceArray);
cudaFree(DeviceMatrix);
cudaFree(DeviceResult);
for(int i=0;i<Column;i++)
printf("Index %d --> %d\n", i+1,HostResult[i]);
free(HostArray);
free(HostMatrix);
free(HostResult);
}
__global__ void MatrixMultiplication(int* MatrixA, int* MatrixB, int* Result, int Dimension){
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Column = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Row < Dimension && Column < Dimension){
for(int i=0;i<Dimension;i++)
Sum += MatrixA[Row * Dimension + i] * MatrixB[i * Dimension + Column];
__syncthreads();
Result[Row * Dimension + Column] = Sum;
}
}
void HostMatrixMultiplication(int Dimension){
int MatrixMemory = Dimension * Dimension * sizeof(int);
int* HostMatrixA = (int*) malloc(MatrixMemory);
int* HostMatrixB = (int*) malloc(MatrixMemory);
int* HostResult = (int*) malloc(MatrixMemory);
srand(time(0));
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
HostMatrixA[i * Dimension + j] = rand() % 30;
HostMatrixB[i * Dimension + j] = rand() % 30;
}
}
int* DeviceMatrixA;
int* DeviceMatrixB;
int* DeviceResult;
cudaMalloc(&DeviceMatrixA, MatrixMemory);
cudaMalloc(&DeviceMatrixB, MatrixMemory);
cudaMalloc(&DeviceResult, MatrixMemory);
cudaMemcpy(DeviceMatrixA, HostMatrixA, MatrixMemory, cudaMemcpyHostToDevice);
cudaMemcpy(DeviceMatrixB, HostMatrixB, MatrixMemory, cudaMemcpyHostToDevice);
dim3 ThreadsPerBlock(Dimension, Dimension);
dim3 BlocksPerGrid(1, 1);
MatrixMultiplication<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceMatrixA, DeviceMatrixB, DeviceResult, Dimension);
cudaError_t Exception = cudaGetLastError();
if(Exception != cudaSuccess){
printf("Cuda Error: %s", cudaGetErrorString(Exception));
return;
}
cudaDeviceSynchronize();
cudaMemcpy(HostResult, DeviceResult, MatrixMemory, cudaMemcpyDeviceToHost);
cudaFree(DeviceMatrixA);
cudaFree(DeviceMatrixB);
cudaFree(DeviceResult);
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
printf("%d ", HostResult[i * Dimension + j]);
}
printf("\n");
}
}
int main(){
int Choice;
printf("1.Vector Addition\n2.Vector Matrix Multiplication\n3.Matrix Multiplication\n4.Exit\n");
printf("Enter The Operation To Be Performed: : ");
scanf("%d", &Choice);
if(Choice==1){
int ArraySize;
printf("Enter The Array Size: : ");
scanf("%d", &ArraySize);
HostVectorSum(ArraySize);
}
else if(Choice==2){
int Row, Column;
printf("Enter The Rows And Columns Of The Matrix: : ");
scanf("%d %d", &Row, &Column);
HostVectorMatrixMultiplication(Row, Column);
}
else if(Choice==3){
int Dimension;
printf("Enter The Dimensions Of The Matrix: : ");
scanf("%d", &Dimension);
HostMatrixMultiplication(Dimension);
}
else
return 0;
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<ctime>
#include<cmath>
#include<stdexcept>
using namespace std;
#define MaxElement 1000
__global__ void Sum(int* Array1, int* Array2, int* Result, int ElementCount){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index < ElementCount)
Result[Index] = Array1[Index] + Array2[Index];
}
void HostVectorSum(int ArraySize=1000, int ThreadsPerBlock=100){
int ArrayMemory = ArraySize * sizeof(int);
int* HostArray1 = (int*) malloc(ArrayMemory);
int* HostArray2 = (int*) malloc(ArrayMemory);
int* HostResult = (int*) malloc(ArrayMemory);
int* DeviceArray1;
int* DeviceArray2;
int* DeviceResult;
srand(time(0));
for(int i=0;i<ArraySize;i++){
HostArray1[i] = rand() % MaxElement;
HostArray2[i] = rand() % MaxElement;
}
hipMalloc(&DeviceArray1, ArrayMemory);
hipMalloc(&DeviceArray2, ArrayMemory);
hipMalloc(&DeviceResult, ArrayMemory);
hipMemcpy(DeviceArray1, HostArray1, ArrayMemory, hipMemcpyHostToDevice);
hipMemcpy(DeviceArray2, HostArray2, ArrayMemory, hipMemcpyHostToDevice);
int BlocksPerGrid = 1;
if(ArraySize > ThreadsPerBlock)
BlocksPerGrid = ceil(double(ArraySize) / double(ThreadsPerBlock));
Sum<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceArray1, DeviceArray2, DeviceResult, ArraySize);
hipMemcpy(HostResult, DeviceResult, ArrayMemory, hipMemcpyDeviceToHost);
hipFree(DeviceArray1);
hipFree(DeviceArray2);
hipFree(DeviceResult);
for(int i=0;i<ArraySize;i++)
printf("Index %d --> %d + %d = %d\n", i+1, HostArray1[i], HostArray2[i], HostResult[i]);
free(HostArray1);
free(HostArray2);
free(HostResult);
}
__global__ void VectorMatrixMultiplication(int* Vector, int* Matrix, int* Result, int Row, int Column){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Index < Column){
int ColumnStartIndex = Index * Row;
for(int i=0;i<Row;i++)
Sum += Vector[i] * Matrix[ColumnStartIndex + i];
Result[Index] = Sum;
}
}
void HostVectorMatrixMultiplication(int Row, int Column){
int* HostArray = (int*) malloc(Row * sizeof(int));
int* HostMatrix = (int*) malloc(Row * Column * sizeof(int));
int* HostResult = (int*) malloc(Column * sizeof(int));
int* DeviceArray;
int* DeviceMatrix;
int* DeviceResult;
srand(time(0));
for(int i=0;i<Row;i++)
HostArray[i] = rand() % MaxElement;
for(int i=0;i<Column;i++)
for(int j=0;j<Row;j++)
HostMatrix[i*Row+j] = rand() % MaxElement;
hipMalloc(&DeviceArray, Row*sizeof(int));
hipMalloc(&DeviceMatrix, Row*Column*sizeof(int));
hipMalloc(&DeviceResult, Column*sizeof(int));
hipMemcpy(DeviceArray, HostArray, Row*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(DeviceMatrix, HostMatrix, Row*Column*sizeof(int), hipMemcpyHostToDevice);
VectorMatrixMultiplication<<<Column, 1>>>(DeviceArray, DeviceMatrix, DeviceResult, Row, Column);
hipMemcpy(HostResult, DeviceResult, Column*sizeof(int), hipMemcpyDeviceToHost);
hipFree(DeviceArray);
hipFree(DeviceMatrix);
hipFree(DeviceResult);
for(int i=0;i<Column;i++)
printf("Index %d --> %d\n", i+1,HostResult[i]);
free(HostArray);
free(HostMatrix);
free(HostResult);
}
__global__ void MatrixMultiplication(int* MatrixA, int* MatrixB, int* Result, int Dimension){
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Column = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Row < Dimension && Column < Dimension){
for(int i=0;i<Dimension;i++)
Sum += MatrixA[Row * Dimension + i] * MatrixB[i * Dimension + Column];
__syncthreads();
Result[Row * Dimension + Column] = Sum;
}
}
void HostMatrixMultiplication(int Dimension){
int MatrixMemory = Dimension * Dimension * sizeof(int);
int* HostMatrixA = (int*) malloc(MatrixMemory);
int* HostMatrixB = (int*) malloc(MatrixMemory);
int* HostResult = (int*) malloc(MatrixMemory);
srand(time(0));
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
HostMatrixA[i * Dimension + j] = rand() % 30;
HostMatrixB[i * Dimension + j] = rand() % 30;
}
}
int* DeviceMatrixA;
int* DeviceMatrixB;
int* DeviceResult;
hipMalloc(&DeviceMatrixA, MatrixMemory);
hipMalloc(&DeviceMatrixB, MatrixMemory);
hipMalloc(&DeviceResult, MatrixMemory);
hipMemcpy(DeviceMatrixA, HostMatrixA, MatrixMemory, hipMemcpyHostToDevice);
hipMemcpy(DeviceMatrixB, HostMatrixB, MatrixMemory, hipMemcpyHostToDevice);
dim3 ThreadsPerBlock(Dimension, Dimension);
dim3 BlocksPerGrid(1, 1);
MatrixMultiplication<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceMatrixA, DeviceMatrixB, DeviceResult, Dimension);
hipError_t Exception = hipGetLastError();
if(Exception != hipSuccess){
printf("Cuda Error: %s", hipGetErrorString(Exception));
return;
}
hipDeviceSynchronize();
hipMemcpy(HostResult, DeviceResult, MatrixMemory, hipMemcpyDeviceToHost);
hipFree(DeviceMatrixA);
hipFree(DeviceMatrixB);
hipFree(DeviceResult);
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
printf("%d ", HostResult[i * Dimension + j]);
}
printf("\n");
}
}
int main(){
int Choice;
printf("1.Vector Addition\n2.Vector Matrix Multiplication\n3.Matrix Multiplication\n4.Exit\n");
printf("Enter The Operation To Be Performed: : ");
scanf("%d", &Choice);
if(Choice==1){
int ArraySize;
printf("Enter The Array Size: : ");
scanf("%d", &ArraySize);
HostVectorSum(ArraySize);
}
else if(Choice==2){
int Row, Column;
printf("Enter The Rows And Columns Of The Matrix: : ");
scanf("%d %d", &Row, &Column);
HostVectorMatrixMultiplication(Row, Column);
}
else if(Choice==3){
int Dimension;
printf("Enter The Dimensions Of The Matrix: : ");
scanf("%d", &Dimension);
HostMatrixMultiplication(Dimension);
}
else
return 0;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<ctime>
#include<cmath>
#include<stdexcept>
using namespace std;
#define MaxElement 1000
__global__ void Sum(int* Array1, int* Array2, int* Result, int ElementCount){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index < ElementCount)
Result[Index] = Array1[Index] + Array2[Index];
}
void HostVectorSum(int ArraySize=1000, int ThreadsPerBlock=100){
int ArrayMemory = ArraySize * sizeof(int);
int* HostArray1 = (int*) malloc(ArrayMemory);
int* HostArray2 = (int*) malloc(ArrayMemory);
int* HostResult = (int*) malloc(ArrayMemory);
int* DeviceArray1;
int* DeviceArray2;
int* DeviceResult;
srand(time(0));
for(int i=0;i<ArraySize;i++){
HostArray1[i] = rand() % MaxElement;
HostArray2[i] = rand() % MaxElement;
}
hipMalloc(&DeviceArray1, ArrayMemory);
hipMalloc(&DeviceArray2, ArrayMemory);
hipMalloc(&DeviceResult, ArrayMemory);
hipMemcpy(DeviceArray1, HostArray1, ArrayMemory, hipMemcpyHostToDevice);
hipMemcpy(DeviceArray2, HostArray2, ArrayMemory, hipMemcpyHostToDevice);
int BlocksPerGrid = 1;
if(ArraySize > ThreadsPerBlock)
BlocksPerGrid = ceil(double(ArraySize) / double(ThreadsPerBlock));
Sum<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceArray1, DeviceArray2, DeviceResult, ArraySize);
hipMemcpy(HostResult, DeviceResult, ArrayMemory, hipMemcpyDeviceToHost);
hipFree(DeviceArray1);
hipFree(DeviceArray2);
hipFree(DeviceResult);
for(int i=0;i<ArraySize;i++)
printf("Index %d --> %d + %d = %d\n", i+1, HostArray1[i], HostArray2[i], HostResult[i]);
free(HostArray1);
free(HostArray2);
free(HostResult);
}
__global__ void VectorMatrixMultiplication(int* Vector, int* Matrix, int* Result, int Row, int Column){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Index < Column){
int ColumnStartIndex = Index * Row;
for(int i=0;i<Row;i++)
Sum += Vector[i] * Matrix[ColumnStartIndex + i];
Result[Index] = Sum;
}
}
void HostVectorMatrixMultiplication(int Row, int Column){
int* HostArray = (int*) malloc(Row * sizeof(int));
int* HostMatrix = (int*) malloc(Row * Column * sizeof(int));
int* HostResult = (int*) malloc(Column * sizeof(int));
int* DeviceArray;
int* DeviceMatrix;
int* DeviceResult;
srand(time(0));
for(int i=0;i<Row;i++)
HostArray[i] = rand() % MaxElement;
for(int i=0;i<Column;i++)
for(int j=0;j<Row;j++)
HostMatrix[i*Row+j] = rand() % MaxElement;
hipMalloc(&DeviceArray, Row*sizeof(int));
hipMalloc(&DeviceMatrix, Row*Column*sizeof(int));
hipMalloc(&DeviceResult, Column*sizeof(int));
hipMemcpy(DeviceArray, HostArray, Row*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(DeviceMatrix, HostMatrix, Row*Column*sizeof(int), hipMemcpyHostToDevice);
VectorMatrixMultiplication<<<Column, 1>>>(DeviceArray, DeviceMatrix, DeviceResult, Row, Column);
hipMemcpy(HostResult, DeviceResult, Column*sizeof(int), hipMemcpyDeviceToHost);
hipFree(DeviceArray);
hipFree(DeviceMatrix);
hipFree(DeviceResult);
for(int i=0;i<Column;i++)
printf("Index %d --> %d\n", i+1,HostResult[i]);
free(HostArray);
free(HostMatrix);
free(HostResult);
}
__global__ void MatrixMultiplication(int* MatrixA, int* MatrixB, int* Result, int Dimension){
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Column = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Row < Dimension && Column < Dimension){
for(int i=0;i<Dimension;i++)
Sum += MatrixA[Row * Dimension + i] * MatrixB[i * Dimension + Column];
__syncthreads();
Result[Row * Dimension + Column] = Sum;
}
}
void HostMatrixMultiplication(int Dimension){
int MatrixMemory = Dimension * Dimension * sizeof(int);
int* HostMatrixA = (int*) malloc(MatrixMemory);
int* HostMatrixB = (int*) malloc(MatrixMemory);
int* HostResult = (int*) malloc(MatrixMemory);
srand(time(0));
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
HostMatrixA[i * Dimension + j] = rand() % 30;
HostMatrixB[i * Dimension + j] = rand() % 30;
}
}
int* DeviceMatrixA;
int* DeviceMatrixB;
int* DeviceResult;
hipMalloc(&DeviceMatrixA, MatrixMemory);
hipMalloc(&DeviceMatrixB, MatrixMemory);
hipMalloc(&DeviceResult, MatrixMemory);
hipMemcpy(DeviceMatrixA, HostMatrixA, MatrixMemory, hipMemcpyHostToDevice);
hipMemcpy(DeviceMatrixB, HostMatrixB, MatrixMemory, hipMemcpyHostToDevice);
dim3 ThreadsPerBlock(Dimension, Dimension);
dim3 BlocksPerGrid(1, 1);
MatrixMultiplication<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceMatrixA, DeviceMatrixB, DeviceResult, Dimension);
hipError_t Exception = hipGetLastError();
if(Exception != hipSuccess){
printf("Cuda Error: %s", hipGetErrorString(Exception));
return;
}
hipDeviceSynchronize();
hipMemcpy(HostResult, DeviceResult, MatrixMemory, hipMemcpyDeviceToHost);
hipFree(DeviceMatrixA);
hipFree(DeviceMatrixB);
hipFree(DeviceResult);
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
printf("%d ", HostResult[i * Dimension + j]);
}
printf("\n");
}
}
int main(){
int Choice;
printf("1.Vector Addition\n2.Vector Matrix Multiplication\n3.Matrix Multiplication\n4.Exit\n");
printf("Enter The Operation To Be Performed: : ");
scanf("%d", &Choice);
if(Choice==1){
int ArraySize;
printf("Enter The Array Size: : ");
scanf("%d", &ArraySize);
HostVectorSum(ArraySize);
}
else if(Choice==2){
int Row, Column;
printf("Enter The Rows And Columns Of The Matrix: : ");
scanf("%d %d", &Row, &Column);
HostVectorMatrixMultiplication(Row, Column);
}
else if(Choice==3){
int Dimension;
printf("Enter The Dimensions Of The Matrix: : ");
scanf("%d", &Dimension);
HostMatrixMultiplication(Dimension);
}
else
return 0;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3SumPiS_S_i
.globl _Z3SumPiS_S_i
.p2align 8
.type _Z3SumPiS_S_i,@function
_Z3SumPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3SumPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3SumPiS_S_i, .Lfunc_end0-_Z3SumPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26VectorMatrixMultiplicationPiS_S_ii
.globl _Z26VectorMatrixMultiplicationPiS_S_ii
.p2align 8
.type _Z26VectorMatrixMultiplicationPiS_S_ii,@function
_Z26VectorMatrixMultiplicationPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_6
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.LBB1_3:
global_load_b32 v6, v[2:3], off
s_load_b32 s3, s[4:5], 0x0
v_add_co_u32 v2, vcc_lo, v2, 4
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v6, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v4
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v0, 0
.LBB1_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26VectorMatrixMultiplicationPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z26VectorMatrixMultiplicationPiS_S_ii, .Lfunc_end1-_Z26VectorMatrixMultiplicationPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20MatrixMultiplicationPiS_S_i
.globl _Z20MatrixMultiplicationPiS_S_i
.p2align 8
.type _Z20MatrixMultiplicationPiS_S_i,@function
_Z20MatrixMultiplicationPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB2_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB2_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB2_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB2_3
s_branch .LBB2_5
.LBB2_4:
v_mov_b32_e32 v2, 0
.LBB2_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20MatrixMultiplicationPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z20MatrixMultiplicationPiS_S_i, .Lfunc_end2-_Z20MatrixMultiplicationPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3SumPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3SumPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26VectorMatrixMultiplicationPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26VectorMatrixMultiplicationPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20MatrixMultiplicationPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20MatrixMultiplicationPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<ctime>
#include<cmath>
#include<stdexcept>
using namespace std;
#define MaxElement 1000
__global__ void Sum(int* Array1, int* Array2, int* Result, int ElementCount){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index < ElementCount)
Result[Index] = Array1[Index] + Array2[Index];
}
void HostVectorSum(int ArraySize=1000, int ThreadsPerBlock=100){
int ArrayMemory = ArraySize * sizeof(int);
int* HostArray1 = (int*) malloc(ArrayMemory);
int* HostArray2 = (int*) malloc(ArrayMemory);
int* HostResult = (int*) malloc(ArrayMemory);
int* DeviceArray1;
int* DeviceArray2;
int* DeviceResult;
srand(time(0));
for(int i=0;i<ArraySize;i++){
HostArray1[i] = rand() % MaxElement;
HostArray2[i] = rand() % MaxElement;
}
hipMalloc(&DeviceArray1, ArrayMemory);
hipMalloc(&DeviceArray2, ArrayMemory);
hipMalloc(&DeviceResult, ArrayMemory);
hipMemcpy(DeviceArray1, HostArray1, ArrayMemory, hipMemcpyHostToDevice);
hipMemcpy(DeviceArray2, HostArray2, ArrayMemory, hipMemcpyHostToDevice);
int BlocksPerGrid = 1;
if(ArraySize > ThreadsPerBlock)
BlocksPerGrid = ceil(double(ArraySize) / double(ThreadsPerBlock));
Sum<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceArray1, DeviceArray2, DeviceResult, ArraySize);
hipMemcpy(HostResult, DeviceResult, ArrayMemory, hipMemcpyDeviceToHost);
hipFree(DeviceArray1);
hipFree(DeviceArray2);
hipFree(DeviceResult);
for(int i=0;i<ArraySize;i++)
printf("Index %d --> %d + %d = %d\n", i+1, HostArray1[i], HostArray2[i], HostResult[i]);
free(HostArray1);
free(HostArray2);
free(HostResult);
}
__global__ void VectorMatrixMultiplication(int* Vector, int* Matrix, int* Result, int Row, int Column){
int Index = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Index < Column){
int ColumnStartIndex = Index * Row;
for(int i=0;i<Row;i++)
Sum += Vector[i] * Matrix[ColumnStartIndex + i];
Result[Index] = Sum;
}
}
void HostVectorMatrixMultiplication(int Row, int Column){
int* HostArray = (int*) malloc(Row * sizeof(int));
int* HostMatrix = (int*) malloc(Row * Column * sizeof(int));
int* HostResult = (int*) malloc(Column * sizeof(int));
int* DeviceArray;
int* DeviceMatrix;
int* DeviceResult;
srand(time(0));
for(int i=0;i<Row;i++)
HostArray[i] = rand() % MaxElement;
for(int i=0;i<Column;i++)
for(int j=0;j<Row;j++)
HostMatrix[i*Row+j] = rand() % MaxElement;
hipMalloc(&DeviceArray, Row*sizeof(int));
hipMalloc(&DeviceMatrix, Row*Column*sizeof(int));
hipMalloc(&DeviceResult, Column*sizeof(int));
hipMemcpy(DeviceArray, HostArray, Row*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(DeviceMatrix, HostMatrix, Row*Column*sizeof(int), hipMemcpyHostToDevice);
VectorMatrixMultiplication<<<Column, 1>>>(DeviceArray, DeviceMatrix, DeviceResult, Row, Column);
hipMemcpy(HostResult, DeviceResult, Column*sizeof(int), hipMemcpyDeviceToHost);
hipFree(DeviceArray);
hipFree(DeviceMatrix);
hipFree(DeviceResult);
for(int i=0;i<Column;i++)
printf("Index %d --> %d\n", i+1,HostResult[i]);
free(HostArray);
free(HostMatrix);
free(HostResult);
}
__global__ void MatrixMultiplication(int* MatrixA, int* MatrixB, int* Result, int Dimension){
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Column = blockIdx.x * blockDim.x + threadIdx.x;
int Sum = 0;
if(Row < Dimension && Column < Dimension){
for(int i=0;i<Dimension;i++)
Sum += MatrixA[Row * Dimension + i] * MatrixB[i * Dimension + Column];
__syncthreads();
Result[Row * Dimension + Column] = Sum;
}
}
void HostMatrixMultiplication(int Dimension){
int MatrixMemory = Dimension * Dimension * sizeof(int);
int* HostMatrixA = (int*) malloc(MatrixMemory);
int* HostMatrixB = (int*) malloc(MatrixMemory);
int* HostResult = (int*) malloc(MatrixMemory);
srand(time(0));
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
HostMatrixA[i * Dimension + j] = rand() % 30;
HostMatrixB[i * Dimension + j] = rand() % 30;
}
}
int* DeviceMatrixA;
int* DeviceMatrixB;
int* DeviceResult;
hipMalloc(&DeviceMatrixA, MatrixMemory);
hipMalloc(&DeviceMatrixB, MatrixMemory);
hipMalloc(&DeviceResult, MatrixMemory);
hipMemcpy(DeviceMatrixA, HostMatrixA, MatrixMemory, hipMemcpyHostToDevice);
hipMemcpy(DeviceMatrixB, HostMatrixB, MatrixMemory, hipMemcpyHostToDevice);
dim3 ThreadsPerBlock(Dimension, Dimension);
dim3 BlocksPerGrid(1, 1);
MatrixMultiplication<<<BlocksPerGrid, ThreadsPerBlock>>>(DeviceMatrixA, DeviceMatrixB, DeviceResult, Dimension);
hipError_t Exception = hipGetLastError();
if(Exception != hipSuccess){
printf("Cuda Error: %s", hipGetErrorString(Exception));
return;
}
hipDeviceSynchronize();
hipMemcpy(HostResult, DeviceResult, MatrixMemory, hipMemcpyDeviceToHost);
hipFree(DeviceMatrixA);
hipFree(DeviceMatrixB);
hipFree(DeviceResult);
for(int i=0;i<Dimension;i++){
for(int j=0;j<Dimension;j++){
printf("%d ", HostResult[i * Dimension + j]);
}
printf("\n");
}
}
int main(){
int Choice;
printf("1.Vector Addition\n2.Vector Matrix Multiplication\n3.Matrix Multiplication\n4.Exit\n");
printf("Enter The Operation To Be Performed: : ");
scanf("%d", &Choice);
if(Choice==1){
int ArraySize;
printf("Enter The Array Size: : ");
scanf("%d", &ArraySize);
HostVectorSum(ArraySize);
}
else if(Choice==2){
int Row, Column;
printf("Enter The Rows And Columns Of The Matrix: : ");
scanf("%d %d", &Row, &Column);
HostVectorMatrixMultiplication(Row, Column);
}
else if(Choice==3){
int Dimension;
printf("Enter The Dimensions Of The Matrix: : ");
scanf("%d", &Dimension);
HostMatrixMultiplication(Dimension);
}
else
return 0;
return 0;
} | .text
.file "Assignment2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__SumPiS_S_i # -- Begin function _Z18__device_stub__SumPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__SumPiS_S_i,@function
_Z18__device_stub__SumPiS_S_i: # @_Z18__device_stub__SumPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3SumPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__SumPiS_S_i, .Lfunc_end0-_Z18__device_stub__SumPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13HostVectorSumii # -- Begin function _Z13HostVectorSumii
.p2align 4, 0x90
.type _Z13HostVectorSumii,@function
_Z13HostVectorSumii: # @_Z13HostVectorSumii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 12(%rsp) # 4-byte Spill
movl %edi, %r12d
leal (,%r12,4), %eax
movslq %eax, %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %r15
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %r12d, %ebp
movq %r12, 48(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %r12 # 8-byte Reload
movl 12(%rsp), %eax # 4-byte Reload
cmpl %eax, %r12d
jle .LBB1_4
# %bb.5:
cvtsi2sd %r12d, %xmm0
cvtsi2sd %eax, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
movl 12(%rsp), %eax # 4-byte Reload
cvttsd2si %xmm0, %edi
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rdi
jmp .LBB1_6
.LBB1_4:
movabsq $4294967296, %rcx # imm = 0x100000000
leaq 1(%rcx), %rdi
.LBB1_6:
movl %eax, %edx
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r12d, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3SumPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 16(%rsp), %rsi
movq %r15, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
testl %r12d, %r12d
jle .LBB1_11
# %bb.9: # %.lr.ph51.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_10: # %.lr.ph51
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %r12
movl (%rbx,%rax,4), %edx
movl (%r14,%rax,4), %ecx
movl (%r15,%rax,4), %r8d
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movq %r12, %rax
cmpq %r12, %rbp
jne .LBB1_10
.LBB1_11: # %._crit_edge52
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13HostVectorSumii, .Lfunc_end1-_Z13HostVectorSumii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__VectorMatrixMultiplicationPiS_S_ii # -- Begin function _Z41__device_stub__VectorMatrixMultiplicationPiS_S_ii
.p2align 4, 0x90
.type _Z41__device_stub__VectorMatrixMultiplicationPiS_S_ii,@function
_Z41__device_stub__VectorMatrixMultiplicationPiS_S_ii: # @_Z41__device_stub__VectorMatrixMultiplicationPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26VectorMatrixMultiplicationPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z41__device_stub__VectorMatrixMultiplicationPiS_S_ii, .Lfunc_end2-_Z41__device_stub__VectorMatrixMultiplicationPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z30HostVectorMatrixMultiplicationii # -- Begin function _Z30HostVectorMatrixMultiplicationii
.p2align 4, 0x90
.type _Z30HostVectorMatrixMultiplicationii,@function
_Z30HostVectorMatrixMultiplicationii: # @_Z30HostVectorMatrixMultiplicationii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r13d
movslq %edi, %rbx
leaq (,%rbx,4), %rdi
movq %rdi, 72(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r14
movl %ebp, %eax
imull %r13d, %eax
movslq %eax, %rdi
shlq $2, %rdi
movq %rdi, 64(%rsp) # 8-byte Spill
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movslq %ebp, %rdi
shlq $2, %rdi
movq %rdi, 80(%rsp) # 8-byte Spill
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %r13d, %r12d
testl %ebx, %ebx
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
cmpq %rbx, %r12
jne .LBB3_2
.LBB3_3: # %.preheader51
movq %r14, 96(%rsp) # 8-byte Spill
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, 52(%rsp) # 4-byte Spill
testl %ebp, %ebp
jle .LBB3_9
# %bb.4: # %.preheader.lr.ph
xorl %r14d, %r14d
xorl %ebx, %ebx
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_8: # %._crit_edge
# in Loop: Header=BB3_5 Depth=1
incq %rbx
addl %r13d, %r14d
cmpq 16(%rsp), %rbx # 8-byte Folded Reload
je .LBB3_9
.LBB3_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_7 Depth 2
testl %r13d, %r13d
jle .LBB3_8
# %bb.6: # %.lr.ph54
# in Loop: Header=BB3_5 Depth=1
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_7: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %r12
jne .LBB3_7
jmp .LBB3_8
.LBB3_9: # %._crit_edge56
leaq 40(%rsp), %rdi
movq 72(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq 64(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 96(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%rdx), %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movl 52(%rsp), %ebp # 4-byte Reload
jne .LBB3_11
# %bb.10:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r13d, 60(%rsp)
movl %ebp, 56(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z26VectorMatrixMultiplicationPiS_S_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
movq 24(%rsp), %rsi
movq 88(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
testl %ebp, %ebp
movq 16(%rsp), %r15 # 8-byte Reload
jle .LBB3_14
# %bb.12: # %.lr.ph59.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_13: # %.lr.ph59
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %edx
incq %r12
movl $.L.str.1, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
cmpq %r12, %r15
jne .LBB3_13
.LBB3_14: # %._crit_edge60
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z30HostVectorMatrixMultiplicationii, .Lfunc_end3-_Z30HostVectorMatrixMultiplicationii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__MatrixMultiplicationPiS_S_i # -- Begin function _Z35__device_stub__MatrixMultiplicationPiS_S_i
.p2align 4, 0x90
.type _Z35__device_stub__MatrixMultiplicationPiS_S_i,@function
_Z35__device_stub__MatrixMultiplicationPiS_S_i: # @_Z35__device_stub__MatrixMultiplicationPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20MatrixMultiplicationPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z35__device_stub__MatrixMultiplicationPiS_S_i, .Lfunc_end4-_Z35__device_stub__MatrixMultiplicationPiS_S_i
.cfi_endproc
# -- End function
.globl _Z24HostMatrixMultiplicationi # -- Begin function _Z24HostMatrixMultiplicationi
.p2align 4, 0x90
.type _Z24HostMatrixMultiplicationi,@function
_Z24HostMatrixMultiplicationi: # @_Z24HostMatrixMultiplicationi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl %edi, %eax
imull %edi, %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movq %r14, 56(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %ebx, %ebp
movl %ebx, 4(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB5_5
# %bb.1: # %.preheader56.lr.ph
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.preheader56
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
movl %r14d, %eax
movq 48(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
movq 40(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-2004318071, %rax, %rcx # imm = 0x88888889
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $4, %ecx
addl %edx, %ecx
movl %ecx, %edx
shll $5, %edx
addl %ecx, %ecx
subl %edx, %ecx
addl %eax, %ecx
movl %ecx, (%r12,%r13,4)
callq rand
cltq
imulq $-2004318071, %rax, %rcx # imm = 0x88888889
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $4, %ecx
addl %edx, %ecx
movl %ecx, %edx
shll $5, %edx
addl %ecx, %ecx
subl %edx, %ecx
addl %eax, %ecx
movl %ecx, (%rbx,%r13,4)
incq %r13
cmpq %r13, %rbp
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %r15
addl 4(%rsp), %r14d # 4-byte Folded Reload
cmpq %rbp, %r15
jne .LBB5_2
.LBB5_5: # %._crit_edge59
leaq 24(%rsp), %rdi
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdx
shlq $32, %rdx
orq %rbp, %rdx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z20MatrixMultiplicationPiS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_7:
callq hipGetLastError
testl %eax, %eax
movq 64(%rsp), %r13 # 8-byte Reload
je .LBB5_9
# %bb.8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
jmp .LBB5_14
.LBB5_9:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB5_14
# %bb.10: # %.preheader.lr.ph
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_12 Depth 2
movl %ebx, %eax
leaq (,%rax,4), %r15
addq %r13, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_12: # Parent Loop BB5_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %rbp
jne .LBB5_12
# %bb.13: # %._crit_edge62
# in Loop: Header=BB5_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl 4(%rsp), %ebx # 4-byte Folded Reload
cmpq %rbp, %r14
jne .LBB5_11
.LBB5_14: # %.loopexit
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z24HostMatrixMultiplicationi, .Lfunc_end5-_Z24HostMatrixMultiplicationi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 20(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 20(%rsp), %eax
cmpl $3, %eax
je .LBB6_5
# %bb.1:
cmpl $2, %eax
je .LBB6_4
# %bb.2:
cmpl $1, %eax
jne .LBB6_6
# %bb.3:
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %edi
movl $100, %esi
callq _Z13HostVectorSumii
jmp .LBB6_6
.LBB6_4:
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
leaq 16(%rsp), %rdx
movl $.L.str.10, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %edi
movl 16(%rsp), %esi
callq _Z30HostVectorMatrixMultiplicationii
jmp .LBB6_6
.LBB6_5:
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %edi
callq _Z24HostMatrixMultiplicationi
.LBB6_6:
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3SumPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26VectorMatrixMultiplicationPiS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20MatrixMultiplicationPiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3SumPiS_S_i,@object # @_Z3SumPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3SumPiS_S_i
.p2align 3, 0x0
_Z3SumPiS_S_i:
.quad _Z18__device_stub__SumPiS_S_i
.size _Z3SumPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Index %d --> %d + %d = %d\n"
.size .L.str, 27
.type _Z26VectorMatrixMultiplicationPiS_S_ii,@object # @_Z26VectorMatrixMultiplicationPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z26VectorMatrixMultiplicationPiS_S_ii
.p2align 3, 0x0
_Z26VectorMatrixMultiplicationPiS_S_ii:
.quad _Z41__device_stub__VectorMatrixMultiplicationPiS_S_ii
.size _Z26VectorMatrixMultiplicationPiS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Index %d --> %d\n"
.size .L.str.1, 17
.type _Z20MatrixMultiplicationPiS_S_i,@object # @_Z20MatrixMultiplicationPiS_S_i
.section .rodata,"a",@progbits
.globl _Z20MatrixMultiplicationPiS_S_i
.p2align 3, 0x0
_Z20MatrixMultiplicationPiS_S_i:
.quad _Z35__device_stub__MatrixMultiplicationPiS_S_i
.size _Z20MatrixMultiplicationPiS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Cuda Error: %s"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Enter The Operation To Be Performed: : "
.size .L.str.6, 40
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Enter The Array Size: : "
.size .L.str.8, 25
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Enter The Rows And Columns Of The Matrix: : "
.size .L.str.9, 45
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d %d"
.size .L.str.10, 6
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Enter The Dimensions Of The Matrix: : "
.size .L.str.11, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3SumPiS_S_i"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26VectorMatrixMultiplicationPiS_S_ii"
.size .L__unnamed_2, 39
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20MatrixMultiplicationPiS_S_i"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "1.Vector Addition\n2.Vector Matrix Multiplication\n3.Matrix Multiplication\n4.Exit"
.size .Lstr, 80
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__SumPiS_S_i
.addrsig_sym _Z41__device_stub__VectorMatrixMultiplicationPiS_S_ii
.addrsig_sym _Z35__device_stub__MatrixMultiplicationPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3SumPiS_S_i
.addrsig_sym _Z26VectorMatrixMultiplicationPiS_S_ii
.addrsig_sym _Z20MatrixMultiplicationPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_add_wavelet ( float *g_u2, float wavelets, const int nx, const int ny, const int ngpus)
{
// global grid idx for (x,y) plane
int ipos = (ngpus == 2 ? ny - 10 : ny / 2 - 10);
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int idx = ipos * nx + ix;
if(ix == nx / 2) g_u2[idx] += wavelets;
} | code for sm_80
Function : _Z18kernel_add_waveletPffiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ MOV R2, c[0x0][0x174] ; /* 0x00005d0000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05270 */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fd600078e00ff */
/*0090*/ @P0 LEA.HI R2, R2, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0002020a11 */
/* 0x000fe200078f08ff */
/*00a0*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fe200078e0200 */
/*00b0*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fe40000000f00 */
/*00c0*/ @P0 SHF.R.S32.HI R0, RZ, 0x1, R2 ; /* 0x00000001ff000819 */
/* 0x000fe40000011402 */
/*00d0*/ ISETP.NE.AND P1, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fe4000bf25270 */
/*00e0*/ IADD3 R0, R0, -0xa, RZ ; /* 0xfffffff600007810 */
/* 0x000fd60007ffe0ff */
/*00f0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD R3, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000037a24 */
/* 0x000fc800078e0203 */
/*0130*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0002 */
/*0140*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FADD R5, R0, c[0x0][0x168] ; /* 0x00005a0000057621 */
/* 0x004fca0000000000 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_add_wavelet ( float *g_u2, float wavelets, const int nx, const int ny, const int ngpus)
{
// global grid idx for (x,y) plane
int ipos = (ngpus == 2 ? ny - 10 : ny / 2 - 10);
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int idx = ipos * nx + ix;
if(ix == nx / 2) g_u2[idx] += wavelets;
} | .file "tmpxft_0004208e_00000000-6_kernel_add_wavelet.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii
.type _Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii, @function
_Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernel_add_waveletPffiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii, .-_Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii
.globl _Z18kernel_add_waveletPffiii
.type _Z18kernel_add_waveletPffiii, @function
_Z18kernel_add_waveletPffiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18kernel_add_waveletPffiii, .-_Z18kernel_add_waveletPffiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernel_add_waveletPffiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_add_waveletPffiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_add_wavelet ( float *g_u2, float wavelets, const int nx, const int ny, const int ngpus)
{
// global grid idx for (x,y) plane
int ipos = (ngpus == 2 ? ny - 10 : ny / 2 - 10);
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int idx = ipos * nx + ix;
if(ix == nx / 2) g_u2[idx] += wavelets;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_add_wavelet ( float *g_u2, float wavelets, const int nx, const int ny, const int ngpus)
{
// global grid idx for (x,y) plane
int ipos = (ngpus == 2 ? ny - 10 : ny / 2 - 10);
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int idx = ipos * nx + ix;
if(ix == nx / 2) g_u2[idx] += wavelets;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_add_wavelet ( float *g_u2, float wavelets, const int nx, const int ny, const int ngpus)
{
// global grid idx for (x,y) plane
int ipos = (ngpus == 2 ? ny - 10 : ny / 2 - 10);
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int idx = ipos * nx + ix;
if(ix == nx / 2) g_u2[idx] += wavelets;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernel_add_waveletPffiii
.globl _Z18kernel_add_waveletPffiii
.p2align 8
.type _Z18kernel_add_waveletPffiii,@function
_Z18kernel_add_waveletPffiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_lshr_b32 s3, s2, 31
s_add_i32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s4, s3
s_ashr_i32 s3, s3, 1
s_cmp_eq_u32 s5, 2
s_cselect_b32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, -10
v_mad_u64_u32 v[2:3], null, s3, s2, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernel_add_waveletPffiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernel_add_waveletPffiii, .Lfunc_end0-_Z18kernel_add_waveletPffiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernel_add_waveletPffiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernel_add_waveletPffiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_add_wavelet ( float *g_u2, float wavelets, const int nx, const int ny, const int ngpus)
{
// global grid idx for (x,y) plane
int ipos = (ngpus == 2 ? ny - 10 : ny / 2 - 10);
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int idx = ipos * nx + ix;
if(ix == nx / 2) g_u2[idx] += wavelets;
} | .text
.file "kernel_add_wavelet.hip"
.globl _Z33__device_stub__kernel_add_waveletPffiii # -- Begin function _Z33__device_stub__kernel_add_waveletPffiii
.p2align 4, 0x90
.type _Z33__device_stub__kernel_add_waveletPffiii,@function
_Z33__device_stub__kernel_add_waveletPffiii: # @_Z33__device_stub__kernel_add_waveletPffiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernel_add_waveletPffiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_add_waveletPffiii, .Lfunc_end0-_Z33__device_stub__kernel_add_waveletPffiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_add_waveletPffiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_add_waveletPffiii,@object # @_Z18kernel_add_waveletPffiii
.section .rodata,"a",@progbits
.globl _Z18kernel_add_waveletPffiii
.p2align 3, 0x0
_Z18kernel_add_waveletPffiii:
.quad _Z33__device_stub__kernel_add_waveletPffiii
.size _Z18kernel_add_waveletPffiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_add_waveletPffiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_add_waveletPffiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_add_waveletPffiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18kernel_add_waveletPffiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ MOV R2, c[0x0][0x174] ; /* 0x00005d0000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05270 */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fd600078e00ff */
/*0090*/ @P0 LEA.HI R2, R2, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0002020a11 */
/* 0x000fe200078f08ff */
/*00a0*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fe200078e0200 */
/*00b0*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fe40000000f00 */
/*00c0*/ @P0 SHF.R.S32.HI R0, RZ, 0x1, R2 ; /* 0x00000001ff000819 */
/* 0x000fe40000011402 */
/*00d0*/ ISETP.NE.AND P1, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fe4000bf25270 */
/*00e0*/ IADD3 R0, R0, -0xa, RZ ; /* 0xfffffff600007810 */
/* 0x000fd60007ffe0ff */
/*00f0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD R3, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000037a24 */
/* 0x000fc800078e0203 */
/*0130*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0002 */
/*0140*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FADD R5, R0, c[0x0][0x168] ; /* 0x00005a0000057621 */
/* 0x004fca0000000000 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernel_add_waveletPffiii
.globl _Z18kernel_add_waveletPffiii
.p2align 8
.type _Z18kernel_add_waveletPffiii,@function
_Z18kernel_add_waveletPffiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_lshr_b32 s3, s2, 31
s_add_i32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s4, s3
s_ashr_i32 s3, s3, 1
s_cmp_eq_u32 s5, 2
s_cselect_b32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, -10
v_mad_u64_u32 v[2:3], null, s3, s2, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernel_add_waveletPffiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernel_add_waveletPffiii, .Lfunc_end0-_Z18kernel_add_waveletPffiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernel_add_waveletPffiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernel_add_waveletPffiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004208e_00000000-6_kernel_add_wavelet.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii
.type _Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii, @function
_Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernel_add_waveletPffiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii, .-_Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii
.globl _Z18kernel_add_waveletPffiii
.type _Z18kernel_add_waveletPffiii, @function
_Z18kernel_add_waveletPffiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18kernel_add_waveletPffiiiPffiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18kernel_add_waveletPffiii, .-_Z18kernel_add_waveletPffiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernel_add_waveletPffiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_add_waveletPffiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_add_wavelet.hip"
.globl _Z33__device_stub__kernel_add_waveletPffiii # -- Begin function _Z33__device_stub__kernel_add_waveletPffiii
.p2align 4, 0x90
.type _Z33__device_stub__kernel_add_waveletPffiii,@function
_Z33__device_stub__kernel_add_waveletPffiii: # @_Z33__device_stub__kernel_add_waveletPffiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernel_add_waveletPffiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_add_waveletPffiii, .Lfunc_end0-_Z33__device_stub__kernel_add_waveletPffiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_add_waveletPffiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_add_waveletPffiii,@object # @_Z18kernel_add_waveletPffiii
.section .rodata,"a",@progbits
.globl _Z18kernel_add_waveletPffiii
.p2align 3, 0x0
_Z18kernel_add_waveletPffiii:
.quad _Z33__device_stub__kernel_add_waveletPffiii
.size _Z18kernel_add_waveletPffiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_add_waveletPffiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_add_waveletPffiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_add_waveletPffiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#include <device_functions.h>
#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define N 3
/*
multiplicacion de matrices con memoria constante
*/
// definicion de memoria constante CUDA
__constant__ float dev_A[N][N];
__constant__ float dev_B[N][N];
//GLOBAL: func desde el host y ejecutada en el kernel(DEVICE)
__global__ void multiplicacion(float *dev_C)
{
int suma = 0;
int columna = threadIdx.x;
int fila = threadIdx.y;
int pos = columna + N * fila;
if (columna < N && fila < N)
{
for (int k = 0; k < N; k++)
{
dev_C[pos] += dev_A[fila][k] * dev_B[k][columna];
}
}
}
int main(int argc, char** argv)
{
float *hst_A, *hst_B, *hst_C;
float *dev_C;
int size = N * N * sizeof(float);
//reserva de memoria en el host
hst_A = (float*)malloc(size);
hst_B = (float*)malloc(size);
hst_C = (float*)malloc(size);
//reserva de memoria en el device
cudaMalloc((void**)&dev_C, size);
//llenar la matriz
for (int i = 0; i < N*N; i++)
{
hst_A[i] = float(i) + 1;
hst_B[i] = float(i);
}
//copiar los datos hacia el device desde memoria constante
cudaError_t error = cudaMemcpyToSymbol(dev_A, hst_A, size);
if (error != cudaSuccess) {
printf("Error Memoria constante dev_A to hst_A\n");
}
error = cudaMemcpyToSymbol(dev_B, hst_B, size);
if (error != cudaSuccess) {
printf("Error Memoria constante dev_B to hst_B\n");
}
//dimensiones del kernel a lanzar
dim3 bloques(1);
dim3 hilos(N, N);
//lanzamiento del kernel
multiplicacion <<<bloques, hilos >>> (dev_C);
//recoger los datos
cudaMemcpy(hst_C, dev_C, size, cudaMemcpyDeviceToHost);
//impresion de los datos
printf("\nMatriz A:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_A[j + i * N]);
}
printf("\n");
}
printf("\nMatriz B:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_B[j + i * N]);
}
printf("\n");
}
printf("\n");
printf("multiplicacion de matrices A y B:\n");
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_C[j + i * N]);
}
printf("\n");
}
printf("\n pulsa INTRO para salir:\n");
fflush(stdin);
char tecla = getchar();
return 0;
} | code for sm_80
Function : _Z14multiplicacionPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0020*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GT.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x001fc80003f04270 */
/*0040*/ ISETP.GT.OR P0, PT, R4, 0x2, P0 ; /* 0x000000020400780c */
/* 0x002fda0000704670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD R2, R5, 0x3, R4 ; /* 0x0000000305027824 */
/* 0x000fe200078e0204 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD R0, R5, 0xc, RZ ; /* 0x0000000c05007824 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD R4, R4, R9, c[0x2][0x0] ; /* 0x0080000004047624 */
/* 0x000fe400078e0209 */
/*00d0*/ LDC R6, c[0x3][R0] ; /* 0x00c0000000067b82 */
/* 0x000eb00000000800 */
/*00e0*/ LDC R5, c[0x3][R4] ; /* 0x00c0000004057b82 */
/* 0x000eb00000000800 */
/*00f0*/ LDC R9, c[0x3][R0+0x4] ; /* 0x00c0010000097b82 */
/* 0x000e300000000800 */
/*0100*/ LDC R8, c[0x3][R4+0xc] ; /* 0x00c0030004087b82 */
/* 0x000e300000000800 */
/*0110*/ LDC R11, c[0x3][R0+0x8] ; /* 0x00c00200000b7b82 */
/* 0x000e700000000800 */
/*0120*/ LDC R10, c[0x3][R4+0x18] ; /* 0x00c00600040a7b82 */
/* 0x000e620000000800 */
/*0130*/ FFMA R5, R5, R6, R7 ; /* 0x0000000605057223 */
/* 0x004fc80000000007 */
/*0140*/ FFMA R5, R8, R9, R5 ; /* 0x0000000908057223 */
/* 0x001fc80000000005 */
/*0150*/ FFMA R5, R10, R11, R5 ; /* 0x0000000b0a057223 */
/* 0x002fca0000000005 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#include <device_functions.h>
#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define N 3
/*
multiplicacion de matrices con memoria constante
*/
// definicion de memoria constante CUDA
__constant__ float dev_A[N][N];
__constant__ float dev_B[N][N];
//GLOBAL: func desde el host y ejecutada en el kernel(DEVICE)
__global__ void multiplicacion(float *dev_C)
{
int suma = 0;
int columna = threadIdx.x;
int fila = threadIdx.y;
int pos = columna + N * fila;
if (columna < N && fila < N)
{
for (int k = 0; k < N; k++)
{
dev_C[pos] += dev_A[fila][k] * dev_B[k][columna];
}
}
}
int main(int argc, char** argv)
{
float *hst_A, *hst_B, *hst_C;
float *dev_C;
int size = N * N * sizeof(float);
//reserva de memoria en el host
hst_A = (float*)malloc(size);
hst_B = (float*)malloc(size);
hst_C = (float*)malloc(size);
//reserva de memoria en el device
cudaMalloc((void**)&dev_C, size);
//llenar la matriz
for (int i = 0; i < N*N; i++)
{
hst_A[i] = float(i) + 1;
hst_B[i] = float(i);
}
//copiar los datos hacia el device desde memoria constante
cudaError_t error = cudaMemcpyToSymbol(dev_A, hst_A, size);
if (error != cudaSuccess) {
printf("Error Memoria constante dev_A to hst_A\n");
}
error = cudaMemcpyToSymbol(dev_B, hst_B, size);
if (error != cudaSuccess) {
printf("Error Memoria constante dev_B to hst_B\n");
}
//dimensiones del kernel a lanzar
dim3 bloques(1);
dim3 hilos(N, N);
//lanzamiento del kernel
multiplicacion <<<bloques, hilos >>> (dev_C);
//recoger los datos
cudaMemcpy(hst_C, dev_C, size, cudaMemcpyDeviceToHost);
//impresion de los datos
printf("\nMatriz A:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_A[j + i * N]);
}
printf("\n");
}
printf("\nMatriz B:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_B[j + i * N]);
}
printf("\n");
}
printf("\n");
printf("multiplicacion de matrices A y B:\n");
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_C[j + i * N]);
}
printf("\n");
}
printf("\n pulsa INTRO para salir:\n");
fflush(stdin);
char tecla = getchar();
return 0;
} | .file "tmpxft_0003f457_00000000-6_ejercicio8.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14multiplicacionPfPf
.type _Z34__device_stub__Z14multiplicacionPfPf, @function
_Z34__device_stub__Z14multiplicacionPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14multiplicacionPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z14multiplicacionPfPf, .-_Z34__device_stub__Z14multiplicacionPfPf
.globl _Z14multiplicacionPf
.type _Z14multiplicacionPf, @function
_Z14multiplicacionPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14multiplicacionPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14multiplicacionPf, .-_Z14multiplicacionPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Error Memoria constante dev_A to hst_A\n"
.align 8
.LC2:
.string "Error Memoria constante dev_B to hst_B\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\nMatriz A:\n"
.LC4:
.string "%.2f\t"
.LC5:
.string "\n"
.LC6:
.string "\nMatriz B:\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "multiplicacion de matrices A y B:\n"
.section .rodata.str1.1
.LC8:
.string "\n pulsa INTRO para salir:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $36, %edi
call malloc@PLT
movq %rax, %r12
movl $36, %edi
call malloc@PLT
movq %rax, %rbp
movl $36, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 24(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm2
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movaps %xmm0, %xmm1
addss %xmm2, %xmm1
movss %xmm1, (%r12,%rax,4)
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $9, %rax
jne .L12
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
movq %r12, %rsi
leaq _ZL5dev_A(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L31
.L13:
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
movq %rbp, %rsi
leaq _ZL5dev_B(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L32
.L14:
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $3, 44(%rsp)
movl $3, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L15:
movl $2, %ecx
movl $36, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r15
jmp .L16
.L31:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L32:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L33:
movq 24(%rsp), %rdi
call _Z34__device_stub__Z14multiplicacionPfPf
jmp .L15
.L34:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r14d
addq $12, %r12
cmpl $9, %r14d
je .L18
.L16:
movl $0, %ebx
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L17
jmp .L34
.L18:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC4(%rip), %r12
leaq .LC5(%rip), %r14
jmp .L19
.L35:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r13d
addq $12, %rbp
cmpl $9, %r13d
je .L21
.L19:
movl $0, %ebx
.L20:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L20
jmp .L35
.L21:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rbp
movl $0, %r13d
leaq .LC4(%rip), %r12
leaq .LC5(%rip), %r14
jmp .L22
.L36:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r13d
addq $12, %rbp
cmpl $9, %r13d
je .L24
.L22:
movl $0, %ebx
.L23:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L23
jmp .L36
.L24:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call fflush@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z14multiplicacionPf"
.LC10:
.string "dev_A"
.LC11:
.string "dev_B"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z14multiplicacionPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_A(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_B(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5dev_B
.comm _ZL5dev_B,36,32
.local _ZL5dev_A
.comm _ZL5dev_A,36,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#include <device_functions.h>
#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define N 3
/*
multiplicacion de matrices con memoria constante
*/
// definicion de memoria constante CUDA
__constant__ float dev_A[N][N];
__constant__ float dev_B[N][N];
//GLOBAL: func desde el host y ejecutada en el kernel(DEVICE)
__global__ void multiplicacion(float *dev_C)
{
int suma = 0;
int columna = threadIdx.x;
int fila = threadIdx.y;
int pos = columna + N * fila;
if (columna < N && fila < N)
{
for (int k = 0; k < N; k++)
{
dev_C[pos] += dev_A[fila][k] * dev_B[k][columna];
}
}
}
int main(int argc, char** argv)
{
float *hst_A, *hst_B, *hst_C;
float *dev_C;
int size = N * N * sizeof(float);
//reserva de memoria en el host
hst_A = (float*)malloc(size);
hst_B = (float*)malloc(size);
hst_C = (float*)malloc(size);
//reserva de memoria en el device
cudaMalloc((void**)&dev_C, size);
//llenar la matriz
for (int i = 0; i < N*N; i++)
{
hst_A[i] = float(i) + 1;
hst_B[i] = float(i);
}
//copiar los datos hacia el device desde memoria constante
cudaError_t error = cudaMemcpyToSymbol(dev_A, hst_A, size);
if (error != cudaSuccess) {
printf("Error Memoria constante dev_A to hst_A\n");
}
error = cudaMemcpyToSymbol(dev_B, hst_B, size);
if (error != cudaSuccess) {
printf("Error Memoria constante dev_B to hst_B\n");
}
//dimensiones del kernel a lanzar
dim3 bloques(1);
dim3 hilos(N, N);
//lanzamiento del kernel
multiplicacion <<<bloques, hilos >>> (dev_C);
//recoger los datos
cudaMemcpy(hst_C, dev_C, size, cudaMemcpyDeviceToHost);
//impresion de los datos
printf("\nMatriz A:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_A[j + i * N]);
}
printf("\n");
}
printf("\nMatriz B:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_B[j + i * N]);
}
printf("\n");
}
printf("\n");
printf("multiplicacion de matrices A y B:\n");
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_C[j + i * N]);
}
printf("\n");
}
printf("\n pulsa INTRO para salir:\n");
fflush(stdin);
char tecla = getchar();
return 0;
} | /*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#include <hip/device_functions.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 3
/*
multiplicacion de matrices con memoria constante
*/
// definicion de memoria constante CUDA
__constant__ float dev_A[N][N];
__constant__ float dev_B[N][N];
//GLOBAL: func desde el host y ejecutada en el kernel(DEVICE)
__global__ void multiplicacion(float *dev_C)
{
int suma = 0;
int columna = threadIdx.x;
int fila = threadIdx.y;
int pos = columna + N * fila;
if (columna < N && fila < N)
{
for (int k = 0; k < N; k++)
{
dev_C[pos] += dev_A[fila][k] * dev_B[k][columna];
}
}
}
int main(int argc, char** argv)
{
float *hst_A, *hst_B, *hst_C;
float *dev_C;
int size = N * N * sizeof(float);
//reserva de memoria en el host
hst_A = (float*)malloc(size);
hst_B = (float*)malloc(size);
hst_C = (float*)malloc(size);
//reserva de memoria en el device
hipMalloc((void**)&dev_C, size);
//llenar la matriz
for (int i = 0; i < N*N; i++)
{
hst_A[i] = float(i) + 1;
hst_B[i] = float(i);
}
//copiar los datos hacia el device desde memoria constante
hipError_t error = hipMemcpyToSymbol(HIP_SYMBOL(dev_A), hst_A, size);
if (error != hipSuccess) {
printf("Error Memoria constante dev_A to hst_A\n");
}
error = hipMemcpyToSymbol(HIP_SYMBOL(dev_B), hst_B, size);
if (error != hipSuccess) {
printf("Error Memoria constante dev_B to hst_B\n");
}
//dimensiones del kernel a lanzar
dim3 bloques(1);
dim3 hilos(N, N);
//lanzamiento del kernel
multiplicacion <<<bloques, hilos >>> (dev_C);
//recoger los datos
hipMemcpy(hst_C, dev_C, size, hipMemcpyDeviceToHost);
//impresion de los datos
printf("\nMatriz A:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_A[j + i * N]);
}
printf("\n");
}
printf("\nMatriz B:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_B[j + i * N]);
}
printf("\n");
}
printf("\n");
printf("multiplicacion de matrices A y B:\n");
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_C[j + i * N]);
}
printf("\n");
}
printf("\n pulsa INTRO para salir:\n");
fflush(stdin);
char tecla = getchar();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#include <hip/device_functions.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 3
/*
multiplicacion de matrices con memoria constante
*/
// definicion de memoria constante CUDA
__constant__ float dev_A[N][N];
__constant__ float dev_B[N][N];
//GLOBAL: func desde el host y ejecutada en el kernel(DEVICE)
__global__ void multiplicacion(float *dev_C)
{
int suma = 0;
int columna = threadIdx.x;
int fila = threadIdx.y;
int pos = columna + N * fila;
if (columna < N && fila < N)
{
for (int k = 0; k < N; k++)
{
dev_C[pos] += dev_A[fila][k] * dev_B[k][columna];
}
}
}
int main(int argc, char** argv)
{
float *hst_A, *hst_B, *hst_C;
float *dev_C;
int size = N * N * sizeof(float);
//reserva de memoria en el host
hst_A = (float*)malloc(size);
hst_B = (float*)malloc(size);
hst_C = (float*)malloc(size);
//reserva de memoria en el device
hipMalloc((void**)&dev_C, size);
//llenar la matriz
for (int i = 0; i < N*N; i++)
{
hst_A[i] = float(i) + 1;
hst_B[i] = float(i);
}
//copiar los datos hacia el device desde memoria constante
hipError_t error = hipMemcpyToSymbol(HIP_SYMBOL(dev_A), hst_A, size);
if (error != hipSuccess) {
printf("Error Memoria constante dev_A to hst_A\n");
}
error = hipMemcpyToSymbol(HIP_SYMBOL(dev_B), hst_B, size);
if (error != hipSuccess) {
printf("Error Memoria constante dev_B to hst_B\n");
}
//dimensiones del kernel a lanzar
dim3 bloques(1);
dim3 hilos(N, N);
//lanzamiento del kernel
multiplicacion <<<bloques, hilos >>> (dev_C);
//recoger los datos
hipMemcpy(hst_C, dev_C, size, hipMemcpyDeviceToHost);
//impresion de los datos
printf("\nMatriz A:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_A[j + i * N]);
}
printf("\n");
}
printf("\nMatriz B:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_B[j + i * N]);
}
printf("\n");
}
printf("\n");
printf("multiplicacion de matrices A y B:\n");
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_C[j + i * N]);
}
printf("\n");
}
printf("\n pulsa INTRO para salir:\n");
fflush(stdin);
char tecla = getchar();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14multiplicacionPf
.globl _Z14multiplicacionPf
.p2align 8
.type _Z14multiplicacionPf,@function
_Z14multiplicacionPf:
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_u32_e32 v0, v1, v4
v_cmpx_gt_u32_e32 3, v0
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_u32_u24_e32 v0, 3, v4
v_lshlrev_b32_e32 v5, 2, v1
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dev_A@rel32@lo+4
s_addc_u32 s3, s3, dev_A@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, dev_B@rel32@lo+4
s_addc_u32 s5, s5, dev_B@rel32@hi+12
v_mad_u64_u32 v[2:3], null, v4, 12, s[2:3]
v_add_lshl_u32 v0, v0, v1, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v6, v0, s[0:1]
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_add_co_u32 v4, s0, v5, s4
v_add_co_ci_u32_e64 v5, null, 0, s5, s0
s_mov_b64 s[0:1], 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v7, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v3, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 12
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cmp_lg_u32 s0, 12
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v7, v9
global_store_b32 v[0:1], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14multiplicacionPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14multiplicacionPf, .Lfunc_end0-_Z14multiplicacionPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected dev_A
.type dev_A,@object
.section .bss,"aw",@nobits
.globl dev_A
.p2align 4, 0x0
dev_A:
.zero 36
.size dev_A, 36
.protected dev_B
.type dev_B,@object
.globl dev_B
.p2align 4, 0x0
dev_B:
.zero 36
.size dev_B, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym dev_A
.addrsig_sym dev_B
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14multiplicacionPf
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14multiplicacionPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#include <hip/device_functions.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 3
/*
multiplicacion de matrices con memoria constante
*/
// definicion de memoria constante CUDA
__constant__ float dev_A[N][N];
__constant__ float dev_B[N][N];
//GLOBAL: func desde el host y ejecutada en el kernel(DEVICE)
__global__ void multiplicacion(float *dev_C)
{
int suma = 0;
int columna = threadIdx.x;
int fila = threadIdx.y;
int pos = columna + N * fila;
if (columna < N && fila < N)
{
for (int k = 0; k < N; k++)
{
dev_C[pos] += dev_A[fila][k] * dev_B[k][columna];
}
}
}
int main(int argc, char** argv)
{
float *hst_A, *hst_B, *hst_C;
float *dev_C;
int size = N * N * sizeof(float);
//reserva de memoria en el host
hst_A = (float*)malloc(size);
hst_B = (float*)malloc(size);
hst_C = (float*)malloc(size);
//reserva de memoria en el device
hipMalloc((void**)&dev_C, size);
//llenar la matriz
for (int i = 0; i < N*N; i++)
{
hst_A[i] = float(i) + 1;
hst_B[i] = float(i);
}
//copiar los datos hacia el device desde memoria constante
hipError_t error = hipMemcpyToSymbol(HIP_SYMBOL(dev_A), hst_A, size);
if (error != hipSuccess) {
printf("Error Memoria constante dev_A to hst_A\n");
}
error = hipMemcpyToSymbol(HIP_SYMBOL(dev_B), hst_B, size);
if (error != hipSuccess) {
printf("Error Memoria constante dev_B to hst_B\n");
}
//dimensiones del kernel a lanzar
dim3 bloques(1);
dim3 hilos(N, N);
//lanzamiento del kernel
multiplicacion <<<bloques, hilos >>> (dev_C);
//recoger los datos
hipMemcpy(hst_C, dev_C, size, hipMemcpyDeviceToHost);
//impresion de los datos
printf("\nMatriz A:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_A[j + i * N]);
}
printf("\n");
}
printf("\nMatriz B:\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_B[j + i * N]);
}
printf("\n");
}
printf("\n");
printf("multiplicacion de matrices A y B:\n");
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
printf("%.2f\t", hst_C[j + i * N]);
}
printf("\n");
}
printf("\n pulsa INTRO para salir:\n");
fflush(stdin);
char tecla = getchar();
return 0;
} | .text
.file "ejercicio8.hip"
.globl _Z29__device_stub__multiplicacionPf # -- Begin function _Z29__device_stub__multiplicacionPf
.p2align 4, 0x90
.type _Z29__device_stub__multiplicacionPf,@function
_Z29__device_stub__multiplicacionPf: # @_Z29__device_stub__multiplicacionPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14multiplicacionPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__multiplicacionPf, .Lfunc_end0-_Z29__device_stub__multiplicacionPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $36, %edi
callq malloc
movq %rax, %r15
movl $36, %edi
callq malloc
movq %rax, %r14
movl $36, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $36, %esi
callq hipMalloc
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm1, (%r14,%rax,4)
addss %xmm0, %xmm1
movss %xmm1, (%r15,%rax,4)
incq %rax
cmpq $9, %rax
jne .LBB1_1
# %bb.2:
movl $dev_A, %edi
movl $36, %edx
movq %r15, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_4:
movl $dev_B, %edi
movl $36, %edx
movq %r14, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_6:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $12884901891, %rdx # imm = 0x300000003
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14multiplicacionPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
movl $36, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # %.preheader66
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r13
cmpq $3, %r13
jne .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $12, %r15
cmpq $3, %r12
jne .LBB1_9
# %bb.12:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_13: # %.preheader65
# =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_14: # Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_14
# %bb.15: # in Loop: Header=BB1_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $12, %r14
cmpq $3, %r15
jne .LBB1_13
# %bb.16:
movl $10, %edi
callq putchar@PLT
movl $.Lstr.4, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_18: # Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r15
cmpq $3, %r15
jne .LBB1_18
# %bb.19: # in Loop: Header=BB1_17 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $12, %rbx
cmpq $3, %r14
jne .LBB1_17
# %bb.20:
movl $.Lstr.5, %edi
callq puts@PLT
movq stdin(%rip), %rdi
callq fflush
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14multiplicacionPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $dev_A, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_B, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_A,@object # @dev_A
.local dev_A
.comm dev_A,36,16
.type dev_B,@object # @dev_B
.local dev_B
.comm dev_B,36,16
.type _Z14multiplicacionPf,@object # @_Z14multiplicacionPf
.section .rodata,"a",@progbits
.globl _Z14multiplicacionPf
.p2align 3, 0x0
_Z14multiplicacionPf:
.quad _Z29__device_stub__multiplicacionPf
.size _Z14multiplicacionPf, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%.2f\t"
.size .L.str.3, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14multiplicacionPf"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "dev_A"
.size .L__unnamed_2, 6
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "dev_B"
.size .L__unnamed_3, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error Memoria constante dev_A to hst_A"
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error Memoria constante dev_B to hst_B"
.size .Lstr.1, 39
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nMatriz A:"
.size .Lstr.2, 11
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nMatriz B:"
.size .Lstr.3, 11
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "multiplicacion de matrices A y B:"
.size .Lstr.4, 34
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\n pulsa INTRO para salir:"
.size .Lstr.5, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__multiplicacionPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_A
.addrsig_sym dev_B
.addrsig_sym _Z14multiplicacionPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14multiplicacionPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0020*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GT.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x001fc80003f04270 */
/*0040*/ ISETP.GT.OR P0, PT, R4, 0x2, P0 ; /* 0x000000020400780c */
/* 0x002fda0000704670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD R2, R5, 0x3, R4 ; /* 0x0000000305027824 */
/* 0x000fe200078e0204 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD R0, R5, 0xc, RZ ; /* 0x0000000c05007824 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD R4, R4, R9, c[0x2][0x0] ; /* 0x0080000004047624 */
/* 0x000fe400078e0209 */
/*00d0*/ LDC R6, c[0x3][R0] ; /* 0x00c0000000067b82 */
/* 0x000eb00000000800 */
/*00e0*/ LDC R5, c[0x3][R4] ; /* 0x00c0000004057b82 */
/* 0x000eb00000000800 */
/*00f0*/ LDC R9, c[0x3][R0+0x4] ; /* 0x00c0010000097b82 */
/* 0x000e300000000800 */
/*0100*/ LDC R8, c[0x3][R4+0xc] ; /* 0x00c0030004087b82 */
/* 0x000e300000000800 */
/*0110*/ LDC R11, c[0x3][R0+0x8] ; /* 0x00c00200000b7b82 */
/* 0x000e700000000800 */
/*0120*/ LDC R10, c[0x3][R4+0x18] ; /* 0x00c00600040a7b82 */
/* 0x000e620000000800 */
/*0130*/ FFMA R5, R5, R6, R7 ; /* 0x0000000605057223 */
/* 0x004fc80000000007 */
/*0140*/ FFMA R5, R8, R9, R5 ; /* 0x0000000908057223 */
/* 0x001fc80000000005 */
/*0150*/ FFMA R5, R10, R11, R5 ; /* 0x0000000b0a057223 */
/* 0x002fca0000000005 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14multiplicacionPf
.globl _Z14multiplicacionPf
.p2align 8
.type _Z14multiplicacionPf,@function
_Z14multiplicacionPf:
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_u32_e32 v0, v1, v4
v_cmpx_gt_u32_e32 3, v0
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_u32_u24_e32 v0, 3, v4
v_lshlrev_b32_e32 v5, 2, v1
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dev_A@rel32@lo+4
s_addc_u32 s3, s3, dev_A@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, dev_B@rel32@lo+4
s_addc_u32 s5, s5, dev_B@rel32@hi+12
v_mad_u64_u32 v[2:3], null, v4, 12, s[2:3]
v_add_lshl_u32 v0, v0, v1, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v6, v0, s[0:1]
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_add_co_u32 v4, s0, v5, s4
v_add_co_ci_u32_e64 v5, null, 0, s5, s0
s_mov_b64 s[0:1], 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v7, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v3, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 12
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cmp_lg_u32 s0, 12
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v7, v9
global_store_b32 v[0:1], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14multiplicacionPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14multiplicacionPf, .Lfunc_end0-_Z14multiplicacionPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected dev_A
.type dev_A,@object
.section .bss,"aw",@nobits
.globl dev_A
.p2align 4, 0x0
dev_A:
.zero 36
.size dev_A, 36
.protected dev_B
.type dev_B,@object
.globl dev_B
.p2align 4, 0x0
dev_B:
.zero 36
.size dev_B, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym dev_A
.addrsig_sym dev_B
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14multiplicacionPf
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14multiplicacionPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003f457_00000000-6_ejercicio8.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14multiplicacionPfPf
.type _Z34__device_stub__Z14multiplicacionPfPf, @function
_Z34__device_stub__Z14multiplicacionPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14multiplicacionPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z14multiplicacionPfPf, .-_Z34__device_stub__Z14multiplicacionPfPf
.globl _Z14multiplicacionPf
.type _Z14multiplicacionPf, @function
_Z14multiplicacionPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14multiplicacionPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14multiplicacionPf, .-_Z14multiplicacionPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Error Memoria constante dev_A to hst_A\n"
.align 8
.LC2:
.string "Error Memoria constante dev_B to hst_B\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\nMatriz A:\n"
.LC4:
.string "%.2f\t"
.LC5:
.string "\n"
.LC6:
.string "\nMatriz B:\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "multiplicacion de matrices A y B:\n"
.section .rodata.str1.1
.LC8:
.string "\n pulsa INTRO para salir:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $36, %edi
call malloc@PLT
movq %rax, %r12
movl $36, %edi
call malloc@PLT
movq %rax, %rbp
movl $36, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 24(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm2
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movaps %xmm0, %xmm1
addss %xmm2, %xmm1
movss %xmm1, (%r12,%rax,4)
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $9, %rax
jne .L12
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
movq %r12, %rsi
leaq _ZL5dev_A(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L31
.L13:
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
movq %rbp, %rsi
leaq _ZL5dev_B(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L32
.L14:
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $3, 44(%rsp)
movl $3, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L15:
movl $2, %ecx
movl $36, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r15
jmp .L16
.L31:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L32:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L33:
movq 24(%rsp), %rdi
call _Z34__device_stub__Z14multiplicacionPfPf
jmp .L15
.L34:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r14d
addq $12, %r12
cmpl $9, %r14d
je .L18
.L16:
movl $0, %ebx
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L17
jmp .L34
.L18:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC4(%rip), %r12
leaq .LC5(%rip), %r14
jmp .L19
.L35:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r13d
addq $12, %rbp
cmpl $9, %r13d
je .L21
.L19:
movl $0, %ebx
.L20:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L20
jmp .L35
.L21:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rbp
movl $0, %r13d
leaq .LC4(%rip), %r12
leaq .LC5(%rip), %r14
jmp .L22
.L36:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r13d
addq $12, %rbp
cmpl $9, %r13d
je .L24
.L22:
movl $0, %ebx
.L23:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L23
jmp .L36
.L24:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call fflush@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z14multiplicacionPf"
.LC10:
.string "dev_A"
.LC11:
.string "dev_B"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z14multiplicacionPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_A(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_B(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5dev_B
.comm _ZL5dev_B,36,32
.local _ZL5dev_A
.comm _ZL5dev_A,36,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ejercicio8.hip"
.globl _Z29__device_stub__multiplicacionPf # -- Begin function _Z29__device_stub__multiplicacionPf
.p2align 4, 0x90
.type _Z29__device_stub__multiplicacionPf,@function
_Z29__device_stub__multiplicacionPf: # @_Z29__device_stub__multiplicacionPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14multiplicacionPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__multiplicacionPf, .Lfunc_end0-_Z29__device_stub__multiplicacionPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $36, %edi
callq malloc
movq %rax, %r15
movl $36, %edi
callq malloc
movq %rax, %r14
movl $36, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $36, %esi
callq hipMalloc
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm1, (%r14,%rax,4)
addss %xmm0, %xmm1
movss %xmm1, (%r15,%rax,4)
incq %rax
cmpq $9, %rax
jne .LBB1_1
# %bb.2:
movl $dev_A, %edi
movl $36, %edx
movq %r15, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_4:
movl $dev_B, %edi
movl $36, %edx
movq %r14, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_6:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $12884901891, %rdx # imm = 0x300000003
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14multiplicacionPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
movl $36, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # %.preheader66
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r13
cmpq $3, %r13
jne .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $12, %r15
cmpq $3, %r12
jne .LBB1_9
# %bb.12:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_13: # %.preheader65
# =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_14: # Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_14
# %bb.15: # in Loop: Header=BB1_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $12, %r14
cmpq $3, %r15
jne .LBB1_13
# %bb.16:
movl $10, %edi
callq putchar@PLT
movl $.Lstr.4, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_18: # Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r15
cmpq $3, %r15
jne .LBB1_18
# %bb.19: # in Loop: Header=BB1_17 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $12, %rbx
cmpq $3, %r14
jne .LBB1_17
# %bb.20:
movl $.Lstr.5, %edi
callq puts@PLT
movq stdin(%rip), %rdi
callq fflush
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14multiplicacionPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $dev_A, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dev_B, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_A,@object # @dev_A
.local dev_A
.comm dev_A,36,16
.type dev_B,@object # @dev_B
.local dev_B
.comm dev_B,36,16
.type _Z14multiplicacionPf,@object # @_Z14multiplicacionPf
.section .rodata,"a",@progbits
.globl _Z14multiplicacionPf
.p2align 3, 0x0
_Z14multiplicacionPf:
.quad _Z29__device_stub__multiplicacionPf
.size _Z14multiplicacionPf, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%.2f\t"
.size .L.str.3, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14multiplicacionPf"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "dev_A"
.size .L__unnamed_2, 6
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "dev_B"
.size .L__unnamed_3, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error Memoria constante dev_A to hst_A"
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error Memoria constante dev_B to hst_B"
.size .Lstr.1, 39
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nMatriz A:"
.size .Lstr.2, 11
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nMatriz B:"
.size .Lstr.3, 11
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "multiplicacion de matrices A y B:"
.size .Lstr.4, 34
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\n pulsa INTRO para salir:"
.size .Lstr.5, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__multiplicacionPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_A
.addrsig_sym dev_B
.addrsig_sym _Z14multiplicacionPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#define R 3
#define BLOCK_SIZE 5 // number of output elements calculated in one block
int iDivUp(int a, int b){ return ((a % b) != 0) ? (a / b + 1) : (a / b); }
__global__ void oneD_stencil_shared(int *in_arr, int *out_arr, int n_input) {
// we declare a shared memory within a block, s.t. input elements don't have to be loaded from global memory several times
// reading from shared memory is faster!
__shared__ int temp_buffer[BLOCK_SIZE + 2*R];
int gindex = R + blockDim.x*blockIdx.x + threadIdx.x;
int lindex = R + threadIdx.x;
if(gindex < n_input){
temp_buffer[lindex] = in_arr[gindex];
if(threadIdx.x < R){
temp_buffer[lindex-R] = in_arr[gindex-R];
temp_buffer[lindex + BLOCK_SIZE] = in_arr[gindex + BLOCK_SIZE];
}
}
// until this point we want the shared buffer to be filled, we wait
__syncthreads();
int res = 0;
for(int i=-R; i<=R; ++i){
res += temp_buffer[lindex + i];
}
int oindex = gindex - R;
out_arr[oindex] = res;
}
int main(void) {
int device;
cudaGetDevice(&device);
struct cudaDeviceProp props;
cudaGetDeviceProperties(&props, device);
printf("Using %s.\n\n", props.name);
// host copies of input and output array
int arr_in[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13};
int in_elements = 13;
int in_size = in_elements*sizeof(int);
int *arr_out;
int out_elements = in_elements-(2*R+1)+1;
int out_size = out_elements*sizeof(int);
arr_out = (int *)malloc(out_size);
int *d_arr_in, *d_arr_out; // host copies of input and output array
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_arr_in, in_size);
cudaMalloc((void **)&d_arr_out, out_size);
// Copy inputs to device
cudaMemcpy(d_arr_in, arr_in, in_size, cudaMemcpyHostToDevice);
// Launch stencil() kernel on GPU
int n_blocks = iDivUp(in_elements, BLOCK_SIZE);
int n_threads_per_block = BLOCK_SIZE;
oneD_stencil_shared<<<n_blocks, n_threads_per_block>>>(d_arr_in, d_arr_out, in_elements);
// Copy result back to host
cudaMemcpy(arr_out, d_arr_out, out_size, cudaMemcpyDeviceToHost);
std::cout << "[";
for(int i=0; i<out_elements; ++i){
std::cout << arr_out[i] << ", ";
}
std::cout << "]" << std::endl;
// Cleanup
cudaFree(d_arr_in); cudaFree(d_arr_out);
return 0;
} | code for sm_80
Function : _Z19oneD_stencil_sharedPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0209 */
/*0060*/ IADD3 R2, R0, 0x3, RZ ; /* 0x0000000300027810 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x120 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f04070 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ @!P0 LDG.E R5, [R2.64+-0xc] ; /* 0xfffff40402058981 */
/* 0x000ee8000c1e1900 */
/*00e0*/ @!P0 LDG.E R6, [R2.64+0x14] ; /* 0x0000140402068981 */
/* 0x000f28000c1e1900 */
/*00f0*/ STS [R9.X4+0xc], R4 ; /* 0x00000c0409007388 */
/* 0x0041e80000004800 */
/*0100*/ @!P0 STS [R9.X4], R5 ; /* 0x0000000509008388 */
/* 0x0081e80000004800 */
/*0110*/ @!P0 STS [R9.X4+0x20], R6 ; /* 0x0000200609008388 */
/* 0x0101e40000004800 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R2, [R9.X4+0x4] ; /* 0x0000040009027984 */
/* 0x000fe80000004800 */
/*0150*/ LDS R3, [R9.X4] ; /* 0x0000000009037984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R4, [R9.X4+0x8] ; /* 0x0000080009047984 */
/* 0x001e280000004800 */
/*0170*/ LDS R5, [R9.X4+0xc] ; /* 0x00000c0009057984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R6, [R9.X4+0x10] ; /* 0x0000100009067984 */
/* 0x000e680000004800 */
/*0190*/ LDS R8, [R9.X4+0x14] ; /* 0x0000140009087984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS R7, [R9.X4+0x18] ; /* 0x0000180009077984 */
/* 0x000ea20000004800 */
/*01b0*/ IADD3 R2, R4, R2, R3 ; /* 0x0000000204027210 */
/* 0x001fe20007ffe003 */
/*01c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*01d0*/ IADD3 R5, R6, R5, R2 ; /* 0x0000000506057210 */
/* 0x002fe20007ffe002 */
/*01e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e0203 */
/*01f0*/ IADD3 R5, R7, R8, R5 ; /* 0x0000000807057210 */
/* 0x004fca0007ffe005 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#define R 3
#define BLOCK_SIZE 5 // number of output elements calculated in one block
int iDivUp(int a, int b){ return ((a % b) != 0) ? (a / b + 1) : (a / b); }
__global__ void oneD_stencil_shared(int *in_arr, int *out_arr, int n_input) {
// we declare a shared memory within a block, s.t. input elements don't have to be loaded from global memory several times
// reading from shared memory is faster!
__shared__ int temp_buffer[BLOCK_SIZE + 2*R];
int gindex = R + blockDim.x*blockIdx.x + threadIdx.x;
int lindex = R + threadIdx.x;
if(gindex < n_input){
temp_buffer[lindex] = in_arr[gindex];
if(threadIdx.x < R){
temp_buffer[lindex-R] = in_arr[gindex-R];
temp_buffer[lindex + BLOCK_SIZE] = in_arr[gindex + BLOCK_SIZE];
}
}
// until this point we want the shared buffer to be filled, we wait
__syncthreads();
int res = 0;
for(int i=-R; i<=R; ++i){
res += temp_buffer[lindex + i];
}
int oindex = gindex - R;
out_arr[oindex] = res;
}
int main(void) {
int device;
cudaGetDevice(&device);
struct cudaDeviceProp props;
cudaGetDeviceProperties(&props, device);
printf("Using %s.\n\n", props.name);
// host copies of input and output array
int arr_in[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13};
int in_elements = 13;
int in_size = in_elements*sizeof(int);
int *arr_out;
int out_elements = in_elements-(2*R+1)+1;
int out_size = out_elements*sizeof(int);
arr_out = (int *)malloc(out_size);
int *d_arr_in, *d_arr_out; // host copies of input and output array
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_arr_in, in_size);
cudaMalloc((void **)&d_arr_out, out_size);
// Copy inputs to device
cudaMemcpy(d_arr_in, arr_in, in_size, cudaMemcpyHostToDevice);
// Launch stencil() kernel on GPU
int n_blocks = iDivUp(in_elements, BLOCK_SIZE);
int n_threads_per_block = BLOCK_SIZE;
oneD_stencil_shared<<<n_blocks, n_threads_per_block>>>(d_arr_in, d_arr_out, in_elements);
// Copy result back to host
cudaMemcpy(arr_out, d_arr_out, out_size, cudaMemcpyDeviceToHost);
std::cout << "[";
for(int i=0; i<out_elements; ++i){
std::cout << arr_out[i] << ", ";
}
std::cout << "]" << std::endl;
// Cleanup
cudaFree(d_arr_in); cudaFree(d_arr_out);
return 0;
} | .file "tmpxft_0003a8b3_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6iDivUpii
.type _Z6iDivUpii, @function
_Z6iDivUpii:
.LFB3669:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
testl %edx, %edx
je .L4
movl %edi, %eax
cltd
idivl %esi
addl $1, %eax
ret
.L4:
movl %edi, %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE3669:
.size _Z6iDivUpii, .-_Z6iDivUpii
.globl _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i
.type _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i, @function
_Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19oneD_stencil_sharedPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i, .-_Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i
.globl _Z19oneD_stencil_sharedPiS_i
.type _Z19oneD_stencil_sharedPiS_i, @function
_Z19oneD_stencil_sharedPiS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z19oneD_stencil_sharedPiS_i, .-_Z19oneD_stencil_sharedPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Using %s.\n\n"
.LC1:
.string "["
.LC2:
.string ", "
.LC3:
.string "]"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1160, %rsp
.cfi_def_cfa_offset 1200
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq 112(%rsp), %rbx
movl 4(%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $6, 68(%rsp)
movl $7, 72(%rsp)
movl $8, 76(%rsp)
movl $9, 80(%rsp)
movl $10, 84(%rsp)
movl $11, 88(%rsp)
movl $12, 92(%rsp)
movl $13, 96(%rsp)
movl $28, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $52, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $52, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
movl $2, %ecx
movl $28, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rbx
addq $28, %rbp
leaq _ZSt4cout(%rip), %r13
leaq .LC2(%rip), %r12
.L16:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L16
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl $13, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z19oneD_stencil_sharedPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19oneD_stencil_sharedPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#define R 3
#define BLOCK_SIZE 5 // number of output elements calculated in one block
int iDivUp(int a, int b){ return ((a % b) != 0) ? (a / b + 1) : (a / b); }
__global__ void oneD_stencil_shared(int *in_arr, int *out_arr, int n_input) {
// we declare a shared memory within a block, s.t. input elements don't have to be loaded from global memory several times
// reading from shared memory is faster!
__shared__ int temp_buffer[BLOCK_SIZE + 2*R];
int gindex = R + blockDim.x*blockIdx.x + threadIdx.x;
int lindex = R + threadIdx.x;
if(gindex < n_input){
temp_buffer[lindex] = in_arr[gindex];
if(threadIdx.x < R){
temp_buffer[lindex-R] = in_arr[gindex-R];
temp_buffer[lindex + BLOCK_SIZE] = in_arr[gindex + BLOCK_SIZE];
}
}
// until this point we want the shared buffer to be filled, we wait
__syncthreads();
int res = 0;
for(int i=-R; i<=R; ++i){
res += temp_buffer[lindex + i];
}
int oindex = gindex - R;
out_arr[oindex] = res;
}
int main(void) {
int device;
cudaGetDevice(&device);
struct cudaDeviceProp props;
cudaGetDeviceProperties(&props, device);
printf("Using %s.\n\n", props.name);
// host copies of input and output array
int arr_in[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13};
int in_elements = 13;
int in_size = in_elements*sizeof(int);
int *arr_out;
int out_elements = in_elements-(2*R+1)+1;
int out_size = out_elements*sizeof(int);
arr_out = (int *)malloc(out_size);
int *d_arr_in, *d_arr_out; // host copies of input and output array
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_arr_in, in_size);
cudaMalloc((void **)&d_arr_out, out_size);
// Copy inputs to device
cudaMemcpy(d_arr_in, arr_in, in_size, cudaMemcpyHostToDevice);
// Launch stencil() kernel on GPU
int n_blocks = iDivUp(in_elements, BLOCK_SIZE);
int n_threads_per_block = BLOCK_SIZE;
oneD_stencil_shared<<<n_blocks, n_threads_per_block>>>(d_arr_in, d_arr_out, in_elements);
// Copy result back to host
cudaMemcpy(arr_out, d_arr_out, out_size, cudaMemcpyDeviceToHost);
std::cout << "[";
for(int i=0; i<out_elements; ++i){
std::cout << arr_out[i] << ", ";
}
std::cout << "]" << std::endl;
// Cleanup
cudaFree(d_arr_in); cudaFree(d_arr_out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#define R 3
#define BLOCK_SIZE 5 // number of output elements calculated in one block
int iDivUp(int a, int b){ return ((a % b) != 0) ? (a / b + 1) : (a / b); }
__global__ void oneD_stencil_shared(int *in_arr, int *out_arr, int n_input) {
// we declare a shared memory within a block, s.t. input elements don't have to be loaded from global memory several times
// reading from shared memory is faster!
__shared__ int temp_buffer[BLOCK_SIZE + 2*R];
int gindex = R + blockDim.x*blockIdx.x + threadIdx.x;
int lindex = R + threadIdx.x;
if(gindex < n_input){
temp_buffer[lindex] = in_arr[gindex];
if(threadIdx.x < R){
temp_buffer[lindex-R] = in_arr[gindex-R];
temp_buffer[lindex + BLOCK_SIZE] = in_arr[gindex + BLOCK_SIZE];
}
}
// until this point we want the shared buffer to be filled, we wait
__syncthreads();
int res = 0;
for(int i=-R; i<=R; ++i){
res += temp_buffer[lindex + i];
}
int oindex = gindex - R;
out_arr[oindex] = res;
}
int main(void) {
int device;
hipGetDevice(&device);
struct hipDeviceProp_t props;
hipGetDeviceProperties(&props, device);
printf("Using %s.\n\n", props.name);
// host copies of input and output array
int arr_in[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13};
int in_elements = 13;
int in_size = in_elements*sizeof(int);
int *arr_out;
int out_elements = in_elements-(2*R+1)+1;
int out_size = out_elements*sizeof(int);
arr_out = (int *)malloc(out_size);
int *d_arr_in, *d_arr_out; // host copies of input and output array
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_arr_in, in_size);
hipMalloc((void **)&d_arr_out, out_size);
// Copy inputs to device
hipMemcpy(d_arr_in, arr_in, in_size, hipMemcpyHostToDevice);
// Launch stencil() kernel on GPU
int n_blocks = iDivUp(in_elements, BLOCK_SIZE);
int n_threads_per_block = BLOCK_SIZE;
oneD_stencil_shared<<<n_blocks, n_threads_per_block>>>(d_arr_in, d_arr_out, in_elements);
// Copy result back to host
hipMemcpy(arr_out, d_arr_out, out_size, hipMemcpyDeviceToHost);
std::cout << "[";
for(int i=0; i<out_elements; ++i){
std::cout << arr_out[i] << ", ";
}
std::cout << "]" << std::endl;
// Cleanup
hipFree(d_arr_in); hipFree(d_arr_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#define R 3
#define BLOCK_SIZE 5 // number of output elements calculated in one block
int iDivUp(int a, int b){ return ((a % b) != 0) ? (a / b + 1) : (a / b); }
__global__ void oneD_stencil_shared(int *in_arr, int *out_arr, int n_input) {
// we declare a shared memory within a block, s.t. input elements don't have to be loaded from global memory several times
// reading from shared memory is faster!
__shared__ int temp_buffer[BLOCK_SIZE + 2*R];
int gindex = R + blockDim.x*blockIdx.x + threadIdx.x;
int lindex = R + threadIdx.x;
if(gindex < n_input){
temp_buffer[lindex] = in_arr[gindex];
if(threadIdx.x < R){
temp_buffer[lindex-R] = in_arr[gindex-R];
temp_buffer[lindex + BLOCK_SIZE] = in_arr[gindex + BLOCK_SIZE];
}
}
// until this point we want the shared buffer to be filled, we wait
__syncthreads();
int res = 0;
for(int i=-R; i<=R; ++i){
res += temp_buffer[lindex + i];
}
int oindex = gindex - R;
out_arr[oindex] = res;
}
int main(void) {
int device;
hipGetDevice(&device);
struct hipDeviceProp_t props;
hipGetDeviceProperties(&props, device);
printf("Using %s.\n\n", props.name);
// host copies of input and output array
int arr_in[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13};
int in_elements = 13;
int in_size = in_elements*sizeof(int);
int *arr_out;
int out_elements = in_elements-(2*R+1)+1;
int out_size = out_elements*sizeof(int);
arr_out = (int *)malloc(out_size);
int *d_arr_in, *d_arr_out; // host copies of input and output array
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_arr_in, in_size);
hipMalloc((void **)&d_arr_out, out_size);
// Copy inputs to device
hipMemcpy(d_arr_in, arr_in, in_size, hipMemcpyHostToDevice);
// Launch stencil() kernel on GPU
int n_blocks = iDivUp(in_elements, BLOCK_SIZE);
int n_threads_per_block = BLOCK_SIZE;
oneD_stencil_shared<<<n_blocks, n_threads_per_block>>>(d_arr_in, d_arr_out, in_elements);
// Copy result back to host
hipMemcpy(arr_out, d_arr_out, out_size, hipMemcpyDeviceToHost);
std::cout << "[";
for(int i=0; i<out_elements; ++i){
std::cout << arr_out[i] << ", ";
}
std::cout << "]" << std::endl;
// Cleanup
hipFree(d_arr_in); hipFree(d_arr_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19oneD_stencil_sharedPiS_i
.globl _Z19oneD_stencil_sharedPiS_i
.p2align 8
.type _Z19oneD_stencil_sharedPiS_i,@function
_Z19oneD_stencil_sharedPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_add3_u32 v1, s15, v0, 3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, 3, v0
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4 offset:12
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v4, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v1, v[1:2], off offset:20
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v4, v1 offset1:8
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_4:
v_add_nc_u32_e32 v3, s2, v2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 28
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v3, v1
s_cbranch_scc0 .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
v_add_nc_u32_e32 v2, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19oneD_stencil_sharedPiS_i
.amdhsa_group_segment_fixed_size 44
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19oneD_stencil_sharedPiS_i, .Lfunc_end0-_Z19oneD_stencil_sharedPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 44
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19oneD_stencil_sharedPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19oneD_stencil_sharedPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#define R 3
#define BLOCK_SIZE 5 // number of output elements calculated in one block
int iDivUp(int a, int b){ return ((a % b) != 0) ? (a / b + 1) : (a / b); }
__global__ void oneD_stencil_shared(int *in_arr, int *out_arr, int n_input) {
// we declare a shared memory within a block, s.t. input elements don't have to be loaded from global memory several times
// reading from shared memory is faster!
__shared__ int temp_buffer[BLOCK_SIZE + 2*R];
int gindex = R + blockDim.x*blockIdx.x + threadIdx.x;
int lindex = R + threadIdx.x;
if(gindex < n_input){
temp_buffer[lindex] = in_arr[gindex];
if(threadIdx.x < R){
temp_buffer[lindex-R] = in_arr[gindex-R];
temp_buffer[lindex + BLOCK_SIZE] = in_arr[gindex + BLOCK_SIZE];
}
}
// until this point we want the shared buffer to be filled, we wait
__syncthreads();
int res = 0;
for(int i=-R; i<=R; ++i){
res += temp_buffer[lindex + i];
}
int oindex = gindex - R;
out_arr[oindex] = res;
}
int main(void) {
int device;
hipGetDevice(&device);
struct hipDeviceProp_t props;
hipGetDeviceProperties(&props, device);
printf("Using %s.\n\n", props.name);
// host copies of input and output array
int arr_in[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13};
int in_elements = 13;
int in_size = in_elements*sizeof(int);
int *arr_out;
int out_elements = in_elements-(2*R+1)+1;
int out_size = out_elements*sizeof(int);
arr_out = (int *)malloc(out_size);
int *d_arr_in, *d_arr_out; // host copies of input and output array
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_arr_in, in_size);
hipMalloc((void **)&d_arr_out, out_size);
// Copy inputs to device
hipMemcpy(d_arr_in, arr_in, in_size, hipMemcpyHostToDevice);
// Launch stencil() kernel on GPU
int n_blocks = iDivUp(in_elements, BLOCK_SIZE);
int n_threads_per_block = BLOCK_SIZE;
oneD_stencil_shared<<<n_blocks, n_threads_per_block>>>(d_arr_in, d_arr_out, in_elements);
// Copy result back to host
hipMemcpy(arr_out, d_arr_out, out_size, hipMemcpyDeviceToHost);
std::cout << "[";
for(int i=0; i<out_elements; ++i){
std::cout << arr_out[i] << ", ";
}
std::cout << "]" << std::endl;
// Cleanup
hipFree(d_arr_in); hipFree(d_arr_out);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6iDivUpii # -- Begin function _Z6iDivUpii
.p2align 4, 0x90
.type _Z6iDivUpii,@function
_Z6iDivUpii: # @_Z6iDivUpii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
retq
.Lfunc_end0:
.size _Z6iDivUpii, .Lfunc_end0-_Z6iDivUpii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__oneD_stencil_sharedPiS_i # -- Begin function _Z34__device_stub__oneD_stencil_sharedPiS_i
.p2align 4, 0x90
.type _Z34__device_stub__oneD_stencil_sharedPiS_i,@function
_Z34__device_stub__oneD_stencil_sharedPiS_i: # @_Z34__device_stub__oneD_stencil_sharedPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19oneD_stencil_sharedPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__oneD_stencil_sharedPiS_i, .Lfunc_end1-_Z34__device_stub__oneD_stencil_sharedPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI2_1:
.long 5 # 0x5
.long 6 # 0x6
.long 7 # 0x7
.long 8 # 0x8
.LCPI2_2:
.long 9 # 0x9
.long 10 # 0xa
.long 11 # 0xb
.long 12 # 0xc
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 1680
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
callq hipGetDevice
movl 24(%rsp), %esi
leaq 184(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 128(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [5,6,7,8]
movaps %xmm0, 144(%rsp)
movaps .LCPI2_2(%rip), %xmm0 # xmm0 = [9,10,11,12]
movaps %xmm0, 160(%rsp)
movl $13, 176(%rsp)
movl $28, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $52, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $28, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $52, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 2(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $13, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19oneD_stencil_sharedPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movl $28, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $7, %r14
jne .LBB2_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB2_8
.LBB2_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 1680
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19oneD_stencil_sharedPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19oneD_stencil_sharedPiS_i,@object # @_Z19oneD_stencil_sharedPiS_i
.section .rodata,"a",@progbits
.globl _Z19oneD_stencil_sharedPiS_i
.p2align 3, 0x0
_Z19oneD_stencil_sharedPiS_i:
.quad _Z34__device_stub__oneD_stencil_sharedPiS_i
.size _Z19oneD_stencil_sharedPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Using %s.\n\n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "["
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "]"
.size .L.str.3, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19oneD_stencil_sharedPiS_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__oneD_stencil_sharedPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19oneD_stencil_sharedPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19oneD_stencil_sharedPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0209 */
/*0060*/ IADD3 R2, R0, 0x3, RZ ; /* 0x0000000300027810 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x120 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f04070 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ @!P0 LDG.E R5, [R2.64+-0xc] ; /* 0xfffff40402058981 */
/* 0x000ee8000c1e1900 */
/*00e0*/ @!P0 LDG.E R6, [R2.64+0x14] ; /* 0x0000140402068981 */
/* 0x000f28000c1e1900 */
/*00f0*/ STS [R9.X4+0xc], R4 ; /* 0x00000c0409007388 */
/* 0x0041e80000004800 */
/*0100*/ @!P0 STS [R9.X4], R5 ; /* 0x0000000509008388 */
/* 0x0081e80000004800 */
/*0110*/ @!P0 STS [R9.X4+0x20], R6 ; /* 0x0000200609008388 */
/* 0x0101e40000004800 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R2, [R9.X4+0x4] ; /* 0x0000040009027984 */
/* 0x000fe80000004800 */
/*0150*/ LDS R3, [R9.X4] ; /* 0x0000000009037984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R4, [R9.X4+0x8] ; /* 0x0000080009047984 */
/* 0x001e280000004800 */
/*0170*/ LDS R5, [R9.X4+0xc] ; /* 0x00000c0009057984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R6, [R9.X4+0x10] ; /* 0x0000100009067984 */
/* 0x000e680000004800 */
/*0190*/ LDS R8, [R9.X4+0x14] ; /* 0x0000140009087984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS R7, [R9.X4+0x18] ; /* 0x0000180009077984 */
/* 0x000ea20000004800 */
/*01b0*/ IADD3 R2, R4, R2, R3 ; /* 0x0000000204027210 */
/* 0x001fe20007ffe003 */
/*01c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*01d0*/ IADD3 R5, R6, R5, R2 ; /* 0x0000000506057210 */
/* 0x002fe20007ffe002 */
/*01e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e0203 */
/*01f0*/ IADD3 R5, R7, R8, R5 ; /* 0x0000000807057210 */
/* 0x004fca0007ffe005 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19oneD_stencil_sharedPiS_i
.globl _Z19oneD_stencil_sharedPiS_i
.p2align 8
.type _Z19oneD_stencil_sharedPiS_i,@function
_Z19oneD_stencil_sharedPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_add3_u32 v1, s15, v0, 3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, 3, v0
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4 offset:12
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v4, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v1, v[1:2], off offset:20
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v4, v1 offset1:8
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_4:
v_add_nc_u32_e32 v3, s2, v2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 28
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v3, v1
s_cbranch_scc0 .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
v_add_nc_u32_e32 v2, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19oneD_stencil_sharedPiS_i
.amdhsa_group_segment_fixed_size 44
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19oneD_stencil_sharedPiS_i, .Lfunc_end0-_Z19oneD_stencil_sharedPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 44
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19oneD_stencil_sharedPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19oneD_stencil_sharedPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003a8b3_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6iDivUpii
.type _Z6iDivUpii, @function
_Z6iDivUpii:
.LFB3669:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
testl %edx, %edx
je .L4
movl %edi, %eax
cltd
idivl %esi
addl $1, %eax
ret
.L4:
movl %edi, %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE3669:
.size _Z6iDivUpii, .-_Z6iDivUpii
.globl _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i
.type _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i, @function
_Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19oneD_stencil_sharedPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i, .-_Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i
.globl _Z19oneD_stencil_sharedPiS_i
.type _Z19oneD_stencil_sharedPiS_i, @function
_Z19oneD_stencil_sharedPiS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z19oneD_stencil_sharedPiS_i, .-_Z19oneD_stencil_sharedPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Using %s.\n\n"
.LC1:
.string "["
.LC2:
.string ", "
.LC3:
.string "]"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1160, %rsp
.cfi_def_cfa_offset 1200
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq 112(%rsp), %rbx
movl 4(%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $6, 68(%rsp)
movl $7, 72(%rsp)
movl $8, 76(%rsp)
movl $9, 80(%rsp)
movl $10, 84(%rsp)
movl $11, 88(%rsp)
movl $12, 92(%rsp)
movl $13, 96(%rsp)
movl $28, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $52, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $52, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
movl $2, %ecx
movl $28, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rbx
addq $28, %rbp
leaq _ZSt4cout(%rip), %r13
leaq .LC2(%rip), %r12
.L16:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L16
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl $13, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z19oneD_stencil_sharedPiS_iPiS_i
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z19oneD_stencil_sharedPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19oneD_stencil_sharedPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6iDivUpii # -- Begin function _Z6iDivUpii
.p2align 4, 0x90
.type _Z6iDivUpii,@function
_Z6iDivUpii: # @_Z6iDivUpii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
retq
.Lfunc_end0:
.size _Z6iDivUpii, .Lfunc_end0-_Z6iDivUpii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__oneD_stencil_sharedPiS_i # -- Begin function _Z34__device_stub__oneD_stencil_sharedPiS_i
.p2align 4, 0x90
.type _Z34__device_stub__oneD_stencil_sharedPiS_i,@function
_Z34__device_stub__oneD_stencil_sharedPiS_i: # @_Z34__device_stub__oneD_stencil_sharedPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19oneD_stencil_sharedPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__oneD_stencil_sharedPiS_i, .Lfunc_end1-_Z34__device_stub__oneD_stencil_sharedPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI2_1:
.long 5 # 0x5
.long 6 # 0x6
.long 7 # 0x7
.long 8 # 0x8
.LCPI2_2:
.long 9 # 0x9
.long 10 # 0xa
.long 11 # 0xb
.long 12 # 0xc
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 1680
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
callq hipGetDevice
movl 24(%rsp), %esi
leaq 184(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 128(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [5,6,7,8]
movaps %xmm0, 144(%rsp)
movaps .LCPI2_2(%rip), %xmm0 # xmm0 = [9,10,11,12]
movaps %xmm0, 160(%rsp)
movl $13, 176(%rsp)
movl $28, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $52, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $28, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $52, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 2(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $13, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19oneD_stencil_sharedPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movl $28, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $7, %r14
jne .LBB2_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB2_8
.LBB2_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 1680
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19oneD_stencil_sharedPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19oneD_stencil_sharedPiS_i,@object # @_Z19oneD_stencil_sharedPiS_i
.section .rodata,"a",@progbits
.globl _Z19oneD_stencil_sharedPiS_i
.p2align 3, 0x0
_Z19oneD_stencil_sharedPiS_i:
.quad _Z34__device_stub__oneD_stencil_sharedPiS_i
.size _Z19oneD_stencil_sharedPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Using %s.\n\n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "["
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "]"
.size .L.str.3, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19oneD_stencil_sharedPiS_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__oneD_stencil_sharedPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19oneD_stencil_sharedPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
#define N 65536
#define A 2
#define blockSize 65
// SAXPY Kernel
// Performs A*X+Y
// Assumes single N blocks with 32 threads each
__global__ void saxpy(int *X, int *Y, int *Z){
// Need to account for different smx tid's
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid<N){
Z[tid] = A * X[tid] + Y[tid];
}
}
int main(){
int X[N], Y[N], Z[N]; // Host data: X,Y input data, Z output data
int *dev_X, *dev_Y, *dev_Z; // Device data pointers
// Allocate memory on the device/GPU
cudaMalloc((void**)&dev_X, N*sizeof(int));
cudaMalloc((void**)&dev_Y, N*sizeof(int));
cudaMalloc((void**)&dev_Z, N*sizeof(int));
// Fill input arrays
for(int i = 0; i<N; i++){
X[i] = i;
Y[i] = i*i;
}
// Copy data to the device
cudaMemcpy(dev_X,X,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_Y,Y,N*sizeof(int),cudaMemcpyHostToDevice);
// Create Event
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Cuda Kernel Call
int gridSize = (N+(blockSize-1)) / blockSize;
// (N+31) / 32
// Call Event
cudaEventRecord(start);
saxpy<<<gridSize,blockSize>>>(dev_X,dev_Y,dev_Z);
cudaEventRecord(stop);
// Copy memory off of the device
cudaMemcpy(Z,dev_Z,N*sizeof(int),cudaMemcpyDeviceToHost);
// Stop Event
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
// Check out contents of working arrays/output data
for(int i = 0; i<N; i++){
int checkValue = A * X[i] + Y[i];
if (Z[i] != checkValue) {
cout << "Mismatch " << i << endl;
}
}
// Free up memory
cudaFree(dev_X);
cudaFree(dev_Y);
cudaFree(dev_Z);
} | code for sm_80
Function : _Z5saxpyPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xffff, PT ; /* 0x0000ffff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ LEA R9, R2, R5, 0x1 ; /* 0x0000000502097211 */
/* 0x004fca00078e08ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
#define N 65536
#define A 2
#define blockSize 65
// SAXPY Kernel
// Performs A*X+Y
// Assumes single N blocks with 32 threads each
__global__ void saxpy(int *X, int *Y, int *Z){
// Need to account for different smx tid's
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid<N){
Z[tid] = A * X[tid] + Y[tid];
}
}
int main(){
int X[N], Y[N], Z[N]; // Host data: X,Y input data, Z output data
int *dev_X, *dev_Y, *dev_Z; // Device data pointers
// Allocate memory on the device/GPU
cudaMalloc((void**)&dev_X, N*sizeof(int));
cudaMalloc((void**)&dev_Y, N*sizeof(int));
cudaMalloc((void**)&dev_Z, N*sizeof(int));
// Fill input arrays
for(int i = 0; i<N; i++){
X[i] = i;
Y[i] = i*i;
}
// Copy data to the device
cudaMemcpy(dev_X,X,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_Y,Y,N*sizeof(int),cudaMemcpyHostToDevice);
// Create Event
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Cuda Kernel Call
int gridSize = (N+(blockSize-1)) / blockSize;
// (N+31) / 32
// Call Event
cudaEventRecord(start);
saxpy<<<gridSize,blockSize>>>(dev_X,dev_Y,dev_Z);
cudaEventRecord(stop);
// Copy memory off of the device
cudaMemcpy(Z,dev_Z,N*sizeof(int),cudaMemcpyDeviceToHost);
// Stop Event
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
// Check out contents of working arrays/output data
for(int i = 0; i<N; i++){
int checkValue = A * X[i] + Y[i];
if (Z[i] != checkValue) {
cout << "Mismatch " << i << endl;
}
}
// Free up memory
cudaFree(dev_X);
cudaFree(dev_Y);
cudaFree(dev_Z);
} | .file "tmpxft_00064c03_00000000-6_saxpyPerformance.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
.type _Z28__device_stub__Z5saxpyPiS_S_PiS_S_, @function
_Z28__device_stub__Z5saxpyPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z28__device_stub__Z5saxpyPiS_S_PiS_S_, .-_Z28__device_stub__Z5saxpyPiS_S_PiS_S_
.globl _Z5saxpyPiS_S_
.type _Z5saxpyPiS_S_, @function
_Z5saxpyPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5saxpyPiS_S_, .-_Z5saxpyPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Mismatch "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -786432(%rsp), %r11
.cfi_def_cfa 11, 786488
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 786576
movq %fs:40, %rax
movq %rax, 786504(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 64(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 262208(%rsp,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L12
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 262208(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $65, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1009, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 524352(%rsp), %rdi
movl $2, %ecx
movl $262144, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 52(%rsp)
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
leaq 524352(%rsp), %r12
leaq .LC1(%rip), %r14
leaq _ZSt4cout(%rip), %r13
jmp .L19
.L24:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
jmp .L13
.L27:
movq 786504(%rsp), %rax
subq %fs:40, %rax
jne .L25
call _ZSt16__throw_bad_castv@PLT
.L25:
call __stack_chk_fail@PLT
.L17:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L18:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L14:
addq $1, %rbx
cmpq $65536, %rbx
je .L26
.L19:
movl 64(%rsp,%rbx,4), %edx
movl 262208(%rsp,%rbx,4), %eax
leal (%rax,%rdx,2), %eax
cmpl %eax, (%r12,%rbx,4)
je .L14
movl $9, %edx
movq %r14, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L27
cmpb $0, 56(%r15)
je .L17
movzbl 67(%r15), %esi
jmp .L18
.L26:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 786504(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $786520, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z5saxpyPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
#define N 65536
#define A 2
#define blockSize 65
// SAXPY Kernel
// Performs A*X+Y
// Assumes single N blocks with 32 threads each
__global__ void saxpy(int *X, int *Y, int *Z){
// Need to account for different smx tid's
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid<N){
Z[tid] = A * X[tid] + Y[tid];
}
}
int main(){
int X[N], Y[N], Z[N]; // Host data: X,Y input data, Z output data
int *dev_X, *dev_Y, *dev_Z; // Device data pointers
// Allocate memory on the device/GPU
cudaMalloc((void**)&dev_X, N*sizeof(int));
cudaMalloc((void**)&dev_Y, N*sizeof(int));
cudaMalloc((void**)&dev_Z, N*sizeof(int));
// Fill input arrays
for(int i = 0; i<N; i++){
X[i] = i;
Y[i] = i*i;
}
// Copy data to the device
cudaMemcpy(dev_X,X,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_Y,Y,N*sizeof(int),cudaMemcpyHostToDevice);
// Create Event
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Cuda Kernel Call
int gridSize = (N+(blockSize-1)) / blockSize;
// (N+31) / 32
// Call Event
cudaEventRecord(start);
saxpy<<<gridSize,blockSize>>>(dev_X,dev_Y,dev_Z);
cudaEventRecord(stop);
// Copy memory off of the device
cudaMemcpy(Z,dev_Z,N*sizeof(int),cudaMemcpyDeviceToHost);
// Stop Event
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
// Check out contents of working arrays/output data
for(int i = 0; i<N; i++){
int checkValue = A * X[i] + Y[i];
if (Z[i] != checkValue) {
cout << "Mismatch " << i << endl;
}
}
// Free up memory
cudaFree(dev_X);
cudaFree(dev_Y);
cudaFree(dev_Z);
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define N 65536
#define A 2
#define blockSize 65
// SAXPY Kernel
// Performs A*X+Y
// Assumes single N blocks with 32 threads each
__global__ void saxpy(int *X, int *Y, int *Z){
// Need to account for different smx tid's
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid<N){
Z[tid] = A * X[tid] + Y[tid];
}
}
int main(){
int X[N], Y[N], Z[N]; // Host data: X,Y input data, Z output data
int *dev_X, *dev_Y, *dev_Z; // Device data pointers
// Allocate memory on the device/GPU
hipMalloc((void**)&dev_X, N*sizeof(int));
hipMalloc((void**)&dev_Y, N*sizeof(int));
hipMalloc((void**)&dev_Z, N*sizeof(int));
// Fill input arrays
for(int i = 0; i<N; i++){
X[i] = i;
Y[i] = i*i;
}
// Copy data to the device
hipMemcpy(dev_X,X,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_Y,Y,N*sizeof(int),hipMemcpyHostToDevice);
// Create Event
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Cuda Kernel Call
int gridSize = (N+(blockSize-1)) / blockSize;
// (N+31) / 32
// Call Event
hipEventRecord(start);
saxpy<<<gridSize,blockSize>>>(dev_X,dev_Y,dev_Z);
hipEventRecord(stop);
// Copy memory off of the device
hipMemcpy(Z,dev_Z,N*sizeof(int),hipMemcpyDeviceToHost);
// Stop Event
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
// Check out contents of working arrays/output data
for(int i = 0; i<N; i++){
int checkValue = A * X[i] + Y[i];
if (Z[i] != checkValue) {
cout << "Mismatch " << i << endl;
}
}
// Free up memory
hipFree(dev_X);
hipFree(dev_Y);
hipFree(dev_Z);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define N 65536
#define A 2
#define blockSize 65
// SAXPY Kernel
// Performs A*X+Y
// Assumes single N blocks with 32 threads each
__global__ void saxpy(int *X, int *Y, int *Z){
// Need to account for different smx tid's
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid<N){
Z[tid] = A * X[tid] + Y[tid];
}
}
int main(){
int X[N], Y[N], Z[N]; // Host data: X,Y input data, Z output data
int *dev_X, *dev_Y, *dev_Z; // Device data pointers
// Allocate memory on the device/GPU
hipMalloc((void**)&dev_X, N*sizeof(int));
hipMalloc((void**)&dev_Y, N*sizeof(int));
hipMalloc((void**)&dev_Z, N*sizeof(int));
// Fill input arrays
for(int i = 0; i<N; i++){
X[i] = i;
Y[i] = i*i;
}
// Copy data to the device
hipMemcpy(dev_X,X,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_Y,Y,N*sizeof(int),hipMemcpyHostToDevice);
// Create Event
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Cuda Kernel Call
int gridSize = (N+(blockSize-1)) / blockSize;
// (N+31) / 32
// Call Event
hipEventRecord(start);
saxpy<<<gridSize,blockSize>>>(dev_X,dev_Y,dev_Z);
hipEventRecord(stop);
// Copy memory off of the device
hipMemcpy(Z,dev_Z,N*sizeof(int),hipMemcpyDeviceToHost);
// Stop Event
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
// Check out contents of working arrays/output data
for(int i = 0; i<N; i++){
int checkValue = A * X[i] + Y[i];
if (Z[i] != checkValue) {
cout << "Mismatch " << i << endl;
}
}
// Free up memory
hipFree(dev_X);
hipFree(dev_Y);
hipFree(dev_Z);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPiS_S_
.globl _Z5saxpyPiS_S_
.p2align 8
.type _Z5saxpyPiS_S_,@function
_Z5saxpyPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x10000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_lshl_add_u32 v2, v2, 1, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPiS_S_, .Lfunc_end0-_Z5saxpyPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define N 65536
#define A 2
#define blockSize 65
// SAXPY Kernel
// Performs A*X+Y
// Assumes single N blocks with 32 threads each
__global__ void saxpy(int *X, int *Y, int *Z){
// Need to account for different smx tid's
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid<N){
Z[tid] = A * X[tid] + Y[tid];
}
}
int main(){
int X[N], Y[N], Z[N]; // Host data: X,Y input data, Z output data
int *dev_X, *dev_Y, *dev_Z; // Device data pointers
// Allocate memory on the device/GPU
hipMalloc((void**)&dev_X, N*sizeof(int));
hipMalloc((void**)&dev_Y, N*sizeof(int));
hipMalloc((void**)&dev_Z, N*sizeof(int));
// Fill input arrays
for(int i = 0; i<N; i++){
X[i] = i;
Y[i] = i*i;
}
// Copy data to the device
hipMemcpy(dev_X,X,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_Y,Y,N*sizeof(int),hipMemcpyHostToDevice);
// Create Event
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Cuda Kernel Call
int gridSize = (N+(blockSize-1)) / blockSize;
// (N+31) / 32
// Call Event
hipEventRecord(start);
saxpy<<<gridSize,blockSize>>>(dev_X,dev_Y,dev_Z);
hipEventRecord(stop);
// Copy memory off of the device
hipMemcpy(Z,dev_Z,N*sizeof(int),hipMemcpyDeviceToHost);
// Stop Event
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
// Check out contents of working arrays/output data
for(int i = 0; i<N; i++){
int checkValue = A * X[i] + Y[i];
if (Z[i] != checkValue) {
cout << "Mismatch " << i << endl;
}
}
// Free up memory
hipFree(dev_X);
hipFree(dev_Y);
hipFree(dev_Z);
} | .text
.file "saxpyPerformance.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__saxpyPiS_S_ # -- Begin function _Z20__device_stub__saxpyPiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPiS_S_,@function
_Z20__device_stub__saxpyPiS_S_: # @_Z20__device_stub__saxpyPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPiS_S_, .Lfunc_end0-_Z20__device_stub__saxpyPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $786544, %rsp # imm = 0xC0070
.cfi_def_cfa_offset 786576
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 524400(%rsp,%rax,4)
movl %eax, %ecx
imull %eax, %ecx
movl %ecx, 262256(%rsp,%rax,4)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
leaq 524400(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 262256(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967361, %rdx # imm = 0x100000041
leaq 944(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 48(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
jmp .LBB1_9
.LBB1_13: # in Loop: Header=BB1_9 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
# in Loop: Header=BB1_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_15: # in Loop: Header=BB1_9 Depth=1
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
je .LBB1_16
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl 524400(%rsp,%rbx,4), %eax
addl %eax, %eax
addl 262256(%rsp,%rbx,4), %eax
cmpl %eax, 112(%rsp,%rbx,4)
je .LBB1_15
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r14)
je .LBB1_13
# %bb.12: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_14
.LBB1_16:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $786544, %rsp # imm = 0xC0070
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 786576
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPiS_S_,@object # @_Z5saxpyPiS_S_
.section .rodata,"a",@progbits
.globl _Z5saxpyPiS_S_
.p2align 3, 0x0
_Z5saxpyPiS_S_:
.quad _Z20__device_stub__saxpyPiS_S_
.size _Z5saxpyPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Mismatch "
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPiS_S_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xffff, PT ; /* 0x0000ffff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ LEA R9, R2, R5, 0x1 ; /* 0x0000000502097211 */
/* 0x004fca00078e08ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPiS_S_
.globl _Z5saxpyPiS_S_
.p2align 8
.type _Z5saxpyPiS_S_,@function
_Z5saxpyPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x10000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_lshl_add_u32 v2, v2, 1, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPiS_S_, .Lfunc_end0-_Z5saxpyPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00064c03_00000000-6_saxpyPerformance.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
.type _Z28__device_stub__Z5saxpyPiS_S_PiS_S_, @function
_Z28__device_stub__Z5saxpyPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z28__device_stub__Z5saxpyPiS_S_PiS_S_, .-_Z28__device_stub__Z5saxpyPiS_S_PiS_S_
.globl _Z5saxpyPiS_S_
.type _Z5saxpyPiS_S_, @function
_Z5saxpyPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5saxpyPiS_S_, .-_Z5saxpyPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Mismatch "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -786432(%rsp), %r11
.cfi_def_cfa 11, 786488
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 786576
movq %fs:40, %rax
movq %rax, 786504(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 64(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 262208(%rsp,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L12
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 262208(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $65, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1009, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 524352(%rsp), %rdi
movl $2, %ecx
movl $262144, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 52(%rsp)
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
leaq 524352(%rsp), %r12
leaq .LC1(%rip), %r14
leaq _ZSt4cout(%rip), %r13
jmp .L19
.L24:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
jmp .L13
.L27:
movq 786504(%rsp), %rax
subq %fs:40, %rax
jne .L25
call _ZSt16__throw_bad_castv@PLT
.L25:
call __stack_chk_fail@PLT
.L17:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L18:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L14:
addq $1, %rbx
cmpq $65536, %rbx
je .L26
.L19:
movl 64(%rsp,%rbx,4), %edx
movl 262208(%rsp,%rbx,4), %eax
leal (%rax,%rdx,2), %eax
cmpl %eax, (%r12,%rbx,4)
je .L14
movl $9, %edx
movq %r14, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L27
cmpb $0, 56(%r15)
je .L17
movzbl 67(%r15), %esi
jmp .L18
.L26:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 786504(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $786520, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z5saxpyPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpyPerformance.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__saxpyPiS_S_ # -- Begin function _Z20__device_stub__saxpyPiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPiS_S_,@function
_Z20__device_stub__saxpyPiS_S_: # @_Z20__device_stub__saxpyPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPiS_S_, .Lfunc_end0-_Z20__device_stub__saxpyPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $786544, %rsp # imm = 0xC0070
.cfi_def_cfa_offset 786576
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 524400(%rsp,%rax,4)
movl %eax, %ecx
imull %eax, %ecx
movl %ecx, 262256(%rsp,%rax,4)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
leaq 524400(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 262256(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967361, %rdx # imm = 0x100000041
leaq 944(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 48(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
jmp .LBB1_9
.LBB1_13: # in Loop: Header=BB1_9 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
# in Loop: Header=BB1_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_15: # in Loop: Header=BB1_9 Depth=1
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
je .LBB1_16
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl 524400(%rsp,%rbx,4), %eax
addl %eax, %eax
addl 262256(%rsp,%rbx,4), %eax
cmpl %eax, 112(%rsp,%rbx,4)
je .LBB1_15
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r14)
je .LBB1_13
# %bb.12: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_14
.LBB1_16:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $786544, %rsp # imm = 0xC0070
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 786576
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPiS_S_,@object # @_Z5saxpyPiS_S_
.section .rodata,"a",@progbits
.globl _Z5saxpyPiS_S_
.p2align 3, 0x0
_Z5saxpyPiS_S_:
.quad _Z20__device_stub__saxpyPiS_S_
.size _Z5saxpyPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Mismatch "
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPiS_S_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/***********************************************************
By Huahua Wang, the University of Minnesota, twin cities
***********************************************************/
__global__ void vecInit(float* X, unsigned int size, float value)
{
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
X[i] = value;
}
} | code for sm_80
Function : _Z7vecInitPfjf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fce0000000f00 */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0005 */
/*00b0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*00e0*/ @!P0 BRA 0xa0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/***********************************************************
By Huahua Wang, the University of Minnesota, twin cities
***********************************************************/
__global__ void vecInit(float* X, unsigned int size, float value)
{
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
X[i] = value;
}
} | .file "tmpxft_0011ec97_00000000-6_vecInit.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7vecInitPfjfPfjf
.type _Z28__device_stub__Z7vecInitPfjfPfjf, @function
_Z28__device_stub__Z7vecInitPfjfPfjf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7vecInitPfjf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z7vecInitPfjfPfjf, .-_Z28__device_stub__Z7vecInitPfjfPfjf
.globl _Z7vecInitPfjf
.type _Z7vecInitPfjf, @function
_Z7vecInitPfjf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7vecInitPfjfPfjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7vecInitPfjf, .-_Z7vecInitPfjf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7vecInitPfjf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vecInitPfjf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/***********************************************************
By Huahua Wang, the University of Minnesota, twin cities
***********************************************************/
__global__ void vecInit(float* X, unsigned int size, float value)
{
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
X[i] = value;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/***********************************************************
By Huahua Wang, the University of Minnesota, twin cities
***********************************************************/
__global__ void vecInit(float* X, unsigned int size, float value)
{
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
X[i] = value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/***********************************************************
By Huahua Wang, the University of Minnesota, twin cities
***********************************************************/
__global__ void vecInit(float* X, unsigned int size, float value)
{
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
X[i] = value;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vecInitPfjf
.globl _Z7vecInitPfjf
.p2align 8
.type _Z7vecInitPfjf,@function
_Z7vecInitPfjf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0xc
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s6
s_mul_i32 s1, s7, s5
s_mov_b32 s5, 0
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vecInitPfjf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vecInitPfjf, .Lfunc_end0-_Z7vecInitPfjf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vecInitPfjf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vecInitPfjf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/***********************************************************
By Huahua Wang, the University of Minnesota, twin cities
***********************************************************/
__global__ void vecInit(float* X, unsigned int size, float value)
{
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < size; i += stride) {
X[i] = value;
}
} | .text
.file "vecInit.hip"
.globl _Z22__device_stub__vecInitPfjf # -- Begin function _Z22__device_stub__vecInitPfjf
.p2align 4, 0x90
.type _Z22__device_stub__vecInitPfjf,@function
_Z22__device_stub__vecInitPfjf: # @_Z22__device_stub__vecInitPfjf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7vecInitPfjf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__vecInitPfjf, .Lfunc_end0-_Z22__device_stub__vecInitPfjf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vecInitPfjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7vecInitPfjf,@object # @_Z7vecInitPfjf
.section .rodata,"a",@progbits
.globl _Z7vecInitPfjf
.p2align 3, 0x0
_Z7vecInitPfjf:
.quad _Z22__device_stub__vecInitPfjf
.size _Z7vecInitPfjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7vecInitPfjf"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vecInitPfjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vecInitPfjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7vecInitPfjf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fce0000000f00 */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0005 */
/*00b0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*00e0*/ @!P0 BRA 0xa0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vecInitPfjf
.globl _Z7vecInitPfjf
.p2align 8
.type _Z7vecInitPfjf,@function
_Z7vecInitPfjf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0xc
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s6
s_mul_i32 s1, s7, s5
s_mov_b32 s5, 0
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vecInitPfjf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vecInitPfjf, .Lfunc_end0-_Z7vecInitPfjf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vecInitPfjf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vecInitPfjf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011ec97_00000000-6_vecInit.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7vecInitPfjfPfjf
.type _Z28__device_stub__Z7vecInitPfjfPfjf, @function
_Z28__device_stub__Z7vecInitPfjfPfjf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7vecInitPfjf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z7vecInitPfjfPfjf, .-_Z28__device_stub__Z7vecInitPfjfPfjf
.globl _Z7vecInitPfjf
.type _Z7vecInitPfjf, @function
_Z7vecInitPfjf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7vecInitPfjfPfjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7vecInitPfjf, .-_Z7vecInitPfjf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7vecInitPfjf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vecInitPfjf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecInit.hip"
.globl _Z22__device_stub__vecInitPfjf # -- Begin function _Z22__device_stub__vecInitPfjf
.p2align 4, 0x90
.type _Z22__device_stub__vecInitPfjf,@function
_Z22__device_stub__vecInitPfjf: # @_Z22__device_stub__vecInitPfjf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7vecInitPfjf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__vecInitPfjf, .Lfunc_end0-_Z22__device_stub__vecInitPfjf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vecInitPfjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7vecInitPfjf,@object # @_Z7vecInitPfjf
.section .rodata,"a",@progbits
.globl _Z7vecInitPfjf
.p2align 3, 0x0
_Z7vecInitPfjf:
.quad _Z22__device_stub__vecInitPfjf
.size _Z7vecInitPfjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7vecInitPfjf"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vecInitPfjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vecInitPfjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define N 32
void add(int *X, int *Y, int *Z){
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
}
__global__ void add_kernel(int *X, int *Y, int *Z){
int i = threadIdx.x ;
int j = threadIdx.y ;
if(i < N && j < N){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
int main(){
int X[N*N] ;
int Y[N*N] ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
X[i*N+j] = 0 ;
Y[i*N+j] = 1 ;
}
}
int Z[N*N] ;
int *d_X, *d_Y, *d_Z ;
cudaMalloc((void **) &d_X, (N*N)*sizeof(int)) ;
cudaMalloc((void **) &d_Y, (N*N)*sizeof(int)) ;
cudaMalloc((void **) &d_Z, (N*N)*sizeof(int)) ;
cudaMemcpy(d_X, &X, (N*N)*sizeof(int), cudaMemcpyHostToDevice) ;
cudaMemcpy(d_Y, &Y, (N*N)*sizeof(int), cudaMemcpyHostToDevice) ;
dim3 dimGrid(32,32,1) ;
dim3 dimBlock(32,32,1) ;
cudaEvent_t start, stop ;
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start) ;
add_kernel<<<dimGrid, dimBlock>>>(d_X, d_Y, d_Z) ;
//add(X, Y, Z) ;
cudaEventRecord(stop) ;
cudaMemcpy(&Z, d_Z, (N*N)*sizeof(int), cudaMemcpyDeviceToHost) ;
cudaEventSynchronize(stop) ;
float millisec = 0 ;
cudaEventElapsedTime(&millisec, start, stop) ;
cudaFree(d_X) ;
cudaFree(d_Y) ;
cudaFree(d_Z) ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
printf("%d ", Z[i*N+j]) ;
}
printf("\n") ;
}
printf("Time : %lf\n", millisec) ;
} | code for sm_80
Function : _Z10add_kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0020*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GT.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x001fc80003f04270 */
/*0040*/ ISETP.GT.OR P0, PT, R6, 0x1f, P0 ; /* 0x0000001f0600780c */
/* 0x002fda0000704670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ LEA R6, R6, R3, 0x5 ; /* 0x0000000306067211 */
/* 0x000fe200078e28ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define N 32
void add(int *X, int *Y, int *Z){
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
}
__global__ void add_kernel(int *X, int *Y, int *Z){
int i = threadIdx.x ;
int j = threadIdx.y ;
if(i < N && j < N){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
int main(){
int X[N*N] ;
int Y[N*N] ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
X[i*N+j] = 0 ;
Y[i*N+j] = 1 ;
}
}
int Z[N*N] ;
int *d_X, *d_Y, *d_Z ;
cudaMalloc((void **) &d_X, (N*N)*sizeof(int)) ;
cudaMalloc((void **) &d_Y, (N*N)*sizeof(int)) ;
cudaMalloc((void **) &d_Z, (N*N)*sizeof(int)) ;
cudaMemcpy(d_X, &X, (N*N)*sizeof(int), cudaMemcpyHostToDevice) ;
cudaMemcpy(d_Y, &Y, (N*N)*sizeof(int), cudaMemcpyHostToDevice) ;
dim3 dimGrid(32,32,1) ;
dim3 dimBlock(32,32,1) ;
cudaEvent_t start, stop ;
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start) ;
add_kernel<<<dimGrid, dimBlock>>>(d_X, d_Y, d_Z) ;
//add(X, Y, Z) ;
cudaEventRecord(stop) ;
cudaMemcpy(&Z, d_Z, (N*N)*sizeof(int), cudaMemcpyDeviceToHost) ;
cudaEventSynchronize(stop) ;
float millisec = 0 ;
cudaEventElapsedTime(&millisec, start, stop) ;
cudaFree(d_X) ;
cudaFree(d_Y) ;
cudaFree(d_Z) ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
printf("%d ", Z[i*N+j]) ;
}
printf("\n") ;
}
printf("Time : %lf\n", millisec) ;
} | .file "tmpxft_00083a0e_00000000-6_matrix_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r8
movq %rsi, %rdi
movq %rdx, %rsi
movl $128, %ecx
.L4:
leaq -128(%rcx), %rax
.L5:
movl (%rdi,%rax), %edx
addl (%r8,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
subq $-128, %rcx
cmpq $4224, %rcx
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
.type _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_, @function
_Z34__device_stub__Z10add_kernelPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_, .-_Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
.globl _Z10add_kernelPiS_S_
.type _Z10add_kernelPiS_S_, @function
_Z10add_kernelPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10add_kernelPiS_S_, .-_Z10add_kernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "Time : %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8240
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 12336
orq $0, (%rsp)
subq $96, %rsp
.cfi_def_cfa_offset 12432
movq %fs:40, %rax
movq %rax, 12376(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rdx
leaq 4176(%rsp), %rcx
movq %rcx, %rsi
.L17:
movl $0, %eax
.L18:
movl $0, (%rdx,%rax)
movl $1, (%rcx,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L18
subq $-128, %rdx
subq $-128, %rcx
cmpq %rsi, %rdx
jne .L17
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4176(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $1, 76(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L20:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8272(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq 8400(%rsp), %rbp
leaq 12496(%rsp), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L21:
leaq -128(%rbp), %rbx
.L22:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L22
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $-128, %rbp
cmpq %r14, %rbp
jne .L21
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 12376(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $12384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
jmp .L20
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10add_kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define N 32
void add(int *X, int *Y, int *Z){
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
}
__global__ void add_kernel(int *X, int *Y, int *Z){
int i = threadIdx.x ;
int j = threadIdx.y ;
if(i < N && j < N){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
int main(){
int X[N*N] ;
int Y[N*N] ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
X[i*N+j] = 0 ;
Y[i*N+j] = 1 ;
}
}
int Z[N*N] ;
int *d_X, *d_Y, *d_Z ;
cudaMalloc((void **) &d_X, (N*N)*sizeof(int)) ;
cudaMalloc((void **) &d_Y, (N*N)*sizeof(int)) ;
cudaMalloc((void **) &d_Z, (N*N)*sizeof(int)) ;
cudaMemcpy(d_X, &X, (N*N)*sizeof(int), cudaMemcpyHostToDevice) ;
cudaMemcpy(d_Y, &Y, (N*N)*sizeof(int), cudaMemcpyHostToDevice) ;
dim3 dimGrid(32,32,1) ;
dim3 dimBlock(32,32,1) ;
cudaEvent_t start, stop ;
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start) ;
add_kernel<<<dimGrid, dimBlock>>>(d_X, d_Y, d_Z) ;
//add(X, Y, Z) ;
cudaEventRecord(stop) ;
cudaMemcpy(&Z, d_Z, (N*N)*sizeof(int), cudaMemcpyDeviceToHost) ;
cudaEventSynchronize(stop) ;
float millisec = 0 ;
cudaEventElapsedTime(&millisec, start, stop) ;
cudaFree(d_X) ;
cudaFree(d_Y) ;
cudaFree(d_Z) ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
printf("%d ", Z[i*N+j]) ;
}
printf("\n") ;
}
printf("Time : %lf\n", millisec) ;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 32
void add(int *X, int *Y, int *Z){
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
}
__global__ void add_kernel(int *X, int *Y, int *Z){
int i = threadIdx.x ;
int j = threadIdx.y ;
if(i < N && j < N){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
int main(){
int X[N*N] ;
int Y[N*N] ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
X[i*N+j] = 0 ;
Y[i*N+j] = 1 ;
}
}
int Z[N*N] ;
int *d_X, *d_Y, *d_Z ;
hipMalloc((void **) &d_X, (N*N)*sizeof(int)) ;
hipMalloc((void **) &d_Y, (N*N)*sizeof(int)) ;
hipMalloc((void **) &d_Z, (N*N)*sizeof(int)) ;
hipMemcpy(d_X, &X, (N*N)*sizeof(int), hipMemcpyHostToDevice) ;
hipMemcpy(d_Y, &Y, (N*N)*sizeof(int), hipMemcpyHostToDevice) ;
dim3 dimGrid(32,32,1) ;
dim3 dimBlock(32,32,1) ;
hipEvent_t start, stop ;
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start) ;
add_kernel<<<dimGrid, dimBlock>>>(d_X, d_Y, d_Z) ;
//add(X, Y, Z) ;
hipEventRecord(stop) ;
hipMemcpy(&Z, d_Z, (N*N)*sizeof(int), hipMemcpyDeviceToHost) ;
hipEventSynchronize(stop) ;
float millisec = 0 ;
hipEventElapsedTime(&millisec, start, stop) ;
hipFree(d_X) ;
hipFree(d_Y) ;
hipFree(d_Z) ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
printf("%d ", Z[i*N+j]) ;
}
printf("\n") ;
}
printf("Time : %lf\n", millisec) ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 32
void add(int *X, int *Y, int *Z){
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
}
__global__ void add_kernel(int *X, int *Y, int *Z){
int i = threadIdx.x ;
int j = threadIdx.y ;
if(i < N && j < N){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
int main(){
int X[N*N] ;
int Y[N*N] ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
X[i*N+j] = 0 ;
Y[i*N+j] = 1 ;
}
}
int Z[N*N] ;
int *d_X, *d_Y, *d_Z ;
hipMalloc((void **) &d_X, (N*N)*sizeof(int)) ;
hipMalloc((void **) &d_Y, (N*N)*sizeof(int)) ;
hipMalloc((void **) &d_Z, (N*N)*sizeof(int)) ;
hipMemcpy(d_X, &X, (N*N)*sizeof(int), hipMemcpyHostToDevice) ;
hipMemcpy(d_Y, &Y, (N*N)*sizeof(int), hipMemcpyHostToDevice) ;
dim3 dimGrid(32,32,1) ;
dim3 dimBlock(32,32,1) ;
hipEvent_t start, stop ;
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start) ;
add_kernel<<<dimGrid, dimBlock>>>(d_X, d_Y, d_Z) ;
//add(X, Y, Z) ;
hipEventRecord(stop) ;
hipMemcpy(&Z, d_Z, (N*N)*sizeof(int), hipMemcpyDeviceToHost) ;
hipEventSynchronize(stop) ;
float millisec = 0 ;
hipEventElapsedTime(&millisec, start, stop) ;
hipFree(d_X) ;
hipFree(d_Y) ;
hipFree(d_Z) ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
printf("%d ", Z[i*N+j]) ;
}
printf("\n") ;
}
printf("Time : %lf\n", millisec) ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_kernelPiS_S_
.globl _Z10add_kernelPiS_S_
.p2align 8
.type _Z10add_kernelPiS_S_,@function
_Z10add_kernelPiS_S_:
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, v1, v0
v_cmpx_gt_u32_e32 32, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 5, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v0, v1, v0, 2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_kernelPiS_S_, .Lfunc_end0-_Z10add_kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10add_kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 32
void add(int *X, int *Y, int *Z){
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
}
__global__ void add_kernel(int *X, int *Y, int *Z){
int i = threadIdx.x ;
int j = threadIdx.y ;
if(i < N && j < N){
Z[i*N+j] = X[i*N+j] + Y[i*N+j] ;
}
}
int main(){
int X[N*N] ;
int Y[N*N] ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
X[i*N+j] = 0 ;
Y[i*N+j] = 1 ;
}
}
int Z[N*N] ;
int *d_X, *d_Y, *d_Z ;
hipMalloc((void **) &d_X, (N*N)*sizeof(int)) ;
hipMalloc((void **) &d_Y, (N*N)*sizeof(int)) ;
hipMalloc((void **) &d_Z, (N*N)*sizeof(int)) ;
hipMemcpy(d_X, &X, (N*N)*sizeof(int), hipMemcpyHostToDevice) ;
hipMemcpy(d_Y, &Y, (N*N)*sizeof(int), hipMemcpyHostToDevice) ;
dim3 dimGrid(32,32,1) ;
dim3 dimBlock(32,32,1) ;
hipEvent_t start, stop ;
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start) ;
add_kernel<<<dimGrid, dimBlock>>>(d_X, d_Y, d_Z) ;
//add(X, Y, Z) ;
hipEventRecord(stop) ;
hipMemcpy(&Z, d_Z, (N*N)*sizeof(int), hipMemcpyDeviceToHost) ;
hipEventSynchronize(stop) ;
float millisec = 0 ;
hipEventElapsedTime(&millisec, start, stop) ;
hipFree(d_X) ;
hipFree(d_Y) ;
hipFree(d_Z) ;
for(int i=0; i<N; i++){
for(int j=0; j<N; j++){
printf("%d ", Z[i*N+j]) ;
}
printf("\n") ;
}
printf("Time : %lf\n", millisec) ;
} | .text
.file "matrix_add.hip"
.globl _Z3addPiS_S_ # -- Begin function _Z3addPiS_S_
.p2align 4, 0x90
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: # @_Z3addPiS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq $32, %rcx
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
subq $-128, %rdx
subq $-128, %rsi
subq $-128, %rdi
cmpq $32, %rax
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_kernelPiS_S_ # -- Begin function _Z25__device_stub__add_kernelPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__add_kernelPiS_S_,@function
_Z25__device_stub__add_kernelPiS_S_: # @_Z25__device_stub__add_kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__add_kernelPiS_S_, .Lfunc_end1-_Z25__device_stub__add_kernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $12400, %rsp # imm = 0x3070
.cfi_def_cfa_offset 12432
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8304(%rsp), %rdi
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
leaq 4208(%rsp), %rax
.p2align 4, 0x90
.LBB2_1: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rcx,4)
incq %rcx
cmpq $32, %rcx
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rbx
subq $-128, %rax
cmpq $32, %rbx
jne .LBB2_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 24(%rsp), %rdi
leaq 8304(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 4208(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10add_kernelPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
leaq 112(%rsp), %rbx
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 48(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $32, %r15
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
subq $-128, %rbx
cmpq $32, %r14
jne .LBB2_7
# %bb.10:
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $12400, %rsp # imm = 0x3070
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add_kernelPiS_S_,@object # @_Z10add_kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z10add_kernelPiS_S_
.p2align 3, 0x0
_Z10add_kernelPiS_S_:
.quad _Z25__device_stub__add_kernelPiS_S_
.size _Z10add_kernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time : %lf\n"
.size .L.str.2, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_kernelPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_kernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10add_kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0020*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GT.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x001fc80003f04270 */
/*0040*/ ISETP.GT.OR P0, PT, R6, 0x1f, P0 ; /* 0x0000001f0600780c */
/* 0x002fda0000704670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ LEA R6, R6, R3, 0x5 ; /* 0x0000000306067211 */
/* 0x000fe200078e28ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_kernelPiS_S_
.globl _Z10add_kernelPiS_S_
.p2align 8
.type _Z10add_kernelPiS_S_,@function
_Z10add_kernelPiS_S_:
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, v1, v0
v_cmpx_gt_u32_e32 32, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 5, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v0, v1, v0, 2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_kernelPiS_S_, .Lfunc_end0-_Z10add_kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10add_kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00083a0e_00000000-6_matrix_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r8
movq %rsi, %rdi
movq %rdx, %rsi
movl $128, %ecx
.L4:
leaq -128(%rcx), %rax
.L5:
movl (%rdi,%rax), %edx
addl (%r8,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
subq $-128, %rcx
cmpq $4224, %rcx
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
.type _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_, @function
_Z34__device_stub__Z10add_kernelPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_, .-_Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
.globl _Z10add_kernelPiS_S_
.type _Z10add_kernelPiS_S_, @function
_Z10add_kernelPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10add_kernelPiS_S_, .-_Z10add_kernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "Time : %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8240
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 12336
orq $0, (%rsp)
subq $96, %rsp
.cfi_def_cfa_offset 12432
movq %fs:40, %rax
movq %rax, 12376(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rdx
leaq 4176(%rsp), %rcx
movq %rcx, %rsi
.L17:
movl $0, %eax
.L18:
movl $0, (%rdx,%rax)
movl $1, (%rcx,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L18
subq $-128, %rdx
subq $-128, %rcx
cmpq %rsi, %rdx
jne .L17
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4176(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $1, 76(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L20:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8272(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq 8400(%rsp), %rbp
leaq 12496(%rsp), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L21:
leaq -128(%rbp), %rbx
.L22:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L22
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $-128, %rbp
cmpq %r14, %rbp
jne .L21
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 12376(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $12384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
jmp .L20
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10add_kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_add.hip"
.globl _Z3addPiS_S_ # -- Begin function _Z3addPiS_S_
.p2align 4, 0x90
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: # @_Z3addPiS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq $32, %rcx
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
subq $-128, %rdx
subq $-128, %rsi
subq $-128, %rdi
cmpq $32, %rax
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_kernelPiS_S_ # -- Begin function _Z25__device_stub__add_kernelPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__add_kernelPiS_S_,@function
_Z25__device_stub__add_kernelPiS_S_: # @_Z25__device_stub__add_kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__add_kernelPiS_S_, .Lfunc_end1-_Z25__device_stub__add_kernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $12400, %rsp # imm = 0x3070
.cfi_def_cfa_offset 12432
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8304(%rsp), %rdi
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
leaq 4208(%rsp), %rax
.p2align 4, 0x90
.LBB2_1: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rcx,4)
incq %rcx
cmpq $32, %rcx
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rbx
subq $-128, %rax
cmpq $32, %rbx
jne .LBB2_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 24(%rsp), %rdi
leaq 8304(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 4208(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10add_kernelPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
leaq 112(%rsp), %rbx
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 48(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $32, %r15
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
subq $-128, %rbx
cmpq $32, %r14
jne .LBB2_7
# %bb.10:
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $12400, %rsp # imm = 0x3070
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add_kernelPiS_S_,@object # @_Z10add_kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z10add_kernelPiS_S_
.p2align 3, 0x0
_Z10add_kernelPiS_S_:
.quad _Z25__device_stub__add_kernelPiS_S_
.size _Z10add_kernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time : %lf\n"
.size .L.str.2, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_kernelPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_kernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
// Kernel that executes on the CUDA device
//__global__ void square_array(float *a, int N)
//{
// int idx = blockIdx.x * blockDim.x + threadIdx.x;
// if (idx<N) a[idx] = a[idx] * a[idx];
//}
// main routine that executes on the host
int main(void) {
float lambda = 20;
int n = 10;
int p = 2;
int m = 10;
int i, j;
float *A_h[n]; // host A matrix pointers
int *IDX_h[n]; // host Aindex matrix pointers
float *A_d[n];
int *IDX_d[n];
for (i = 0; i < n; i++) {
float *vec;
vec = (float *) malloc(p * sizeof(float));
int *vec_idx;
vec_idx = (int *) malloc(p * sizeof(int));
for (j = 0; j < p; j++) {
int idx = (int) (m * (rand() / (RAND_MAX + 1.0)));
float val = (float) rand() / RAND_MAX;
vec[j] = val;
vec_idx[j] = idx;
}
A_h[i] = &vec[0];
IDX_h[i] = &vec_idx[0];
float *vec_d;
int *vec_idx_d;
cudaMalloc((void **) &vec_d, p * sizeof(float));
cudaMalloc((void **) &vec_idx_d, p * sizeof(int));
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_d, p * sizeof(float))); // Allocate array on device
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_idx_d, p * sizeof(int))); // Allocate array on device
cudaMemcpy(vec_d, vec, sizeof(float) * p, cudaMemcpyHostToDevice);
cudaMemcpy(vec_idx_d, vec_idx, sizeof(int) * p, cudaMemcpyHostToDevice);
}
puts("idem generovat x_0\n"); /* prints !!!Hello World!!! */
float x_h[n];
float L_h[n];
float Li_h[n];
for (i = 0; i < n; i++) {
float val = (float) rand() / RAND_MAX;
x_h[i] = val;
L_h[i] = 0;
}
float gradient_h[m];
for (i = 0; i < m; i++) {
gradient_h[i] = 0;
}
// size_t size = m * sizeof(float);
// gradient_h = (float *)malloc(size);
for (i = 0; i < n; i++) {
float *vector = A_h[i];
int *vector_idx = IDX_h[i];
for (j = 0; j < p; j++) {
L_h[i] += vector[j] * vector[j];
gradient_h[vector_idx[j]] = gradient_h[vector_idx[j]] + (x_h[i])
* (vector[j]);
}
}
for (i = 0; i < m; i++) {
printf("gradient value: %d %f\n", i, gradient_h[i]);
}
//vypocet Li
for (i = 0; i < n; i++) {
Li_h[i] = 1 / L_h[i];
printf("Li: %d %f xi: %f\n", i, Li_h[i], x_h[i]);
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
for (i = 0; i < 10; i++) {
int coordinate = (int) (n * (rand() / (RAND_MAX + 1.0)));
// printf("Zvolil som suradnicu: %d \n", coordinate);
float *vector = A_h[coordinate];
int *vector_idx = IDX_h[coordinate];
float alpha = 0;
for (j = 0; j < p; j++) {
alpha += vector[vector_idx[j]] * gradient_h[vector_idx[j]];
}
// printf("alpha: %f \n", alpha);
//minimize alfa*d + 0.5 * L*d^2 + lambda |x+d|
double delta = -(alpha + lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta < 0) {
delta = -(alpha - lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta > 0) {
delta = -x_h[coordinate];
}
}
for (j = 0; j < p; j++) {
gradient_h[vector_idx[j]] += delta * vector[j];
}
x_h[coordinate] += delta;
//
//
// g(idx)=g(idx)+delta*A(idx,j);
//
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
// size_t matrixsize = n*p * sizeof(float);
//
// h_A = (float *)malloc(matrixsize); // Allocate array on host
// cudaMalloc((void **) &d_A, matrixsize); // Allocate array on device
// Initialize host array and copy it to CUDA device
// for (int i=0; i<N; i++) a_h[i] = (float)i;
// cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
// Do calculation on device:
// int block_size = 4;
// int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
// square_array <<< n_blocks, block_size >>> (a_d, N);
// Retrieve result from device and store it in host array
// cudaMemcpy(a_h, a_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Print results
// for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
// free(h_A);
// cudaFree(d_A);
cudaFree(A_d);
cudaFree(IDX_d);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
// Kernel that executes on the CUDA device
//__global__ void square_array(float *a, int N)
//{
// int idx = blockIdx.x * blockDim.x + threadIdx.x;
// if (idx<N) a[idx] = a[idx] * a[idx];
//}
// main routine that executes on the host
int main(void) {
float lambda = 20;
int n = 10;
int p = 2;
int m = 10;
int i, j;
float *A_h[n]; // host A matrix pointers
int *IDX_h[n]; // host Aindex matrix pointers
float *A_d[n];
int *IDX_d[n];
for (i = 0; i < n; i++) {
float *vec;
vec = (float *) malloc(p * sizeof(float));
int *vec_idx;
vec_idx = (int *) malloc(p * sizeof(int));
for (j = 0; j < p; j++) {
int idx = (int) (m * (rand() / (RAND_MAX + 1.0)));
float val = (float) rand() / RAND_MAX;
vec[j] = val;
vec_idx[j] = idx;
}
A_h[i] = &vec[0];
IDX_h[i] = &vec_idx[0];
float *vec_d;
int *vec_idx_d;
cudaMalloc((void **) &vec_d, p * sizeof(float));
cudaMalloc((void **) &vec_idx_d, p * sizeof(int));
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_d, p * sizeof(float))); // Allocate array on device
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_idx_d, p * sizeof(int))); // Allocate array on device
cudaMemcpy(vec_d, vec, sizeof(float) * p, cudaMemcpyHostToDevice);
cudaMemcpy(vec_idx_d, vec_idx, sizeof(int) * p, cudaMemcpyHostToDevice);
}
puts("idem generovat x_0\n"); /* prints !!!Hello World!!! */
float x_h[n];
float L_h[n];
float Li_h[n];
for (i = 0; i < n; i++) {
float val = (float) rand() / RAND_MAX;
x_h[i] = val;
L_h[i] = 0;
}
float gradient_h[m];
for (i = 0; i < m; i++) {
gradient_h[i] = 0;
}
// size_t size = m * sizeof(float);
// gradient_h = (float *)malloc(size);
for (i = 0; i < n; i++) {
float *vector = A_h[i];
int *vector_idx = IDX_h[i];
for (j = 0; j < p; j++) {
L_h[i] += vector[j] * vector[j];
gradient_h[vector_idx[j]] = gradient_h[vector_idx[j]] + (x_h[i])
* (vector[j]);
}
}
for (i = 0; i < m; i++) {
printf("gradient value: %d %f\n", i, gradient_h[i]);
}
//vypocet Li
for (i = 0; i < n; i++) {
Li_h[i] = 1 / L_h[i];
printf("Li: %d %f xi: %f\n", i, Li_h[i], x_h[i]);
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
for (i = 0; i < 10; i++) {
int coordinate = (int) (n * (rand() / (RAND_MAX + 1.0)));
// printf("Zvolil som suradnicu: %d \n", coordinate);
float *vector = A_h[coordinate];
int *vector_idx = IDX_h[coordinate];
float alpha = 0;
for (j = 0; j < p; j++) {
alpha += vector[vector_idx[j]] * gradient_h[vector_idx[j]];
}
// printf("alpha: %f \n", alpha);
//minimize alfa*d + 0.5 * L*d^2 + lambda |x+d|
double delta = -(alpha + lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta < 0) {
delta = -(alpha - lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta > 0) {
delta = -x_h[coordinate];
}
}
for (j = 0; j < p; j++) {
gradient_h[vector_idx[j]] += delta * vector[j];
}
x_h[coordinate] += delta;
//
//
// g(idx)=g(idx)+delta*A(idx,j);
//
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
// size_t matrixsize = n*p * sizeof(float);
//
// h_A = (float *)malloc(matrixsize); // Allocate array on host
// cudaMalloc((void **) &d_A, matrixsize); // Allocate array on device
// Initialize host array and copy it to CUDA device
// for (int i=0; i<N; i++) a_h[i] = (float)i;
// cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
// Do calculation on device:
// int block_size = 4;
// int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
// square_array <<< n_blocks, block_size >>> (a_d, N);
// Retrieve result from device and store it in host array
// cudaMemcpy(a_h, a_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Print results
// for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
// free(h_A);
// cudaFree(d_A);
cudaFree(A_d);
cudaFree(IDX_d);
} | .file "tmpxft_000cda15_00000000-6_NRCDM.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "idem generovat x_0\n"
.LC5:
.string "gradient value: %d %f\n"
.LC7:
.string "Li: %d %f xi: %f\n"
.LC8:
.string "x[%d] = %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $544, %rsp
.cfi_def_cfa_offset 592
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
movl $0, %r12d
movq %rsp, %r13
.L4:
movl $8, %edi
call malloc@PLT
movq %rax, %rbp
movl $8, %edi
call malloc@PLT
movq %rax, %rbx
call rand@PLT
movl %eax, %r14d
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp)
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, (%rbx)
call rand@PLT
movl %eax, %r14d
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 4(%rbp)
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 4(%rbx)
movq %rbp, 208(%rsp,%r12)
movq %rbx, 288(%rsp,%r12)
movl $8, %esi
movq %r13, %rdi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
addq $8, %r12
cmpq $80, %r12
jne .L4
leaq .LC3(%rip), %rdi
call puts@PLT
movl $0, %ebx
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 16(%rsp,%rbx)
movl $0x00000000, 64(%rsp,%rbx)
addq $4, %rbx
cmpq $40, %rbx
jne .L5
leaq 160(%rsp), %rax
leaq 200(%rsp), %rdx
.L6:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L6
movl $0, %eax
leaq 64(%rsp), %rdi
.L7:
movq 208(%rsp,%rax,2), %rcx
movq 288(%rsp,%rax,2), %rdx
movss 16(%rsp,%rax), %xmm1
movss (%rcx), %xmm0
movaps %xmm0, %xmm2
mulss %xmm0, %xmm2
addss (%rax,%rdi), %xmm2
movslq (%rdx), %rsi
mulss %xmm1, %xmm0
addss 160(%rsp,%rsi,4), %xmm0
movss %xmm0, 160(%rsp,%rsi,4)
movss 4(%rcx), %xmm0
movslq 4(%rdx), %rdx
mulss %xmm0, %xmm1
addss 160(%rsp,%rdx,4), %xmm1
movss %xmm1, 160(%rsp,%rdx,4)
mulss %xmm0, %xmm0
addss %xmm2, %xmm0
movss %xmm0, (%rax,%rdi)
addq $4, %rax
cmpq $40, %rax
jne .L7
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L8:
pxor %xmm0, %xmm0
cvtss2sd 160(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L8
movl $0, %ebx
leaq 64(%rsp), %r13
leaq 16(%rsp), %r12
leaq .LC7(%rip), %rbp
.L9:
movss .LC6(%rip), %xmm0
divss 0(%r13,%rbx,4), %xmm0
movss %xmm0, 112(%rsp,%rbx,4)
cvtss2sd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L9
movl $0, %ebx
leaq .LC8(%rip), %rbp
.L10:
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L10
jmp .L14
.L11:
movslq %esi, %rsi
pxor %xmm1, %xmm1
cvtss2sd (%rcx), %xmm1
mulsd %xmm0, %xmm1
cvtss2sd %xmm3, %xmm3
addsd %xmm3, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 160(%rsp,%rsi,4)
cltq
pxor %xmm1, %xmm1
cvtss2sd 4(%rcx), %xmm1
mulsd %xmm0, %xmm1
pxor %xmm3, %xmm3
cvtss2sd 160(%rsp,%rax,4), %xmm3
addsd %xmm3, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 160(%rsp,%rax,4)
movslq %edx, %rdx
addsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 16(%rsp,%rdx,4)
subl $1, %ebx
je .L29
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
cvttsd2sil %xmm0, %edx
movslq %edx, %rdi
movq 208(%rsp,%rdi,8), %rcx
movq 288(%rsp,%rdi,8), %rax
movl (%rax), %esi
movslq %esi, %r8
movss 160(%rsp,%r8,4), %xmm3
movaps %xmm3, %xmm0
mulss (%rcx,%r8,4), %xmm0
pxor %xmm1, %xmm1
addss %xmm1, %xmm0
movl 4(%rax), %eax
movslq %eax, %r8
movss (%rcx,%r8,4), %xmm1
mulss 160(%rsp,%r8,4), %xmm1
addss %xmm0, %xmm1
movss 112(%rsp,%rdi,4), %xmm5
movaps %xmm1, %xmm0
addss .LC9(%rip), %xmm0
xorps .LC10(%rip), %xmm0
mulss %xmm5, %xmm0
cvtss2sd %xmm0, %xmm0
movss 16(%rsp,%rdi,4), %xmm4
pxor %xmm2, %xmm2
cvtss2sd %xmm4, %xmm2
movapd %xmm2, %xmm6
addsd %xmm0, %xmm6
pxor %xmm7, %xmm7
comisd %xmm6, %xmm7
jbe .L11
subss .LC9(%rip), %xmm1
xorps .LC10(%rip), %xmm1
mulss %xmm5, %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movapd %xmm2, %xmm5
addsd %xmm0, %xmm5
comisd %xmm7, %xmm5
jbe .L11
xorps .LC10(%rip), %xmm4
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
jmp .L11
.L29:
movl $0, %ebx
leaq .LC8(%rip), %rbp
.L15:
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L15
leaq 368(%rsp), %rdi
call cudaFree@PLT
leaq 448(%rsp), %rdi
call cudaFree@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $544, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1040187392
.align 8
.LC2:
.long 0
.long 1076101120
.section .rodata.cst4
.align 4
.LC6:
.long 1065353216
.align 4
.LC9:
.long 1101004800
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC10:
.long -2147483648
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
// Kernel that executes on the CUDA device
//__global__ void square_array(float *a, int N)
//{
// int idx = blockIdx.x * blockDim.x + threadIdx.x;
// if (idx<N) a[idx] = a[idx] * a[idx];
//}
// main routine that executes on the host
int main(void) {
float lambda = 20;
int n = 10;
int p = 2;
int m = 10;
int i, j;
float *A_h[n]; // host A matrix pointers
int *IDX_h[n]; // host Aindex matrix pointers
float *A_d[n];
int *IDX_d[n];
for (i = 0; i < n; i++) {
float *vec;
vec = (float *) malloc(p * sizeof(float));
int *vec_idx;
vec_idx = (int *) malloc(p * sizeof(int));
for (j = 0; j < p; j++) {
int idx = (int) (m * (rand() / (RAND_MAX + 1.0)));
float val = (float) rand() / RAND_MAX;
vec[j] = val;
vec_idx[j] = idx;
}
A_h[i] = &vec[0];
IDX_h[i] = &vec_idx[0];
float *vec_d;
int *vec_idx_d;
cudaMalloc((void **) &vec_d, p * sizeof(float));
cudaMalloc((void **) &vec_idx_d, p * sizeof(int));
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_d, p * sizeof(float))); // Allocate array on device
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_idx_d, p * sizeof(int))); // Allocate array on device
cudaMemcpy(vec_d, vec, sizeof(float) * p, cudaMemcpyHostToDevice);
cudaMemcpy(vec_idx_d, vec_idx, sizeof(int) * p, cudaMemcpyHostToDevice);
}
puts("idem generovat x_0\n"); /* prints !!!Hello World!!! */
float x_h[n];
float L_h[n];
float Li_h[n];
for (i = 0; i < n; i++) {
float val = (float) rand() / RAND_MAX;
x_h[i] = val;
L_h[i] = 0;
}
float gradient_h[m];
for (i = 0; i < m; i++) {
gradient_h[i] = 0;
}
// size_t size = m * sizeof(float);
// gradient_h = (float *)malloc(size);
for (i = 0; i < n; i++) {
float *vector = A_h[i];
int *vector_idx = IDX_h[i];
for (j = 0; j < p; j++) {
L_h[i] += vector[j] * vector[j];
gradient_h[vector_idx[j]] = gradient_h[vector_idx[j]] + (x_h[i])
* (vector[j]);
}
}
for (i = 0; i < m; i++) {
printf("gradient value: %d %f\n", i, gradient_h[i]);
}
//vypocet Li
for (i = 0; i < n; i++) {
Li_h[i] = 1 / L_h[i];
printf("Li: %d %f xi: %f\n", i, Li_h[i], x_h[i]);
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
for (i = 0; i < 10; i++) {
int coordinate = (int) (n * (rand() / (RAND_MAX + 1.0)));
// printf("Zvolil som suradnicu: %d \n", coordinate);
float *vector = A_h[coordinate];
int *vector_idx = IDX_h[coordinate];
float alpha = 0;
for (j = 0; j < p; j++) {
alpha += vector[vector_idx[j]] * gradient_h[vector_idx[j]];
}
// printf("alpha: %f \n", alpha);
//minimize alfa*d + 0.5 * L*d^2 + lambda |x+d|
double delta = -(alpha + lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta < 0) {
delta = -(alpha - lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta > 0) {
delta = -x_h[coordinate];
}
}
for (j = 0; j < p; j++) {
gradient_h[vector_idx[j]] += delta * vector[j];
}
x_h[coordinate] += delta;
//
//
// g(idx)=g(idx)+delta*A(idx,j);
//
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
// size_t matrixsize = n*p * sizeof(float);
//
// h_A = (float *)malloc(matrixsize); // Allocate array on host
// cudaMalloc((void **) &d_A, matrixsize); // Allocate array on device
// Initialize host array and copy it to CUDA device
// for (int i=0; i<N; i++) a_h[i] = (float)i;
// cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
// Do calculation on device:
// int block_size = 4;
// int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
// square_array <<< n_blocks, block_size >>> (a_d, N);
// Retrieve result from device and store it in host array
// cudaMemcpy(a_h, a_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Print results
// for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
// free(h_A);
// cudaFree(d_A);
cudaFree(A_d);
cudaFree(IDX_d);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
// Kernel that executes on the CUDA device
//__global__ void square_array(float *a, int N)
//{
// int idx = blockIdx.x * blockDim.x + threadIdx.x;
// if (idx<N) a[idx] = a[idx] * a[idx];
//}
// main routine that executes on the host
int main(void) {
float lambda = 20;
int n = 10;
int p = 2;
int m = 10;
int i, j;
float *A_h[n]; // host A matrix pointers
int *IDX_h[n]; // host Aindex matrix pointers
float *A_d[n];
int *IDX_d[n];
for (i = 0; i < n; i++) {
float *vec;
vec = (float *) malloc(p * sizeof(float));
int *vec_idx;
vec_idx = (int *) malloc(p * sizeof(int));
for (j = 0; j < p; j++) {
int idx = (int) (m * (rand() / (RAND_MAX + 1.0)));
float val = (float) rand() / RAND_MAX;
vec[j] = val;
vec_idx[j] = idx;
}
A_h[i] = &vec[0];
IDX_h[i] = &vec_idx[0];
float *vec_d;
int *vec_idx_d;
hipMalloc((void **) &vec_d, p * sizeof(float));
hipMalloc((void **) &vec_idx_d, p * sizeof(int));
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_d, p * sizeof(float))); // Allocate array on device
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_idx_d, p * sizeof(int))); // Allocate array on device
hipMemcpy(vec_d, vec, sizeof(float) * p, hipMemcpyHostToDevice);
hipMemcpy(vec_idx_d, vec_idx, sizeof(int) * p, hipMemcpyHostToDevice);
}
puts("idem generovat x_0\n"); /* prints !!!Hello World!!! */
float x_h[n];
float L_h[n];
float Li_h[n];
for (i = 0; i < n; i++) {
float val = (float) rand() / RAND_MAX;
x_h[i] = val;
L_h[i] = 0;
}
float gradient_h[m];
for (i = 0; i < m; i++) {
gradient_h[i] = 0;
}
// size_t size = m * sizeof(float);
// gradient_h = (float *)malloc(size);
for (i = 0; i < n; i++) {
float *vector = A_h[i];
int *vector_idx = IDX_h[i];
for (j = 0; j < p; j++) {
L_h[i] += vector[j] * vector[j];
gradient_h[vector_idx[j]] = gradient_h[vector_idx[j]] + (x_h[i])
* (vector[j]);
}
}
for (i = 0; i < m; i++) {
printf("gradient value: %d %f\n", i, gradient_h[i]);
}
//vypocet Li
for (i = 0; i < n; i++) {
Li_h[i] = 1 / L_h[i];
printf("Li: %d %f xi: %f\n", i, Li_h[i], x_h[i]);
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
for (i = 0; i < 10; i++) {
int coordinate = (int) (n * (rand() / (RAND_MAX + 1.0)));
// printf("Zvolil som suradnicu: %d \n", coordinate);
float *vector = A_h[coordinate];
int *vector_idx = IDX_h[coordinate];
float alpha = 0;
for (j = 0; j < p; j++) {
alpha += vector[vector_idx[j]] * gradient_h[vector_idx[j]];
}
// printf("alpha: %f \n", alpha);
//minimize alfa*d + 0.5 * L*d^2 + lambda |x+d|
double delta = -(alpha + lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta < 0) {
delta = -(alpha - lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta > 0) {
delta = -x_h[coordinate];
}
}
for (j = 0; j < p; j++) {
gradient_h[vector_idx[j]] += delta * vector[j];
}
x_h[coordinate] += delta;
//
//
// g(idx)=g(idx)+delta*A(idx,j);
//
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
// size_t matrixsize = n*p * sizeof(float);
//
// h_A = (float *)malloc(matrixsize); // Allocate array on host
// cudaMalloc((void **) &d_A, matrixsize); // Allocate array on device
// Initialize host array and copy it to CUDA device
// for (int i=0; i<N; i++) a_h[i] = (float)i;
// cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
// Do calculation on device:
// int block_size = 4;
// int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
// square_array <<< n_blocks, block_size >>> (a_d, N);
// Retrieve result from device and store it in host array
// cudaMemcpy(a_h, a_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Print results
// for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
// free(h_A);
// cudaFree(d_A);
hipFree(A_d);
hipFree(IDX_d);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
// Kernel that executes on the CUDA device
//__global__ void square_array(float *a, int N)
//{
// int idx = blockIdx.x * blockDim.x + threadIdx.x;
// if (idx<N) a[idx] = a[idx] * a[idx];
//}
// main routine that executes on the host
int main(void) {
float lambda = 20;
int n = 10;
int p = 2;
int m = 10;
int i, j;
float *A_h[n]; // host A matrix pointers
int *IDX_h[n]; // host Aindex matrix pointers
float *A_d[n];
int *IDX_d[n];
for (i = 0; i < n; i++) {
float *vec;
vec = (float *) malloc(p * sizeof(float));
int *vec_idx;
vec_idx = (int *) malloc(p * sizeof(int));
for (j = 0; j < p; j++) {
int idx = (int) (m * (rand() / (RAND_MAX + 1.0)));
float val = (float) rand() / RAND_MAX;
vec[j] = val;
vec_idx[j] = idx;
}
A_h[i] = &vec[0];
IDX_h[i] = &vec_idx[0];
float *vec_d;
int *vec_idx_d;
hipMalloc((void **) &vec_d, p * sizeof(float));
hipMalloc((void **) &vec_idx_d, p * sizeof(int));
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_d, p * sizeof(float))); // Allocate array on device
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_idx_d, p * sizeof(int))); // Allocate array on device
hipMemcpy(vec_d, vec, sizeof(float) * p, hipMemcpyHostToDevice);
hipMemcpy(vec_idx_d, vec_idx, sizeof(int) * p, hipMemcpyHostToDevice);
}
puts("idem generovat x_0\n"); /* prints !!!Hello World!!! */
float x_h[n];
float L_h[n];
float Li_h[n];
for (i = 0; i < n; i++) {
float val = (float) rand() / RAND_MAX;
x_h[i] = val;
L_h[i] = 0;
}
float gradient_h[m];
for (i = 0; i < m; i++) {
gradient_h[i] = 0;
}
// size_t size = m * sizeof(float);
// gradient_h = (float *)malloc(size);
for (i = 0; i < n; i++) {
float *vector = A_h[i];
int *vector_idx = IDX_h[i];
for (j = 0; j < p; j++) {
L_h[i] += vector[j] * vector[j];
gradient_h[vector_idx[j]] = gradient_h[vector_idx[j]] + (x_h[i])
* (vector[j]);
}
}
for (i = 0; i < m; i++) {
printf("gradient value: %d %f\n", i, gradient_h[i]);
}
//vypocet Li
for (i = 0; i < n; i++) {
Li_h[i] = 1 / L_h[i];
printf("Li: %d %f xi: %f\n", i, Li_h[i], x_h[i]);
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
for (i = 0; i < 10; i++) {
int coordinate = (int) (n * (rand() / (RAND_MAX + 1.0)));
// printf("Zvolil som suradnicu: %d \n", coordinate);
float *vector = A_h[coordinate];
int *vector_idx = IDX_h[coordinate];
float alpha = 0;
for (j = 0; j < p; j++) {
alpha += vector[vector_idx[j]] * gradient_h[vector_idx[j]];
}
// printf("alpha: %f \n", alpha);
//minimize alfa*d + 0.5 * L*d^2 + lambda |x+d|
double delta = -(alpha + lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta < 0) {
delta = -(alpha - lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta > 0) {
delta = -x_h[coordinate];
}
}
for (j = 0; j < p; j++) {
gradient_h[vector_idx[j]] += delta * vector[j];
}
x_h[coordinate] += delta;
//
//
// g(idx)=g(idx)+delta*A(idx,j);
//
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
// size_t matrixsize = n*p * sizeof(float);
//
// h_A = (float *)malloc(matrixsize); // Allocate array on host
// cudaMalloc((void **) &d_A, matrixsize); // Allocate array on device
// Initialize host array and copy it to CUDA device
// for (int i=0; i<N; i++) a_h[i] = (float)i;
// cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
// Do calculation on device:
// int block_size = 4;
// int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
// square_array <<< n_blocks, block_size >>> (a_d, N);
// Retrieve result from device and store it in host array
// cudaMemcpy(a_h, a_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Print results
// for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
// free(h_A);
// cudaFree(d_A);
hipFree(A_d);
hipFree(IDX_d);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
// Kernel that executes on the CUDA device
//__global__ void square_array(float *a, int N)
//{
// int idx = blockIdx.x * blockDim.x + threadIdx.x;
// if (idx<N) a[idx] = a[idx] * a[idx];
//}
// main routine that executes on the host
int main(void) {
float lambda = 20;
int n = 10;
int p = 2;
int m = 10;
int i, j;
float *A_h[n]; // host A matrix pointers
int *IDX_h[n]; // host Aindex matrix pointers
float *A_d[n];
int *IDX_d[n];
for (i = 0; i < n; i++) {
float *vec;
vec = (float *) malloc(p * sizeof(float));
int *vec_idx;
vec_idx = (int *) malloc(p * sizeof(int));
for (j = 0; j < p; j++) {
int idx = (int) (m * (rand() / (RAND_MAX + 1.0)));
float val = (float) rand() / RAND_MAX;
vec[j] = val;
vec_idx[j] = idx;
}
A_h[i] = &vec[0];
IDX_h[i] = &vec_idx[0];
float *vec_d;
int *vec_idx_d;
hipMalloc((void **) &vec_d, p * sizeof(float));
hipMalloc((void **) &vec_idx_d, p * sizeof(int));
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_d, p * sizeof(float))); // Allocate array on device
// CUDA_SAFE_CALL(cudaMalloc((void **) &vec_idx_d, p * sizeof(int))); // Allocate array on device
hipMemcpy(vec_d, vec, sizeof(float) * p, hipMemcpyHostToDevice);
hipMemcpy(vec_idx_d, vec_idx, sizeof(int) * p, hipMemcpyHostToDevice);
}
puts("idem generovat x_0\n"); /* prints !!!Hello World!!! */
float x_h[n];
float L_h[n];
float Li_h[n];
for (i = 0; i < n; i++) {
float val = (float) rand() / RAND_MAX;
x_h[i] = val;
L_h[i] = 0;
}
float gradient_h[m];
for (i = 0; i < m; i++) {
gradient_h[i] = 0;
}
// size_t size = m * sizeof(float);
// gradient_h = (float *)malloc(size);
for (i = 0; i < n; i++) {
float *vector = A_h[i];
int *vector_idx = IDX_h[i];
for (j = 0; j < p; j++) {
L_h[i] += vector[j] * vector[j];
gradient_h[vector_idx[j]] = gradient_h[vector_idx[j]] + (x_h[i])
* (vector[j]);
}
}
for (i = 0; i < m; i++) {
printf("gradient value: %d %f\n", i, gradient_h[i]);
}
//vypocet Li
for (i = 0; i < n; i++) {
Li_h[i] = 1 / L_h[i];
printf("Li: %d %f xi: %f\n", i, Li_h[i], x_h[i]);
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
for (i = 0; i < 10; i++) {
int coordinate = (int) (n * (rand() / (RAND_MAX + 1.0)));
// printf("Zvolil som suradnicu: %d \n", coordinate);
float *vector = A_h[coordinate];
int *vector_idx = IDX_h[coordinate];
float alpha = 0;
for (j = 0; j < p; j++) {
alpha += vector[vector_idx[j]] * gradient_h[vector_idx[j]];
}
// printf("alpha: %f \n", alpha);
//minimize alfa*d + 0.5 * L*d^2 + lambda |x+d|
double delta = -(alpha + lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta < 0) {
delta = -(alpha - lambda) * Li_h[coordinate];
if (x_h[coordinate] + delta > 0) {
delta = -x_h[coordinate];
}
}
for (j = 0; j < p; j++) {
gradient_h[vector_idx[j]] += delta * vector[j];
}
x_h[coordinate] += delta;
//
//
// g(idx)=g(idx)+delta*A(idx,j);
//
}
for (i = 0; i < n; i++) {
printf("x[%d] = %f \n", i, x_h[i]);
}
// size_t matrixsize = n*p * sizeof(float);
//
// h_A = (float *)malloc(matrixsize); // Allocate array on host
// cudaMalloc((void **) &d_A, matrixsize); // Allocate array on device
// Initialize host array and copy it to CUDA device
// for (int i=0; i<N; i++) a_h[i] = (float)i;
// cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
// Do calculation on device:
// int block_size = 4;
// int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
// square_array <<< n_blocks, block_size >>> (a_d, N);
// Retrieve result from device and store it in host array
// cudaMemcpy(a_h, a_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Print results
// for (int i=0; i<N; i++) printf("%d %f\n", i, a_h[i]);
// Cleanup
// free(h_A);
// cudaFree(d_A);
hipFree(A_d);
hipFree(IDX_d);
} | .text
.file "NRCDM.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI0_1:
.quad 0x4024000000000000 # double 10
.LCPI0_7:
.quad 0x0000000000000000 # double 0
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_2:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_3:
.long 0x3f800000 # float 1
.LCPI0_4:
.long 0x41a00000 # float 20
.LCPI0_6:
.long 0xc1a00000 # float -20
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_5:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $344, %rsp # imm = 0x158
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movl $8, %edi
callq malloc
movq %rax, %r12
movl $8, %edi
callq malloc
movq %rax, %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %r14d
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_2(%rip), %xmm0
movss %xmm0, (%r12,%rbx,4)
movl %r14d, (%r15,%rbx,4)
incq %rbx
cmpq $1, %rbx
je .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
movq %r12, -224(%rbp,%r13,8)
movq %r15, -144(%rbp,%r13,8)
movl $8, %esi
leaq -56(%rbp), %rdi
callq hipMalloc
movl $8, %esi
leaq -48(%rbp), %rdi
callq hipMalloc
movq -56(%rbp), %rdi
movl $8, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq -48(%rbp), %rdi
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
incq %r13
cmpq $10, %r13
jne .LBB0_1
# %bb.4:
movl $.L.str, %edi
callq puts
movq %rsp, %r14
addq $-48, %r14
movq %r14, %rsp
movq %rsp, %r13
addq $-48, %r13
movq %r13, %rsp
movq %rsp, %r15
addq $-48, %r15
movq %r15, %rsp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_2(%rip), %xmm0
movss %xmm0, (%r14,%rbx,4)
movl $0, (%r13,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB0_5
# %bb.6: # %.preheader132.preheader
movq %rsp, %rax
leaq -48(%rax), %r12
movq %r12, %rsp
xorps %xmm0, %xmm0
movaps %xmm0, -32(%rax)
movaps %xmm0, -48(%rax)
movq $0, -16(%rax)
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_7: # %.preheader132
# =>This Loop Header: Depth=1
# Child Loop BB0_8 Depth 2
movq -224(%rbp,%rax,8), %rcx
movq -144(%rbp,%rax,8), %rdx
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_8: # Parent Loop BB0_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm3
mulss %xmm2, %xmm3
movslq (%rdx,%rsi,4), %rdi
mulss %xmm1, %xmm2
addss (%r12,%rdi,4), %xmm2
addss %xmm3, %xmm0
movss %xmm2, (%r12,%rdi,4)
incq %rsi
cmpq $1, %rsi
je .LBB0_8
# %bb.9: # in Loop: Header=BB0_7 Depth=1
movss %xmm0, (%r13,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB0_7
# %bb.10: # %.preheader131.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_11: # %.preheader131
# =>This Inner Loop Header: Depth=1
movss (%r12,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_11
# %bb.12: # %.preheader130.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_13: # %.preheader130
# =>This Inner Loop Header: Depth=1
movss .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%r13,%rbx,4), %xmm0
movss %xmm0, (%r15,%rbx,4)
cvtss2sd %xmm0, %xmm0
movss (%r14,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.2, %edi
movl %ebx, %esi
movb $2, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_13
# %bb.14: # %.preheader129.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_15: # %.preheader129
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_15
# %bb.16: # %.preheader128.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_17: # %.preheader128
# =>This Loop Header: Depth=1
# Child Loop BB0_18 Depth 2
# Child Loop BB0_23 Depth 2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %eax
cltq
movq -224(%rbp,%rax,8), %rcx
movq -144(%rbp,%rax,8), %rdx
xorps %xmm2, %xmm2
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_18: # Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%rdx,%rsi,4), %rdi
movss (%rcx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r12,%rdi,4), %xmm0
addss %xmm0, %xmm2
incq %rsi
cmpq $1, %rsi
je .LBB0_18
# %bb.19: # in Loop: Header=BB0_17 Depth=1
movaps %xmm2, %xmm0
addss .LCPI0_4(%rip), %xmm0
movaps .LCPI0_5(%rip), %xmm6 # xmm6 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm6, %xmm0
movss (%r15,%rax,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
mulss %xmm4, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
movaps %xmm0, %xmm5
addsd %xmm1, %xmm5
xorpd %xmm7, %xmm7
ucomisd %xmm5, %xmm7
jbe .LBB0_22
# %bb.20: # in Loop: Header=BB0_17 Depth=1
addss .LCPI0_6(%rip), %xmm2
xorps %xmm6, %xmm2
mulss %xmm2, %xmm4
xorps %xmm1, %xmm1
cvtss2sd %xmm4, %xmm1
movaps %xmm0, %xmm2
addsd %xmm1, %xmm2
ucomisd .LCPI0_7(%rip), %xmm2
jbe .LBB0_22
# %bb.21: # in Loop: Header=BB0_17 Depth=1
xorps %xmm6, %xmm3
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
.LBB0_22: # in Loop: Header=BB0_17 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_23: # Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
mulsd %xmm1, %xmm2
movslq (%rdx,%rsi,4), %rdi
movss (%r12,%rdi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
addsd %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtsd2ss %xmm3, %xmm2
movss %xmm2, (%r12,%rdi,4)
incq %rsi
cmpq $1, %rsi
je .LBB0_23
# %bb.24: # in Loop: Header=BB0_17 Depth=1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%r14,%rax,4)
incl %ebx
cmpl $10, %ebx
jne .LBB0_17
# %bb.25: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_26: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_26
# %bb.27:
leaq -384(%rbp), %rdi
callq hipFree
leaq -304(%rbp), %rdi
callq hipFree
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "idem generovat x_0\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gradient value: %d %f\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Li: %d %f xi: %f\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "x[%d] = %f \n"
.size .L.str.3, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cda15_00000000-6_NRCDM.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "idem generovat x_0\n"
.LC5:
.string "gradient value: %d %f\n"
.LC7:
.string "Li: %d %f xi: %f\n"
.LC8:
.string "x[%d] = %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $544, %rsp
.cfi_def_cfa_offset 592
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
movl $0, %r12d
movq %rsp, %r13
.L4:
movl $8, %edi
call malloc@PLT
movq %rax, %rbp
movl $8, %edi
call malloc@PLT
movq %rax, %rbx
call rand@PLT
movl %eax, %r14d
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp)
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, (%rbx)
call rand@PLT
movl %eax, %r14d
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 4(%rbp)
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 4(%rbx)
movq %rbp, 208(%rsp,%r12)
movq %rbx, 288(%rsp,%r12)
movl $8, %esi
movq %r13, %rdi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
addq $8, %r12
cmpq $80, %r12
jne .L4
leaq .LC3(%rip), %rdi
call puts@PLT
movl $0, %ebx
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 16(%rsp,%rbx)
movl $0x00000000, 64(%rsp,%rbx)
addq $4, %rbx
cmpq $40, %rbx
jne .L5
leaq 160(%rsp), %rax
leaq 200(%rsp), %rdx
.L6:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L6
movl $0, %eax
leaq 64(%rsp), %rdi
.L7:
movq 208(%rsp,%rax,2), %rcx
movq 288(%rsp,%rax,2), %rdx
movss 16(%rsp,%rax), %xmm1
movss (%rcx), %xmm0
movaps %xmm0, %xmm2
mulss %xmm0, %xmm2
addss (%rax,%rdi), %xmm2
movslq (%rdx), %rsi
mulss %xmm1, %xmm0
addss 160(%rsp,%rsi,4), %xmm0
movss %xmm0, 160(%rsp,%rsi,4)
movss 4(%rcx), %xmm0
movslq 4(%rdx), %rdx
mulss %xmm0, %xmm1
addss 160(%rsp,%rdx,4), %xmm1
movss %xmm1, 160(%rsp,%rdx,4)
mulss %xmm0, %xmm0
addss %xmm2, %xmm0
movss %xmm0, (%rax,%rdi)
addq $4, %rax
cmpq $40, %rax
jne .L7
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L8:
pxor %xmm0, %xmm0
cvtss2sd 160(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L8
movl $0, %ebx
leaq 64(%rsp), %r13
leaq 16(%rsp), %r12
leaq .LC7(%rip), %rbp
.L9:
movss .LC6(%rip), %xmm0
divss 0(%r13,%rbx,4), %xmm0
movss %xmm0, 112(%rsp,%rbx,4)
cvtss2sd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L9
movl $0, %ebx
leaq .LC8(%rip), %rbp
.L10:
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L10
jmp .L14
.L11:
movslq %esi, %rsi
pxor %xmm1, %xmm1
cvtss2sd (%rcx), %xmm1
mulsd %xmm0, %xmm1
cvtss2sd %xmm3, %xmm3
addsd %xmm3, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 160(%rsp,%rsi,4)
cltq
pxor %xmm1, %xmm1
cvtss2sd 4(%rcx), %xmm1
mulsd %xmm0, %xmm1
pxor %xmm3, %xmm3
cvtss2sd 160(%rsp,%rax,4), %xmm3
addsd %xmm3, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 160(%rsp,%rax,4)
movslq %edx, %rdx
addsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 16(%rsp,%rdx,4)
subl $1, %ebx
je .L29
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
cvttsd2sil %xmm0, %edx
movslq %edx, %rdi
movq 208(%rsp,%rdi,8), %rcx
movq 288(%rsp,%rdi,8), %rax
movl (%rax), %esi
movslq %esi, %r8
movss 160(%rsp,%r8,4), %xmm3
movaps %xmm3, %xmm0
mulss (%rcx,%r8,4), %xmm0
pxor %xmm1, %xmm1
addss %xmm1, %xmm0
movl 4(%rax), %eax
movslq %eax, %r8
movss (%rcx,%r8,4), %xmm1
mulss 160(%rsp,%r8,4), %xmm1
addss %xmm0, %xmm1
movss 112(%rsp,%rdi,4), %xmm5
movaps %xmm1, %xmm0
addss .LC9(%rip), %xmm0
xorps .LC10(%rip), %xmm0
mulss %xmm5, %xmm0
cvtss2sd %xmm0, %xmm0
movss 16(%rsp,%rdi,4), %xmm4
pxor %xmm2, %xmm2
cvtss2sd %xmm4, %xmm2
movapd %xmm2, %xmm6
addsd %xmm0, %xmm6
pxor %xmm7, %xmm7
comisd %xmm6, %xmm7
jbe .L11
subss .LC9(%rip), %xmm1
xorps .LC10(%rip), %xmm1
mulss %xmm5, %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movapd %xmm2, %xmm5
addsd %xmm0, %xmm5
comisd %xmm7, %xmm5
jbe .L11
xorps .LC10(%rip), %xmm4
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
jmp .L11
.L29:
movl $0, %ebx
leaq .LC8(%rip), %rbp
.L15:
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L15
leaq 368(%rsp), %rdi
call cudaFree@PLT
leaq 448(%rsp), %rdi
call cudaFree@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $544, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1040187392
.align 8
.LC2:
.long 0
.long 1076101120
.section .rodata.cst4
.align 4
.LC6:
.long 1065353216
.align 4
.LC9:
.long 1101004800
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC10:
.long -2147483648
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NRCDM.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI0_1:
.quad 0x4024000000000000 # double 10
.LCPI0_7:
.quad 0x0000000000000000 # double 0
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_2:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_3:
.long 0x3f800000 # float 1
.LCPI0_4:
.long 0x41a00000 # float 20
.LCPI0_6:
.long 0xc1a00000 # float -20
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_5:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $344, %rsp # imm = 0x158
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movl $8, %edi
callq malloc
movq %rax, %r12
movl $8, %edi
callq malloc
movq %rax, %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %r14d
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_2(%rip), %xmm0
movss %xmm0, (%r12,%rbx,4)
movl %r14d, (%r15,%rbx,4)
incq %rbx
cmpq $1, %rbx
je .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
movq %r12, -224(%rbp,%r13,8)
movq %r15, -144(%rbp,%r13,8)
movl $8, %esi
leaq -56(%rbp), %rdi
callq hipMalloc
movl $8, %esi
leaq -48(%rbp), %rdi
callq hipMalloc
movq -56(%rbp), %rdi
movl $8, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq -48(%rbp), %rdi
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
incq %r13
cmpq $10, %r13
jne .LBB0_1
# %bb.4:
movl $.L.str, %edi
callq puts
movq %rsp, %r14
addq $-48, %r14
movq %r14, %rsp
movq %rsp, %r13
addq $-48, %r13
movq %r13, %rsp
movq %rsp, %r15
addq $-48, %r15
movq %r15, %rsp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_2(%rip), %xmm0
movss %xmm0, (%r14,%rbx,4)
movl $0, (%r13,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB0_5
# %bb.6: # %.preheader132.preheader
movq %rsp, %rax
leaq -48(%rax), %r12
movq %r12, %rsp
xorps %xmm0, %xmm0
movaps %xmm0, -32(%rax)
movaps %xmm0, -48(%rax)
movq $0, -16(%rax)
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_7: # %.preheader132
# =>This Loop Header: Depth=1
# Child Loop BB0_8 Depth 2
movq -224(%rbp,%rax,8), %rcx
movq -144(%rbp,%rax,8), %rdx
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_8: # Parent Loop BB0_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm3
mulss %xmm2, %xmm3
movslq (%rdx,%rsi,4), %rdi
mulss %xmm1, %xmm2
addss (%r12,%rdi,4), %xmm2
addss %xmm3, %xmm0
movss %xmm2, (%r12,%rdi,4)
incq %rsi
cmpq $1, %rsi
je .LBB0_8
# %bb.9: # in Loop: Header=BB0_7 Depth=1
movss %xmm0, (%r13,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB0_7
# %bb.10: # %.preheader131.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_11: # %.preheader131
# =>This Inner Loop Header: Depth=1
movss (%r12,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_11
# %bb.12: # %.preheader130.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_13: # %.preheader130
# =>This Inner Loop Header: Depth=1
movss .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%r13,%rbx,4), %xmm0
movss %xmm0, (%r15,%rbx,4)
cvtss2sd %xmm0, %xmm0
movss (%r14,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.2, %edi
movl %ebx, %esi
movb $2, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_13
# %bb.14: # %.preheader129.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_15: # %.preheader129
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_15
# %bb.16: # %.preheader128.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_17: # %.preheader128
# =>This Loop Header: Depth=1
# Child Loop BB0_18 Depth 2
# Child Loop BB0_23 Depth 2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %eax
cltq
movq -224(%rbp,%rax,8), %rcx
movq -144(%rbp,%rax,8), %rdx
xorps %xmm2, %xmm2
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_18: # Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%rdx,%rsi,4), %rdi
movss (%rcx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r12,%rdi,4), %xmm0
addss %xmm0, %xmm2
incq %rsi
cmpq $1, %rsi
je .LBB0_18
# %bb.19: # in Loop: Header=BB0_17 Depth=1
movaps %xmm2, %xmm0
addss .LCPI0_4(%rip), %xmm0
movaps .LCPI0_5(%rip), %xmm6 # xmm6 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm6, %xmm0
movss (%r15,%rax,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
mulss %xmm4, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
movaps %xmm0, %xmm5
addsd %xmm1, %xmm5
xorpd %xmm7, %xmm7
ucomisd %xmm5, %xmm7
jbe .LBB0_22
# %bb.20: # in Loop: Header=BB0_17 Depth=1
addss .LCPI0_6(%rip), %xmm2
xorps %xmm6, %xmm2
mulss %xmm2, %xmm4
xorps %xmm1, %xmm1
cvtss2sd %xmm4, %xmm1
movaps %xmm0, %xmm2
addsd %xmm1, %xmm2
ucomisd .LCPI0_7(%rip), %xmm2
jbe .LBB0_22
# %bb.21: # in Loop: Header=BB0_17 Depth=1
xorps %xmm6, %xmm3
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
.LBB0_22: # in Loop: Header=BB0_17 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_23: # Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
mulsd %xmm1, %xmm2
movslq (%rdx,%rsi,4), %rdi
movss (%r12,%rdi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
addsd %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtsd2ss %xmm3, %xmm2
movss %xmm2, (%r12,%rdi,4)
incq %rsi
cmpq $1, %rsi
je .LBB0_23
# %bb.24: # in Loop: Header=BB0_17 Depth=1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%r14,%rax,4)
incl %ebx
cmpl $10, %ebx
jne .LBB0_17
# %bb.25: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_26: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_26
# %bb.27:
leaq -384(%rbp), %rdi
callq hipFree
leaq -304(%rbp), %rdi
callq hipFree
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "idem generovat x_0\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gradient value: %d %f\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Li: %d %f xi: %f\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "x[%d] = %f \n"
.size .L.str.3, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
/******************************************************************************/
#define BLOCK_SIZE_X 256
#define BLOCK_SIZE_Y 1
__constant__ int c_maxiter;
__constant__ float c_xmin;
__constant__ float c_ymin;
__constant__ float c_x_step;
__constant__ float c_y_step;
__constant__ int c_N;
__constant__ int c_width;
__constant__ int c_rowsize;
/******************************************************************************/
__device__ void d_smooth_fast_element_colormap(int iter, float re2, float im2,
int *rp, int *gp, int *bp)
{
if(iter == c_maxiter) {
/* black */
*rp = 0; // Red channel
*gp = 0; // Green channel
*bp = 0; // Blue channel
}
else {
int brightness = 256.*log2(1.75-log2(0.5)+iter-log2(log2(re2+im2)))/log2((float)c_maxiter);
*rp = brightness; // Red channel
*gp = brightness; // Green channel
*bp = 255; // Blue channel
}
}
__device__ void in_cardioid_or_period2_bulb(int *iterp, float x, float y)
{
float xdiff = x - 0.25;
float y2 = y * y;
float q = xdiff*xdiff + y2;
// Is the point in the cardioid?
if (q * (q + xdiff) < 0.25*y2) {
*iterp = c_maxiter;
}
else if ((x+1.)*(x+1.) + y2 < 0.0625) { // Is the point in the period-2 bulb?
*iterp = c_maxiter;
}
}
__global__ void compute_escape_time(char *img)
{
int offset = gridDim.x*blockDim.x*threadIdx.y + blockIdx.x*blockDim.x+threadIdx.x;
int i = offset / c_width;
int j = offset - i * c_width;
int iteration = 0;
float c_re = c_xmin + c_x_step/2 + j*c_x_step;
float c_im = c_ymin + c_y_step/2 + i*c_y_step;
float zn_re = 0.;
float zn_im = 0.;
float tmp_re;
float re2 = 0.;
float im2 = 0.;
int bailout_radius2 = 2*2;
int r, g, b;
if (offset < c_N) {
// Check if point is in cardioid or in period-2 bulb
in_cardioid_or_period2_bulb(&iteration, c_re, c_im);
while ((re2 + im2 < bailout_radius2) && (iteration < c_maxiter)) {
tmp_re = re2 - im2 + c_re;
zn_im = zn_re * zn_im;
zn_im += zn_im; // Multiply by two
zn_im += c_im;
zn_re = tmp_re;
re2 = zn_re * zn_re;
im2 = zn_im * zn_im;
iteration++;
}
d_smooth_fast_element_colormap(iteration, re2, im2, &r, &g, &b);
offset = c_rowsize * i + 3 * j; // offset in the image array
img[offset++] = b;
img[offset++] = g;
img[offset] = r;
}
}
/******************************************************************************/
extern "C" void kernel_wrapper(char *h_img, int d_img_size, int MAX_ITER,
float X_MIN, float Y_MIN, float h_x_step,
float h_y_step, int N, int WIDTH, int row_size)
{
dim3 block_size, grid_size;
char *d_img;
// Create the grid of blocks of threads
block_size.x = BLOCK_SIZE_X; block_size.y = BLOCK_SIZE_Y;
grid_size.x = N / (block_size.x*block_size.y) + (N%(block_size.x*block_size.y) == 0? 0 : 1);
cudaMalloc((void **)&d_img, d_img_size);
cudaMemset(d_img, 0, d_img_size);
// Copy memory to constant memory in the device
cudaMemcpyToSymbol(c_maxiter, &MAX_ITER, sizeof(int));
cudaMemcpyToSymbol(c_xmin, &X_MIN, sizeof(float));
cudaMemcpyToSymbol(c_ymin, &Y_MIN, sizeof(float));
cudaMemcpyToSymbol(c_x_step, &h_x_step, sizeof(float));
cudaMemcpyToSymbol(c_y_step, &h_y_step, sizeof(float));
cudaMemcpyToSymbol(c_N, &N, sizeof(int));
cudaMemcpyToSymbol(c_width, &WIDTH, sizeof(int));
cudaMemcpyToSymbol(c_rowsize, &row_size, sizeof(int));
// Call the kernel to execute on the gpu
compute_escape_time<<<grid_size, block_size>>>(d_img);
// Copy the results back
cudaMemcpy(h_img, d_img, d_img_size, cudaMemcpyDeviceToHost);
cudaFree(d_img);
} | .file "tmpxft_0004c352_00000000-6_escape_time_5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30d_smooth_fast_element_colormapiffPiS_S_
.type _Z30d_smooth_fast_element_colormapiffPiS_S_, @function
_Z30d_smooth_fast_element_colormapiffPiS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z30d_smooth_fast_element_colormapiffPiS_S_, .-_Z30d_smooth_fast_element_colormapiffPiS_S_
.globl _Z27in_cardioid_or_period2_bulbPiff
.type _Z27in_cardioid_or_period2_bulbPiff, @function
_Z27in_cardioid_or_period2_bulbPiff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z27in_cardioid_or_period2_bulbPiff, .-_Z27in_cardioid_or_period2_bulbPiff
.globl _Z39__device_stub__Z19compute_escape_timePcPc
.type _Z39__device_stub__Z19compute_escape_timePcPc, @function
_Z39__device_stub__Z19compute_escape_timePcPc:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19compute_escape_timePc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z19compute_escape_timePcPc, .-_Z39__device_stub__Z19compute_escape_timePcPc
.globl _Z19compute_escape_timePc
.type _Z19compute_escape_timePc, @function
_Z19compute_escape_timePc:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z19compute_escape_timePcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z19compute_escape_timePc, .-_Z19compute_escape_timePc
.globl kernel_wrapper
.type kernel_wrapper, @function
kernel_wrapper:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 12(%rsp)
movl %ecx, %eax
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rdx
movq %rdx, 72(%rsp)
xorl %edx, %edx
movl $1, 56(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
testb %cl, %cl
setne %dl
movzbl %dl, %edx
shrl $8, %eax
addl %edx, %eax
movl %eax, 60(%rsp)
movslq %esi, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
leaq 28(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL9c_maxiter(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 24(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6c_xmin(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 20(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6c_ymin(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8c_x_step(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8c_y_step(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3c_N(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL7c_width(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL9c_rowsize(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $256, 48(%rsp)
movl $1, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rdi
call _Z39__device_stub__Z19compute_escape_timePcPc
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size kernel_wrapper, .-kernel_wrapper
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19compute_escape_timePc"
.LC1:
.string "c_maxiter"
.LC2:
.string "c_xmin"
.LC3:
.string "c_ymin"
.LC4:
.string "c_x_step"
.LC5:
.string "c_y_step"
.LC6:
.string "c_N"
.LC7:
.string "c_width"
.LC8:
.string "c_rowsize"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19compute_escape_timePc(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9c_maxiter(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6c_xmin(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6c_ymin(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8c_x_step(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8c_y_step(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3c_N(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_width(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9c_rowsize(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL9c_rowsize
.comm _ZL9c_rowsize,4,4
.local _ZL7c_width
.comm _ZL7c_width,4,4
.local _ZL3c_N
.comm _ZL3c_N,4,4
.local _ZL8c_y_step
.comm _ZL8c_y_step,4,4
.local _ZL8c_x_step
.comm _ZL8c_x_step,4,4
.local _ZL6c_ymin
.comm _ZL6c_ymin,4,4
.local _ZL6c_xmin
.comm _ZL6c_xmin,4,4
.local _ZL9c_maxiter
.comm _ZL9c_maxiter,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
/******************************************************************************/
#define BLOCK_SIZE_X 256
#define BLOCK_SIZE_Y 1
__constant__ int c_maxiter;
__constant__ float c_xmin;
__constant__ float c_ymin;
__constant__ float c_x_step;
__constant__ float c_y_step;
__constant__ int c_N;
__constant__ int c_width;
__constant__ int c_rowsize;
/******************************************************************************/
__device__ void d_smooth_fast_element_colormap(int iter, float re2, float im2,
int *rp, int *gp, int *bp)
{
if(iter == c_maxiter) {
/* black */
*rp = 0; // Red channel
*gp = 0; // Green channel
*bp = 0; // Blue channel
}
else {
int brightness = 256.*log2(1.75-log2(0.5)+iter-log2(log2(re2+im2)))/log2((float)c_maxiter);
*rp = brightness; // Red channel
*gp = brightness; // Green channel
*bp = 255; // Blue channel
}
}
__device__ void in_cardioid_or_period2_bulb(int *iterp, float x, float y)
{
float xdiff = x - 0.25;
float y2 = y * y;
float q = xdiff*xdiff + y2;
// Is the point in the cardioid?
if (q * (q + xdiff) < 0.25*y2) {
*iterp = c_maxiter;
}
else if ((x+1.)*(x+1.) + y2 < 0.0625) { // Is the point in the period-2 bulb?
*iterp = c_maxiter;
}
}
__global__ void compute_escape_time(char *img)
{
int offset = gridDim.x*blockDim.x*threadIdx.y + blockIdx.x*blockDim.x+threadIdx.x;
int i = offset / c_width;
int j = offset - i * c_width;
int iteration = 0;
float c_re = c_xmin + c_x_step/2 + j*c_x_step;
float c_im = c_ymin + c_y_step/2 + i*c_y_step;
float zn_re = 0.;
float zn_im = 0.;
float tmp_re;
float re2 = 0.;
float im2 = 0.;
int bailout_radius2 = 2*2;
int r, g, b;
if (offset < c_N) {
// Check if point is in cardioid or in period-2 bulb
in_cardioid_or_period2_bulb(&iteration, c_re, c_im);
while ((re2 + im2 < bailout_radius2) && (iteration < c_maxiter)) {
tmp_re = re2 - im2 + c_re;
zn_im = zn_re * zn_im;
zn_im += zn_im; // Multiply by two
zn_im += c_im;
zn_re = tmp_re;
re2 = zn_re * zn_re;
im2 = zn_im * zn_im;
iteration++;
}
d_smooth_fast_element_colormap(iteration, re2, im2, &r, &g, &b);
offset = c_rowsize * i + 3 * j; // offset in the image array
img[offset++] = b;
img[offset++] = g;
img[offset] = r;
}
}
/******************************************************************************/
extern "C" void kernel_wrapper(char *h_img, int d_img_size, int MAX_ITER,
float X_MIN, float Y_MIN, float h_x_step,
float h_y_step, int N, int WIDTH, int row_size)
{
dim3 block_size, grid_size;
char *d_img;
// Create the grid of blocks of threads
block_size.x = BLOCK_SIZE_X; block_size.y = BLOCK_SIZE_Y;
grid_size.x = N / (block_size.x*block_size.y) + (N%(block_size.x*block_size.y) == 0? 0 : 1);
cudaMalloc((void **)&d_img, d_img_size);
cudaMemset(d_img, 0, d_img_size);
// Copy memory to constant memory in the device
cudaMemcpyToSymbol(c_maxiter, &MAX_ITER, sizeof(int));
cudaMemcpyToSymbol(c_xmin, &X_MIN, sizeof(float));
cudaMemcpyToSymbol(c_ymin, &Y_MIN, sizeof(float));
cudaMemcpyToSymbol(c_x_step, &h_x_step, sizeof(float));
cudaMemcpyToSymbol(c_y_step, &h_y_step, sizeof(float));
cudaMemcpyToSymbol(c_N, &N, sizeof(int));
cudaMemcpyToSymbol(c_width, &WIDTH, sizeof(int));
cudaMemcpyToSymbol(c_rowsize, &row_size, sizeof(int));
// Call the kernel to execute on the gpu
compute_escape_time<<<grid_size, block_size>>>(d_img);
// Copy the results back
cudaMemcpy(h_img, d_img, d_img_size, cudaMemcpyDeviceToHost);
cudaFree(d_img);
} | #ifndef _ESCAPE_TIME_5_H_
#define _ESCAPE_TIME_5_H_
__device__ void d_smooth_fast_element_colormap(int iter, float re2, float im2,
int *rp, int *gp, int *bp);
__device__ void in_cardioid_or_period2_bulb(int *iterp, float x, float y);
__global__ void compute_escape_time(char *img);
void kernel_wrapper(char *h_img, int d_img_size, int MAX_ITER, float X_MIN,
float Y_MIN, float h_x_step, float h_y_step,
int N, int WIDTH, int row_size);
#endif // _ESCAPE_TIME_5_H_ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef _ESCAPE_TIME_5_H_
#define _ESCAPE_TIME_5_H_
__device__ void d_smooth_fast_element_colormap(int iter, float re2, float im2,
int *rp, int *gp, int *bp);
__device__ void in_cardioid_or_period2_bulb(int *iterp, float x, float y);
__global__ void compute_escape_time(char *img);
void kernel_wrapper(char *h_img, int d_img_size, int MAX_ITER, float X_MIN,
float Y_MIN, float h_x_step, float h_y_step,
int N, int WIDTH, int row_size);
#endif // _ESCAPE_TIME_5_H_ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef _ESCAPE_TIME_5_H_
#define _ESCAPE_TIME_5_H_
__device__ void d_smooth_fast_element_colormap(int iter, float re2, float im2,
int *rp, int *gp, int *bp);
__device__ void in_cardioid_or_period2_bulb(int *iterp, float x, float y);
__global__ void compute_escape_time(char *img);
void kernel_wrapper(char *h_img, int d_img_size, int MAX_ITER, float X_MIN,
float Y_MIN, float h_x_step, float h_y_step,
int N, int WIDTH, int row_size);
#endif // _ESCAPE_TIME_5_H_ | .text
.file "escape_time_5.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c352_00000000-6_escape_time_5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30d_smooth_fast_element_colormapiffPiS_S_
.type _Z30d_smooth_fast_element_colormapiffPiS_S_, @function
_Z30d_smooth_fast_element_colormapiffPiS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z30d_smooth_fast_element_colormapiffPiS_S_, .-_Z30d_smooth_fast_element_colormapiffPiS_S_
.globl _Z27in_cardioid_or_period2_bulbPiff
.type _Z27in_cardioid_or_period2_bulbPiff, @function
_Z27in_cardioid_or_period2_bulbPiff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z27in_cardioid_or_period2_bulbPiff, .-_Z27in_cardioid_or_period2_bulbPiff
.globl _Z39__device_stub__Z19compute_escape_timePcPc
.type _Z39__device_stub__Z19compute_escape_timePcPc, @function
_Z39__device_stub__Z19compute_escape_timePcPc:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19compute_escape_timePc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z19compute_escape_timePcPc, .-_Z39__device_stub__Z19compute_escape_timePcPc
.globl _Z19compute_escape_timePc
.type _Z19compute_escape_timePc, @function
_Z19compute_escape_timePc:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z19compute_escape_timePcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z19compute_escape_timePc, .-_Z19compute_escape_timePc
.globl kernel_wrapper
.type kernel_wrapper, @function
kernel_wrapper:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 12(%rsp)
movl %ecx, %eax
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rdx
movq %rdx, 72(%rsp)
xorl %edx, %edx
movl $1, 56(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
testb %cl, %cl
setne %dl
movzbl %dl, %edx
shrl $8, %eax
addl %edx, %eax
movl %eax, 60(%rsp)
movslq %esi, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
leaq 28(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL9c_maxiter(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 24(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6c_xmin(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 20(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6c_ymin(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8c_x_step(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8c_y_step(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3c_N(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL7c_width(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL9c_rowsize(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $256, 48(%rsp)
movl $1, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rdi
call _Z39__device_stub__Z19compute_escape_timePcPc
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size kernel_wrapper, .-kernel_wrapper
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19compute_escape_timePc"
.LC1:
.string "c_maxiter"
.LC2:
.string "c_xmin"
.LC3:
.string "c_ymin"
.LC4:
.string "c_x_step"
.LC5:
.string "c_y_step"
.LC6:
.string "c_N"
.LC7:
.string "c_width"
.LC8:
.string "c_rowsize"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19compute_escape_timePc(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9c_maxiter(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6c_xmin(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6c_ymin(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8c_x_step(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8c_y_step(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3c_N(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_width(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9c_rowsize(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL9c_rowsize
.comm _ZL9c_rowsize,4,4
.local _ZL7c_width
.comm _ZL7c_width,4,4
.local _ZL3c_N
.comm _ZL3c_N,4,4
.local _ZL8c_y_step
.comm _ZL8c_y_step,4,4
.local _ZL8c_x_step
.comm _ZL8c_x_step,4,4
.local _ZL6c_ymin
.comm _ZL6c_ymin,4,4
.local _ZL6c_xmin
.comm _ZL6c_xmin,4,4
.local _ZL9c_maxiter
.comm _ZL9c_maxiter,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "escape_time_5.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void NNResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth);
float yRatio = (float)(inputHeight - 1) / (outputHeight);
int x = (int) (xRatio * (px+.5f));
int y = (int) (yRatio * (py+.5f));
output[py * outputWidth + px] = input[y*inputWidth + x];
}
} | code for sm_80
Function : _Z16NNResampleKernelPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R4, c[0x0][0x178] ; /* 0x00005e0000047b06 */
/* 0x000e220000201400 */
/*00b0*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*00c0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fd2000fffe03f */
/*00d0*/ I2F R3, UR4 ; /* 0x0000000400037d06 */
/* 0x000e700008201400 */
/*00e0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x001e300000001000 */
/*00f0*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e620000000000 */
/*0100*/ FFMA R2, -R4, R5, 1 ; /* 0x3f80000004027423 */
/* 0x001fc80000000105 */
/*0110*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fc80000000005 */
/*0120*/ FFMA R5, R3, R2, RZ ; /* 0x0000000203057223 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, -R4, R5, R3 ; /* 0x0000000504067223 */
/* 0x000fc80000000103 */
/*0140*/ FFMA R2, R2, R6, R5 ; /* 0x0000000602027223 */
/* 0x000fe20000000005 */
/*0150*/ @!P0 BRA 0x1b0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0170*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0003 */
/*0190*/ CALL.REL.NOINC 0x570 ; /* 0x000003d000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0003 */
/*01b0*/ I2F R4, c[0x0][0x17c] ; /* 0x00005f0000047b06 */
/* 0x000e220000201400 */
/*01c0*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe40000000800 */
/*01d0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fd2000fffe03f */
/*01e0*/ I2F R3, UR4 ; /* 0x0000000400037d06 */
/* 0x000e700008201400 */
/*01f0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x001e300000001000 */
/*0200*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e620000000000 */
/*0210*/ FFMA R6, -R4, R5, 1 ; /* 0x3f80000004067423 */
/* 0x001fc80000000105 */
/*0220*/ FFMA R6, R5, R6, R5 ; /* 0x0000000605067223 */
/* 0x000fc80000000005 */
/*0230*/ FFMA R5, R3, R6, RZ ; /* 0x0000000603057223 */
/* 0x000fc800000000ff */
/*0240*/ FFMA R7, -R4, R5, R3 ; /* 0x0000000504077223 */
/* 0x000fc80000000103 */
/*0250*/ FFMA R6, R6, R7, R5 ; /* 0x0000000706067223 */
/* 0x000fe20000000005 */
/*0260*/ @!P0 BRA 0x2c0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0280*/ MOV R4, 0x2b0 ; /* 0x000002b000047802 */
/* 0x000fe20000000f00 */
/*0290*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0003 */
/*02a0*/ CALL.REL.NOINC 0x570 ; /* 0x000002c000007944 */
/* 0x000fea0003c00000 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0003 */
/*02c0*/ IABS R8, c[0x0][0x178] ; /* 0x00005e0000087a13 */
/* 0x000fe20000000000 */
/*02d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*02e0*/ IABS R9, R0 ; /* 0x0000000000097213 */
/* 0x000fe40000000000 */
/*02f0*/ I2F.RP R3, R8 ; /* 0x0000000800037306 */
/* 0x000e300000209400 */
/*0300*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0310*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*0320*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0340*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0350*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0360*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fc800078e0004 */
/*0370*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0009 */
/*0380*/ IMAD.HI.U32 R5, R5, R7, RZ ; /* 0x0000000705057227 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*03a0*/ IMAD R3, R8, R3, R7 ; /* 0x0000000308037224 */
/* 0x000fca00078e0207 */
/*03b0*/ ISETP.GT.U32.AND P2, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f44070 */
/*03c0*/ @!P2 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x000000010303a824 */
/* 0x000fe200078e0a08 */
/*03d0*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fe40007ffe0ff */
/*03e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f45270 */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*0400*/ LOP3.LUT R3, R0, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0000037a12 */
/* 0x000fc800078e3cff */
/*0410*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f26270 */
/*0420*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fcc0007ffe0ff */
/*0430*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0440*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff05aa12 */
/* 0x000fc800078e33ff */
/*0450*/ I2F R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000201400 */
/*0460*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0470*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fc800078e0200 */
/*0480*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*0490*/ FADD R7, R4, 0.5 ; /* 0x3f00000004077421 */
/* 0x001fe40000000000 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*04b0*/ FMUL R7, R7, R6 ; /* 0x0000000607077220 */
/* 0x000fe40000400000 */
/*04c0*/ FADD R3, R3, 0.5 ; /* 0x3f00000003037421 */
/* 0x002fc80000000000 */
/*04d0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000fe2000020f100 */
/*04e0*/ FMUL R6, R3, R2 ; /* 0x0000000203067220 */
/* 0x000fce0000400000 */
/*04f0*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e24000020f100 */
/*0500*/ IMAD R2, R7, c[0x0][0x170], R6 ; /* 0x00005c0007027a24 */
/* 0x001fc800078e0206 */
/*0510*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*0520*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a24 */
/* 0x000fc800078e0200 */
/*0540*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0550*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ SHF.R.U32.HI R5, RZ, 0x17, R6 ; /* 0x00000017ff057819 */
/* 0x000fe40000011606 */
/*0580*/ SHF.R.U32.HI R3, RZ, 0x17, R7.reuse ; /* 0x00000017ff037819 */
/* 0x100fe40000011607 */
/*0590*/ LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050b7812 */
/* 0x000fe400078ec0ff */
/*05a0*/ LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03097812 */
/* 0x000fe200078ec0ff */
/*05b0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*05c0*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fe40007ffe0ff */
/*05d0*/ IADD3 R8, R9, -0x1, RZ ; /* 0xffffffff09087810 */
/* 0x000fc40007ffe0ff */
/*05e0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*05f0*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*0600*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff058224 */
/* 0x000fe200078e00ff */
/*0610*/ @!P0 BRA 0x790 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0620*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1c200 */
/*0630*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0640*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0650*/ @P0 BRA 0xb70 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0660*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c803 */
/*0670*/ @!P0 BRA 0xb50 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0680*/ FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ; /* 0x7f8000000700780b */
/* 0x040fe40003f5d200 */
/*0690*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*06a0*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fd60003f1d200 */
/*06b0*/ @!P1 BRA !P2, 0xb50 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*06c0*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*06d0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*06e0*/ @P1 BRA 0xb30 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*06f0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0710*/ @P0 BRA 0xb00 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0720*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0730*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0740*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe400078e00ff */
/*0750*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ; /* 0xffffffc0ff058424 */
/* 0x000fe400078e00ff */
/*0760*/ @!P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007038823 */
/* 0x000fe400000000ff */
/*0770*/ @!P1 FFMA R6, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006069823 */
/* 0x000fe200000000ff */
/*0780*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*0790*/ LEA R7, R11, 0xc0800000, 0x17 ; /* 0xc08000000b077811 */
/* 0x000fca00078eb8ff */
/*07a0*/ IMAD.IADD R7, R6, 0x1, -R7 ; /* 0x0000000106077824 */
/* 0x000fe200078e0a07 */
/*07b0*/ IADD3 R6, R9, -0x7f, RZ ; /* 0xffffff8109067810 */
/* 0x000fc60007ffe0ff */
/*07c0*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e220000001000 */
/*07d0*/ FADD.FTZ R10, -R7, -RZ ; /* 0x800000ff070a7221 */
/* 0x000fe40000010100 */
/*07e0*/ IMAD R3, R6, -0x800000, R3 ; /* 0xff80000006037824 */
/* 0x000fe400078e0203 */
/*07f0*/ FFMA R9, R8, R10, 1 ; /* 0x3f80000008097423 */
/* 0x001fc8000000000a */
/*0800*/ FFMA R12, R8, R9, R8 ; /* 0x00000009080c7223 */
/* 0x000fc80000000008 */
/*0810*/ FFMA R8, R3, R12, RZ ; /* 0x0000000c03087223 */
/* 0x000fc800000000ff */
/*0820*/ FFMA R9, R10, R8, R3 ; /* 0x000000080a097223 */
/* 0x000fc80000000003 */
/*0830*/ FFMA R9, R12, R9, R8 ; /* 0x000000090c097223 */
/* 0x000fe20000000008 */
/*0840*/ IADD3 R8, R6, 0x7f, -R11 ; /* 0x0000007f06087810 */
/* 0x000fc60007ffe80b */
/*0850*/ FFMA R10, R10, R9, R3 ; /* 0x000000090a0a7223 */
/* 0x000fe40000000003 */
/*0860*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fe400078e0205 */
/*0870*/ FFMA R3, R12, R10, R9 ; /* 0x0000000a0c037223 */
/* 0x000fca0000000009 */
/*0880*/ SHF.R.U32.HI R6, RZ, 0x17, R3 ; /* 0x00000017ff067819 */
/* 0x000fc80000011603 */
/*0890*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*08a0*/ IMAD.IADD R11, R6, 0x1, R8 ; /* 0x00000001060b7824 */
/* 0x000fca00078e0208 */
/*08b0*/ IADD3 R5, R11, -0x1, RZ ; /* 0xffffffff0b057810 */
/* 0x000fc80007ffe0ff */
/*08c0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*08d0*/ @!P0 BRA 0xae0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*08f0*/ @P0 BRA 0xab0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0900*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0910*/ @P0 BRA 0xb80 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0920*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0930*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0940*/ @!P0 BRA 0xb80 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0950*/ FFMA.RZ R5, R12.reuse, R10.reuse, R9.reuse ; /* 0x0000000a0c057223 */
/* 0x1c0fe2000000c009 */
/*0960*/ IADD3 R8, R11.reuse, 0x20, RZ ; /* 0x000000200b087810 */
/* 0x040fe20007ffe0ff */
/*0970*/ FFMA.RM R6, R12.reuse, R10.reuse, R9.reuse ; /* 0x0000000a0c067223 */
/* 0x1c0fe20000004009 */
/*0980*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0990*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*09a0*/ FFMA.RP R5, R12, R10, R9 ; /* 0x0000000a0c057223 */
/* 0x000fe20000008009 */
/*09b0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*09c0*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0b */
/*09d0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*09e0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*09f0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0a00*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0a10*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0a20*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0a30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0a40*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0a50*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0a60*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0a70*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0a80*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*0a90*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*0aa0*/ BRA 0xb80 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0ac0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xb80 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD R3, R8, 0x800000, R3 ; /* 0x0080000008037824 */
/* 0x000fe200078e0203 */
/*0af0*/ BRA 0xb80 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b00*/ LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fc800078e4803 */
/*0b10*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b20*/ BRA 0xb80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b30*/ LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fe200078e4803 */
/*0b40*/ BRA 0xb80 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b50*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0b60*/ BRA 0xb80 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b70*/ FADD.FTZ R3, R7, R6 ; /* 0x0000000607037221 */
/* 0x000fe40000010000 */
/*0b80*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0b90*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff46004007950 */
/* 0x000fea0003c3ffff */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void NNResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth);
float yRatio = (float)(inputHeight - 1) / (outputHeight);
int x = (int) (xRatio * (px+.5f));
int y = (int) (yRatio * (py+.5f));
output[py * outputWidth + px] = input[y*inputWidth + x];
}
} | .file "tmpxft_0008c790_00000000-6_NNResampleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii
.type _Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii, @function
_Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16NNResampleKernelPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii, .-_Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii
.globl _Z16NNResampleKernelPfS_iiii
.type _Z16NNResampleKernelPfS_iiii, @function
_Z16NNResampleKernelPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16NNResampleKernelPfS_iiii, .-_Z16NNResampleKernelPfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16NNResampleKernelPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16NNResampleKernelPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void NNResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth);
float yRatio = (float)(inputHeight - 1) / (outputHeight);
int x = (int) (xRatio * (px+.5f));
int y = (int) (yRatio * (py+.5f));
output[py * outputWidth + px] = input[y*inputWidth + x];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NNResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth);
float yRatio = (float)(inputHeight - 1) / (outputHeight);
int x = (int) (xRatio * (px+.5f));
int y = (int) (yRatio * (py+.5f));
output[py * outputWidth + px] = input[y*inputWidth + x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NNResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth);
float yRatio = (float)(inputHeight - 1) / (outputHeight);
int x = (int) (xRatio * (px+.5f));
int y = (int) (yRatio * (py+.5f));
output[py * outputWidth + px] = input[y*inputWidth + x];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16NNResampleKernelPfS_iiii
.globl _Z16NNResampleKernelPfS_iiii
.p2align 8
.type _Z16NNResampleKernelPfS_iiii,@function
_Z16NNResampleKernelPfS_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s2, s4, 31
s_load_b64 s[6:7], s[0:1], 0x10
s_add_i32 s3, s4, s2
v_cvt_f32_i32_e32 v6, s5
s_xor_b32 s8, s3, s2
v_ashrrev_i32_e32 v3, 31, v1
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s3, 0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s3, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s6, -1
v_cvt_f32_i32_e32 v5, s3
s_add_i32 s3, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v7, s3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v10, null, v6, v6, v7
v_div_scale_f32 v16, s3, v7, v6, v7
v_rcp_f32_e32 v12, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v10, v12, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v12, v15, v12
v_add_nc_u32_e32 v4, v1, v3
v_add_nc_u32_e32 v0, v0, v2
v_cvt_f32_i32_e32 v2, s4
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_scale_f32 v8, null, v2, v2, v5
v_div_scale_f32 v13, s2, v5, v2, v5
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v8
v_mul_lo_u32 v9, v0, s8
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v8, v11, 1.0
v_sub_nc_u32_e32 v4, v4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v14, v11
v_add_nc_u32_e32 v9, 1, v0
v_cmp_le_u32_e32 vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v9, vcc_lo
v_subrev_nc_u32_e32 v9, s8, v4
v_dual_cndmask_b32 v4, v4, v9 :: v_dual_add_nc_u32 v9, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s8, v4
v_mul_f32_e32 v4, v13, v11
v_cndmask_b32_e32 v0, v0, v9, vcc_lo
v_mul_f32_e32 v9, v16, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v14, -v8, v4, v13
s_mov_b32 vcc_lo, s2
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v15, -v10, v9, v16
v_fmac_f32_e32 v4, v14, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v3
v_fmac_f32_e32 v9, v15, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v8, -v8, v4, v13
v_mul_lo_u32 v3, v0, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, -v10, v9, v16
v_div_fmas_f32 v4, v8, v11, v4
s_mov_b32 vcc_lo, s3
v_cvt_f32_i32_e32 v0, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_div_fmas_f32 v8, v10, v12, v9
v_div_fixup_f32 v2, v4, v2, v5
v_sub_nc_u32_e32 v3, v1, v3
v_add_f32_e32 v0, 0.5, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f32 v4, v8, v6, v7
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v0, v4, v0 :: v_dual_add_f32 v3, 0.5, v3
v_cvt_i32_f32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v3
v_cvt_i32_f32_e32 v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, s6, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16NNResampleKernelPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16NNResampleKernelPfS_iiii, .Lfunc_end0-_Z16NNResampleKernelPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16NNResampleKernelPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16NNResampleKernelPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NNResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth);
float yRatio = (float)(inputHeight - 1) / (outputHeight);
int x = (int) (xRatio * (px+.5f));
int y = (int) (yRatio * (py+.5f));
output[py * outputWidth + px] = input[y*inputWidth + x];
}
} | .text
.file "NNResampleKernel.hip"
.globl _Z31__device_stub__NNResampleKernelPfS_iiii # -- Begin function _Z31__device_stub__NNResampleKernelPfS_iiii
.p2align 4, 0x90
.type _Z31__device_stub__NNResampleKernelPfS_iiii,@function
_Z31__device_stub__NNResampleKernelPfS_iiii: # @_Z31__device_stub__NNResampleKernelPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16NNResampleKernelPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z31__device_stub__NNResampleKernelPfS_iiii, .Lfunc_end0-_Z31__device_stub__NNResampleKernelPfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16NNResampleKernelPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16NNResampleKernelPfS_iiii,@object # @_Z16NNResampleKernelPfS_iiii
.section .rodata,"a",@progbits
.globl _Z16NNResampleKernelPfS_iiii
.p2align 3, 0x0
_Z16NNResampleKernelPfS_iiii:
.quad _Z31__device_stub__NNResampleKernelPfS_iiii
.size _Z16NNResampleKernelPfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16NNResampleKernelPfS_iiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__NNResampleKernelPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16NNResampleKernelPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16NNResampleKernelPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R4, c[0x0][0x178] ; /* 0x00005e0000047b06 */
/* 0x000e220000201400 */
/*00b0*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*00c0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fd2000fffe03f */
/*00d0*/ I2F R3, UR4 ; /* 0x0000000400037d06 */
/* 0x000e700008201400 */
/*00e0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x001e300000001000 */
/*00f0*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e620000000000 */
/*0100*/ FFMA R2, -R4, R5, 1 ; /* 0x3f80000004027423 */
/* 0x001fc80000000105 */
/*0110*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fc80000000005 */
/*0120*/ FFMA R5, R3, R2, RZ ; /* 0x0000000203057223 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, -R4, R5, R3 ; /* 0x0000000504067223 */
/* 0x000fc80000000103 */
/*0140*/ FFMA R2, R2, R6, R5 ; /* 0x0000000602027223 */
/* 0x000fe20000000005 */
/*0150*/ @!P0 BRA 0x1b0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0170*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0003 */
/*0190*/ CALL.REL.NOINC 0x570 ; /* 0x000003d000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0003 */
/*01b0*/ I2F R4, c[0x0][0x17c] ; /* 0x00005f0000047b06 */
/* 0x000e220000201400 */
/*01c0*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe40000000800 */
/*01d0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fd2000fffe03f */
/*01e0*/ I2F R3, UR4 ; /* 0x0000000400037d06 */
/* 0x000e700008201400 */
/*01f0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x001e300000001000 */
/*0200*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e620000000000 */
/*0210*/ FFMA R6, -R4, R5, 1 ; /* 0x3f80000004067423 */
/* 0x001fc80000000105 */
/*0220*/ FFMA R6, R5, R6, R5 ; /* 0x0000000605067223 */
/* 0x000fc80000000005 */
/*0230*/ FFMA R5, R3, R6, RZ ; /* 0x0000000603057223 */
/* 0x000fc800000000ff */
/*0240*/ FFMA R7, -R4, R5, R3 ; /* 0x0000000504077223 */
/* 0x000fc80000000103 */
/*0250*/ FFMA R6, R6, R7, R5 ; /* 0x0000000706067223 */
/* 0x000fe20000000005 */
/*0260*/ @!P0 BRA 0x2c0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0280*/ MOV R4, 0x2b0 ; /* 0x000002b000047802 */
/* 0x000fe20000000f00 */
/*0290*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0003 */
/*02a0*/ CALL.REL.NOINC 0x570 ; /* 0x000002c000007944 */
/* 0x000fea0003c00000 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0003 */
/*02c0*/ IABS R8, c[0x0][0x178] ; /* 0x00005e0000087a13 */
/* 0x000fe20000000000 */
/*02d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*02e0*/ IABS R9, R0 ; /* 0x0000000000097213 */
/* 0x000fe40000000000 */
/*02f0*/ I2F.RP R3, R8 ; /* 0x0000000800037306 */
/* 0x000e300000209400 */
/*0300*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0310*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*0320*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0340*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0350*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0360*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fc800078e0004 */
/*0370*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0009 */
/*0380*/ IMAD.HI.U32 R5, R5, R7, RZ ; /* 0x0000000705057227 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*03a0*/ IMAD R3, R8, R3, R7 ; /* 0x0000000308037224 */
/* 0x000fca00078e0207 */
/*03b0*/ ISETP.GT.U32.AND P2, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f44070 */
/*03c0*/ @!P2 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x000000010303a824 */
/* 0x000fe200078e0a08 */
/*03d0*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fe40007ffe0ff */
/*03e0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f45270 */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*0400*/ LOP3.LUT R3, R0, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0000037a12 */
/* 0x000fc800078e3cff */
/*0410*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f26270 */
/*0420*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fcc0007ffe0ff */
/*0430*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0440*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff05aa12 */
/* 0x000fc800078e33ff */
/*0450*/ I2F R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000201400 */
/*0460*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0470*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fc800078e0200 */
/*0480*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*0490*/ FADD R7, R4, 0.5 ; /* 0x3f00000004077421 */
/* 0x001fe40000000000 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*04b0*/ FMUL R7, R7, R6 ; /* 0x0000000607077220 */
/* 0x000fe40000400000 */
/*04c0*/ FADD R3, R3, 0.5 ; /* 0x3f00000003037421 */
/* 0x002fc80000000000 */
/*04d0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000fe2000020f100 */
/*04e0*/ FMUL R6, R3, R2 ; /* 0x0000000203067220 */
/* 0x000fce0000400000 */
/*04f0*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e24000020f100 */
/*0500*/ IMAD R2, R7, c[0x0][0x170], R6 ; /* 0x00005c0007027a24 */
/* 0x001fc800078e0206 */
/*0510*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*0520*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a24 */
/* 0x000fc800078e0200 */
/*0540*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0550*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ SHF.R.U32.HI R5, RZ, 0x17, R6 ; /* 0x00000017ff057819 */
/* 0x000fe40000011606 */
/*0580*/ SHF.R.U32.HI R3, RZ, 0x17, R7.reuse ; /* 0x00000017ff037819 */
/* 0x100fe40000011607 */
/*0590*/ LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050b7812 */
/* 0x000fe400078ec0ff */
/*05a0*/ LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03097812 */
/* 0x000fe200078ec0ff */
/*05b0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*05c0*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fe40007ffe0ff */
/*05d0*/ IADD3 R8, R9, -0x1, RZ ; /* 0xffffffff09087810 */
/* 0x000fc40007ffe0ff */
/*05e0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*05f0*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*0600*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff058224 */
/* 0x000fe200078e00ff */
/*0610*/ @!P0 BRA 0x790 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0620*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1c200 */
/*0630*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0640*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0650*/ @P0 BRA 0xb70 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0660*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c803 */
/*0670*/ @!P0 BRA 0xb50 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0680*/ FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ; /* 0x7f8000000700780b */
/* 0x040fe40003f5d200 */
/*0690*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*06a0*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fd60003f1d200 */
/*06b0*/ @!P1 BRA !P2, 0xb50 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*06c0*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*06d0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*06e0*/ @P1 BRA 0xb30 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*06f0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0710*/ @P0 BRA 0xb00 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0720*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0730*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0740*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe400078e00ff */
/*0750*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ; /* 0xffffffc0ff058424 */
/* 0x000fe400078e00ff */
/*0760*/ @!P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007038823 */
/* 0x000fe400000000ff */
/*0770*/ @!P1 FFMA R6, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006069823 */
/* 0x000fe200000000ff */
/*0780*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*0790*/ LEA R7, R11, 0xc0800000, 0x17 ; /* 0xc08000000b077811 */
/* 0x000fca00078eb8ff */
/*07a0*/ IMAD.IADD R7, R6, 0x1, -R7 ; /* 0x0000000106077824 */
/* 0x000fe200078e0a07 */
/*07b0*/ IADD3 R6, R9, -0x7f, RZ ; /* 0xffffff8109067810 */
/* 0x000fc60007ffe0ff */
/*07c0*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e220000001000 */
/*07d0*/ FADD.FTZ R10, -R7, -RZ ; /* 0x800000ff070a7221 */
/* 0x000fe40000010100 */
/*07e0*/ IMAD R3, R6, -0x800000, R3 ; /* 0xff80000006037824 */
/* 0x000fe400078e0203 */
/*07f0*/ FFMA R9, R8, R10, 1 ; /* 0x3f80000008097423 */
/* 0x001fc8000000000a */
/*0800*/ FFMA R12, R8, R9, R8 ; /* 0x00000009080c7223 */
/* 0x000fc80000000008 */
/*0810*/ FFMA R8, R3, R12, RZ ; /* 0x0000000c03087223 */
/* 0x000fc800000000ff */
/*0820*/ FFMA R9, R10, R8, R3 ; /* 0x000000080a097223 */
/* 0x000fc80000000003 */
/*0830*/ FFMA R9, R12, R9, R8 ; /* 0x000000090c097223 */
/* 0x000fe20000000008 */
/*0840*/ IADD3 R8, R6, 0x7f, -R11 ; /* 0x0000007f06087810 */
/* 0x000fc60007ffe80b */
/*0850*/ FFMA R10, R10, R9, R3 ; /* 0x000000090a0a7223 */
/* 0x000fe40000000003 */
/*0860*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fe400078e0205 */
/*0870*/ FFMA R3, R12, R10, R9 ; /* 0x0000000a0c037223 */
/* 0x000fca0000000009 */
/*0880*/ SHF.R.U32.HI R6, RZ, 0x17, R3 ; /* 0x00000017ff067819 */
/* 0x000fc80000011603 */
/*0890*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*08a0*/ IMAD.IADD R11, R6, 0x1, R8 ; /* 0x00000001060b7824 */
/* 0x000fca00078e0208 */
/*08b0*/ IADD3 R5, R11, -0x1, RZ ; /* 0xffffffff0b057810 */
/* 0x000fc80007ffe0ff */
/*08c0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*08d0*/ @!P0 BRA 0xae0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*08f0*/ @P0 BRA 0xab0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0900*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0910*/ @P0 BRA 0xb80 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0920*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0930*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0940*/ @!P0 BRA 0xb80 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0950*/ FFMA.RZ R5, R12.reuse, R10.reuse, R9.reuse ; /* 0x0000000a0c057223 */
/* 0x1c0fe2000000c009 */
/*0960*/ IADD3 R8, R11.reuse, 0x20, RZ ; /* 0x000000200b087810 */
/* 0x040fe20007ffe0ff */
/*0970*/ FFMA.RM R6, R12.reuse, R10.reuse, R9.reuse ; /* 0x0000000a0c067223 */
/* 0x1c0fe20000004009 */
/*0980*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0990*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*09a0*/ FFMA.RP R5, R12, R10, R9 ; /* 0x0000000a0c057223 */
/* 0x000fe20000008009 */
/*09b0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*09c0*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0b */
/*09d0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*09e0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*09f0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0a00*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0a10*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0a20*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0a30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0a40*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0a50*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0a60*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0a70*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0a80*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*0a90*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*0aa0*/ BRA 0xb80 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0ac0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xb80 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD R3, R8, 0x800000, R3 ; /* 0x0080000008037824 */
/* 0x000fe200078e0203 */
/*0af0*/ BRA 0xb80 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b00*/ LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fc800078e4803 */
/*0b10*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b20*/ BRA 0xb80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b30*/ LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fe200078e4803 */
/*0b40*/ BRA 0xb80 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b50*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0b60*/ BRA 0xb80 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b70*/ FADD.FTZ R3, R7, R6 ; /* 0x0000000607037221 */
/* 0x000fe40000010000 */
/*0b80*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0b90*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff46004007950 */
/* 0x000fea0003c3ffff */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16NNResampleKernelPfS_iiii
.globl _Z16NNResampleKernelPfS_iiii
.p2align 8
.type _Z16NNResampleKernelPfS_iiii,@function
_Z16NNResampleKernelPfS_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s2, s4, 31
s_load_b64 s[6:7], s[0:1], 0x10
s_add_i32 s3, s4, s2
v_cvt_f32_i32_e32 v6, s5
s_xor_b32 s8, s3, s2
v_ashrrev_i32_e32 v3, 31, v1
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s3, 0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s3, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s6, -1
v_cvt_f32_i32_e32 v5, s3
s_add_i32 s3, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v7, s3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v10, null, v6, v6, v7
v_div_scale_f32 v16, s3, v7, v6, v7
v_rcp_f32_e32 v12, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v10, v12, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v12, v15, v12
v_add_nc_u32_e32 v4, v1, v3
v_add_nc_u32_e32 v0, v0, v2
v_cvt_f32_i32_e32 v2, s4
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_scale_f32 v8, null, v2, v2, v5
v_div_scale_f32 v13, s2, v5, v2, v5
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v8
v_mul_lo_u32 v9, v0, s8
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v8, v11, 1.0
v_sub_nc_u32_e32 v4, v4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v14, v11
v_add_nc_u32_e32 v9, 1, v0
v_cmp_le_u32_e32 vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v9, vcc_lo
v_subrev_nc_u32_e32 v9, s8, v4
v_dual_cndmask_b32 v4, v4, v9 :: v_dual_add_nc_u32 v9, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s8, v4
v_mul_f32_e32 v4, v13, v11
v_cndmask_b32_e32 v0, v0, v9, vcc_lo
v_mul_f32_e32 v9, v16, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v14, -v8, v4, v13
s_mov_b32 vcc_lo, s2
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v15, -v10, v9, v16
v_fmac_f32_e32 v4, v14, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v3
v_fmac_f32_e32 v9, v15, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v8, -v8, v4, v13
v_mul_lo_u32 v3, v0, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, -v10, v9, v16
v_div_fmas_f32 v4, v8, v11, v4
s_mov_b32 vcc_lo, s3
v_cvt_f32_i32_e32 v0, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_div_fmas_f32 v8, v10, v12, v9
v_div_fixup_f32 v2, v4, v2, v5
v_sub_nc_u32_e32 v3, v1, v3
v_add_f32_e32 v0, 0.5, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f32 v4, v8, v6, v7
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v0, v4, v0 :: v_dual_add_f32 v3, 0.5, v3
v_cvt_i32_f32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v3
v_cvt_i32_f32_e32 v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, s6, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16NNResampleKernelPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16NNResampleKernelPfS_iiii, .Lfunc_end0-_Z16NNResampleKernelPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16NNResampleKernelPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16NNResampleKernelPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008c790_00000000-6_NNResampleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii
.type _Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii, @function
_Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16NNResampleKernelPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii, .-_Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii
.globl _Z16NNResampleKernelPfS_iiii
.type _Z16NNResampleKernelPfS_iiii, @function
_Z16NNResampleKernelPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z16NNResampleKernelPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16NNResampleKernelPfS_iiii, .-_Z16NNResampleKernelPfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16NNResampleKernelPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16NNResampleKernelPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NNResampleKernel.hip"
.globl _Z31__device_stub__NNResampleKernelPfS_iiii # -- Begin function _Z31__device_stub__NNResampleKernelPfS_iiii
.p2align 4, 0x90
.type _Z31__device_stub__NNResampleKernelPfS_iiii,@function
_Z31__device_stub__NNResampleKernelPfS_iiii: # @_Z31__device_stub__NNResampleKernelPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16NNResampleKernelPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z31__device_stub__NNResampleKernelPfS_iiii, .Lfunc_end0-_Z31__device_stub__NNResampleKernelPfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16NNResampleKernelPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16NNResampleKernelPfS_iiii,@object # @_Z16NNResampleKernelPfS_iiii
.section .rodata,"a",@progbits
.globl _Z16NNResampleKernelPfS_iiii
.p2align 3, 0x0
_Z16NNResampleKernelPfS_iiii:
.quad _Z31__device_stub__NNResampleKernelPfS_iiii
.size _Z16NNResampleKernelPfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16NNResampleKernelPfS_iiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__NNResampleKernelPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16NNResampleKernelPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <sys/time.h>
#define min(a, b) (a < b ? a : b)
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__device__ void gpu_bottomUpMerge(double* source, double* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__global__ void gpu_mergesort(double* source, double* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
}
void mergesort_gpu(double* data, long size, int xThreadPerBlock, int xBlocksPerGrid) {
dim3 threadsPerBlock;
dim3 blocksPerGrid;
threadsPerBlock.x = xThreadPerBlock;
threadsPerBlock.y = 1;
threadsPerBlock.z = 1;
blocksPerGrid.x = xBlocksPerGrid;
blocksPerGrid.y = 1;
blocksPerGrid.z = 1;
double* D_data;
double* D_swp;
dim3* D_threads;
dim3* D_blocks;
cudaMalloc((void**) &D_data, size * sizeof(double));
cudaMalloc((void**) &D_swp, size * sizeof(double));
cudaMemcpy(D_data, data, size * sizeof(long), cudaMemcpyHostToDevice);
cudaMalloc((void**) &D_threads, sizeof(dim3));
cudaMalloc((void**) &D_blocks, sizeof(dim3));
cudaMemcpy(D_threads, &threadsPerBlock, sizeof(dim3), cudaMemcpyHostToDevice);
cudaMemcpy(D_blocks, &blocksPerGrid, sizeof(dim3), cudaMemcpyHostToDevice);
double* A = D_data;
double* B = D_swp;
long nThreads = threadsPerBlock.x * threadsPerBlock.y * threadsPerBlock.z *
blocksPerGrid.x * blocksPerGrid.y * blocksPerGrid.z;
for (int width = 2; width < (size << 1); width <<= 1) {
long slices = size / ((nThreads) * width) + 1;
gpu_mergesort<<<blocksPerGrid, threadsPerBlock>>>(A, B, size, width, slices, D_threads, D_blocks);
A = A == D_data ? D_swp : D_data;
B = B == D_data ? D_swp : D_data;
}
cudaMemcpy(data, A, size * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(A);
cudaFree(B);
} | .file "tmpxft_001b112e_00000000-6_gpuMergesort.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6getIdxP4dim3S0_
.type _Z6getIdxP4dim3S0_, @function
_Z6getIdxP4dim3S0_:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z6getIdxP4dim3S0_, .-_Z6getIdxP4dim3S0_
.globl _Z17gpu_bottomUpMergePdS_lll
.type _Z17gpu_bottomUpMergePdS_lll, @function
_Z17gpu_bottomUpMergePdS_lll:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z17gpu_bottomUpMergePdS_lll, .-_Z17gpu_bottomUpMergePdS_lll
.globl _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_
.type _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_, @function
_Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_:
.LFB3696:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13gpu_mergesortPdS_lllP4dim3S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_, .-_Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_
.globl _Z13gpu_mergesortPdS_lllP4dim3S1_
.type _Z13gpu_mergesortPdS_lllP4dim3S1_, @function
_Z13gpu_mergesortPdS_lllP4dim3S1_:
.LFB3697:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z13gpu_mergesortPdS_lllP4dim3S1_, .-_Z13gpu_mergesortPdS_lllP4dim3S1_
.globl _Z13mergesort_gpuPdlii
.type _Z13mergesort_gpuPdlii, @function
_Z13mergesort_gpuPdlii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r15
movq %rdi, 24(%rsp)
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %edx, 64(%rsp)
movl %ecx, 76(%rsp)
leaq 0(,%rsi,8), %rbx
movq %rbx, 16(%rsp)
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $12, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 76(%rsp), %rsi
movl $1, %ecx
movl $12, %edx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %r12
movq 40(%rsp), %r13
movl 64(%rsp), %eax
imull 68(%rsp), %eax
imull 72(%rsp), %eax
imull 76(%rsp), %eax
imull 80(%rsp), %eax
movl %eax, %edx
imull 84(%rsp), %edx
movq %rdx, 8(%rsp)
leaq (%r14,%r14), %r15
cmpq $2, %r15
jle .L16
movl $2, %ebx
movl $2, %ebp
jmp .L20
.L17:
movq 32(%rsp), %rax
cmpq %r12, %rax
je .L26
movq %rax, %r12
.L18:
cmpq %r13, %rax
je .L27
movq %rax, %r13
.L19:
addl %ebx, %ebx
movslq %ebx, %rbp
cmpq %r15, %rbp
jge .L16
.L20:
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 8(%rsp), %rcx
imulq %rbp, %rcx
movq %r14, %rax
cqto
idivq %rcx
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq 64(%rsp)
.cfi_def_cfa_offset 176
movq 64(%rsp), %r9
leaq 1(%rax), %r8
movq %rbp, %rcx
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L26:
movq 40(%rsp), %r12
jmp .L18
.L27:
movq 40(%rsp), %r13
jmp .L19
.L16:
movl $2, %ecx
movq 16(%rsp), %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq %r12, %rdi
call cudaFree@PLT
movq %r13, %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z13mergesort_gpuPdlii, .-_Z13mergesort_gpuPdlii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13gpu_mergesortPdS_lllP4dim3S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_mergesortPdS_lllP4dim3S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <sys/time.h>
#define min(a, b) (a < b ? a : b)
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__device__ void gpu_bottomUpMerge(double* source, double* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__global__ void gpu_mergesort(double* source, double* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
}
void mergesort_gpu(double* data, long size, int xThreadPerBlock, int xBlocksPerGrid) {
dim3 threadsPerBlock;
dim3 blocksPerGrid;
threadsPerBlock.x = xThreadPerBlock;
threadsPerBlock.y = 1;
threadsPerBlock.z = 1;
blocksPerGrid.x = xBlocksPerGrid;
blocksPerGrid.y = 1;
blocksPerGrid.z = 1;
double* D_data;
double* D_swp;
dim3* D_threads;
dim3* D_blocks;
cudaMalloc((void**) &D_data, size * sizeof(double));
cudaMalloc((void**) &D_swp, size * sizeof(double));
cudaMemcpy(D_data, data, size * sizeof(long), cudaMemcpyHostToDevice);
cudaMalloc((void**) &D_threads, sizeof(dim3));
cudaMalloc((void**) &D_blocks, sizeof(dim3));
cudaMemcpy(D_threads, &threadsPerBlock, sizeof(dim3), cudaMemcpyHostToDevice);
cudaMemcpy(D_blocks, &blocksPerGrid, sizeof(dim3), cudaMemcpyHostToDevice);
double* A = D_data;
double* B = D_swp;
long nThreads = threadsPerBlock.x * threadsPerBlock.y * threadsPerBlock.z *
blocksPerGrid.x * blocksPerGrid.y * blocksPerGrid.z;
for (int width = 2; width < (size << 1); width <<= 1) {
long slices = size / ((nThreads) * width) + 1;
gpu_mergesort<<<blocksPerGrid, threadsPerBlock>>>(A, B, size, width, slices, D_threads, D_blocks);
A = A == D_data ? D_swp : D_data;
B = B == D_data ? D_swp : D_data;
}
cudaMemcpy(data, A, size * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(A);
cudaFree(B);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#define min(a, b) (a < b ? a : b)
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__device__ void gpu_bottomUpMerge(double* source, double* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__global__ void gpu_mergesort(double* source, double* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
}
void mergesort_gpu(double* data, long size, int xThreadPerBlock, int xBlocksPerGrid) {
dim3 threadsPerBlock;
dim3 blocksPerGrid;
threadsPerBlock.x = xThreadPerBlock;
threadsPerBlock.y = 1;
threadsPerBlock.z = 1;
blocksPerGrid.x = xBlocksPerGrid;
blocksPerGrid.y = 1;
blocksPerGrid.z = 1;
double* D_data;
double* D_swp;
dim3* D_threads;
dim3* D_blocks;
hipMalloc((void**) &D_data, size * sizeof(double));
hipMalloc((void**) &D_swp, size * sizeof(double));
hipMemcpy(D_data, data, size * sizeof(long), hipMemcpyHostToDevice);
hipMalloc((void**) &D_threads, sizeof(dim3));
hipMalloc((void**) &D_blocks, sizeof(dim3));
hipMemcpy(D_threads, &threadsPerBlock, sizeof(dim3), hipMemcpyHostToDevice);
hipMemcpy(D_blocks, &blocksPerGrid, sizeof(dim3), hipMemcpyHostToDevice);
double* A = D_data;
double* B = D_swp;
long nThreads = threadsPerBlock.x * threadsPerBlock.y * threadsPerBlock.z *
blocksPerGrid.x * blocksPerGrid.y * blocksPerGrid.z;
for (int width = 2; width < (size << 1); width <<= 1) {
long slices = size / ((nThreads) * width) + 1;
gpu_mergesort<<<blocksPerGrid, threadsPerBlock>>>(A, B, size, width, slices, D_threads, D_blocks);
A = A == D_data ? D_swp : D_data;
B = B == D_data ? D_swp : D_data;
}
hipMemcpy(data, A, size * sizeof(double), hipMemcpyDeviceToHost);
hipFree(A);
hipFree(B);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#define min(a, b) (a < b ? a : b)
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__device__ void gpu_bottomUpMerge(double* source, double* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__global__ void gpu_mergesort(double* source, double* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
}
void mergesort_gpu(double* data, long size, int xThreadPerBlock, int xBlocksPerGrid) {
dim3 threadsPerBlock;
dim3 blocksPerGrid;
threadsPerBlock.x = xThreadPerBlock;
threadsPerBlock.y = 1;
threadsPerBlock.z = 1;
blocksPerGrid.x = xBlocksPerGrid;
blocksPerGrid.y = 1;
blocksPerGrid.z = 1;
double* D_data;
double* D_swp;
dim3* D_threads;
dim3* D_blocks;
hipMalloc((void**) &D_data, size * sizeof(double));
hipMalloc((void**) &D_swp, size * sizeof(double));
hipMemcpy(D_data, data, size * sizeof(long), hipMemcpyHostToDevice);
hipMalloc((void**) &D_threads, sizeof(dim3));
hipMalloc((void**) &D_blocks, sizeof(dim3));
hipMemcpy(D_threads, &threadsPerBlock, sizeof(dim3), hipMemcpyHostToDevice);
hipMemcpy(D_blocks, &blocksPerGrid, sizeof(dim3), hipMemcpyHostToDevice);
double* A = D_data;
double* B = D_swp;
long nThreads = threadsPerBlock.x * threadsPerBlock.y * threadsPerBlock.z *
blocksPerGrid.x * blocksPerGrid.y * blocksPerGrid.z;
for (int width = 2; width < (size << 1); width <<= 1) {
long slices = size / ((nThreads) * width) + 1;
gpu_mergesort<<<blocksPerGrid, threadsPerBlock>>>(A, B, size, width, slices, D_threads, D_blocks);
A = A == D_data ? D_swp : D_data;
B = B == D_data ? D_swp : D_data;
}
hipMemcpy(data, A, size * sizeof(double), hipMemcpyDeviceToHost);
hipFree(A);
hipFree(B);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpu_mergesortPdS_lllP4dim3S1_
.globl _Z13gpu_mergesortPdS_lllP4dim3S1_
.p2align 8
.type _Z13gpu_mergesortPdS_lllP4dim3S1_,@function
_Z13gpu_mergesortPdS_lllP4dim3S1_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b256 s[4:11], s[0:1], 0x10
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x4
s_clause 0x1
s_load_b32 s12, s[10:11], 0x8
s_load_b64 s[10:11], s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_mul_i32 s2, s2, s3
s_mul_hi_u32 s3, s8, s6
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s2, s12, v[1:2]
v_bfe_u32 v3, v0, 10, 10
s_mul_i32 s2, s8, s6
v_mul_lo_u32 v1, v2, s11
v_and_b32_e32 v2, 0x3ff, v0
v_cmp_gt_i64_e64 s11, s[8:9], 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v1, v3
v_mad_u64_u32 v[4:5], null, v3, s10, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s2, v4, 0
s_mul_i32 s2, s8, s7
s_add_i32 s2, s3, s2
s_mul_i32 s3, s9, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s2, v4, v[1:2]
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v5
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1]
s_and_b32 s11, s11, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s12, s11
s_cbranch_execz .LBB0_15
v_mad_u64_u32 v[4:5], null, s10, v3, v[2:3]
s_mul_i32 s10, s8, s6
s_mul_hi_u32 s11, s8, s6
s_mul_i32 s16, s9, s6
s_load_b128 s[12:15], s[0:1], 0x0
v_cmp_gt_i64_e64 s1, s[6:7], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s10, v4, 0
s_mul_i32 s10, s8, s7
s_add_i32 s10, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_i32 s10, s10, s16
s_mov_b32 s16, 0
v_mad_u64_u32 v[5:6], null, s10, v4, v[3:4]
s_ashr_i64 s[10:11], s[6:7], 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v3, v5
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s14, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
s_lshl_b64 s[14:15], s[6:7], 3
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s17
.LBB0_3:
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
v_cmp_le_i64_e32 vcc_lo, s[4:5], v[4:5]
v_cmp_ge_i64_e64 s0, s[2:3], s[8:9]
v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s14
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
s_and_b32 s0, exec_lo, s0
s_or_b32 s16, s0, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_15
.LBB0_4:
v_add_co_u32 v4, vcc_lo, v0, s6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_3
v_add_co_u32 v6, vcc_lo, v0, s10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
v_cmp_gt_i64_e64 s0, s[4:5], v[4:5]
v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[6:7]
s_mov_b32 s17, 0
v_mov_b32_e32 v11, v3
v_cndmask_b32_e64 v9, s5, v5, s0
v_cndmask_b32_e64 v8, s4, v4, s0
v_dual_mov_b32 v10, v2 :: v_dual_cndmask_b32 v7, s5, v7
v_cndmask_b32_e32 v6, s4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v6
s_branch .LBB0_7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s18
v_add_co_u32 v0, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v10, s0, v10, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v11, s0, 0, v11, s0
v_cmp_ge_i64_e32 vcc_lo, v[0:1], v[8:9]
v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
s_or_b32 s17, vcc_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_2
.LBB0_7:
s_mov_b32 s19, -1
s_mov_b32 s0, 0
s_mov_b32 s18, exec_lo
v_cmpx_lt_i64_e64 v[12:13], v[6:7]
s_cbranch_execz .LBB0_11
v_cmp_ge_i64_e64 s0, v[14:15], v[8:9]
s_mov_b32 s20, 0
s_mov_b32 s19, exec_lo
v_cmpx_lt_i64_e64 v[14:15], v[8:9]
s_cbranch_execz .LBB0_10
v_lshlrev_b64 v[16:17], 3, v[12:13]
v_lshlrev_b64 v[18:19], 3, v[14:15]
s_or_b32 s0, s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v16, vcc_lo, s12, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v18, vcc_lo, s12, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo
s_clause 0x1
global_load_b64 v[16:17], v[16:17], off
global_load_b64 v[18:19], v[18:19], off
s_waitcnt vmcnt(0)
v_cmp_nlt_f64_e32 vcc_lo, v[16:17], v[18:19]
s_and_b32 s20, vcc_lo, exec_lo
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_not1_b32 s19, s20, exec_lo
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s18, s19
s_cbranch_execz .LBB0_13
v_lshlrev_b64 v[16:17], 3, v[14:15]
s_and_not1_b32 s0, s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s12, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s13, v17, vcc_lo
global_load_b64 v[18:19], v[16:17], off
v_add_co_u32 v16, vcc_lo, v14, 1
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v15, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[10:11], v[18:19], off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s18, s0
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[16:17], 3, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s12, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s13, v17, vcc_lo
v_add_co_u32 v12, vcc_lo, v12, 1
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
global_load_b64 v[18:19], v[16:17], off
v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
s_waitcnt vmcnt(0)
global_store_b64 v[10:11], v[18:19], off
s_branch .LBB0_6
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpu_mergesortPdS_lllP4dim3S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpu_mergesortPdS_lllP4dim3S1_, .Lfunc_end0-_Z13gpu_mergesortPdS_lllP4dim3S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpu_mergesortPdS_lllP4dim3S1_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z13gpu_mergesortPdS_lllP4dim3S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#define min(a, b) (a < b ? a : b)
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__device__ void gpu_bottomUpMerge(double* source, double* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__global__ void gpu_mergesort(double* source, double* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
}
void mergesort_gpu(double* data, long size, int xThreadPerBlock, int xBlocksPerGrid) {
dim3 threadsPerBlock;
dim3 blocksPerGrid;
threadsPerBlock.x = xThreadPerBlock;
threadsPerBlock.y = 1;
threadsPerBlock.z = 1;
blocksPerGrid.x = xBlocksPerGrid;
blocksPerGrid.y = 1;
blocksPerGrid.z = 1;
double* D_data;
double* D_swp;
dim3* D_threads;
dim3* D_blocks;
hipMalloc((void**) &D_data, size * sizeof(double));
hipMalloc((void**) &D_swp, size * sizeof(double));
hipMemcpy(D_data, data, size * sizeof(long), hipMemcpyHostToDevice);
hipMalloc((void**) &D_threads, sizeof(dim3));
hipMalloc((void**) &D_blocks, sizeof(dim3));
hipMemcpy(D_threads, &threadsPerBlock, sizeof(dim3), hipMemcpyHostToDevice);
hipMemcpy(D_blocks, &blocksPerGrid, sizeof(dim3), hipMemcpyHostToDevice);
double* A = D_data;
double* B = D_swp;
long nThreads = threadsPerBlock.x * threadsPerBlock.y * threadsPerBlock.z *
blocksPerGrid.x * blocksPerGrid.y * blocksPerGrid.z;
for (int width = 2; width < (size << 1); width <<= 1) {
long slices = size / ((nThreads) * width) + 1;
gpu_mergesort<<<blocksPerGrid, threadsPerBlock>>>(A, B, size, width, slices, D_threads, D_blocks);
A = A == D_data ? D_swp : D_data;
B = B == D_data ? D_swp : D_data;
}
hipMemcpy(data, A, size * sizeof(double), hipMemcpyDeviceToHost);
hipFree(A);
hipFree(B);
} | .text
.file "gpuMergesort.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_ # -- Begin function _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.p2align 4, 0x90
.type _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_,@function
_Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_: # @_Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13gpu_mergesortPdS_lllP4dim3S1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_, .Lfunc_end0-_Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.cfi_endproc
# -- End function
.globl _Z13mergesort_gpuPdlii # -- Begin function _Z13mergesort_gpuPdlii
.p2align 4, 0x90
.type _Z13mergesort_gpuPdlii,@function
_Z13mergesort_gpuPdlii: # @_Z13mergesort_gpuPdlii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %rbx
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, 24(%rsp)
movl $1, 32(%rsp)
movq %rax, 8(%rsp)
movl $1, 16(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 8(%rsp)
leaq (,%rsi,8), %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbx, 80(%rsp) # 8-byte Spill
movq %rbx, %rsi
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
movl $12, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $12, %esi
callq hipMalloc
movq 56(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $12, %edx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $12, %edx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rbp
movq 64(%rsp), %r13
movq %r15, 96(%rsp) # 8-byte Spill
leaq (%r15,%r15), %rbx
cmpq $3, %rbx
jl .LBB1_1
# %bb.3: # %.lr.ph
movl 28(%rsp), %eax
imull 24(%rsp), %eax
imull 32(%rsp), %eax
imull 8(%rsp), %eax
imull 12(%rsp), %eax
imull 16(%rsp), %eax
movq %rax, 88(%rsp) # 8-byte Spill
movl $2, %r15d
movl $2, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=1
movq 40(%rsp), %r12
cmpq %r12, %rbp
movq 64(%rsp), %rax
movq %r12, %rbp
cmoveq %rax, %rbp
cmpq %r12, %r13
cmoveq %rax, %r12
addl %r15d, %r15d
movslq %r15d, %r14
movq %r12, %r13
cmpq %r14, %rbx
jle .LBB1_2
.LBB1_4: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
movq 24(%rsp), %rdx
movl 32(%rsp), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=1
movq %r14, %rcx
imulq 88(%rsp), %rcx # 8-byte Folded Reload
movq 96(%rsp), %rsi # 8-byte Reload
movq %rsi, %rax
cqto
idivq %rcx
incq %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rbp, 200(%rsp)
movq %r13, 192(%rsp)
movq %rsi, 184(%rsp)
movq %r14, 176(%rsp)
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 176(%rsp), %rax
movq %rax, 232(%rsp)
leaq 168(%rsp), %rax
movq %rax, 240(%rsp)
leaq 160(%rsp), %rax
movq %rax, 248(%rsp)
leaq 152(%rsp), %rax
movq %rax, 256(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z13gpu_mergesortPdS_lllP4dim3S1_, %edi
leaq 208(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_6
.LBB1_1:
movq %r13, %r12
.LBB1_2: # %._crit_edge
movq 80(%rsp), %rdi # 8-byte Reload
movq %rbp, %rsi
movq 72(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq %rbp, %rdi
callq hipFree
movq %r12, %rdi
callq hipFree
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13mergesort_gpuPdlii, .Lfunc_end1-_Z13mergesort_gpuPdlii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_mergesortPdS_lllP4dim3S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpu_mergesortPdS_lllP4dim3S1_,@object # @_Z13gpu_mergesortPdS_lllP4dim3S1_
.section .rodata,"a",@progbits
.globl _Z13gpu_mergesortPdS_lllP4dim3S1_
.p2align 3, 0x0
_Z13gpu_mergesortPdS_lllP4dim3S1_:
.quad _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.size _Z13gpu_mergesortPdS_lllP4dim3S1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13gpu_mergesortPdS_lllP4dim3S1_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpu_mergesortPdS_lllP4dim3S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b112e_00000000-6_gpuMergesort.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6getIdxP4dim3S0_
.type _Z6getIdxP4dim3S0_, @function
_Z6getIdxP4dim3S0_:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z6getIdxP4dim3S0_, .-_Z6getIdxP4dim3S0_
.globl _Z17gpu_bottomUpMergePdS_lll
.type _Z17gpu_bottomUpMergePdS_lll, @function
_Z17gpu_bottomUpMergePdS_lll:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z17gpu_bottomUpMergePdS_lll, .-_Z17gpu_bottomUpMergePdS_lll
.globl _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_
.type _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_, @function
_Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_:
.LFB3696:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13gpu_mergesortPdS_lllP4dim3S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_, .-_Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_
.globl _Z13gpu_mergesortPdS_lllP4dim3S1_
.type _Z13gpu_mergesortPdS_lllP4dim3S1_, @function
_Z13gpu_mergesortPdS_lllP4dim3S1_:
.LFB3697:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z13gpu_mergesortPdS_lllP4dim3S1_, .-_Z13gpu_mergesortPdS_lllP4dim3S1_
.globl _Z13mergesort_gpuPdlii
.type _Z13mergesort_gpuPdlii, @function
_Z13mergesort_gpuPdlii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r15
movq %rdi, 24(%rsp)
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %edx, 64(%rsp)
movl %ecx, 76(%rsp)
leaq 0(,%rsi,8), %rbx
movq %rbx, 16(%rsp)
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $12, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 76(%rsp), %rsi
movl $1, %ecx
movl $12, %edx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %r12
movq 40(%rsp), %r13
movl 64(%rsp), %eax
imull 68(%rsp), %eax
imull 72(%rsp), %eax
imull 76(%rsp), %eax
imull 80(%rsp), %eax
movl %eax, %edx
imull 84(%rsp), %edx
movq %rdx, 8(%rsp)
leaq (%r14,%r14), %r15
cmpq $2, %r15
jle .L16
movl $2, %ebx
movl $2, %ebp
jmp .L20
.L17:
movq 32(%rsp), %rax
cmpq %r12, %rax
je .L26
movq %rax, %r12
.L18:
cmpq %r13, %rax
je .L27
movq %rax, %r13
.L19:
addl %ebx, %ebx
movslq %ebx, %rbp
cmpq %r15, %rbp
jge .L16
.L20:
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 8(%rsp), %rcx
imulq %rbp, %rcx
movq %r14, %rax
cqto
idivq %rcx
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq 64(%rsp)
.cfi_def_cfa_offset 176
movq 64(%rsp), %r9
leaq 1(%rax), %r8
movq %rbp, %rcx
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z47__device_stub__Z13gpu_mergesortPdS_lllP4dim3S1_PdS_lllP4dim3S1_
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L26:
movq 40(%rsp), %r12
jmp .L18
.L27:
movq 40(%rsp), %r13
jmp .L19
.L16:
movl $2, %ecx
movq 16(%rsp), %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq %r12, %rdi
call cudaFree@PLT
movq %r13, %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z13mergesort_gpuPdlii, .-_Z13mergesort_gpuPdlii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13gpu_mergesortPdS_lllP4dim3S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_mergesortPdS_lllP4dim3S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpuMergesort.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_ # -- Begin function _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.p2align 4, 0x90
.type _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_,@function
_Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_: # @_Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13gpu_mergesortPdS_lllP4dim3S1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_, .Lfunc_end0-_Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.cfi_endproc
# -- End function
.globl _Z13mergesort_gpuPdlii # -- Begin function _Z13mergesort_gpuPdlii
.p2align 4, 0x90
.type _Z13mergesort_gpuPdlii,@function
_Z13mergesort_gpuPdlii: # @_Z13mergesort_gpuPdlii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %rbx
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, 24(%rsp)
movl $1, 32(%rsp)
movq %rax, 8(%rsp)
movl $1, 16(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 8(%rsp)
leaq (,%rsi,8), %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbx, 80(%rsp) # 8-byte Spill
movq %rbx, %rsi
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
movl $12, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $12, %esi
callq hipMalloc
movq 56(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $12, %edx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $12, %edx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rbp
movq 64(%rsp), %r13
movq %r15, 96(%rsp) # 8-byte Spill
leaq (%r15,%r15), %rbx
cmpq $3, %rbx
jl .LBB1_1
# %bb.3: # %.lr.ph
movl 28(%rsp), %eax
imull 24(%rsp), %eax
imull 32(%rsp), %eax
imull 8(%rsp), %eax
imull 12(%rsp), %eax
imull 16(%rsp), %eax
movq %rax, 88(%rsp) # 8-byte Spill
movl $2, %r15d
movl $2, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=1
movq 40(%rsp), %r12
cmpq %r12, %rbp
movq 64(%rsp), %rax
movq %r12, %rbp
cmoveq %rax, %rbp
cmpq %r12, %r13
cmoveq %rax, %r12
addl %r15d, %r15d
movslq %r15d, %r14
movq %r12, %r13
cmpq %r14, %rbx
jle .LBB1_2
.LBB1_4: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
movq 24(%rsp), %rdx
movl 32(%rsp), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=1
movq %r14, %rcx
imulq 88(%rsp), %rcx # 8-byte Folded Reload
movq 96(%rsp), %rsi # 8-byte Reload
movq %rsi, %rax
cqto
idivq %rcx
incq %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rbp, 200(%rsp)
movq %r13, 192(%rsp)
movq %rsi, 184(%rsp)
movq %r14, 176(%rsp)
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 176(%rsp), %rax
movq %rax, 232(%rsp)
leaq 168(%rsp), %rax
movq %rax, 240(%rsp)
leaq 160(%rsp), %rax
movq %rax, 248(%rsp)
leaq 152(%rsp), %rax
movq %rax, 256(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z13gpu_mergesortPdS_lllP4dim3S1_, %edi
leaq 208(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_6
.LBB1_1:
movq %r13, %r12
.LBB1_2: # %._crit_edge
movq 80(%rsp), %rdi # 8-byte Reload
movq %rbp, %rsi
movq 72(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq %rbp, %rdi
callq hipFree
movq %r12, %rdi
callq hipFree
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13mergesort_gpuPdlii, .Lfunc_end1-_Z13mergesort_gpuPdlii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_mergesortPdS_lllP4dim3S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpu_mergesortPdS_lllP4dim3S1_,@object # @_Z13gpu_mergesortPdS_lllP4dim3S1_
.section .rodata,"a",@progbits
.globl _Z13gpu_mergesortPdS_lllP4dim3S1_
.p2align 3, 0x0
_Z13gpu_mergesortPdS_lllP4dim3S1_:
.quad _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.size _Z13gpu_mergesortPdS_lllP4dim3S1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13gpu_mergesortPdS_lllP4dim3S1_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_mergesortPdS_lllP4dim3S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpu_mergesortPdS_lllP4dim3S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <bits/stdc++.h>
using namespace std;
__global__ void kernel(float* r, float* g, float* b, float* r2, float* g2, float* b2, int N, int M, int x) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 512) {
int des = (2*tId + x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*tId];
g2[res] = g[2*tId];
b2[res] = b[2*tId];
}
else {
int des = (2*(tId%512)+1 - x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*(tId%512)+1];
g2[res] = g[2*(tId%512)+1];
b2[res] = b[2*(tId%512)+1];
}
}
int main(int argc, char const *argv[]) {
cudaEvent_t ct1, ct2;
float *R, *G, *B;
float *R_gpu, *G_gpu, *B_gpu;
float *R_gpu2, *G_gpu2, *B_gpu2;
float dt;
int M, N, X = atoi(argv[3]);
FILE *in = fopen(argv[1], "r");
fscanf(in, "%d %d", &M, &N);
int block_size = 256;
int grid_size = (int) ceil( (float) (M * N) / block_size);
R = new float[M*N];
G = new float[M*N];
B = new float[M*N];
cudaMalloc(&R_gpu, sizeof(float) * N * M);
cudaMalloc(&G_gpu, sizeof(float) * N * M);
cudaMalloc(&B_gpu, sizeof(float) * N * M);
cudaMalloc(&R_gpu2, sizeof(float) * N * M);
cudaMalloc(&G_gpu2, sizeof(float) * N * M);
cudaMalloc(&B_gpu2, sizeof(float) * N * M);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &R[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &G[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &B[i]);
fclose (in);
cudaMemcpy(R_gpu, R, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(G_gpu, G, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B, sizeof(float) * N * M, cudaMemcpyHostToDevice);
// Solo para pruebas
cudaMemcpy(R_gpu2, R, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(G_gpu2, G, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu2, B, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
kernel<<<grid_size, block_size>>>(R_gpu, G_gpu, B_gpu, R_gpu2, G_gpu2, B_gpu2, N, M, X);
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
cudaMemcpy(R, R_gpu2, sizeof(float) * N * M, cudaMemcpyDeviceToHost);
cudaMemcpy(G, G_gpu2, sizeof(float) * N * M, cudaMemcpyDeviceToHost);
cudaMemcpy(B, B_gpu2, sizeof(float) * N * M, cudaMemcpyDeviceToHost);
FILE * res;
res = fopen (argv[2],"w");
fprintf(res, "%d %d\n", M, N);
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", R[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", G[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", B[i], i == N * M - 1 ? '\n' : ' ');
fclose (res);
cudaFree(R_gpu);
cudaFree(G_gpu);
cudaFree(B_gpu);
cudaFree(R_gpu2);
cudaFree(G_gpu2);
cudaFree(B_gpu2);
delete R;
delete G;
delete B;
return 0;
} | code for sm_80
Function : _Z6kernelPfS_S_S_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x190] ; /* 0x0000640000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD.SHL.U32 R5, R0.reuse, 0x2, RZ ; /* 0x0000000200057824 */
/* 0x040fe200078e00ff */
/*0080*/ ISETP.GE.AND P0, PT, R0, 0x200, PT ; /* 0x000002000000780c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 LOP3.LUT R0, R5, 0x3fe, RZ, 0xc0, !PT ; /* 0x000003fe05000812 */
/* 0x000fc800078ec0ff */
/*00a0*/ @P0 LOP3.LUT R0, R0, 0x1, RZ, 0xfc, !PT ; /* 0x0000000100000812 */
/* 0x000fc800078efcff */
/*00b0*/ @P0 IADD3 R4, R0, -c[0x0][0x198], RZ ; /* 0x8000660000040a10 */
/* 0x000fe40007ffe0ff */
/*00c0*/ @!P0 MOV R0, R5 ; /* 0x0000000500008202 */
/* 0x000fca0000000f00 */
/*00d0*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020b */
/*00e0*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0100*/ @!P0 IADD3 R4, R5, c[0x0][0x198], RZ ; /* 0x0000660005048a10 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0120*/ ISETP.GT.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fc8000bf04270 */
/*0130*/ SEL R10, R4, RZ, !P0 ; /* 0x000000ff040a7207 */
/* 0x000fca0004000000 */
/*0140*/ IMAD.WIDE R4, R10, R11, c[0x0][0x178] ; /* 0x00005e000a047625 */
/* 0x000fca00078e020b */
/*0150*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fe8000c101906 */
/*0160*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.WIDE R8, R10, R11, c[0x0][0x180] ; /* 0x000060000a087625 */
/* 0x000fc800078e020b */
/*0180*/ IMAD.WIDE R2, R0, R11.reuse, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x080fe200078e020b */
/*0190*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fea000c101906 */
/*01a0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x188] ; /* 0x000062000a0a7625 */
/* 0x000fca00078e020b */
/*01c0*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x004fe2000c101906 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <bits/stdc++.h>
using namespace std;
__global__ void kernel(float* r, float* g, float* b, float* r2, float* g2, float* b2, int N, int M, int x) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 512) {
int des = (2*tId + x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*tId];
g2[res] = g[2*tId];
b2[res] = b[2*tId];
}
else {
int des = (2*(tId%512)+1 - x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*(tId%512)+1];
g2[res] = g[2*(tId%512)+1];
b2[res] = b[2*(tId%512)+1];
}
}
int main(int argc, char const *argv[]) {
cudaEvent_t ct1, ct2;
float *R, *G, *B;
float *R_gpu, *G_gpu, *B_gpu;
float *R_gpu2, *G_gpu2, *B_gpu2;
float dt;
int M, N, X = atoi(argv[3]);
FILE *in = fopen(argv[1], "r");
fscanf(in, "%d %d", &M, &N);
int block_size = 256;
int grid_size = (int) ceil( (float) (M * N) / block_size);
R = new float[M*N];
G = new float[M*N];
B = new float[M*N];
cudaMalloc(&R_gpu, sizeof(float) * N * M);
cudaMalloc(&G_gpu, sizeof(float) * N * M);
cudaMalloc(&B_gpu, sizeof(float) * N * M);
cudaMalloc(&R_gpu2, sizeof(float) * N * M);
cudaMalloc(&G_gpu2, sizeof(float) * N * M);
cudaMalloc(&B_gpu2, sizeof(float) * N * M);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &R[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &G[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &B[i]);
fclose (in);
cudaMemcpy(R_gpu, R, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(G_gpu, G, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B, sizeof(float) * N * M, cudaMemcpyHostToDevice);
// Solo para pruebas
cudaMemcpy(R_gpu2, R, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(G_gpu2, G, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu2, B, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
kernel<<<grid_size, block_size>>>(R_gpu, G_gpu, B_gpu, R_gpu2, G_gpu2, B_gpu2, N, M, X);
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
cudaMemcpy(R, R_gpu2, sizeof(float) * N * M, cudaMemcpyDeviceToHost);
cudaMemcpy(G, G_gpu2, sizeof(float) * N * M, cudaMemcpyDeviceToHost);
cudaMemcpy(B, B_gpu2, sizeof(float) * N * M, cudaMemcpyDeviceToHost);
FILE * res;
res = fopen (argv[2],"w");
fprintf(res, "%d %d\n", M, N);
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", R[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", G[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", B[i], i == N * M - 1 ? '\n' : ' ');
fclose (res);
cudaFree(R_gpu);
cudaFree(G_gpu);
cudaFree(B_gpu);
cudaFree(R_gpu2);
cudaFree(G_gpu2);
cudaFree(B_gpu2);
delete R;
delete G;
delete B;
return 0;
} | .file "tmpxft_001b549e_00000000-6_kernel2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10862:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10862:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
.type _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii, @function
_Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii:
.LFB10884:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6kernelPfS_S_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10884:
.size _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii, .-_Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
.globl _Z6kernelPfS_S_S_S_S_iii
.type _Z6kernelPfS_S_S_S_S_iii, @function
_Z6kernelPfS_S_S_S_S_iii:
.LFB10885:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10885:
.size _Z6kernelPfS_S_S_S_S_iii, .-_Z6kernelPfS_S_S_S_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d %d"
.LC6:
.string "%f"
.LC7:
.string "Tiempo: "
.LC8:
.string "[ms]"
.LC9:
.string "w"
.LC10:
.string "%d %d\n"
.LC11:
.string "%f%c"
.text
.globl main
.type main, @function
main:
.LFB10859:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %rbx
movq %rsi, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movq 8(%rbx), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
leaq 44(%rsp), %rcx
leaq 40(%rsp), %rdx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 40(%rsp), %edi
imull 44(%rsp), %edi
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC12(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2sil %xmm3, %eax
movl %eax, 12(%rsp)
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L13
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movl 40(%rsp), %edi
imull 44(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L50
salq $2, %rdi
call _Znam@PLT
movq %rax, %r15
movl 40(%rsp), %edi
imull 44(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L51
salq $2, %rdi
call _Znam@PLT
movq %rax, %r14
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
movq %r13, %r12
movl $0, %ebp
testl %eax, %eax
jle .L25
.L23:
movq %r12, %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $4, %r12
cmpl %ebp, %eax
jg .L23
testl %eax, %eax
jle .L25
movq %r15, %r12
movl $0, %ebp
.L24:
movq %r12, %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $4, %r12
cmpl %ebp, %eax
jg .L24
testl %eax, %eax
jle .L25
movq %r14, %r12
movl $0, %ebp
.L26:
movq %r12, %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
addq $4, %r12
movl 44(%rsp), %eax
imull 40(%rsp), %eax
cmpl %ebp, %eax
jg .L26
.L25:
movq %rbx, %rdi
call fclose@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl 12(%rsp), %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L27:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 124(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 124(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 88(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 96(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 104(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rax
movq 16(%rax), %rdi
leaq .LC9(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl 44(%rsp), %r8d
movl 40(%rsp), %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
testl %eax, %eax
jle .L33
movl $0, %ebx
leaq .LC11(%rip), %r12
.L30:
subl $1, %eax
cmpl %ebx, %eax
movl $32, %ecx
movl $10, %eax
cmove %eax, %ecx
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L30
testl %eax, %eax
jle .L33
movl $0, %ebx
leaq .LC11(%rip), %r12
.L32:
subl $1, %eax
cmpl %ebx, %eax
movl $32, %ecx
movl $10, %eax
cmove %eax, %ecx
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L32
testl %eax, %eax
jle .L33
movl $0, %ebx
leaq .LC11(%rip), %r12
.L35:
subl $1, %eax
cmpl %ebx, %eax
movl $32, %ecx
movl $10, %eax
cmove %eax, %ecx
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L35
.L33:
movq %rbp, %rdi
call fclose@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movl $4, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r15, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r14, %rdi
call _ZdlPvm@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L16
call __stack_chk_fail@PLT
.L16:
call __cxa_throw_bad_array_new_length@PLT
.L50:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L19
call __stack_chk_fail@PLT
.L19:
call __cxa_throw_bad_array_new_length@PLT
.L51:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L22
call __stack_chk_fail@PLT
.L22:
call __cxa_throw_bad_array_new_length@PLT
.L52:
subq $8, %rsp
.cfi_def_cfa_offset 216
movl 32(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 224
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 232
movl 68(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 240
movq 136(%rsp), %r9
movq 128(%rsp), %r8
movq 120(%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L27
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10859:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z6kernelPfS_S_S_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10887:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_S_S_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10887:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 998244352
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1065353216
.align 4
.LC12:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <bits/stdc++.h>
using namespace std;
__global__ void kernel(float* r, float* g, float* b, float* r2, float* g2, float* b2, int N, int M, int x) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 512) {
int des = (2*tId + x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*tId];
g2[res] = g[2*tId];
b2[res] = b[2*tId];
}
else {
int des = (2*(tId%512)+1 - x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*(tId%512)+1];
g2[res] = g[2*(tId%512)+1];
b2[res] = b[2*(tId%512)+1];
}
}
int main(int argc, char const *argv[]) {
cudaEvent_t ct1, ct2;
float *R, *G, *B;
float *R_gpu, *G_gpu, *B_gpu;
float *R_gpu2, *G_gpu2, *B_gpu2;
float dt;
int M, N, X = atoi(argv[3]);
FILE *in = fopen(argv[1], "r");
fscanf(in, "%d %d", &M, &N);
int block_size = 256;
int grid_size = (int) ceil( (float) (M * N) / block_size);
R = new float[M*N];
G = new float[M*N];
B = new float[M*N];
cudaMalloc(&R_gpu, sizeof(float) * N * M);
cudaMalloc(&G_gpu, sizeof(float) * N * M);
cudaMalloc(&B_gpu, sizeof(float) * N * M);
cudaMalloc(&R_gpu2, sizeof(float) * N * M);
cudaMalloc(&G_gpu2, sizeof(float) * N * M);
cudaMalloc(&B_gpu2, sizeof(float) * N * M);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &R[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &G[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &B[i]);
fclose (in);
cudaMemcpy(R_gpu, R, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(G_gpu, G, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu, B, sizeof(float) * N * M, cudaMemcpyHostToDevice);
// Solo para pruebas
cudaMemcpy(R_gpu2, R, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(G_gpu2, G, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(B_gpu2, B, sizeof(float) * N * M, cudaMemcpyHostToDevice);
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
kernel<<<grid_size, block_size>>>(R_gpu, G_gpu, B_gpu, R_gpu2, G_gpu2, B_gpu2, N, M, X);
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
cudaMemcpy(R, R_gpu2, sizeof(float) * N * M, cudaMemcpyDeviceToHost);
cudaMemcpy(G, G_gpu2, sizeof(float) * N * M, cudaMemcpyDeviceToHost);
cudaMemcpy(B, B_gpu2, sizeof(float) * N * M, cudaMemcpyDeviceToHost);
FILE * res;
res = fopen (argv[2],"w");
fprintf(res, "%d %d\n", M, N);
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", R[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", G[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", B[i], i == N * M - 1 ? '\n' : ' ');
fclose (res);
cudaFree(R_gpu);
cudaFree(G_gpu);
cudaFree(B_gpu);
cudaFree(R_gpu2);
cudaFree(G_gpu2);
cudaFree(B_gpu2);
delete R;
delete G;
delete B;
return 0;
} | #include <hip/hip_runtime.h>
#include <bits/stdc++.h>
using namespace std;
__global__ void kernel(float* r, float* g, float* b, float* r2, float* g2, float* b2, int N, int M, int x) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 512) {
int des = (2*tId + x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*tId];
g2[res] = g[2*tId];
b2[res] = b[2*tId];
}
else {
int des = (2*(tId%512)+1 - x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*(tId%512)+1];
g2[res] = g[2*(tId%512)+1];
b2[res] = b[2*(tId%512)+1];
}
}
int main(int argc, char const *argv[]) {
hipEvent_t ct1, ct2;
float *R, *G, *B;
float *R_gpu, *G_gpu, *B_gpu;
float *R_gpu2, *G_gpu2, *B_gpu2;
float dt;
int M, N, X = atoi(argv[3]);
FILE *in = fopen(argv[1], "r");
fscanf(in, "%d %d", &M, &N);
int block_size = 256;
int grid_size = (int) ceil( (float) (M * N) / block_size);
R = new float[M*N];
G = new float[M*N];
B = new float[M*N];
hipMalloc(&R_gpu, sizeof(float) * N * M);
hipMalloc(&G_gpu, sizeof(float) * N * M);
hipMalloc(&B_gpu, sizeof(float) * N * M);
hipMalloc(&R_gpu2, sizeof(float) * N * M);
hipMalloc(&G_gpu2, sizeof(float) * N * M);
hipMalloc(&B_gpu2, sizeof(float) * N * M);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &R[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &G[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &B[i]);
fclose (in);
hipMemcpy(R_gpu, R, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(G_gpu, G, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B, sizeof(float) * N * M, hipMemcpyHostToDevice);
// Solo para pruebas
hipMemcpy(R_gpu2, R, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(G_gpu2, G, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(B_gpu2, B, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
kernel<<<grid_size, block_size>>>(R_gpu, G_gpu, B_gpu, R_gpu2, G_gpu2, B_gpu2, N, M, X);
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
hipMemcpy(R, R_gpu2, sizeof(float) * N * M, hipMemcpyDeviceToHost);
hipMemcpy(G, G_gpu2, sizeof(float) * N * M, hipMemcpyDeviceToHost);
hipMemcpy(B, B_gpu2, sizeof(float) * N * M, hipMemcpyDeviceToHost);
FILE * res;
res = fopen (argv[2],"w");
fprintf(res, "%d %d\n", M, N);
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", R[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", G[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", B[i], i == N * M - 1 ? '\n' : ' ');
fclose (res);
hipFree(R_gpu);
hipFree(G_gpu);
hipFree(B_gpu);
hipFree(R_gpu2);
hipFree(G_gpu2);
hipFree(B_gpu2);
delete R;
delete G;
delete B;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <bits/stdc++.h>
using namespace std;
__global__ void kernel(float* r, float* g, float* b, float* r2, float* g2, float* b2, int N, int M, int x) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 512) {
int des = (2*tId + x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*tId];
g2[res] = g[2*tId];
b2[res] = b[2*tId];
}
else {
int des = (2*(tId%512)+1 - x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*(tId%512)+1];
g2[res] = g[2*(tId%512)+1];
b2[res] = b[2*(tId%512)+1];
}
}
int main(int argc, char const *argv[]) {
hipEvent_t ct1, ct2;
float *R, *G, *B;
float *R_gpu, *G_gpu, *B_gpu;
float *R_gpu2, *G_gpu2, *B_gpu2;
float dt;
int M, N, X = atoi(argv[3]);
FILE *in = fopen(argv[1], "r");
fscanf(in, "%d %d", &M, &N);
int block_size = 256;
int grid_size = (int) ceil( (float) (M * N) / block_size);
R = new float[M*N];
G = new float[M*N];
B = new float[M*N];
hipMalloc(&R_gpu, sizeof(float) * N * M);
hipMalloc(&G_gpu, sizeof(float) * N * M);
hipMalloc(&B_gpu, sizeof(float) * N * M);
hipMalloc(&R_gpu2, sizeof(float) * N * M);
hipMalloc(&G_gpu2, sizeof(float) * N * M);
hipMalloc(&B_gpu2, sizeof(float) * N * M);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &R[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &G[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &B[i]);
fclose (in);
hipMemcpy(R_gpu, R, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(G_gpu, G, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B, sizeof(float) * N * M, hipMemcpyHostToDevice);
// Solo para pruebas
hipMemcpy(R_gpu2, R, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(G_gpu2, G, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(B_gpu2, B, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
kernel<<<grid_size, block_size>>>(R_gpu, G_gpu, B_gpu, R_gpu2, G_gpu2, B_gpu2, N, M, X);
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
hipMemcpy(R, R_gpu2, sizeof(float) * N * M, hipMemcpyDeviceToHost);
hipMemcpy(G, G_gpu2, sizeof(float) * N * M, hipMemcpyDeviceToHost);
hipMemcpy(B, B_gpu2, sizeof(float) * N * M, hipMemcpyDeviceToHost);
FILE * res;
res = fopen (argv[2],"w");
fprintf(res, "%d %d\n", M, N);
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", R[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", G[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", B[i], i == N * M - 1 ? '\n' : ' ');
fclose (res);
hipFree(R_gpu);
hipFree(G_gpu);
hipFree(B_gpu);
hipFree(R_gpu2);
hipFree(G_gpu2);
hipFree(B_gpu2);
delete R;
delete G;
delete B;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_S_S_S_S_iii
.globl _Z6kernelPfS_S_S_S_S_iii
.p2align 8
.type _Z6kernelPfS_S_S_S_S_iii,@function
_Z6kernelPfS_S_S_S_S_iii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x4c
s_load_b64 s[4:5], s[0:1], 0x30
s_load_b32 s2, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s5, s4
s_mov_b32 s4, exec_lo
v_lshlrev_b32_e32 v0, 1, v1
v_cmpx_lt_i32_e32 0x1ff, v1
s_xor_b32 s4, exec_lo, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v0, v0, 0x3fe, 1
v_subrev_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, s3, v1
v_dual_cndmask_b32 v2, 0, v1 :: v_dual_mov_b32 v1, 0
s_and_not1_saveexec_b32 s4, s4
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v2, 0, v1, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
s_or_b32 exec_lo, exec_lo, s4
s_load_b256 s[4:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_load_b32 v8, v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v8, off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_S_S_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_S_S_S_S_iii, .Lfunc_end0-_Z6kernelPfS_S_S_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_S_S_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_S_S_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <bits/stdc++.h>
using namespace std;
__global__ void kernel(float* r, float* g, float* b, float* r2, float* g2, float* b2, int N, int M, int x) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < 512) {
int des = (2*tId + x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*tId];
g2[res] = g[2*tId];
b2[res] = b[2*tId];
}
else {
int des = (2*(tId%512)+1 - x);
int res = ( des > N * M ) * 0 + ( des <= N * M ) * des;
r2[res] = r[2*(tId%512)+1];
g2[res] = g[2*(tId%512)+1];
b2[res] = b[2*(tId%512)+1];
}
}
int main(int argc, char const *argv[]) {
hipEvent_t ct1, ct2;
float *R, *G, *B;
float *R_gpu, *G_gpu, *B_gpu;
float *R_gpu2, *G_gpu2, *B_gpu2;
float dt;
int M, N, X = atoi(argv[3]);
FILE *in = fopen(argv[1], "r");
fscanf(in, "%d %d", &M, &N);
int block_size = 256;
int grid_size = (int) ceil( (float) (M * N) / block_size);
R = new float[M*N];
G = new float[M*N];
B = new float[M*N];
hipMalloc(&R_gpu, sizeof(float) * N * M);
hipMalloc(&G_gpu, sizeof(float) * N * M);
hipMalloc(&B_gpu, sizeof(float) * N * M);
hipMalloc(&R_gpu2, sizeof(float) * N * M);
hipMalloc(&G_gpu2, sizeof(float) * N * M);
hipMalloc(&B_gpu2, sizeof(float) * N * M);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &R[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &G[i]);
for (int i = 0; i < N * M; ++i) fscanf (in, "%f", &B[i]);
fclose (in);
hipMemcpy(R_gpu, R, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(G_gpu, G, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(B_gpu, B, sizeof(float) * N * M, hipMemcpyHostToDevice);
// Solo para pruebas
hipMemcpy(R_gpu2, R, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(G_gpu2, G, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipMemcpy(B_gpu2, B, sizeof(float) * N * M, hipMemcpyHostToDevice);
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
kernel<<<grid_size, block_size>>>(R_gpu, G_gpu, B_gpu, R_gpu2, G_gpu2, B_gpu2, N, M, X);
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo: " << dt << "[ms]" << '\n';
hipMemcpy(R, R_gpu2, sizeof(float) * N * M, hipMemcpyDeviceToHost);
hipMemcpy(G, G_gpu2, sizeof(float) * N * M, hipMemcpyDeviceToHost);
hipMemcpy(B, B_gpu2, sizeof(float) * N * M, hipMemcpyDeviceToHost);
FILE * res;
res = fopen (argv[2],"w");
fprintf(res, "%d %d\n", M, N);
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", R[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", G[i], i == N * M - 1 ? '\n' : ' ');
for (int i = 0; i < N * M; ++i) fprintf(res, "%f%c", B[i], i == N * M - 1 ? '\n' : ' ');
fclose (res);
hipFree(R_gpu);
hipFree(G_gpu);
hipFree(B_gpu);
hipFree(R_gpu2);
hipFree(G_gpu2);
hipFree(B_gpu2);
delete R;
delete G;
delete B;
return 0;
} | .text
.file "kernel2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPfS_S_S_S_S_iii # -- Begin function _Z21__device_stub__kernelPfS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_S_S_S_S_iii,@function
_Z21__device_stub__kernelPfS_S_S_S_S_iii: # @_Z21__device_stub__kernelPfS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPfS_S_S_S_S_iii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_S_S_S_S_iii, .Lfunc_end0-_Z21__device_stub__kernelPfS_S_S_S_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 112(%rsp) # 8-byte Spill
movq %rbx, 120(%rsp) # 8-byte Spill
movq 8(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %rbp
leaq 8(%rsp), %rdx
leaq 4(%rsp), %rcx
movl $.L.str.1, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq 8(%rsp), %rax
movslq 4(%rsp), %r14
imulq %rax, %r14
cvtsi2ss %r14d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %r14, %rbx
shlq $2, %rbx
testl %r14d, %r14d
movq $-1, %r15
cmovnsq %rbx, %r15
movq %r15, %rdi
callq _Znam
movq %rax, %r13
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %r15, %rdi
callq _Znam
movq %rax, %r15
leaq 56(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r13, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbp, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 4(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %rbx
cmpq %rcx, %r12
jl .LBB1_2
.LBB1_3: # %.preheader70
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph73.preheader
movq %r14, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph73
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbp, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 4(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %rbx
cmpq %rcx, %r12
jl .LBB1_5
.LBB1_6: # %.preheader69
cvttss2si 12(%rsp), %eax # 4-byte Folded Reload
movl %eax, 12(%rsp) # 4-byte Spill
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_9
# %bb.7: # %.lr.ph75.preheader
movq %r15, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbp, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 4(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %rbx
cmpq %rcx, %r12
jl .LBB1_8
.LBB1_9: # %._crit_edge
movq %rbp, %rdi
callq fclose
movq 56(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 64(%rsp), %rdi
callq hipEventCreate
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 12(%rsp), %edi # 4-byte Reload
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
movq 16(%rsp), %r8
movl 4(%rsp), %r9d
movl 8(%rsp), %r10d
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq %rdx, 184(%rsp)
movq %rsi, 176(%rsp)
movq %rdi, 168(%rsp)
movq %r8, 160(%rsp)
movl %r9d, 84(%rsp)
movl %r10d, 80(%rsp)
movq 112(%rsp), %rax # 8-byte Reload
movl %eax, 76(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 176(%rsp), %rax
movq %rax, 232(%rsp)
leaq 168(%rsp), %rax
movq %rax, 240(%rsp)
leaq 160(%rsp), %rax
movq %rax, 248(%rsp)
leaq 84(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rax
movq %rax, 264(%rsp)
leaq 76(%rsp), %rax
movq %rax, 272(%rsp)
leaq 88(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z6kernelPfS_S_S_S_S_iii, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rdi
callq hipEventSynchronize
movq 104(%rsp), %rsi
movq 64(%rsp), %rdx
leaq 208(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 208(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.4, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 88(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .LBB1_13
# %bb.12:
leaq 88(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 32(%rsp), %rsi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 120(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rdi
movl $.L.str.5, %esi
callq fopen
movq %rax, %r12
movl 8(%rsp), %edx
movl 4(%rsp), %ecx
movl $.L.str.6, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_19
# %bb.15: # %.lr.ph77.preheader
xorl %ebx, %ebx
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_18: # %.lr.ph77
# in Loop: Header=BB1_16 Depth=1
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbx
movslq 4(%rsp), %rcx
movslq 8(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %rbx
jge .LBB1_19
.LBB1_16: # %.lr.ph77
# =>This Inner Loop Header: Depth=1
decl %eax
movl $10, %edx
cmpq %rax, %rbx
je .LBB1_18
# %bb.17: # %.lr.ph77
# in Loop: Header=BB1_16 Depth=1
movl $32, %edx
jmp .LBB1_18
.LBB1_19: # %.preheader68
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_24
# %bb.20: # %.lr.ph79.preheader
xorl %ebx, %ebx
jmp .LBB1_21
.p2align 4, 0x90
.LBB1_23: # %.lr.ph79
# in Loop: Header=BB1_21 Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbx
movslq 4(%rsp), %rcx
movslq 8(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %rbx
jge .LBB1_24
.LBB1_21: # %.lr.ph79
# =>This Inner Loop Header: Depth=1
decl %eax
movl $10, %edx
cmpq %rax, %rbx
je .LBB1_23
# %bb.22: # %.lr.ph79
# in Loop: Header=BB1_21 Depth=1
movl $32, %edx
jmp .LBB1_23
.LBB1_24: # %.preheader
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_29
# %bb.25: # %.lr.ph81.preheader
xorl %ebx, %ebx
jmp .LBB1_26
.p2align 4, 0x90
.LBB1_28: # %.lr.ph81
# in Loop: Header=BB1_26 Depth=1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbx
movslq 4(%rsp), %rcx
movslq 8(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %rbx
jge .LBB1_29
.LBB1_26: # %.lr.ph81
# =>This Inner Loop Header: Depth=1
decl %eax
movl $10, %edx
cmpq %rax, %rbx
je .LBB1_28
# %bb.27: # %.lr.ph81
# in Loop: Header=BB1_26 Depth=1
movl $32, %edx
jmp .LBB1_28
.LBB1_29: # %._crit_edge82
movq %r12, %rdi
callq fclose
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_S_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_S_S_S_S_iii,@object # @_Z6kernelPfS_S_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_S_S_S_S_iii
.p2align 3, 0x0
_Z6kernelPfS_S_S_S_S_iii:
.quad _Z21__device_stub__kernelPfS_S_S_S_S_iii
.size _Z6kernelPfS_S_S_S_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Tiempo: "
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[ms]"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d %d\n"
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%f%c"
.size .L.str.7, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfS_S_S_S_S_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_S_S_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_S_S_S_S_iii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPfS_S_S_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x190] ; /* 0x0000640000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD.SHL.U32 R5, R0.reuse, 0x2, RZ ; /* 0x0000000200057824 */
/* 0x040fe200078e00ff */
/*0080*/ ISETP.GE.AND P0, PT, R0, 0x200, PT ; /* 0x000002000000780c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 LOP3.LUT R0, R5, 0x3fe, RZ, 0xc0, !PT ; /* 0x000003fe05000812 */
/* 0x000fc800078ec0ff */
/*00a0*/ @P0 LOP3.LUT R0, R0, 0x1, RZ, 0xfc, !PT ; /* 0x0000000100000812 */
/* 0x000fc800078efcff */
/*00b0*/ @P0 IADD3 R4, R0, -c[0x0][0x198], RZ ; /* 0x8000660000040a10 */
/* 0x000fe40007ffe0ff */
/*00c0*/ @!P0 MOV R0, R5 ; /* 0x0000000500008202 */
/* 0x000fca0000000f00 */
/*00d0*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020b */
/*00e0*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0100*/ @!P0 IADD3 R4, R5, c[0x0][0x198], RZ ; /* 0x0000660005048a10 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0120*/ ISETP.GT.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fc8000bf04270 */
/*0130*/ SEL R10, R4, RZ, !P0 ; /* 0x000000ff040a7207 */
/* 0x000fca0004000000 */
/*0140*/ IMAD.WIDE R4, R10, R11, c[0x0][0x178] ; /* 0x00005e000a047625 */
/* 0x000fca00078e020b */
/*0150*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fe8000c101906 */
/*0160*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.WIDE R8, R10, R11, c[0x0][0x180] ; /* 0x000060000a087625 */
/* 0x000fc800078e020b */
/*0180*/ IMAD.WIDE R2, R0, R11.reuse, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x080fe200078e020b */
/*0190*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fea000c101906 */
/*01a0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x188] ; /* 0x000062000a0a7625 */
/* 0x000fca00078e020b */
/*01c0*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x004fe2000c101906 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_S_S_S_S_iii
.globl _Z6kernelPfS_S_S_S_S_iii
.p2align 8
.type _Z6kernelPfS_S_S_S_S_iii,@function
_Z6kernelPfS_S_S_S_S_iii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x4c
s_load_b64 s[4:5], s[0:1], 0x30
s_load_b32 s2, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s5, s4
s_mov_b32 s4, exec_lo
v_lshlrev_b32_e32 v0, 1, v1
v_cmpx_lt_i32_e32 0x1ff, v1
s_xor_b32 s4, exec_lo, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v0, v0, 0x3fe, 1
v_subrev_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, s3, v1
v_dual_cndmask_b32 v2, 0, v1 :: v_dual_mov_b32 v1, 0
s_and_not1_saveexec_b32 s4, s4
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v2, 0, v1, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
s_or_b32 exec_lo, exec_lo, s4
s_load_b256 s[4:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_load_b32 v8, v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v8, off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_S_S_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_S_S_S_S_iii, .Lfunc_end0-_Z6kernelPfS_S_S_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_S_S_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_S_S_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b549e_00000000-6_kernel2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10862:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10862:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
.type _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii, @function
_Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii:
.LFB10884:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6kernelPfS_S_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10884:
.size _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii, .-_Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
.globl _Z6kernelPfS_S_S_S_S_iii
.type _Z6kernelPfS_S_S_S_S_iii, @function
_Z6kernelPfS_S_S_S_S_iii:
.LFB10885:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10885:
.size _Z6kernelPfS_S_S_S_S_iii, .-_Z6kernelPfS_S_S_S_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d %d"
.LC6:
.string "%f"
.LC7:
.string "Tiempo: "
.LC8:
.string "[ms]"
.LC9:
.string "w"
.LC10:
.string "%d %d\n"
.LC11:
.string "%f%c"
.text
.globl main
.type main, @function
main:
.LFB10859:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %rbx
movq %rsi, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movq 8(%rbx), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
leaq 44(%rsp), %rcx
leaq 40(%rsp), %rdx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 40(%rsp), %edi
imull 44(%rsp), %edi
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC12(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2sil %xmm3, %eax
movl %eax, 12(%rsp)
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L13
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movl 40(%rsp), %edi
imull 44(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L50
salq $2, %rdi
call _Znam@PLT
movq %rax, %r15
movl 40(%rsp), %edi
imull 44(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L51
salq $2, %rdi
call _Znam@PLT
movq %rax, %r14
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
movslq 40(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
movq %r13, %r12
movl $0, %ebp
testl %eax, %eax
jle .L25
.L23:
movq %r12, %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $4, %r12
cmpl %ebp, %eax
jg .L23
testl %eax, %eax
jle .L25
movq %r15, %r12
movl $0, %ebp
.L24:
movq %r12, %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $4, %r12
cmpl %ebp, %eax
jg .L24
testl %eax, %eax
jle .L25
movq %r14, %r12
movl $0, %ebp
.L26:
movq %r12, %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
addq $4, %r12
movl 44(%rsp), %eax
imull 40(%rsp), %eax
cmpl %ebp, %eax
jg .L26
.L25:
movq %rbx, %rdi
call fclose@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl 12(%rsp), %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L27:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 124(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 124(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 88(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 96(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movslq 44(%rsp), %rdx
movslq 40(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 104(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rax
movq 16(%rax), %rdi
leaq .LC9(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl 44(%rsp), %r8d
movl 40(%rsp), %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
testl %eax, %eax
jle .L33
movl $0, %ebx
leaq .LC11(%rip), %r12
.L30:
subl $1, %eax
cmpl %ebx, %eax
movl $32, %ecx
movl $10, %eax
cmove %eax, %ecx
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L30
testl %eax, %eax
jle .L33
movl $0, %ebx
leaq .LC11(%rip), %r12
.L32:
subl $1, %eax
cmpl %ebx, %eax
movl $32, %ecx
movl $10, %eax
cmove %eax, %ecx
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L32
testl %eax, %eax
jle .L33
movl $0, %ebx
leaq .LC11(%rip), %r12
.L35:
subl $1, %eax
cmpl %ebx, %eax
movl $32, %ecx
movl $10, %eax
cmove %eax, %ecx
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl 44(%rsp), %eax
imull 40(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L35
.L33:
movq %rbp, %rdi
call fclose@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movl $4, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r15, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r14, %rdi
call _ZdlPvm@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L16
call __stack_chk_fail@PLT
.L16:
call __cxa_throw_bad_array_new_length@PLT
.L50:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L19
call __stack_chk_fail@PLT
.L19:
call __cxa_throw_bad_array_new_length@PLT
.L51:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L22
call __stack_chk_fail@PLT
.L22:
call __cxa_throw_bad_array_new_length@PLT
.L52:
subq $8, %rsp
.cfi_def_cfa_offset 216
movl 32(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 224
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 232
movl 68(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 240
movq 136(%rsp), %r9
movq 128(%rsp), %r8
movq 120(%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z38__device_stub__Z6kernelPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L27
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10859:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z6kernelPfS_S_S_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10887:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_S_S_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10887:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 998244352
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1065353216
.align 4
.LC12:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPfS_S_S_S_S_iii # -- Begin function _Z21__device_stub__kernelPfS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_S_S_S_S_iii,@function
_Z21__device_stub__kernelPfS_S_S_S_S_iii: # @_Z21__device_stub__kernelPfS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPfS_S_S_S_S_iii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_S_S_S_S_iii, .Lfunc_end0-_Z21__device_stub__kernelPfS_S_S_S_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 112(%rsp) # 8-byte Spill
movq %rbx, 120(%rsp) # 8-byte Spill
movq 8(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %rbp
leaq 8(%rsp), %rdx
leaq 4(%rsp), %rcx
movl $.L.str.1, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq 8(%rsp), %rax
movslq 4(%rsp), %r14
imulq %rax, %r14
cvtsi2ss %r14d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %r14, %rbx
shlq $2, %rbx
testl %r14d, %r14d
movq $-1, %r15
cmovnsq %rbx, %r15
movq %r15, %rdi
callq _Znam
movq %rax, %r13
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %r15, %rdi
callq _Znam
movq %rax, %r15
leaq 56(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r13, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbp, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 4(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %rbx
cmpq %rcx, %r12
jl .LBB1_2
.LBB1_3: # %.preheader70
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph73.preheader
movq %r14, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph73
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbp, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 4(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %rbx
cmpq %rcx, %r12
jl .LBB1_5
.LBB1_6: # %.preheader69
cvttss2si 12(%rsp), %eax # 4-byte Folded Reload
movl %eax, 12(%rsp) # 4-byte Spill
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_9
# %bb.7: # %.lr.ph75.preheader
movq %r15, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbp, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 4(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %rbx
cmpq %rcx, %r12
jl .LBB1_8
.LBB1_9: # %._crit_edge
movq %rbp, %rdi
callq fclose
movq 56(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 64(%rsp), %rdi
callq hipEventCreate
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 12(%rsp), %edi # 4-byte Reload
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
movq 16(%rsp), %r8
movl 4(%rsp), %r9d
movl 8(%rsp), %r10d
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq %rdx, 184(%rsp)
movq %rsi, 176(%rsp)
movq %rdi, 168(%rsp)
movq %r8, 160(%rsp)
movl %r9d, 84(%rsp)
movl %r10d, 80(%rsp)
movq 112(%rsp), %rax # 8-byte Reload
movl %eax, 76(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 176(%rsp), %rax
movq %rax, 232(%rsp)
leaq 168(%rsp), %rax
movq %rax, 240(%rsp)
leaq 160(%rsp), %rax
movq %rax, 248(%rsp)
leaq 84(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rax
movq %rax, 264(%rsp)
leaq 76(%rsp), %rax
movq %rax, 272(%rsp)
leaq 88(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z6kernelPfS_S_S_S_S_iii, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rdi
callq hipEventSynchronize
movq 104(%rsp), %rsi
movq 64(%rsp), %rdx
leaq 208(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 208(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.4, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 88(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .LBB1_13
# %bb.12:
leaq 88(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 32(%rsp), %rsi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movslq 4(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 120(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rdi
movl $.L.str.5, %esi
callq fopen
movq %rax, %r12
movl 8(%rsp), %edx
movl 4(%rsp), %ecx
movl $.L.str.6, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_19
# %bb.15: # %.lr.ph77.preheader
xorl %ebx, %ebx
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_18: # %.lr.ph77
# in Loop: Header=BB1_16 Depth=1
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbx
movslq 4(%rsp), %rcx
movslq 8(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %rbx
jge .LBB1_19
.LBB1_16: # %.lr.ph77
# =>This Inner Loop Header: Depth=1
decl %eax
movl $10, %edx
cmpq %rax, %rbx
je .LBB1_18
# %bb.17: # %.lr.ph77
# in Loop: Header=BB1_16 Depth=1
movl $32, %edx
jmp .LBB1_18
.LBB1_19: # %.preheader68
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_24
# %bb.20: # %.lr.ph79.preheader
xorl %ebx, %ebx
jmp .LBB1_21
.p2align 4, 0x90
.LBB1_23: # %.lr.ph79
# in Loop: Header=BB1_21 Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbx
movslq 4(%rsp), %rcx
movslq 8(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %rbx
jge .LBB1_24
.LBB1_21: # %.lr.ph79
# =>This Inner Loop Header: Depth=1
decl %eax
movl $10, %edx
cmpq %rax, %rbx
je .LBB1_23
# %bb.22: # %.lr.ph79
# in Loop: Header=BB1_21 Depth=1
movl $32, %edx
jmp .LBB1_23
.LBB1_24: # %.preheader
movl 8(%rsp), %eax
imull 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_29
# %bb.25: # %.lr.ph81.preheader
xorl %ebx, %ebx
jmp .LBB1_26
.p2align 4, 0x90
.LBB1_28: # %.lr.ph81
# in Loop: Header=BB1_26 Depth=1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbx
movslq 4(%rsp), %rcx
movslq 8(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %rbx
jge .LBB1_29
.LBB1_26: # %.lr.ph81
# =>This Inner Loop Header: Depth=1
decl %eax
movl $10, %edx
cmpq %rax, %rbx
je .LBB1_28
# %bb.27: # %.lr.ph81
# in Loop: Header=BB1_26 Depth=1
movl $32, %edx
jmp .LBB1_28
.LBB1_29: # %._crit_edge82
movq %r12, %rdi
callq fclose
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_S_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_S_S_S_S_iii,@object # @_Z6kernelPfS_S_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_S_S_S_S_iii
.p2align 3, 0x0
_Z6kernelPfS_S_S_S_S_iii:
.quad _Z21__device_stub__kernelPfS_S_S_S_S_iii
.size _Z6kernelPfS_S_S_S_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Tiempo: "
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[ms]"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d %d\n"
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%f%c"
.size .L.str.7, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfS_S_S_S_S_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_S_S_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_S_S_S_S_iii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
// Simple implementation of Mandelbrot set from Wikipedia
// http://en.wikipedia.org/wiki/Mandelbrot_set
// Note that this kernel is meant to be a simple, straight-forward
// implementation, and so may not represent optimized GPU code.
extern "C"
__device__
void mandelbrot(float* Data) {
// Which pixel am I?
unsigned DataX = blockIdx.x * blockDim.x + threadIdx.x;
unsigned DataY = blockIdx.y * blockDim.y + threadIdx.y;
unsigned Width = gridDim.x * blockDim.x;
unsigned Height = gridDim.y * blockDim.y;
float R, G, B, A;
// Scale coordinates to (-2.5, 1) and (-1, 1)
float NormX = (float)DataX / (float)Width;
NormX *= 3.5f;
NormX -= 2.5f;
float NormY = (float)DataY / (float)Height;
NormY *= 2.0f;
NormY -= 1.0f;
float X0 = NormX;
float Y0 = NormY;
float X = 0.0f;
float Y = 0.0f;
unsigned Iter = 0;
unsigned MaxIter = 1000;
// Iterate
while(X*X + Y*Y < 4.0f && Iter < MaxIter) {
float XTemp = X*X - Y*Y + X0;
Y = 2.0f*X*Y + Y0;
X = XTemp;
Iter++;
}
unsigned ColorG = Iter % 50;
unsigned ColorB = Iter % 25;
R = 0.0f;
G = (float)ColorG / 50.0f;
B = (float)ColorB / 25.0f;
A = 1.0f;
Data[DataY*Width*4+DataX*4+0] = R;
Data[DataY*Width*4+DataX*4+1] = G;
Data[DataY*Width*4+DataX*4+2] = B;
Data[DataY*Width*4+DataX*4+3] = A;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
// Simple implementation of Mandelbrot set from Wikipedia
// http://en.wikipedia.org/wiki/Mandelbrot_set
// Note that this kernel is meant to be a simple, straight-forward
// implementation, and so may not represent optimized GPU code.
extern "C"
__device__
void mandelbrot(float* Data) {
// Which pixel am I?
unsigned DataX = blockIdx.x * blockDim.x + threadIdx.x;
unsigned DataY = blockIdx.y * blockDim.y + threadIdx.y;
unsigned Width = gridDim.x * blockDim.x;
unsigned Height = gridDim.y * blockDim.y;
float R, G, B, A;
// Scale coordinates to (-2.5, 1) and (-1, 1)
float NormX = (float)DataX / (float)Width;
NormX *= 3.5f;
NormX -= 2.5f;
float NormY = (float)DataY / (float)Height;
NormY *= 2.0f;
NormY -= 1.0f;
float X0 = NormX;
float Y0 = NormY;
float X = 0.0f;
float Y = 0.0f;
unsigned Iter = 0;
unsigned MaxIter = 1000;
// Iterate
while(X*X + Y*Y < 4.0f && Iter < MaxIter) {
float XTemp = X*X - Y*Y + X0;
Y = 2.0f*X*Y + Y0;
X = XTemp;
Iter++;
}
unsigned ColorG = Iter % 50;
unsigned ColorB = Iter % 25;
R = 0.0f;
G = (float)ColorG / 50.0f;
B = (float)ColorB / 25.0f;
A = 1.0f;
Data[DataY*Width*4+DataX*4+0] = R;
Data[DataY*Width*4+DataX*4+1] = G;
Data[DataY*Width*4+DataX*4+2] = B;
Data[DataY*Width*4+DataX*4+3] = A;
} | .file "tmpxft_00137794_00000000-6_math-funcs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl mandelbrot
.type mandelbrot, @function
mandelbrot:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size mandelbrot, .-mandelbrot
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
// Simple implementation of Mandelbrot set from Wikipedia
// http://en.wikipedia.org/wiki/Mandelbrot_set
// Note that this kernel is meant to be a simple, straight-forward
// implementation, and so may not represent optimized GPU code.
extern "C"
__device__
void mandelbrot(float* Data) {
// Which pixel am I?
unsigned DataX = blockIdx.x * blockDim.x + threadIdx.x;
unsigned DataY = blockIdx.y * blockDim.y + threadIdx.y;
unsigned Width = gridDim.x * blockDim.x;
unsigned Height = gridDim.y * blockDim.y;
float R, G, B, A;
// Scale coordinates to (-2.5, 1) and (-1, 1)
float NormX = (float)DataX / (float)Width;
NormX *= 3.5f;
NormX -= 2.5f;
float NormY = (float)DataY / (float)Height;
NormY *= 2.0f;
NormY -= 1.0f;
float X0 = NormX;
float Y0 = NormY;
float X = 0.0f;
float Y = 0.0f;
unsigned Iter = 0;
unsigned MaxIter = 1000;
// Iterate
while(X*X + Y*Y < 4.0f && Iter < MaxIter) {
float XTemp = X*X - Y*Y + X0;
Y = 2.0f*X*Y + Y0;
X = XTemp;
Iter++;
}
unsigned ColorG = Iter % 50;
unsigned ColorB = Iter % 25;
R = 0.0f;
G = (float)ColorG / 50.0f;
B = (float)ColorB / 25.0f;
A = 1.0f;
Data[DataY*Width*4+DataX*4+0] = R;
Data[DataY*Width*4+DataX*4+1] = G;
Data[DataY*Width*4+DataX*4+2] = B;
Data[DataY*Width*4+DataX*4+3] = A;
} | #include <hip/hip_runtime.h>
/*
* Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
// Simple implementation of Mandelbrot set from Wikipedia
// http://en.wikipedia.org/wiki/Mandelbrot_set
// Note that this kernel is meant to be a simple, straight-forward
// implementation, and so may not represent optimized GPU code.
extern "C"
__device__
void mandelbrot(float* Data) {
// Which pixel am I?
unsigned DataX = blockIdx.x * blockDim.x + threadIdx.x;
unsigned DataY = blockIdx.y * blockDim.y + threadIdx.y;
unsigned Width = gridDim.x * blockDim.x;
unsigned Height = gridDim.y * blockDim.y;
float R, G, B, A;
// Scale coordinates to (-2.5, 1) and (-1, 1)
float NormX = (float)DataX / (float)Width;
NormX *= 3.5f;
NormX -= 2.5f;
float NormY = (float)DataY / (float)Height;
NormY *= 2.0f;
NormY -= 1.0f;
float X0 = NormX;
float Y0 = NormY;
float X = 0.0f;
float Y = 0.0f;
unsigned Iter = 0;
unsigned MaxIter = 1000;
// Iterate
while(X*X + Y*Y < 4.0f && Iter < MaxIter) {
float XTemp = X*X - Y*Y + X0;
Y = 2.0f*X*Y + Y0;
X = XTemp;
Iter++;
}
unsigned ColorG = Iter % 50;
unsigned ColorB = Iter % 25;
R = 0.0f;
G = (float)ColorG / 50.0f;
B = (float)ColorB / 25.0f;
A = 1.0f;
Data[DataY*Width*4+DataX*4+0] = R;
Data[DataY*Width*4+DataX*4+1] = G;
Data[DataY*Width*4+DataX*4+2] = B;
Data[DataY*Width*4+DataX*4+3] = A;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
// Simple implementation of Mandelbrot set from Wikipedia
// http://en.wikipedia.org/wiki/Mandelbrot_set
// Note that this kernel is meant to be a simple, straight-forward
// implementation, and so may not represent optimized GPU code.
extern "C"
__device__
void mandelbrot(float* Data) {
// Which pixel am I?
unsigned DataX = blockIdx.x * blockDim.x + threadIdx.x;
unsigned DataY = blockIdx.y * blockDim.y + threadIdx.y;
unsigned Width = gridDim.x * blockDim.x;
unsigned Height = gridDim.y * blockDim.y;
float R, G, B, A;
// Scale coordinates to (-2.5, 1) and (-1, 1)
float NormX = (float)DataX / (float)Width;
NormX *= 3.5f;
NormX -= 2.5f;
float NormY = (float)DataY / (float)Height;
NormY *= 2.0f;
NormY -= 1.0f;
float X0 = NormX;
float Y0 = NormY;
float X = 0.0f;
float Y = 0.0f;
unsigned Iter = 0;
unsigned MaxIter = 1000;
// Iterate
while(X*X + Y*Y < 4.0f && Iter < MaxIter) {
float XTemp = X*X - Y*Y + X0;
Y = 2.0f*X*Y + Y0;
X = XTemp;
Iter++;
}
unsigned ColorG = Iter % 50;
unsigned ColorB = Iter % 25;
R = 0.0f;
G = (float)ColorG / 50.0f;
B = (float)ColorB / 25.0f;
A = 1.0f;
Data[DataY*Width*4+DataX*4+0] = R;
Data[DataY*Width*4+DataX*4+1] = G;
Data[DataY*Width*4+DataX*4+2] = B;
Data[DataY*Width*4+DataX*4+3] = A;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
// Simple implementation of Mandelbrot set from Wikipedia
// http://en.wikipedia.org/wiki/Mandelbrot_set
// Note that this kernel is meant to be a simple, straight-forward
// implementation, and so may not represent optimized GPU code.
extern "C"
__device__
void mandelbrot(float* Data) {
// Which pixel am I?
unsigned DataX = blockIdx.x * blockDim.x + threadIdx.x;
unsigned DataY = blockIdx.y * blockDim.y + threadIdx.y;
unsigned Width = gridDim.x * blockDim.x;
unsigned Height = gridDim.y * blockDim.y;
float R, G, B, A;
// Scale coordinates to (-2.5, 1) and (-1, 1)
float NormX = (float)DataX / (float)Width;
NormX *= 3.5f;
NormX -= 2.5f;
float NormY = (float)DataY / (float)Height;
NormY *= 2.0f;
NormY -= 1.0f;
float X0 = NormX;
float Y0 = NormY;
float X = 0.0f;
float Y = 0.0f;
unsigned Iter = 0;
unsigned MaxIter = 1000;
// Iterate
while(X*X + Y*Y < 4.0f && Iter < MaxIter) {
float XTemp = X*X - Y*Y + X0;
Y = 2.0f*X*Y + Y0;
X = XTemp;
Iter++;
}
unsigned ColorG = Iter % 50;
unsigned ColorB = Iter % 25;
R = 0.0f;
G = (float)ColorG / 50.0f;
B = (float)ColorB / 25.0f;
A = 1.0f;
Data[DataY*Width*4+DataX*4+0] = R;
Data[DataY*Width*4+DataX*4+1] = G;
Data[DataY*Width*4+DataX*4+2] = B;
Data[DataY*Width*4+DataX*4+3] = A;
} | .text
.file "math-funcs.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00137794_00000000-6_math-funcs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl mandelbrot
.type mandelbrot, @function
mandelbrot:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size mandelbrot, .-mandelbrot
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "math-funcs.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void set_bookmarks(int2* vis_in, int npts, int blocksize, int blockgrid, int* bookmarks) {
for (int q=threadIdx.x+blockIdx.x*blockDim.x;q<=npts;q+=gridDim.x*blockDim.x) {
int2 this_vis = vis_in[q];
int2 last_vis = vis_in[q-1];
int main_x = this_vis.x/GCF_GRID/blocksize;
int main_x_last = last_vis.x/GCF_GRID/blocksize;
int main_y = this_vis.y/GCF_GRID/blocksize;
int main_y_last = last_vis.y/GCF_GRID/blocksize;
if (0==q) {
main_y_last=0;
main_x_last=-1;
}
if (npts==q) main_x = main_y = blockgrid;
if (main_x != main_x_last || main_y != main_y_last) {
for (int z=main_y_last*blockgrid+main_x_last+1;
z<=main_y*blockgrid+main_x; z++) {
bookmarks[z] = q;
}
}
}
} | code for sm_80
Function : _Z13set_bookmarksP4int2iiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fca00078e0209 */
/*0090*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x0000a8000c1e1b00 */
/*00a0*/ LDG.E.64 R2, [R8.64+-0x8] ; /* 0xfffff80408027981 */
/* 0x0000e2000c1e1b00 */
/*00b0*/ IABS R4, c[0x0][0x16c] ; /* 0x00005b0000047a13 */
/* 0x000fe20000000000 */
/*00c0*/ BSSY B0, 0xb50 ; /* 0x00000a8000007945 */
/* 0x000fe60003800000 */
/*00d0*/ I2F.RP R12, R4 ; /* 0x00000004000c7306 */
/* 0x000e700000209400 */
/*00e0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x002e640000001000 */
/*00f0*/ IADD3 R10, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c0a7810 */
/* 0x002fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000324000021f000 */
/*0110*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x002fe400078e00ff */
/*0120*/ IMAD.MOV R13, RZ, RZ, -R11 ; /* 0x000000ffff0d7224 */
/* 0x010fc800078e0a0b */
/*0130*/ IMAD R13, R13, R4, RZ ; /* 0x000000040d0d7224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R8, R11, R13, R10 ; /* 0x0000000d0b087227 */
/* 0x001fe200078e000a */
/*0150*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x004fe40000011406 */
/*0160*/ SHF.R.S32.HI R14, RZ, 0x1f, R7 ; /* 0x0000001fff0e7819 */
/* 0x000fe40000011407 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R2 ; /* 0x0000001fff097819 */
/* 0x008fe40000011402 */
/*0180*/ LEA.HI R5, R5, R6, RZ, 0x3 ; /* 0x0000000605057211 */
/* 0x000fe400078f18ff */
/*0190*/ LEA.HI R14, R14, R7, RZ, 0x3 ; /* 0x000000070e0e7211 */
/* 0x000fe400078f18ff */
/*01a0*/ LEA.HI R6, R9, R2, RZ, 0x3 ; /* 0x0000000209067211 */
/* 0x000fc400078f18ff */
/*01b0*/ SHF.R.S32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fe40000011405 */
/*01c0*/ SHF.R.S32.HI R9, RZ, 0x3, R14 ; /* 0x00000003ff097819 */
/* 0x000fe4000001140e */
/*01d0*/ SHF.R.S32.HI R12, RZ, 0x1f, R3 ; /* 0x0000001fff0c7819 */
/* 0x000fe40000011403 */
/*01e0*/ IABS R11, R5 ; /* 0x00000005000b7213 */
/* 0x000fe40000000000 */
/*01f0*/ IABS R15, R9 ; /* 0x00000009000f7213 */
/* 0x000fe40000000000 */
/*0200*/ LEA.HI R7, R12, R3, RZ, 0x3 ; /* 0x000000030c077211 */
/* 0x000fe200078f18ff */
/*0210*/ IMAD.HI.U32 R3, R8, R11, RZ ; /* 0x0000000b08037227 */
/* 0x000fe200078e00ff */
/*0220*/ SHF.R.S32.HI R6, RZ, 0x3, R6 ; /* 0x00000003ff067819 */
/* 0x000fc40000011406 */
/*0230*/ SHF.R.S32.HI R7, RZ, 0x3, R7 ; /* 0x00000003ff077819 */
/* 0x000fe20000011407 */
/*0240*/ IMAD.HI.U32 R10, R8.reuse, R15, RZ ; /* 0x0000000f080a7227 */
/* 0x040fe200078e00ff */
/*0250*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*0260*/ IABS R17, R7 ; /* 0x0000000700117213 */
/* 0x000fe20000000000 */
/*0270*/ IMAD.MOV R12, RZ, RZ, -R3 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a03 */
/*0280*/ LOP3.LUT R5, R5, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0005057a12 */
/* 0x000fe200078e3cff */
/*0290*/ IMAD.MOV R14, RZ, RZ, -R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0a */
/*02a0*/ LOP3.LUT R9, R9, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0009097a12 */
/* 0x000fe200078e3cff */
/*02b0*/ IMAD.HI.U32 R2, R8, R13, RZ ; /* 0x0000000d08027227 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R6, R6, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0006067a12 */
/* 0x000fc400078e3cff */
/*02d0*/ LOP3.LUT R7, R7, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0007077a12 */
/* 0x000fe200078e3cff */
/*02e0*/ IMAD R11, R4.reuse, R12, R11 ; /* 0x0000000c040b7224 */
/* 0x040fe200078e020b */
/*02f0*/ ISETP.GE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f26270 */
/*0300*/ IMAD R15, R4, R14, R15 ; /* 0x0000000e040f7224 */
/* 0x000fe400078e020f */
/*0310*/ IMAD.HI.U32 R8, R8, R17, RZ ; /* 0x0000001108087227 */
/* 0x000fe200078e00ff */
/*0320*/ ISETP.GT.U32.AND P3, PT, R4.reuse, R11, PT ; /* 0x0000000b0400720c */
/* 0x040fe40003f64070 */
/*0330*/ ISETP.GT.U32.AND P5, PT, R4, R15, PT ; /* 0x0000000f0400720c */
/* 0x000fe20003fa4070 */
/*0340*/ IMAD.MOV R12, RZ, RZ, -R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0a02 */
/*0350*/ IMAD.MOV R16, RZ, RZ, -R8 ; /* 0x000000ffff107224 */
/* 0x000fc400078e0a08 */
/*0360*/ IMAD R13, R4.reuse, R12, R13 ; /* 0x0000000c040d7224 */
/* 0x040fe400078e020d */
/*0370*/ IMAD R17, R4, R16, R17 ; /* 0x0000001004117224 */
/* 0x000fc600078e0211 */
/*0380*/ ISETP.GT.U32.AND P4, PT, R4.reuse, R13, PT ; /* 0x0000000d0400720c */
/* 0x040fe20003f84070 */
/*0390*/ @!P3 IMAD.IADD R11, R11, 0x1, -R4.reuse ; /* 0x000000010b0bb824 */
/* 0x100fe200078e0a04 */
/*03a0*/ ISETP.GT.U32.AND P0, PT, R4, R17, PT ; /* 0x000000110400720c */
/* 0x000fe20003f04070 */
/*03b0*/ @!P5 IMAD.IADD R15, R15, 0x1, -R4 ; /* 0x000000010f0fd824 */
/* 0x000fe200078e0a04 */
/*03c0*/ @!P3 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303b810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ ISETP.GE.U32.AND P6, PT, R11, R4.reuse, PT ; /* 0x000000040b00720c */
/* 0x080fe40003fc6070 */
/*03e0*/ ISETP.GE.U32.AND P2, PT, R15, R4, PT ; /* 0x000000040f00720c */
/* 0x000fe40003f46070 */
/*03f0*/ @!P5 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0ad810 */
/* 0x000fc40007ffe0ff */
/*0400*/ ISETP.GE.AND P5, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003fa6270 */
/*0410*/ @!P4 IMAD.IADD R13, R13, 0x1, -R4.reuse ; /* 0x000000010d0dc824 */
/* 0x100fe200078e0a04 */
/*0420*/ @!P4 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202c810 */
/* 0x000fe20007ffe0ff */
/*0430*/ @!P0 IMAD.IADD R17, R17, 0x1, -R4 ; /* 0x0000000111118824 */
/* 0x000fe200078e0a04 */
/*0440*/ @!P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108088810 */
/* 0x000fe40007ffe0ff */
/*0450*/ ISETP.GE.U32.AND P3, PT, R13, R4.reuse, PT ; /* 0x000000040d00720c */
/* 0x080fe40003f66070 */
/*0460*/ ISETP.GE.U32.AND P4, PT, R17, R4, PT ; /* 0x000000041100720c */
/* 0x000fe40003f86070 */
/*0470*/ @P6 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103036810 */
/* 0x000fc40007ffe0ff */
/*0480*/ @P2 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a2810 */
/* 0x000fe40007ffe0ff */
/*0490*/ ISETP.GE.AND P6, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003fc6270 */
/*04a0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*04b0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f46270 */
/*04c0*/ @!P5 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0ad224 */
/* 0x000fe200078e0a0a */
/*04d0*/ LOP3.LUT R4, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff047a12 */
/* 0x000fe400078e33ff */
/*04e0*/ @P3 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102023810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ @P4 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108084810 */
/* 0x000fc40007ffe0ff */
/*0500*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe40003f65270 */
/*0510*/ ISETP.NE.AND P0, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f05270 */
/*0520*/ @!P6 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02e224 */
/* 0x000fe200078e0a02 */
/*0530*/ ISETP.NE.AND P4, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f85270 */
/*0540*/ @!P2 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0a08 */
/*0550*/ SEL R3, R4.reuse, R3, !P3 ; /* 0x0000000304037207 */
/* 0x040fe40005800000 */
/*0560*/ SEL R10, R4.reuse, R10, !P3 ; /* 0x0000000a040a7207 */
/* 0x040fe40005800000 */
/*0570*/ SEL R8, R4, R8, !P3 ; /* 0x0000000804087207 */
/* 0x000fc40005800000 */
/*0580*/ SEL R2, R4, R2, !P3 ; /* 0x0000000204027207 */
/* 0x000fe40005800000 */
/*0590*/ SEL R3, R3, c[0x0][0x170], P4 ; /* 0x00005c0003037a07 */
/* 0x000fe40002000000 */
/*05a0*/ SEL R7, R10, c[0x0][0x170], P4 ; /* 0x00005c000a077a07 */
/* 0x000fe40002000000 */
/*05b0*/ SEL R8, R8, RZ, P0 ; /* 0x000000ff08087207 */
/* 0x000fe40000000000 */
/*05c0*/ SEL R5, R2, 0xffffffff, P0 ; /* 0xffffffff02057807 */
/* 0x000fe40000000000 */
/*05d0*/ ISETP.NE.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fc40003f05270 */
/*05e0*/ ISETP.EQ.AND P1, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fda0003f22270 */
/*05f0*/ @!P0 BRA P1, 0xb40 ; /* 0x0000054000008947 */
/* 0x000fea0000800000 */
/*0600*/ IMAD R6, R8, c[0x0][0x170], R5 ; /* 0x00005c0008067a24 */
/* 0x000fe400078e0205 */
/*0610*/ IMAD R9, R7, c[0x0][0x170], R3 ; /* 0x00005c0007097a24 */
/* 0x000fca00078e0203 */
/*0620*/ ISETP.GE.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f06270 */
/*0630*/ @P0 BRA 0xb40 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.IADD R2, R7, 0x1, -R8 ; /* 0x0000000107027824 */
/* 0x000fe200078e0a08 */
/*0650*/ BSSY B1, 0x790 ; /* 0x0000013000017945 */
/* 0x000fe20003800000 */
/*0660*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0670*/ IMAD R2, R2, c[0x0][0x170], R3 ; /* 0x00005c0002027a24 */
/* 0x000fc800078e0203 */
/*0680*/ IMAD.IADD R3, R2, 0x1, -R5 ; /* 0x0000000102037824 */
/* 0x000fe200078e0a05 */
/*0690*/ IADD3 R2, -R5, -0x1, R2 ; /* 0xffffffff05027810 */
/* 0x000fc80007ffe102 */
/*06a0*/ LOP3.LUT P0, R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fe4000780c0ff */
/*06b0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fd60003f26070 */
/*06c0*/ @!P0 BRA 0x780 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*06d0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*06f0*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fc60003f05270 */
/*0700*/ IMAD.WIDE R2, R4, R3, c[0x0][0x178] ; /* 0x00005e0004027625 */
/* 0x000fca00078e0203 */
/*0710*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001ea000c101904 */
/*0720*/ @!P0 BRA 0x780 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.NE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe20003f05270 */
/*0740*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x0003e2000c101904 */
/*0750*/ IADD3 R4, R6, 0x2, RZ ; /* 0x0000000206047810 */
/* 0x000fd60007ffe0ff */
/*0760*/ @P0 STG.E [R2.64+0x8], R0 ; /* 0x0000080002000986 */
/* 0x0003e2000c101904 */
/*0770*/ @P0 IADD3 R4, R6, 0x3, RZ ; /* 0x0000000306040810 */
/* 0x000fc60007ffe0ff */
/*0780*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0790*/ @!P1 BRA 0xb40 ; /* 0x000003a000009947 */
/* 0x000fea0003800000 */
/*07a0*/ IMAD.IADD R2, R9, 0x1, -R4 ; /* 0x0000000109027824 */
/* 0x003fe200078e0a04 */
/*07b0*/ BSSY B1, 0x9c0 ; /* 0x0000020000017945 */
/* 0x000fe20003800000 */
/*07c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*07e0*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe40003f24270 */
/*07f0*/ IADD3 R2, R4, 0x1, RZ ; /* 0x0000000104027810 */
/* 0x000fca0007ffe0ff */
/*0800*/ IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fcc00078e0203 */
/*0810*/ @!P1 BRA 0x9b0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0820*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0830*/ IADD3 R7, R9, -0xc, RZ ; /* 0xfffffff409077810 */
/* 0x000fe40007ffe0ff */
/*0840*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007ffe0ff */
/*0850*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*0860*/ IADD3 R5, P2, R2, 0x40, RZ ; /* 0x0000004002057810 */
/* 0x000fe40007f5e0ff */
/*0870*/ ISETP.GE.AND P1, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe20003f26270 */
/*0880*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe4000c101904 */
/*0890*/ IMAD.X R6, RZ, RZ, R3, P2 ; /* 0x000000ffff067224 */
/* 0x000fe400010e0603 */
/*08a0*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*08b0*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*08c0*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*08d0*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x000fe8000c101904 */
/*08e0*/ STG.E [R2.64+0x18], R0 ; /* 0x0000180002007986 */
/* 0x000fe8000c101904 */
/*08f0*/ STG.E [R2.64+0x1c], R0 ; /* 0x00001c0002007986 */
/* 0x000fe8000c101904 */
/*0900*/ STG.E [R2.64+0x20], R0 ; /* 0x0000200002007986 */
/* 0x000fe8000c101904 */
/*0910*/ STG.E [R2.64+0x24], R0 ; /* 0x0000240002007986 */
/* 0x000fe8000c101904 */
/*0920*/ STG.E [R2.64+0x28], R0 ; /* 0x0000280002007986 */
/* 0x000fe8000c101904 */
/*0930*/ STG.E [R2.64+0x2c], R0 ; /* 0x00002c0002007986 */
/* 0x000fe8000c101904 */
/*0940*/ STG.E [R2.64+0x30], R0 ; /* 0x0000300002007986 */
/* 0x000fe8000c101904 */
/*0950*/ STG.E [R2.64+0x34], R0 ; /* 0x0000340002007986 */
/* 0x000fe8000c101904 */
/*0960*/ STG.E [R2.64+0x38], R0 ; /* 0x0000380002007986 */
/* 0x000fe8000c101904 */
/*0970*/ STG.E [R2.64+0x3c], R0 ; /* 0x00003c0002007986 */
/* 0x0001e4000c101904 */
/*0980*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0990*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*09a0*/ @!P1 BRA 0x840 ; /* 0xfffffe9000009947 */
/* 0x000fea000383ffff */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ IMAD.IADD R5, R9, 0x1, -R4 ; /* 0x0000000109057824 */
/* 0x000fe200078e0a04 */
/*09d0*/ BSSY B1, 0xaf0 ; /* 0x0000011000017945 */
/* 0x000fe80003800000 */
/*09e0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*09f0*/ @!P1 BRA 0xae0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0a00*/ IADD3 R5, P1, R2, 0x20, RZ ; /* 0x0000002002057810 */
/* 0x000fe20007f3e0ff */
/*0a10*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a30*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.X R6, RZ, RZ, R3, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0603 */
/*0a50*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0a60*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*0a70*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*0a80*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*0a90*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x000fe8000c101904 */
/*0aa0*/ STG.E [R2.64+0x18], R0 ; /* 0x0000180002007986 */
/* 0x000fe8000c101904 */
/*0ab0*/ STG.E [R2.64+0x1c], R0 ; /* 0x00001c0002007986 */
/* 0x0001e4000c101904 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0ad0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*0ae0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0af0*/ ISETP.LT.OR P0, PT, R4, R9, P0 ; /* 0x000000090400720c */
/* 0x000fda0000701670 */
/*0b00*/ @P0 STG.E [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e8000c101904 */
/*0b10*/ @P0 STG.E [R2.64+0x4], R0 ; /* 0x0000040002000986 */
/* 0x0001e8000c101904 */
/*0b20*/ @P0 STG.E [R2.64+0x8], R0 ; /* 0x0000080002000986 */
/* 0x0001e8000c101904 */
/*0b30*/ @P0 STG.E [R2.64+0xc], R0 ; /* 0x00000c0002000986 */
/* 0x0001e4000c101904 */
/*0b40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b50*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff037624 */
/* 0x003fc800078e00ff */
/*0b60*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x000fca00078e0200 */
/*0b70*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04270 */
/*0b80*/ @!P0 BRA 0x70 ; /* 0xfffff4e000008947 */
/* 0x000fea000383ffff */
/*0b90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void set_bookmarks(int2* vis_in, int npts, int blocksize, int blockgrid, int* bookmarks) {
for (int q=threadIdx.x+blockIdx.x*blockDim.x;q<=npts;q+=gridDim.x*blockDim.x) {
int2 this_vis = vis_in[q];
int2 last_vis = vis_in[q-1];
int main_x = this_vis.x/GCF_GRID/blocksize;
int main_x_last = last_vis.x/GCF_GRID/blocksize;
int main_y = this_vis.y/GCF_GRID/blocksize;
int main_y_last = last_vis.y/GCF_GRID/blocksize;
if (0==q) {
main_y_last=0;
main_x_last=-1;
}
if (npts==q) main_x = main_y = blockgrid;
if (main_x != main_x_last || main_y != main_y_last) {
for (int z=main_y_last*blockgrid+main_x_last+1;
z<=main_y*blockgrid+main_x; z++) {
bookmarks[z] = q;
}
}
}
} | .file "tmpxft_00186931_00000000-6_set_bookmarks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi
.type _Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi, @function
_Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13set_bookmarksP4int2iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi, .-_Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi
.globl _Z13set_bookmarksP4int2iiiPi
.type _Z13set_bookmarksP4int2iiiPi, @function
_Z13set_bookmarksP4int2iiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13set_bookmarksP4int2iiiPi, .-_Z13set_bookmarksP4int2iiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13set_bookmarksP4int2iiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13set_bookmarksP4int2iiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void set_bookmarks(int2* vis_in, int npts, int blocksize, int blockgrid, int* bookmarks) {
for (int q=threadIdx.x+blockIdx.x*blockDim.x;q<=npts;q+=gridDim.x*blockDim.x) {
int2 this_vis = vis_in[q];
int2 last_vis = vis_in[q-1];
int main_x = this_vis.x/GCF_GRID/blocksize;
int main_x_last = last_vis.x/GCF_GRID/blocksize;
int main_y = this_vis.y/GCF_GRID/blocksize;
int main_y_last = last_vis.y/GCF_GRID/blocksize;
if (0==q) {
main_y_last=0;
main_x_last=-1;
}
if (npts==q) main_x = main_y = blockgrid;
if (main_x != main_x_last || main_y != main_y_last) {
for (int z=main_y_last*blockgrid+main_x_last+1;
z<=main_y*blockgrid+main_x; z++) {
bookmarks[z] = q;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_bookmarks(int2* vis_in, int npts, int blocksize, int blockgrid, int* bookmarks) {
for (int q=threadIdx.x+blockIdx.x*blockDim.x;q<=npts;q+=gridDim.x*blockDim.x) {
int2 this_vis = vis_in[q];
int2 last_vis = vis_in[q-1];
int main_x = this_vis.x/GCF_GRID/blocksize;
int main_x_last = last_vis.x/GCF_GRID/blocksize;
int main_y = this_vis.y/GCF_GRID/blocksize;
int main_y_last = last_vis.y/GCF_GRID/blocksize;
if (0==q) {
main_y_last=0;
main_x_last=-1;
}
if (npts==q) main_x = main_y = blockgrid;
if (main_x != main_x_last || main_y != main_y_last) {
for (int z=main_y_last*blockgrid+main_x_last+1;
z<=main_y*blockgrid+main_x; z++) {
bookmarks[z] = q;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_bookmarks(int2* vis_in, int npts, int blocksize, int blockgrid, int* bookmarks) {
for (int q=threadIdx.x+blockIdx.x*blockDim.x;q<=npts;q+=gridDim.x*blockDim.x) {
int2 this_vis = vis_in[q];
int2 last_vis = vis_in[q-1];
int main_x = this_vis.x/GCF_GRID/blocksize;
int main_x_last = last_vis.x/GCF_GRID/blocksize;
int main_y = this_vis.y/GCF_GRID/blocksize;
int main_y_last = last_vis.y/GCF_GRID/blocksize;
if (0==q) {
main_y_last=0;
main_x_last=-1;
}
if (npts==q) main_x = main_y = blockgrid;
if (main_x != main_x_last || main_y != main_y_last) {
for (int z=main_y_last*blockgrid+main_x_last+1;
z<=main_y*blockgrid+main_x; z++) {
bookmarks[z] = q;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.globl _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.p2align 8
.type _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi,@function
_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x8
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s6, v1
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0xc
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s7, s8, 4
s_addc_u32 s8, s9, 0
s_ashr_i32 s9, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s9
s_xor_b32 s10, s2, s9
s_load_b32 s2, s[4:5], 0x0
v_cvt_f32_u32_e32 v0, s10
s_sub_i32 s4, 0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s2, s11
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v0
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, v0, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s6, v1
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b64 v[4:5], v[2:3], off
global_load_b64 v[2:3], v[2:3], off offset:-8
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v0, 31, v4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v2
v_ashrrev_i32_e32 v8, 31, v5
v_ashrrev_i32_e32 v9, 31, v3
v_lshrrev_b32_e32 v0, 29, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshrrev_b32_e32 v6, 29, v6
v_lshrrev_b32_e32 v8, 29, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshrrev_b32_e32 v9, 29, v9
v_add_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, v2, v6
v_add_nc_u32_e32 v4, v5, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 3, v0
v_ashrrev_i32_e32 v0, 31, v0
v_ashrrev_i32_e32 v6, 3, v2
v_ashrrev_i32_e32 v2, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v5, v0
v_add_nc_u32_e32 v6, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v5, v5, v0
v_xor_b32_e32 v0, s9, v0
v_xor_b32_e32 v6, v6, v2
v_xor_b32_e32 v2, s9, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v10, v5, v7
v_mul_hi_u32 v11, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v14, v10, s10
v_add_nc_u32_e32 v18, 1, v10
v_mul_lo_u32 v15, v11, s10
v_add_nc_u32_e32 v19, 1, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v5, v5, v14
v_sub_nc_u32_e32 v6, v6, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s10, v5
v_add_nc_u32_e32 v3, v3, v9
v_cmp_le_u32_e64 s0, s10, v6
v_subrev_nc_u32_e32 v15, s10, v5
v_cndmask_b32_e32 v10, v10, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 3, v3
v_ashrrev_i32_e32 v3, 31, v3
v_cndmask_b32_e64 v11, v11, v19, s0
v_cndmask_b32_e32 v5, v5, v15, vcc_lo
v_add_nc_u32_e32 v15, 1, v10
v_add_nc_u32_e32 v9, v9, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s10, v5
v_xor_b32_e32 v9, v9, v3
v_xor_b32_e32 v3, s9, v3
v_cndmask_b32_e32 v5, v10, v15, vcc_lo
v_ashrrev_i32_e32 v8, 3, v4
v_ashrrev_i32_e32 v4, 31, v4
v_mul_hi_u32 v13, v9, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v0
v_sub_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v13, s10
v_add_nc_u32_e32 v14, 1, v13
v_sub_nc_u32_e32 v9, v9, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s10, v9
v_cndmask_b32_e64 v13, v13, v14, s2
v_subrev_nc_u32_e32 v14, s10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v14, s2
v_add_nc_u32_e32 v14, 1, v13
v_add_nc_u32_e32 v8, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v4
v_xor_b32_e32 v4, s9, v4
v_mul_hi_u32 v12, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v16, v12, s10
v_add_nc_u32_e32 v20, 1, v12
v_sub_nc_u32_e32 v8, v8, v16
v_subrev_nc_u32_e32 v16, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e64 s1, s10, v8
v_cndmask_b32_e64 v6, v6, v16, s0
v_subrev_nc_u32_e32 v17, s10, v8
v_add_nc_u32_e32 v16, 1, v11
v_cmp_eq_u32_e64 s0, s6, v1
v_cndmask_b32_e64 v12, v12, v20, s1
v_cmp_le_u32_e32 vcc_lo, s10, v6
v_cndmask_b32_e64 v8, v8, v17, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v0, v0, s3, s0
v_add_nc_u32_e32 v17, 1, v12
v_cndmask_b32_e32 v6, v11, v16, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v6, v2
v_cndmask_b32_e32 v9, v13, v14, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v8
v_sub_nc_u32_e32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v3
v_cndmask_b32_e32 v8, v12, v17, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_sub_nc_u32_e32 v3, v9, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v4
v_cndmask_b32_e64 v5, v3, 0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v8, v4
v_cndmask_b32_e64 v4, v2, -1, vcc_lo
v_cndmask_b32_e64 v6, v6, s3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, v0, v4
v_cmp_ne_u32_e64 s0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v5, s3, v[4:5]
v_mad_u64_u32 v[4:5], null, v6, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v2, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_co_u32 v5, vcc_lo, s7, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s8, v6, vcc_lo
.LBB0_6:
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[5:6], v1, off
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
v_cmp_ge_i32_e32 vcc_lo, v2, v4
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_6
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, .Lfunc_end0-_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_bookmarks(int2* vis_in, int npts, int blocksize, int blockgrid, int* bookmarks) {
for (int q=threadIdx.x+blockIdx.x*blockDim.x;q<=npts;q+=gridDim.x*blockDim.x) {
int2 this_vis = vis_in[q];
int2 last_vis = vis_in[q-1];
int main_x = this_vis.x/GCF_GRID/blocksize;
int main_x_last = last_vis.x/GCF_GRID/blocksize;
int main_y = this_vis.y/GCF_GRID/blocksize;
int main_y_last = last_vis.y/GCF_GRID/blocksize;
if (0==q) {
main_y_last=0;
main_x_last=-1;
}
if (npts==q) main_x = main_y = blockgrid;
if (main_x != main_x_last || main_y != main_y_last) {
for (int z=main_y_last*blockgrid+main_x_last+1;
z<=main_y*blockgrid+main_x; z++) {
bookmarks[z] = q;
}
}
}
} | .text
.file "set_bookmarks.hip"
.globl _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi # -- Begin function _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.p2align 4, 0x90
.type _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi,@function
_Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi: # @_Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, .Lfunc_end0-_Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi,@object # @_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.section .rodata,"a",@progbits
.globl _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.p2align 3, 0x0
_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi:
.quad _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.size _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13set_bookmarksP4int2iiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fca00078e0209 */
/*0090*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x0000a8000c1e1b00 */
/*00a0*/ LDG.E.64 R2, [R8.64+-0x8] ; /* 0xfffff80408027981 */
/* 0x0000e2000c1e1b00 */
/*00b0*/ IABS R4, c[0x0][0x16c] ; /* 0x00005b0000047a13 */
/* 0x000fe20000000000 */
/*00c0*/ BSSY B0, 0xb50 ; /* 0x00000a8000007945 */
/* 0x000fe60003800000 */
/*00d0*/ I2F.RP R12, R4 ; /* 0x00000004000c7306 */
/* 0x000e700000209400 */
/*00e0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x002e640000001000 */
/*00f0*/ IADD3 R10, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c0a7810 */
/* 0x002fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000324000021f000 */
/*0110*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x002fe400078e00ff */
/*0120*/ IMAD.MOV R13, RZ, RZ, -R11 ; /* 0x000000ffff0d7224 */
/* 0x010fc800078e0a0b */
/*0130*/ IMAD R13, R13, R4, RZ ; /* 0x000000040d0d7224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R8, R11, R13, R10 ; /* 0x0000000d0b087227 */
/* 0x001fe200078e000a */
/*0150*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x004fe40000011406 */
/*0160*/ SHF.R.S32.HI R14, RZ, 0x1f, R7 ; /* 0x0000001fff0e7819 */
/* 0x000fe40000011407 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R2 ; /* 0x0000001fff097819 */
/* 0x008fe40000011402 */
/*0180*/ LEA.HI R5, R5, R6, RZ, 0x3 ; /* 0x0000000605057211 */
/* 0x000fe400078f18ff */
/*0190*/ LEA.HI R14, R14, R7, RZ, 0x3 ; /* 0x000000070e0e7211 */
/* 0x000fe400078f18ff */
/*01a0*/ LEA.HI R6, R9, R2, RZ, 0x3 ; /* 0x0000000209067211 */
/* 0x000fc400078f18ff */
/*01b0*/ SHF.R.S32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fe40000011405 */
/*01c0*/ SHF.R.S32.HI R9, RZ, 0x3, R14 ; /* 0x00000003ff097819 */
/* 0x000fe4000001140e */
/*01d0*/ SHF.R.S32.HI R12, RZ, 0x1f, R3 ; /* 0x0000001fff0c7819 */
/* 0x000fe40000011403 */
/*01e0*/ IABS R11, R5 ; /* 0x00000005000b7213 */
/* 0x000fe40000000000 */
/*01f0*/ IABS R15, R9 ; /* 0x00000009000f7213 */
/* 0x000fe40000000000 */
/*0200*/ LEA.HI R7, R12, R3, RZ, 0x3 ; /* 0x000000030c077211 */
/* 0x000fe200078f18ff */
/*0210*/ IMAD.HI.U32 R3, R8, R11, RZ ; /* 0x0000000b08037227 */
/* 0x000fe200078e00ff */
/*0220*/ SHF.R.S32.HI R6, RZ, 0x3, R6 ; /* 0x00000003ff067819 */
/* 0x000fc40000011406 */
/*0230*/ SHF.R.S32.HI R7, RZ, 0x3, R7 ; /* 0x00000003ff077819 */
/* 0x000fe20000011407 */
/*0240*/ IMAD.HI.U32 R10, R8.reuse, R15, RZ ; /* 0x0000000f080a7227 */
/* 0x040fe200078e00ff */
/*0250*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*0260*/ IABS R17, R7 ; /* 0x0000000700117213 */
/* 0x000fe20000000000 */
/*0270*/ IMAD.MOV R12, RZ, RZ, -R3 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a03 */
/*0280*/ LOP3.LUT R5, R5, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0005057a12 */
/* 0x000fe200078e3cff */
/*0290*/ IMAD.MOV R14, RZ, RZ, -R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0a */
/*02a0*/ LOP3.LUT R9, R9, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0009097a12 */
/* 0x000fe200078e3cff */
/*02b0*/ IMAD.HI.U32 R2, R8, R13, RZ ; /* 0x0000000d08027227 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R6, R6, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0006067a12 */
/* 0x000fc400078e3cff */
/*02d0*/ LOP3.LUT R7, R7, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0007077a12 */
/* 0x000fe200078e3cff */
/*02e0*/ IMAD R11, R4.reuse, R12, R11 ; /* 0x0000000c040b7224 */
/* 0x040fe200078e020b */
/*02f0*/ ISETP.GE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f26270 */
/*0300*/ IMAD R15, R4, R14, R15 ; /* 0x0000000e040f7224 */
/* 0x000fe400078e020f */
/*0310*/ IMAD.HI.U32 R8, R8, R17, RZ ; /* 0x0000001108087227 */
/* 0x000fe200078e00ff */
/*0320*/ ISETP.GT.U32.AND P3, PT, R4.reuse, R11, PT ; /* 0x0000000b0400720c */
/* 0x040fe40003f64070 */
/*0330*/ ISETP.GT.U32.AND P5, PT, R4, R15, PT ; /* 0x0000000f0400720c */
/* 0x000fe20003fa4070 */
/*0340*/ IMAD.MOV R12, RZ, RZ, -R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0a02 */
/*0350*/ IMAD.MOV R16, RZ, RZ, -R8 ; /* 0x000000ffff107224 */
/* 0x000fc400078e0a08 */
/*0360*/ IMAD R13, R4.reuse, R12, R13 ; /* 0x0000000c040d7224 */
/* 0x040fe400078e020d */
/*0370*/ IMAD R17, R4, R16, R17 ; /* 0x0000001004117224 */
/* 0x000fc600078e0211 */
/*0380*/ ISETP.GT.U32.AND P4, PT, R4.reuse, R13, PT ; /* 0x0000000d0400720c */
/* 0x040fe20003f84070 */
/*0390*/ @!P3 IMAD.IADD R11, R11, 0x1, -R4.reuse ; /* 0x000000010b0bb824 */
/* 0x100fe200078e0a04 */
/*03a0*/ ISETP.GT.U32.AND P0, PT, R4, R17, PT ; /* 0x000000110400720c */
/* 0x000fe20003f04070 */
/*03b0*/ @!P5 IMAD.IADD R15, R15, 0x1, -R4 ; /* 0x000000010f0fd824 */
/* 0x000fe200078e0a04 */
/*03c0*/ @!P3 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303b810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ ISETP.GE.U32.AND P6, PT, R11, R4.reuse, PT ; /* 0x000000040b00720c */
/* 0x080fe40003fc6070 */
/*03e0*/ ISETP.GE.U32.AND P2, PT, R15, R4, PT ; /* 0x000000040f00720c */
/* 0x000fe40003f46070 */
/*03f0*/ @!P5 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0ad810 */
/* 0x000fc40007ffe0ff */
/*0400*/ ISETP.GE.AND P5, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003fa6270 */
/*0410*/ @!P4 IMAD.IADD R13, R13, 0x1, -R4.reuse ; /* 0x000000010d0dc824 */
/* 0x100fe200078e0a04 */
/*0420*/ @!P4 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202c810 */
/* 0x000fe20007ffe0ff */
/*0430*/ @!P0 IMAD.IADD R17, R17, 0x1, -R4 ; /* 0x0000000111118824 */
/* 0x000fe200078e0a04 */
/*0440*/ @!P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108088810 */
/* 0x000fe40007ffe0ff */
/*0450*/ ISETP.GE.U32.AND P3, PT, R13, R4.reuse, PT ; /* 0x000000040d00720c */
/* 0x080fe40003f66070 */
/*0460*/ ISETP.GE.U32.AND P4, PT, R17, R4, PT ; /* 0x000000041100720c */
/* 0x000fe40003f86070 */
/*0470*/ @P6 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103036810 */
/* 0x000fc40007ffe0ff */
/*0480*/ @P2 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a2810 */
/* 0x000fe40007ffe0ff */
/*0490*/ ISETP.GE.AND P6, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003fc6270 */
/*04a0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*04b0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f46270 */
/*04c0*/ @!P5 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0ad224 */
/* 0x000fe200078e0a0a */
/*04d0*/ LOP3.LUT R4, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff047a12 */
/* 0x000fe400078e33ff */
/*04e0*/ @P3 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102023810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ @P4 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108084810 */
/* 0x000fc40007ffe0ff */
/*0500*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe40003f65270 */
/*0510*/ ISETP.NE.AND P0, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f05270 */
/*0520*/ @!P6 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02e224 */
/* 0x000fe200078e0a02 */
/*0530*/ ISETP.NE.AND P4, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f85270 */
/*0540*/ @!P2 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0a08 */
/*0550*/ SEL R3, R4.reuse, R3, !P3 ; /* 0x0000000304037207 */
/* 0x040fe40005800000 */
/*0560*/ SEL R10, R4.reuse, R10, !P3 ; /* 0x0000000a040a7207 */
/* 0x040fe40005800000 */
/*0570*/ SEL R8, R4, R8, !P3 ; /* 0x0000000804087207 */
/* 0x000fc40005800000 */
/*0580*/ SEL R2, R4, R2, !P3 ; /* 0x0000000204027207 */
/* 0x000fe40005800000 */
/*0590*/ SEL R3, R3, c[0x0][0x170], P4 ; /* 0x00005c0003037a07 */
/* 0x000fe40002000000 */
/*05a0*/ SEL R7, R10, c[0x0][0x170], P4 ; /* 0x00005c000a077a07 */
/* 0x000fe40002000000 */
/*05b0*/ SEL R8, R8, RZ, P0 ; /* 0x000000ff08087207 */
/* 0x000fe40000000000 */
/*05c0*/ SEL R5, R2, 0xffffffff, P0 ; /* 0xffffffff02057807 */
/* 0x000fe40000000000 */
/*05d0*/ ISETP.NE.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fc40003f05270 */
/*05e0*/ ISETP.EQ.AND P1, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fda0003f22270 */
/*05f0*/ @!P0 BRA P1, 0xb40 ; /* 0x0000054000008947 */
/* 0x000fea0000800000 */
/*0600*/ IMAD R6, R8, c[0x0][0x170], R5 ; /* 0x00005c0008067a24 */
/* 0x000fe400078e0205 */
/*0610*/ IMAD R9, R7, c[0x0][0x170], R3 ; /* 0x00005c0007097a24 */
/* 0x000fca00078e0203 */
/*0620*/ ISETP.GE.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f06270 */
/*0630*/ @P0 BRA 0xb40 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.IADD R2, R7, 0x1, -R8 ; /* 0x0000000107027824 */
/* 0x000fe200078e0a08 */
/*0650*/ BSSY B1, 0x790 ; /* 0x0000013000017945 */
/* 0x000fe20003800000 */
/*0660*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0670*/ IMAD R2, R2, c[0x0][0x170], R3 ; /* 0x00005c0002027a24 */
/* 0x000fc800078e0203 */
/*0680*/ IMAD.IADD R3, R2, 0x1, -R5 ; /* 0x0000000102037824 */
/* 0x000fe200078e0a05 */
/*0690*/ IADD3 R2, -R5, -0x1, R2 ; /* 0xffffffff05027810 */
/* 0x000fc80007ffe102 */
/*06a0*/ LOP3.LUT P0, R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fe4000780c0ff */
/*06b0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fd60003f26070 */
/*06c0*/ @!P0 BRA 0x780 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*06d0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*06f0*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fc60003f05270 */
/*0700*/ IMAD.WIDE R2, R4, R3, c[0x0][0x178] ; /* 0x00005e0004027625 */
/* 0x000fca00078e0203 */
/*0710*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001ea000c101904 */
/*0720*/ @!P0 BRA 0x780 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.NE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe20003f05270 */
/*0740*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x0003e2000c101904 */
/*0750*/ IADD3 R4, R6, 0x2, RZ ; /* 0x0000000206047810 */
/* 0x000fd60007ffe0ff */
/*0760*/ @P0 STG.E [R2.64+0x8], R0 ; /* 0x0000080002000986 */
/* 0x0003e2000c101904 */
/*0770*/ @P0 IADD3 R4, R6, 0x3, RZ ; /* 0x0000000306040810 */
/* 0x000fc60007ffe0ff */
/*0780*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0790*/ @!P1 BRA 0xb40 ; /* 0x000003a000009947 */
/* 0x000fea0003800000 */
/*07a0*/ IMAD.IADD R2, R9, 0x1, -R4 ; /* 0x0000000109027824 */
/* 0x003fe200078e0a04 */
/*07b0*/ BSSY B1, 0x9c0 ; /* 0x0000020000017945 */
/* 0x000fe20003800000 */
/*07c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*07e0*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe40003f24270 */
/*07f0*/ IADD3 R2, R4, 0x1, RZ ; /* 0x0000000104027810 */
/* 0x000fca0007ffe0ff */
/*0800*/ IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fcc00078e0203 */
/*0810*/ @!P1 BRA 0x9b0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0820*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0830*/ IADD3 R7, R9, -0xc, RZ ; /* 0xfffffff409077810 */
/* 0x000fe40007ffe0ff */
/*0840*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007ffe0ff */
/*0850*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*0860*/ IADD3 R5, P2, R2, 0x40, RZ ; /* 0x0000004002057810 */
/* 0x000fe40007f5e0ff */
/*0870*/ ISETP.GE.AND P1, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe20003f26270 */
/*0880*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe4000c101904 */
/*0890*/ IMAD.X R6, RZ, RZ, R3, P2 ; /* 0x000000ffff067224 */
/* 0x000fe400010e0603 */
/*08a0*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*08b0*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*08c0*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*08d0*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x000fe8000c101904 */
/*08e0*/ STG.E [R2.64+0x18], R0 ; /* 0x0000180002007986 */
/* 0x000fe8000c101904 */
/*08f0*/ STG.E [R2.64+0x1c], R0 ; /* 0x00001c0002007986 */
/* 0x000fe8000c101904 */
/*0900*/ STG.E [R2.64+0x20], R0 ; /* 0x0000200002007986 */
/* 0x000fe8000c101904 */
/*0910*/ STG.E [R2.64+0x24], R0 ; /* 0x0000240002007986 */
/* 0x000fe8000c101904 */
/*0920*/ STG.E [R2.64+0x28], R0 ; /* 0x0000280002007986 */
/* 0x000fe8000c101904 */
/*0930*/ STG.E [R2.64+0x2c], R0 ; /* 0x00002c0002007986 */
/* 0x000fe8000c101904 */
/*0940*/ STG.E [R2.64+0x30], R0 ; /* 0x0000300002007986 */
/* 0x000fe8000c101904 */
/*0950*/ STG.E [R2.64+0x34], R0 ; /* 0x0000340002007986 */
/* 0x000fe8000c101904 */
/*0960*/ STG.E [R2.64+0x38], R0 ; /* 0x0000380002007986 */
/* 0x000fe8000c101904 */
/*0970*/ STG.E [R2.64+0x3c], R0 ; /* 0x00003c0002007986 */
/* 0x0001e4000c101904 */
/*0980*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0990*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*09a0*/ @!P1 BRA 0x840 ; /* 0xfffffe9000009947 */
/* 0x000fea000383ffff */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ IMAD.IADD R5, R9, 0x1, -R4 ; /* 0x0000000109057824 */
/* 0x000fe200078e0a04 */
/*09d0*/ BSSY B1, 0xaf0 ; /* 0x0000011000017945 */
/* 0x000fe80003800000 */
/*09e0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*09f0*/ @!P1 BRA 0xae0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0a00*/ IADD3 R5, P1, R2, 0x20, RZ ; /* 0x0000002002057810 */
/* 0x000fe20007f3e0ff */
/*0a10*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a30*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.X R6, RZ, RZ, R3, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0603 */
/*0a50*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0a60*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*0a70*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*0a80*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*0a90*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x000fe8000c101904 */
/*0aa0*/ STG.E [R2.64+0x18], R0 ; /* 0x0000180002007986 */
/* 0x000fe8000c101904 */
/*0ab0*/ STG.E [R2.64+0x1c], R0 ; /* 0x00001c0002007986 */
/* 0x0001e4000c101904 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0ad0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*0ae0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0af0*/ ISETP.LT.OR P0, PT, R4, R9, P0 ; /* 0x000000090400720c */
/* 0x000fda0000701670 */
/*0b00*/ @P0 STG.E [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e8000c101904 */
/*0b10*/ @P0 STG.E [R2.64+0x4], R0 ; /* 0x0000040002000986 */
/* 0x0001e8000c101904 */
/*0b20*/ @P0 STG.E [R2.64+0x8], R0 ; /* 0x0000080002000986 */
/* 0x0001e8000c101904 */
/*0b30*/ @P0 STG.E [R2.64+0xc], R0 ; /* 0x00000c0002000986 */
/* 0x0001e4000c101904 */
/*0b40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b50*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff037624 */
/* 0x003fc800078e00ff */
/*0b60*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x000fca00078e0200 */
/*0b70*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04270 */
/*0b80*/ @!P0 BRA 0x70 ; /* 0xfffff4e000008947 */
/* 0x000fea000383ffff */
/*0b90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.globl _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.p2align 8
.type _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi,@function
_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x8
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s6, v1
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0xc
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s7, s8, 4
s_addc_u32 s8, s9, 0
s_ashr_i32 s9, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s9
s_xor_b32 s10, s2, s9
s_load_b32 s2, s[4:5], 0x0
v_cvt_f32_u32_e32 v0, s10
s_sub_i32 s4, 0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s2, s11
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v0
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, v0, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s6, v1
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b64 v[4:5], v[2:3], off
global_load_b64 v[2:3], v[2:3], off offset:-8
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v0, 31, v4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v2
v_ashrrev_i32_e32 v8, 31, v5
v_ashrrev_i32_e32 v9, 31, v3
v_lshrrev_b32_e32 v0, 29, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshrrev_b32_e32 v6, 29, v6
v_lshrrev_b32_e32 v8, 29, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshrrev_b32_e32 v9, 29, v9
v_add_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, v2, v6
v_add_nc_u32_e32 v4, v5, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 3, v0
v_ashrrev_i32_e32 v0, 31, v0
v_ashrrev_i32_e32 v6, 3, v2
v_ashrrev_i32_e32 v2, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v5, v0
v_add_nc_u32_e32 v6, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v5, v5, v0
v_xor_b32_e32 v0, s9, v0
v_xor_b32_e32 v6, v6, v2
v_xor_b32_e32 v2, s9, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v10, v5, v7
v_mul_hi_u32 v11, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v14, v10, s10
v_add_nc_u32_e32 v18, 1, v10
v_mul_lo_u32 v15, v11, s10
v_add_nc_u32_e32 v19, 1, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v5, v5, v14
v_sub_nc_u32_e32 v6, v6, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s10, v5
v_add_nc_u32_e32 v3, v3, v9
v_cmp_le_u32_e64 s0, s10, v6
v_subrev_nc_u32_e32 v15, s10, v5
v_cndmask_b32_e32 v10, v10, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 3, v3
v_ashrrev_i32_e32 v3, 31, v3
v_cndmask_b32_e64 v11, v11, v19, s0
v_cndmask_b32_e32 v5, v5, v15, vcc_lo
v_add_nc_u32_e32 v15, 1, v10
v_add_nc_u32_e32 v9, v9, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s10, v5
v_xor_b32_e32 v9, v9, v3
v_xor_b32_e32 v3, s9, v3
v_cndmask_b32_e32 v5, v10, v15, vcc_lo
v_ashrrev_i32_e32 v8, 3, v4
v_ashrrev_i32_e32 v4, 31, v4
v_mul_hi_u32 v13, v9, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v0
v_sub_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v13, s10
v_add_nc_u32_e32 v14, 1, v13
v_sub_nc_u32_e32 v9, v9, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s10, v9
v_cndmask_b32_e64 v13, v13, v14, s2
v_subrev_nc_u32_e32 v14, s10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v14, s2
v_add_nc_u32_e32 v14, 1, v13
v_add_nc_u32_e32 v8, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v4
v_xor_b32_e32 v4, s9, v4
v_mul_hi_u32 v12, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v16, v12, s10
v_add_nc_u32_e32 v20, 1, v12
v_sub_nc_u32_e32 v8, v8, v16
v_subrev_nc_u32_e32 v16, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e64 s1, s10, v8
v_cndmask_b32_e64 v6, v6, v16, s0
v_subrev_nc_u32_e32 v17, s10, v8
v_add_nc_u32_e32 v16, 1, v11
v_cmp_eq_u32_e64 s0, s6, v1
v_cndmask_b32_e64 v12, v12, v20, s1
v_cmp_le_u32_e32 vcc_lo, s10, v6
v_cndmask_b32_e64 v8, v8, v17, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v0, v0, s3, s0
v_add_nc_u32_e32 v17, 1, v12
v_cndmask_b32_e32 v6, v11, v16, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v6, v2
v_cndmask_b32_e32 v9, v13, v14, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v8
v_sub_nc_u32_e32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v3
v_cndmask_b32_e32 v8, v12, v17, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_sub_nc_u32_e32 v3, v9, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v4
v_cndmask_b32_e64 v5, v3, 0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v8, v4
v_cndmask_b32_e64 v4, v2, -1, vcc_lo
v_cndmask_b32_e64 v6, v6, s3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, v0, v4
v_cmp_ne_u32_e64 s0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v5, s3, v[4:5]
v_mad_u64_u32 v[4:5], null, v6, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v2, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_co_u32 v5, vcc_lo, s7, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s8, v6, vcc_lo
.LBB0_6:
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[5:6], v1, off
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
v_cmp_ge_i32_e32 vcc_lo, v2, v4
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_6
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, .Lfunc_end0-_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00186931_00000000-6_set_bookmarks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi
.type _Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi, @function
_Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13set_bookmarksP4int2iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi, .-_Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi
.globl _Z13set_bookmarksP4int2iiiPi
.type _Z13set_bookmarksP4int2iiiPi, @function
_Z13set_bookmarksP4int2iiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z13set_bookmarksP4int2iiiPiP4int2iiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13set_bookmarksP4int2iiiPi, .-_Z13set_bookmarksP4int2iiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13set_bookmarksP4int2iiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13set_bookmarksP4int2iiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "set_bookmarks.hip"
.globl _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi # -- Begin function _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.p2align 4, 0x90
.type _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi,@function
_Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi: # @_Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, .Lfunc_end0-_Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi,@object # @_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.section .rodata,"a",@progbits
.globl _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.p2align 3, 0x0
_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi:
.quad _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.size _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13set_bookmarksP15HIP_vector_typeIiLj2EEiiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} \
}
float scan_seq(float *, int, int);
int calculate_grid_size(int, int);
float scan(float*, int, int, char*, int);
void fprint_mat(FILE *, float *, int);
float* init(int);
__global__ void scan_kernel(float *, int);
__global__ void scan_kernel_coalesc(float *, int);
int block_size;
int main(int argc, char **argv) {
if(argc < 4) {
printf("usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\n\
algoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n", argv[0]);
exit(-1);
}
FILE *input = fopen(argv[1], "r");
int debug = (argc > 4 ? strcmp("debug", argv[4]) == 0 : 0);
int size = atoi(argv[1]);
float *vector = init(size);
float size_of = size * sizeof(float);
float mega_byte = 1024 * 1024;
block_size = atoi(argv[3]);
printf("%f MBytes\n", (size_of / mega_byte));
if(strncmp(argv[2], "s", 1) == 0) {
float sum = scan_seq(vector, size, debug);
printf("Sum: %f\n", sum);
} else {
float sum = scan(vector, block_size, size, argv[2], debug);
printf("Sum: %f\n", sum);
}
return 0;
}
int calculate_grid_size(int tile_size, int size) {
int div = size / tile_size;
int remainder = size - (tile_size * div);
if(remainder > 0) {
div++;
}
return div;
}
float scan(float *input, int tile_size, int size, char *algorithm, int debug) {
int dim_grid = calculate_grid_size(tile_size, size);
float *device_input;
FILE *f = NULL;
size_t size_bytes = size * sizeof(float);
size_t block_size_bytes = tile_size * sizeof(float);
CUDA_CHECK_RETURN(cudaMalloc((void **) &device_input, size_bytes));
CUDA_CHECK_RETURN(cudaMemcpy(device_input, input, size_bytes, cudaMemcpyHostToDevice));
if(strlen(algorithm) == 1 && strncmp(algorithm, "c", 1) == 0) {
scan_kernel <<<dim_grid, tile_size>>> (device_input, size);
if(debug) {
f = fopen("saida_c.txt", "w");
}
} else {
scan_kernel_coalesc <<<dim_grid, tile_size, block_size_bytes>>> (device_input, size);
if(debug) {
f = fopen("saida_cc.txt", "w");
}
}
CUDA_CHECK_RETURN(cudaGetLastError());
CUDA_CHECK_RETURN(cudaMemcpy(input, device_input, size_bytes, cudaMemcpyDeviceToHost));
CUDA_CHECK_RETURN(cudaFree(device_input));
// Percorro as bordas dos blocos para pegar o menor
int index = 0;
float sum = 0;
float sum1 = 0.0, sum2 = 0.0;
int half_dim_grid = dim_grid / 2;
if(debug) {
fprint_mat(f, input, size);
fclose(f);
}
// Soma as bordas, soma a metade para evitar de perder precisao
for(int i = 1; i < half_dim_grid; ++i) {
index = (tile_size * i) - 1;
sum1 += input[index];
}
for(int i = half_dim_grid; i < dim_grid; ++i) {
index = (tile_size * i) - 1;
sum2 += input[index];
}
sum = sum1;
if((size) != index) {
sum += input[size - 1];
}
sum += sum2;
return sum;
}
float scan_seq(float *input, int size, int debug) {
float found = 0;
for(int i = 0; i < size; ++i) {
found += input[i];
}
if(debug) {
FILE *f = fopen("saida_s.txt", "w");
fprint_mat(f, input, size);
fclose(f);
}
return found;
}
void fprint_mat(FILE *f, float *v, int n) {
for(int i = 0; i < n-1; i++) {
fprintf(f, "%f ", v[i]);
}
fprintf(f, "%f", v[n-1]);
}
float* init(int n) {
float *v = (float*) malloc(sizeof(float) * n);
for(int i = 0; i < n; ++i) {
v[i] = (float) i;
}
return v;
}
////////////////////////////////////////////////////////////////////////////////
/***
* Esse Scan é feito apenas no interior do bloco, logo quem chamou ele precisa verificar
* os limites dos blocos para pegar o menor valor
*/
__global__
void scan_kernel(float *input, int size) {
int local_block_dim = blockDim.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int ti_bi = ti - bi; // ti - bi evita que a thread saia do limite do bloco.
int local_size = size;
float aux = 0;
int offset = 1;
// Algoritmo do Scan em cima das posições e threads relativas ao bloco
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(ti_bi >= offset && ti < local_size) {
aux = input[ti - offset];
}
__syncthreads();
if(ti_bi >= offset && ti < local_size) {
input[ti] = aux + input[ti];
}
__syncthreads();
}
}
__global__
void scan_kernel_coalesc(float *input, int size) {
int local_block_dim = blockDim.x;
int thread_id = threadIdx.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int local_size = size;
float aux = 0;
int offset = 1;
extern __shared__ float local[];
// Carrega o valor relativo a thread para a memória local.
if(ti < local_size) {
local[thread_id] = input[ti];
}
__syncthreads();
// Aplica o Scan em cima da memória local
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(thread_id >= offset && thread_id < local_block_dim) {
aux = local[thread_id - offset];
}
__syncthreads();
if(thread_id >= offset && thread_id < local_block_dim) {
local[thread_id] = aux + local[thread_id];
}
__syncthreads();
}
// Volta com o valor local na memória global
input[ti] = local[thread_id];
} | code for sm_80
Function : _Z19scan_kernel_coalescPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0060*/ BSSY B0, 0xf0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0070*/ ISETP.GT.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f24270 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R9 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0209 */
/*0090*/ ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x040fe20003f06270 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0203 */
/*00b0*/ @P0 BRA 0xe0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STS [R9.X4], R0 ; /* 0x0000000009007388 */
/* 0x0041e40000004800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ @!P1 BRA 0x1f0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0110*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fca00078e00ff */
/*0130*/ ISETP.GE.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fc80003f06270 */
/*0140*/ ISETP.LT.AND P0, PT, R9, c[0x0][0x0], P0 ; /* 0x0000000009007a0c */
/* 0x000fda0000701270 */
/*0150*/ @P0 IADD3 R5, R9, -R4, RZ ; /* 0x8000000409050210 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047824 */
/* 0x000fc800078e00ff */
/*0170*/ @P0 LDS R0, [R5.X4] ; /* 0x0000000005000984 */
/* 0x000fe80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P0 LDS R7, [R9.X4] ; /* 0x0000000009070984 */
/* 0x000e240000004800 */
/*01a0*/ @P0 FADD R7, R0, R7 ; /* 0x0000000700070221 */
/* 0x001fca0000000000 */
/*01b0*/ @P0 STS [R9.X4], R7 ; /* 0x0000000709000388 */
/* 0x0001e80000004800 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 BRA 0x130 ; /* 0xffffff4000008947 */
/* 0x001fea000383ffff */
/*01f0*/ LDS R5, [R9.X4] ; /* 0x0000000009057984 */
/* 0x000e680000004800 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11scan_kernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fe20000000f00 */
/*0080*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R8 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0208 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*00c0*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fc80003f06270 */
/*00d0*/ ISETP.LT.AND P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000701270 */
/*00e0*/ @P0 MOV R5, 0x4 ; /* 0x0000000400050802 */
/* 0x000fe20000000f00 */
/*00f0*/ @P0 IMAD.IADD R4, R0, 0x1, -R7 ; /* 0x0000000100040824 */
/* 0x000fc800078e0a07 */
/*0100*/ @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004040625 */
/* 0x000fca00078e0205 */
/*0110*/ @P0 LDG.E R6, [R4.64] ; /* 0x0000000404060981 */
/* 0x000ea8000c1e1900 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P0 LDG.E R9, [R2.64] ; /* 0x0000000402090981 */
/* 0x000ea2000c1e1900 */
/*0140*/ SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107077819 */
/* 0x000fe200000006ff */
/*0150*/ @P0 FADD R9, R6, R9 ; /* 0x0000000906090221 */
/* 0x004fca0000000000 */
/*0160*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0001e8000c101904 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f06270 */
/*0190*/ @!P0 BRA 0xc0 ; /* 0xffffff2000008947 */
/* 0x001fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} \
}
float scan_seq(float *, int, int);
int calculate_grid_size(int, int);
float scan(float*, int, int, char*, int);
void fprint_mat(FILE *, float *, int);
float* init(int);
__global__ void scan_kernel(float *, int);
__global__ void scan_kernel_coalesc(float *, int);
int block_size;
int main(int argc, char **argv) {
if(argc < 4) {
printf("usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\n\
algoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n", argv[0]);
exit(-1);
}
FILE *input = fopen(argv[1], "r");
int debug = (argc > 4 ? strcmp("debug", argv[4]) == 0 : 0);
int size = atoi(argv[1]);
float *vector = init(size);
float size_of = size * sizeof(float);
float mega_byte = 1024 * 1024;
block_size = atoi(argv[3]);
printf("%f MBytes\n", (size_of / mega_byte));
if(strncmp(argv[2], "s", 1) == 0) {
float sum = scan_seq(vector, size, debug);
printf("Sum: %f\n", sum);
} else {
float sum = scan(vector, block_size, size, argv[2], debug);
printf("Sum: %f\n", sum);
}
return 0;
}
int calculate_grid_size(int tile_size, int size) {
int div = size / tile_size;
int remainder = size - (tile_size * div);
if(remainder > 0) {
div++;
}
return div;
}
float scan(float *input, int tile_size, int size, char *algorithm, int debug) {
int dim_grid = calculate_grid_size(tile_size, size);
float *device_input;
FILE *f = NULL;
size_t size_bytes = size * sizeof(float);
size_t block_size_bytes = tile_size * sizeof(float);
CUDA_CHECK_RETURN(cudaMalloc((void **) &device_input, size_bytes));
CUDA_CHECK_RETURN(cudaMemcpy(device_input, input, size_bytes, cudaMemcpyHostToDevice));
if(strlen(algorithm) == 1 && strncmp(algorithm, "c", 1) == 0) {
scan_kernel <<<dim_grid, tile_size>>> (device_input, size);
if(debug) {
f = fopen("saida_c.txt", "w");
}
} else {
scan_kernel_coalesc <<<dim_grid, tile_size, block_size_bytes>>> (device_input, size);
if(debug) {
f = fopen("saida_cc.txt", "w");
}
}
CUDA_CHECK_RETURN(cudaGetLastError());
CUDA_CHECK_RETURN(cudaMemcpy(input, device_input, size_bytes, cudaMemcpyDeviceToHost));
CUDA_CHECK_RETURN(cudaFree(device_input));
// Percorro as bordas dos blocos para pegar o menor
int index = 0;
float sum = 0;
float sum1 = 0.0, sum2 = 0.0;
int half_dim_grid = dim_grid / 2;
if(debug) {
fprint_mat(f, input, size);
fclose(f);
}
// Soma as bordas, soma a metade para evitar de perder precisao
for(int i = 1; i < half_dim_grid; ++i) {
index = (tile_size * i) - 1;
sum1 += input[index];
}
for(int i = half_dim_grid; i < dim_grid; ++i) {
index = (tile_size * i) - 1;
sum2 += input[index];
}
sum = sum1;
if((size) != index) {
sum += input[size - 1];
}
sum += sum2;
return sum;
}
float scan_seq(float *input, int size, int debug) {
float found = 0;
for(int i = 0; i < size; ++i) {
found += input[i];
}
if(debug) {
FILE *f = fopen("saida_s.txt", "w");
fprint_mat(f, input, size);
fclose(f);
}
return found;
}
void fprint_mat(FILE *f, float *v, int n) {
for(int i = 0; i < n-1; i++) {
fprintf(f, "%f ", v[i]);
}
fprintf(f, "%f", v[n-1]);
}
float* init(int n) {
float *v = (float*) malloc(sizeof(float) * n);
for(int i = 0; i < n; ++i) {
v[i] = (float) i;
}
return v;
}
////////////////////////////////////////////////////////////////////////////////
/***
* Esse Scan é feito apenas no interior do bloco, logo quem chamou ele precisa verificar
* os limites dos blocos para pegar o menor valor
*/
__global__
void scan_kernel(float *input, int size) {
int local_block_dim = blockDim.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int ti_bi = ti - bi; // ti - bi evita que a thread saia do limite do bloco.
int local_size = size;
float aux = 0;
int offset = 1;
// Algoritmo do Scan em cima das posições e threads relativas ao bloco
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(ti_bi >= offset && ti < local_size) {
aux = input[ti - offset];
}
__syncthreads();
if(ti_bi >= offset && ti < local_size) {
input[ti] = aux + input[ti];
}
__syncthreads();
}
}
__global__
void scan_kernel_coalesc(float *input, int size) {
int local_block_dim = blockDim.x;
int thread_id = threadIdx.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int local_size = size;
float aux = 0;
int offset = 1;
extern __shared__ float local[];
// Carrega o valor relativo a thread para a memória local.
if(ti < local_size) {
local[thread_id] = input[ti];
}
__syncthreads();
// Aplica o Scan em cima da memória local
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(thread_id >= offset && thread_id < local_block_dim) {
aux = local[thread_id - offset];
}
__syncthreads();
if(thread_id >= offset && thread_id < local_block_dim) {
local[thread_id] = aux + local[thread_id];
}
__syncthreads();
}
// Volta com o valor local na memória global
input[ti] = local[thread_id];
} | .file "tmpxft_000fe07a_00000000-6_Sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19calculate_grid_sizeii
.type _Z19calculate_grid_sizeii, @function
_Z19calculate_grid_sizeii:
.LFB2058:
.cfi_startproc
endbr64
movl %esi, %eax
cltd
idivl %edi
testl %edx, %edx
setg %dl
movzbl %dl, %edx
addl %edx, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z19calculate_grid_sizeii, .-_Z19calculate_grid_sizeii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "%f"
.text
.globl _Z10fprint_matP8_IO_FILEPfi
.type _Z10fprint_matP8_IO_FILEPfi, @function
_Z10fprint_matP8_IO_FILEPfi:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r15
movl %edx, %r14d
cmpl $1, %edx
jle .L6
movq %rsi, %rbx
leal -2(%rdx), %eax
leaq 4(%rsi,%rax,4), %r13
leaq .LC0(%rip), %r12
.L7:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L7
.L6:
movslq %r14d, %r14
pxor %xmm0, %xmm0
cvtss2sd -4(%r15,%r14,4), %xmm0
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z10fprint_matP8_IO_FILEPfi, .-_Z10fprint_matP8_IO_FILEPfi
.section .rodata.str1.1
.LC3:
.string "w"
.LC4:
.string "saida_s.txt"
.text
.globl _Z8scan_seqPfii
.type _Z8scan_seqPfii, @function
_Z8scan_seqPfii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
testl %esi, %esi
jle .L14
movq %rdi, %rax
movslq %esi, %rcx
leaq (%rdi,%rcx,4), %rcx
movl $0x00000000, %ebx
.L12:
movd %ebx, %xmm1
addss (%rax), %xmm1
movd %xmm1, %ebx
addq $4, %rax
cmpq %rcx, %rax
jne .L12
.L11:
testl %edx, %edx
jne .L17
.L10:
movd %ebx, %xmm0
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl $0x00000000, %ebx
jmp .L11
.L17:
leaq .LC3(%rip), %rsi
leaq .LC4(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl %ebp, %edx
movq %r12, %rsi
movq %rax, %rdi
call _Z10fprint_matP8_IO_FILEPfi
movq %r13, %rdi
call fclose@PLT
jmp .L10
.cfi_endproc
.LFE2060:
.size _Z8scan_seqPfii, .-_Z8scan_seqPfii
.globl _Z4initi
.type _Z4initi, @function
_Z4initi:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebp
movslq %edi, %rbx
leaq 0(,%rbx,4), %rdi
call malloc@PLT
testl %ebp, %ebp
jle .L18
movl $0, %edx
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rax,%rdx,4)
addq $1, %rdx
cmpq %rdx, %rbx
jne .L20
.L18:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z4initi, .-_Z4initi
.globl _Z32__device_stub__Z11scan_kernelPfiPfi
.type _Z32__device_stub__Z11scan_kernelPfiPfi, @function
_Z32__device_stub__Z11scan_kernelPfiPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11scan_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z32__device_stub__Z11scan_kernelPfiPfi, .-_Z32__device_stub__Z11scan_kernelPfiPfi
.globl _Z11scan_kernelPfi
.type _Z11scan_kernelPfi, @function
_Z11scan_kernelPfi:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11scan_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z11scan_kernelPfi, .-_Z11scan_kernelPfi
.globl _Z40__device_stub__Z19scan_kernel_coalescPfiPfi
.type _Z40__device_stub__Z19scan_kernel_coalescPfiPfi, @function
_Z40__device_stub__Z19scan_kernel_coalescPfiPfi:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19scan_kernel_coalescPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z40__device_stub__Z19scan_kernel_coalescPfiPfi, .-_Z40__device_stub__Z19scan_kernel_coalescPfiPfi
.globl _Z19scan_kernel_coalescPfi
.type _Z19scan_kernel_coalescPfi, @function
_Z19scan_kernel_coalescPfi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19scan_kernel_coalescPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z19scan_kernel_coalescPfi, .-_Z19scan_kernel_coalescPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/wakim/prog-gpu-cuda/master/Sum/src/Sum.cu"
.align 8
.LC6:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1
.LC7:
.string "saida_c.txt"
.LC8:
.string "saida_cc.txt"
.text
.globl _Z4scanPfiiPci
.type _Z4scanPfiiPci, @function
_Z4scanPfiiPci:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movl %esi, %r13d
movl %edx, %ebx
movl %edx, 4(%rsp)
movq %rcx, %rbp
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edx, %esi
movl %r13d, %edi
call _Z19calculate_grid_sizeii
movl %eax, %r12d
movslq %ebx, %r15
salq $2, %r15
movslq %r13d, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L63
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L64
movq %rbp, %rdi
call strlen@PLT
cmpq $1, %rax
jne .L42
cmpb $99, 0(%rbp)
je .L65
.L42:
movl %r13d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r12d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movq %rbx, %r8
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L45:
movq $0, 8(%rsp)
cmpl $0, (%rsp)
jne .L67
.L44:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L68
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L69
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L70
movl %r12d, %ebp
shrl $31, %ebp
addl %r12d, %ebp
sarl %ebp
cmpl $0, (%rsp)
jne .L71
.L49:
cmpl $3, %r12d
jle .L58
leaq (%r14,%rbx), %rdx
movl $1, %eax
pxor %xmm0, %xmm0
.L51:
addss -4(%rdx), %xmm0
addl $1, %eax
addq %rbx, %rdx
cmpl %eax, %ebp
jg .L51
leal -2(%rbp), %eax
imull %r13d, %eax
leal -1(%r13,%rax), %eax
.L50:
cmpl %ebp, %r12d
jle .L59
movl %r13d, %esi
imull %ebp, %esi
movslq %esi, %rax
leaq (%r14,%rax,4), %rdx
movl %ebp, %eax
pxor %xmm1, %xmm1
.L53:
addss -4(%rdx), %xmm1
movl %eax, %ecx
addl $1, %eax
addq %rbx, %rdx
cmpl %eax, %r12d
jne .L53
subl %ebp, %ecx
imull %r13d, %ecx
leal -1(%rsi,%rcx), %eax
.L52:
cmpl %eax, 4(%rsp)
je .L54
addss -4(%r14,%r15), %xmm0
.L54:
addss %xmm1, %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $87, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $88, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
movl %r13d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r12d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L43:
movq $0, 8(%rsp)
cmpl $0, (%rsp)
je .L44
leaq .LC3(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
jmp .L44
.L73:
movl 4(%rsp), %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z11scan_kernelPfiPfi
jmp .L43
.L66:
movl 4(%rsp), %esi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z19scan_kernel_coalescPfiPfi
jmp .L45
.L67:
leaq .LC3(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
jmp .L44
.L68:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $102, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $104, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L70:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $106, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
movl 4(%rsp), %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call _Z10fprint_matP8_IO_FILEPfi
movq 8(%rsp), %rdi
call fclose@PLT
jmp .L49
.L58:
pxor %xmm0, %xmm0
movl $0, %eax
jmp .L50
.L59:
pxor %xmm1, %xmm1
jmp .L52
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z4scanPfiiPci, .-_Z4scanPfiiPci
.section .rodata.str1.8
.align 8
.LC9:
.string "usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\nalgoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n"
.section .rodata.str1.1
.LC10:
.string "r"
.LC11:
.string "debug"
.LC13:
.string "%f MBytes\n"
.LC14:
.string "Sum: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %rbp
cmpl $3, %edi
jle .L83
movl %edi, %ebx
movq 8(%rsi), %rdi
leaq .LC10(%rip), %rsi
call fopen@PLT
movl $0, %r13d
cmpl $4, %ebx
jle .L76
movq 32(%rbp), %rsi
leaq .LC11(%rip), %rdi
call strcmp@PLT
testl %eax, %eax
sete %r13b
movzbl %r13b, %r13d
.L76:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movl %eax, %edi
call _Z4initi
movq %rax, %r12
movslq %ebx, %rbx
salq $2, %rbx
js .L77
pxor %xmm1, %xmm1
cvtsi2ssq %rbx, %xmm1
movd %xmm1, %ebx
.L78:
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, block_size(%rip)
movd %ebx, %xmm0
mulss .LC12(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rbp), %rcx
cmpb $115, (%rcx)
je .L84
movl %r13d, %r8d
movl %r14d, %edx
movl block_size(%rip), %esi
movq %r12, %rdi
call _Z4scanPfiiPci
cvtss2sd %xmm0, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L80:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L83:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L77:
shrq %rbx
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
addss %xmm0, %xmm0
movd %xmm0, %ebx
jmp .L78
.L84:
movl %r13d, %edx
movl %r14d, %esi
movq %r12, %rdi
call _Z8scan_seqPfii
cvtss2sd %xmm0, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L80
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z19scan_kernel_coalescPfi"
.LC16:
.string "_Z11scan_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z19scan_kernel_coalescPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z11scan_kernelPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl block_size
.bss
.align 4
.type block_size, @object
.size block_size, 4
block_size:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC12:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} \
}
float scan_seq(float *, int, int);
int calculate_grid_size(int, int);
float scan(float*, int, int, char*, int);
void fprint_mat(FILE *, float *, int);
float* init(int);
__global__ void scan_kernel(float *, int);
__global__ void scan_kernel_coalesc(float *, int);
int block_size;
int main(int argc, char **argv) {
if(argc < 4) {
printf("usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\n\
algoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n", argv[0]);
exit(-1);
}
FILE *input = fopen(argv[1], "r");
int debug = (argc > 4 ? strcmp("debug", argv[4]) == 0 : 0);
int size = atoi(argv[1]);
float *vector = init(size);
float size_of = size * sizeof(float);
float mega_byte = 1024 * 1024;
block_size = atoi(argv[3]);
printf("%f MBytes\n", (size_of / mega_byte));
if(strncmp(argv[2], "s", 1) == 0) {
float sum = scan_seq(vector, size, debug);
printf("Sum: %f\n", sum);
} else {
float sum = scan(vector, block_size, size, argv[2], debug);
printf("Sum: %f\n", sum);
}
return 0;
}
int calculate_grid_size(int tile_size, int size) {
int div = size / tile_size;
int remainder = size - (tile_size * div);
if(remainder > 0) {
div++;
}
return div;
}
float scan(float *input, int tile_size, int size, char *algorithm, int debug) {
int dim_grid = calculate_grid_size(tile_size, size);
float *device_input;
FILE *f = NULL;
size_t size_bytes = size * sizeof(float);
size_t block_size_bytes = tile_size * sizeof(float);
CUDA_CHECK_RETURN(cudaMalloc((void **) &device_input, size_bytes));
CUDA_CHECK_RETURN(cudaMemcpy(device_input, input, size_bytes, cudaMemcpyHostToDevice));
if(strlen(algorithm) == 1 && strncmp(algorithm, "c", 1) == 0) {
scan_kernel <<<dim_grid, tile_size>>> (device_input, size);
if(debug) {
f = fopen("saida_c.txt", "w");
}
} else {
scan_kernel_coalesc <<<dim_grid, tile_size, block_size_bytes>>> (device_input, size);
if(debug) {
f = fopen("saida_cc.txt", "w");
}
}
CUDA_CHECK_RETURN(cudaGetLastError());
CUDA_CHECK_RETURN(cudaMemcpy(input, device_input, size_bytes, cudaMemcpyDeviceToHost));
CUDA_CHECK_RETURN(cudaFree(device_input));
// Percorro as bordas dos blocos para pegar o menor
int index = 0;
float sum = 0;
float sum1 = 0.0, sum2 = 0.0;
int half_dim_grid = dim_grid / 2;
if(debug) {
fprint_mat(f, input, size);
fclose(f);
}
// Soma as bordas, soma a metade para evitar de perder precisao
for(int i = 1; i < half_dim_grid; ++i) {
index = (tile_size * i) - 1;
sum1 += input[index];
}
for(int i = half_dim_grid; i < dim_grid; ++i) {
index = (tile_size * i) - 1;
sum2 += input[index];
}
sum = sum1;
if((size) != index) {
sum += input[size - 1];
}
sum += sum2;
return sum;
}
float scan_seq(float *input, int size, int debug) {
float found = 0;
for(int i = 0; i < size; ++i) {
found += input[i];
}
if(debug) {
FILE *f = fopen("saida_s.txt", "w");
fprint_mat(f, input, size);
fclose(f);
}
return found;
}
void fprint_mat(FILE *f, float *v, int n) {
for(int i = 0; i < n-1; i++) {
fprintf(f, "%f ", v[i]);
}
fprintf(f, "%f", v[n-1]);
}
float* init(int n) {
float *v = (float*) malloc(sizeof(float) * n);
for(int i = 0; i < n; ++i) {
v[i] = (float) i;
}
return v;
}
////////////////////////////////////////////////////////////////////////////////
/***
* Esse Scan é feito apenas no interior do bloco, logo quem chamou ele precisa verificar
* os limites dos blocos para pegar o menor valor
*/
__global__
void scan_kernel(float *input, int size) {
int local_block_dim = blockDim.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int ti_bi = ti - bi; // ti - bi evita que a thread saia do limite do bloco.
int local_size = size;
float aux = 0;
int offset = 1;
// Algoritmo do Scan em cima das posições e threads relativas ao bloco
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(ti_bi >= offset && ti < local_size) {
aux = input[ti - offset];
}
__syncthreads();
if(ti_bi >= offset && ti < local_size) {
input[ti] = aux + input[ti];
}
__syncthreads();
}
}
__global__
void scan_kernel_coalesc(float *input, int size) {
int local_block_dim = blockDim.x;
int thread_id = threadIdx.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int local_size = size;
float aux = 0;
int offset = 1;
extern __shared__ float local[];
// Carrega o valor relativo a thread para a memória local.
if(ti < local_size) {
local[thread_id] = input[ti];
}
__syncthreads();
// Aplica o Scan em cima da memória local
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(thread_id >= offset && thread_id < local_block_dim) {
aux = local[thread_id - offset];
}
__syncthreads();
if(thread_id >= offset && thread_id < local_block_dim) {
local[thread_id] = aux + local[thread_id];
}
__syncthreads();
}
// Volta com o valor local na memória global
input[ti] = local[thread_id];
} | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} \
}
float scan_seq(float *, int, int);
int calculate_grid_size(int, int);
float scan(float*, int, int, char*, int);
void fprint_mat(FILE *, float *, int);
float* init(int);
__global__ void scan_kernel(float *, int);
__global__ void scan_kernel_coalesc(float *, int);
int block_size;
int main(int argc, char **argv) {
if(argc < 4) {
printf("usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\n\
algoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n", argv[0]);
exit(-1);
}
FILE *input = fopen(argv[1], "r");
int debug = (argc > 4 ? strcmp("debug", argv[4]) == 0 : 0);
int size = atoi(argv[1]);
float *vector = init(size);
float size_of = size * sizeof(float);
float mega_byte = 1024 * 1024;
block_size = atoi(argv[3]);
printf("%f MBytes\n", (size_of / mega_byte));
if(strncmp(argv[2], "s", 1) == 0) {
float sum = scan_seq(vector, size, debug);
printf("Sum: %f\n", sum);
} else {
float sum = scan(vector, block_size, size, argv[2], debug);
printf("Sum: %f\n", sum);
}
return 0;
}
int calculate_grid_size(int tile_size, int size) {
int div = size / tile_size;
int remainder = size - (tile_size * div);
if(remainder > 0) {
div++;
}
return div;
}
float scan(float *input, int tile_size, int size, char *algorithm, int debug) {
int dim_grid = calculate_grid_size(tile_size, size);
float *device_input;
FILE *f = NULL;
size_t size_bytes = size * sizeof(float);
size_t block_size_bytes = tile_size * sizeof(float);
CUDA_CHECK_RETURN(hipMalloc((void **) &device_input, size_bytes));
CUDA_CHECK_RETURN(hipMemcpy(device_input, input, size_bytes, hipMemcpyHostToDevice));
if(strlen(algorithm) == 1 && strncmp(algorithm, "c", 1) == 0) {
scan_kernel <<<dim_grid, tile_size>>> (device_input, size);
if(debug) {
f = fopen("saida_c.txt", "w");
}
} else {
scan_kernel_coalesc <<<dim_grid, tile_size, block_size_bytes>>> (device_input, size);
if(debug) {
f = fopen("saida_cc.txt", "w");
}
}
CUDA_CHECK_RETURN(hipGetLastError());
CUDA_CHECK_RETURN(hipMemcpy(input, device_input, size_bytes, hipMemcpyDeviceToHost));
CUDA_CHECK_RETURN(hipFree(device_input));
// Percorro as bordas dos blocos para pegar o menor
int index = 0;
float sum = 0;
float sum1 = 0.0, sum2 = 0.0;
int half_dim_grid = dim_grid / 2;
if(debug) {
fprint_mat(f, input, size);
fclose(f);
}
// Soma as bordas, soma a metade para evitar de perder precisao
for(int i = 1; i < half_dim_grid; ++i) {
index = (tile_size * i) - 1;
sum1 += input[index];
}
for(int i = half_dim_grid; i < dim_grid; ++i) {
index = (tile_size * i) - 1;
sum2 += input[index];
}
sum = sum1;
if((size) != index) {
sum += input[size - 1];
}
sum += sum2;
return sum;
}
float scan_seq(float *input, int size, int debug) {
float found = 0;
for(int i = 0; i < size; ++i) {
found += input[i];
}
if(debug) {
FILE *f = fopen("saida_s.txt", "w");
fprint_mat(f, input, size);
fclose(f);
}
return found;
}
void fprint_mat(FILE *f, float *v, int n) {
for(int i = 0; i < n-1; i++) {
fprintf(f, "%f ", v[i]);
}
fprintf(f, "%f", v[n-1]);
}
float* init(int n) {
float *v = (float*) malloc(sizeof(float) * n);
for(int i = 0; i < n; ++i) {
v[i] = (float) i;
}
return v;
}
////////////////////////////////////////////////////////////////////////////////
/***
* Esse Scan é feito apenas no interior do bloco, logo quem chamou ele precisa verificar
* os limites dos blocos para pegar o menor valor
*/
__global__
void scan_kernel(float *input, int size) {
int local_block_dim = blockDim.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int ti_bi = ti - bi; // ti - bi evita que a thread saia do limite do bloco.
int local_size = size;
float aux = 0;
int offset = 1;
// Algoritmo do Scan em cima das posições e threads relativas ao bloco
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(ti_bi >= offset && ti < local_size) {
aux = input[ti - offset];
}
__syncthreads();
if(ti_bi >= offset && ti < local_size) {
input[ti] = aux + input[ti];
}
__syncthreads();
}
}
__global__
void scan_kernel_coalesc(float *input, int size) {
int local_block_dim = blockDim.x;
int thread_id = threadIdx.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int local_size = size;
float aux = 0;
int offset = 1;
extern __shared__ float local[];
// Carrega o valor relativo a thread para a memória local.
if(ti < local_size) {
local[thread_id] = input[ti];
}
__syncthreads();
// Aplica o Scan em cima da memória local
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(thread_id >= offset && thread_id < local_block_dim) {
aux = local[thread_id - offset];
}
__syncthreads();
if(thread_id >= offset && thread_id < local_block_dim) {
local[thread_id] = aux + local[thread_id];
}
__syncthreads();
}
// Volta com o valor local na memória global
input[ti] = local[thread_id];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} \
}
float scan_seq(float *, int, int);
int calculate_grid_size(int, int);
float scan(float*, int, int, char*, int);
void fprint_mat(FILE *, float *, int);
float* init(int);
__global__ void scan_kernel(float *, int);
__global__ void scan_kernel_coalesc(float *, int);
int block_size;
int main(int argc, char **argv) {
if(argc < 4) {
printf("usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\n\
algoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n", argv[0]);
exit(-1);
}
FILE *input = fopen(argv[1], "r");
int debug = (argc > 4 ? strcmp("debug", argv[4]) == 0 : 0);
int size = atoi(argv[1]);
float *vector = init(size);
float size_of = size * sizeof(float);
float mega_byte = 1024 * 1024;
block_size = atoi(argv[3]);
printf("%f MBytes\n", (size_of / mega_byte));
if(strncmp(argv[2], "s", 1) == 0) {
float sum = scan_seq(vector, size, debug);
printf("Sum: %f\n", sum);
} else {
float sum = scan(vector, block_size, size, argv[2], debug);
printf("Sum: %f\n", sum);
}
return 0;
}
int calculate_grid_size(int tile_size, int size) {
int div = size / tile_size;
int remainder = size - (tile_size * div);
if(remainder > 0) {
div++;
}
return div;
}
float scan(float *input, int tile_size, int size, char *algorithm, int debug) {
int dim_grid = calculate_grid_size(tile_size, size);
float *device_input;
FILE *f = NULL;
size_t size_bytes = size * sizeof(float);
size_t block_size_bytes = tile_size * sizeof(float);
CUDA_CHECK_RETURN(hipMalloc((void **) &device_input, size_bytes));
CUDA_CHECK_RETURN(hipMemcpy(device_input, input, size_bytes, hipMemcpyHostToDevice));
if(strlen(algorithm) == 1 && strncmp(algorithm, "c", 1) == 0) {
scan_kernel <<<dim_grid, tile_size>>> (device_input, size);
if(debug) {
f = fopen("saida_c.txt", "w");
}
} else {
scan_kernel_coalesc <<<dim_grid, tile_size, block_size_bytes>>> (device_input, size);
if(debug) {
f = fopen("saida_cc.txt", "w");
}
}
CUDA_CHECK_RETURN(hipGetLastError());
CUDA_CHECK_RETURN(hipMemcpy(input, device_input, size_bytes, hipMemcpyDeviceToHost));
CUDA_CHECK_RETURN(hipFree(device_input));
// Percorro as bordas dos blocos para pegar o menor
int index = 0;
float sum = 0;
float sum1 = 0.0, sum2 = 0.0;
int half_dim_grid = dim_grid / 2;
if(debug) {
fprint_mat(f, input, size);
fclose(f);
}
// Soma as bordas, soma a metade para evitar de perder precisao
for(int i = 1; i < half_dim_grid; ++i) {
index = (tile_size * i) - 1;
sum1 += input[index];
}
for(int i = half_dim_grid; i < dim_grid; ++i) {
index = (tile_size * i) - 1;
sum2 += input[index];
}
sum = sum1;
if((size) != index) {
sum += input[size - 1];
}
sum += sum2;
return sum;
}
float scan_seq(float *input, int size, int debug) {
float found = 0;
for(int i = 0; i < size; ++i) {
found += input[i];
}
if(debug) {
FILE *f = fopen("saida_s.txt", "w");
fprint_mat(f, input, size);
fclose(f);
}
return found;
}
void fprint_mat(FILE *f, float *v, int n) {
for(int i = 0; i < n-1; i++) {
fprintf(f, "%f ", v[i]);
}
fprintf(f, "%f", v[n-1]);
}
float* init(int n) {
float *v = (float*) malloc(sizeof(float) * n);
for(int i = 0; i < n; ++i) {
v[i] = (float) i;
}
return v;
}
////////////////////////////////////////////////////////////////////////////////
/***
* Esse Scan é feito apenas no interior do bloco, logo quem chamou ele precisa verificar
* os limites dos blocos para pegar o menor valor
*/
__global__
void scan_kernel(float *input, int size) {
int local_block_dim = blockDim.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int ti_bi = ti - bi; // ti - bi evita que a thread saia do limite do bloco.
int local_size = size;
float aux = 0;
int offset = 1;
// Algoritmo do Scan em cima das posições e threads relativas ao bloco
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(ti_bi >= offset && ti < local_size) {
aux = input[ti - offset];
}
__syncthreads();
if(ti_bi >= offset && ti < local_size) {
input[ti] = aux + input[ti];
}
__syncthreads();
}
}
__global__
void scan_kernel_coalesc(float *input, int size) {
int local_block_dim = blockDim.x;
int thread_id = threadIdx.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int local_size = size;
float aux = 0;
int offset = 1;
extern __shared__ float local[];
// Carrega o valor relativo a thread para a memória local.
if(ti < local_size) {
local[thread_id] = input[ti];
}
__syncthreads();
// Aplica o Scan em cima da memória local
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(thread_id >= offset && thread_id < local_block_dim) {
aux = local[thread_id - offset];
}
__syncthreads();
if(thread_id >= offset && thread_id < local_block_dim) {
local[thread_id] = aux + local[thread_id];
}
__syncthreads();
}
// Volta com o valor local na memória global
input[ti] = local[thread_id];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11scan_kernelPfi
.globl _Z11scan_kernelPfi
.p2align 8
.type _Z11scan_kernelPfi,@function
_Z11scan_kernelPfi:
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s2, s4, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_and_b32 s1, 0xffff, s4
v_mov_b32_e32 v4, 0
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
s_mov_b32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s4, s4, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s4, s1
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_3:
v_cmp_le_u32_e64 s0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, vcc_lo, s0
s_and_saveexec_b32 s6, s5
s_cbranch_execz .LBB0_5
v_subrev_nc_u32_e32 v4, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v4
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
global_load_b32 v4, v[4:5], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s5
s_cbranch_execz .LBB0_2
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v4, v5
global_store_b32 v[2:3], v5, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11scan_kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11scan_kernelPfi, .Lfunc_end0-_Z11scan_kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19scan_kernel_coalescPfi
.globl _Z19scan_kernel_coalescPfi
.p2align 8
.type _Z19scan_kernel_coalescPfi,@function
_Z19scan_kernel_coalescPfi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshl_add_u32 v4, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_lt_u32 s1, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_9
v_cmp_gt_u32_e32 vcc_lo, s1, v0
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s4, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s4, s1
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_9
.LBB1_5:
v_cmp_le_u32_e64 s0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s5, s0
s_cbranch_execz .LBB1_7
v_subrev_nc_u32_e32 v4, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v4, v4
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s5, s0
s_cbranch_execz .LBB1_4
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v4, v5
ds_store_b32 v3, v5
s_branch .LBB1_4
.LBB1_9:
s_set_inst_prefetch_distance 0x2
v_lshl_add_u32 v0, v0, 2, 0
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19scan_kernel_coalescPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19scan_kernel_coalescPfi, .Lfunc_end1-_Z19scan_kernel_coalescPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11scan_kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11scan_kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19scan_kernel_coalescPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19scan_kernel_coalescPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} \
}
float scan_seq(float *, int, int);
int calculate_grid_size(int, int);
float scan(float*, int, int, char*, int);
void fprint_mat(FILE *, float *, int);
float* init(int);
__global__ void scan_kernel(float *, int);
__global__ void scan_kernel_coalesc(float *, int);
int block_size;
int main(int argc, char **argv) {
if(argc < 4) {
printf("usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\n\
algoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n", argv[0]);
exit(-1);
}
FILE *input = fopen(argv[1], "r");
int debug = (argc > 4 ? strcmp("debug", argv[4]) == 0 : 0);
int size = atoi(argv[1]);
float *vector = init(size);
float size_of = size * sizeof(float);
float mega_byte = 1024 * 1024;
block_size = atoi(argv[3]);
printf("%f MBytes\n", (size_of / mega_byte));
if(strncmp(argv[2], "s", 1) == 0) {
float sum = scan_seq(vector, size, debug);
printf("Sum: %f\n", sum);
} else {
float sum = scan(vector, block_size, size, argv[2], debug);
printf("Sum: %f\n", sum);
}
return 0;
}
int calculate_grid_size(int tile_size, int size) {
int div = size / tile_size;
int remainder = size - (tile_size * div);
if(remainder > 0) {
div++;
}
return div;
}
float scan(float *input, int tile_size, int size, char *algorithm, int debug) {
int dim_grid = calculate_grid_size(tile_size, size);
float *device_input;
FILE *f = NULL;
size_t size_bytes = size * sizeof(float);
size_t block_size_bytes = tile_size * sizeof(float);
CUDA_CHECK_RETURN(hipMalloc((void **) &device_input, size_bytes));
CUDA_CHECK_RETURN(hipMemcpy(device_input, input, size_bytes, hipMemcpyHostToDevice));
if(strlen(algorithm) == 1 && strncmp(algorithm, "c", 1) == 0) {
scan_kernel <<<dim_grid, tile_size>>> (device_input, size);
if(debug) {
f = fopen("saida_c.txt", "w");
}
} else {
scan_kernel_coalesc <<<dim_grid, tile_size, block_size_bytes>>> (device_input, size);
if(debug) {
f = fopen("saida_cc.txt", "w");
}
}
CUDA_CHECK_RETURN(hipGetLastError());
CUDA_CHECK_RETURN(hipMemcpy(input, device_input, size_bytes, hipMemcpyDeviceToHost));
CUDA_CHECK_RETURN(hipFree(device_input));
// Percorro as bordas dos blocos para pegar o menor
int index = 0;
float sum = 0;
float sum1 = 0.0, sum2 = 0.0;
int half_dim_grid = dim_grid / 2;
if(debug) {
fprint_mat(f, input, size);
fclose(f);
}
// Soma as bordas, soma a metade para evitar de perder precisao
for(int i = 1; i < half_dim_grid; ++i) {
index = (tile_size * i) - 1;
sum1 += input[index];
}
for(int i = half_dim_grid; i < dim_grid; ++i) {
index = (tile_size * i) - 1;
sum2 += input[index];
}
sum = sum1;
if((size) != index) {
sum += input[size - 1];
}
sum += sum2;
return sum;
}
float scan_seq(float *input, int size, int debug) {
float found = 0;
for(int i = 0; i < size; ++i) {
found += input[i];
}
if(debug) {
FILE *f = fopen("saida_s.txt", "w");
fprint_mat(f, input, size);
fclose(f);
}
return found;
}
void fprint_mat(FILE *f, float *v, int n) {
for(int i = 0; i < n-1; i++) {
fprintf(f, "%f ", v[i]);
}
fprintf(f, "%f", v[n-1]);
}
float* init(int n) {
float *v = (float*) malloc(sizeof(float) * n);
for(int i = 0; i < n; ++i) {
v[i] = (float) i;
}
return v;
}
////////////////////////////////////////////////////////////////////////////////
/***
* Esse Scan é feito apenas no interior do bloco, logo quem chamou ele precisa verificar
* os limites dos blocos para pegar o menor valor
*/
__global__
void scan_kernel(float *input, int size) {
int local_block_dim = blockDim.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int ti_bi = ti - bi; // ti - bi evita que a thread saia do limite do bloco.
int local_size = size;
float aux = 0;
int offset = 1;
// Algoritmo do Scan em cima das posições e threads relativas ao bloco
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(ti_bi >= offset && ti < local_size) {
aux = input[ti - offset];
}
__syncthreads();
if(ti_bi >= offset && ti < local_size) {
input[ti] = aux + input[ti];
}
__syncthreads();
}
}
__global__
void scan_kernel_coalesc(float *input, int size) {
int local_block_dim = blockDim.x;
int thread_id = threadIdx.x;
int bi = local_block_dim * blockIdx.x;
int ti = bi + threadIdx.x;
int local_size = size;
float aux = 0;
int offset = 1;
extern __shared__ float local[];
// Carrega o valor relativo a thread para a memória local.
if(ti < local_size) {
local[thread_id] = input[ti];
}
__syncthreads();
// Aplica o Scan em cima da memória local
for(offset = 1; offset < local_block_dim; offset *= 2) {
if(thread_id >= offset && thread_id < local_block_dim) {
aux = local[thread_id - offset];
}
__syncthreads();
if(thread_id >= offset && thread_id < local_block_dim) {
local[thread_id] = aux + local[thread_id];
}
__syncthreads();
}
// Volta com o valor local na memória global
input[ti] = local[thread_id];
} | .text
.file "Sum.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
cmpl $3, %edi
jle .LBB0_22
# %bb.1:
movl %edi, %ebx
movq 8(%r15), %rdi
movl $.L.str.1, %esi
callq fopen
xorl %ebp, %ebp
cmpl $4, %ebx
je .LBB0_3
# %bb.2:
movq 32(%r15), %rsi
movl $.L.str.2, %edi
callq strcmp
xorl %ebp, %ebp
testl %eax, %eax
sete %bpl
.LBB0_3:
movq 8(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq %r14d, %r13
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
testl %r13d, %r13d
jle .LBB0_6
# %bb.4: # %.lr.ph.preheader.i
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_5
.LBB0_6: # %_Z4initi.exit
testq %r12, %r12
js .LBB0_7
# %bb.8: # %_Z4initi.exit
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
jmp .LBB0_9
.LBB0_7:
movq %r12, %rax
shrq %rax
andl $1, %r12d
orq %rax, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
addss %xmm0, %xmm0
.LBB0_9: # %_Z4initi.exit
movss %xmm0, (%rsp) # 4-byte Spill
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, block_size(%rip)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 16(%r15), %rcx
cmpb $115, (%rcx)
jne .LBB0_20
# %bb.10:
testl %r14d, %r14d
jle .LBB0_11
# %bb.18: # %.lr.ph.preheader.i20
movl %r14d, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_19: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
addss (%rbx,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB0_19
# %bb.12: # %._crit_edge.i.loopexit
cvtss2sd %xmm0, %xmm0
testl %ebp, %ebp
jne .LBB0_14
jmp .LBB0_21
.LBB0_20:
movl block_size(%rip), %esi
movq %rbx, %rdi
movl %r14d, %edx
movl %ebp, %r8d
callq _Z4scanPfiiPci
cvtss2sd %xmm0, %xmm0
jmp .LBB0_21
.LBB0_11:
xorps %xmm0, %xmm0
testl %ebp, %ebp
je .LBB0_21
.LBB0_14:
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.12, %edi
movl $.L.str.10, %esi
callq fopen
movq %rax, %r15
leal -1(%r14), %ebp
cmpl $2, %r14d
jl .LBB0_17
# %bb.15: # %.lr.ph.preheader.i.i
movl %ebp, %r14d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_16: # %.lr.ph.i.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r14
jne .LBB0_16
.LBB0_17: # %_Z10fprint_matP8_IO_FILEPfi.exit.i
movslq %ebp, %rax
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
movq %r15, %rdi
callq fclose
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
.LBB0_21: # %_Z8scan_seqPfii.exit
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_22:
.cfi_def_cfa_offset 64
movq (%r15), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z4initi # -- Begin function _Z4initi
.p2align 4, 0x90
.type _Z4initi,@function
_Z4initi: # @_Z4initi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movslq %edi, %r14
leaq (,%r14,4), %rdi
callq malloc
testl %r14d, %r14d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4initi, .Lfunc_end1-_Z4initi
.cfi_endproc
# -- End function
.globl _Z8scan_seqPfii # -- Begin function _Z8scan_seqPfii
.p2align 4, 0x90
.type _Z8scan_seqPfii,@function
_Z8scan_seqPfii: # @_Z8scan_seqPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r15d
movq %rdi, %rbx
testl %esi, %esi
jle .LBB2_1
# %bb.8: # %.lr.ph.preheader
movl %r15d, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rbx,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB2_9
# %bb.2: # %._crit_edge
testl %edx, %edx
jne .LBB2_3
jmp .LBB2_7
.LBB2_1:
xorps %xmm0, %xmm0
testl %edx, %edx
je .LBB2_7
.LBB2_3:
movss %xmm0, 12(%rsp) # 4-byte Spill
movl $.L.str.12, %edi
movl $.L.str.10, %esi
callq fopen
movq %rax, %r14
leal -1(%r15), %ebp
cmpl $2, %r15d
jl .LBB2_6
# %bb.4: # %.lr.ph.preheader.i
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r15
jne .LBB2_5
.LBB2_6: # %_Z10fprint_matP8_IO_FILEPfi.exit
movslq %ebp, %rax
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
movq %r14, %rdi
callq fclose
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
.LBB2_7:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8scan_seqPfii, .Lfunc_end2-_Z8scan_seqPfii
.cfi_endproc
# -- End function
.globl _Z4scanPfiiPci # -- Begin function _Z4scanPfiiPci
.p2align 4, 0x90
.type _Z4scanPfiiPci,@function
_Z4scanPfiiPci: # @_Z4scanPfiiPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 4(%rsp) # 4-byte Spill
movq %rcx, %r14
movl %edx, %ecx
movl %esi, %ebp
movq %rdi, %rbx
movl %edx, %eax
cltd
idivl %esi
movl %eax, 8(%rsp) # 4-byte Spill
imull %esi, %eax
xorl %r15d, %r15d
cmpl %ecx, %eax
setl %r12b
movq %rcx, 24(%rsp) # 8-byte Spill
movslq %ecx, %rax
movq %rax, 128(%rsp) # 8-byte Spill
leaq (,%rax,4), %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_30
# %bb.1:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_31
# %bb.2:
movb %r12b, %r15b
addl %r15d, 8(%rsp) # 4-byte Folded Spill
movslq %ebp, %rax
movq %rax, 120(%rsp) # 8-byte Spill
leaq (,%rax,4), %r15
movabsq $4294967296, %r12 # imm = 0x100000000
movq %r14, %rdi
callq strlen
cmpq $1, %rax
jne .LBB3_9
# %bb.3:
cmpb $99, (%r14)
jne .LBB3_9
# %bb.4:
movl 8(%rsp), %edi # 4-byte Reload
orq %r12, %rdi
movl %ebp, %edx
orq %r12, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11scan_kernelPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movl $.L.str.9, %edi
jmp .LBB3_7
.LBB3_9:
movl 8(%rsp), %edi # 4-byte Reload
orq %r12, %rdi
movl %ebp, %edx
orq %r12, %rdx
movl $1, %esi
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19scan_kernel_coalescPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
movl $.L.str.11, %edi
.LBB3_7:
movl 4(%rsp), %r12d # 4-byte Reload
testl %r12d, %r12d
je .LBB3_8
# %bb.12: # %.sink.split
movl $.L.str.10, %esi
callq fopen
movq %rax, %r14
jmp .LBB3_13
.LBB3_8:
xorl %r14d, %r14d
.LBB3_13:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_32
# %bb.14:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_33
# %bb.15:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_34
# %bb.16:
movl 8(%rsp), %esi # 4-byte Reload
movl %esi, %edi
shrl $31, %edi
addl %esi, %edi
testl %r12d, %r12d
je .LBB3_21
# %bb.17:
movl %edi, 92(%rsp) # 4-byte Spill
movq 24(%rsp), %rax # 8-byte Reload
leal -1(%rax), %ecx
movl %ecx, 4(%rsp) # 4-byte Spill
cmpl $2, %eax
movq %rbx, %r13
jl .LBB3_20
# %bb.18: # %.lr.ph.preheader.i
movl 4(%rsp), %r12d # 4-byte Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_19: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %rbx
cmpq %rbx, %r12
jne .LBB3_19
.LBB3_20: # %_Z10fprint_matP8_IO_FILEPfi.exit
movslq 4(%rsp), %rax # 4-byte Folded Reload
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
movq %r14, %rdi
callq fclose
movq %r13, %rbx
movl 8(%rsp), %esi # 4-byte Reload
movl 92(%rsp), %edi # 4-byte Reload
.LBB3_21:
sarl %edi
xorps %xmm0, %xmm0
xorl %eax, %eax
xorps %xmm1, %xmm1
cmpl $4, %esi
jl .LBB3_24
# %bb.22: # %.lr.ph.preheader
cmpl $3, %edi
movl $2, %ecx
cmovgel %edi, %ecx
movq 120(%rsp), %rax # 8-byte Reload
leaq (%rbx,%rax,4), %rdx
addq $-4, %rdx
decq %rcx
movl $-1, %eax
.p2align 4, 0x90
.LBB3_23: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rdx), %xmm1
addl %ebp, %eax
addq %r15, %rdx
decq %rcx
jne .LBB3_23
.LBB3_24: # %.preheader
cmpl %esi, %edi
jge .LBB3_27
# %bb.25: # %.lr.ph110.preheader
movslq %edi, %rax
movslq %esi, %rcx
decl %edi
imull %ebp, %edi
decl %edi
movq 120(%rsp), %rdx # 8-byte Reload
imulq %rax, %rdx
leaq (%rbx,%rdx,4), %rdx
addq $-4, %rdx
subq %rax, %rcx
xorps %xmm0, %xmm0
movl %edi, %eax
.p2align 4, 0x90
.LBB3_26: # %.lr.ph110
# =>This Inner Loop Header: Depth=1
addss (%rdx), %xmm0
addl %ebp, %eax
addq %r15, %rdx
decq %rcx
jne .LBB3_26
.LBB3_27: # %._crit_edge
cmpl 24(%rsp), %eax # 4-byte Folded Reload
je .LBB3_29
# %bb.28:
movq 128(%rsp), %rax # 8-byte Reload
addss -4(%rbx,%rax,4), %xmm1
.LBB3_29:
addss %xmm1, %xmm0
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_30:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %ecx
jmp .LBB3_35
.LBB3_31:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $90, %ecx
jmp .LBB3_35
.LBB3_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $104, %ecx
jmp .LBB3_35
.LBB3_33:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $106, %ecx
jmp .LBB3_35
.LBB3_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %ecx
.LBB3_35:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z4scanPfiiPci, .Lfunc_end3-_Z4scanPfiiPci
.cfi_endproc
# -- End function
.globl _Z19calculate_grid_sizeii # -- Begin function _Z19calculate_grid_sizeii
.p2align 4, 0x90
.type _Z19calculate_grid_sizeii,@function
_Z19calculate_grid_sizeii: # @_Z19calculate_grid_sizeii
.cfi_startproc
# %bb.0:
movl %esi, %eax
cltd
idivl %edi
imull %eax, %edi
xorl %ecx, %ecx
cmpl %esi, %edi
setl %cl
addl %ecx, %eax
retq
.Lfunc_end4:
.size _Z19calculate_grid_sizeii, .Lfunc_end4-_Z19calculate_grid_sizeii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__scan_kernelPfi # -- Begin function _Z26__device_stub__scan_kernelPfi
.p2align 4, 0x90
.type _Z26__device_stub__scan_kernelPfi,@function
_Z26__device_stub__scan_kernelPfi: # @_Z26__device_stub__scan_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11scan_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z26__device_stub__scan_kernelPfi, .Lfunc_end5-_Z26__device_stub__scan_kernelPfi
.cfi_endproc
# -- End function
.globl _Z34__device_stub__scan_kernel_coalescPfi # -- Begin function _Z34__device_stub__scan_kernel_coalescPfi
.p2align 4, 0x90
.type _Z34__device_stub__scan_kernel_coalescPfi,@function
_Z34__device_stub__scan_kernel_coalescPfi: # @_Z34__device_stub__scan_kernel_coalescPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19scan_kernel_coalescPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z34__device_stub__scan_kernel_coalescPfi, .Lfunc_end6-_Z34__device_stub__scan_kernel_coalescPfi
.cfi_endproc
# -- End function
.globl _Z10fprint_matP8_IO_FILEPfi # -- Begin function _Z10fprint_matP8_IO_FILEPfi
.p2align 4, 0x90
.type _Z10fprint_matP8_IO_FILEPfi,@function
_Z10fprint_matP8_IO_FILEPfi: # @_Z10fprint_matP8_IO_FILEPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rsi, %r14
movq %rdi, %rbx
leal -1(%rdx), %ebp
cmpl $2, %edx
jl .LBB7_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r15
jne .LBB7_2
.LBB7_3: # %._crit_edge
movslq %ebp, %rax
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %esi
movq %rbx, %rdi
movb $1, %al
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fprintf # TAILCALL
.Lfunc_end7:
.size _Z10fprint_matP8_IO_FILEPfi, .Lfunc_end7-_Z10fprint_matP8_IO_FILEPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11scan_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19scan_kernel_coalescPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type block_size,@object # @block_size
.bss
.globl block_size
.p2align 2, 0x0
block_size:
.long 0 # 0x0
.size block_size, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\nalgoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n"
.size .L.str, 148
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "debug"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f MBytes\n"
.size .L.str.3, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Sum: %f\n"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/wakim/prog-gpu-cuda/master/Sum/src/Sum.hip"
.size .L.str.7, 100
.type _Z11scan_kernelPfi,@object # @_Z11scan_kernelPfi
.section .rodata,"a",@progbits
.globl _Z11scan_kernelPfi
.p2align 3, 0x0
_Z11scan_kernelPfi:
.quad _Z26__device_stub__scan_kernelPfi
.size _Z11scan_kernelPfi, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "saida_c.txt"
.size .L.str.9, 12
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "w"
.size .L.str.10, 2
.type _Z19scan_kernel_coalescPfi,@object # @_Z19scan_kernel_coalescPfi
.section .rodata,"a",@progbits
.globl _Z19scan_kernel_coalescPfi
.p2align 3, 0x0
_Z19scan_kernel_coalescPfi:
.quad _Z34__device_stub__scan_kernel_coalescPfi
.size _Z19scan_kernel_coalescPfi, 8
.type .L.str.11,@object # @.str.11
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.11:
.asciz "saida_cc.txt"
.size .L.str.11, 13
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "saida_s.txt"
.size .L.str.12, 12
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%f "
.size .L.str.13, 4
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%f"
.size .L.str.14, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11scan_kernelPfi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19scan_kernel_coalescPfi"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__scan_kernelPfi
.addrsig_sym _Z34__device_stub__scan_kernel_coalescPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11scan_kernelPfi
.addrsig_sym _Z19scan_kernel_coalescPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19scan_kernel_coalescPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0060*/ BSSY B0, 0xf0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0070*/ ISETP.GT.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f24270 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R9 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0209 */
/*0090*/ ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x040fe20003f06270 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0203 */
/*00b0*/ @P0 BRA 0xe0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STS [R9.X4], R0 ; /* 0x0000000009007388 */
/* 0x0041e40000004800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ @!P1 BRA 0x1f0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0110*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fca00078e00ff */
/*0130*/ ISETP.GE.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fc80003f06270 */
/*0140*/ ISETP.LT.AND P0, PT, R9, c[0x0][0x0], P0 ; /* 0x0000000009007a0c */
/* 0x000fda0000701270 */
/*0150*/ @P0 IADD3 R5, R9, -R4, RZ ; /* 0x8000000409050210 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047824 */
/* 0x000fc800078e00ff */
/*0170*/ @P0 LDS R0, [R5.X4] ; /* 0x0000000005000984 */
/* 0x000fe80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P0 LDS R7, [R9.X4] ; /* 0x0000000009070984 */
/* 0x000e240000004800 */
/*01a0*/ @P0 FADD R7, R0, R7 ; /* 0x0000000700070221 */
/* 0x001fca0000000000 */
/*01b0*/ @P0 STS [R9.X4], R7 ; /* 0x0000000709000388 */
/* 0x0001e80000004800 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 BRA 0x130 ; /* 0xffffff4000008947 */
/* 0x001fea000383ffff */
/*01f0*/ LDS R5, [R9.X4] ; /* 0x0000000009057984 */
/* 0x000e680000004800 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11scan_kernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fe20000000f00 */
/*0080*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R8 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0208 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*00c0*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fc80003f06270 */
/*00d0*/ ISETP.LT.AND P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000701270 */
/*00e0*/ @P0 MOV R5, 0x4 ; /* 0x0000000400050802 */
/* 0x000fe20000000f00 */
/*00f0*/ @P0 IMAD.IADD R4, R0, 0x1, -R7 ; /* 0x0000000100040824 */
/* 0x000fc800078e0a07 */
/*0100*/ @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004040625 */
/* 0x000fca00078e0205 */
/*0110*/ @P0 LDG.E R6, [R4.64] ; /* 0x0000000404060981 */
/* 0x000ea8000c1e1900 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P0 LDG.E R9, [R2.64] ; /* 0x0000000402090981 */
/* 0x000ea2000c1e1900 */
/*0140*/ SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107077819 */
/* 0x000fe200000006ff */
/*0150*/ @P0 FADD R9, R6, R9 ; /* 0x0000000906090221 */
/* 0x004fca0000000000 */
/*0160*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0001e8000c101904 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f06270 */
/*0190*/ @!P0 BRA 0xc0 ; /* 0xffffff2000008947 */
/* 0x001fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11scan_kernelPfi
.globl _Z11scan_kernelPfi
.p2align 8
.type _Z11scan_kernelPfi,@function
_Z11scan_kernelPfi:
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s2, s4, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_and_b32 s1, 0xffff, s4
v_mov_b32_e32 v4, 0
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
s_mov_b32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s4, s4, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s4, s1
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_3:
v_cmp_le_u32_e64 s0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, vcc_lo, s0
s_and_saveexec_b32 s6, s5
s_cbranch_execz .LBB0_5
v_subrev_nc_u32_e32 v4, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v4
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
global_load_b32 v4, v[4:5], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s5
s_cbranch_execz .LBB0_2
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v4, v5
global_store_b32 v[2:3], v5, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11scan_kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11scan_kernelPfi, .Lfunc_end0-_Z11scan_kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19scan_kernel_coalescPfi
.globl _Z19scan_kernel_coalescPfi
.p2align 8
.type _Z19scan_kernel_coalescPfi,@function
_Z19scan_kernel_coalescPfi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshl_add_u32 v4, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_lt_u32 s1, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_9
v_cmp_gt_u32_e32 vcc_lo, s1, v0
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s4, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s4, s1
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_9
.LBB1_5:
v_cmp_le_u32_e64 s0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s5, s0
s_cbranch_execz .LBB1_7
v_subrev_nc_u32_e32 v4, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v4, v4
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s5, s0
s_cbranch_execz .LBB1_4
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v4, v5
ds_store_b32 v3, v5
s_branch .LBB1_4
.LBB1_9:
s_set_inst_prefetch_distance 0x2
v_lshl_add_u32 v0, v0, 2, 0
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19scan_kernel_coalescPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19scan_kernel_coalescPfi, .Lfunc_end1-_Z19scan_kernel_coalescPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11scan_kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11scan_kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19scan_kernel_coalescPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19scan_kernel_coalescPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fe07a_00000000-6_Sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19calculate_grid_sizeii
.type _Z19calculate_grid_sizeii, @function
_Z19calculate_grid_sizeii:
.LFB2058:
.cfi_startproc
endbr64
movl %esi, %eax
cltd
idivl %edi
testl %edx, %edx
setg %dl
movzbl %dl, %edx
addl %edx, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z19calculate_grid_sizeii, .-_Z19calculate_grid_sizeii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "%f"
.text
.globl _Z10fprint_matP8_IO_FILEPfi
.type _Z10fprint_matP8_IO_FILEPfi, @function
_Z10fprint_matP8_IO_FILEPfi:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r15
movl %edx, %r14d
cmpl $1, %edx
jle .L6
movq %rsi, %rbx
leal -2(%rdx), %eax
leaq 4(%rsi,%rax,4), %r13
leaq .LC0(%rip), %r12
.L7:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L7
.L6:
movslq %r14d, %r14
pxor %xmm0, %xmm0
cvtss2sd -4(%r15,%r14,4), %xmm0
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z10fprint_matP8_IO_FILEPfi, .-_Z10fprint_matP8_IO_FILEPfi
.section .rodata.str1.1
.LC3:
.string "w"
.LC4:
.string "saida_s.txt"
.text
.globl _Z8scan_seqPfii
.type _Z8scan_seqPfii, @function
_Z8scan_seqPfii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
testl %esi, %esi
jle .L14
movq %rdi, %rax
movslq %esi, %rcx
leaq (%rdi,%rcx,4), %rcx
movl $0x00000000, %ebx
.L12:
movd %ebx, %xmm1
addss (%rax), %xmm1
movd %xmm1, %ebx
addq $4, %rax
cmpq %rcx, %rax
jne .L12
.L11:
testl %edx, %edx
jne .L17
.L10:
movd %ebx, %xmm0
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl $0x00000000, %ebx
jmp .L11
.L17:
leaq .LC3(%rip), %rsi
leaq .LC4(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl %ebp, %edx
movq %r12, %rsi
movq %rax, %rdi
call _Z10fprint_matP8_IO_FILEPfi
movq %r13, %rdi
call fclose@PLT
jmp .L10
.cfi_endproc
.LFE2060:
.size _Z8scan_seqPfii, .-_Z8scan_seqPfii
.globl _Z4initi
.type _Z4initi, @function
_Z4initi:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebp
movslq %edi, %rbx
leaq 0(,%rbx,4), %rdi
call malloc@PLT
testl %ebp, %ebp
jle .L18
movl $0, %edx
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rax,%rdx,4)
addq $1, %rdx
cmpq %rdx, %rbx
jne .L20
.L18:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z4initi, .-_Z4initi
.globl _Z32__device_stub__Z11scan_kernelPfiPfi
.type _Z32__device_stub__Z11scan_kernelPfiPfi, @function
_Z32__device_stub__Z11scan_kernelPfiPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11scan_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z32__device_stub__Z11scan_kernelPfiPfi, .-_Z32__device_stub__Z11scan_kernelPfiPfi
.globl _Z11scan_kernelPfi
.type _Z11scan_kernelPfi, @function
_Z11scan_kernelPfi:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11scan_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z11scan_kernelPfi, .-_Z11scan_kernelPfi
.globl _Z40__device_stub__Z19scan_kernel_coalescPfiPfi
.type _Z40__device_stub__Z19scan_kernel_coalescPfiPfi, @function
_Z40__device_stub__Z19scan_kernel_coalescPfiPfi:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19scan_kernel_coalescPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z40__device_stub__Z19scan_kernel_coalescPfiPfi, .-_Z40__device_stub__Z19scan_kernel_coalescPfiPfi
.globl _Z19scan_kernel_coalescPfi
.type _Z19scan_kernel_coalescPfi, @function
_Z19scan_kernel_coalescPfi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19scan_kernel_coalescPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z19scan_kernel_coalescPfi, .-_Z19scan_kernel_coalescPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/wakim/prog-gpu-cuda/master/Sum/src/Sum.cu"
.align 8
.LC6:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1
.LC7:
.string "saida_c.txt"
.LC8:
.string "saida_cc.txt"
.text
.globl _Z4scanPfiiPci
.type _Z4scanPfiiPci, @function
_Z4scanPfiiPci:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movl %esi, %r13d
movl %edx, %ebx
movl %edx, 4(%rsp)
movq %rcx, %rbp
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edx, %esi
movl %r13d, %edi
call _Z19calculate_grid_sizeii
movl %eax, %r12d
movslq %ebx, %r15
salq $2, %r15
movslq %r13d, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L63
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L64
movq %rbp, %rdi
call strlen@PLT
cmpq $1, %rax
jne .L42
cmpb $99, 0(%rbp)
je .L65
.L42:
movl %r13d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r12d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movq %rbx, %r8
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L45:
movq $0, 8(%rsp)
cmpl $0, (%rsp)
jne .L67
.L44:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L68
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L69
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L70
movl %r12d, %ebp
shrl $31, %ebp
addl %r12d, %ebp
sarl %ebp
cmpl $0, (%rsp)
jne .L71
.L49:
cmpl $3, %r12d
jle .L58
leaq (%r14,%rbx), %rdx
movl $1, %eax
pxor %xmm0, %xmm0
.L51:
addss -4(%rdx), %xmm0
addl $1, %eax
addq %rbx, %rdx
cmpl %eax, %ebp
jg .L51
leal -2(%rbp), %eax
imull %r13d, %eax
leal -1(%r13,%rax), %eax
.L50:
cmpl %ebp, %r12d
jle .L59
movl %r13d, %esi
imull %ebp, %esi
movslq %esi, %rax
leaq (%r14,%rax,4), %rdx
movl %ebp, %eax
pxor %xmm1, %xmm1
.L53:
addss -4(%rdx), %xmm1
movl %eax, %ecx
addl $1, %eax
addq %rbx, %rdx
cmpl %eax, %r12d
jne .L53
subl %ebp, %ecx
imull %r13d, %ecx
leal -1(%rsi,%rcx), %eax
.L52:
cmpl %eax, 4(%rsp)
je .L54
addss -4(%r14,%r15), %xmm0
.L54:
addss %xmm1, %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $87, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $88, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
movl %r13d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r12d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L43:
movq $0, 8(%rsp)
cmpl $0, (%rsp)
je .L44
leaq .LC3(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
jmp .L44
.L73:
movl 4(%rsp), %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z11scan_kernelPfiPfi
jmp .L43
.L66:
movl 4(%rsp), %esi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z19scan_kernel_coalescPfiPfi
jmp .L45
.L67:
leaq .LC3(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
jmp .L44
.L68:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $102, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $104, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L70:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $106, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
movl 4(%rsp), %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call _Z10fprint_matP8_IO_FILEPfi
movq 8(%rsp), %rdi
call fclose@PLT
jmp .L49
.L58:
pxor %xmm0, %xmm0
movl $0, %eax
jmp .L50
.L59:
pxor %xmm1, %xmm1
jmp .L52
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z4scanPfiiPci, .-_Z4scanPfiiPci
.section .rodata.str1.8
.align 8
.LC9:
.string "usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\nalgoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n"
.section .rodata.str1.1
.LC10:
.string "r"
.LC11:
.string "debug"
.LC13:
.string "%f MBytes\n"
.LC14:
.string "Sum: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %rbp
cmpl $3, %edi
jle .L83
movl %edi, %ebx
movq 8(%rsi), %rdi
leaq .LC10(%rip), %rsi
call fopen@PLT
movl $0, %r13d
cmpl $4, %ebx
jle .L76
movq 32(%rbp), %rsi
leaq .LC11(%rip), %rdi
call strcmp@PLT
testl %eax, %eax
sete %r13b
movzbl %r13b, %r13d
.L76:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movl %eax, %edi
call _Z4initi
movq %rax, %r12
movslq %ebx, %rbx
salq $2, %rbx
js .L77
pxor %xmm1, %xmm1
cvtsi2ssq %rbx, %xmm1
movd %xmm1, %ebx
.L78:
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, block_size(%rip)
movd %ebx, %xmm0
mulss .LC12(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rbp), %rcx
cmpb $115, (%rcx)
je .L84
movl %r13d, %r8d
movl %r14d, %edx
movl block_size(%rip), %esi
movq %r12, %rdi
call _Z4scanPfiiPci
cvtss2sd %xmm0, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L80:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L83:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L77:
shrq %rbx
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
addss %xmm0, %xmm0
movd %xmm0, %ebx
jmp .L78
.L84:
movl %r13d, %edx
movl %r14d, %esi
movq %r12, %rdi
call _Z8scan_seqPfii
cvtss2sd %xmm0, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L80
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z19scan_kernel_coalescPfi"
.LC16:
.string "_Z11scan_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z19scan_kernel_coalescPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z11scan_kernelPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl block_size
.bss
.align 4
.type block_size, @object
.size block_size, 4
block_size:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC12:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Sum.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
cmpl $3, %edi
jle .LBB0_22
# %bb.1:
movl %edi, %ebx
movq 8(%r15), %rdi
movl $.L.str.1, %esi
callq fopen
xorl %ebp, %ebp
cmpl $4, %ebx
je .LBB0_3
# %bb.2:
movq 32(%r15), %rsi
movl $.L.str.2, %edi
callq strcmp
xorl %ebp, %ebp
testl %eax, %eax
sete %bpl
.LBB0_3:
movq 8(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq %r14d, %r13
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
testl %r13d, %r13d
jle .LBB0_6
# %bb.4: # %.lr.ph.preheader.i
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_5
.LBB0_6: # %_Z4initi.exit
testq %r12, %r12
js .LBB0_7
# %bb.8: # %_Z4initi.exit
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
jmp .LBB0_9
.LBB0_7:
movq %r12, %rax
shrq %rax
andl $1, %r12d
orq %rax, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
addss %xmm0, %xmm0
.LBB0_9: # %_Z4initi.exit
movss %xmm0, (%rsp) # 4-byte Spill
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, block_size(%rip)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 16(%r15), %rcx
cmpb $115, (%rcx)
jne .LBB0_20
# %bb.10:
testl %r14d, %r14d
jle .LBB0_11
# %bb.18: # %.lr.ph.preheader.i20
movl %r14d, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_19: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
addss (%rbx,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB0_19
# %bb.12: # %._crit_edge.i.loopexit
cvtss2sd %xmm0, %xmm0
testl %ebp, %ebp
jne .LBB0_14
jmp .LBB0_21
.LBB0_20:
movl block_size(%rip), %esi
movq %rbx, %rdi
movl %r14d, %edx
movl %ebp, %r8d
callq _Z4scanPfiiPci
cvtss2sd %xmm0, %xmm0
jmp .LBB0_21
.LBB0_11:
xorps %xmm0, %xmm0
testl %ebp, %ebp
je .LBB0_21
.LBB0_14:
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.12, %edi
movl $.L.str.10, %esi
callq fopen
movq %rax, %r15
leal -1(%r14), %ebp
cmpl $2, %r14d
jl .LBB0_17
# %bb.15: # %.lr.ph.preheader.i.i
movl %ebp, %r14d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_16: # %.lr.ph.i.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r14
jne .LBB0_16
.LBB0_17: # %_Z10fprint_matP8_IO_FILEPfi.exit.i
movslq %ebp, %rax
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
movq %r15, %rdi
callq fclose
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
.LBB0_21: # %_Z8scan_seqPfii.exit
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_22:
.cfi_def_cfa_offset 64
movq (%r15), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z4initi # -- Begin function _Z4initi
.p2align 4, 0x90
.type _Z4initi,@function
_Z4initi: # @_Z4initi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movslq %edi, %r14
leaq (,%r14,4), %rdi
callq malloc
testl %r14d, %r14d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4initi, .Lfunc_end1-_Z4initi
.cfi_endproc
# -- End function
.globl _Z8scan_seqPfii # -- Begin function _Z8scan_seqPfii
.p2align 4, 0x90
.type _Z8scan_seqPfii,@function
_Z8scan_seqPfii: # @_Z8scan_seqPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r15d
movq %rdi, %rbx
testl %esi, %esi
jle .LBB2_1
# %bb.8: # %.lr.ph.preheader
movl %r15d, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rbx,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB2_9
# %bb.2: # %._crit_edge
testl %edx, %edx
jne .LBB2_3
jmp .LBB2_7
.LBB2_1:
xorps %xmm0, %xmm0
testl %edx, %edx
je .LBB2_7
.LBB2_3:
movss %xmm0, 12(%rsp) # 4-byte Spill
movl $.L.str.12, %edi
movl $.L.str.10, %esi
callq fopen
movq %rax, %r14
leal -1(%r15), %ebp
cmpl $2, %r15d
jl .LBB2_6
# %bb.4: # %.lr.ph.preheader.i
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r15
jne .LBB2_5
.LBB2_6: # %_Z10fprint_matP8_IO_FILEPfi.exit
movslq %ebp, %rax
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
movq %r14, %rdi
callq fclose
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
.LBB2_7:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8scan_seqPfii, .Lfunc_end2-_Z8scan_seqPfii
.cfi_endproc
# -- End function
.globl _Z4scanPfiiPci # -- Begin function _Z4scanPfiiPci
.p2align 4, 0x90
.type _Z4scanPfiiPci,@function
_Z4scanPfiiPci: # @_Z4scanPfiiPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 4(%rsp) # 4-byte Spill
movq %rcx, %r14
movl %edx, %ecx
movl %esi, %ebp
movq %rdi, %rbx
movl %edx, %eax
cltd
idivl %esi
movl %eax, 8(%rsp) # 4-byte Spill
imull %esi, %eax
xorl %r15d, %r15d
cmpl %ecx, %eax
setl %r12b
movq %rcx, 24(%rsp) # 8-byte Spill
movslq %ecx, %rax
movq %rax, 128(%rsp) # 8-byte Spill
leaq (,%rax,4), %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_30
# %bb.1:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_31
# %bb.2:
movb %r12b, %r15b
addl %r15d, 8(%rsp) # 4-byte Folded Spill
movslq %ebp, %rax
movq %rax, 120(%rsp) # 8-byte Spill
leaq (,%rax,4), %r15
movabsq $4294967296, %r12 # imm = 0x100000000
movq %r14, %rdi
callq strlen
cmpq $1, %rax
jne .LBB3_9
# %bb.3:
cmpb $99, (%r14)
jne .LBB3_9
# %bb.4:
movl 8(%rsp), %edi # 4-byte Reload
orq %r12, %rdi
movl %ebp, %edx
orq %r12, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11scan_kernelPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movl $.L.str.9, %edi
jmp .LBB3_7
.LBB3_9:
movl 8(%rsp), %edi # 4-byte Reload
orq %r12, %rdi
movl %ebp, %edx
orq %r12, %rdx
movl $1, %esi
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19scan_kernel_coalescPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
movl $.L.str.11, %edi
.LBB3_7:
movl 4(%rsp), %r12d # 4-byte Reload
testl %r12d, %r12d
je .LBB3_8
# %bb.12: # %.sink.split
movl $.L.str.10, %esi
callq fopen
movq %rax, %r14
jmp .LBB3_13
.LBB3_8:
xorl %r14d, %r14d
.LBB3_13:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_32
# %bb.14:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_33
# %bb.15:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_34
# %bb.16:
movl 8(%rsp), %esi # 4-byte Reload
movl %esi, %edi
shrl $31, %edi
addl %esi, %edi
testl %r12d, %r12d
je .LBB3_21
# %bb.17:
movl %edi, 92(%rsp) # 4-byte Spill
movq 24(%rsp), %rax # 8-byte Reload
leal -1(%rax), %ecx
movl %ecx, 4(%rsp) # 4-byte Spill
cmpl $2, %eax
movq %rbx, %r13
jl .LBB3_20
# %bb.18: # %.lr.ph.preheader.i
movl 4(%rsp), %r12d # 4-byte Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_19: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %rbx
cmpq %rbx, %r12
jne .LBB3_19
.LBB3_20: # %_Z10fprint_matP8_IO_FILEPfi.exit
movslq 4(%rsp), %rax # 4-byte Folded Reload
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
movq %r14, %rdi
callq fclose
movq %r13, %rbx
movl 8(%rsp), %esi # 4-byte Reload
movl 92(%rsp), %edi # 4-byte Reload
.LBB3_21:
sarl %edi
xorps %xmm0, %xmm0
xorl %eax, %eax
xorps %xmm1, %xmm1
cmpl $4, %esi
jl .LBB3_24
# %bb.22: # %.lr.ph.preheader
cmpl $3, %edi
movl $2, %ecx
cmovgel %edi, %ecx
movq 120(%rsp), %rax # 8-byte Reload
leaq (%rbx,%rax,4), %rdx
addq $-4, %rdx
decq %rcx
movl $-1, %eax
.p2align 4, 0x90
.LBB3_23: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rdx), %xmm1
addl %ebp, %eax
addq %r15, %rdx
decq %rcx
jne .LBB3_23
.LBB3_24: # %.preheader
cmpl %esi, %edi
jge .LBB3_27
# %bb.25: # %.lr.ph110.preheader
movslq %edi, %rax
movslq %esi, %rcx
decl %edi
imull %ebp, %edi
decl %edi
movq 120(%rsp), %rdx # 8-byte Reload
imulq %rax, %rdx
leaq (%rbx,%rdx,4), %rdx
addq $-4, %rdx
subq %rax, %rcx
xorps %xmm0, %xmm0
movl %edi, %eax
.p2align 4, 0x90
.LBB3_26: # %.lr.ph110
# =>This Inner Loop Header: Depth=1
addss (%rdx), %xmm0
addl %ebp, %eax
addq %r15, %rdx
decq %rcx
jne .LBB3_26
.LBB3_27: # %._crit_edge
cmpl 24(%rsp), %eax # 4-byte Folded Reload
je .LBB3_29
# %bb.28:
movq 128(%rsp), %rax # 8-byte Reload
addss -4(%rbx,%rax,4), %xmm1
.LBB3_29:
addss %xmm1, %xmm0
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_30:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %ecx
jmp .LBB3_35
.LBB3_31:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $90, %ecx
jmp .LBB3_35
.LBB3_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $104, %ecx
jmp .LBB3_35
.LBB3_33:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $106, %ecx
jmp .LBB3_35
.LBB3_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %ecx
.LBB3_35:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z4scanPfiiPci, .Lfunc_end3-_Z4scanPfiiPci
.cfi_endproc
# -- End function
.globl _Z19calculate_grid_sizeii # -- Begin function _Z19calculate_grid_sizeii
.p2align 4, 0x90
.type _Z19calculate_grid_sizeii,@function
_Z19calculate_grid_sizeii: # @_Z19calculate_grid_sizeii
.cfi_startproc
# %bb.0:
movl %esi, %eax
cltd
idivl %edi
imull %eax, %edi
xorl %ecx, %ecx
cmpl %esi, %edi
setl %cl
addl %ecx, %eax
retq
.Lfunc_end4:
.size _Z19calculate_grid_sizeii, .Lfunc_end4-_Z19calculate_grid_sizeii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__scan_kernelPfi # -- Begin function _Z26__device_stub__scan_kernelPfi
.p2align 4, 0x90
.type _Z26__device_stub__scan_kernelPfi,@function
_Z26__device_stub__scan_kernelPfi: # @_Z26__device_stub__scan_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11scan_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z26__device_stub__scan_kernelPfi, .Lfunc_end5-_Z26__device_stub__scan_kernelPfi
.cfi_endproc
# -- End function
.globl _Z34__device_stub__scan_kernel_coalescPfi # -- Begin function _Z34__device_stub__scan_kernel_coalescPfi
.p2align 4, 0x90
.type _Z34__device_stub__scan_kernel_coalescPfi,@function
_Z34__device_stub__scan_kernel_coalescPfi: # @_Z34__device_stub__scan_kernel_coalescPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19scan_kernel_coalescPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z34__device_stub__scan_kernel_coalescPfi, .Lfunc_end6-_Z34__device_stub__scan_kernel_coalescPfi
.cfi_endproc
# -- End function
.globl _Z10fprint_matP8_IO_FILEPfi # -- Begin function _Z10fprint_matP8_IO_FILEPfi
.p2align 4, 0x90
.type _Z10fprint_matP8_IO_FILEPfi,@function
_Z10fprint_matP8_IO_FILEPfi: # @_Z10fprint_matP8_IO_FILEPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rsi, %r14
movq %rdi, %rbx
leal -1(%rdx), %ebp
cmpl $2, %edx
jl .LBB7_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r15
jne .LBB7_2
.LBB7_3: # %._crit_edge
movslq %ebp, %rax
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %esi
movq %rbx, %rdi
movb $1, %al
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fprintf # TAILCALL
.Lfunc_end7:
.size _Z10fprint_matP8_IO_FILEPfi, .Lfunc_end7-_Z10fprint_matP8_IO_FILEPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11scan_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19scan_kernel_coalescPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type block_size,@object # @block_size
.bss
.globl block_size
.p2align 2, 0x0
block_size:
.long 0 # 0x0
.size block_size, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: %s <tamanho_vetor> <algoritmo> <tamanho_bloco> <debug opcional>\nalgoritmo:\n\ts (Sequencial)\n\tc (Cuda nao coalescente)\n\tcc (Cuda coalescente)\n"
.size .L.str, 148
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "debug"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f MBytes\n"
.size .L.str.3, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Sum: %f\n"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/wakim/prog-gpu-cuda/master/Sum/src/Sum.hip"
.size .L.str.7, 100
.type _Z11scan_kernelPfi,@object # @_Z11scan_kernelPfi
.section .rodata,"a",@progbits
.globl _Z11scan_kernelPfi
.p2align 3, 0x0
_Z11scan_kernelPfi:
.quad _Z26__device_stub__scan_kernelPfi
.size _Z11scan_kernelPfi, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "saida_c.txt"
.size .L.str.9, 12
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "w"
.size .L.str.10, 2
.type _Z19scan_kernel_coalescPfi,@object # @_Z19scan_kernel_coalescPfi
.section .rodata,"a",@progbits
.globl _Z19scan_kernel_coalescPfi
.p2align 3, 0x0
_Z19scan_kernel_coalescPfi:
.quad _Z34__device_stub__scan_kernel_coalescPfi
.size _Z19scan_kernel_coalescPfi, 8
.type .L.str.11,@object # @.str.11
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.11:
.asciz "saida_cc.txt"
.size .L.str.11, 13
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "saida_s.txt"
.size .L.str.12, 12
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%f "
.size .L.str.13, 4
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%f"
.size .L.str.14, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11scan_kernelPfi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19scan_kernel_coalescPfi"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__scan_kernelPfi
.addrsig_sym _Z34__device_stub__scan_kernel_coalescPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11scan_kernelPfi
.addrsig_sym _Z19scan_kernel_coalescPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define N 300000
#define BLOCK_SIZE_X 1024
#define checkCudaErrors(msg) err_msg(msg, __LINE__)
void err_msg(cudaError_t msg, int x)
{
if (msg != cudaSuccess) {
std::cerr << "In line: " << x << ". error: " << cudaGetErrorString(msg) << std::endl;
exit(1);
}
return;
}
__global__ void findMax(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] >= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] >= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] >= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
__global__ void findMin(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] <= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] <= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] <= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
int main()
{
int points_num = N;
float *x, *y, *z;
float *max_x, *max_y, *max_z, *min_x, *min_y, *min_z;
float a_max_x, a_min_x, a_max_y, a_min_y, a_max_z, a_min_z;
float *d_x, *d_y, *d_z;
std::chrono::time_point<std::chrono::system_clock> start, end;
double time;
x = new float[N];
y = new float[N];
z = new float[N];
std::mt19937 mt(10);
for (int i = 0; i < N; i++) {
x[i] = mt() / 10000.0;
y[i] = mt() / 10000.0;
z[i] = mt() / 10000.0;
}
start = std::chrono::system_clock::now();
a_max_x = a_min_x = x[0];
a_max_y = a_min_y = y[0];
a_max_z = a_min_z = z[0];
for (int i = 1; i < N; i++) {
a_max_x = (a_max_x > x[i]) ? a_max_x : x[i];
a_min_x = (a_min_x < x[i]) ? a_min_x : x[i];
a_max_y = (a_max_y > y[i]) ? a_max_y : y[i];
a_min_y = (a_min_y < y[i]) ? a_min_y : y[i];
a_max_z = (a_max_z > z[i]) ? a_max_z : z[i];
a_min_z = (a_min_z < z[i]) ? a_min_z : z[i];
}
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "CPU sort: " << time << "ms." << std::endl;
checkCudaErrors(cudaMalloc(&d_x, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&d_y, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&d_z, sizeof(float) * points_num));
checkCudaErrors(cudaMemcpy(d_x, x, sizeof(float) * points_num, cudaMemcpyHostToDevice));
checkCudaErrors(cudaMemcpy(d_y, y, sizeof(float) * points_num, cudaMemcpyHostToDevice));
checkCudaErrors(cudaMemcpy(d_z, z, sizeof(float) * points_num, cudaMemcpyHostToDevice));
start = std::chrono::system_clock::now();
checkCudaErrors(cudaMalloc(&max_x, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&max_y, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&max_z, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&min_x, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&min_y, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&min_z, sizeof(float) * points_num));
checkCudaErrors(cudaMemcpy(max_x, d_x, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(max_y, d_y, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(max_z, d_z, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(min_x, d_x, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(min_y, d_y, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(min_z, d_z, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
while (points_num > 1) {
int half_points_num = (points_num - 1) / 2 + 1;
int block_x = (half_points_num > BLOCK_SIZE_X) ? BLOCK_SIZE_X : half_points_num;
int grid_x = (half_points_num - 1) / block_x + 1;
findMax<<<grid_x, block_x>>>(max_x, max_y, max_z, points_num, half_points_num);
checkCudaErrors(cudaGetLastError());
findMin<<<grid_x, block_x>>>(min_x, min_y, min_z, points_num, half_points_num);
checkCudaErrors(cudaGetLastError());
points_num = half_points_num;
}
checkCudaErrors(cudaDeviceSynchronize());
checkCudaErrors(cudaMemcpy(&a_max_x, max_x, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_max_y, max_y, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_max_z, max_z, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_min_x, min_x, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_min_y, min_y, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_min_z, min_z, sizeof(float), cudaMemcpyDeviceToHost));
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "GPU sort: " << time << "ms." << std::endl;
checkCudaErrors(cudaFree(max_x));
checkCudaErrors(cudaFree(max_y));
checkCudaErrors(cudaFree(max_z));
checkCudaErrors(cudaFree(min_x));
checkCudaErrors(cudaFree(min_y));
checkCudaErrors(cudaFree(min_z));
checkCudaErrors(cudaFree(d_x));
checkCudaErrors(cudaFree(d_y));
checkCudaErrors(cudaFree(d_z));
delete[] x;
delete[] y;
delete[] z;
return 0;
} | .file "tmpxft_00017697_00000000-6_sort.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4862:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4862:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "In line: "
.LC1:
.string ". error: "
.text
.globl _Z7err_msg9cudaErrori
.type _Z7err_msg9cudaErrori, @function
_Z7err_msg9cudaErrori:
.LFB4852:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movl %esi, %ebp
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4852:
.size _Z7err_msg9cudaErrori, .-_Z7err_msg9cudaErrori
.globl _Z32__device_stub__Z7findMaxPfS_S_iiPfS_S_ii
.type _Z32__device_stub__Z7findMaxPfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7findMaxPfS_S_iiPfS_S_ii:
.LFB4884:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7findMaxPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4884:
.size _Z32__device_stub__Z7findMaxPfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7findMaxPfS_S_iiPfS_S_ii
.globl _Z7findMaxPfS_S_ii
.type _Z7findMaxPfS_S_ii, @function
_Z7findMaxPfS_S_ii:
.LFB4885:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7findMaxPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4885:
.size _Z7findMaxPfS_S_ii, .-_Z7findMaxPfS_S_ii
.globl _Z32__device_stub__Z7findMinPfS_S_iiPfS_S_ii
.type _Z32__device_stub__Z7findMinPfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7findMinPfS_S_iiPfS_S_ii:
.LFB4886:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7findMinPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4886:
.size _Z32__device_stub__Z7findMinPfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7findMinPfS_S_iiPfS_S_ii
.globl _Z7findMinPfS_S_ii
.type _Z7findMinPfS_S_ii, @function
_Z7findMinPfS_S_ii:
.LFB4887:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7findMinPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4887:
.size _Z7findMinPfS_S_ii, .-_Z7findMinPfS_S_ii
.section .rodata.str1.1
.LC2:
.string "_Z7findMinPfS_S_ii"
.LC3:
.string "_Z7findMaxPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4889:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7findMinPfS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7findMaxPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4889:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB5411:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L29:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L29
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L31:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L31
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE5411:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB5237:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $623, 4992(%rdi)
ja .L38
.L36:
movq 4992(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 4992(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rax, %rdx
movq %rdx, %rax
shrq $18, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L36
.cfi_endproc
.LFE5237:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .rodata.str1.1
.LC6:
.string "CPU sort: "
.LC7:
.string "ms."
.LC8:
.string "GPU sort: "
.text
.globl main
.type main, @function
main:
.LFB4853:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $4096, %rsp
.cfi_def_cfa_offset 4152
orq $0, (%rsp)
subq $1064, %rsp
.cfi_def_cfa_offset 5216
movq %fs:40, %rax
movq %rax, 5144(%rsp)
xorl %eax, %eax
movl $1200000, %edi
call _Znam@PLT
movq %rax, %r13
movl $1200000, %edi
call _Znam@PLT
movq %rax, %r12
movl $1200000, %edi
call _Znam@PLT
movq %rax, %rbp
movq $10, 144(%rsp)
movl $1, %ecx
movabsq $945986875574848801, %rdi
.L40:
movq 136(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, 144(%rsp,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L40
movq $624, 5136(%rsp)
movl $0, %ebx
leaq 144(%rsp), %r14
jmp .L47
.L41:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L42
.L43:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L44
.L45:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L46:
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $1200000, %rbx
je .L76
.L47:
movq %r14, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
testq %rax, %rax
js .L41
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L42:
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rbx)
movq %r14, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
testq %rax, %rax
js .L43
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L44:
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx)
movq %r14, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
testq %rax, %rax
js .L45
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L46
.L76:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movss 0(%r13), %xmm3
movss (%r12), %xmm2
movss 0(%rbp), %xmm1
movaps %xmm1, %xmm4
movaps %xmm2, %xmm5
movaps %xmm3, %xmm6
movl $4, %eax
.L60:
movss 0(%r13,%rax), %xmm0
maxss %xmm0, %xmm3
minss %xmm0, %xmm6
movss (%r12,%rax), %xmm0
maxss %xmm0, %xmm2
minss %xmm0, %xmm5
movss 0(%rbp,%rax), %xmm0
maxss %xmm0, %xmm1
minss %xmm0, %xmm4
addq $4, %rax
cmpq $1200000, %rax
jne .L60
movss %xmm3, 24(%rsp)
movss %xmm6, 28(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm5, 36(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm4, 44(%rsp)
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC5(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 96(%rsp), %rdi
movl $1200000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $92, %esi
call _Z7err_msg9cudaErrori
leaq 104(%rsp), %rdi
movl $1200000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $93, %esi
call _Z7err_msg9cudaErrori
leaq 112(%rsp), %rdi
movl $1200000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $94, %esi
call _Z7err_msg9cudaErrori
movl $1, %ecx
movl $1200000, %edx
movq %r13, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $96, %esi
call _Z7err_msg9cudaErrori
movl $1, %ecx
movl $1200000, %edx
movq %r12, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $97, %esi
call _Z7err_msg9cudaErrori
movl $1, %ecx
movl $1200000, %edx
movq %rbp, %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $98, %esi
call _Z7err_msg9cudaErrori
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
leaq 48(%rsp), %rdi
movl $1200000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $102, %esi
call _Z7err_msg9cudaErrori
leaq 56(%rsp), %rdi
movl $1200000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $103, %esi
call _Z7err_msg9cudaErrori
leaq 64(%rsp), %rdi
movl $1200000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $104, %esi
call _Z7err_msg9cudaErrori
leaq 72(%rsp), %rdi
movl $1200000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $105, %esi
call _Z7err_msg9cudaErrori
leaq 80(%rsp), %rdi
movl $1200000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $106, %esi
call _Z7err_msg9cudaErrori
leaq 88(%rsp), %rdi
movl $1200000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $107, %esi
call _Z7err_msg9cudaErrori
movl $3, %ecx
movl $1200000, %edx
movq 96(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $109, %esi
call _Z7err_msg9cudaErrori
movl $3, %ecx
movl $1200000, %edx
movq 104(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $110, %esi
call _Z7err_msg9cudaErrori
movl $3, %ecx
movl $1200000, %edx
movq 112(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $111, %esi
call _Z7err_msg9cudaErrori
movl $3, %ecx
movl $1200000, %edx
movq 96(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $113, %esi
call _Z7err_msg9cudaErrori
movl $3, %ecx
movl $1200000, %edx
movq 104(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $114, %esi
call _Z7err_msg9cudaErrori
movl $3, %ecx
movl $1200000, %edx
movq 112(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $115, %esi
call _Z7err_msg9cudaErrori
movl $19, 4(%rsp)
movl $300000, %r15d
jmp .L63
.L78:
movl %r15d, %r8d
movl (%rsp), %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z32__device_stub__Z7findMaxPfS_S_iiPfS_S_ii
jmp .L61
.L62:
call cudaGetLastError@PLT
movl %eax, %edi
movl $126, %esi
call _Z7err_msg9cudaErrori
subl $1, 4(%rsp)
je .L77
.L63:
leal -1(%r15), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movl %r15d, (%rsp)
leal 1(%rax), %r15d
movl $1024, %r14d
cmpl %r14d, %r15d
cmovle %r15d, %r14d
movl %r14d, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
cltd
idivl %r14d
leal 1(%rax), %ebx
movl %ebx, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L61:
call cudaGetLastError@PLT
movl %eax, %edi
movl $123, %esi
call _Z7err_msg9cudaErrori
movl %r14d, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl %ebx, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L62
movl %r15d, %r8d
movl (%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z32__device_stub__Z7findMinPfS_S_iiPfS_S_ii
jmp .L62
.L77:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $131, %esi
call _Z7err_msg9cudaErrori
leaq 24(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $133, %esi
call _Z7err_msg9cudaErrori
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 56(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $134, %esi
call _Z7err_msg9cudaErrori
leaq 40(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $135, %esi
call _Z7err_msg9cudaErrori
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 72(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $137, %esi
call _Z7err_msg9cudaErrori
leaq 36(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 80(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $138, %esi
call _Z7err_msg9cudaErrori
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 88(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $139, %esi
call _Z7err_msg9cudaErrori
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq 8(%rsp), %rsi
subq %rsi, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC5(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $147, %esi
call _Z7err_msg9cudaErrori
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $148, %esi
call _Z7err_msg9cudaErrori
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $149, %esi
call _Z7err_msg9cudaErrori
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $150, %esi
call _Z7err_msg9cudaErrori
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $151, %esi
call _Z7err_msg9cudaErrori
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $152, %esi
call _Z7err_msg9cudaErrori
movq 96(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $153, %esi
call _Z7err_msg9cudaErrori
movq 104(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $154, %esi
call _Z7err_msg9cudaErrori
movq 112(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $155, %esi
call _Z7err_msg9cudaErrori
movq %r13, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 5144(%rsp), %rax
subq %fs:40, %rax
jne .L79
movl $0, %eax
addq $5160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4853:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1086556160
.align 8
.LC5:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define N 300000
#define BLOCK_SIZE_X 1024
#define checkCudaErrors(msg) err_msg(msg, __LINE__)
void err_msg(cudaError_t msg, int x)
{
if (msg != cudaSuccess) {
std::cerr << "In line: " << x << ". error: " << cudaGetErrorString(msg) << std::endl;
exit(1);
}
return;
}
__global__ void findMax(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] >= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] >= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] >= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
__global__ void findMin(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] <= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] <= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] <= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
int main()
{
int points_num = N;
float *x, *y, *z;
float *max_x, *max_y, *max_z, *min_x, *min_y, *min_z;
float a_max_x, a_min_x, a_max_y, a_min_y, a_max_z, a_min_z;
float *d_x, *d_y, *d_z;
std::chrono::time_point<std::chrono::system_clock> start, end;
double time;
x = new float[N];
y = new float[N];
z = new float[N];
std::mt19937 mt(10);
for (int i = 0; i < N; i++) {
x[i] = mt() / 10000.0;
y[i] = mt() / 10000.0;
z[i] = mt() / 10000.0;
}
start = std::chrono::system_clock::now();
a_max_x = a_min_x = x[0];
a_max_y = a_min_y = y[0];
a_max_z = a_min_z = z[0];
for (int i = 1; i < N; i++) {
a_max_x = (a_max_x > x[i]) ? a_max_x : x[i];
a_min_x = (a_min_x < x[i]) ? a_min_x : x[i];
a_max_y = (a_max_y > y[i]) ? a_max_y : y[i];
a_min_y = (a_min_y < y[i]) ? a_min_y : y[i];
a_max_z = (a_max_z > z[i]) ? a_max_z : z[i];
a_min_z = (a_min_z < z[i]) ? a_min_z : z[i];
}
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "CPU sort: " << time << "ms." << std::endl;
checkCudaErrors(cudaMalloc(&d_x, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&d_y, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&d_z, sizeof(float) * points_num));
checkCudaErrors(cudaMemcpy(d_x, x, sizeof(float) * points_num, cudaMemcpyHostToDevice));
checkCudaErrors(cudaMemcpy(d_y, y, sizeof(float) * points_num, cudaMemcpyHostToDevice));
checkCudaErrors(cudaMemcpy(d_z, z, sizeof(float) * points_num, cudaMemcpyHostToDevice));
start = std::chrono::system_clock::now();
checkCudaErrors(cudaMalloc(&max_x, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&max_y, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&max_z, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&min_x, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&min_y, sizeof(float) * points_num));
checkCudaErrors(cudaMalloc(&min_z, sizeof(float) * points_num));
checkCudaErrors(cudaMemcpy(max_x, d_x, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(max_y, d_y, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(max_z, d_z, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(min_x, d_x, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(min_y, d_y, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
checkCudaErrors(cudaMemcpy(min_z, d_z, sizeof(float) * points_num, cudaMemcpyDeviceToDevice));
while (points_num > 1) {
int half_points_num = (points_num - 1) / 2 + 1;
int block_x = (half_points_num > BLOCK_SIZE_X) ? BLOCK_SIZE_X : half_points_num;
int grid_x = (half_points_num - 1) / block_x + 1;
findMax<<<grid_x, block_x>>>(max_x, max_y, max_z, points_num, half_points_num);
checkCudaErrors(cudaGetLastError());
findMin<<<grid_x, block_x>>>(min_x, min_y, min_z, points_num, half_points_num);
checkCudaErrors(cudaGetLastError());
points_num = half_points_num;
}
checkCudaErrors(cudaDeviceSynchronize());
checkCudaErrors(cudaMemcpy(&a_max_x, max_x, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_max_y, max_y, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_max_z, max_z, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_min_x, min_x, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_min_y, min_y, sizeof(float), cudaMemcpyDeviceToHost));
checkCudaErrors(cudaMemcpy(&a_min_z, min_z, sizeof(float), cudaMemcpyDeviceToHost));
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "GPU sort: " << time << "ms." << std::endl;
checkCudaErrors(cudaFree(max_x));
checkCudaErrors(cudaFree(max_y));
checkCudaErrors(cudaFree(max_z));
checkCudaErrors(cudaFree(min_x));
checkCudaErrors(cudaFree(min_y));
checkCudaErrors(cudaFree(min_z));
checkCudaErrors(cudaFree(d_x));
checkCudaErrors(cudaFree(d_y));
checkCudaErrors(cudaFree(d_z));
delete[] x;
delete[] y;
delete[] z;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <random>
#include <chrono>
#define N 300000
#define BLOCK_SIZE_X 1024
#define checkCudaErrors(msg) err_msg(msg, __LINE__)
void err_msg(hipError_t msg, int x)
{
if (msg != hipSuccess) {
std::cerr << "In line: " << x << ". error: " << hipGetErrorString(msg) << std::endl;
exit(1);
}
return;
}
__global__ void findMax(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] >= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] >= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] >= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
__global__ void findMin(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] <= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] <= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] <= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
int main()
{
int points_num = N;
float *x, *y, *z;
float *max_x, *max_y, *max_z, *min_x, *min_y, *min_z;
float a_max_x, a_min_x, a_max_y, a_min_y, a_max_z, a_min_z;
float *d_x, *d_y, *d_z;
std::chrono::time_point<std::chrono::system_clock> start, end;
double time;
x = new float[N];
y = new float[N];
z = new float[N];
std::mt19937 mt(10);
for (int i = 0; i < N; i++) {
x[i] = mt() / 10000.0;
y[i] = mt() / 10000.0;
z[i] = mt() / 10000.0;
}
start = std::chrono::system_clock::now();
a_max_x = a_min_x = x[0];
a_max_y = a_min_y = y[0];
a_max_z = a_min_z = z[0];
for (int i = 1; i < N; i++) {
a_max_x = (a_max_x > x[i]) ? a_max_x : x[i];
a_min_x = (a_min_x < x[i]) ? a_min_x : x[i];
a_max_y = (a_max_y > y[i]) ? a_max_y : y[i];
a_min_y = (a_min_y < y[i]) ? a_min_y : y[i];
a_max_z = (a_max_z > z[i]) ? a_max_z : z[i];
a_min_z = (a_min_z < z[i]) ? a_min_z : z[i];
}
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "CPU sort: " << time << "ms." << std::endl;
checkCudaErrors(hipMalloc(&d_x, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&d_y, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&d_z, sizeof(float) * points_num));
checkCudaErrors(hipMemcpy(d_x, x, sizeof(float) * points_num, hipMemcpyHostToDevice));
checkCudaErrors(hipMemcpy(d_y, y, sizeof(float) * points_num, hipMemcpyHostToDevice));
checkCudaErrors(hipMemcpy(d_z, z, sizeof(float) * points_num, hipMemcpyHostToDevice));
start = std::chrono::system_clock::now();
checkCudaErrors(hipMalloc(&max_x, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&max_y, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&max_z, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&min_x, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&min_y, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&min_z, sizeof(float) * points_num));
checkCudaErrors(hipMemcpy(max_x, d_x, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(max_y, d_y, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(max_z, d_z, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(min_x, d_x, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(min_y, d_y, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(min_z, d_z, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
while (points_num > 1) {
int half_points_num = (points_num - 1) / 2 + 1;
int block_x = (half_points_num > BLOCK_SIZE_X) ? BLOCK_SIZE_X : half_points_num;
int grid_x = (half_points_num - 1) / block_x + 1;
findMax<<<grid_x, block_x>>>(max_x, max_y, max_z, points_num, half_points_num);
checkCudaErrors(hipGetLastError());
findMin<<<grid_x, block_x>>>(min_x, min_y, min_z, points_num, half_points_num);
checkCudaErrors(hipGetLastError());
points_num = half_points_num;
}
checkCudaErrors(hipDeviceSynchronize());
checkCudaErrors(hipMemcpy(&a_max_x, max_x, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_max_y, max_y, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_max_z, max_z, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_min_x, min_x, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_min_y, min_y, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_min_z, min_z, sizeof(float), hipMemcpyDeviceToHost));
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "GPU sort: " << time << "ms." << std::endl;
checkCudaErrors(hipFree(max_x));
checkCudaErrors(hipFree(max_y));
checkCudaErrors(hipFree(max_z));
checkCudaErrors(hipFree(min_x));
checkCudaErrors(hipFree(min_y));
checkCudaErrors(hipFree(min_z));
checkCudaErrors(hipFree(d_x));
checkCudaErrors(hipFree(d_y));
checkCudaErrors(hipFree(d_z));
delete[] x;
delete[] y;
delete[] z;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <random>
#include <chrono>
#define N 300000
#define BLOCK_SIZE_X 1024
#define checkCudaErrors(msg) err_msg(msg, __LINE__)
void err_msg(hipError_t msg, int x)
{
if (msg != hipSuccess) {
std::cerr << "In line: " << x << ". error: " << hipGetErrorString(msg) << std::endl;
exit(1);
}
return;
}
__global__ void findMax(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] >= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] >= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] >= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
__global__ void findMin(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] <= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] <= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] <= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
int main()
{
int points_num = N;
float *x, *y, *z;
float *max_x, *max_y, *max_z, *min_x, *min_y, *min_z;
float a_max_x, a_min_x, a_max_y, a_min_y, a_max_z, a_min_z;
float *d_x, *d_y, *d_z;
std::chrono::time_point<std::chrono::system_clock> start, end;
double time;
x = new float[N];
y = new float[N];
z = new float[N];
std::mt19937 mt(10);
for (int i = 0; i < N; i++) {
x[i] = mt() / 10000.0;
y[i] = mt() / 10000.0;
z[i] = mt() / 10000.0;
}
start = std::chrono::system_clock::now();
a_max_x = a_min_x = x[0];
a_max_y = a_min_y = y[0];
a_max_z = a_min_z = z[0];
for (int i = 1; i < N; i++) {
a_max_x = (a_max_x > x[i]) ? a_max_x : x[i];
a_min_x = (a_min_x < x[i]) ? a_min_x : x[i];
a_max_y = (a_max_y > y[i]) ? a_max_y : y[i];
a_min_y = (a_min_y < y[i]) ? a_min_y : y[i];
a_max_z = (a_max_z > z[i]) ? a_max_z : z[i];
a_min_z = (a_min_z < z[i]) ? a_min_z : z[i];
}
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "CPU sort: " << time << "ms." << std::endl;
checkCudaErrors(hipMalloc(&d_x, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&d_y, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&d_z, sizeof(float) * points_num));
checkCudaErrors(hipMemcpy(d_x, x, sizeof(float) * points_num, hipMemcpyHostToDevice));
checkCudaErrors(hipMemcpy(d_y, y, sizeof(float) * points_num, hipMemcpyHostToDevice));
checkCudaErrors(hipMemcpy(d_z, z, sizeof(float) * points_num, hipMemcpyHostToDevice));
start = std::chrono::system_clock::now();
checkCudaErrors(hipMalloc(&max_x, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&max_y, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&max_z, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&min_x, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&min_y, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&min_z, sizeof(float) * points_num));
checkCudaErrors(hipMemcpy(max_x, d_x, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(max_y, d_y, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(max_z, d_z, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(min_x, d_x, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(min_y, d_y, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(min_z, d_z, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
while (points_num > 1) {
int half_points_num = (points_num - 1) / 2 + 1;
int block_x = (half_points_num > BLOCK_SIZE_X) ? BLOCK_SIZE_X : half_points_num;
int grid_x = (half_points_num - 1) / block_x + 1;
findMax<<<grid_x, block_x>>>(max_x, max_y, max_z, points_num, half_points_num);
checkCudaErrors(hipGetLastError());
findMin<<<grid_x, block_x>>>(min_x, min_y, min_z, points_num, half_points_num);
checkCudaErrors(hipGetLastError());
points_num = half_points_num;
}
checkCudaErrors(hipDeviceSynchronize());
checkCudaErrors(hipMemcpy(&a_max_x, max_x, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_max_y, max_y, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_max_z, max_z, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_min_x, min_x, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_min_y, min_y, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_min_z, min_z, sizeof(float), hipMemcpyDeviceToHost));
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "GPU sort: " << time << "ms." << std::endl;
checkCudaErrors(hipFree(max_x));
checkCudaErrors(hipFree(max_y));
checkCudaErrors(hipFree(max_z));
checkCudaErrors(hipFree(min_x));
checkCudaErrors(hipFree(min_y));
checkCudaErrors(hipFree(min_z));
checkCudaErrors(hipFree(d_x));
checkCudaErrors(hipFree(d_y));
checkCudaErrors(hipFree(d_z));
delete[] x;
delete[] y;
delete[] z;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7findMaxPfS_S_ii
.globl _Z7findMaxPfS_S_ii
.p2align 8
.type _Z7findMaxPfS_S_ii,@function
_Z7findMaxPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x1c
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_9
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_add3_u32 v3, s15, s8, v0
s_load_b32 s1, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
v_add_co_u32 v0, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v2, vcc_lo, s17, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s18, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s19, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, s18, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v12, vcc_lo
v_add_co_u32 v11, vcc_lo, s16, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v12, vcc_lo
s_ashr_i32 s3, s2, 31
s_mov_b64 s[6:7], 0
s_lshl_b64 s[4:5], s[2:3], 2
s_mov_b32 s3, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v14, s0, v5, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v15, s0, s7, v6, s0
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_add_u32 s6, s6, s4
s_addc_u32 s7, s7, s5
s_waitcnt vmcnt(0)
global_store_b32 v[14:15], v13, off
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_9
.LBB0_3:
v_add_co_u32 v13, vcc_lo, v0, s6
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v2, vcc_lo
global_load_b32 v13, v[13:14], off
v_add_nc_u32_e32 v14, s8, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s1, v14
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_5
v_add_co_u32 v14, s0, v11, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v15, s0, s7, v12, s0
global_load_b32 v14, v[14:15], off
s_waitcnt vmcnt(0)
v_cmp_ge_f32_e64 s0, v13, v14
v_cndmask_b32_e64 v13, v14, v13, s0
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
v_add_co_u32 v14, s0, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v15, s0, s7, v2, s0
v_add_co_u32 v16, s0, v3, s6
v_add_co_ci_u32_e64 v17, s0, s7, v4, s0
s_waitcnt vmcnt(0)
global_store_b32 v[14:15], v13, off
global_load_b32 v13, v[16:17], off
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_7
v_add_co_u32 v14, s0, v9, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v15, s0, s7, v10, s0
global_load_b32 v14, v[14:15], off
s_waitcnt vmcnt(0)
v_cmp_ge_f32_e64 s0, v13, v14
v_cndmask_b32_e64 v13, v14, v13, s0
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s9
v_add_co_u32 v14, s0, v3, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v15, s0, s7, v4, s0
v_add_co_u32 v16, s0, v5, s6
v_add_co_ci_u32_e64 v17, s0, s7, v6, s0
s_waitcnt vmcnt(0)
global_store_b32 v[14:15], v13, off
global_load_b32 v13, v[16:17], off
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v14, vcc_lo, v7, s6
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v8, vcc_lo
global_load_b32 v14, v[14:15], off
s_waitcnt vmcnt(0)
v_cmp_ge_f32_e32 vcc_lo, v13, v14
v_cndmask_b32_e32 v13, v14, v13, vcc_lo
s_branch .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7findMaxPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7findMaxPfS_S_ii, .Lfunc_end0-_Z7findMaxPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7findMinPfS_S_ii
.globl _Z7findMinPfS_S_ii
.p2align 8
.type _Z7findMinPfS_S_ii,@function
_Z7findMinPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x1c
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB1_9
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_add3_u32 v3, s15, s8, v0
s_load_b32 s1, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
v_add_co_u32 v0, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v2, vcc_lo, s17, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s18, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s19, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, s18, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v12, vcc_lo
v_add_co_u32 v11, vcc_lo, s16, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v12, vcc_lo
s_ashr_i32 s3, s2, 31
s_mov_b64 s[6:7], 0
s_lshl_b64 s[4:5], s[2:3], 2
s_mov_b32 s3, 0
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v14, s0, v5, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v15, s0, s7, v6, s0
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_add_u32 s6, s6, s4
s_addc_u32 s7, s7, s5
s_waitcnt vmcnt(0)
global_store_b32 v[14:15], v13, off
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB1_9
.LBB1_3:
v_add_co_u32 v13, vcc_lo, v0, s6
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v2, vcc_lo
global_load_b32 v13, v[13:14], off
v_add_nc_u32_e32 v14, s8, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s1, v14
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB1_5
v_add_co_u32 v14, s0, v11, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v15, s0, s7, v12, s0
global_load_b32 v14, v[14:15], off
s_waitcnt vmcnt(0)
v_cmp_le_f32_e64 s0, v13, v14
v_cndmask_b32_e64 v13, v14, v13, s0
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s9
v_add_co_u32 v14, s0, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v15, s0, s7, v2, s0
v_add_co_u32 v16, s0, v3, s6
v_add_co_ci_u32_e64 v17, s0, s7, v4, s0
s_waitcnt vmcnt(0)
global_store_b32 v[14:15], v13, off
global_load_b32 v13, v[16:17], off
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB1_7
v_add_co_u32 v14, s0, v9, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v15, s0, s7, v10, s0
global_load_b32 v14, v[14:15], off
s_waitcnt vmcnt(0)
v_cmp_le_f32_e64 s0, v13, v14
v_cndmask_b32_e64 v13, v14, v13, s0
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s9
v_add_co_u32 v14, s0, v3, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v15, s0, s7, v4, s0
v_add_co_u32 v16, s0, v5, s6
v_add_co_ci_u32_e64 v17, s0, s7, v6, s0
s_waitcnt vmcnt(0)
global_store_b32 v[14:15], v13, off
global_load_b32 v13, v[16:17], off
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_2
v_add_co_u32 v14, vcc_lo, v7, s6
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v8, vcc_lo
global_load_b32 v14, v[14:15], off
s_waitcnt vmcnt(0)
v_cmp_le_f32_e32 vcc_lo, v13, v14
v_cndmask_b32_e32 v13, v14, v13, vcc_lo
s_branch .LBB1_2
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7findMinPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7findMinPfS_S_ii, .Lfunc_end1-_Z7findMinPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7findMaxPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z7findMaxPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7findMinPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z7findMinPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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