system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <random>
#include <chrono>
#define N 300000
#define BLOCK_SIZE_X 1024
#define checkCudaErrors(msg) err_msg(msg, __LINE__)
void err_msg(hipError_t msg, int x)
{
if (msg != hipSuccess) {
std::cerr << "In line: " << x << ". error: " << hipGetErrorString(msg) << std::endl;
exit(1);
}
return;
}
__global__ void findMax(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] >= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] >= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] >= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
__global__ void findMin(float *x, float *y, float *z, int full_size, int half_size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < half_size; i += stride) {
x[i] = (i + half_size < full_size) ? ((x[i] <= x[i + half_size]) ? x[i] : x[i + half_size]) : x[i];
y[i] = (i + half_size < full_size) ? ((y[i] <= y[i + half_size]) ? y[i] : y[i + half_size]) : y[i];
z[i] = (i + half_size < full_size) ? ((z[i] <= z[i + half_size]) ? z[i] : z[i + half_size]) : z[i];
}
}
int main()
{
int points_num = N;
float *x, *y, *z;
float *max_x, *max_y, *max_z, *min_x, *min_y, *min_z;
float a_max_x, a_min_x, a_max_y, a_min_y, a_max_z, a_min_z;
float *d_x, *d_y, *d_z;
std::chrono::time_point<std::chrono::system_clock> start, end;
double time;
x = new float[N];
y = new float[N];
z = new float[N];
std::mt19937 mt(10);
for (int i = 0; i < N; i++) {
x[i] = mt() / 10000.0;
y[i] = mt() / 10000.0;
z[i] = mt() / 10000.0;
}
start = std::chrono::system_clock::now();
a_max_x = a_min_x = x[0];
a_max_y = a_min_y = y[0];
a_max_z = a_min_z = z[0];
for (int i = 1; i < N; i++) {
a_max_x = (a_max_x > x[i]) ? a_max_x : x[i];
a_min_x = (a_min_x < x[i]) ? a_min_x : x[i];
a_max_y = (a_max_y > y[i]) ? a_max_y : y[i];
a_min_y = (a_min_y < y[i]) ? a_min_y : y[i];
a_max_z = (a_max_z > z[i]) ? a_max_z : z[i];
a_min_z = (a_min_z < z[i]) ? a_min_z : z[i];
}
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "CPU sort: " << time << "ms." << std::endl;
checkCudaErrors(hipMalloc(&d_x, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&d_y, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&d_z, sizeof(float) * points_num));
checkCudaErrors(hipMemcpy(d_x, x, sizeof(float) * points_num, hipMemcpyHostToDevice));
checkCudaErrors(hipMemcpy(d_y, y, sizeof(float) * points_num, hipMemcpyHostToDevice));
checkCudaErrors(hipMemcpy(d_z, z, sizeof(float) * points_num, hipMemcpyHostToDevice));
start = std::chrono::system_clock::now();
checkCudaErrors(hipMalloc(&max_x, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&max_y, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&max_z, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&min_x, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&min_y, sizeof(float) * points_num));
checkCudaErrors(hipMalloc(&min_z, sizeof(float) * points_num));
checkCudaErrors(hipMemcpy(max_x, d_x, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(max_y, d_y, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(max_z, d_z, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(min_x, d_x, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(min_y, d_y, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
checkCudaErrors(hipMemcpy(min_z, d_z, sizeof(float) * points_num, hipMemcpyDeviceToDevice));
while (points_num > 1) {
int half_points_num = (points_num - 1) / 2 + 1;
int block_x = (half_points_num > BLOCK_SIZE_X) ? BLOCK_SIZE_X : half_points_num;
int grid_x = (half_points_num - 1) / block_x + 1;
findMax<<<grid_x, block_x>>>(max_x, max_y, max_z, points_num, half_points_num);
checkCudaErrors(hipGetLastError());
findMin<<<grid_x, block_x>>>(min_x, min_y, min_z, points_num, half_points_num);
checkCudaErrors(hipGetLastError());
points_num = half_points_num;
}
checkCudaErrors(hipDeviceSynchronize());
checkCudaErrors(hipMemcpy(&a_max_x, max_x, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_max_y, max_y, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_max_z, max_z, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_min_x, min_x, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_min_y, min_y, sizeof(float), hipMemcpyDeviceToHost));
checkCudaErrors(hipMemcpy(&a_min_z, min_z, sizeof(float), hipMemcpyDeviceToHost));
end = std::chrono::system_clock::now();
time = std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() / 1000.0;
std::cout << "GPU sort: " << time << "ms." << std::endl;
checkCudaErrors(hipFree(max_x));
checkCudaErrors(hipFree(max_y));
checkCudaErrors(hipFree(max_z));
checkCudaErrors(hipFree(min_x));
checkCudaErrors(hipFree(min_y));
checkCudaErrors(hipFree(min_z));
checkCudaErrors(hipFree(d_x));
checkCudaErrors(hipFree(d_y));
checkCudaErrors(hipFree(d_z));
delete[] x;
delete[] y;
delete[] z;
return 0;
} | .text
.file "sort.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7err_msg10hipError_ti # -- Begin function _Z7err_msg10hipError_ti
.p2align 4, 0x90
.type _Z7err_msg10hipError_ti,@function
_Z7err_msg10hipError_ti: # @_Z7err_msg10hipError_ti
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl %esi, %ebp
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z7err_msg10hipError_ti, .Lfunc_end0-_Z7err_msg10hipError_ti
.cfi_endproc
# -- End function
.globl _Z22__device_stub__findMaxPfS_S_ii # -- Begin function _Z22__device_stub__findMaxPfS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__findMaxPfS_S_ii,@function
_Z22__device_stub__findMaxPfS_S_ii: # @_Z22__device_stub__findMaxPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7findMaxPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__findMaxPfS_S_ii, .Lfunc_end1-_Z22__device_stub__findMaxPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__findMinPfS_S_ii # -- Begin function _Z22__device_stub__findMinPfS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__findMinPfS_S_ii,@function
_Z22__device_stub__findMinPfS_S_ii: # @_Z22__device_stub__findMinPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7findMinPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__findMinPfS_S_ii, .Lfunc_end2-_Z22__device_stub__findMinPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI3_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_2:
.quad 0x40c3880000000000 # double 1.0E+4
.LCPI3_3:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $5256, %rsp # imm = 0x1488
.cfi_def_cfa_offset 5312
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1200000, %edi # imm = 0x124F80
callq _Znam
movq %rax, %r15
movl $1200000, %edi # imm = 0x124F80
callq _Znam
movq %rax, %r12
movl $1200000, %edi # imm = 0x124F80
callq _Znam
movq %rax, %r13
movq $10, 256(%rsp)
movl $1, %eax
movl $10, %ecx
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movq %rcx, %rdx
shrq $30, %rdx
xorl %ecx, %edx
imull $1812433253, %edx, %ecx # imm = 0x6C078965
addl %eax, %ecx
movq %rcx, 256(%rsp,%rax,8)
incq %rax
cmpq $624, %rax # imm = 0x270
jne .LBB3_1
# %bb.2: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, 5248(%rsp) # imm = 0x270
xorl %r14d, %r14d
leaq 256(%rsp), %rbx
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
movq %rax, %xmm0
movdqa .LCPI3_0(%rip), %xmm1 # xmm1 = [1127219200,1160773632,0,0]
punpckldq %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
movapd .LCPI3_1(%rip), %xmm1 # xmm1 = [4.503599627370496E+15,1.9342813113834067E+25]
subpd %xmm1, %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
movsd .LCPI3_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%r15,%r14,4)
movq %rbx, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
movq %rax, %xmm0
punpckldq .LCPI3_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI3_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd .LCPI3_2(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%r12,%r14,4)
movq %rbx, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
movq %rax, %xmm0
punpckldq .LCPI3_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI3_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd .LCPI3_2(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%r13,%r14,4)
incq %r14
cmpq $300000, %r14 # imm = 0x493E0
jne .LBB3_3
# %bb.4:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 32(%rsp)
movss %xmm0, 36(%rsp)
movss (%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, 24(%rsp)
movss %xmm1, 28(%rsp)
movss (%r13), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss %xmm2, 16(%rsp)
movss %xmm2, 20(%rsp)
movl $1, %eax
movaps %xmm0, %xmm3
movaps %xmm1, %xmm4
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movss (%r15,%rax,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
maxss %xmm6, %xmm0
minss %xmm6, %xmm3
movss (%r12,%rax,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
maxss %xmm6, %xmm1
minss %xmm6, %xmm4
movss (%r13,%rax,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
maxss %xmm6, %xmm2
minss %xmm6, %xmm5
incq %rax
cmpq $300000, %rax # imm = 0x493E0
jne .LBB3_5
# %bb.6:
movss %xmm0, 36(%rsp)
movss %xmm3, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm5, 16(%rsp)
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
divsd .LCPI3_3(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_21
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB3_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB3_10
.LBB3_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 56(%rsp), %rdi
movl $1200000, %esi # imm = 0x124F80
callq hipMalloc
movl %eax, %edi
movl $92, %esi
callq _Z7err_msg10hipError_ti
leaq 48(%rsp), %rdi
movl $1200000, %esi # imm = 0x124F80
callq hipMalloc
movl %eax, %edi
movl $93, %esi
callq _Z7err_msg10hipError_ti
leaq 40(%rsp), %rdi
movl $1200000, %esi # imm = 0x124F80
callq hipMalloc
movl %eax, %edi
movl $94, %esi
callq _Z7err_msg10hipError_ti
movq 56(%rsp), %rdi
movl $1200000, %edx # imm = 0x124F80
movq %r15, 248(%rsp) # 8-byte Spill
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $96, %esi
callq _Z7err_msg10hipError_ti
movq 48(%rsp), %rdi
movl $1200000, %edx # imm = 0x124F80
movq %r12, 176(%rsp) # 8-byte Spill
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $97, %esi
callq _Z7err_msg10hipError_ti
movq 40(%rsp), %rdi
movl $1200000, %edx # imm = 0x124F80
movq %r13, 240(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $98, %esi
callq _Z7err_msg10hipError_ti
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 8(%rsp) # 8-byte Spill
leaq 104(%rsp), %rdi
movl $1200000, %esi # imm = 0x124F80
callq hipMalloc
movl %eax, %edi
movl $102, %esi
callq _Z7err_msg10hipError_ti
leaq 96(%rsp), %rdi
movl $1200000, %esi # imm = 0x124F80
callq hipMalloc
movl %eax, %edi
movl $103, %esi
callq _Z7err_msg10hipError_ti
leaq 88(%rsp), %rdi
movl $1200000, %esi # imm = 0x124F80
callq hipMalloc
movl %eax, %edi
movl $104, %esi
callq _Z7err_msg10hipError_ti
leaq 80(%rsp), %rdi
movl $1200000, %esi # imm = 0x124F80
callq hipMalloc
movl %eax, %edi
movl $105, %esi
callq _Z7err_msg10hipError_ti
leaq 72(%rsp), %rdi
movl $1200000, %esi # imm = 0x124F80
callq hipMalloc
movl %eax, %edi
movl $106, %esi
callq _Z7err_msg10hipError_ti
leaq 64(%rsp), %rdi
movl $1200000, %esi # imm = 0x124F80
callq hipMalloc
movl %eax, %edi
movl $107, %esi
callq _Z7err_msg10hipError_ti
movq 104(%rsp), %rdi
movq 56(%rsp), %rsi
movl $1200000, %edx # imm = 0x124F80
movl $3, %ecx
callq hipMemcpy
movl %eax, %edi
movl $109, %esi
callq _Z7err_msg10hipError_ti
movq 96(%rsp), %rdi
movq 48(%rsp), %rsi
movl $1200000, %edx # imm = 0x124F80
movl $3, %ecx
callq hipMemcpy
movl %eax, %edi
movl $110, %esi
callq _Z7err_msg10hipError_ti
movq 88(%rsp), %rdi
movq 40(%rsp), %rsi
movl $1200000, %edx # imm = 0x124F80
movl $3, %ecx
callq hipMemcpy
movl %eax, %edi
movl $111, %esi
callq _Z7err_msg10hipError_ti
movq 80(%rsp), %rdi
movq 56(%rsp), %rsi
movl $1200000, %edx # imm = 0x124F80
movl $3, %ecx
callq hipMemcpy
movl %eax, %edi
movl $113, %esi
callq _Z7err_msg10hipError_ti
movq 72(%rsp), %rdi
movq 48(%rsp), %rsi
movl $1200000, %edx # imm = 0x124F80
movl $3, %ecx
callq hipMemcpy
movl %eax, %edi
movl $114, %esi
callq _Z7err_msg10hipError_ti
movq 64(%rsp), %rdi
movq 40(%rsp), %rsi
movl $1200000, %edx # imm = 0x124F80
movl $3, %ecx
callq hipMemcpy
movl %eax, %edi
movl $115, %esi
callq _Z7err_msg10hipError_ti
movl $300000, %ebp # imm = 0x493E0
leaq 184(%rsp), %rbx
leaq 192(%rsp), %r14
jmp .LBB3_11
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_11 Depth=1
callq hipGetLastError
movl %eax, %edi
movl $126, %esi
callq _Z7err_msg10hipError_ti
cmpl $2, %ebp
movl %r12d, %ebp
jbe .LBB3_16
.LBB3_11: # =>This Inner Loop Header: Depth=1
leal -1(%rbp), %eax
shrl %eax
leal 1(%rax), %r12d
cmpl $1024, %r12d # imm = 0x400
movl $1024, %r15d # imm = 0x400
cmovbl %r12d, %r15d
# kill: def $eax killed $eax killed $rax
xorl %edx, %edx
divl %r15d
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rcx # imm = 0x100000000
leaq (%rcx,%rax), %r13
incq %r13
orq %rcx, %r15
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12: # in Loop: Header=BB3_11 Depth=1
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %ebp, 4(%rsp)
movl %r12d, (%rsp)
leaq 168(%rsp), %rax
movq %rax, 192(%rsp)
leaq 160(%rsp), %rax
movq %rax, 200(%rsp)
leaq 152(%rsp), %rax
movq %rax, 208(%rsp)
leaq 4(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z7findMaxPfS_S_ii, %edi
movq %r14, %r9
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # in Loop: Header=BB3_11 Depth=1
callq hipGetLastError
movl %eax, %edi
movl $123, %esi
callq _Z7err_msg10hipError_ti
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14: # in Loop: Header=BB3_11 Depth=1
movq 80(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %ebp, 4(%rsp)
movl %r12d, (%rsp)
leaq 168(%rsp), %rax
movq %rax, 192(%rsp)
leaq 160(%rsp), %rax
movq %rax, 200(%rsp)
leaq 152(%rsp), %rax
movq %rax, 208(%rsp)
leaq 4(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z7findMinPfS_S_ii, %edi
movq %r14, %r9
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_15
.LBB3_16:
callq hipDeviceSynchronize
movl %eax, %edi
movl $131, %esi
callq _Z7err_msg10hipError_ti
movq 104(%rsp), %rsi
leaq 36(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $133, %esi
callq _Z7err_msg10hipError_ti
movq 96(%rsp), %rsi
leaq 28(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $134, %esi
callq _Z7err_msg10hipError_ti
movq 88(%rsp), %rsi
leaq 20(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $135, %esi
callq _Z7err_msg10hipError_ti
movq 80(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $137, %esi
callq _Z7err_msg10hipError_ti
movq 72(%rsp), %rsi
leaq 24(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $138, %esi
callq _Z7err_msg10hipError_ti
movq 64(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $139, %esi
callq _Z7err_msg10hipError_ti
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 8(%rsp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rdx
addq %rax, %rdx
cvtsi2sd %rdx, %xmm0
divsd .LCPI3_3(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i111
cmpb $0, 56(%r14)
movq 248(%rsp), %r15 # 8-byte Reload
movq 240(%rsp), %r12 # 8-byte Reload
je .LBB3_19
# %bb.18:
movzbl 67(%r14), %eax
jmp .LBB3_20
.LBB3_19:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit114
movq 176(%rsp), %r14 # 8-byte Reload
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 104(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $147, %esi
callq _Z7err_msg10hipError_ti
movq 96(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $148, %esi
callq _Z7err_msg10hipError_ti
movq 88(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $149, %esi
callq _Z7err_msg10hipError_ti
movq 80(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $150, %esi
callq _Z7err_msg10hipError_ti
movq 72(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $151, %esi
callq _Z7err_msg10hipError_ti
movq 64(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $152, %esi
callq _Z7err_msg10hipError_ti
movq 56(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $153, %esi
callq _Z7err_msg10hipError_ti
movq 48(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $154, %esi
callq _Z7err_msg10hipError_ti
movq 40(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $155, %esi
callq _Z7err_msg10hipError_ti
movq %r15, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $5256, %rsp # imm = 0x1488
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_21:
.cfi_def_cfa_offset 5312
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB4_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB4_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB4_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB4_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end4:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end4-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7findMaxPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7findMinPfS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "In line: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ". error: "
.size .L.str.1, 10
.type _Z7findMaxPfS_S_ii,@object # @_Z7findMaxPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z7findMaxPfS_S_ii
.p2align 3, 0x0
_Z7findMaxPfS_S_ii:
.quad _Z22__device_stub__findMaxPfS_S_ii
.size _Z7findMaxPfS_S_ii, 8
.type _Z7findMinPfS_S_ii,@object # @_Z7findMinPfS_S_ii
.globl _Z7findMinPfS_S_ii
.p2align 3, 0x0
_Z7findMinPfS_S_ii:
.quad _Z22__device_stub__findMinPfS_S_ii
.size _Z7findMinPfS_S_ii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "CPU sort: "
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ms."
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU sort: "
.size .L.str.4, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7findMaxPfS_S_ii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7findMinPfS_S_ii"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__findMaxPfS_S_ii
.addrsig_sym _Z22__device_stub__findMinPfS_S_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cerr
.addrsig_sym _Z7findMaxPfS_S_ii
.addrsig_sym _Z7findMinPfS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | typedef unsigned uint32_t;
extern "C" {
__global__ void my_dot( float const * const a, float const * const b, float * const c, uint32_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n ) { c[ix] = a[ix] + b[ix]; }
}
struct n_t {
uint32_t n;
};
__global__ void my_dot_struct( float const * const a, float const * const b, float * const c, struct n_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n.n ) { c[ix] = a[ix] + b[ix]; }
}
} | code for sm_80
Function : my_dot_struct
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : my_dot
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | typedef unsigned uint32_t;
extern "C" {
__global__ void my_dot( float const * const a, float const * const b, float * const c, uint32_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n ) { c[ix] = a[ix] + b[ix]; }
}
struct n_t {
uint32_t n;
};
__global__ void my_dot_struct( float const * const a, float const * const b, float * const c, struct n_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n.n ) { c[ix] = a[ix] + b[ix]; }
}
} | .file "tmpxft_001b105f_00000000-6_nvrtc_test_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj
.type _Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj, @function
_Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq my_dot(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj, .-_Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj
.globl my_dot
.type my_dot, @function
my_dot:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size my_dot, .-my_dot
.globl _Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t
.type _Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t, @function
_Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rcx, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq my_dot_struct(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t, .-_Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t
.globl my_dot_struct
.type my_dot_struct, @function
my_dot_struct:
.LFB2054:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movl %ecx, 12(%rsp)
leaq 12(%rsp), %rcx
call _Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size my_dot_struct, .-my_dot_struct
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "my_dot_struct"
.LC1:
.string "my_dot"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq my_dot_struct(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq my_dot(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | typedef unsigned uint32_t;
extern "C" {
__global__ void my_dot( float const * const a, float const * const b, float * const c, uint32_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n ) { c[ix] = a[ix] + b[ix]; }
}
struct n_t {
uint32_t n;
};
__global__ void my_dot_struct( float const * const a, float const * const b, float * const c, struct n_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n.n ) { c[ix] = a[ix] + b[ix]; }
}
} | #include <hip/hip_runtime.h>
typedef unsigned uint32_t;
extern "C" {
__global__ void my_dot( float const * const a, float const * const b, float * const c, uint32_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n ) { c[ix] = a[ix] + b[ix]; }
}
struct n_t {
uint32_t n;
};
__global__ void my_dot_struct( float const * const a, float const * const b, float * const c, struct n_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n.n ) { c[ix] = a[ix] + b[ix]; }
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
typedef unsigned uint32_t;
extern "C" {
__global__ void my_dot( float const * const a, float const * const b, float * const c, uint32_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n ) { c[ix] = a[ix] + b[ix]; }
}
struct n_t {
uint32_t n;
};
__global__ void my_dot_struct( float const * const a, float const * const b, float * const c, struct n_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n.n ) { c[ix] = a[ix] + b[ix]; }
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected my_dot
.globl my_dot
.p2align 8
.type my_dot,@function
my_dot:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel my_dot
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size my_dot, .Lfunc_end0-my_dot
.section .AMDGPU.csdata,"",@progbits
.text
.protected my_dot_struct
.globl my_dot_struct
.p2align 8
.type my_dot_struct,@function
my_dot_struct:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel my_dot_struct
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size my_dot_struct, .Lfunc_end1-my_dot_struct
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: my_dot
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: my_dot.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: my_dot_struct
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: my_dot_struct.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
typedef unsigned uint32_t;
extern "C" {
__global__ void my_dot( float const * const a, float const * const b, float * const c, uint32_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n ) { c[ix] = a[ix] + b[ix]; }
}
struct n_t {
uint32_t n;
};
__global__ void my_dot_struct( float const * const a, float const * const b, float * const c, struct n_t const n ) {
uint32_t const ix = blockDim.x * blockIdx.x + threadIdx.x;
if( ix < n.n ) { c[ix] = a[ix] + b[ix]; }
}
} | .text
.file "nvrtc_test_dot.hip"
.globl __device_stub__my_dot # -- Begin function __device_stub__my_dot
.p2align 4, 0x90
.type __device_stub__my_dot,@function
__device_stub__my_dot: # @__device_stub__my_dot
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $my_dot, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__my_dot, .Lfunc_end0-__device_stub__my_dot
.cfi_endproc
# -- End function
.globl __device_stub__my_dot_struct # -- Begin function __device_stub__my_dot_struct
.p2align 4, 0x90
.type __device_stub__my_dot_struct,@function
__device_stub__my_dot_struct: # @__device_stub__my_dot_struct
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %ecx, 4(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $my_dot_struct, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__my_dot_struct, .Lfunc_end1-__device_stub__my_dot_struct
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $my_dot, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $my_dot_struct, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type my_dot,@object # @my_dot
.section .rodata,"a",@progbits
.globl my_dot
.p2align 3, 0x0
my_dot:
.quad __device_stub__my_dot
.size my_dot, 8
.type my_dot_struct,@object # @my_dot_struct
.globl my_dot_struct
.p2align 3, 0x0
my_dot_struct:
.quad __device_stub__my_dot_struct
.size my_dot_struct, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "my_dot"
.size .L__unnamed_1, 7
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "my_dot_struct"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__my_dot
.addrsig_sym __device_stub__my_dot_struct
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym my_dot
.addrsig_sym my_dot_struct
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : my_dot_struct
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : my_dot
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected my_dot
.globl my_dot
.p2align 8
.type my_dot,@function
my_dot:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel my_dot
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size my_dot, .Lfunc_end0-my_dot
.section .AMDGPU.csdata,"",@progbits
.text
.protected my_dot_struct
.globl my_dot_struct
.p2align 8
.type my_dot_struct,@function
my_dot_struct:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel my_dot_struct
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size my_dot_struct, .Lfunc_end1-my_dot_struct
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: my_dot
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: my_dot.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: my_dot_struct
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: my_dot_struct.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b105f_00000000-6_nvrtc_test_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj
.type _Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj, @function
_Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq my_dot(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj, .-_Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj
.globl my_dot
.type my_dot, @function
my_dot:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6my_dotPKfS0_PfjPKfS0_Pfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size my_dot, .-my_dot
.globl _Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t
.type _Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t, @function
_Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rcx, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq my_dot_struct(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t, .-_Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t
.globl my_dot_struct
.type my_dot_struct, @function
my_dot_struct:
.LFB2054:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movl %ecx, 12(%rsp)
leaq 12(%rsp), %rcx
call _Z43__device_stub__Z13my_dot_structPKfS0_Pf3n_tPKfS0_PfRK3n_t
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size my_dot_struct, .-my_dot_struct
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "my_dot_struct"
.LC1:
.string "my_dot"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq my_dot_struct(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq my_dot(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nvrtc_test_dot.hip"
.globl __device_stub__my_dot # -- Begin function __device_stub__my_dot
.p2align 4, 0x90
.type __device_stub__my_dot,@function
__device_stub__my_dot: # @__device_stub__my_dot
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $my_dot, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__my_dot, .Lfunc_end0-__device_stub__my_dot
.cfi_endproc
# -- End function
.globl __device_stub__my_dot_struct # -- Begin function __device_stub__my_dot_struct
.p2align 4, 0x90
.type __device_stub__my_dot_struct,@function
__device_stub__my_dot_struct: # @__device_stub__my_dot_struct
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %ecx, 4(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $my_dot_struct, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__my_dot_struct, .Lfunc_end1-__device_stub__my_dot_struct
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $my_dot, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $my_dot_struct, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type my_dot,@object # @my_dot
.section .rodata,"a",@progbits
.globl my_dot
.p2align 3, 0x0
my_dot:
.quad __device_stub__my_dot
.size my_dot, 8
.type my_dot_struct,@object # @my_dot_struct
.globl my_dot_struct
.p2align 3, 0x0
my_dot_struct:
.quad __device_stub__my_dot_struct
.size my_dot_struct, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "my_dot"
.size .L__unnamed_1, 7
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "my_dot_struct"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__my_dot
.addrsig_sym __device_stub__my_dot_struct
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym my_dot
.addrsig_sym my_dot_struct
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d557a_00000000-6_sw4-reg-3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.type _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, @function
_Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
movq %rcx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq %r8, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
movq %r9, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
movq 288(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
movq 296(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, .-_Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.type _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, @function
_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, .-_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.globl _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.type _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, @function
_Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
movq %rcx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq %r8, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
movq %r9, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
movq 288(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
movq 296(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, .-_Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.type _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, @function
_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, .-_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.globl _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.type _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, @function
_Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
movq %rcx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq %r8, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
movq %r9, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
movq 288(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
movq 296(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, .-_Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.type _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, @function
_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, .-_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for uacc_0\n"
.align 8
.LC2:
.string "Failed to allocate device memory for uacc_1\n"
.align 8
.LC3:
.string "Failed to allocate device memory for uacc_2\n"
.align 8
.LC4:
.string "Failed to allocate device memory for u_0\n"
.align 8
.LC5:
.string "Failed to allocate device memory for u_1\n"
.align 8
.LC6:
.string "Failed to allocate device memory for u_2\n"
.align 8
.LC7:
.string "Failed to allocate device memory for mu\n"
.align 8
.LC8:
.string "Failed to allocate device memory for la\n"
.align 8
.LC9:
.string "Failed to allocate device memory for strx\n"
.align 8
.LC10:
.string "Failed to allocate device memory for stry\n"
.align 8
.LC11:
.string "Failed to allocate device memory for strz\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 256(%rsp), %r15
movq 264(%rsp), %r14
movq 272(%rsp), %r13
movq 280(%rsp), %rax
movq %rax, 48(%rsp)
movq 288(%rsp), %rbx
movq %rbx, 56(%rsp)
movl 296(%rsp), %r12d
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movslq %r12d, %rbp
movq %rbp, %rbx
imulq %rbp, %rbx
imulq %rbp, %rbx
salq $3, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC3(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC4(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC5(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC6(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC7(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
leaq 128(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC8(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
salq $3, %rbp
leaq 136(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC9(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
leaq 144(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC10(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
leaq 152(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC11(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 152(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 168(%rsp)
movl %r12d, %edx
shrl $3, %edx
movl %edx, %eax
addl $1, %eax
testb $7, %r12b
cmove %edx, %eax
movl %r12d, %ecx
shrl $4, %ecx
movl %ecx, %edx
addl $1, %edx
testb $15, %r12b
cmove %ecx, %edx
movl %edx, 172(%rsp)
movl %eax, 176(%rsp)
movl $1, 180(%rsp)
movl $16, 160(%rsp)
movl $8, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $1, %ecx
movq 172(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L36:
movl 168(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movq 172(%rsp), %rdi
movl 180(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L37:
movl 168(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movq 172(%rsp), %rdi
movl 180(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L38:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq %r12
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 160(%rsp)
.cfi_def_cfa_offset 288
pushq 160(%rsp)
.cfi_def_cfa_offset 296
pushq 160(%rsp)
.cfi_def_cfa_offset 304
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $48, %rsp
.cfi_def_cfa_offset 256
jmp .L36
.L42:
pushq %r12
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 160(%rsp)
.cfi_def_cfa_offset 288
pushq 160(%rsp)
.cfi_def_cfa_offset 296
pushq 160(%rsp)
.cfi_def_cfa_offset 304
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $48, %rsp
.cfi_def_cfa_offset 256
jmp .L37
.L43:
pushq %r12
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 160(%rsp)
.cfi_def_cfa_offset 288
pushq 160(%rsp)
.cfi_def_cfa_offset 296
pushq 160(%rsp)
.cfi_def_cfa_offset 304
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $48, %rsp
.cfi_def_cfa_offset 256
jmp .L38
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i"
.align 8
.LC13:
.string "_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i"
.align 8
.LC14:
.string "_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sw4-reg-3.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i,@function
_Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i: # @_Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end1:
.size _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end1-_Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i,@function
_Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i: # @_Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end2-_Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i,@function
_Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i: # @_Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end3:
.size _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end3-_Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 352(%rsp) # 8-byte Spill
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, 336(%rsp) # 8-byte Spill
movq %rsi, 344(%rsp) # 8-byte Spill
movq %rdi, %rbp
movslq 456(%rsp), %r12
leaq (,%r12,8), %r13
movq %r12, %r14
imulq %r12, %r14
imulq %r13, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 24(%rsp), %rdi
movq %rbp, 232(%rsp) # 8-byte Spill
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_4
# %bb.5: # %_Z11check_errorPKc.exit110
movq 16(%rsp), %rdi
movq 344(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_6
# %bb.7: # %_Z11check_errorPKc.exit112
movq 8(%rsp), %rdi
movq 336(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 88(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_8
# %bb.9: # %_Z11check_errorPKc.exit114
movq 88(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z11check_errorPKc.exit116
movq 80(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_12
# %bb.13: # %_Z11check_errorPKc.exit118
movq 72(%rsp), %rdi
movq 352(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
movq 232(%rsp), %rbx # 8-byte Reload
jne .LBB4_14
# %bb.15: # %_Z11check_errorPKc.exit120
movq 416(%rsp), %rsi
movq 64(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_16
# %bb.17: # %_Z11check_errorPKc.exit122
movq 424(%rsp), %rsi
movq 56(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_18
# %bb.19: # %_Z11check_errorPKc.exit124
movq 432(%rsp), %rsi
movq 48(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_20
# %bb.21: # %_Z11check_errorPKc.exit126
movq 440(%rsp), %rsi
movq 40(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_22
# %bb.23: # %_Z11check_errorPKc.exit128
movq 448(%rsp), %rsi
movabsq $34359738384, %rbp # imm = 0x800000010
movq 32(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %eax
shrl $4, %eax
leal 1(%rax), %ecx
testb $15, %r12b
cmovel %eax, %ecx
movl %r12d, %eax
shrl $3, %eax
leal 1(%rax), %r13d
testb $7, %r12b
cmovel %eax, %r13d
shlq $32, %r13
orq %rcx, %r13
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_25
# %bb.24:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
movq 72(%rsp), %r8
movq 64(%rsp), %r9
movq 56(%rsp), %r10
movq 48(%rsp), %r11
movq 40(%rsp), %rbx
movq 32(%rsp), %r15
movq %rax, 224(%rsp)
movq %rcx, 216(%rsp)
movq %rdx, 208(%rsp)
movq %rsi, 200(%rsp)
movq %rdi, 192(%rsp)
movq %r8, 184(%rsp)
movq %r9, 176(%rsp)
movq %r10, 168(%rsp)
movq %r11, 160(%rsp)
movq %rbx, 152(%rsp)
movq 232(%rsp), %rbx # 8-byte Reload
movq %r15, 144(%rsp)
movl %r12d, 4(%rsp)
leaq 224(%rsp), %rax
movq %rax, 240(%rsp)
leaq 216(%rsp), %rax
movq %rax, 248(%rsp)
leaq 208(%rsp), %rax
movq %rax, 256(%rsp)
leaq 200(%rsp), %rax
movq %rax, 264(%rsp)
leaq 192(%rsp), %rax
movq %rax, 272(%rsp)
leaq 184(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rax
movq %rax, 288(%rsp)
leaq 168(%rsp), %rax
movq %rax, 296(%rsp)
leaq 160(%rsp), %rax
movq %rax, 304(%rsp)
leaq 152(%rsp), %rax
movq %rax, 312(%rsp)
leaq 144(%rsp), %rax
movq %rax, 320(%rsp)
leaq 4(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_25:
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_27
# %bb.26:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
movq 72(%rsp), %r8
movq 64(%rsp), %r9
movq 56(%rsp), %r10
movq 48(%rsp), %r11
movq 40(%rsp), %rbx
movq 32(%rsp), %r15
movq %rax, 224(%rsp)
movq %rcx, 216(%rsp)
movq %rdx, 208(%rsp)
movq %rsi, 200(%rsp)
movq %rdi, 192(%rsp)
movq %r8, 184(%rsp)
movq %r9, 176(%rsp)
movq %r10, 168(%rsp)
movq %r11, 160(%rsp)
movq %rbx, 152(%rsp)
movq 232(%rsp), %rbx # 8-byte Reload
movq %r15, 144(%rsp)
movl %r12d, 4(%rsp)
leaq 224(%rsp), %rax
movq %rax, 240(%rsp)
leaq 216(%rsp), %rax
movq %rax, 248(%rsp)
leaq 208(%rsp), %rax
movq %rax, 256(%rsp)
leaq 200(%rsp), %rax
movq %rax, 264(%rsp)
leaq 192(%rsp), %rax
movq %rax, 272(%rsp)
leaq 184(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rax
movq %rax, 288(%rsp)
leaq 168(%rsp), %rax
movq %rax, 296(%rsp)
leaq 160(%rsp), %rax
movq %rax, 304(%rsp)
leaq 152(%rsp), %rax
movq %rax, 312(%rsp)
leaq 144(%rsp), %rax
movq %rax, 320(%rsp)
leaq 4(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_27:
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_29
# %bb.28:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
movq 72(%rsp), %r8
movq 64(%rsp), %r9
movq 56(%rsp), %r10
movq 48(%rsp), %r11
movq 40(%rsp), %rbx
movq 32(%rsp), %r15
movq %rax, 224(%rsp)
movq %rcx, 216(%rsp)
movq %rdx, 208(%rsp)
movq %rsi, 200(%rsp)
movq %rdi, 192(%rsp)
movq %r8, 184(%rsp)
movq %r9, 176(%rsp)
movq %r10, 168(%rsp)
movq %r11, 160(%rsp)
movq %rbx, 152(%rsp)
movq 232(%rsp), %rbx # 8-byte Reload
movq %r15, 144(%rsp)
movl %r12d, 4(%rsp)
leaq 224(%rsp), %rax
movq %rax, 240(%rsp)
leaq 216(%rsp), %rax
movq %rax, 248(%rsp)
leaq 208(%rsp), %rax
movq %rax, 256(%rsp)
leaq 200(%rsp), %rax
movq %rax, 264(%rsp)
leaq 192(%rsp), %rax
movq %rax, 272(%rsp)
leaq 184(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rax
movq %rax, 288(%rsp)
leaq 168(%rsp), %rax
movq %rax, 296(%rsp)
leaq 160(%rsp), %rax
movq %rax, 304(%rsp)
leaq 152(%rsp), %rax
movq %rax, 312(%rsp)
leaq 144(%rsp), %rax
movq %rax, 320(%rsp)
leaq 4(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_29:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq 344(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq 336(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 416
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB4_2
.LBB4_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
jmp .LBB4_2
.LBB4_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.3, %esi
jmp .LBB4_2
.LBB4_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.4, %esi
jmp .LBB4_2
.LBB4_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.5, %esi
jmp .LBB4_2
.LBB4_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.6, %esi
jmp .LBB4_2
.LBB4_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.7, %esi
jmp .LBB4_2
.LBB4_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.8, %esi
jmp .LBB4_2
.LBB4_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.9, %esi
jmp .LBB4_2
.LBB4_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.10, %esi
jmp .LBB4_2
.LBB4_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.11, %esi
.LBB4_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end4:
.size host_code, .Lfunc_end4-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i,@object # @_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i:
.quad _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.size _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, 8
.type _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i,@object # @_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i:
.quad _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.size _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, 8
.type _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i,@object # @_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i:
.quad _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.size _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for uacc_0\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for uacc_1\n"
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device memory for uacc_2\n"
.size .L.str.3, 45
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device memory for u_0\n"
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device memory for u_1\n"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device memory for u_2\n"
.size .L.str.6, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device memory for mu\n"
.size .L.str.7, 41
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device memory for la\n"
.size .L.str.8, 41
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to allocate device memory for strx\n"
.size .L.str.9, 43
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to allocate device memory for stry\n"
.size .L.str.10, 43
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to allocate device memory for strz\n"
.size .L.str.11, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void k2(const int N, bool* visited, int* frontier, bool* new_frontier, bool* augFound) {
int count = 0;
for(int i=0;i<N;i++) {
if(new_frontier[i]) {
new_frontier[i] = false;
frontier[++count] = i;
visited[i] = true;
}
}
frontier[0] = count;
//Complete search if sink has been reached
for(int i = 0; i < frontier[0]; i++)
if(frontier[i + 1] == (N - 1))
augFound[0] = true;
} | code for sm_80
Function : _Z2k2iPbPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff077624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0040*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 BRA 0x5e0 ; /* 0x0000058000008947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R7.reuse, -0x1, RZ ; /* 0xffffffff07007810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0080*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fe400078ec0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*00b0*/ @!P0 BRA 0x440 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R9, R7, -c[0x0][0x160], RZ ; /* 0x8000580007097a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0120*/ LDG.E.U8 R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea2000c1e1100 */
/*0130*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0150*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*0160*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b0424 */
/* 0x000fe200078e00ff */
/*0170*/ @P0 STG.E.U8 [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x000fe6000c10110a */
/*0180*/ @P0 IMAD.WIDE R10, R0, R11, c[0x0][0x170] ; /* 0x00005c00000a0625 */
/* 0x000fca00078e020b */
/*0190*/ @P0 STG.E [R10.64], R6 ; /* 0x000000060a000986 */
/* 0x0001e8000c10190a */
/*01a0*/ @P0 STG.E.U8 [R4.64], R13 ; /* 0x0000000d04000986 */
/* 0x0003e8000c10110a */
/*01b0*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010a02087981 */
/* 0x000ea4000c1e1100 */
/*01c0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fe20003f05270 */
/*01d0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fd800078e00ff */
/*01e0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff110424 */
/* 0x000fe200078e00ff */
/*0200*/ @P0 IADD3 R15, R6, 0x1, RZ ; /* 0x00000001060f0810 */
/* 0x000fe20007ffe0ff */
/*0210*/ @P0 STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02000986 */
/* 0x000fe2000c10110a */
/*0220*/ @P0 PRMT R11, R8, 0x7610, R11 ; /* 0x00007610080b0816 */
/* 0x001fe2000000000b */
/*0230*/ @P0 IMAD.WIDE R12, R0, R17, c[0x0][0x170] ; /* 0x00005c00000c0625 */
/* 0x002fca00078e0211 */
/*0240*/ @P0 STG.E [R12.64], R15 ; /* 0x0000000f0c000986 */
/* 0x0001e8000c10190a */
/*0250*/ @P0 STG.E.U8 [R4.64+0x1], R11 ; /* 0x0000010b04000986 */
/* 0x0003e8000c10110a */
/*0260*/ LDG.E.U8 R8, [R2.64+0x2] ; /* 0x0000020a02087981 */
/* 0x000ea4000c1e1100 */
/*0270*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fe20003f05270 */
/*0280*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fd800078e00ff */
/*0290*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff130424 */
/* 0x000fe200078e00ff */
/*02b0*/ @P0 IADD3 R17, R6, 0x2, RZ ; /* 0x0000000206110810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ @P0 STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02000986 */
/* 0x0005e2000c10110a */
/*02d0*/ @P0 PRMT R13, R8, 0x7610, R13 ; /* 0x00007610080d0816 */
/* 0x001fe2000000000d */
/*02e0*/ @P0 IMAD.WIDE R10, R0, R19, c[0x0][0x170] ; /* 0x00005c00000a0625 */
/* 0x002fca00078e0213 */
/*02f0*/ @P0 STG.E [R10.64], R17 ; /* 0x000000110a000986 */
/* 0x0005e8000c10190a */
/*0300*/ @P0 STG.E.U8 [R4.64+0x2], R13 ; /* 0x0000020d04000986 */
/* 0x0005e8000c10110a */
/*0310*/ LDG.E.U8 R8, [R2.64+0x3] ; /* 0x0000030a02087981 */
/* 0x000ee4000c1e1100 */
/*0320*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x008fda0003f05270 */
/*0330*/ @!P0 BRA 0x3c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x004fe20007ffe0ff */
/*0350*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0360*/ IADD3 R13, R6, 0x3, RZ ; /* 0x00000003060d7810 */
/* 0x000fe20007ffe0ff */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*0380*/ STG.E.U8 [R2.64+0x3], RZ ; /* 0x000003ff02007986 */
/* 0x0001e2000c10110a */
/*0390*/ IMAD.WIDE R10, R0, R11, c[0x0][0x170] ; /* 0x00005c00000a7625 */
/* 0x000fca00078e020b */
/*03a0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001e8000c10190a */
/*03b0*/ STG.E.U8 [R4.64+0x3], R8 ; /* 0x0000030804007986 */
/* 0x0001e4000c10110a */
/*03c0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x004fe40007ffe0ff */
/*03d0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f3e0ff */
/*03e0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007f5e0ff */
/*03f0*/ IMAD.IADD R8, R9, 0x1, R6 ; /* 0x0000000109087824 */
/* 0x000fe400078e0206 */
/*0400*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fc400008e0603 */
/*0410*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0420*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0430*/ @P0 BRA 0x120 ; /* 0xfffffce000000947 */
/* 0x000fea000383ffff */
/*0440*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0450*/ @!P0 BRA 0x5e0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R4, P0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f1e0ff */
/*0470*/ IADD3 R10, P1, R6, c[0x0][0x178], RZ ; /* 0x00005e00060a7a10 */
/* 0x000fe40007f3e0ff */
/*0480*/ SHF.R.S32.HI R2, RZ, 0x1f, R6 ; /* 0x0000001fff027819 */
/* 0x000fc80000011406 */
/*0490*/ IADD3.X R5, R2.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0002057a10 */
/* 0x040fe400007fe4ff */
/*04a0*/ IADD3.X R3, R2, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f0002037a10 */
/* 0x000fe40000ffe4ff */
/*04b0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fca00078e000a */
/*04c0*/ LDG.E.U8 R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea2000c1e1100 */
/*04d0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ IADD3 R10, P1, R2, 0x1, RZ ; /* 0x00000001020a7810 */
/* 0x000fe40007f3e0ff */
/*04f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0500*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f45270 */
/*0510*/ @!P2 BRA 0x590 ; /* 0x000000700000a947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0530*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0540*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c10110a */
/*0550*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fca00078e0209 */
/*0570*/ STG.E [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0001e8000c10190a */
/*0580*/ STG.E.U8 [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c10110a */
/*0590*/ IADD3 R4, P2, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x001fe20007f5e0ff */
/*05a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*05b0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*05d0*/ @P0 BRA 0x4b0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*05e0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*05f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0610*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001ea000c10190a */
/*0620*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0630*/ UMOV UR6, 0x1 ; /* 0x0000000100067882 */
/* 0x000fe40000000000 */
/*0640*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0650*/ UIADD3 UR6, -UR6, UR4, URZ ; /* 0x0000000406067290 */
/* 0x000fe4000fffe13f */
/*0660*/ UMOV UR12, 0x4 ; /* 0x00000004000c7882 */
/* 0x000fc40000000000 */
/*0670*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0680*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0690*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*06a0*/ UIADD3 UR7, UP0, UR12, UR8, URZ ; /* 0x000000080c077290 */
/* 0x000fc8000ff1e03f */
/*06b0*/ UIADD3.X UR8, UR5, UR9, URZ, UP0, !UPT ; /* 0x0000000905087290 */
/* 0x000fe400087fe43f */
/*06c0*/ IMAD.U32 R4, RZ, RZ, UR7 ; /* 0x00000007ff047e24 */
/* 0x002fc8000f8e00ff */
/*06d0*/ IMAD.U32 R5, RZ, RZ, UR8 ; /* 0x00000008ff057e24 */
/* 0x000fca000f8e00ff */
/*06e0*/ LDG.E R4, [R4.64] ; /* 0x0000000a04047981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0700*/ UIADD3 UR12, UP0, UR12, 0x4, URZ ; /* 0x000000040c0c7890 */
/* 0x000fe2000ff1e03f */
/*0710*/ ISETP.NE.AND P0, PT, R4, UR6, PT ; /* 0x0000000604007c0c */
/* 0x004fda000bf05270 */
/*0720*/ @P0 BRA 0x780 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0730*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe400078e00ff */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe400078e00ff */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fca00078e00ff */
/*0760*/ STG.E.U8 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0003e8000c10110a */
/*0770*/ LDG.E R0, [R2.64] ; /* 0x0000000a02007981 */
/* 0x001364000c1e1900 */
/*0780*/ ISETP.LE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x020fe2000bf03270 */
/*0790*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fd800087fe43f */
/*07a0*/ @!P0 BRA 0x690 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*07b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07c0*/ BRA 0x7c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void k2(const int N, bool* visited, int* frontier, bool* new_frontier, bool* augFound) {
int count = 0;
for(int i=0;i<N;i++) {
if(new_frontier[i]) {
new_frontier[i] = false;
frontier[++count] = i;
visited[i] = true;
}
}
frontier[0] = count;
//Complete search if sink has been reached
for(int i = 0; i < frontier[0]; i++)
if(frontier[i + 1] == (N - 1))
augFound[0] = true;
} | .file "tmpxft_000a6485_00000000-6_k2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_
.type _Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_, @function
_Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z2k2iPbPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_, .-_Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_
.globl _Z2k2iPbPiS_S_
.type _Z2k2iPbPiS_S_, @function
_Z2k2iPbPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2k2iPbPiS_S_, .-_Z2k2iPbPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2k2iPbPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2k2iPbPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void k2(const int N, bool* visited, int* frontier, bool* new_frontier, bool* augFound) {
int count = 0;
for(int i=0;i<N;i++) {
if(new_frontier[i]) {
new_frontier[i] = false;
frontier[++count] = i;
visited[i] = true;
}
}
frontier[0] = count;
//Complete search if sink has been reached
for(int i = 0; i < frontier[0]; i++)
if(frontier[i + 1] == (N - 1))
augFound[0] = true;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void k2(const int N, bool* visited, int* frontier, bool* new_frontier, bool* augFound) {
int count = 0;
for(int i=0;i<N;i++) {
if(new_frontier[i]) {
new_frontier[i] = false;
frontier[++count] = i;
visited[i] = true;
}
}
frontier[0] = count;
//Complete search if sink has been reached
for(int i = 0; i < frontier[0]; i++)
if(frontier[i + 1] == (N - 1))
augFound[0] = true;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void k2(const int N, bool* visited, int* frontier, bool* new_frontier, bool* augFound) {
int count = 0;
for(int i=0;i<N;i++) {
if(new_frontier[i]) {
new_frontier[i] = false;
frontier[++count] = i;
visited[i] = true;
}
}
frontier[0] = count;
//Complete search if sink has been reached
for(int i = 0; i < frontier[0]; i++)
if(frontier[i + 1] == (N - 1))
augFound[0] = true;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2k2iPbPiS_S_
.globl _Z2k2iPbPiS_S_
.p2align 8
.type _Z2k2iPbPiS_S_,@function
_Z2k2iPbPiS_S_:
s_clause 0x1
s_load_b32 s14, s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s14, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x18
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 1
s_mov_b32 s2, 0
s_mov_b64 s[10:11], 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_u32 s10, s10, 1
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s14, s10
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_add_u32 s12, s8, s10
s_addc_u32 s13, s9, s11
global_load_u8 v1, v0, s[12:13]
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v1
s_cbranch_vccnz .LBB0_2
s_add_i32 s2, s2, 1
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s10
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[2:3], 2
s_add_u32 s16, s4, s16
s_addc_u32 s17, s5, s17
s_add_u32 s18, s6, s10
s_addc_u32 s19, s7, s11
s_clause 0x2
global_store_b8 v0, v1, s[12:13]
global_store_b32 v0, v2, s[16:17]
global_store_b8 v0, v3, s[18:19]
s_branch .LBB0_2
.LBB0_5:
s_mov_b32 s2, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_cmp_lt_i32 s2, 1
global_store_b32 v0, v1, s[4:5]
s_cbranch_scc1 .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x20
s_add_i32 s3, s14, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_branch .LBB0_9
.LBB0_8:
s_add_i32 s2, s2, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_11
.LBB0_9:
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, s3, v1
s_cbranch_vccnz .LBB0_8
v_mov_b32_e32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b8 v0, v1, s[0:1]
s_branch .LBB0_8
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2k2iPbPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2k2iPbPiS_S_, .Lfunc_end0-_Z2k2iPbPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2k2iPbPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z2k2iPbPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void k2(const int N, bool* visited, int* frontier, bool* new_frontier, bool* augFound) {
int count = 0;
for(int i=0;i<N;i++) {
if(new_frontier[i]) {
new_frontier[i] = false;
frontier[++count] = i;
visited[i] = true;
}
}
frontier[0] = count;
//Complete search if sink has been reached
for(int i = 0; i < frontier[0]; i++)
if(frontier[i + 1] == (N - 1))
augFound[0] = true;
} | .text
.file "k2.hip"
.globl _Z17__device_stub__k2iPbPiS_S_ # -- Begin function _Z17__device_stub__k2iPbPiS_S_
.p2align 4, 0x90
.type _Z17__device_stub__k2iPbPiS_S_,@function
_Z17__device_stub__k2iPbPiS_S_: # @_Z17__device_stub__k2iPbPiS_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z2k2iPbPiS_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z17__device_stub__k2iPbPiS_S_, .Lfunc_end0-_Z17__device_stub__k2iPbPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2k2iPbPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2k2iPbPiS_S_,@object # @_Z2k2iPbPiS_S_
.section .rodata,"a",@progbits
.globl _Z2k2iPbPiS_S_
.p2align 3, 0x0
_Z2k2iPbPiS_S_:
.quad _Z17__device_stub__k2iPbPiS_S_
.size _Z2k2iPbPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2k2iPbPiS_S_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__k2iPbPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2k2iPbPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2k2iPbPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff077624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0040*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 BRA 0x5e0 ; /* 0x0000058000008947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R7.reuse, -0x1, RZ ; /* 0xffffffff07007810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0080*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fe400078ec0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*00b0*/ @!P0 BRA 0x440 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R9, R7, -c[0x0][0x160], RZ ; /* 0x8000580007097a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0120*/ LDG.E.U8 R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea2000c1e1100 */
/*0130*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0150*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*0160*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b0424 */
/* 0x000fe200078e00ff */
/*0170*/ @P0 STG.E.U8 [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x000fe6000c10110a */
/*0180*/ @P0 IMAD.WIDE R10, R0, R11, c[0x0][0x170] ; /* 0x00005c00000a0625 */
/* 0x000fca00078e020b */
/*0190*/ @P0 STG.E [R10.64], R6 ; /* 0x000000060a000986 */
/* 0x0001e8000c10190a */
/*01a0*/ @P0 STG.E.U8 [R4.64], R13 ; /* 0x0000000d04000986 */
/* 0x0003e8000c10110a */
/*01b0*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010a02087981 */
/* 0x000ea4000c1e1100 */
/*01c0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fe20003f05270 */
/*01d0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fd800078e00ff */
/*01e0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff110424 */
/* 0x000fe200078e00ff */
/*0200*/ @P0 IADD3 R15, R6, 0x1, RZ ; /* 0x00000001060f0810 */
/* 0x000fe20007ffe0ff */
/*0210*/ @P0 STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02000986 */
/* 0x000fe2000c10110a */
/*0220*/ @P0 PRMT R11, R8, 0x7610, R11 ; /* 0x00007610080b0816 */
/* 0x001fe2000000000b */
/*0230*/ @P0 IMAD.WIDE R12, R0, R17, c[0x0][0x170] ; /* 0x00005c00000c0625 */
/* 0x002fca00078e0211 */
/*0240*/ @P0 STG.E [R12.64], R15 ; /* 0x0000000f0c000986 */
/* 0x0001e8000c10190a */
/*0250*/ @P0 STG.E.U8 [R4.64+0x1], R11 ; /* 0x0000010b04000986 */
/* 0x0003e8000c10110a */
/*0260*/ LDG.E.U8 R8, [R2.64+0x2] ; /* 0x0000020a02087981 */
/* 0x000ea4000c1e1100 */
/*0270*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fe20003f05270 */
/*0280*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fd800078e00ff */
/*0290*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff130424 */
/* 0x000fe200078e00ff */
/*02b0*/ @P0 IADD3 R17, R6, 0x2, RZ ; /* 0x0000000206110810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ @P0 STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02000986 */
/* 0x0005e2000c10110a */
/*02d0*/ @P0 PRMT R13, R8, 0x7610, R13 ; /* 0x00007610080d0816 */
/* 0x001fe2000000000d */
/*02e0*/ @P0 IMAD.WIDE R10, R0, R19, c[0x0][0x170] ; /* 0x00005c00000a0625 */
/* 0x002fca00078e0213 */
/*02f0*/ @P0 STG.E [R10.64], R17 ; /* 0x000000110a000986 */
/* 0x0005e8000c10190a */
/*0300*/ @P0 STG.E.U8 [R4.64+0x2], R13 ; /* 0x0000020d04000986 */
/* 0x0005e8000c10110a */
/*0310*/ LDG.E.U8 R8, [R2.64+0x3] ; /* 0x0000030a02087981 */
/* 0x000ee4000c1e1100 */
/*0320*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x008fda0003f05270 */
/*0330*/ @!P0 BRA 0x3c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x004fe20007ffe0ff */
/*0350*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0360*/ IADD3 R13, R6, 0x3, RZ ; /* 0x00000003060d7810 */
/* 0x000fe20007ffe0ff */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*0380*/ STG.E.U8 [R2.64+0x3], RZ ; /* 0x000003ff02007986 */
/* 0x0001e2000c10110a */
/*0390*/ IMAD.WIDE R10, R0, R11, c[0x0][0x170] ; /* 0x00005c00000a7625 */
/* 0x000fca00078e020b */
/*03a0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001e8000c10190a */
/*03b0*/ STG.E.U8 [R4.64+0x3], R8 ; /* 0x0000030804007986 */
/* 0x0001e4000c10110a */
/*03c0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x004fe40007ffe0ff */
/*03d0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f3e0ff */
/*03e0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007f5e0ff */
/*03f0*/ IMAD.IADD R8, R9, 0x1, R6 ; /* 0x0000000109087824 */
/* 0x000fe400078e0206 */
/*0400*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fc400008e0603 */
/*0410*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0420*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0430*/ @P0 BRA 0x120 ; /* 0xfffffce000000947 */
/* 0x000fea000383ffff */
/*0440*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0450*/ @!P0 BRA 0x5e0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R4, P0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f1e0ff */
/*0470*/ IADD3 R10, P1, R6, c[0x0][0x178], RZ ; /* 0x00005e00060a7a10 */
/* 0x000fe40007f3e0ff */
/*0480*/ SHF.R.S32.HI R2, RZ, 0x1f, R6 ; /* 0x0000001fff027819 */
/* 0x000fc80000011406 */
/*0490*/ IADD3.X R5, R2.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0002057a10 */
/* 0x040fe400007fe4ff */
/*04a0*/ IADD3.X R3, R2, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f0002037a10 */
/* 0x000fe40000ffe4ff */
/*04b0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fca00078e000a */
/*04c0*/ LDG.E.U8 R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea2000c1e1100 */
/*04d0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ IADD3 R10, P1, R2, 0x1, RZ ; /* 0x00000001020a7810 */
/* 0x000fe40007f3e0ff */
/*04f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0500*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f45270 */
/*0510*/ @!P2 BRA 0x590 ; /* 0x000000700000a947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0530*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0540*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c10110a */
/*0550*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fca00078e0209 */
/*0570*/ STG.E [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0001e8000c10190a */
/*0580*/ STG.E.U8 [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c10110a */
/*0590*/ IADD3 R4, P2, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x001fe20007f5e0ff */
/*05a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*05b0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*05d0*/ @P0 BRA 0x4b0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*05e0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*05f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0610*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001ea000c10190a */
/*0620*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0630*/ UMOV UR6, 0x1 ; /* 0x0000000100067882 */
/* 0x000fe40000000000 */
/*0640*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0650*/ UIADD3 UR6, -UR6, UR4, URZ ; /* 0x0000000406067290 */
/* 0x000fe4000fffe13f */
/*0660*/ UMOV UR12, 0x4 ; /* 0x00000004000c7882 */
/* 0x000fc40000000000 */
/*0670*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0680*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0690*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*06a0*/ UIADD3 UR7, UP0, UR12, UR8, URZ ; /* 0x000000080c077290 */
/* 0x000fc8000ff1e03f */
/*06b0*/ UIADD3.X UR8, UR5, UR9, URZ, UP0, !UPT ; /* 0x0000000905087290 */
/* 0x000fe400087fe43f */
/*06c0*/ IMAD.U32 R4, RZ, RZ, UR7 ; /* 0x00000007ff047e24 */
/* 0x002fc8000f8e00ff */
/*06d0*/ IMAD.U32 R5, RZ, RZ, UR8 ; /* 0x00000008ff057e24 */
/* 0x000fca000f8e00ff */
/*06e0*/ LDG.E R4, [R4.64] ; /* 0x0000000a04047981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0700*/ UIADD3 UR12, UP0, UR12, 0x4, URZ ; /* 0x000000040c0c7890 */
/* 0x000fe2000ff1e03f */
/*0710*/ ISETP.NE.AND P0, PT, R4, UR6, PT ; /* 0x0000000604007c0c */
/* 0x004fda000bf05270 */
/*0720*/ @P0 BRA 0x780 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0730*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe400078e00ff */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe400078e00ff */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fca00078e00ff */
/*0760*/ STG.E.U8 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0003e8000c10110a */
/*0770*/ LDG.E R0, [R2.64] ; /* 0x0000000a02007981 */
/* 0x001364000c1e1900 */
/*0780*/ ISETP.LE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x020fe2000bf03270 */
/*0790*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fd800087fe43f */
/*07a0*/ @!P0 BRA 0x690 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*07b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07c0*/ BRA 0x7c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2k2iPbPiS_S_
.globl _Z2k2iPbPiS_S_
.p2align 8
.type _Z2k2iPbPiS_S_,@function
_Z2k2iPbPiS_S_:
s_clause 0x1
s_load_b32 s14, s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s14, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x18
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 1
s_mov_b32 s2, 0
s_mov_b64 s[10:11], 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_u32 s10, s10, 1
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s14, s10
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_add_u32 s12, s8, s10
s_addc_u32 s13, s9, s11
global_load_u8 v1, v0, s[12:13]
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v1
s_cbranch_vccnz .LBB0_2
s_add_i32 s2, s2, 1
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s10
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[2:3], 2
s_add_u32 s16, s4, s16
s_addc_u32 s17, s5, s17
s_add_u32 s18, s6, s10
s_addc_u32 s19, s7, s11
s_clause 0x2
global_store_b8 v0, v1, s[12:13]
global_store_b32 v0, v2, s[16:17]
global_store_b8 v0, v3, s[18:19]
s_branch .LBB0_2
.LBB0_5:
s_mov_b32 s2, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_cmp_lt_i32 s2, 1
global_store_b32 v0, v1, s[4:5]
s_cbranch_scc1 .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x20
s_add_i32 s3, s14, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_branch .LBB0_9
.LBB0_8:
s_add_i32 s2, s2, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_11
.LBB0_9:
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, s3, v1
s_cbranch_vccnz .LBB0_8
v_mov_b32_e32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b8 v0, v1, s[0:1]
s_branch .LBB0_8
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2k2iPbPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2k2iPbPiS_S_, .Lfunc_end0-_Z2k2iPbPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2k2iPbPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z2k2iPbPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a6485_00000000-6_k2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_
.type _Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_, @function
_Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z2k2iPbPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_, .-_Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_
.globl _Z2k2iPbPiS_S_
.type _Z2k2iPbPiS_S_, @function
_Z2k2iPbPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z2k2iPbPiS_S_iPbPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2k2iPbPiS_S_, .-_Z2k2iPbPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2k2iPbPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2k2iPbPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "k2.hip"
.globl _Z17__device_stub__k2iPbPiS_S_ # -- Begin function _Z17__device_stub__k2iPbPiS_S_
.p2align 4, 0x90
.type _Z17__device_stub__k2iPbPiS_S_,@function
_Z17__device_stub__k2iPbPiS_S_: # @_Z17__device_stub__k2iPbPiS_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z2k2iPbPiS_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z17__device_stub__k2iPbPiS_S_, .Lfunc_end0-_Z17__device_stub__k2iPbPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2k2iPbPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2k2iPbPiS_S_,@object # @_Z2k2iPbPiS_S_
.section .rodata,"a",@progbits
.globl _Z2k2iPbPiS_S_
.p2align 3, 0x0
_Z2k2iPbPiS_S_:
.quad _Z17__device_stub__k2iPbPiS_S_
.size _Z2k2iPbPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2k2iPbPiS_S_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__k2iPbPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2k2iPbPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
//All three kernels run 512 threads per workgroup
//Must be a power of two
#define THREADBLOCK_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// Basic scan codelets
////////////////////////////////////////////////////////////////////////////////
//Naive inclusive scan: O(N * log2(N)) operations
//Allocate 2 * 'size' local memory, initialize the first half
//with 'size' zeros avoiding if(pos >= offset) condition evaluation
//and saving instructions
__global__ void uniformUpdate( uint4 *d_Data, uint *d_Buffer )
{
__shared__ uint buf;
uint pos = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0)
{
buf = d_Buffer[blockIdx.x];
}
__syncthreads();
uint4 data4 = d_Data[pos];
data4.x += buf;
data4.y += buf;
data4.z += buf;
data4.w += buf;
d_Data[pos] = data4;
} | code for sm_80
Function : _Z13uniformUpdateP5uint4Pj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0xf0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0060*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x001fe20003f05270 */
/*0070*/ IMAD R4, R2, c[0x0][0x0], R3 ; /* 0x0000000002047a24 */
/* 0x002fca00078e0203 */
/*0080*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fce00078e0005 */
/*0090*/ @P0 BRA 0xe0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0003 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e40000000800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDG.E.128 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1d00 */
/*0110*/ LDS R0, [RZ] ; /* 0x00000000ff007984 */
/* 0x000ea40000000800 */
/*0120*/ IADD3 R11, R11, R0.reuse, RZ ; /* 0x000000000b0b7210 */
/* 0x084fe20007ffe0ff */
/*0130*/ IMAD.IADD R10, R10, 0x1, R0 ; /* 0x000000010a0a7824 */
/* 0x000fe200078e0200 */
/*0140*/ IADD3 R9, R9, R0, RZ ; /* 0x0000000009097210 */
/* 0x000fc40007ffe0ff */
/*0150*/ IADD3 R8, R8, R0, RZ ; /* 0x0000000008087210 */
/* 0x000fca0007ffe0ff */
/*0160*/ STG.E.128 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x000fe2000c101d04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
//All three kernels run 512 threads per workgroup
//Must be a power of two
#define THREADBLOCK_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// Basic scan codelets
////////////////////////////////////////////////////////////////////////////////
//Naive inclusive scan: O(N * log2(N)) operations
//Allocate 2 * 'size' local memory, initialize the first half
//with 'size' zeros avoiding if(pos >= offset) condition evaluation
//and saving instructions
__global__ void uniformUpdate( uint4 *d_Data, uint *d_Buffer )
{
__shared__ uint buf;
uint pos = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0)
{
buf = d_Buffer[blockIdx.x];
}
__syncthreads();
uint4 data4 = d_Data[pos];
data4.x += buf;
data4.y += buf;
data4.z += buf;
data4.w += buf;
d_Data[pos] = data4;
} | .file "tmpxft_000ae386_00000000-6_uniformUpdate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj
.type _Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj, @function
_Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13uniformUpdateP5uint4Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj, .-_Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj
.globl _Z13uniformUpdateP5uint4Pj
.type _Z13uniformUpdateP5uint4Pj, @function
_Z13uniformUpdateP5uint4Pj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13uniformUpdateP5uint4Pj, .-_Z13uniformUpdateP5uint4Pj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13uniformUpdateP5uint4Pj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13uniformUpdateP5uint4Pj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
//All three kernels run 512 threads per workgroup
//Must be a power of two
#define THREADBLOCK_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// Basic scan codelets
////////////////////////////////////////////////////////////////////////////////
//Naive inclusive scan: O(N * log2(N)) operations
//Allocate 2 * 'size' local memory, initialize the first half
//with 'size' zeros avoiding if(pos >= offset) condition evaluation
//and saving instructions
__global__ void uniformUpdate( uint4 *d_Data, uint *d_Buffer )
{
__shared__ uint buf;
uint pos = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0)
{
buf = d_Buffer[blockIdx.x];
}
__syncthreads();
uint4 data4 = d_Data[pos];
data4.x += buf;
data4.y += buf;
data4.z += buf;
data4.w += buf;
d_Data[pos] = data4;
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
//All three kernels run 512 threads per workgroup
//Must be a power of two
#define THREADBLOCK_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// Basic scan codelets
////////////////////////////////////////////////////////////////////////////////
//Naive inclusive scan: O(N * log2(N)) operations
//Allocate 2 * 'size' local memory, initialize the first half
//with 'size' zeros avoiding if(pos >= offset) condition evaluation
//and saving instructions
__global__ void uniformUpdate( uint4 *d_Data, uint *d_Buffer )
{
__shared__ uint buf;
uint pos = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0)
{
buf = d_Buffer[blockIdx.x];
}
__syncthreads();
uint4 data4 = d_Data[pos];
data4.x += buf;
data4.y += buf;
data4.z += buf;
data4.w += buf;
d_Data[pos] = data4;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
//All three kernels run 512 threads per workgroup
//Must be a power of two
#define THREADBLOCK_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// Basic scan codelets
////////////////////////////////////////////////////////////////////////////////
//Naive inclusive scan: O(N * log2(N)) operations
//Allocate 2 * 'size' local memory, initialize the first half
//with 'size' zeros avoiding if(pos >= offset) condition evaluation
//and saving instructions
__global__ void uniformUpdate( uint4 *d_Data, uint *d_Buffer )
{
__shared__ uint buf;
uint pos = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0)
{
buf = d_Buffer[blockIdx.x];
}
__syncthreads();
uint4 data4 = d_Data[pos];
data4.x += buf;
data4.y += buf;
data4.z += buf;
data4.w += buf;
d_Data[pos] = data4;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.globl _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.p2align 8
.type _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj,@function
_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj:
s_load_b32 s4, s[0:1], 0x1c
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x8
s_lshl_b64 s[8:9], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, 0xffff, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s2, s3, v[0:1]
v_mov_b32_e32 v4, 0
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[0:1], 4, v[3:4]
ds_load_b32 v4, v4
v_add_co_u32 v5, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v1, vcc_lo
global_load_b128 v[0:3], v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
v_add_nc_u32_e32 v1, v4, v1
v_add_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v3, v4, v3
global_store_b128 v[5:6], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj, .Lfunc_end0-_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
//All three kernels run 512 threads per workgroup
//Must be a power of two
#define THREADBLOCK_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// Basic scan codelets
////////////////////////////////////////////////////////////////////////////////
//Naive inclusive scan: O(N * log2(N)) operations
//Allocate 2 * 'size' local memory, initialize the first half
//with 'size' zeros avoiding if(pos >= offset) condition evaluation
//and saving instructions
__global__ void uniformUpdate( uint4 *d_Data, uint *d_Buffer )
{
__shared__ uint buf;
uint pos = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0)
{
buf = d_Buffer[blockIdx.x];
}
__syncthreads();
uint4 data4 = d_Data[pos];
data4.x += buf;
data4.y += buf;
data4.z += buf;
data4.w += buf;
d_Data[pos] = data4;
} | .text
.file "uniformUpdate.hip"
.globl _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj # -- Begin function _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.p2align 4, 0x90
.type _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj,@function
_Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj: # @_Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj, .Lfunc_end0-_Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj,@object # @_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.section .rodata,"a",@progbits
.globl _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.p2align 3, 0x0
_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj:
.quad _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.size _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13uniformUpdateP5uint4Pj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0xf0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0060*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x001fe20003f05270 */
/*0070*/ IMAD R4, R2, c[0x0][0x0], R3 ; /* 0x0000000002047a24 */
/* 0x002fca00078e0203 */
/*0080*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fce00078e0005 */
/*0090*/ @P0 BRA 0xe0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0003 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e40000000800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDG.E.128 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1d00 */
/*0110*/ LDS R0, [RZ] ; /* 0x00000000ff007984 */
/* 0x000ea40000000800 */
/*0120*/ IADD3 R11, R11, R0.reuse, RZ ; /* 0x000000000b0b7210 */
/* 0x084fe20007ffe0ff */
/*0130*/ IMAD.IADD R10, R10, 0x1, R0 ; /* 0x000000010a0a7824 */
/* 0x000fe200078e0200 */
/*0140*/ IADD3 R9, R9, R0, RZ ; /* 0x0000000009097210 */
/* 0x000fc40007ffe0ff */
/*0150*/ IADD3 R8, R8, R0, RZ ; /* 0x0000000008087210 */
/* 0x000fca0007ffe0ff */
/*0160*/ STG.E.128 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x000fe2000c101d04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.globl _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.p2align 8
.type _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj,@function
_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj:
s_load_b32 s4, s[0:1], 0x1c
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x8
s_lshl_b64 s[8:9], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, 0xffff, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s2, s3, v[0:1]
v_mov_b32_e32 v4, 0
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[0:1], 4, v[3:4]
ds_load_b32 v4, v4
v_add_co_u32 v5, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v1, vcc_lo
global_load_b128 v[0:3], v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
v_add_nc_u32_e32 v1, v4, v1
v_add_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v3, v4, v3
global_store_b128 v[5:6], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj, .Lfunc_end0-_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ae386_00000000-6_uniformUpdate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj
.type _Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj, @function
_Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13uniformUpdateP5uint4Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj, .-_Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj
.globl _Z13uniformUpdateP5uint4Pj
.type _Z13uniformUpdateP5uint4Pj, @function
_Z13uniformUpdateP5uint4Pj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13uniformUpdateP5uint4PjP5uint4Pj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13uniformUpdateP5uint4Pj, .-_Z13uniformUpdateP5uint4Pj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13uniformUpdateP5uint4Pj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13uniformUpdateP5uint4Pj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "uniformUpdate.hip"
.globl _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj # -- Begin function _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.p2align 4, 0x90
.type _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj,@function
_Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj: # @_Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj, .Lfunc_end0-_Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj,@object # @_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.section .rodata,"a",@progbits
.globl _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.p2align 3, 0x0
_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj:
.quad _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.size _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__uniformUpdateP15HIP_vector_typeIjLj4EEPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13uniformUpdateP15HIP_vector_typeIjLj4EEPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void square_matrix_kernel(int32_t num_rows, int32_t num_cols, const float* feats, int32_t ldf, float* feats_sq, int32_t lds) {
for (int i = blockIdx.y * blockDim.y + threadIdx.y; i < num_rows;
i += blockDim.y * gridDim.y) {
for (int j = blockIdx.x * blockDim.x + threadIdx.x; j < num_cols;
j += blockDim.x * gridDim.x) {
float f = feats[i * ldf + j];
feats_sq[i * lds + j] = f * f;
}
}
} | code for sm_80
Function : _Z20square_matrix_kerneliiPKfiPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0090*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x164], PT ; /* 0x0000590006007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ BSSY B0, 0x1c0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*00c0*/ MOV R11, c[0x0][0x4] ; /* 0x00000100000b7a02 */
/* 0x000fd60000000f00 */
/*00d0*/ @P0 BRA 0x1b0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*00e0*/ MOV R7, R6 ; /* 0x0000000600077202 */
/* 0x000fc80000000f00 */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fe200000001ff */
/*0100*/ IMAD R2, R0, c[0x0][0x170], R7 ; /* 0x00005c0000027a24 */
/* 0x000fd200078e0207 */
/*0110*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD R4, R0, c[0x0][0x180], R7 ; /* 0x0000600000047a24 */
/* 0x000fe200078e0207 */
/*0140*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fc60000000f00 */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fc800078e0205 */
/*0160*/ IMAD R7, R8, c[0x0][0xc], R7 ; /* 0x0000030008077a24 */
/* 0x000fca00078e0207 */
/*0170*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x164], PT ; /* 0x0000590007007a0c */
/* 0x000fe20003f06270 */
/*0180*/ FMUL R9, R2, R2 ; /* 0x0000000202097220 */
/* 0x004fca0000400000 */
/*0190*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001ee000c101904 */
/*01a0*/ @!P0 BRA 0xf0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ IMAD R0, R11, c[0x0][0x10], R0 ; /* 0x000004000b007a24 */
/* 0x000fca00078e0200 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 BRA 0xa0 ; /* 0xfffffeb000008947 */
/* 0x000fea000383ffff */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void square_matrix_kernel(int32_t num_rows, int32_t num_cols, const float* feats, int32_t ldf, float* feats_sq, int32_t lds) {
for (int i = blockIdx.y * blockDim.y + threadIdx.y; i < num_rows;
i += blockDim.y * gridDim.y) {
for (int j = blockIdx.x * blockDim.x + threadIdx.x; j < num_cols;
j += blockDim.x * gridDim.x) {
float f = feats[i * ldf + j];
feats_sq[i * lds + j] = f * f;
}
}
} | .file "tmpxft_001a7ca9_00000000-6_square_matrix_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi
.type _Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi, @function
_Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20square_matrix_kerneliiPKfiPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi, .-_Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi
.globl _Z20square_matrix_kerneliiPKfiPfi
.type _Z20square_matrix_kerneliiPKfiPfi, @function
_Z20square_matrix_kerneliiPKfiPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20square_matrix_kerneliiPKfiPfi, .-_Z20square_matrix_kerneliiPKfiPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20square_matrix_kerneliiPKfiPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20square_matrix_kerneliiPKfiPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void square_matrix_kernel(int32_t num_rows, int32_t num_cols, const float* feats, int32_t ldf, float* feats_sq, int32_t lds) {
for (int i = blockIdx.y * blockDim.y + threadIdx.y; i < num_rows;
i += blockDim.y * gridDim.y) {
for (int j = blockIdx.x * blockDim.x + threadIdx.x; j < num_cols;
j += blockDim.x * gridDim.x) {
float f = feats[i * ldf + j];
feats_sq[i * lds + j] = f * f;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_matrix_kernel(int32_t num_rows, int32_t num_cols, const float* feats, int32_t ldf, float* feats_sq, int32_t lds) {
for (int i = blockIdx.y * blockDim.y + threadIdx.y; i < num_rows;
i += blockDim.y * gridDim.y) {
for (int j = blockIdx.x * blockDim.x + threadIdx.x; j < num_cols;
j += blockDim.x * gridDim.x) {
float f = feats[i * ldf + j];
feats_sq[i * lds + j] = f * f;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_matrix_kernel(int32_t num_rows, int32_t num_cols, const float* feats, int32_t ldf, float* feats_sq, int32_t lds) {
for (int i = blockIdx.y * blockDim.y + threadIdx.y; i < num_rows;
i += blockDim.y * gridDim.y) {
for (int j = blockIdx.x * blockDim.x + threadIdx.x; j < num_cols;
j += blockDim.x * gridDim.x) {
float f = feats[i * ldf + j];
feats_sq[i * lds + j] = f * f;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20square_matrix_kerneliiPKfiPfi
.globl _Z20square_matrix_kerneliiPKfiPfi
.p2align 8
.type _Z20square_matrix_kerneliiPKfiPfi,@function
_Z20square_matrix_kerneliiPKfiPfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s6, s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s4, 16
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_6
s_load_b32 s9, s[2:3], 0xc
s_clause 0x1
s_load_b32 s12, s[0:1], 0x20
s_load_b32 s13, s[0:1], 0x10
s_load_b64 s[10:11], s[2:3], 0x0
s_clause 0x2
s_load_b32 s7, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s9, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s14, s0, v[0:1]
v_mul_lo_u32 v0, s12, v1
v_mul_lo_u32 v3, s13, v1
s_mul_i32 s8, s11, s8
s_mul_i32 s9, s10, s0
s_mul_i32 s10, s8, s12
s_mul_i32 s11, s8, s13
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s7, v2
s_mov_b32 s12, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v1, s8, v1
v_add_nc_u32_e32 v0, s10, v0
v_add_nc_u32_e32 v3, s11, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s6, v1
s_or_b32 s12, s0, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v4, v2
s_mov_b32 s14, 0
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v3, v4
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_load_b32 v7, v[5:6], off
v_add_nc_u32_e32 v5, v0, v4
v_add_nc_u32_e32 v4, s9, v4
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s1, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s1, s5, v6, s1
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, v7, v7
v_cmp_le_i32_e64 s0, s7, v4
global_store_b32 v[5:6], v7, off
s_or_b32 s14, s0, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20square_matrix_kerneliiPKfiPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20square_matrix_kerneliiPKfiPfi, .Lfunc_end0-_Z20square_matrix_kerneliiPKfiPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20square_matrix_kerneliiPKfiPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20square_matrix_kerneliiPKfiPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_matrix_kernel(int32_t num_rows, int32_t num_cols, const float* feats, int32_t ldf, float* feats_sq, int32_t lds) {
for (int i = blockIdx.y * blockDim.y + threadIdx.y; i < num_rows;
i += blockDim.y * gridDim.y) {
for (int j = blockIdx.x * blockDim.x + threadIdx.x; j < num_cols;
j += blockDim.x * gridDim.x) {
float f = feats[i * ldf + j];
feats_sq[i * lds + j] = f * f;
}
}
} | .text
.file "square_matrix_kernel.hip"
.globl _Z35__device_stub__square_matrix_kerneliiPKfiPfi # -- Begin function _Z35__device_stub__square_matrix_kerneliiPKfiPfi
.p2align 4, 0x90
.type _Z35__device_stub__square_matrix_kerneliiPKfiPfi,@function
_Z35__device_stub__square_matrix_kerneliiPKfiPfi: # @_Z35__device_stub__square_matrix_kerneliiPKfiPfi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20square_matrix_kerneliiPKfiPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z35__device_stub__square_matrix_kerneliiPKfiPfi, .Lfunc_end0-_Z35__device_stub__square_matrix_kerneliiPKfiPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20square_matrix_kerneliiPKfiPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20square_matrix_kerneliiPKfiPfi,@object # @_Z20square_matrix_kerneliiPKfiPfi
.section .rodata,"a",@progbits
.globl _Z20square_matrix_kerneliiPKfiPfi
.p2align 3, 0x0
_Z20square_matrix_kerneliiPKfiPfi:
.quad _Z35__device_stub__square_matrix_kerneliiPKfiPfi
.size _Z20square_matrix_kerneliiPKfiPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20square_matrix_kerneliiPKfiPfi"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__square_matrix_kerneliiPKfiPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20square_matrix_kerneliiPKfiPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20square_matrix_kerneliiPKfiPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0090*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x164], PT ; /* 0x0000590006007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ BSSY B0, 0x1c0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*00c0*/ MOV R11, c[0x0][0x4] ; /* 0x00000100000b7a02 */
/* 0x000fd60000000f00 */
/*00d0*/ @P0 BRA 0x1b0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*00e0*/ MOV R7, R6 ; /* 0x0000000600077202 */
/* 0x000fc80000000f00 */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fe200000001ff */
/*0100*/ IMAD R2, R0, c[0x0][0x170], R7 ; /* 0x00005c0000027a24 */
/* 0x000fd200078e0207 */
/*0110*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD R4, R0, c[0x0][0x180], R7 ; /* 0x0000600000047a24 */
/* 0x000fe200078e0207 */
/*0140*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fc60000000f00 */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fc800078e0205 */
/*0160*/ IMAD R7, R8, c[0x0][0xc], R7 ; /* 0x0000030008077a24 */
/* 0x000fca00078e0207 */
/*0170*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x164], PT ; /* 0x0000590007007a0c */
/* 0x000fe20003f06270 */
/*0180*/ FMUL R9, R2, R2 ; /* 0x0000000202097220 */
/* 0x004fca0000400000 */
/*0190*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001ee000c101904 */
/*01a0*/ @!P0 BRA 0xf0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ IMAD R0, R11, c[0x0][0x10], R0 ; /* 0x000004000b007a24 */
/* 0x000fca00078e0200 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 BRA 0xa0 ; /* 0xfffffeb000008947 */
/* 0x000fea000383ffff */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20square_matrix_kerneliiPKfiPfi
.globl _Z20square_matrix_kerneliiPKfiPfi
.p2align 8
.type _Z20square_matrix_kerneliiPKfiPfi,@function
_Z20square_matrix_kerneliiPKfiPfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s6, s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s4, 16
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_6
s_load_b32 s9, s[2:3], 0xc
s_clause 0x1
s_load_b32 s12, s[0:1], 0x20
s_load_b32 s13, s[0:1], 0x10
s_load_b64 s[10:11], s[2:3], 0x0
s_clause 0x2
s_load_b32 s7, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s9, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s14, s0, v[0:1]
v_mul_lo_u32 v0, s12, v1
v_mul_lo_u32 v3, s13, v1
s_mul_i32 s8, s11, s8
s_mul_i32 s9, s10, s0
s_mul_i32 s10, s8, s12
s_mul_i32 s11, s8, s13
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s7, v2
s_mov_b32 s12, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v1, s8, v1
v_add_nc_u32_e32 v0, s10, v0
v_add_nc_u32_e32 v3, s11, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s6, v1
s_or_b32 s12, s0, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v4, v2
s_mov_b32 s14, 0
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v3, v4
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_load_b32 v7, v[5:6], off
v_add_nc_u32_e32 v5, v0, v4
v_add_nc_u32_e32 v4, s9, v4
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s1, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s1, s5, v6, s1
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, v7, v7
v_cmp_le_i32_e64 s0, s7, v4
global_store_b32 v[5:6], v7, off
s_or_b32 s14, s0, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20square_matrix_kerneliiPKfiPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20square_matrix_kerneliiPKfiPfi, .Lfunc_end0-_Z20square_matrix_kerneliiPKfiPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20square_matrix_kerneliiPKfiPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20square_matrix_kerneliiPKfiPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a7ca9_00000000-6_square_matrix_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi
.type _Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi, @function
_Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20square_matrix_kerneliiPKfiPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi, .-_Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi
.globl _Z20square_matrix_kerneliiPKfiPfi
.type _Z20square_matrix_kerneliiPKfiPfi, @function
_Z20square_matrix_kerneliiPKfiPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20square_matrix_kerneliiPKfiPfiiiPKfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20square_matrix_kerneliiPKfiPfi, .-_Z20square_matrix_kerneliiPKfiPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20square_matrix_kerneliiPKfiPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20square_matrix_kerneliiPKfiPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square_matrix_kernel.hip"
.globl _Z35__device_stub__square_matrix_kerneliiPKfiPfi # -- Begin function _Z35__device_stub__square_matrix_kerneliiPKfiPfi
.p2align 4, 0x90
.type _Z35__device_stub__square_matrix_kerneliiPKfiPfi,@function
_Z35__device_stub__square_matrix_kerneliiPKfiPfi: # @_Z35__device_stub__square_matrix_kerneliiPKfiPfi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20square_matrix_kerneliiPKfiPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z35__device_stub__square_matrix_kerneliiPKfiPfi, .Lfunc_end0-_Z35__device_stub__square_matrix_kerneliiPKfiPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20square_matrix_kerneliiPKfiPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20square_matrix_kerneliiPKfiPfi,@object # @_Z20square_matrix_kerneliiPKfiPfi
.section .rodata,"a",@progbits
.globl _Z20square_matrix_kerneliiPKfiPfi
.p2align 3, 0x0
_Z20square_matrix_kerneliiPKfiPfi:
.quad _Z35__device_stub__square_matrix_kerneliiPKfiPfi
.size _Z20square_matrix_kerneliiPKfiPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20square_matrix_kerneliiPKfiPfi"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__square_matrix_kerneliiPKfiPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20square_matrix_kerneliiPKfiPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include <stdio.h>
#include <string.h>
#include<time.h>
#define Size 10
#define patternSize 3
#define patternNum 20
#define ThreadNum 20
#define BlockNum 1
__device__ void preKmp(char *x, int m, int kmpNext[])
{
int i, j;
i = 0;
j = kmpNext[0] = -1;
while(i < m)
{
while(j>-1 && x[i]!=x[j])
j = kmpNext[j];
i++;
j++;
if(x[i]==x[j])
kmpNext[i] = kmpNext[j];
else
kmpNext[i] = j;
}
}
/*******************************************
This variable m:pattern.length x:pattern
n:array.length y:array
*******************************************/
__device__ void KMP(char *x, int m, char *y, int n,int *answer,int id)
{
int i, j, kmpNext[Size];
preKmp(x,m,kmpNext);
i = j = 0;
while(j < n)
{
while(i>-1 && x[i]!=y[j])
{
i = kmpNext[i];
}
i++;
j++;
if(i >= m)
{
i = kmpNext[i];
answer[id]=j-1;
}
}
}
__global__ void kmp_kernel(char *array,char *pattern,int *answer)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
char *p;
p=&pattern[id*(patternSize+1)];
KMP(p,patternSize,array,Size,answer,id);
}
int main(int argc,char *argv[])
{
int i=0,j=0,tmp,*answer,*d_answer;
cudaError_t r;
char *array,*b,*pattern;
char *d_array,*d_pattern;
srand(time(0));
array=(char*)malloc(sizeof(char)*Size);
b=(char*)malloc(sizeof(char)*26);
pattern=(char*)malloc(sizeof(char)*(patternSize+1)*patternNum);
answer=(int*)malloc(sizeof(int)*patternNum);
/************************************
* cudaMalloc
************************************/
r=cudaMalloc((void**)&d_array,sizeof(char)*Size);
printf("cudaMalloc d_array : %s\n",cudaGetErrorString(r));
r=cudaMalloc((void**)&d_pattern,sizeof(char)*(patternSize+1)*patternNum);
printf("cudaMalloc d_pattern : %s\n",cudaGetErrorString(r));
r=cudaMalloc((void**)&d_answer,sizeof(int)*patternNum);
printf("cudaMalloc d_answer : %s\n",cudaGetErrorString(r));
b="abcdefghijklmnopqrstuvwxyz";
for(i=0;i<Size;i++)
array[i]=b[rand()%26];
for(i=0;i<patternNum;i++)
{
tmp=rand()%(Size-patternSize);
for(j=0;j<patternSize+1;j++)
{
if(j!=patternSize)
{
pattern[i*(patternSize+1)+j]=array[tmp++];
printf("%d %c\n",i,array[tmp-1]);
}
else
{
printf("===================== %d \n",j);
pattern[i*(patternSize+1)+j]='\0';
printf("%c\n",pattern[i*patternSize+j]);
}
}
}
for(i=0;i<patternNum;i++)
{
answer[i]=0;
}
r=cudaMemcpy(d_array,array,sizeof(char)*Size,cudaMemcpyHostToDevice);
printf("Memcpy H->D d_array : %s\n",cudaGetErrorString(r));
r=cudaMemcpy(d_pattern,pattern,sizeof(char)*(patternSize+1)*patternNum,cudaMemcpyHostToDevice);
printf("Memcpy H->D d_pattern : %s\n",cudaGetErrorString(r));
r=cudaMemcpy(d_answer,answer,sizeof(int)*patternNum,cudaMemcpyHostToDevice);
printf("Memcpy H->D d_answer : %s\n",cudaGetErrorString(r));
kmp_kernel<<<BlockNum, ThreadNum>>>(d_array, d_pattern, d_answer);
r=cudaMemcpy(answer, d_answer, sizeof(int)*patternNum, cudaMemcpyDeviceToHost);
printf("Memcpy D->H answer : %s\n",cudaGetErrorString(r));
printf("Array:\n");
printf("%s\n", array);
for(i=0;i<(patternSize+1)*patternNum;i++)
printf("%c", pattern[i]);
printf("\n\n");
for(i=0;i<patternNum;i++)
printf("%d, %d\n", i, answer[i]);
//printf("array : %c\n",array[3]);
//for(i=0;i<patternSize*patternNum;i++)
//printf("%s\n",pattern);
//for(i=0;i<patternNum;i++)
//printf("%d %s\n",i,pattern[i]);
//KMP<<<blockNum,threadNum>>>(b, strlen(b), array, strlen(array));
return 0;
} | .file "tmpxft_00067b68_00000000-6_cuda_kmp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6preKmpPciPi
.type _Z6preKmpPciPi, @function
_Z6preKmpPciPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6preKmpPciPi, .-_Z6preKmpPciPi
.globl _Z3KMPPciS_iPii
.type _Z3KMPPciS_iPii, @function
_Z3KMPPciS_iPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z3KMPPciS_iPii, .-_Z3KMPPciS_iPii
.globl _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi
.type _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi, @function
_Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kmp_kernelPcS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi, .-_Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi
.globl _Z10kmp_kernelPcS_Pi
.type _Z10kmp_kernelPcS_Pi, @function
_Z10kmp_kernelPcS_Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10kmp_kernelPcS_Pi, .-_Z10kmp_kernelPcS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc d_array : %s\n"
.LC1:
.string "cudaMalloc d_pattern : %s\n"
.LC2:
.string "cudaMalloc d_answer : %s\n"
.LC3:
.string "abcdefghijklmnopqrstuvwxyz"
.LC4:
.string "%d %c\n"
.LC5:
.string "===================== %d \n"
.LC6:
.string "%c\n"
.LC7:
.string "Memcpy H->D d_array : %s\n"
.LC8:
.string "Memcpy H->D d_pattern : %s\n"
.LC9:
.string "Memcpy H->D d_answer : %s\n"
.LC10:
.string "Memcpy D->H answer : %s\n"
.LC11:
.string "Array:\n"
.LC12:
.string "%s\n"
.LC13:
.string "%c"
.LC14:
.string "\n\n"
.LC15:
.string "%d, %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $10, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movl $80, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $80, %edi
call malloc@PLT
movq %rax, %r14
leaq 48(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 10(%rbx), %r12
leaq .LC3(%rip), %rbp
.L16:
call rand@PLT
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $26, %edx, %edx
subl %edx, %eax
cltq
movzbl 0(%rbp,%rax), %eax
movb %al, (%rbx)
addq $1, %rbx
cmpq %r12, %rbx
jne .L16
movq (%rsp), %r12
movl $0, %r13d
leaq .LC4(%rip), %r15
movq %r12, 16(%rsp)
movq %r14, 24(%rsp)
.L18:
movl %r13d, %r14d
call rand@PLT
movslq %eax, %rbx
imulq $-1840700269, %rbx, %rbx
shrq $32, %rbx
addl %eax, %ebx
sarl $2, %ebx
cltd
subl %edx, %ebx
leal 0(,%rbx,8), %edx
subl %ebx, %edx
subl %edx, %eax
movl $0, %ebp
movslq %eax, %rbx
movq 8(%rsp), %rax
addq %rax, %rbx
.L17:
movzbl (%rbx,%rbp), %ecx
movb %cl, (%r12,%rbp)
movsbl %cl, %ecx
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpq $3, %rbp
jne .L17
movl $3, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movb $0, 3(%r12)
leaq 0(%r13,%r13,2), %rax
movq (%rsp), %rsi
movsbl 3(%rsi,%rax), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
addq $4, %r12
cmpq $20, %r13
jne .L18
movq 16(%rsp), %rbp
movq 24(%rsp), %r14
movq %r14, %rax
leaq 80(%r14), %rdx
.L19:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
movl $1, %ecx
movl $10, %edx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $80, %edx
movq (%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $20, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L20:
movl $2, %ecx
movl $80, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rbx
addq $80, %rbx
leaq .LC13(%rip), %r12
.L21:
movsbl 0(%rbp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpq %rbx, %rbp
jne .L21
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC15(%rip), %rbp
.L22:
movl (%r14,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $20, %rbx
jne .L22
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi
jmp .L20
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z10kmp_kernelPcS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kmp_kernelPcS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include <stdio.h>
#include <string.h>
#include<time.h>
#define Size 10
#define patternSize 3
#define patternNum 20
#define ThreadNum 20
#define BlockNum 1
__device__ void preKmp(char *x, int m, int kmpNext[])
{
int i, j;
i = 0;
j = kmpNext[0] = -1;
while(i < m)
{
while(j>-1 && x[i]!=x[j])
j = kmpNext[j];
i++;
j++;
if(x[i]==x[j])
kmpNext[i] = kmpNext[j];
else
kmpNext[i] = j;
}
}
/*******************************************
This variable m:pattern.length x:pattern
n:array.length y:array
*******************************************/
__device__ void KMP(char *x, int m, char *y, int n,int *answer,int id)
{
int i, j, kmpNext[Size];
preKmp(x,m,kmpNext);
i = j = 0;
while(j < n)
{
while(i>-1 && x[i]!=y[j])
{
i = kmpNext[i];
}
i++;
j++;
if(i >= m)
{
i = kmpNext[i];
answer[id]=j-1;
}
}
}
__global__ void kmp_kernel(char *array,char *pattern,int *answer)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
char *p;
p=&pattern[id*(patternSize+1)];
KMP(p,patternSize,array,Size,answer,id);
}
int main(int argc,char *argv[])
{
int i=0,j=0,tmp,*answer,*d_answer;
cudaError_t r;
char *array,*b,*pattern;
char *d_array,*d_pattern;
srand(time(0));
array=(char*)malloc(sizeof(char)*Size);
b=(char*)malloc(sizeof(char)*26);
pattern=(char*)malloc(sizeof(char)*(patternSize+1)*patternNum);
answer=(int*)malloc(sizeof(int)*patternNum);
/************************************
* cudaMalloc
************************************/
r=cudaMalloc((void**)&d_array,sizeof(char)*Size);
printf("cudaMalloc d_array : %s\n",cudaGetErrorString(r));
r=cudaMalloc((void**)&d_pattern,sizeof(char)*(patternSize+1)*patternNum);
printf("cudaMalloc d_pattern : %s\n",cudaGetErrorString(r));
r=cudaMalloc((void**)&d_answer,sizeof(int)*patternNum);
printf("cudaMalloc d_answer : %s\n",cudaGetErrorString(r));
b="abcdefghijklmnopqrstuvwxyz";
for(i=0;i<Size;i++)
array[i]=b[rand()%26];
for(i=0;i<patternNum;i++)
{
tmp=rand()%(Size-patternSize);
for(j=0;j<patternSize+1;j++)
{
if(j!=patternSize)
{
pattern[i*(patternSize+1)+j]=array[tmp++];
printf("%d %c\n",i,array[tmp-1]);
}
else
{
printf("===================== %d \n",j);
pattern[i*(patternSize+1)+j]='\0';
printf("%c\n",pattern[i*patternSize+j]);
}
}
}
for(i=0;i<patternNum;i++)
{
answer[i]=0;
}
r=cudaMemcpy(d_array,array,sizeof(char)*Size,cudaMemcpyHostToDevice);
printf("Memcpy H->D d_array : %s\n",cudaGetErrorString(r));
r=cudaMemcpy(d_pattern,pattern,sizeof(char)*(patternSize+1)*patternNum,cudaMemcpyHostToDevice);
printf("Memcpy H->D d_pattern : %s\n",cudaGetErrorString(r));
r=cudaMemcpy(d_answer,answer,sizeof(int)*patternNum,cudaMemcpyHostToDevice);
printf("Memcpy H->D d_answer : %s\n",cudaGetErrorString(r));
kmp_kernel<<<BlockNum, ThreadNum>>>(d_array, d_pattern, d_answer);
r=cudaMemcpy(answer, d_answer, sizeof(int)*patternNum, cudaMemcpyDeviceToHost);
printf("Memcpy D->H answer : %s\n",cudaGetErrorString(r));
printf("Array:\n");
printf("%s\n", array);
for(i=0;i<(patternSize+1)*patternNum;i++)
printf("%c", pattern[i]);
printf("\n\n");
for(i=0;i<patternNum;i++)
printf("%d, %d\n", i, answer[i]);
//printf("array : %c\n",array[3]);
//for(i=0;i<patternSize*patternNum;i++)
//printf("%s\n",pattern);
//for(i=0;i<patternNum;i++)
//printf("%d %s\n",i,pattern[i]);
//KMP<<<blockNum,threadNum>>>(b, strlen(b), array, strlen(array));
return 0;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include <stdio.h>
#include <string.h>
#include<time.h>
#define Size 10
#define patternSize 3
#define patternNum 20
#define ThreadNum 20
#define BlockNum 1
__device__ void preKmp(char *x, int m, int kmpNext[])
{
int i, j;
i = 0;
j = kmpNext[0] = -1;
while(i < m)
{
while(j>-1 && x[i]!=x[j])
j = kmpNext[j];
i++;
j++;
if(x[i]==x[j])
kmpNext[i] = kmpNext[j];
else
kmpNext[i] = j;
}
}
/*******************************************
This variable m:pattern.length x:pattern
n:array.length y:array
*******************************************/
__device__ void KMP(char *x, int m, char *y, int n,int *answer,int id)
{
int i, j, kmpNext[Size];
preKmp(x,m,kmpNext);
i = j = 0;
while(j < n)
{
while(i>-1 && x[i]!=y[j])
{
i = kmpNext[i];
}
i++;
j++;
if(i >= m)
{
i = kmpNext[i];
answer[id]=j-1;
}
}
}
__global__ void kmp_kernel(char *array,char *pattern,int *answer)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
char *p;
p=&pattern[id*(patternSize+1)];
KMP(p,patternSize,array,Size,answer,id);
}
int main(int argc,char *argv[])
{
int i=0,j=0,tmp,*answer,*d_answer;
hipError_t r;
char *array,*b,*pattern;
char *d_array,*d_pattern;
srand(time(0));
array=(char*)malloc(sizeof(char)*Size);
b=(char*)malloc(sizeof(char)*26);
pattern=(char*)malloc(sizeof(char)*(patternSize+1)*patternNum);
answer=(int*)malloc(sizeof(int)*patternNum);
/************************************
* cudaMalloc
************************************/
r=hipMalloc((void**)&d_array,sizeof(char)*Size);
printf("hipMalloc d_array : %s\n",hipGetErrorString(r));
r=hipMalloc((void**)&d_pattern,sizeof(char)*(patternSize+1)*patternNum);
printf("hipMalloc d_pattern : %s\n",hipGetErrorString(r));
r=hipMalloc((void**)&d_answer,sizeof(int)*patternNum);
printf("hipMalloc d_answer : %s\n",hipGetErrorString(r));
b="abcdefghijklmnopqrstuvwxyz";
for(i=0;i<Size;i++)
array[i]=b[rand()%26];
for(i=0;i<patternNum;i++)
{
tmp=rand()%(Size-patternSize);
for(j=0;j<patternSize+1;j++)
{
if(j!=patternSize)
{
pattern[i*(patternSize+1)+j]=array[tmp++];
printf("%d %c\n",i,array[tmp-1]);
}
else
{
printf("===================== %d \n",j);
pattern[i*(patternSize+1)+j]='\0';
printf("%c\n",pattern[i*patternSize+j]);
}
}
}
for(i=0;i<patternNum;i++)
{
answer[i]=0;
}
r=hipMemcpy(d_array,array,sizeof(char)*Size,hipMemcpyHostToDevice);
printf("Memcpy H->D d_array : %s\n",hipGetErrorString(r));
r=hipMemcpy(d_pattern,pattern,sizeof(char)*(patternSize+1)*patternNum,hipMemcpyHostToDevice);
printf("Memcpy H->D d_pattern : %s\n",hipGetErrorString(r));
r=hipMemcpy(d_answer,answer,sizeof(int)*patternNum,hipMemcpyHostToDevice);
printf("Memcpy H->D d_answer : %s\n",hipGetErrorString(r));
kmp_kernel<<<BlockNum, ThreadNum>>>(d_array, d_pattern, d_answer);
r=hipMemcpy(answer, d_answer, sizeof(int)*patternNum, hipMemcpyDeviceToHost);
printf("Memcpy D->H answer : %s\n",hipGetErrorString(r));
printf("Array:\n");
printf("%s\n", array);
for(i=0;i<(patternSize+1)*patternNum;i++)
printf("%c", pattern[i]);
printf("\n\n");
for(i=0;i<patternNum;i++)
printf("%d, %d\n", i, answer[i]);
//printf("array : %c\n",array[3]);
//for(i=0;i<patternSize*patternNum;i++)
//printf("%s\n",pattern);
//for(i=0;i<patternNum;i++)
//printf("%d %s\n",i,pattern[i]);
//KMP<<<blockNum,threadNum>>>(b, strlen(b), array, strlen(array));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include <stdio.h>
#include <string.h>
#include<time.h>
#define Size 10
#define patternSize 3
#define patternNum 20
#define ThreadNum 20
#define BlockNum 1
__device__ void preKmp(char *x, int m, int kmpNext[])
{
int i, j;
i = 0;
j = kmpNext[0] = -1;
while(i < m)
{
while(j>-1 && x[i]!=x[j])
j = kmpNext[j];
i++;
j++;
if(x[i]==x[j])
kmpNext[i] = kmpNext[j];
else
kmpNext[i] = j;
}
}
/*******************************************
This variable m:pattern.length x:pattern
n:array.length y:array
*******************************************/
__device__ void KMP(char *x, int m, char *y, int n,int *answer,int id)
{
int i, j, kmpNext[Size];
preKmp(x,m,kmpNext);
i = j = 0;
while(j < n)
{
while(i>-1 && x[i]!=y[j])
{
i = kmpNext[i];
}
i++;
j++;
if(i >= m)
{
i = kmpNext[i];
answer[id]=j-1;
}
}
}
__global__ void kmp_kernel(char *array,char *pattern,int *answer)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
char *p;
p=&pattern[id*(patternSize+1)];
KMP(p,patternSize,array,Size,answer,id);
}
int main(int argc,char *argv[])
{
int i=0,j=0,tmp,*answer,*d_answer;
hipError_t r;
char *array,*b,*pattern;
char *d_array,*d_pattern;
srand(time(0));
array=(char*)malloc(sizeof(char)*Size);
b=(char*)malloc(sizeof(char)*26);
pattern=(char*)malloc(sizeof(char)*(patternSize+1)*patternNum);
answer=(int*)malloc(sizeof(int)*patternNum);
/************************************
* cudaMalloc
************************************/
r=hipMalloc((void**)&d_array,sizeof(char)*Size);
printf("hipMalloc d_array : %s\n",hipGetErrorString(r));
r=hipMalloc((void**)&d_pattern,sizeof(char)*(patternSize+1)*patternNum);
printf("hipMalloc d_pattern : %s\n",hipGetErrorString(r));
r=hipMalloc((void**)&d_answer,sizeof(int)*patternNum);
printf("hipMalloc d_answer : %s\n",hipGetErrorString(r));
b="abcdefghijklmnopqrstuvwxyz";
for(i=0;i<Size;i++)
array[i]=b[rand()%26];
for(i=0;i<patternNum;i++)
{
tmp=rand()%(Size-patternSize);
for(j=0;j<patternSize+1;j++)
{
if(j!=patternSize)
{
pattern[i*(patternSize+1)+j]=array[tmp++];
printf("%d %c\n",i,array[tmp-1]);
}
else
{
printf("===================== %d \n",j);
pattern[i*(patternSize+1)+j]='\0';
printf("%c\n",pattern[i*patternSize+j]);
}
}
}
for(i=0;i<patternNum;i++)
{
answer[i]=0;
}
r=hipMemcpy(d_array,array,sizeof(char)*Size,hipMemcpyHostToDevice);
printf("Memcpy H->D d_array : %s\n",hipGetErrorString(r));
r=hipMemcpy(d_pattern,pattern,sizeof(char)*(patternSize+1)*patternNum,hipMemcpyHostToDevice);
printf("Memcpy H->D d_pattern : %s\n",hipGetErrorString(r));
r=hipMemcpy(d_answer,answer,sizeof(int)*patternNum,hipMemcpyHostToDevice);
printf("Memcpy H->D d_answer : %s\n",hipGetErrorString(r));
kmp_kernel<<<BlockNum, ThreadNum>>>(d_array, d_pattern, d_answer);
r=hipMemcpy(answer, d_answer, sizeof(int)*patternNum, hipMemcpyDeviceToHost);
printf("Memcpy D->H answer : %s\n",hipGetErrorString(r));
printf("Array:\n");
printf("%s\n", array);
for(i=0;i<(patternSize+1)*patternNum;i++)
printf("%c", pattern[i]);
printf("\n\n");
for(i=0;i<patternNum;i++)
printf("%d, %d\n", i, answer[i]);
//printf("array : %c\n",array[3]);
//for(i=0;i<patternSize*patternNum;i++)
//printf("%s\n",pattern);
//for(i=0;i<patternNum;i++)
//printf("%d %s\n",i,pattern[i]);
//KMP<<<blockNum,threadNum>>>(b, strlen(b), array, strlen(array));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kmp_kernelPcS_Pi
.globl _Z10kmp_kernelPcS_Pi
.p2align 8
.type _Z10kmp_kernelPcS_Pi,@function
_Z10kmp_kernelPcS_Pi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, s15, s4, v[0:1]
v_dual_mov_b32 v11, -1 :: v_dual_lshlrev_b32 v0, 2, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v12, vcc_lo, s2, v0
v_mov_b32_e32 v0, -1
s_mov_b32 s2, 0
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v1, vcc_lo
s_branch .LBB0_3
.LBB0_1:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v11, 1, v11
s_add_i32 s2, s2, 1
v_add_co_u32 v14, vcc_lo, v12, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v17, 31, v11
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v13, vcc_lo
v_add_co_u32 v16, vcc_lo, v12, v11
v_add_co_ci_u32_e32 v17, vcc_lo, v13, v17, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 1, v11
s_mov_b32 m0, s2
s_clause 0x1
global_load_u8 v14, v[14:15], off
global_load_u8 v15, v[16:17], off
s_cmp_lg_u32 s2, 3
v_cndmask_b32_e32 v16, v0, v1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v16, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 3, v11
v_cndmask_b32_e32 v16, v16, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 4, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v16, v4, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 5, v11
v_cndmask_b32_e32 v16, v16, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 6, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v16, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 7, v11
v_cndmask_b32_e32 v16, v16, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v16, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 9, v11
v_cndmask_b32_e32 v16, v16, v9, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v14, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v14, v11, v16, vcc_lo
v_movreld_b32_e32 v0, v14
s_cbranch_scc0 .LBB0_8
.LBB0_3:
s_mov_b32 s3, exec_lo
v_cmpx_lt_i32_e32 -1, v11
s_cbranch_execz .LBB0_2
v_add_co_u32 v14, vcc_lo, v12, s2
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v13, vcc_lo
s_mov_b32 s4, 0
global_load_u8 v14, v[14:15], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v14, 0xff, v14
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s4, s6, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_1
.LBB0_6:
v_add_co_u32 v15, vcc_lo, v12, v11
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v13, vcc_lo
s_or_b32 s5, s5, exec_lo
s_mov_b32 s6, exec_lo
global_load_u8 v15, v[15:16], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e64 v14, v15
s_cbranch_execz .LBB0_5
v_cmp_eq_u32_e32 vcc_lo, 1, v11
s_and_not1_b32 s5, s5, exec_lo
v_cndmask_b32_e32 v15, v0, v1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v15, v15, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 3, v11
v_cndmask_b32_e32 v15, v15, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 4, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v15, v15, v4, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 5, v11
v_cndmask_b32_e32 v15, v15, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 6, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v15, v15, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 7, v11
v_cndmask_b32_e32 v15, v15, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v15, v15, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 9, v11
v_cndmask_b32_e32 v11, v15, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, 0, v11
s_and_b32 s7, vcc_lo, exec_lo
s_or_b32 s5, s5, s7
s_branch .LBB0_5
.LBB0_8:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v11, 31, v10
v_mov_b32_e32 v14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s2, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
s_mov_b32 s2, 0
s_branch .LBB0_10
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v14, v15
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 10
s_cbranch_scc0 .LBB0_18
.LBB0_10:
s_mov_b32 s3, exec_lo
v_cmpx_lt_i32_e32 -1, v14
s_cbranch_execz .LBB0_16
v_mov_b32_e32 v15, s2
s_mov_b32 s4, 0
global_load_u8 v15, v15, s[0:1]
s_waitcnt vmcnt(0)
v_and_b32_e32 v15, 0xff, v15
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_13
.p2align 6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s4, s6, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_15
.LBB0_13:
v_add_co_u32 v16, vcc_lo, v12, v14
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v13, vcc_lo
s_or_b32 s5, s5, exec_lo
s_mov_b32 s6, exec_lo
global_load_u8 v16, v[16:17], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e64 v16, v15
s_cbranch_execz .LBB0_12
v_cmp_eq_u32_e32 vcc_lo, 1, v14
s_and_not1_b32 s5, s5, exec_lo
v_cndmask_b32_e32 v16, v0, v1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v16, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 3, v14
v_cndmask_b32_e32 v16, v16, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 4, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v16, v4, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 5, v14
v_cndmask_b32_e32 v16, v16, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 6, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v16, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 7, v14
v_cndmask_b32_e32 v16, v16, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 8, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v16, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 9, v14
v_cndmask_b32_e32 v14, v16, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, 0, v14
s_and_b32 s7, vcc_lo, exec_lo
s_or_b32 s5, s5, s7
s_branch .LBB0_12
.LBB0_15:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v15, 1, v14
s_mov_b32 s3, exec_lo
v_cmpx_lt_i32_e32 1, v14
s_cbranch_execz .LBB0_9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 1, v15
v_cndmask_b32_e32 v14, v0, v1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v15
v_cndmask_b32_e32 v14, v14, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 3, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v14, v14, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 4, v15
v_cndmask_b32_e32 v14, v14, v4, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 5, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v14, v14, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 6, v15
v_cndmask_b32_e32 v14, v14, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 7, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v14, v14, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 8, v15
v_cndmask_b32_e32 v14, v14, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 9, v15
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v16, s2 :: v_dual_cndmask_b32 v15, v14, v9
global_store_b32 v[10:11], v16, off
s_branch .LBB0_9
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kmp_kernelPcS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kmp_kernelPcS_Pi, .Lfunc_end0-_Z10kmp_kernelPcS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kmp_kernelPcS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kmp_kernelPcS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include <stdio.h>
#include <string.h>
#include<time.h>
#define Size 10
#define patternSize 3
#define patternNum 20
#define ThreadNum 20
#define BlockNum 1
__device__ void preKmp(char *x, int m, int kmpNext[])
{
int i, j;
i = 0;
j = kmpNext[0] = -1;
while(i < m)
{
while(j>-1 && x[i]!=x[j])
j = kmpNext[j];
i++;
j++;
if(x[i]==x[j])
kmpNext[i] = kmpNext[j];
else
kmpNext[i] = j;
}
}
/*******************************************
This variable m:pattern.length x:pattern
n:array.length y:array
*******************************************/
__device__ void KMP(char *x, int m, char *y, int n,int *answer,int id)
{
int i, j, kmpNext[Size];
preKmp(x,m,kmpNext);
i = j = 0;
while(j < n)
{
while(i>-1 && x[i]!=y[j])
{
i = kmpNext[i];
}
i++;
j++;
if(i >= m)
{
i = kmpNext[i];
answer[id]=j-1;
}
}
}
__global__ void kmp_kernel(char *array,char *pattern,int *answer)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
char *p;
p=&pattern[id*(patternSize+1)];
KMP(p,patternSize,array,Size,answer,id);
}
int main(int argc,char *argv[])
{
int i=0,j=0,tmp,*answer,*d_answer;
hipError_t r;
char *array,*b,*pattern;
char *d_array,*d_pattern;
srand(time(0));
array=(char*)malloc(sizeof(char)*Size);
b=(char*)malloc(sizeof(char)*26);
pattern=(char*)malloc(sizeof(char)*(patternSize+1)*patternNum);
answer=(int*)malloc(sizeof(int)*patternNum);
/************************************
* cudaMalloc
************************************/
r=hipMalloc((void**)&d_array,sizeof(char)*Size);
printf("hipMalloc d_array : %s\n",hipGetErrorString(r));
r=hipMalloc((void**)&d_pattern,sizeof(char)*(patternSize+1)*patternNum);
printf("hipMalloc d_pattern : %s\n",hipGetErrorString(r));
r=hipMalloc((void**)&d_answer,sizeof(int)*patternNum);
printf("hipMalloc d_answer : %s\n",hipGetErrorString(r));
b="abcdefghijklmnopqrstuvwxyz";
for(i=0;i<Size;i++)
array[i]=b[rand()%26];
for(i=0;i<patternNum;i++)
{
tmp=rand()%(Size-patternSize);
for(j=0;j<patternSize+1;j++)
{
if(j!=patternSize)
{
pattern[i*(patternSize+1)+j]=array[tmp++];
printf("%d %c\n",i,array[tmp-1]);
}
else
{
printf("===================== %d \n",j);
pattern[i*(patternSize+1)+j]='\0';
printf("%c\n",pattern[i*patternSize+j]);
}
}
}
for(i=0;i<patternNum;i++)
{
answer[i]=0;
}
r=hipMemcpy(d_array,array,sizeof(char)*Size,hipMemcpyHostToDevice);
printf("Memcpy H->D d_array : %s\n",hipGetErrorString(r));
r=hipMemcpy(d_pattern,pattern,sizeof(char)*(patternSize+1)*patternNum,hipMemcpyHostToDevice);
printf("Memcpy H->D d_pattern : %s\n",hipGetErrorString(r));
r=hipMemcpy(d_answer,answer,sizeof(int)*patternNum,hipMemcpyHostToDevice);
printf("Memcpy H->D d_answer : %s\n",hipGetErrorString(r));
kmp_kernel<<<BlockNum, ThreadNum>>>(d_array, d_pattern, d_answer);
r=hipMemcpy(answer, d_answer, sizeof(int)*patternNum, hipMemcpyDeviceToHost);
printf("Memcpy D->H answer : %s\n",hipGetErrorString(r));
printf("Array:\n");
printf("%s\n", array);
for(i=0;i<(patternSize+1)*patternNum;i++)
printf("%c", pattern[i]);
printf("\n\n");
for(i=0;i<patternNum;i++)
printf("%d, %d\n", i, answer[i]);
//printf("array : %c\n",array[3]);
//for(i=0;i<patternSize*patternNum;i++)
//printf("%s\n",pattern);
//for(i=0;i<patternNum;i++)
//printf("%d %s\n",i,pattern[i]);
//KMP<<<blockNum,threadNum>>>(b, strlen(b), array, strlen(array));
return 0;
} | .text
.file "cuda_kmp.hip"
.globl _Z25__device_stub__kmp_kernelPcS_Pi # -- Begin function _Z25__device_stub__kmp_kernelPcS_Pi
.p2align 4, 0x90
.type _Z25__device_stub__kmp_kernelPcS_Pi,@function
_Z25__device_stub__kmp_kernelPcS_Pi: # @_Z25__device_stub__kmp_kernelPcS_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kmp_kernelPcS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__kmp_kernelPcS_Pi, .Lfunc_end0-_Z25__device_stub__kmp_kernelPcS_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $10, %edi
callq malloc
movq %rax, %r14
movl $80, %edi
callq malloc
movq %rax, %rbx
movl $80, %edi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movl $10, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
cltq
movzbl .L.str.3(%rax), %eax
movb %al, (%r14,%r12)
incq %r12
cmpq $10, %r12
jne .LBB1_1
# %bb.2: # %.preheader60
movq %r14, 24(%rsp) # 8-byte Spill
movq %rbx, 16(%rsp) # 8-byte Spill
movq %rbx, %r13
xorl %r12d, %r12d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_3 Depth=1
incq %r12
addq $4, %r13
cmpq $20, %r12
je .LBB1_9
.LBB1_3: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
callq rand
cltq
imulq $-1840700269, %rax, %rbp # imm = 0x92492493
shrq $32, %rbp
addl %eax, %ebp
movl %ebp, %ecx
shrl $31, %ecx
sarl $2, %ebp
addl %ecx, %ebp
leal (,%rbp,8), %ecx
subl %ecx, %ebp
addl %eax, %ebp
leaq 3(,%r12,4), %rbx
leaq (%r12,%r12,2), %r15
movq $-4, %r14
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movl $.L.str.5, %edi
movl $3, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rax # 8-byte Reload
movb $0, (%rax,%rbx)
movsbl 3(%rax,%r15), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r14
je .LBB1_8
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $-1, %r14
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movslq %ebp, %rax
incl %ebp
movq 24(%rsp), %rcx # 8-byte Reload
movsbl (%rcx,%rax), %edx
movb %dl, 4(%r13,%r14)
movl $.L.str.4, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r14
jne .LBB1_4
jmp .LBB1_8
.LBB1_9: # %.preheader.preheader
xorps %xmm0, %xmm0
movq 48(%rsp), %r15 # 8-byte Reload
movups %xmm0, 64(%r15)
movups %xmm0, 48(%r15)
movups %xmm0, 32(%r15)
movups %xmm0, 16(%r15)
movups %xmm0, (%r15)
movq 40(%rsp), %rdi
movl $10, %edx
movq 24(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rdi
movl $80, %edx
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $80, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 19(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10kmp_kernelPcS_Pi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rsi
movl $80, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
xorl %ebx, %ebx
movl $.L.str.10, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movq %r12, %rdi
callq puts@PLT
.p2align 4, 0x90
.LBB1_12: # =>This Inner Loop Header: Depth=1
movsbl (%r14,%rbx), %edi
callq putchar@PLT
incq %rbx
cmpq $80, %rbx
jne .LBB1_12
# %bb.13:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
movl (%r15,%r14,4), %edx
movl $.L.str.15, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $20, %r14
jne .LBB1_14
# %bb.15:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kmp_kernelPcS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kmp_kernelPcS_Pi,@object # @_Z10kmp_kernelPcS_Pi
.section .rodata,"a",@progbits
.globl _Z10kmp_kernelPcS_Pi
.p2align 3, 0x0
_Z10kmp_kernelPcS_Pi:
.quad _Z25__device_stub__kmp_kernelPcS_Pi
.size _Z10kmp_kernelPcS_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc d_array : %s\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc d_pattern : %s\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc d_answer : %s\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "abcdefghijklmnopqrstuvwxyz"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %c\n"
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "===================== %d \n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%c\n"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Memcpy H->D d_array : %s\n"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Memcpy H->D d_pattern : %s\n"
.size .L.str.8, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Memcpy H->D d_answer : %s\n"
.size .L.str.9, 27
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Memcpy D->H answer : %s\n"
.size .L.str.10, 25
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "%d, %d\n"
.size .L.str.15, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10kmp_kernelPcS_Pi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Array:"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kmp_kernelPcS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kmp_kernelPcS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00067b68_00000000-6_cuda_kmp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6preKmpPciPi
.type _Z6preKmpPciPi, @function
_Z6preKmpPciPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6preKmpPciPi, .-_Z6preKmpPciPi
.globl _Z3KMPPciS_iPii
.type _Z3KMPPciS_iPii, @function
_Z3KMPPciS_iPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z3KMPPciS_iPii, .-_Z3KMPPciS_iPii
.globl _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi
.type _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi, @function
_Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kmp_kernelPcS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi, .-_Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi
.globl _Z10kmp_kernelPcS_Pi
.type _Z10kmp_kernelPcS_Pi, @function
_Z10kmp_kernelPcS_Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10kmp_kernelPcS_Pi, .-_Z10kmp_kernelPcS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc d_array : %s\n"
.LC1:
.string "cudaMalloc d_pattern : %s\n"
.LC2:
.string "cudaMalloc d_answer : %s\n"
.LC3:
.string "abcdefghijklmnopqrstuvwxyz"
.LC4:
.string "%d %c\n"
.LC5:
.string "===================== %d \n"
.LC6:
.string "%c\n"
.LC7:
.string "Memcpy H->D d_array : %s\n"
.LC8:
.string "Memcpy H->D d_pattern : %s\n"
.LC9:
.string "Memcpy H->D d_answer : %s\n"
.LC10:
.string "Memcpy D->H answer : %s\n"
.LC11:
.string "Array:\n"
.LC12:
.string "%s\n"
.LC13:
.string "%c"
.LC14:
.string "\n\n"
.LC15:
.string "%d, %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $10, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movl $80, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $80, %edi
call malloc@PLT
movq %rax, %r14
leaq 48(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 10(%rbx), %r12
leaq .LC3(%rip), %rbp
.L16:
call rand@PLT
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $26, %edx, %edx
subl %edx, %eax
cltq
movzbl 0(%rbp,%rax), %eax
movb %al, (%rbx)
addq $1, %rbx
cmpq %r12, %rbx
jne .L16
movq (%rsp), %r12
movl $0, %r13d
leaq .LC4(%rip), %r15
movq %r12, 16(%rsp)
movq %r14, 24(%rsp)
.L18:
movl %r13d, %r14d
call rand@PLT
movslq %eax, %rbx
imulq $-1840700269, %rbx, %rbx
shrq $32, %rbx
addl %eax, %ebx
sarl $2, %ebx
cltd
subl %edx, %ebx
leal 0(,%rbx,8), %edx
subl %ebx, %edx
subl %edx, %eax
movl $0, %ebp
movslq %eax, %rbx
movq 8(%rsp), %rax
addq %rax, %rbx
.L17:
movzbl (%rbx,%rbp), %ecx
movb %cl, (%r12,%rbp)
movsbl %cl, %ecx
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpq $3, %rbp
jne .L17
movl $3, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movb $0, 3(%r12)
leaq 0(%r13,%r13,2), %rax
movq (%rsp), %rsi
movsbl 3(%rsi,%rax), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
addq $4, %r12
cmpq $20, %r13
jne .L18
movq 16(%rsp), %rbp
movq 24(%rsp), %r14
movq %r14, %rax
leaq 80(%r14), %rdx
.L19:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
movl $1, %ecx
movl $10, %edx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $80, %edx
movq (%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $20, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L20:
movl $2, %ecx
movl $80, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rbx
addq $80, %rbx
leaq .LC13(%rip), %r12
.L21:
movsbl 0(%rbp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpq %rbx, %rbp
jne .L21
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC15(%rip), %rbp
.L22:
movl (%r14,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $20, %rbx
jne .L22
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z34__device_stub__Z10kmp_kernelPcS_PiPcS_Pi
jmp .L20
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z10kmp_kernelPcS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kmp_kernelPcS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_kmp.hip"
.globl _Z25__device_stub__kmp_kernelPcS_Pi # -- Begin function _Z25__device_stub__kmp_kernelPcS_Pi
.p2align 4, 0x90
.type _Z25__device_stub__kmp_kernelPcS_Pi,@function
_Z25__device_stub__kmp_kernelPcS_Pi: # @_Z25__device_stub__kmp_kernelPcS_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kmp_kernelPcS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__kmp_kernelPcS_Pi, .Lfunc_end0-_Z25__device_stub__kmp_kernelPcS_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $10, %edi
callq malloc
movq %rax, %r14
movl $80, %edi
callq malloc
movq %rax, %rbx
movl $80, %edi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movl $10, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
cltq
movzbl .L.str.3(%rax), %eax
movb %al, (%r14,%r12)
incq %r12
cmpq $10, %r12
jne .LBB1_1
# %bb.2: # %.preheader60
movq %r14, 24(%rsp) # 8-byte Spill
movq %rbx, 16(%rsp) # 8-byte Spill
movq %rbx, %r13
xorl %r12d, %r12d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_3 Depth=1
incq %r12
addq $4, %r13
cmpq $20, %r12
je .LBB1_9
.LBB1_3: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
callq rand
cltq
imulq $-1840700269, %rax, %rbp # imm = 0x92492493
shrq $32, %rbp
addl %eax, %ebp
movl %ebp, %ecx
shrl $31, %ecx
sarl $2, %ebp
addl %ecx, %ebp
leal (,%rbp,8), %ecx
subl %ecx, %ebp
addl %eax, %ebp
leaq 3(,%r12,4), %rbx
leaq (%r12,%r12,2), %r15
movq $-4, %r14
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movl $.L.str.5, %edi
movl $3, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rax # 8-byte Reload
movb $0, (%rax,%rbx)
movsbl 3(%rax,%r15), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r14
je .LBB1_8
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $-1, %r14
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movslq %ebp, %rax
incl %ebp
movq 24(%rsp), %rcx # 8-byte Reload
movsbl (%rcx,%rax), %edx
movb %dl, 4(%r13,%r14)
movl $.L.str.4, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r14
jne .LBB1_4
jmp .LBB1_8
.LBB1_9: # %.preheader.preheader
xorps %xmm0, %xmm0
movq 48(%rsp), %r15 # 8-byte Reload
movups %xmm0, 64(%r15)
movups %xmm0, 48(%r15)
movups %xmm0, 32(%r15)
movups %xmm0, 16(%r15)
movups %xmm0, (%r15)
movq 40(%rsp), %rdi
movl $10, %edx
movq 24(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rdi
movl $80, %edx
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $80, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 19(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10kmp_kernelPcS_Pi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rsi
movl $80, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
xorl %ebx, %ebx
movl $.L.str.10, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movq %r12, %rdi
callq puts@PLT
.p2align 4, 0x90
.LBB1_12: # =>This Inner Loop Header: Depth=1
movsbl (%r14,%rbx), %edi
callq putchar@PLT
incq %rbx
cmpq $80, %rbx
jne .LBB1_12
# %bb.13:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
movl (%r15,%r14,4), %edx
movl $.L.str.15, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $20, %r14
jne .LBB1_14
# %bb.15:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kmp_kernelPcS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kmp_kernelPcS_Pi,@object # @_Z10kmp_kernelPcS_Pi
.section .rodata,"a",@progbits
.globl _Z10kmp_kernelPcS_Pi
.p2align 3, 0x0
_Z10kmp_kernelPcS_Pi:
.quad _Z25__device_stub__kmp_kernelPcS_Pi
.size _Z10kmp_kernelPcS_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc d_array : %s\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc d_pattern : %s\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc d_answer : %s\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "abcdefghijklmnopqrstuvwxyz"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %c\n"
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "===================== %d \n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%c\n"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Memcpy H->D d_array : %s\n"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Memcpy H->D d_pattern : %s\n"
.size .L.str.8, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Memcpy H->D d_answer : %s\n"
.size .L.str.9, 27
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Memcpy D->H answer : %s\n"
.size .L.str.10, 25
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "%d, %d\n"
.size .L.str.15, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10kmp_kernelPcS_Pi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Array:"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kmp_kernelPcS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kmp_kernelPcS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
} | code for sm_80
Function : _Z12matrixMulGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x1fffff, PT ; /* 0x001fffff0000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R13, R13, c[0x0][0x0], R2 ; /* 0x000000000d0d7a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R13, 0x1fffff, P0 ; /* 0x001fffff0d00780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R13, R13, 0x15, RZ ; /* 0x000000150d0d7819 */
/* 0x000fe200000006ff */
/*00b0*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*00d0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R15, R13, 0x1, RZ ; /* 0x000000010d0f7810 */
/* 0x000fe20007ffe0ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0110*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0120*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0130*/ IMAD.WIDE R10, R13, 0x4, R4 ; /* 0x000000040d0a7825 */
/* 0x000fe200078e0204 */
/*0140*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fc60008000f00 */
/*0150*/ IMAD.WIDE R2, R15, 0x4, R4 ; /* 0x000000040f027825 */
/* 0x000fe200078e0204 */
/*0160*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x0000a6000c1e1900 */
/*0170*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe200078e0206 */
/*0180*/ LDG.E R28, [R2.64] ; /* 0x00000004021c7981 */
/* 0x000ee8000c1e1900 */
/*0190*/ IADD3 R18, P0, R6.reuse, 0x1000000, RZ ; /* 0x0100000006127810 */
/* 0x040fe20007f1e0ff */
/*01a0*/ LDG.E R26, [R6.64] ; /* 0x00000004061a7981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ IMAD.X R19, RZ, RZ, R7, P0 ; /* 0x000000ffff137224 */
/* 0x000fe200000e0607 */
/*01c0*/ IADD3 R8, P0, R6, 0x2000000, RZ ; /* 0x0200000006087810 */
/* 0x000fe20007f1e0ff */
/*01d0*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040402187981 */
/* 0x000f28000c1e1900 */
/*01e0*/ LDG.E R29, [R18.64+-0x800000] ; /* 0x80000004121d7981 */
/* 0x0002e2000c1e1900 */
/*01f0*/ IADD3.X R9, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff097210 */
/* 0x000fc600007fe4ff */
/*0200*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x000322000c1e1900 */
/*0210*/ IADD3 R10, P0, R6, 0x3000000, RZ ; /* 0x03000000060a7810 */
/* 0x001fc60007f1e0ff */
/*0220*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R23, [R8.64+-0x800000] ; /* 0x8000000408177981 */
/* 0x000162000c1e1900 */
/*0240*/ IADD3.X R11, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fc600007fe4ff */
/*0250*/ LDG.E R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R25, [R2.64+0xc] ; /* 0x00000c0402197981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R21, [R10.64+-0x800000] ; /* 0x800000040a157981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x002368000c1e1900 */
/*02a0*/ LDG.E R19, [R2.64+0x14] ; /* 0x0000140402137981 */
/* 0x000f62000c1e1900 */
/*02b0*/ IADD3 R8, P0, R6, 0x4000000, RZ ; /* 0x0400000006087810 */
/* 0x001fc80007f1e0ff */
/*02c0*/ IADD3.X R9, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff097210 */
/* 0x000fe400007fe4ff */
/*02d0*/ IADD3 R10, P0, R6, 0x5000000, RZ ; /* 0x05000000060a7810 */
/* 0x002fc80007f1e0ff */
/*02e0*/ IADD3.X R11, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fe200007fe4ff */
/*02f0*/ IMAD R26, R26, R27, R16 ; /* 0x0000001b1a1a7224 */
/* 0x004fc800078e0210 */
/*0300*/ IMAD R26, R29, R28, R26 ; /* 0x0000001c1d1a7224 */
/* 0x008fe200078e021a */
/*0310*/ IADD3 R16, P1, R6, 0x8000000, RZ ; /* 0x0800000006107810 */
/* 0x000fe20007f3e0ff */
/*0320*/ LDG.E R29, [R2.64+0x2c] ; /* 0x00002c04021d7981 */
/* 0x000ea4000c1e1900 */
/*0330*/ IMAD R24, R17, R24, R26 ; /* 0x0000001811187224 */
/* 0x010fe400078e021a */
/*0340*/ IMAD.X R17, RZ, RZ, R7, P1 ; /* 0x000000ffff117224 */
/* 0x000fe200008e0607 */
/*0350*/ LDG.E R26, [R10.64] ; /* 0x000000040a1a7981 */
/* 0x0000e8000c1e1900 */
/*0360*/ LDG.E R16, [R16.64+-0x800000] ; /* 0x8000000410107981 */
/* 0x000322000c1e1900 */
/*0370*/ IMAD R20, R23, R20, R24 ; /* 0x0000001417147224 */
/* 0x020fc600078e0218 */
/*0380*/ LDG.E R23, [R8.64+-0x800000] ; /* 0x8000000408177981 */
/* 0x000aa8000c1e1900 */
/*0390*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000aa2000c1e1900 */
/*03a0*/ IMAD R20, R22, R25, R20 ; /* 0x0000001916147224 */
/* 0x000fc600078e0214 */
/*03b0*/ LDG.E R22, [R2.64+0x18] ; /* 0x0000180402167981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R25, [R2.64+0x1c] ; /* 0x00001c0402197981 */
/* 0x000ee2000c1e1900 */
/*03d0*/ IMAD R27, R21, R14, R20 ; /* 0x0000000e151b7224 */
/* 0x000fe200078e0214 */
/*03e0*/ IADD3 R20, P0, R6, 0x6000000, RZ ; /* 0x0600000006147810 */
/* 0x000fe40007f1e0ff */
/*03f0*/ LDG.E R14, [R2.64+0x20] ; /* 0x00002004020e7981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R17, [R10.64+-0x800000] ; /* 0x800000040a117981 */
/* 0x002122000c1e1900 */
/*0410*/ IADD3.X R21, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff157210 */
/* 0x000fe200007fe4ff */
/*0420*/ IMAD R18, R18, R19, R27 ; /* 0x0000001312127224 */
/* 0x000fc400078e021b */
/*0430*/ LDG.E R19, [R2.64+0x24] ; /* 0x0000240402137981 */
/* 0x000f22000c1e1900 */
/*0440*/ IADD3 R6, P0, R6, 0x7000000, RZ ; /* 0x0700000006067810 */
/* 0x000fc60007f1e0ff */
/*0450*/ LDG.E R9, [R2.64+0x28] ; /* 0x0000280402097981 */
/* 0x020f68000c1e1900 */
/*0460*/ LDG.E R8, [R20.64+-0x800000] ; /* 0x8000000414087981 */
/* 0x000362000c1e1900 */
/*0470*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fc600000e0607 */
/*0480*/ LDG.E R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x000368000c1e1900 */
/*0490*/ LDG.E R27, [R2.64+0x30] ; /* 0x00003004021b7981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R10, [R2.64+0x34] ; /* 0x00003404020a7981 */
/* 0x001f68000c1e1900 */
/*04b0*/ LDG.E R20, [R6.64+-0x800000] ; /* 0x8000000406147981 */
/* 0x002168000c1e1900 */
/*04c0*/ LDG.E R11, [R2.64+0x38] ; /* 0x00003804020b7981 */
/* 0x000f68000c1e1900 */
/*04d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x001f62000c1e1900 */
/*04e0*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.NE.AND P0, PT, R12, 0x200000, PT ; /* 0x002000000c00780c */
/* 0x000fe20003f05270 */
/*0500*/ UIADD3 UR6, UP0, UR6, 0x8000000, URZ ; /* 0x0800000006067890 */
/* 0x000fe2000ff1e03f */
/*0510*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fc60007f3e0ff */
/*0520*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0530*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0540*/ IMAD R18, R23, R22, R18 ; /* 0x0000001617127224 */
/* 0x004fc800078e0212 */
/*0550*/ IMAD R18, R24, R25, R18 ; /* 0x0000001918127224 */
/* 0x008fc800078e0212 */
/*0560*/ IMAD R14, R17, R14, R18 ; /* 0x0000000e110e7224 */
/* 0x010fc800078e0212 */
/*0570*/ IMAD R14, R26, R19, R14 ; /* 0x000000131a0e7224 */
/* 0x000fc800078e020e */
/*0580*/ IMAD R8, R8, R9, R14 ; /* 0x0000000908087224 */
/* 0x020fc800078e020e */
/*0590*/ IMAD R8, R28, R29, R8 ; /* 0x0000001d1c087224 */
/* 0x000fc800078e0208 */
/*05a0*/ IMAD R8, R20, R27, R8 ; /* 0x0000001b14087224 */
/* 0x000fc800078e0208 */
/*05b0*/ IMAD R7, R7, R10, R8 ; /* 0x0000000a07077224 */
/* 0x000fc800078e0208 */
/*05c0*/ IMAD R16, R16, R11, R7 ; /* 0x0000000b10107224 */
/* 0x000fe200078e0207 */
/*05d0*/ @P0 BRA 0x120 ; /* 0xfffffb4000000947 */
/* 0x000fea000383ffff */
/*05e0*/ IADD3 R2, R0, R13, RZ ; /* 0x0000000d00027210 */
/* 0x000fe40007ffe0ff */
/*05f0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0600*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0610*/ STG.E [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x000fe2000c101904 */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
} | .file "tmpxft_000a01a8_00000000-6_matrixMulGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.type _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, @function
_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, .-_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.globl _Z12matrixMulGPUPiS_S_
.type _Z12matrixMulGPUPiS_S_, @function
_Z12matrixMulGPUPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12matrixMulGPUPiS_S_, .-_Z12matrixMulGPUPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12matrixMulGPUPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matrixMulGPUPiS_S_
.globl _Z12matrixMulGPUPiS_S_
.p2align 8
.type _Z12matrixMulGPUPiS_S_,@function
_Z12matrixMulGPUPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x200000, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 21, v0
v_mov_b32_e32 v4, 0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v2, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v5, vcc_lo, v7, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, 0x200000, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 0x800000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[5:6], off
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v9, v3, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v5
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v0, 21, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matrixMulGPUPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matrixMulGPUPiS_S_, .Lfunc_end0-_Z12matrixMulGPUPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matrixMulGPUPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matrixMulGPUPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
} | .text
.file "matrixMulGPU.hip"
.globl _Z27__device_stub__matrixMulGPUPiS_S_ # -- Begin function _Z27__device_stub__matrixMulGPUPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__matrixMulGPUPiS_S_,@function
_Z27__device_stub__matrixMulGPUPiS_S_: # @_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixMulGPUPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__matrixMulGPUPiS_S_, .Lfunc_end0-_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixMulGPUPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matrixMulGPUPiS_S_,@object # @_Z12matrixMulGPUPiS_S_
.section .rodata,"a",@progbits
.globl _Z12matrixMulGPUPiS_S_
.p2align 3, 0x0
_Z12matrixMulGPUPiS_S_:
.quad _Z27__device_stub__matrixMulGPUPiS_S_
.size _Z12matrixMulGPUPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12matrixMulGPUPiS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matrixMulGPUPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matrixMulGPUPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12matrixMulGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x1fffff, PT ; /* 0x001fffff0000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R13, R13, c[0x0][0x0], R2 ; /* 0x000000000d0d7a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R13, 0x1fffff, P0 ; /* 0x001fffff0d00780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R13, R13, 0x15, RZ ; /* 0x000000150d0d7819 */
/* 0x000fe200000006ff */
/*00b0*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*00d0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R15, R13, 0x1, RZ ; /* 0x000000010d0f7810 */
/* 0x000fe20007ffe0ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0110*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0120*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0130*/ IMAD.WIDE R10, R13, 0x4, R4 ; /* 0x000000040d0a7825 */
/* 0x000fe200078e0204 */
/*0140*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fc60008000f00 */
/*0150*/ IMAD.WIDE R2, R15, 0x4, R4 ; /* 0x000000040f027825 */
/* 0x000fe200078e0204 */
/*0160*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x0000a6000c1e1900 */
/*0170*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe200078e0206 */
/*0180*/ LDG.E R28, [R2.64] ; /* 0x00000004021c7981 */
/* 0x000ee8000c1e1900 */
/*0190*/ IADD3 R18, P0, R6.reuse, 0x1000000, RZ ; /* 0x0100000006127810 */
/* 0x040fe20007f1e0ff */
/*01a0*/ LDG.E R26, [R6.64] ; /* 0x00000004061a7981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ IMAD.X R19, RZ, RZ, R7, P0 ; /* 0x000000ffff137224 */
/* 0x000fe200000e0607 */
/*01c0*/ IADD3 R8, P0, R6, 0x2000000, RZ ; /* 0x0200000006087810 */
/* 0x000fe20007f1e0ff */
/*01d0*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040402187981 */
/* 0x000f28000c1e1900 */
/*01e0*/ LDG.E R29, [R18.64+-0x800000] ; /* 0x80000004121d7981 */
/* 0x0002e2000c1e1900 */
/*01f0*/ IADD3.X R9, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff097210 */
/* 0x000fc600007fe4ff */
/*0200*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x000322000c1e1900 */
/*0210*/ IADD3 R10, P0, R6, 0x3000000, RZ ; /* 0x03000000060a7810 */
/* 0x001fc60007f1e0ff */
/*0220*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R23, [R8.64+-0x800000] ; /* 0x8000000408177981 */
/* 0x000162000c1e1900 */
/*0240*/ IADD3.X R11, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fc600007fe4ff */
/*0250*/ LDG.E R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R25, [R2.64+0xc] ; /* 0x00000c0402197981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R21, [R10.64+-0x800000] ; /* 0x800000040a157981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x002368000c1e1900 */
/*02a0*/ LDG.E R19, [R2.64+0x14] ; /* 0x0000140402137981 */
/* 0x000f62000c1e1900 */
/*02b0*/ IADD3 R8, P0, R6, 0x4000000, RZ ; /* 0x0400000006087810 */
/* 0x001fc80007f1e0ff */
/*02c0*/ IADD3.X R9, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff097210 */
/* 0x000fe400007fe4ff */
/*02d0*/ IADD3 R10, P0, R6, 0x5000000, RZ ; /* 0x05000000060a7810 */
/* 0x002fc80007f1e0ff */
/*02e0*/ IADD3.X R11, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fe200007fe4ff */
/*02f0*/ IMAD R26, R26, R27, R16 ; /* 0x0000001b1a1a7224 */
/* 0x004fc800078e0210 */
/*0300*/ IMAD R26, R29, R28, R26 ; /* 0x0000001c1d1a7224 */
/* 0x008fe200078e021a */
/*0310*/ IADD3 R16, P1, R6, 0x8000000, RZ ; /* 0x0800000006107810 */
/* 0x000fe20007f3e0ff */
/*0320*/ LDG.E R29, [R2.64+0x2c] ; /* 0x00002c04021d7981 */
/* 0x000ea4000c1e1900 */
/*0330*/ IMAD R24, R17, R24, R26 ; /* 0x0000001811187224 */
/* 0x010fe400078e021a */
/*0340*/ IMAD.X R17, RZ, RZ, R7, P1 ; /* 0x000000ffff117224 */
/* 0x000fe200008e0607 */
/*0350*/ LDG.E R26, [R10.64] ; /* 0x000000040a1a7981 */
/* 0x0000e8000c1e1900 */
/*0360*/ LDG.E R16, [R16.64+-0x800000] ; /* 0x8000000410107981 */
/* 0x000322000c1e1900 */
/*0370*/ IMAD R20, R23, R20, R24 ; /* 0x0000001417147224 */
/* 0x020fc600078e0218 */
/*0380*/ LDG.E R23, [R8.64+-0x800000] ; /* 0x8000000408177981 */
/* 0x000aa8000c1e1900 */
/*0390*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000aa2000c1e1900 */
/*03a0*/ IMAD R20, R22, R25, R20 ; /* 0x0000001916147224 */
/* 0x000fc600078e0214 */
/*03b0*/ LDG.E R22, [R2.64+0x18] ; /* 0x0000180402167981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R25, [R2.64+0x1c] ; /* 0x00001c0402197981 */
/* 0x000ee2000c1e1900 */
/*03d0*/ IMAD R27, R21, R14, R20 ; /* 0x0000000e151b7224 */
/* 0x000fe200078e0214 */
/*03e0*/ IADD3 R20, P0, R6, 0x6000000, RZ ; /* 0x0600000006147810 */
/* 0x000fe40007f1e0ff */
/*03f0*/ LDG.E R14, [R2.64+0x20] ; /* 0x00002004020e7981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R17, [R10.64+-0x800000] ; /* 0x800000040a117981 */
/* 0x002122000c1e1900 */
/*0410*/ IADD3.X R21, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff157210 */
/* 0x000fe200007fe4ff */
/*0420*/ IMAD R18, R18, R19, R27 ; /* 0x0000001312127224 */
/* 0x000fc400078e021b */
/*0430*/ LDG.E R19, [R2.64+0x24] ; /* 0x0000240402137981 */
/* 0x000f22000c1e1900 */
/*0440*/ IADD3 R6, P0, R6, 0x7000000, RZ ; /* 0x0700000006067810 */
/* 0x000fc60007f1e0ff */
/*0450*/ LDG.E R9, [R2.64+0x28] ; /* 0x0000280402097981 */
/* 0x020f68000c1e1900 */
/*0460*/ LDG.E R8, [R20.64+-0x800000] ; /* 0x8000000414087981 */
/* 0x000362000c1e1900 */
/*0470*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fc600000e0607 */
/*0480*/ LDG.E R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x000368000c1e1900 */
/*0490*/ LDG.E R27, [R2.64+0x30] ; /* 0x00003004021b7981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R10, [R2.64+0x34] ; /* 0x00003404020a7981 */
/* 0x001f68000c1e1900 */
/*04b0*/ LDG.E R20, [R6.64+-0x800000] ; /* 0x8000000406147981 */
/* 0x002168000c1e1900 */
/*04c0*/ LDG.E R11, [R2.64+0x38] ; /* 0x00003804020b7981 */
/* 0x000f68000c1e1900 */
/*04d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x001f62000c1e1900 */
/*04e0*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.NE.AND P0, PT, R12, 0x200000, PT ; /* 0x002000000c00780c */
/* 0x000fe20003f05270 */
/*0500*/ UIADD3 UR6, UP0, UR6, 0x8000000, URZ ; /* 0x0800000006067890 */
/* 0x000fe2000ff1e03f */
/*0510*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fc60007f3e0ff */
/*0520*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0530*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0540*/ IMAD R18, R23, R22, R18 ; /* 0x0000001617127224 */
/* 0x004fc800078e0212 */
/*0550*/ IMAD R18, R24, R25, R18 ; /* 0x0000001918127224 */
/* 0x008fc800078e0212 */
/*0560*/ IMAD R14, R17, R14, R18 ; /* 0x0000000e110e7224 */
/* 0x010fc800078e0212 */
/*0570*/ IMAD R14, R26, R19, R14 ; /* 0x000000131a0e7224 */
/* 0x000fc800078e020e */
/*0580*/ IMAD R8, R8, R9, R14 ; /* 0x0000000908087224 */
/* 0x020fc800078e020e */
/*0590*/ IMAD R8, R28, R29, R8 ; /* 0x0000001d1c087224 */
/* 0x000fc800078e0208 */
/*05a0*/ IMAD R8, R20, R27, R8 ; /* 0x0000001b14087224 */
/* 0x000fc800078e0208 */
/*05b0*/ IMAD R7, R7, R10, R8 ; /* 0x0000000a07077224 */
/* 0x000fc800078e0208 */
/*05c0*/ IMAD R16, R16, R11, R7 ; /* 0x0000000b10107224 */
/* 0x000fe200078e0207 */
/*05d0*/ @P0 BRA 0x120 ; /* 0xfffffb4000000947 */
/* 0x000fea000383ffff */
/*05e0*/ IADD3 R2, R0, R13, RZ ; /* 0x0000000d00027210 */
/* 0x000fe40007ffe0ff */
/*05f0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0600*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0610*/ STG.E [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x000fe2000c101904 */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matrixMulGPUPiS_S_
.globl _Z12matrixMulGPUPiS_S_
.p2align 8
.type _Z12matrixMulGPUPiS_S_,@function
_Z12matrixMulGPUPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x200000, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 21, v0
v_mov_b32_e32 v4, 0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v2, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v5, vcc_lo, v7, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, 0x200000, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 0x800000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[5:6], off
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v9, v3, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v5
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v0, 21, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matrixMulGPUPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matrixMulGPUPiS_S_, .Lfunc_end0-_Z12matrixMulGPUPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matrixMulGPUPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matrixMulGPUPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a01a8_00000000-6_matrixMulGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.type _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, @function
_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, .-_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.globl _Z12matrixMulGPUPiS_S_
.type _Z12matrixMulGPUPiS_S_, @function
_Z12matrixMulGPUPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12matrixMulGPUPiS_S_, .-_Z12matrixMulGPUPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12matrixMulGPUPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMulGPU.hip"
.globl _Z27__device_stub__matrixMulGPUPiS_S_ # -- Begin function _Z27__device_stub__matrixMulGPUPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__matrixMulGPUPiS_S_,@function
_Z27__device_stub__matrixMulGPUPiS_S_: # @_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixMulGPUPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__matrixMulGPUPiS_S_, .Lfunc_end0-_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixMulGPUPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matrixMulGPUPiS_S_,@object # @_Z12matrixMulGPUPiS_S_
.section .rodata,"a",@progbits
.globl _Z12matrixMulGPUPiS_S_
.p2align 3, 0x0
_Z12matrixMulGPUPiS_S_:
.quad _Z27__device_stub__matrixMulGPUPiS_S_
.size _Z12matrixMulGPUPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12matrixMulGPUPiS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matrixMulGPUPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matrixMulGPUPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Define this to turn on error checking
#define CUDA_ERROR_CHECK
#include <cuda.h>
#include <stdio.h>
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall(cudaError err, const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
if (cudaSuccess != err)
{
fprintf(stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString(err));
exit(-1);
}
#endif
return;
}
inline void __cudaCheckError(const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if (cudaSuccess != err)
{
fprintf(stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString(err));
exit(-1);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if (cudaSuccess != err)
{
fprintf(stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString(err));
exit(-1);
}
#endif
return;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Define this to turn on error checking
#define CUDA_ERROR_CHECK
#include <cuda.h>
#include <stdio.h>
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall(cudaError err, const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
if (cudaSuccess != err)
{
fprintf(stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString(err));
exit(-1);
}
#endif
return;
}
inline void __cudaCheckError(const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if (cudaSuccess != err)
{
fprintf(stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString(err));
exit(-1);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if (cudaSuccess != err)
{
fprintf(stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString(err));
exit(-1);
}
#endif
return;
} | .file "tmpxft_00149faa_00000000-6_errorchecking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Define this to turn on error checking
#define CUDA_ERROR_CHECK
#include <cuda.h>
#include <stdio.h>
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall(cudaError err, const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
if (cudaSuccess != err)
{
fprintf(stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString(err));
exit(-1);
}
#endif
return;
}
inline void __cudaCheckError(const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if (cudaSuccess != err)
{
fprintf(stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString(err));
exit(-1);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if (cudaSuccess != err)
{
fprintf(stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString(err));
exit(-1);
}
#endif
return;
} | // Define this to turn on error checking
#define CUDA_ERROR_CHECK
#include <hip/hip_runtime.h>
#include <stdio.h>
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall(hipError_t err, const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
if (hipSuccess != err)
{
fprintf(stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString(err));
exit(-1);
}
#endif
return;
}
inline void __cudaCheckError(const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
fprintf(stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString(err));
exit(-1);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if (hipSuccess != err)
{
fprintf(stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString(err));
exit(-1);
}
#endif
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Define this to turn on error checking
#define CUDA_ERROR_CHECK
#include <hip/hip_runtime.h>
#include <stdio.h>
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall(hipError_t err, const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
if (hipSuccess != err)
{
fprintf(stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString(err));
exit(-1);
}
#endif
return;
}
inline void __cudaCheckError(const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
fprintf(stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString(err));
exit(-1);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if (hipSuccess != err)
{
fprintf(stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString(err));
exit(-1);
}
#endif
return;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Define this to turn on error checking
#define CUDA_ERROR_CHECK
#include <hip/hip_runtime.h>
#include <stdio.h>
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall(hipError_t err, const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
if (hipSuccess != err)
{
fprintf(stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString(err));
exit(-1);
}
#endif
return;
}
inline void __cudaCheckError(const char *file, const int line)
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
fprintf(stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString(err));
exit(-1);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if (hipSuccess != err)
{
fprintf(stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString(err));
exit(-1);
}
#endif
return;
} | .text
.file "errorchecking.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00149faa_00000000-6_errorchecking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "errorchecking.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // This file is derived from the code at
// http://www.jcornwall.me.uk/2009/04/mersenne-twisters-in-cuda/
// which in turn is derived from the NVIDIA CUDA SDK example 'MersenneTwister'.
/*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
// Some parts contain code from Makoto Matsumoto and Takuji Nishimura's dci.h
/* Copyright (C) 2001-2006 Makoto Matsumoto and Takuji Nishimura. */
/* This library is free software; you can redistribute it and/or */
/* modify it under the terms of the GNU Library General Public */
/* License as published by the Free Software Foundation; either */
/* version 2 of the License, or (at your option) any later */
/* version. */
/* This library is distributed in the hope that it will be useful, */
/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. */
/* See the GNU Library General Public License for more details. */
/* You should have received a copy of the GNU Library General */
/* Public License along with this library; if not, write to the */
/* Free Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA */
/* 02111-1307 USA */
//#include <cassert>
//#include <cstdio>
//#include <vector>
#define MT_MM 9
#define MT_NN 19
#define MT_WMASK 0xFFFFFFFFU
#define MT_UMASK 0xFFFFFFFEU
#define MT_LMASK 0x1U
#define MT_RNG_COUNT 32768
#define MT_SHIFT0 12
#define MT_SHIFTB 7
#define MT_SHIFTC 15
#define MT_SHIFT1 18
// Record format for MersenneTwister.dat, created by spawnTwisters.c
// size = 16 bytes
struct __align__(16) mt_struct_stripped {
unsigned int matrix_a;
unsigned int mask_b;
unsigned int mask_c;
unsigned int seed;
};
// Per-thread state object for a single twister.
// size = 84 bytes but aligned = 96 bytes
struct __align__(16) MersenneTwisterState {
unsigned int mt[MT_NN];
int iState;
unsigned int mti1;
};
// Preloaded, offline-generated seed data structure.
__device__ static mt_struct_stripped MT[MT_RNG_COUNT];
// Hold the current states of the twisters
__device__ static MersenneTwisterState MTS[MT_RNG_COUNT];
__device__ void MersenneTwisterInitialise(MersenneTwisterState *state, unsigned int threadID) {
state->mt[0] = MT[threadID].seed;
for(int i = 1; i < MT_NN; ++ i) {
state->mt[i] = (1812433253U * (state->mt[i - 1] ^ (state->mt[i - 1] >> 30)) + i) & MT_WMASK;
}
state->iState = 0;
state->mti1 = state->mt[0];
}
__device__ unsigned int MersenneTwisterGenerate(MersenneTwisterState *state, unsigned int threadID) {
int iState1 = state->iState + 1;
int iStateM = state->iState + MT_MM;
if(iState1 >= MT_NN) iState1 -= MT_NN;
if(iStateM >= MT_NN) iStateM -= MT_NN;
unsigned int mti = state->mti1;
state->mti1 = state->mt[iState1];
unsigned int mtiM = state->mt[iStateM];
unsigned int x = (mti & MT_UMASK) | (state->mti1 & MT_LMASK);
x = mtiM ^ (x >> 1) ^ ((x & 1) ? MT[threadID].matrix_a : 0);
state->mt[state->iState] = x;
state->iState = iState1;
// Tempering transformation.
x ^= (x >> MT_SHIFT0);
x ^= (x << MT_SHIFTB) & MT[threadID].mask_b;
x ^= (x << MT_SHIFTC) & MT[threadID].mask_c;
x ^= (x >> MT_SHIFT1);
return x;
}
__global__ void InitialiseAllMersenneTwisters() {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
MersenneTwisterInitialise(&(MTS[tid]),tid);
} | code for sm_80
Function : _Z29InitialiseAllMersenneTwistersv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x4][0x0] ; /* 0x0100000000027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R4, [R2.64+0xc] ; /* 0x00000c0402047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R22, RZ, RZ, 0x6c078965 ; /* 0x6c078965ff167424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.U32.HI R5, RZ, 0x1e, R4 ; /* 0x0000001eff057819 */
/* 0x004fc80000011604 */
/*00b0*/ LOP3.LUT R5, R5, R4, RZ, 0x3c, !PT ; /* 0x0000000405057212 */
/* 0x000fca00078e3cff */
/*00c0*/ IMAD R5, R5, R22, 0x1 ; /* 0x0000000105057424 */
/* 0x000fca00078e0216 */
/*00d0*/ SHF.R.U32.HI R6, RZ, 0x1e, R5 ; /* 0x0000001eff067819 */
/* 0x000fc80000011605 */
/*00e0*/ LOP3.LUT R7, R6, R5, RZ, 0x3c, !PT ; /* 0x0000000506077212 */
/* 0x000fca00078e3cff */
/*00f0*/ IMAD R6, R7, R22, 0x2 ; /* 0x0000000207067424 */
/* 0x000fca00078e0216 */
/*0100*/ SHF.R.U32.HI R7, RZ, 0x1e, R6 ; /* 0x0000001eff077819 */
/* 0x000fc80000011606 */
/*0110*/ LOP3.LUT R7, R7, R6, RZ, 0x3c, !PT ; /* 0x0000000607077212 */
/* 0x000fca00078e3cff */
/*0120*/ IMAD R7, R7, R22, 0x3 ; /* 0x0000000307077424 */
/* 0x000fca00078e0216 */
/*0130*/ SHF.R.U32.HI R2, RZ, 0x1e, R7 ; /* 0x0000001eff027819 */
/* 0x000fc80000011607 */
/*0140*/ LOP3.LUT R3, R2, R7, RZ, 0x3c, !PT ; /* 0x0000000702037212 */
/* 0x000fca00078e3cff */
/*0150*/ IMAD R8, R3, R22, 0x4 ; /* 0x0000000403087424 */
/* 0x000fca00078e0216 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1e, R8 ; /* 0x0000001eff037819 */
/* 0x000fc80000011608 */
/*0170*/ LOP3.LUT R3, R3, R8, RZ, 0x3c, !PT ; /* 0x0000000803037212 */
/* 0x000fca00078e3cff */
/*0180*/ IMAD R9, R3, R22, 0x5 ; /* 0x0000000503097424 */
/* 0x000fca00078e0216 */
/*0190*/ SHF.R.U32.HI R2, RZ, 0x1e, R9 ; /* 0x0000001eff027819 */
/* 0x000fc80000011609 */
/*01a0*/ LOP3.LUT R3, R2, R9, RZ, 0x3c, !PT ; /* 0x0000000902037212 */
/* 0x000fca00078e3cff */
/*01b0*/ IMAD R10, R3, R22, 0x6 ; /* 0x00000006030a7424 */
/* 0x000fca00078e0216 */
/*01c0*/ SHF.R.U32.HI R3, RZ, 0x1e, R10 ; /* 0x0000001eff037819 */
/* 0x000fc8000001160a */
/*01d0*/ LOP3.LUT R3, R3, R10, RZ, 0x3c, !PT ; /* 0x0000000a03037212 */
/* 0x000fca00078e3cff */
/*01e0*/ IMAD R11, R3, R22, 0x7 ; /* 0x00000007030b7424 */
/* 0x000fca00078e0216 */
/*01f0*/ SHF.R.U32.HI R2, RZ, 0x1e, R11 ; /* 0x0000001eff027819 */
/* 0x000fc8000001160b */
/*0200*/ LOP3.LUT R3, R2, R11, RZ, 0x3c, !PT ; /* 0x0000000b02037212 */
/* 0x000fca00078e3cff */
/*0210*/ IMAD R12, R3, R22, 0x8 ; /* 0x00000008030c7424 */
/* 0x000fca00078e0216 */
/*0220*/ SHF.R.U32.HI R3, RZ, 0x1e, R12 ; /* 0x0000001eff037819 */
/* 0x000fc8000001160c */
/*0230*/ LOP3.LUT R3, R3, R12, RZ, 0x3c, !PT ; /* 0x0000000c03037212 */
/* 0x000fca00078e3cff */
/*0240*/ IMAD R13, R3, R22, 0x9 ; /* 0x00000009030d7424 */
/* 0x000fca00078e0216 */
/*0250*/ SHF.R.U32.HI R2, RZ, 0x1e, R13 ; /* 0x0000001eff027819 */
/* 0x000fc8000001160d */
/*0260*/ LOP3.LUT R3, R2, R13, RZ, 0x3c, !PT ; /* 0x0000000d02037212 */
/* 0x000fca00078e3cff */
/*0270*/ IMAD R14, R3, R22, 0xa ; /* 0x0000000a030e7424 */
/* 0x000fca00078e0216 */
/*0280*/ SHF.R.U32.HI R3, RZ, 0x1e, R14 ; /* 0x0000001eff037819 */
/* 0x000fc8000001160e */
/*0290*/ LOP3.LUT R3, R3, R14, RZ, 0x3c, !PT ; /* 0x0000000e03037212 */
/* 0x000fca00078e3cff */
/*02a0*/ IMAD R15, R3, R22, 0xb ; /* 0x0000000b030f7424 */
/* 0x000fca00078e0216 */
/*02b0*/ SHF.R.U32.HI R2, RZ, 0x1e, R15 ; /* 0x0000001eff027819 */
/* 0x000fc8000001160f */
/*02c0*/ LOP3.LUT R3, R2, R15, RZ, 0x3c, !PT ; /* 0x0000000f02037212 */
/* 0x000fca00078e3cff */
/*02d0*/ IMAD R16, R3, R22, 0xc ; /* 0x0000000c03107424 */
/* 0x000fca00078e0216 */
/*02e0*/ SHF.R.U32.HI R3, RZ, 0x1e, R16 ; /* 0x0000001eff037819 */
/* 0x000fc80000011610 */
/*02f0*/ LOP3.LUT R3, R3, R16, RZ, 0x3c, !PT ; /* 0x0000001003037212 */
/* 0x000fca00078e3cff */
/*0300*/ IMAD R17, R3, R22, 0xd ; /* 0x0000000d03117424 */
/* 0x000fca00078e0216 */
/*0310*/ SHF.R.U32.HI R2, RZ, 0x1e, R17 ; /* 0x0000001eff027819 */
/* 0x000fc80000011611 */
/*0320*/ LOP3.LUT R3, R2, R17, RZ, 0x3c, !PT ; /* 0x0000001102037212 */
/* 0x000fca00078e3cff */
/*0330*/ IMAD R18, R3, R22, 0xe ; /* 0x0000000e03127424 */
/* 0x000fca00078e0216 */
/*0340*/ SHF.R.U32.HI R3, RZ, 0x1e, R18 ; /* 0x0000001eff037819 */
/* 0x000fc80000011612 */
/*0350*/ LOP3.LUT R3, R3, R18, RZ, 0x3c, !PT ; /* 0x0000001203037212 */
/* 0x000fca00078e3cff */
/*0360*/ IMAD R19, R3, R22, 0xf ; /* 0x0000000f03137424 */
/* 0x000fca00078e0216 */
/*0370*/ SHF.R.U32.HI R2, RZ, 0x1e, R19 ; /* 0x0000001eff027819 */
/* 0x000fc80000011613 */
/*0380*/ LOP3.LUT R3, R2, R19, RZ, 0x3c, !PT ; /* 0x0000001302037212 */
/* 0x000fca00078e3cff */
/*0390*/ IMAD R20, R3, R22, 0x10 ; /* 0x0000001003147424 */
/* 0x000fca00078e0216 */
/*03a0*/ SHF.R.U32.HI R3, RZ, 0x1e, R20 ; /* 0x0000001eff037819 */
/* 0x000fc80000011614 */
/*03b0*/ LOP3.LUT R3, R3, R20, RZ, 0x3c, !PT ; /* 0x0000001403037212 */
/* 0x000fca00078e3cff */
/*03c0*/ IMAD R21, R3, R22, 0x11 ; /* 0x0000001103157424 */
/* 0x000fe400078e0216 */
/*03d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x60 ; /* 0x00000060ff037424 */
/* 0x000fc600078e00ff */
/*03e0*/ SHF.R.U32.HI R24, RZ, 0x1e, R21 ; /* 0x0000001eff187819 */
/* 0x000fe20000011615 */
/*03f0*/ IMAD.WIDE R2, R0, R3, c[0x4][0x8] ; /* 0x0100020000027625 */
/* 0x000fc600078e0203 */
/*0400*/ LOP3.LUT R25, R24, R21, RZ, 0x3c, !PT ; /* 0x0000001518197212 */
/* 0x000fe400078e3cff */
/*0410*/ STG.E [R2.64+0x50], R4 ; /* 0x0000500402007986 */
/* 0x000fe6000c101904 */
/*0420*/ IMAD R22, R25, R22, 0x12 ; /* 0x0000001219167424 */
/* 0x000fe200078e0216 */
/*0430*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101d04 */
/*0440*/ STG.E.128 [R2.64+0x10], R8 ; /* 0x0000100802007986 */
/* 0x000fe8000c101d04 */
/*0450*/ STG.E.128 [R2.64+0x20], R12 ; /* 0x0000200c02007986 */
/* 0x000fe8000c101d04 */
/*0460*/ STG.E.128 [R2.64+0x30], R16 ; /* 0x0000301002007986 */
/* 0x000fe8000c101d04 */
/*0470*/ STG.E.128 [R2.64+0x40], R20 ; /* 0x0000401402007986 */
/* 0x000fe2000c101d04 */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // This file is derived from the code at
// http://www.jcornwall.me.uk/2009/04/mersenne-twisters-in-cuda/
// which in turn is derived from the NVIDIA CUDA SDK example 'MersenneTwister'.
/*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
// Some parts contain code from Makoto Matsumoto and Takuji Nishimura's dci.h
/* Copyright (C) 2001-2006 Makoto Matsumoto and Takuji Nishimura. */
/* This library is free software; you can redistribute it and/or */
/* modify it under the terms of the GNU Library General Public */
/* License as published by the Free Software Foundation; either */
/* version 2 of the License, or (at your option) any later */
/* version. */
/* This library is distributed in the hope that it will be useful, */
/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. */
/* See the GNU Library General Public License for more details. */
/* You should have received a copy of the GNU Library General */
/* Public License along with this library; if not, write to the */
/* Free Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA */
/* 02111-1307 USA */
//#include <cassert>
//#include <cstdio>
//#include <vector>
#define MT_MM 9
#define MT_NN 19
#define MT_WMASK 0xFFFFFFFFU
#define MT_UMASK 0xFFFFFFFEU
#define MT_LMASK 0x1U
#define MT_RNG_COUNT 32768
#define MT_SHIFT0 12
#define MT_SHIFTB 7
#define MT_SHIFTC 15
#define MT_SHIFT1 18
// Record format for MersenneTwister.dat, created by spawnTwisters.c
// size = 16 bytes
struct __align__(16) mt_struct_stripped {
unsigned int matrix_a;
unsigned int mask_b;
unsigned int mask_c;
unsigned int seed;
};
// Per-thread state object for a single twister.
// size = 84 bytes but aligned = 96 bytes
struct __align__(16) MersenneTwisterState {
unsigned int mt[MT_NN];
int iState;
unsigned int mti1;
};
// Preloaded, offline-generated seed data structure.
__device__ static mt_struct_stripped MT[MT_RNG_COUNT];
// Hold the current states of the twisters
__device__ static MersenneTwisterState MTS[MT_RNG_COUNT];
__device__ void MersenneTwisterInitialise(MersenneTwisterState *state, unsigned int threadID) {
state->mt[0] = MT[threadID].seed;
for(int i = 1; i < MT_NN; ++ i) {
state->mt[i] = (1812433253U * (state->mt[i - 1] ^ (state->mt[i - 1] >> 30)) + i) & MT_WMASK;
}
state->iState = 0;
state->mti1 = state->mt[0];
}
__device__ unsigned int MersenneTwisterGenerate(MersenneTwisterState *state, unsigned int threadID) {
int iState1 = state->iState + 1;
int iStateM = state->iState + MT_MM;
if(iState1 >= MT_NN) iState1 -= MT_NN;
if(iStateM >= MT_NN) iStateM -= MT_NN;
unsigned int mti = state->mti1;
state->mti1 = state->mt[iState1];
unsigned int mtiM = state->mt[iStateM];
unsigned int x = (mti & MT_UMASK) | (state->mti1 & MT_LMASK);
x = mtiM ^ (x >> 1) ^ ((x & 1) ? MT[threadID].matrix_a : 0);
state->mt[state->iState] = x;
state->iState = iState1;
// Tempering transformation.
x ^= (x >> MT_SHIFT0);
x ^= (x << MT_SHIFTB) & MT[threadID].mask_b;
x ^= (x << MT_SHIFTC) & MT[threadID].mask_c;
x ^= (x >> MT_SHIFT1);
return x;
}
__global__ void InitialiseAllMersenneTwisters() {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
MersenneTwisterInitialise(&(MTS[tid]),tid);
} | .file "tmpxft_000d5e4d_00000000-6_MersenneTwister.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25MersenneTwisterInitialiseP20MersenneTwisterStatej
.type _Z25MersenneTwisterInitialiseP20MersenneTwisterStatej, @function
_Z25MersenneTwisterInitialiseP20MersenneTwisterStatej:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z25MersenneTwisterInitialiseP20MersenneTwisterStatej, .-_Z25MersenneTwisterInitialiseP20MersenneTwisterStatej
.globl _Z23MersenneTwisterGenerateP20MersenneTwisterStatej
.type _Z23MersenneTwisterGenerateP20MersenneTwisterStatej, @function
_Z23MersenneTwisterGenerateP20MersenneTwisterStatej:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z23MersenneTwisterGenerateP20MersenneTwisterStatej, .-_Z23MersenneTwisterGenerateP20MersenneTwisterStatej
.globl _Z48__device_stub__Z29InitialiseAllMersenneTwistersvv
.type _Z48__device_stub__Z29InitialiseAllMersenneTwistersvv, @function
_Z48__device_stub__Z29InitialiseAllMersenneTwistersvv:
.LFB2053:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z29InitialiseAllMersenneTwistersv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z48__device_stub__Z29InitialiseAllMersenneTwistersvv, .-_Z48__device_stub__Z29InitialiseAllMersenneTwistersvv
.globl _Z29InitialiseAllMersenneTwistersv
.type _Z29InitialiseAllMersenneTwistersv, @function
_Z29InitialiseAllMersenneTwistersv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z29InitialiseAllMersenneTwistersvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z29InitialiseAllMersenneTwistersv, .-_Z29InitialiseAllMersenneTwistersv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29InitialiseAllMersenneTwistersv"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "MT"
.LC2:
.string "MTS"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29InitialiseAllMersenneTwistersv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $524288, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2MT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $3145728, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3MTS(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3MTS
.comm _ZL3MTS,3145728,32
.local _ZL2MT
.comm _ZL2MT,524288,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // This file is derived from the code at
// http://www.jcornwall.me.uk/2009/04/mersenne-twisters-in-cuda/
// which in turn is derived from the NVIDIA CUDA SDK example 'MersenneTwister'.
/*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
// Some parts contain code from Makoto Matsumoto and Takuji Nishimura's dci.h
/* Copyright (C) 2001-2006 Makoto Matsumoto and Takuji Nishimura. */
/* This library is free software; you can redistribute it and/or */
/* modify it under the terms of the GNU Library General Public */
/* License as published by the Free Software Foundation; either */
/* version 2 of the License, or (at your option) any later */
/* version. */
/* This library is distributed in the hope that it will be useful, */
/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. */
/* See the GNU Library General Public License for more details. */
/* You should have received a copy of the GNU Library General */
/* Public License along with this library; if not, write to the */
/* Free Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA */
/* 02111-1307 USA */
//#include <cassert>
//#include <cstdio>
//#include <vector>
#define MT_MM 9
#define MT_NN 19
#define MT_WMASK 0xFFFFFFFFU
#define MT_UMASK 0xFFFFFFFEU
#define MT_LMASK 0x1U
#define MT_RNG_COUNT 32768
#define MT_SHIFT0 12
#define MT_SHIFTB 7
#define MT_SHIFTC 15
#define MT_SHIFT1 18
// Record format for MersenneTwister.dat, created by spawnTwisters.c
// size = 16 bytes
struct __align__(16) mt_struct_stripped {
unsigned int matrix_a;
unsigned int mask_b;
unsigned int mask_c;
unsigned int seed;
};
// Per-thread state object for a single twister.
// size = 84 bytes but aligned = 96 bytes
struct __align__(16) MersenneTwisterState {
unsigned int mt[MT_NN];
int iState;
unsigned int mti1;
};
// Preloaded, offline-generated seed data structure.
__device__ static mt_struct_stripped MT[MT_RNG_COUNT];
// Hold the current states of the twisters
__device__ static MersenneTwisterState MTS[MT_RNG_COUNT];
__device__ void MersenneTwisterInitialise(MersenneTwisterState *state, unsigned int threadID) {
state->mt[0] = MT[threadID].seed;
for(int i = 1; i < MT_NN; ++ i) {
state->mt[i] = (1812433253U * (state->mt[i - 1] ^ (state->mt[i - 1] >> 30)) + i) & MT_WMASK;
}
state->iState = 0;
state->mti1 = state->mt[0];
}
__device__ unsigned int MersenneTwisterGenerate(MersenneTwisterState *state, unsigned int threadID) {
int iState1 = state->iState + 1;
int iStateM = state->iState + MT_MM;
if(iState1 >= MT_NN) iState1 -= MT_NN;
if(iStateM >= MT_NN) iStateM -= MT_NN;
unsigned int mti = state->mti1;
state->mti1 = state->mt[iState1];
unsigned int mtiM = state->mt[iStateM];
unsigned int x = (mti & MT_UMASK) | (state->mti1 & MT_LMASK);
x = mtiM ^ (x >> 1) ^ ((x & 1) ? MT[threadID].matrix_a : 0);
state->mt[state->iState] = x;
state->iState = iState1;
// Tempering transformation.
x ^= (x >> MT_SHIFT0);
x ^= (x << MT_SHIFTB) & MT[threadID].mask_b;
x ^= (x << MT_SHIFTC) & MT[threadID].mask_c;
x ^= (x >> MT_SHIFT1);
return x;
}
__global__ void InitialiseAllMersenneTwisters() {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
MersenneTwisterInitialise(&(MTS[tid]),tid);
} | #include <hip/hip_runtime.h>
// This file is derived from the code at
// http://www.jcornwall.me.uk/2009/04/mersenne-twisters-in-cuda/
// which in turn is derived from the NVIDIA CUDA SDK example 'MersenneTwister'.
/*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
// Some parts contain code from Makoto Matsumoto and Takuji Nishimura's dci.h
/* Copyright (C) 2001-2006 Makoto Matsumoto and Takuji Nishimura. */
/* This library is free software; you can redistribute it and/or */
/* modify it under the terms of the GNU Library General Public */
/* License as published by the Free Software Foundation; either */
/* version 2 of the License, or (at your option) any later */
/* version. */
/* This library is distributed in the hope that it will be useful, */
/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. */
/* See the GNU Library General Public License for more details. */
/* You should have received a copy of the GNU Library General */
/* Public License along with this library; if not, write to the */
/* Free Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA */
/* 02111-1307 USA */
//#include <cassert>
//#include <cstdio>
//#include <vector>
#define MT_MM 9
#define MT_NN 19
#define MT_WMASK 0xFFFFFFFFU
#define MT_UMASK 0xFFFFFFFEU
#define MT_LMASK 0x1U
#define MT_RNG_COUNT 32768
#define MT_SHIFT0 12
#define MT_SHIFTB 7
#define MT_SHIFTC 15
#define MT_SHIFT1 18
// Record format for MersenneTwister.dat, created by spawnTwisters.c
// size = 16 bytes
struct __align__(16) mt_struct_stripped {
unsigned int matrix_a;
unsigned int mask_b;
unsigned int mask_c;
unsigned int seed;
};
// Per-thread state object for a single twister.
// size = 84 bytes but aligned = 96 bytes
struct __align__(16) MersenneTwisterState {
unsigned int mt[MT_NN];
int iState;
unsigned int mti1;
};
// Preloaded, offline-generated seed data structure.
__device__ static mt_struct_stripped MT[MT_RNG_COUNT];
// Hold the current states of the twisters
__device__ static MersenneTwisterState MTS[MT_RNG_COUNT];
__device__ void MersenneTwisterInitialise(MersenneTwisterState *state, unsigned int threadID) {
state->mt[0] = MT[threadID].seed;
for(int i = 1; i < MT_NN; ++ i) {
state->mt[i] = (1812433253U * (state->mt[i - 1] ^ (state->mt[i - 1] >> 30)) + i) & MT_WMASK;
}
state->iState = 0;
state->mti1 = state->mt[0];
}
__device__ unsigned int MersenneTwisterGenerate(MersenneTwisterState *state, unsigned int threadID) {
int iState1 = state->iState + 1;
int iStateM = state->iState + MT_MM;
if(iState1 >= MT_NN) iState1 -= MT_NN;
if(iStateM >= MT_NN) iStateM -= MT_NN;
unsigned int mti = state->mti1;
state->mti1 = state->mt[iState1];
unsigned int mtiM = state->mt[iStateM];
unsigned int x = (mti & MT_UMASK) | (state->mti1 & MT_LMASK);
x = mtiM ^ (x >> 1) ^ ((x & 1) ? MT[threadID].matrix_a : 0);
state->mt[state->iState] = x;
state->iState = iState1;
// Tempering transformation.
x ^= (x >> MT_SHIFT0);
x ^= (x << MT_SHIFTB) & MT[threadID].mask_b;
x ^= (x << MT_SHIFTC) & MT[threadID].mask_c;
x ^= (x >> MT_SHIFT1);
return x;
}
__global__ void InitialiseAllMersenneTwisters() {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
MersenneTwisterInitialise(&(MTS[tid]),tid);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// This file is derived from the code at
// http://www.jcornwall.me.uk/2009/04/mersenne-twisters-in-cuda/
// which in turn is derived from the NVIDIA CUDA SDK example 'MersenneTwister'.
/*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
// Some parts contain code from Makoto Matsumoto and Takuji Nishimura's dci.h
/* Copyright (C) 2001-2006 Makoto Matsumoto and Takuji Nishimura. */
/* This library is free software; you can redistribute it and/or */
/* modify it under the terms of the GNU Library General Public */
/* License as published by the Free Software Foundation; either */
/* version 2 of the License, or (at your option) any later */
/* version. */
/* This library is distributed in the hope that it will be useful, */
/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. */
/* See the GNU Library General Public License for more details. */
/* You should have received a copy of the GNU Library General */
/* Public License along with this library; if not, write to the */
/* Free Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA */
/* 02111-1307 USA */
//#include <cassert>
//#include <cstdio>
//#include <vector>
#define MT_MM 9
#define MT_NN 19
#define MT_WMASK 0xFFFFFFFFU
#define MT_UMASK 0xFFFFFFFEU
#define MT_LMASK 0x1U
#define MT_RNG_COUNT 32768
#define MT_SHIFT0 12
#define MT_SHIFTB 7
#define MT_SHIFTC 15
#define MT_SHIFT1 18
// Record format for MersenneTwister.dat, created by spawnTwisters.c
// size = 16 bytes
struct __align__(16) mt_struct_stripped {
unsigned int matrix_a;
unsigned int mask_b;
unsigned int mask_c;
unsigned int seed;
};
// Per-thread state object for a single twister.
// size = 84 bytes but aligned = 96 bytes
struct __align__(16) MersenneTwisterState {
unsigned int mt[MT_NN];
int iState;
unsigned int mti1;
};
// Preloaded, offline-generated seed data structure.
__device__ static mt_struct_stripped MT[MT_RNG_COUNT];
// Hold the current states of the twisters
__device__ static MersenneTwisterState MTS[MT_RNG_COUNT];
__device__ void MersenneTwisterInitialise(MersenneTwisterState *state, unsigned int threadID) {
state->mt[0] = MT[threadID].seed;
for(int i = 1; i < MT_NN; ++ i) {
state->mt[i] = (1812433253U * (state->mt[i - 1] ^ (state->mt[i - 1] >> 30)) + i) & MT_WMASK;
}
state->iState = 0;
state->mti1 = state->mt[0];
}
__device__ unsigned int MersenneTwisterGenerate(MersenneTwisterState *state, unsigned int threadID) {
int iState1 = state->iState + 1;
int iStateM = state->iState + MT_MM;
if(iState1 >= MT_NN) iState1 -= MT_NN;
if(iStateM >= MT_NN) iStateM -= MT_NN;
unsigned int mti = state->mti1;
state->mti1 = state->mt[iState1];
unsigned int mtiM = state->mt[iStateM];
unsigned int x = (mti & MT_UMASK) | (state->mti1 & MT_LMASK);
x = mtiM ^ (x >> 1) ^ ((x & 1) ? MT[threadID].matrix_a : 0);
state->mt[state->iState] = x;
state->iState = iState1;
// Tempering transformation.
x ^= (x >> MT_SHIFT0);
x ^= (x << MT_SHIFTB) & MT[threadID].mask_b;
x ^= (x << MT_SHIFTC) & MT[threadID].mask_c;
x ^= (x >> MT_SHIFT1);
return x;
}
__global__ void InitialiseAllMersenneTwisters() {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
MersenneTwisterInitialise(&(MTS[tid]),tid);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29InitialiseAllMersenneTwistersv
.globl _Z29InitialiseAllMersenneTwistersv
.p2align 8
.type _Z29InitialiseAllMersenneTwistersv,@function
_Z29InitialiseAllMersenneTwistersv:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, _ZL3MTS@rel32@lo+4
s_addc_u32 s1, s1, _ZL3MTS@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _ZL3MTS@rel32@lo+8
s_addc_u32 s3, s3, _ZL3MTS@rel32@hi+16
v_mov_b32_e32 v0, 0
v_mad_i64_i32 v[4:5], null, v1, 0x60, s[0:1]
v_mad_i64_i32 v[2:3], null, v1, 0x60, s[2:3]
s_mov_b32 s0, 1
s_mov_b32 s1, 0
global_store_b32 v[4:5], v0, off
.LBB0_1:
s_lshr_b32 s2, s1, 30
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s2, s1
s_mul_i32 s1, s1, 0x6c078965
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, s0
s_add_i32 s0, s0, 1
v_mov_b32_e32 v0, s1
s_cmp_lg_u32 s0, 19
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, _ZL3MTS@rel32@lo+80
s_addc_u32 s1, s1, _ZL3MTS@rel32@hi+88
v_mov_b32_e32 v0, 0
v_mad_i64_i32 v[2:3], null, v1, 0x60, s[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v1, v0
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29InitialiseAllMersenneTwistersv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29InitialiseAllMersenneTwistersv, .Lfunc_end0-_Z29InitialiseAllMersenneTwistersv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type _ZL3MTS,@object
.local _ZL3MTS
.comm _ZL3MTS,3145728,4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29InitialiseAllMersenneTwistersv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29InitialiseAllMersenneTwistersv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// This file is derived from the code at
// http://www.jcornwall.me.uk/2009/04/mersenne-twisters-in-cuda/
// which in turn is derived from the NVIDIA CUDA SDK example 'MersenneTwister'.
/*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
// Some parts contain code from Makoto Matsumoto and Takuji Nishimura's dci.h
/* Copyright (C) 2001-2006 Makoto Matsumoto and Takuji Nishimura. */
/* This library is free software; you can redistribute it and/or */
/* modify it under the terms of the GNU Library General Public */
/* License as published by the Free Software Foundation; either */
/* version 2 of the License, or (at your option) any later */
/* version. */
/* This library is distributed in the hope that it will be useful, */
/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. */
/* See the GNU Library General Public License for more details. */
/* You should have received a copy of the GNU Library General */
/* Public License along with this library; if not, write to the */
/* Free Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA */
/* 02111-1307 USA */
//#include <cassert>
//#include <cstdio>
//#include <vector>
#define MT_MM 9
#define MT_NN 19
#define MT_WMASK 0xFFFFFFFFU
#define MT_UMASK 0xFFFFFFFEU
#define MT_LMASK 0x1U
#define MT_RNG_COUNT 32768
#define MT_SHIFT0 12
#define MT_SHIFTB 7
#define MT_SHIFTC 15
#define MT_SHIFT1 18
// Record format for MersenneTwister.dat, created by spawnTwisters.c
// size = 16 bytes
struct __align__(16) mt_struct_stripped {
unsigned int matrix_a;
unsigned int mask_b;
unsigned int mask_c;
unsigned int seed;
};
// Per-thread state object for a single twister.
// size = 84 bytes but aligned = 96 bytes
struct __align__(16) MersenneTwisterState {
unsigned int mt[MT_NN];
int iState;
unsigned int mti1;
};
// Preloaded, offline-generated seed data structure.
__device__ static mt_struct_stripped MT[MT_RNG_COUNT];
// Hold the current states of the twisters
__device__ static MersenneTwisterState MTS[MT_RNG_COUNT];
__device__ void MersenneTwisterInitialise(MersenneTwisterState *state, unsigned int threadID) {
state->mt[0] = MT[threadID].seed;
for(int i = 1; i < MT_NN; ++ i) {
state->mt[i] = (1812433253U * (state->mt[i - 1] ^ (state->mt[i - 1] >> 30)) + i) & MT_WMASK;
}
state->iState = 0;
state->mti1 = state->mt[0];
}
__device__ unsigned int MersenneTwisterGenerate(MersenneTwisterState *state, unsigned int threadID) {
int iState1 = state->iState + 1;
int iStateM = state->iState + MT_MM;
if(iState1 >= MT_NN) iState1 -= MT_NN;
if(iStateM >= MT_NN) iStateM -= MT_NN;
unsigned int mti = state->mti1;
state->mti1 = state->mt[iState1];
unsigned int mtiM = state->mt[iStateM];
unsigned int x = (mti & MT_UMASK) | (state->mti1 & MT_LMASK);
x = mtiM ^ (x >> 1) ^ ((x & 1) ? MT[threadID].matrix_a : 0);
state->mt[state->iState] = x;
state->iState = iState1;
// Tempering transformation.
x ^= (x >> MT_SHIFT0);
x ^= (x << MT_SHIFTB) & MT[threadID].mask_b;
x ^= (x << MT_SHIFTC) & MT[threadID].mask_c;
x ^= (x >> MT_SHIFT1);
return x;
}
__global__ void InitialiseAllMersenneTwisters() {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
MersenneTwisterInitialise(&(MTS[tid]),tid);
} | .text
.file "MersenneTwister.hip"
.globl _Z44__device_stub__InitialiseAllMersenneTwistersv # -- Begin function _Z44__device_stub__InitialiseAllMersenneTwistersv
.p2align 4, 0x90
.type _Z44__device_stub__InitialiseAllMersenneTwistersv,@function
_Z44__device_stub__InitialiseAllMersenneTwistersv: # @_Z44__device_stub__InitialiseAllMersenneTwistersv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z29InitialiseAllMersenneTwistersv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z44__device_stub__InitialiseAllMersenneTwistersv, .Lfunc_end0-_Z44__device_stub__InitialiseAllMersenneTwistersv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29InitialiseAllMersenneTwistersv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29InitialiseAllMersenneTwistersv,@object # @_Z29InitialiseAllMersenneTwistersv
.section .rodata,"a",@progbits
.globl _Z29InitialiseAllMersenneTwistersv
.p2align 3, 0x0
_Z29InitialiseAllMersenneTwistersv:
.quad _Z44__device_stub__InitialiseAllMersenneTwistersv
.size _Z29InitialiseAllMersenneTwistersv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29InitialiseAllMersenneTwistersv"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__InitialiseAllMersenneTwistersv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29InitialiseAllMersenneTwistersv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z29InitialiseAllMersenneTwistersv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x4][0x0] ; /* 0x0100000000027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R4, [R2.64+0xc] ; /* 0x00000c0402047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R22, RZ, RZ, 0x6c078965 ; /* 0x6c078965ff167424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.U32.HI R5, RZ, 0x1e, R4 ; /* 0x0000001eff057819 */
/* 0x004fc80000011604 */
/*00b0*/ LOP3.LUT R5, R5, R4, RZ, 0x3c, !PT ; /* 0x0000000405057212 */
/* 0x000fca00078e3cff */
/*00c0*/ IMAD R5, R5, R22, 0x1 ; /* 0x0000000105057424 */
/* 0x000fca00078e0216 */
/*00d0*/ SHF.R.U32.HI R6, RZ, 0x1e, R5 ; /* 0x0000001eff067819 */
/* 0x000fc80000011605 */
/*00e0*/ LOP3.LUT R7, R6, R5, RZ, 0x3c, !PT ; /* 0x0000000506077212 */
/* 0x000fca00078e3cff */
/*00f0*/ IMAD R6, R7, R22, 0x2 ; /* 0x0000000207067424 */
/* 0x000fca00078e0216 */
/*0100*/ SHF.R.U32.HI R7, RZ, 0x1e, R6 ; /* 0x0000001eff077819 */
/* 0x000fc80000011606 */
/*0110*/ LOP3.LUT R7, R7, R6, RZ, 0x3c, !PT ; /* 0x0000000607077212 */
/* 0x000fca00078e3cff */
/*0120*/ IMAD R7, R7, R22, 0x3 ; /* 0x0000000307077424 */
/* 0x000fca00078e0216 */
/*0130*/ SHF.R.U32.HI R2, RZ, 0x1e, R7 ; /* 0x0000001eff027819 */
/* 0x000fc80000011607 */
/*0140*/ LOP3.LUT R3, R2, R7, RZ, 0x3c, !PT ; /* 0x0000000702037212 */
/* 0x000fca00078e3cff */
/*0150*/ IMAD R8, R3, R22, 0x4 ; /* 0x0000000403087424 */
/* 0x000fca00078e0216 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1e, R8 ; /* 0x0000001eff037819 */
/* 0x000fc80000011608 */
/*0170*/ LOP3.LUT R3, R3, R8, RZ, 0x3c, !PT ; /* 0x0000000803037212 */
/* 0x000fca00078e3cff */
/*0180*/ IMAD R9, R3, R22, 0x5 ; /* 0x0000000503097424 */
/* 0x000fca00078e0216 */
/*0190*/ SHF.R.U32.HI R2, RZ, 0x1e, R9 ; /* 0x0000001eff027819 */
/* 0x000fc80000011609 */
/*01a0*/ LOP3.LUT R3, R2, R9, RZ, 0x3c, !PT ; /* 0x0000000902037212 */
/* 0x000fca00078e3cff */
/*01b0*/ IMAD R10, R3, R22, 0x6 ; /* 0x00000006030a7424 */
/* 0x000fca00078e0216 */
/*01c0*/ SHF.R.U32.HI R3, RZ, 0x1e, R10 ; /* 0x0000001eff037819 */
/* 0x000fc8000001160a */
/*01d0*/ LOP3.LUT R3, R3, R10, RZ, 0x3c, !PT ; /* 0x0000000a03037212 */
/* 0x000fca00078e3cff */
/*01e0*/ IMAD R11, R3, R22, 0x7 ; /* 0x00000007030b7424 */
/* 0x000fca00078e0216 */
/*01f0*/ SHF.R.U32.HI R2, RZ, 0x1e, R11 ; /* 0x0000001eff027819 */
/* 0x000fc8000001160b */
/*0200*/ LOP3.LUT R3, R2, R11, RZ, 0x3c, !PT ; /* 0x0000000b02037212 */
/* 0x000fca00078e3cff */
/*0210*/ IMAD R12, R3, R22, 0x8 ; /* 0x00000008030c7424 */
/* 0x000fca00078e0216 */
/*0220*/ SHF.R.U32.HI R3, RZ, 0x1e, R12 ; /* 0x0000001eff037819 */
/* 0x000fc8000001160c */
/*0230*/ LOP3.LUT R3, R3, R12, RZ, 0x3c, !PT ; /* 0x0000000c03037212 */
/* 0x000fca00078e3cff */
/*0240*/ IMAD R13, R3, R22, 0x9 ; /* 0x00000009030d7424 */
/* 0x000fca00078e0216 */
/*0250*/ SHF.R.U32.HI R2, RZ, 0x1e, R13 ; /* 0x0000001eff027819 */
/* 0x000fc8000001160d */
/*0260*/ LOP3.LUT R3, R2, R13, RZ, 0x3c, !PT ; /* 0x0000000d02037212 */
/* 0x000fca00078e3cff */
/*0270*/ IMAD R14, R3, R22, 0xa ; /* 0x0000000a030e7424 */
/* 0x000fca00078e0216 */
/*0280*/ SHF.R.U32.HI R3, RZ, 0x1e, R14 ; /* 0x0000001eff037819 */
/* 0x000fc8000001160e */
/*0290*/ LOP3.LUT R3, R3, R14, RZ, 0x3c, !PT ; /* 0x0000000e03037212 */
/* 0x000fca00078e3cff */
/*02a0*/ IMAD R15, R3, R22, 0xb ; /* 0x0000000b030f7424 */
/* 0x000fca00078e0216 */
/*02b0*/ SHF.R.U32.HI R2, RZ, 0x1e, R15 ; /* 0x0000001eff027819 */
/* 0x000fc8000001160f */
/*02c0*/ LOP3.LUT R3, R2, R15, RZ, 0x3c, !PT ; /* 0x0000000f02037212 */
/* 0x000fca00078e3cff */
/*02d0*/ IMAD R16, R3, R22, 0xc ; /* 0x0000000c03107424 */
/* 0x000fca00078e0216 */
/*02e0*/ SHF.R.U32.HI R3, RZ, 0x1e, R16 ; /* 0x0000001eff037819 */
/* 0x000fc80000011610 */
/*02f0*/ LOP3.LUT R3, R3, R16, RZ, 0x3c, !PT ; /* 0x0000001003037212 */
/* 0x000fca00078e3cff */
/*0300*/ IMAD R17, R3, R22, 0xd ; /* 0x0000000d03117424 */
/* 0x000fca00078e0216 */
/*0310*/ SHF.R.U32.HI R2, RZ, 0x1e, R17 ; /* 0x0000001eff027819 */
/* 0x000fc80000011611 */
/*0320*/ LOP3.LUT R3, R2, R17, RZ, 0x3c, !PT ; /* 0x0000001102037212 */
/* 0x000fca00078e3cff */
/*0330*/ IMAD R18, R3, R22, 0xe ; /* 0x0000000e03127424 */
/* 0x000fca00078e0216 */
/*0340*/ SHF.R.U32.HI R3, RZ, 0x1e, R18 ; /* 0x0000001eff037819 */
/* 0x000fc80000011612 */
/*0350*/ LOP3.LUT R3, R3, R18, RZ, 0x3c, !PT ; /* 0x0000001203037212 */
/* 0x000fca00078e3cff */
/*0360*/ IMAD R19, R3, R22, 0xf ; /* 0x0000000f03137424 */
/* 0x000fca00078e0216 */
/*0370*/ SHF.R.U32.HI R2, RZ, 0x1e, R19 ; /* 0x0000001eff027819 */
/* 0x000fc80000011613 */
/*0380*/ LOP3.LUT R3, R2, R19, RZ, 0x3c, !PT ; /* 0x0000001302037212 */
/* 0x000fca00078e3cff */
/*0390*/ IMAD R20, R3, R22, 0x10 ; /* 0x0000001003147424 */
/* 0x000fca00078e0216 */
/*03a0*/ SHF.R.U32.HI R3, RZ, 0x1e, R20 ; /* 0x0000001eff037819 */
/* 0x000fc80000011614 */
/*03b0*/ LOP3.LUT R3, R3, R20, RZ, 0x3c, !PT ; /* 0x0000001403037212 */
/* 0x000fca00078e3cff */
/*03c0*/ IMAD R21, R3, R22, 0x11 ; /* 0x0000001103157424 */
/* 0x000fe400078e0216 */
/*03d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x60 ; /* 0x00000060ff037424 */
/* 0x000fc600078e00ff */
/*03e0*/ SHF.R.U32.HI R24, RZ, 0x1e, R21 ; /* 0x0000001eff187819 */
/* 0x000fe20000011615 */
/*03f0*/ IMAD.WIDE R2, R0, R3, c[0x4][0x8] ; /* 0x0100020000027625 */
/* 0x000fc600078e0203 */
/*0400*/ LOP3.LUT R25, R24, R21, RZ, 0x3c, !PT ; /* 0x0000001518197212 */
/* 0x000fe400078e3cff */
/*0410*/ STG.E [R2.64+0x50], R4 ; /* 0x0000500402007986 */
/* 0x000fe6000c101904 */
/*0420*/ IMAD R22, R25, R22, 0x12 ; /* 0x0000001219167424 */
/* 0x000fe200078e0216 */
/*0430*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101d04 */
/*0440*/ STG.E.128 [R2.64+0x10], R8 ; /* 0x0000100802007986 */
/* 0x000fe8000c101d04 */
/*0450*/ STG.E.128 [R2.64+0x20], R12 ; /* 0x0000200c02007986 */
/* 0x000fe8000c101d04 */
/*0460*/ STG.E.128 [R2.64+0x30], R16 ; /* 0x0000301002007986 */
/* 0x000fe8000c101d04 */
/*0470*/ STG.E.128 [R2.64+0x40], R20 ; /* 0x0000401402007986 */
/* 0x000fe2000c101d04 */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29InitialiseAllMersenneTwistersv
.globl _Z29InitialiseAllMersenneTwistersv
.p2align 8
.type _Z29InitialiseAllMersenneTwistersv,@function
_Z29InitialiseAllMersenneTwistersv:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, _ZL3MTS@rel32@lo+4
s_addc_u32 s1, s1, _ZL3MTS@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _ZL3MTS@rel32@lo+8
s_addc_u32 s3, s3, _ZL3MTS@rel32@hi+16
v_mov_b32_e32 v0, 0
v_mad_i64_i32 v[4:5], null, v1, 0x60, s[0:1]
v_mad_i64_i32 v[2:3], null, v1, 0x60, s[2:3]
s_mov_b32 s0, 1
s_mov_b32 s1, 0
global_store_b32 v[4:5], v0, off
.LBB0_1:
s_lshr_b32 s2, s1, 30
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s2, s1
s_mul_i32 s1, s1, 0x6c078965
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, s0
s_add_i32 s0, s0, 1
v_mov_b32_e32 v0, s1
s_cmp_lg_u32 s0, 19
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, _ZL3MTS@rel32@lo+80
s_addc_u32 s1, s1, _ZL3MTS@rel32@hi+88
v_mov_b32_e32 v0, 0
v_mad_i64_i32 v[2:3], null, v1, 0x60, s[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v1, v0
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29InitialiseAllMersenneTwistersv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29InitialiseAllMersenneTwistersv, .Lfunc_end0-_Z29InitialiseAllMersenneTwistersv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type _ZL3MTS,@object
.local _ZL3MTS
.comm _ZL3MTS,3145728,4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29InitialiseAllMersenneTwistersv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29InitialiseAllMersenneTwistersv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d5e4d_00000000-6_MersenneTwister.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25MersenneTwisterInitialiseP20MersenneTwisterStatej
.type _Z25MersenneTwisterInitialiseP20MersenneTwisterStatej, @function
_Z25MersenneTwisterInitialiseP20MersenneTwisterStatej:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z25MersenneTwisterInitialiseP20MersenneTwisterStatej, .-_Z25MersenneTwisterInitialiseP20MersenneTwisterStatej
.globl _Z23MersenneTwisterGenerateP20MersenneTwisterStatej
.type _Z23MersenneTwisterGenerateP20MersenneTwisterStatej, @function
_Z23MersenneTwisterGenerateP20MersenneTwisterStatej:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z23MersenneTwisterGenerateP20MersenneTwisterStatej, .-_Z23MersenneTwisterGenerateP20MersenneTwisterStatej
.globl _Z48__device_stub__Z29InitialiseAllMersenneTwistersvv
.type _Z48__device_stub__Z29InitialiseAllMersenneTwistersvv, @function
_Z48__device_stub__Z29InitialiseAllMersenneTwistersvv:
.LFB2053:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z29InitialiseAllMersenneTwistersv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z48__device_stub__Z29InitialiseAllMersenneTwistersvv, .-_Z48__device_stub__Z29InitialiseAllMersenneTwistersvv
.globl _Z29InitialiseAllMersenneTwistersv
.type _Z29InitialiseAllMersenneTwistersv, @function
_Z29InitialiseAllMersenneTwistersv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z29InitialiseAllMersenneTwistersvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z29InitialiseAllMersenneTwistersv, .-_Z29InitialiseAllMersenneTwistersv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29InitialiseAllMersenneTwistersv"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "MT"
.LC2:
.string "MTS"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29InitialiseAllMersenneTwistersv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $524288, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2MT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $3145728, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3MTS(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3MTS
.comm _ZL3MTS,3145728,32
.local _ZL2MT
.comm _ZL2MT,524288,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MersenneTwister.hip"
.globl _Z44__device_stub__InitialiseAllMersenneTwistersv # -- Begin function _Z44__device_stub__InitialiseAllMersenneTwistersv
.p2align 4, 0x90
.type _Z44__device_stub__InitialiseAllMersenneTwistersv,@function
_Z44__device_stub__InitialiseAllMersenneTwistersv: # @_Z44__device_stub__InitialiseAllMersenneTwistersv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z29InitialiseAllMersenneTwistersv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z44__device_stub__InitialiseAllMersenneTwistersv, .Lfunc_end0-_Z44__device_stub__InitialiseAllMersenneTwistersv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29InitialiseAllMersenneTwistersv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29InitialiseAllMersenneTwistersv,@object # @_Z29InitialiseAllMersenneTwistersv
.section .rodata,"a",@progbits
.globl _Z29InitialiseAllMersenneTwistersv
.p2align 3, 0x0
_Z29InitialiseAllMersenneTwistersv:
.quad _Z44__device_stub__InitialiseAllMersenneTwistersv
.size _Z29InitialiseAllMersenneTwistersv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29InitialiseAllMersenneTwistersv"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__InitialiseAllMersenneTwistersv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29InitialiseAllMersenneTwistersv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sneldiv(unsigned short *inA, float *inB, int *sub, int Nprj, int snno)
{
int idz = threadIdx.x + blockDim.x*blockIdx.x;
if (blockIdx.y<Nprj && idz<snno) {
// inB > only active bins of the subset
// inA > all sinogram bins
float a = (float)inA[snno*sub[blockIdx.y] + idz];
a /= inB[snno*blockIdx.y + idz];//sub[blockIdx.y]
inB[snno*blockIdx.y + idz] = a; //sub[blockIdx.y]
}
} | code for sm_80
Function : _Z7sneldivPtPfPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e620000002600 */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc80003f06270 */
/*0060*/ ISETP.GE.U32.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x002fda0000706470 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE.U32 R4, R7, R3, c[0x0][0x170] ; /* 0x00005c0007047625 */
/* 0x000fcc00078e0003 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R2, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007027a24 */
/* 0x000fe400078e0200 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0003 */
/*00f0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ee2000c1e1900 */
/*0100*/ IMAD R6, R5, c[0x0][0x17c], R0 ; /* 0x00005f0005067a24 */
/* 0x004fc800078e0200 */
/*0110*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fcc00078e0207 */
/*0120*/ LDG.E.U16 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1500 */
/*0130*/ MUFU.RCP R0, R9 ; /* 0x0000000900007308 */
/* 0x008e220000001000 */
/*0140*/ BSSY B0, 0x200 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0150*/ FFMA R11, -R9, R0, 1 ; /* 0x3f800000090b7423 */
/* 0x001fc80000000100 */
/*0160*/ FFMA R11, R0, R11, R0 ; /* 0x0000000b000b7223 */
/* 0x000fe40000000000 */
/*0170*/ I2F.U16 R8, R6 ; /* 0x0000000600087306 */
/* 0x004e300000101000 */
/*0180*/ FCHK P0, R8, R9 ; /* 0x0000000908007302 */
/* 0x001e220000000000 */
/*0190*/ FFMA R0, R8, R11, RZ ; /* 0x0000000b08007223 */
/* 0x000fc800000000ff */
/*01a0*/ FFMA R4, -R9, R0, R8 ; /* 0x0000000009047223 */
/* 0x000fc80000000108 */
/*01b0*/ FFMA R11, R11, R4, R0 ; /* 0x000000040b0b7223 */
/* 0x000fe20000000000 */
/*01c0*/ @!P0 BRA 0x1f0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*01d0*/ MOV R0, 0x1f0 ; /* 0x000001f000007802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x220 ; /* 0x0000003000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R5, RZ, 0x17, R9.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011609 */
/*0230*/ BSSY B1, 0x880 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0240*/ SHF.R.U32.HI R4, RZ, 0x17, R8.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011608 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0260*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0280*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0290*/ IADD3 R12, R5, -0x1, RZ ; /* 0xffffffff050c7810 */
/* 0x000fc40007ffe0ff */
/*02a0*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*02c0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*02d0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P0 BRA 0x460 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0300*/ FSETP.GTU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f3c200 */
/*0310*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0320*/ @P0 BRA 0x860 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0330*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0340*/ @!P0 BRA 0x840 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*0360*/ FSETP.NEU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f3d200 */
/*0370*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*0380*/ @!P1 BRA !P2, 0x840 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0390*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*03a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03b0*/ @P1 BRA 0x820 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BRA 0x7f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0400*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0410*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0430*/ @!P0 FFMA R6, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008068823 */
/* 0x000fe400000000ff */
/*0440*/ @!P1 FFMA R7, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009079823 */
/* 0x000fe200000000ff */
/*0450*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA R8, R5, 0xc0800000, 0x17 ; /* 0xc080000005087811 */
/* 0x000fe200078eb8ff */
/*0470*/ BSSY B2, 0x7e0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0480*/ IMAD.IADD R8, R7, 0x1, -R8 ; /* 0x0000000107087824 */
/* 0x000fe200078e0a08 */
/*0490*/ IADD3 R7, R4, -0x7f, RZ ; /* 0xffffff8104077810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e220000001000 */
/*04b0*/ FADD.FTZ R11, -R8, -RZ ; /* 0x800000ff080b7221 */
/* 0x000fe40000010100 */
/*04c0*/ IMAD R6, R7.reuse, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x040fe200078e0206 */
/*04d0*/ IADD3 R7, R7, 0x7f, -R5 ; /* 0x0000007f07077810 */
/* 0x000fca0007ffe805 */
/*04e0*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*04f0*/ FFMA R4, R9, R11, 1 ; /* 0x3f80000009047423 */
/* 0x001fc8000000000b */
/*0500*/ FFMA R13, R9, R4, R9 ; /* 0x00000004090d7223 */
/* 0x000fc80000000009 */
/*0510*/ FFMA R4, R6, R13, RZ ; /* 0x0000000d06047223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R9, R11, R4, R6 ; /* 0x000000040b097223 */
/* 0x000fc80000000006 */
/*0530*/ FFMA R12, R13, R9, R4 ; /* 0x000000090d0c7223 */
/* 0x000fc80000000004 */
/*0540*/ FFMA R6, R11, R12, R6 ; /* 0x0000000c0b067223 */
/* 0x000fc80000000006 */
/*0550*/ FFMA R4, R13, R6, R12 ; /* 0x000000060d047223 */
/* 0x000fca000000000c */
/*0560*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0570*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0580*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0590*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*05b0*/ @!P0 BRA 0x7c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*05d0*/ @P0 BRA 0x790 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05f0*/ @P0 BRA 0x7d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0610*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0620*/ @!P0 BRA 0x7d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0630*/ FFMA.RZ R5, R13, R6.reuse, R12.reuse ; /* 0x000000060d057223 */
/* 0x180fe2000000c00c */
/*0640*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe40007ffe0ff */
/*0650*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0660*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0670*/ FFMA.RP R5, R13, R6.reuse, R12.reuse ; /* 0x000000060d057223 */
/* 0x180fe2000000800c */
/*0680*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0690*/ FFMA.RM R6, R13, R6, R12 ; /* 0x000000060d067223 */
/* 0x000fe2000000400c */
/*06a0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe200078efcff */
/*06b0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0a09 */
/*06c0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06d0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fe40003f1d000 */
/*06e0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06f0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0700*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0710*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0720*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fe40000011606 */
/*0730*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0740*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0750*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0760*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0770*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*07a0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x7d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*07d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x870 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R4, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fc800078e4806 */
/*0800*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R4, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fe200078e4806 */
/*0830*/ BRA 0x870 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0840*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ FADD.FTZ R4, R8, R9 ; /* 0x0000000908047221 */
/* 0x000fe40000010000 */
/*0870*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b7224 */
/* 0x001fe400078e0004 */
/*0890*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*08a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08b0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff74004007950 */
/* 0x000fea0003c3ffff */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sneldiv(unsigned short *inA, float *inB, int *sub, int Nprj, int snno)
{
int idz = threadIdx.x + blockDim.x*blockIdx.x;
if (blockIdx.y<Nprj && idz<snno) {
// inB > only active bins of the subset
// inA > all sinogram bins
float a = (float)inA[snno*sub[blockIdx.y] + idz];
a /= inB[snno*blockIdx.y + idz];//sub[blockIdx.y]
inB[snno*blockIdx.y + idz] = a; //sub[blockIdx.y]
}
} | .file "tmpxft_001384c2_00000000-6_sneldiv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii
.type _Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii, @function
_Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sneldivPtPfPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii, .-_Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii
.globl _Z7sneldivPtPfPiii
.type _Z7sneldivPtPfPiii, @function
_Z7sneldivPtPfPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7sneldivPtPfPiii, .-_Z7sneldivPtPfPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7sneldivPtPfPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sneldivPtPfPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sneldiv(unsigned short *inA, float *inB, int *sub, int Nprj, int snno)
{
int idz = threadIdx.x + blockDim.x*blockIdx.x;
if (blockIdx.y<Nprj && idz<snno) {
// inB > only active bins of the subset
// inA > all sinogram bins
float a = (float)inA[snno*sub[blockIdx.y] + idz];
a /= inB[snno*blockIdx.y + idz];//sub[blockIdx.y]
inB[snno*blockIdx.y + idz] = a; //sub[blockIdx.y]
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sneldiv(unsigned short *inA, float *inB, int *sub, int Nprj, int snno)
{
int idz = threadIdx.x + blockDim.x*blockIdx.x;
if (blockIdx.y<Nprj && idz<snno) {
// inB > only active bins of the subset
// inA > all sinogram bins
float a = (float)inA[snno*sub[blockIdx.y] + idz];
a /= inB[snno*blockIdx.y + idz];//sub[blockIdx.y]
inB[snno*blockIdx.y + idz] = a; //sub[blockIdx.y]
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sneldiv(unsigned short *inA, float *inB, int *sub, int Nprj, int snno)
{
int idz = threadIdx.x + blockDim.x*blockIdx.x;
if (blockIdx.y<Nprj && idz<snno) {
// inB > only active bins of the subset
// inA > all sinogram bins
float a = (float)inA[snno*sub[blockIdx.y] + idz];
a /= inB[snno*blockIdx.y + idz];//sub[blockIdx.y]
inB[snno*blockIdx.y + idz] = a; //sub[blockIdx.y]
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sneldivPtPfPiii
.globl _Z7sneldivPtPfPiii
.p2align 8
.type _Z7sneldivPtPfPiii,@function
_Z7sneldivPtPfPiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_u32 s15, s4
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
s_load_b32 s3, s[6:7], 0x0
s_load_b128 s[8:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s3, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_mad_u64_u32 v[4:5], null, s2, s5, v[1:2]
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[0:1], 1, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
global_load_u16 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(1)
v_cvt_f32_u32_e32 v0, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v1, v1, v0
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v0, v1, v0
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v4, v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sneldivPtPfPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sneldivPtPfPiii, .Lfunc_end0-_Z7sneldivPtPfPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sneldivPtPfPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7sneldivPtPfPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sneldiv(unsigned short *inA, float *inB, int *sub, int Nprj, int snno)
{
int idz = threadIdx.x + blockDim.x*blockIdx.x;
if (blockIdx.y<Nprj && idz<snno) {
// inB > only active bins of the subset
// inA > all sinogram bins
float a = (float)inA[snno*sub[blockIdx.y] + idz];
a /= inB[snno*blockIdx.y + idz];//sub[blockIdx.y]
inB[snno*blockIdx.y + idz] = a; //sub[blockIdx.y]
}
} | .text
.file "sneldiv.hip"
.globl _Z22__device_stub__sneldivPtPfPiii # -- Begin function _Z22__device_stub__sneldivPtPfPiii
.p2align 4, 0x90
.type _Z22__device_stub__sneldivPtPfPiii,@function
_Z22__device_stub__sneldivPtPfPiii: # @_Z22__device_stub__sneldivPtPfPiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sneldivPtPfPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__sneldivPtPfPiii, .Lfunc_end0-_Z22__device_stub__sneldivPtPfPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sneldivPtPfPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sneldivPtPfPiii,@object # @_Z7sneldivPtPfPiii
.section .rodata,"a",@progbits
.globl _Z7sneldivPtPfPiii
.p2align 3, 0x0
_Z7sneldivPtPfPiii:
.quad _Z22__device_stub__sneldivPtPfPiii
.size _Z7sneldivPtPfPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7sneldivPtPfPiii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sneldivPtPfPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sneldivPtPfPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7sneldivPtPfPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e620000002600 */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc80003f06270 */
/*0060*/ ISETP.GE.U32.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x002fda0000706470 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE.U32 R4, R7, R3, c[0x0][0x170] ; /* 0x00005c0007047625 */
/* 0x000fcc00078e0003 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R2, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007027a24 */
/* 0x000fe400078e0200 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0003 */
/*00f0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ee2000c1e1900 */
/*0100*/ IMAD R6, R5, c[0x0][0x17c], R0 ; /* 0x00005f0005067a24 */
/* 0x004fc800078e0200 */
/*0110*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fcc00078e0207 */
/*0120*/ LDG.E.U16 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1500 */
/*0130*/ MUFU.RCP R0, R9 ; /* 0x0000000900007308 */
/* 0x008e220000001000 */
/*0140*/ BSSY B0, 0x200 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0150*/ FFMA R11, -R9, R0, 1 ; /* 0x3f800000090b7423 */
/* 0x001fc80000000100 */
/*0160*/ FFMA R11, R0, R11, R0 ; /* 0x0000000b000b7223 */
/* 0x000fe40000000000 */
/*0170*/ I2F.U16 R8, R6 ; /* 0x0000000600087306 */
/* 0x004e300000101000 */
/*0180*/ FCHK P0, R8, R9 ; /* 0x0000000908007302 */
/* 0x001e220000000000 */
/*0190*/ FFMA R0, R8, R11, RZ ; /* 0x0000000b08007223 */
/* 0x000fc800000000ff */
/*01a0*/ FFMA R4, -R9, R0, R8 ; /* 0x0000000009047223 */
/* 0x000fc80000000108 */
/*01b0*/ FFMA R11, R11, R4, R0 ; /* 0x000000040b0b7223 */
/* 0x000fe20000000000 */
/*01c0*/ @!P0 BRA 0x1f0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*01d0*/ MOV R0, 0x1f0 ; /* 0x000001f000007802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x220 ; /* 0x0000003000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R5, RZ, 0x17, R9.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011609 */
/*0230*/ BSSY B1, 0x880 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0240*/ SHF.R.U32.HI R4, RZ, 0x17, R8.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011608 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0260*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0280*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0290*/ IADD3 R12, R5, -0x1, RZ ; /* 0xffffffff050c7810 */
/* 0x000fc40007ffe0ff */
/*02a0*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*02c0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*02d0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P0 BRA 0x460 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0300*/ FSETP.GTU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f3c200 */
/*0310*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0320*/ @P0 BRA 0x860 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0330*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0340*/ @!P0 BRA 0x840 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*0360*/ FSETP.NEU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f3d200 */
/*0370*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*0380*/ @!P1 BRA !P2, 0x840 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0390*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*03a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03b0*/ @P1 BRA 0x820 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BRA 0x7f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0400*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0410*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0430*/ @!P0 FFMA R6, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008068823 */
/* 0x000fe400000000ff */
/*0440*/ @!P1 FFMA R7, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009079823 */
/* 0x000fe200000000ff */
/*0450*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA R8, R5, 0xc0800000, 0x17 ; /* 0xc080000005087811 */
/* 0x000fe200078eb8ff */
/*0470*/ BSSY B2, 0x7e0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0480*/ IMAD.IADD R8, R7, 0x1, -R8 ; /* 0x0000000107087824 */
/* 0x000fe200078e0a08 */
/*0490*/ IADD3 R7, R4, -0x7f, RZ ; /* 0xffffff8104077810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e220000001000 */
/*04b0*/ FADD.FTZ R11, -R8, -RZ ; /* 0x800000ff080b7221 */
/* 0x000fe40000010100 */
/*04c0*/ IMAD R6, R7.reuse, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x040fe200078e0206 */
/*04d0*/ IADD3 R7, R7, 0x7f, -R5 ; /* 0x0000007f07077810 */
/* 0x000fca0007ffe805 */
/*04e0*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*04f0*/ FFMA R4, R9, R11, 1 ; /* 0x3f80000009047423 */
/* 0x001fc8000000000b */
/*0500*/ FFMA R13, R9, R4, R9 ; /* 0x00000004090d7223 */
/* 0x000fc80000000009 */
/*0510*/ FFMA R4, R6, R13, RZ ; /* 0x0000000d06047223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R9, R11, R4, R6 ; /* 0x000000040b097223 */
/* 0x000fc80000000006 */
/*0530*/ FFMA R12, R13, R9, R4 ; /* 0x000000090d0c7223 */
/* 0x000fc80000000004 */
/*0540*/ FFMA R6, R11, R12, R6 ; /* 0x0000000c0b067223 */
/* 0x000fc80000000006 */
/*0550*/ FFMA R4, R13, R6, R12 ; /* 0x000000060d047223 */
/* 0x000fca000000000c */
/*0560*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0570*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0580*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0590*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*05b0*/ @!P0 BRA 0x7c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*05d0*/ @P0 BRA 0x790 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05f0*/ @P0 BRA 0x7d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0610*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0620*/ @!P0 BRA 0x7d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0630*/ FFMA.RZ R5, R13, R6.reuse, R12.reuse ; /* 0x000000060d057223 */
/* 0x180fe2000000c00c */
/*0640*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe40007ffe0ff */
/*0650*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0660*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0670*/ FFMA.RP R5, R13, R6.reuse, R12.reuse ; /* 0x000000060d057223 */
/* 0x180fe2000000800c */
/*0680*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0690*/ FFMA.RM R6, R13, R6, R12 ; /* 0x000000060d067223 */
/* 0x000fe2000000400c */
/*06a0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe200078efcff */
/*06b0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0a09 */
/*06c0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06d0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fe40003f1d000 */
/*06e0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06f0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0700*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0710*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0720*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fe40000011606 */
/*0730*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0740*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0750*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0760*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0770*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*07a0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x7d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*07d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x870 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R4, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fc800078e4806 */
/*0800*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R4, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fe200078e4806 */
/*0830*/ BRA 0x870 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0840*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ FADD.FTZ R4, R8, R9 ; /* 0x0000000908047221 */
/* 0x000fe40000010000 */
/*0870*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b7224 */
/* 0x001fe400078e0004 */
/*0890*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*08a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08b0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff74004007950 */
/* 0x000fea0003c3ffff */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sneldivPtPfPiii
.globl _Z7sneldivPtPfPiii
.p2align 8
.type _Z7sneldivPtPfPiii,@function
_Z7sneldivPtPfPiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_u32 s15, s4
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
s_load_b32 s3, s[6:7], 0x0
s_load_b128 s[8:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s3, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_mad_u64_u32 v[4:5], null, s2, s5, v[1:2]
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[0:1], 1, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
global_load_u16 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(1)
v_cvt_f32_u32_e32 v0, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v1, v1, v0
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v0, v1, v0
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v4, v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sneldivPtPfPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sneldivPtPfPiii, .Lfunc_end0-_Z7sneldivPtPfPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sneldivPtPfPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7sneldivPtPfPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001384c2_00000000-6_sneldiv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii
.type _Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii, @function
_Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sneldivPtPfPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii, .-_Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii
.globl _Z7sneldivPtPfPiii
.type _Z7sneldivPtPfPiii, @function
_Z7sneldivPtPfPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7sneldivPtPfPiiiPtPfPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7sneldivPtPfPiii, .-_Z7sneldivPtPfPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7sneldivPtPfPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sneldivPtPfPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sneldiv.hip"
.globl _Z22__device_stub__sneldivPtPfPiii # -- Begin function _Z22__device_stub__sneldivPtPfPiii
.p2align 4, 0x90
.type _Z22__device_stub__sneldivPtPfPiii,@function
_Z22__device_stub__sneldivPtPfPiii: # @_Z22__device_stub__sneldivPtPfPiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sneldivPtPfPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__sneldivPtPfPiii, .Lfunc_end0-_Z22__device_stub__sneldivPtPfPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sneldivPtPfPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sneldivPtPfPiii,@object # @_Z7sneldivPtPfPiii
.section .rodata,"a",@progbits
.globl _Z7sneldivPtPfPiii
.p2align 3, 0x0
_Z7sneldivPtPfPiii:
.quad _Z22__device_stub__sneldivPtPfPiii
.size _Z7sneldivPtPfPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7sneldivPtPfPiii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sneldivPtPfPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sneldivPtPfPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_2(float *d_data_in, float *d_data_out, int data_size)
{
__shared__ float s_data[BLKSIZE];
int tid = threadIdx.x;
int index = tid + blockIdx.x*blockDim.x;
s_data[tid] = 0.0;
if (index < data_size){
s_data[tid] = d_data_in[index];
}
__syncthreads();
for (int s = 2; s <= blockDim.x; s = s * 2){
index = tid * s;
if (index < blockDim.x){
s_data[index] += s_data[index + s / 2];
}
__syncthreads();
}
if (tid == 0){
d_data_out[blockIdx.x] = s_data[tid];
}
} | code for sm_80
Function : _Z8kernel_2PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x110 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e640000002500 */
/*0060*/ ISETP.LE.U32.AND P2, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fe40003f43070 */
/*0070*/ STS [R5.X4], RZ ; /* 0x000000ff05007388 */
/* 0x0011e20000004800 */
/*0080*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0090*/ IMAD R2, R4, c[0x0][0x0], R5 ; /* 0x0000000004027a24 */
/* 0x002fca00078e0205 */
/*00a0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f26270 */
/*00b0*/ @P1 BRA 0x100 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @!P2 BRA 0x200 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R6, R5, R0, RZ ; /* 0x0000000005067224 */
/* 0x000fca00078e02ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f26070 */
/*0160*/ @!P1 LEA.HI R2, R0.reuse, R0, RZ, 0x1 ; /* 0x0000000000029211 */
/* 0x040fe200078f08ff */
/*0170*/ @!P1 LDS R3, [R6.X4] ; /* 0x0000000006039984 */
/* 0x000fe20000004800 */
/*0180*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fe400000006ff */
/*0190*/ @!P1 LEA.HI R2, R2, R6, RZ, 0x1f ; /* 0x0000000602029211 */
/* 0x000fcc00078ff8ff */
/*01a0*/ @!P1 LDS R2, [R2.X4] ; /* 0x0000000002029984 */
/* 0x000e240000004800 */
/*01b0*/ @!P1 FADD R3, R3, R2 ; /* 0x0000000203039221 */
/* 0x001fca0000000000 */
/*01c0*/ @!P1 STS [R6.X4], R3 ; /* 0x0000000306009388 */
/* 0x0001e80000004800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.GT.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f24070 */
/*01f0*/ @!P1 BRA 0x140 ; /* 0xffffff4000009947 */
/* 0x001fea000383ffff */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0003 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_2(float *d_data_in, float *d_data_out, int data_size)
{
__shared__ float s_data[BLKSIZE];
int tid = threadIdx.x;
int index = tid + blockIdx.x*blockDim.x;
s_data[tid] = 0.0;
if (index < data_size){
s_data[tid] = d_data_in[index];
}
__syncthreads();
for (int s = 2; s <= blockDim.x; s = s * 2){
index = tid * s;
if (index < blockDim.x){
s_data[index] += s_data[index + s / 2];
}
__syncthreads();
}
if (tid == 0){
d_data_out[blockIdx.x] = s_data[tid];
}
} | .file "tmpxft_000a4893_00000000-6_kernel_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8kernel_2PfS_iPfS_i
.type _Z30__device_stub__Z8kernel_2PfS_iPfS_i, @function
_Z30__device_stub__Z8kernel_2PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8kernel_2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z8kernel_2PfS_iPfS_i, .-_Z30__device_stub__Z8kernel_2PfS_iPfS_i
.globl _Z8kernel_2PfS_i
.type _Z8kernel_2PfS_i, @function
_Z8kernel_2PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8kernel_2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8kernel_2PfS_i, .-_Z8kernel_2PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8kernel_2PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kernel_2PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_2(float *d_data_in, float *d_data_out, int data_size)
{
__shared__ float s_data[BLKSIZE];
int tid = threadIdx.x;
int index = tid + blockIdx.x*blockDim.x;
s_data[tid] = 0.0;
if (index < data_size){
s_data[tid] = d_data_in[index];
}
__syncthreads();
for (int s = 2; s <= blockDim.x; s = s * 2){
index = tid * s;
if (index < blockDim.x){
s_data[index] += s_data[index + s / 2];
}
__syncthreads();
}
if (tid == 0){
d_data_out[blockIdx.x] = s_data[tid];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_2(float *d_data_in, float *d_data_out, int data_size)
{
__shared__ float s_data[BLKSIZE];
int tid = threadIdx.x;
int index = tid + blockIdx.x*blockDim.x;
s_data[tid] = 0.0;
if (index < data_size){
s_data[tid] = d_data_in[index];
}
__syncthreads();
for (int s = 2; s <= blockDim.x; s = s * 2){
index = tid * s;
if (index < blockDim.x){
s_data[index] += s_data[index + s / 2];
}
__syncthreads();
}
if (tid == 0){
d_data_out[blockIdx.x] = s_data[tid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_2(float *d_data_in, float *d_data_out, int data_size)
{
__shared__ float s_data[BLKSIZE];
int tid = threadIdx.x;
int index = tid + blockIdx.x*blockDim.x;
s_data[tid] = 0.0;
if (index < data_size){
s_data[tid] = d_data_in[index];
}
__syncthreads();
for (int s = 2; s <= blockDim.x; s = s * 2){
index = tid * s;
if (index < blockDim.x){
s_data[index] += s_data[index + s / 2];
}
__syncthreads();
}
if (tid == 0){
d_data_out[blockIdx.x] = s_data[tid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8kernel_2PfS_i
.globl _Z8kernel_2PfS_i
.p2align 8
.type _Z8kernel_2PfS_i,@function
_Z8kernel_2PfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v3, v2
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_u32 s3, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s4, 2
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s4, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_lshr_b32 s6, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_add_lshl_u32 v2, v1, s6, 2
v_lshlrev_b32_e32 v1, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v4
ds_store_b32 v1, v2
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v3
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8kernel_2PfS_i
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8kernel_2PfS_i, .Lfunc_end0-_Z8kernel_2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8kernel_2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8kernel_2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_2(float *d_data_in, float *d_data_out, int data_size)
{
__shared__ float s_data[BLKSIZE];
int tid = threadIdx.x;
int index = tid + blockIdx.x*blockDim.x;
s_data[tid] = 0.0;
if (index < data_size){
s_data[tid] = d_data_in[index];
}
__syncthreads();
for (int s = 2; s <= blockDim.x; s = s * 2){
index = tid * s;
if (index < blockDim.x){
s_data[index] += s_data[index + s / 2];
}
__syncthreads();
}
if (tid == 0){
d_data_out[blockIdx.x] = s_data[tid];
}
} | .text
.file "kernel_2.hip"
.globl _Z23__device_stub__kernel_2PfS_i # -- Begin function _Z23__device_stub__kernel_2PfS_i
.p2align 4, 0x90
.type _Z23__device_stub__kernel_2PfS_i,@function
_Z23__device_stub__kernel_2PfS_i: # @_Z23__device_stub__kernel_2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8kernel_2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__kernel_2PfS_i, .Lfunc_end0-_Z23__device_stub__kernel_2PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kernel_2PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kernel_2PfS_i,@object # @_Z8kernel_2PfS_i
.section .rodata,"a",@progbits
.globl _Z8kernel_2PfS_i
.p2align 3, 0x0
_Z8kernel_2PfS_i:
.quad _Z23__device_stub__kernel_2PfS_i
.size _Z8kernel_2PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kernel_2PfS_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kernel_2PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kernel_2PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8kernel_2PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x110 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e640000002500 */
/*0060*/ ISETP.LE.U32.AND P2, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fe40003f43070 */
/*0070*/ STS [R5.X4], RZ ; /* 0x000000ff05007388 */
/* 0x0011e20000004800 */
/*0080*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0090*/ IMAD R2, R4, c[0x0][0x0], R5 ; /* 0x0000000004027a24 */
/* 0x002fca00078e0205 */
/*00a0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f26270 */
/*00b0*/ @P1 BRA 0x100 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @!P2 BRA 0x200 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R6, R5, R0, RZ ; /* 0x0000000005067224 */
/* 0x000fca00078e02ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f26070 */
/*0160*/ @!P1 LEA.HI R2, R0.reuse, R0, RZ, 0x1 ; /* 0x0000000000029211 */
/* 0x040fe200078f08ff */
/*0170*/ @!P1 LDS R3, [R6.X4] ; /* 0x0000000006039984 */
/* 0x000fe20000004800 */
/*0180*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fe400000006ff */
/*0190*/ @!P1 LEA.HI R2, R2, R6, RZ, 0x1f ; /* 0x0000000602029211 */
/* 0x000fcc00078ff8ff */
/*01a0*/ @!P1 LDS R2, [R2.X4] ; /* 0x0000000002029984 */
/* 0x000e240000004800 */
/*01b0*/ @!P1 FADD R3, R3, R2 ; /* 0x0000000203039221 */
/* 0x001fca0000000000 */
/*01c0*/ @!P1 STS [R6.X4], R3 ; /* 0x0000000306009388 */
/* 0x0001e80000004800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.GT.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f24070 */
/*01f0*/ @!P1 BRA 0x140 ; /* 0xffffff4000009947 */
/* 0x001fea000383ffff */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0003 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8kernel_2PfS_i
.globl _Z8kernel_2PfS_i
.p2align 8
.type _Z8kernel_2PfS_i,@function
_Z8kernel_2PfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v3, v2
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_u32 s3, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s4, 2
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s4, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_lshr_b32 s6, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_add_lshl_u32 v2, v1, s6, 2
v_lshlrev_b32_e32 v1, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v4
ds_store_b32 v1, v2
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v3
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8kernel_2PfS_i
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8kernel_2PfS_i, .Lfunc_end0-_Z8kernel_2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8kernel_2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8kernel_2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a4893_00000000-6_kernel_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8kernel_2PfS_iPfS_i
.type _Z30__device_stub__Z8kernel_2PfS_iPfS_i, @function
_Z30__device_stub__Z8kernel_2PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8kernel_2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z8kernel_2PfS_iPfS_i, .-_Z30__device_stub__Z8kernel_2PfS_iPfS_i
.globl _Z8kernel_2PfS_i
.type _Z8kernel_2PfS_i, @function
_Z8kernel_2PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8kernel_2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8kernel_2PfS_i, .-_Z8kernel_2PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8kernel_2PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kernel_2PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_2.hip"
.globl _Z23__device_stub__kernel_2PfS_i # -- Begin function _Z23__device_stub__kernel_2PfS_i
.p2align 4, 0x90
.type _Z23__device_stub__kernel_2PfS_i,@function
_Z23__device_stub__kernel_2PfS_i: # @_Z23__device_stub__kernel_2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8kernel_2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__kernel_2PfS_i, .Lfunc_end0-_Z23__device_stub__kernel_2PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kernel_2PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kernel_2PfS_i,@object # @_Z8kernel_2PfS_i
.section .rodata,"a",@progbits
.globl _Z8kernel_2PfS_i
.p2align 3, 0x0
_Z8kernel_2PfS_i:
.quad _Z23__device_stub__kernel_2PfS_i
.size _Z8kernel_2PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kernel_2PfS_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kernel_2PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kernel_2PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <vector>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <cmath>
#include <cstdio>
#include <iostream>
using namespace std;
//using namespace std::chrono;
int test_reduce(int* v);
using namespace std;
__global__ void reduce0(int *g_idata, int *g_odata) {
extern __shared__ int sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
int test_reduce(int* in, int N) {
int* d_in;
int* d_out;
int num_threads = 32;
int num_blocks = N / num_threads;
int *out = new int[num_blocks];
cudaMalloc(&d_in, N * sizeof(int));
cudaMalloc(&d_out, num_blocks * sizeof(int));
cudaMemcpy(d_in, in, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, num_blocks * sizeof(int), cudaMemcpyHostToDevice);
reduce0<<<num_blocks, num_threads, num_threads * sizeof(int)>>>(d_in, d_out);
int res = 0;
cudaMemcpy(out, d_out, sizeof(int) * num_blocks, cudaMemcpyDeviceToHost);
for(int i = 0; i < num_blocks; i++)
{
//std::cout << out[i] << std::endl;
res += out[i];
}
cudaFree(d_in);
cudaFree(d_out);
//delete in;
delete out;
return res;
}
int main() {
int N = 1024;
int* in = new int[N];
for (int i = 0; i < N; i++) {
in[i] = i + 1;
}
int maximo = 0;
for (int i = 0; i < N; i++) {
maximo += in[i];// std::max(maximo, vec[i]);
}
cout << "Max CPU " << maximo << endl;
int max_cuda = test_reduce(in, N);
cout << "Max GPU " << max_cuda << endl;
delete in;
return 0;
} | code for sm_80
Function : _Z7reduce0PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*00b0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P1 BRA 0x2c0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*00e0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.L.U32 R10, R5, 0x1, RZ ; /* 0x00000001050a7819 */
/* 0x000fc800000006ff */
/*0110*/ I2F.U32.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e220000209000 */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R10 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0a */
/*0130*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fcc0003f45070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0180*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fd200078e02ff */
/*0190*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a031210 */
/* 0x000fc80007ffe1ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103031824 */
/* 0x000fe200078e0a0a */
/*0210*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @!P1 LEA R2, R5, R0, 0x2 ; /* 0x0000000005029211 */
/* 0x000fe200078e10ff */
/*0240*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe20000004800 */
/*0250*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fc80000000f00 */
/*0260*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0270*/ @!P1 IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103039824 */
/* 0x001fca00078e0202 */
/*0280*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*02b0*/ @!P1 BRA 0x100 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <vector>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <cmath>
#include <cstdio>
#include <iostream>
using namespace std;
//using namespace std::chrono;
int test_reduce(int* v);
using namespace std;
__global__ void reduce0(int *g_idata, int *g_odata) {
extern __shared__ int sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
int test_reduce(int* in, int N) {
int* d_in;
int* d_out;
int num_threads = 32;
int num_blocks = N / num_threads;
int *out = new int[num_blocks];
cudaMalloc(&d_in, N * sizeof(int));
cudaMalloc(&d_out, num_blocks * sizeof(int));
cudaMemcpy(d_in, in, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, num_blocks * sizeof(int), cudaMemcpyHostToDevice);
reduce0<<<num_blocks, num_threads, num_threads * sizeof(int)>>>(d_in, d_out);
int res = 0;
cudaMemcpy(out, d_out, sizeof(int) * num_blocks, cudaMemcpyDeviceToHost);
for(int i = 0; i < num_blocks; i++)
{
//std::cout << out[i] << std::endl;
res += out[i];
}
cudaFree(d_in);
cudaFree(d_out);
//delete in;
delete out;
return res;
}
int main() {
int N = 1024;
int* in = new int[N];
for (int i = 0; i < N; i++) {
in[i] = i + 1;
}
int maximo = 0;
for (int i = 0; i < N; i++) {
maximo += in[i];// std::max(maximo, vec[i]);
}
cout << "Max CPU " << maximo << endl;
int max_cuda = test_reduce(in, N);
cout << "Max GPU " << max_cuda << endl;
delete in;
return 0;
} | .file "tmpxft_0019d61d_00000000-6_reduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7reduce0PiS_PiS_
.type _Z28__device_stub__Z7reduce0PiS_PiS_, @function
_Z28__device_stub__Z7reduce0PiS_PiS_:
.LFB4058:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce0PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4058:
.size _Z28__device_stub__Z7reduce0PiS_PiS_, .-_Z28__device_stub__Z7reduce0PiS_PiS_
.globl _Z7reduce0PiS_
.type _Z7reduce0PiS_, @function
_Z7reduce0PiS_:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce0PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _Z7reduce0PiS_, .-_Z7reduce0PiS_
.globl _Z11test_reducePii
.type _Z11test_reducePii, @function
_Z11test_reducePii:
.LFB4032:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal 31(%rsi), %ebp
testl %esi, %esi
cmovns %esi, %ebp
sarl $5, %ebp
movslq %ebp, %r13
movabsq $2305843009213693950, %rax
cmpq %r13, %rax
jb .L12
movq %rdi, %r15
movl %esi, %ebx
salq $2, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r12
movslq %ebx, %r14
salq $2, %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl %ebp, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $128, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
cmpl $31, %ebx
jle .L19
movl $0, %eax
movl $0, %ebx
.L17:
addl (%r12,%rax,4), %ebx
addq $1, %rax
cmpl %eax, %ebp
jg .L17
.L16:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $4, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl %ebx, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L23:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7reduce0PiS_PiS_
jmp .L13
.L19:
movl $0, %ebx
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.size _Z11test_reducePii, .-_Z11test_reducePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Max CPU "
.LC1:
.string "Max GPU "
.text
.globl main
.type main, @function
main:
.LFB4033:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $4096, %edi
call _Znam@PLT
movq %rax, %rbp
movl $1, %eax
.L26:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $1025, %rax
jne .L26
movq %rbp, %rax
leaq 4096(%rbp), %rcx
movl $0, %edx
.L27:
addl (%rax), %edx
movl %edx, %ebx
addq $4, %rax
cmpq %rcx, %rax
jne .L27
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, %esi
movq %rbp, %rdi
call _Z11test_reducePii
movl %eax, %ebx
leaq .LC1(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4033:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7reduce0PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce0PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <vector>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <cmath>
#include <cstdio>
#include <iostream>
using namespace std;
//using namespace std::chrono;
int test_reduce(int* v);
using namespace std;
__global__ void reduce0(int *g_idata, int *g_odata) {
extern __shared__ int sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
int test_reduce(int* in, int N) {
int* d_in;
int* d_out;
int num_threads = 32;
int num_blocks = N / num_threads;
int *out = new int[num_blocks];
cudaMalloc(&d_in, N * sizeof(int));
cudaMalloc(&d_out, num_blocks * sizeof(int));
cudaMemcpy(d_in, in, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, num_blocks * sizeof(int), cudaMemcpyHostToDevice);
reduce0<<<num_blocks, num_threads, num_threads * sizeof(int)>>>(d_in, d_out);
int res = 0;
cudaMemcpy(out, d_out, sizeof(int) * num_blocks, cudaMemcpyDeviceToHost);
for(int i = 0; i < num_blocks; i++)
{
//std::cout << out[i] << std::endl;
res += out[i];
}
cudaFree(d_in);
cudaFree(d_out);
//delete in;
delete out;
return res;
}
int main() {
int N = 1024;
int* in = new int[N];
for (int i = 0; i < N; i++) {
in[i] = i + 1;
}
int maximo = 0;
for (int i = 0; i < N; i++) {
maximo += in[i];// std::max(maximo, vec[i]);
}
cout << "Max CPU " << maximo << endl;
int max_cuda = test_reduce(in, N);
cout << "Max GPU " << max_cuda << endl;
delete in;
return 0;
} | #include <vector>
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <cmath>
#include <cstdio>
#include <iostream>
using namespace std;
//using namespace std::chrono;
int test_reduce(int* v);
using namespace std;
__global__ void reduce0(int *g_idata, int *g_odata) {
extern __shared__ int sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
int test_reduce(int* in, int N) {
int* d_in;
int* d_out;
int num_threads = 32;
int num_blocks = N / num_threads;
int *out = new int[num_blocks];
hipMalloc(&d_in, N * sizeof(int));
hipMalloc(&d_out, num_blocks * sizeof(int));
hipMemcpy(d_in, in, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_out, out, num_blocks * sizeof(int), hipMemcpyHostToDevice);
reduce0<<<num_blocks, num_threads, num_threads * sizeof(int)>>>(d_in, d_out);
int res = 0;
hipMemcpy(out, d_out, sizeof(int) * num_blocks, hipMemcpyDeviceToHost);
for(int i = 0; i < num_blocks; i++)
{
//std::cout << out[i] << std::endl;
res += out[i];
}
hipFree(d_in);
hipFree(d_out);
//delete in;
delete out;
return res;
}
int main() {
int N = 1024;
int* in = new int[N];
for (int i = 0; i < N; i++) {
in[i] = i + 1;
}
int maximo = 0;
for (int i = 0; i < N; i++) {
maximo += in[i];// std::max(maximo, vec[i]);
}
cout << "Max CPU " << maximo << endl;
int max_cuda = test_reduce(in, N);
cout << "Max GPU " << max_cuda << endl;
delete in;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <vector>
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <cmath>
#include <cstdio>
#include <iostream>
using namespace std;
//using namespace std::chrono;
int test_reduce(int* v);
using namespace std;
__global__ void reduce0(int *g_idata, int *g_odata) {
extern __shared__ int sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
int test_reduce(int* in, int N) {
int* d_in;
int* d_out;
int num_threads = 32;
int num_blocks = N / num_threads;
int *out = new int[num_blocks];
hipMalloc(&d_in, N * sizeof(int));
hipMalloc(&d_out, num_blocks * sizeof(int));
hipMemcpy(d_in, in, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_out, out, num_blocks * sizeof(int), hipMemcpyHostToDevice);
reduce0<<<num_blocks, num_threads, num_threads * sizeof(int)>>>(d_in, d_out);
int res = 0;
hipMemcpy(out, d_out, sizeof(int) * num_blocks, hipMemcpyDeviceToHost);
for(int i = 0; i < num_blocks; i++)
{
//std::cout << out[i] << std::endl;
res += out[i];
}
hipFree(d_in);
hipFree(d_out);
//delete in;
delete out;
return res;
}
int main() {
int N = 1024;
int* in = new int[N];
for (int i = 0; i < N; i++) {
in[i] = i + 1;
}
int maximo = 0;
for (int i = 0; i < N; i++) {
maximo += in[i];// std::max(maximo, vec[i]);
}
cout << "Max CPU " << maximo << endl;
int max_cuda = test_reduce(in, N);
cout << "Max GPU " << max_cuda << endl;
delete in;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce0PiS_
.globl _Z7reduce0PiS_
.p2align 8
.type _Z7reduce0PiS_,@function
_Z7reduce0PiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_mov_b32 s5, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce0PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce0PiS_, .Lfunc_end0-_Z7reduce0PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce0PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce0PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <vector>
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <cmath>
#include <cstdio>
#include <iostream>
using namespace std;
//using namespace std::chrono;
int test_reduce(int* v);
using namespace std;
__global__ void reduce0(int *g_idata, int *g_odata) {
extern __shared__ int sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
int test_reduce(int* in, int N) {
int* d_in;
int* d_out;
int num_threads = 32;
int num_blocks = N / num_threads;
int *out = new int[num_blocks];
hipMalloc(&d_in, N * sizeof(int));
hipMalloc(&d_out, num_blocks * sizeof(int));
hipMemcpy(d_in, in, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_out, out, num_blocks * sizeof(int), hipMemcpyHostToDevice);
reduce0<<<num_blocks, num_threads, num_threads * sizeof(int)>>>(d_in, d_out);
int res = 0;
hipMemcpy(out, d_out, sizeof(int) * num_blocks, hipMemcpyDeviceToHost);
for(int i = 0; i < num_blocks; i++)
{
//std::cout << out[i] << std::endl;
res += out[i];
}
hipFree(d_in);
hipFree(d_out);
//delete in;
delete out;
return res;
}
int main() {
int N = 1024;
int* in = new int[N];
for (int i = 0; i < N; i++) {
in[i] = i + 1;
}
int maximo = 0;
for (int i = 0; i < N; i++) {
maximo += in[i];// std::max(maximo, vec[i]);
}
cout << "Max CPU " << maximo << endl;
int max_cuda = test_reduce(in, N);
cout << "Max GPU " << max_cuda << endl;
delete in;
return 0;
} | .text
.file "reduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__reduce0PiS_ # -- Begin function _Z22__device_stub__reduce0PiS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce0PiS_,@function
_Z22__device_stub__reduce0PiS_: # @_Z22__device_stub__reduce0PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce0PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce0PiS_, .Lfunc_end0-_Z22__device_stub__reduce0PiS_
.cfi_endproc
# -- End function
.globl _Z11test_reducePii # -- Begin function _Z11test_reducePii
.p2align 4, 0x90
.type _Z11test_reducePii,@function
_Z11test_reducePii: # @_Z11test_reducePii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
leal 31(%r14), %ebp
testl %esi, %esi
cmovnsl %esi, %ebp
movq %rdi, %r12
sarl $5, %ebp
movslq %ebp, %r15
shlq $2, %r15
cmpl $-31, %esi
movq $-1, %rdi
cmovgeq %r15, %rdi
callq _Znam
movq %rax, %rbx
movslq %r14d, %r13
shlq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rbp), %rdi
orq $32, %rdx
xorl %r12d, %r12d
movl $128, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce0PiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $32, %r14d
jl .LBB1_5
# %bb.3: # %.lr.ph.preheader
movl %ebp, %eax
xorl %ecx, %ecx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %r12d
incq %rcx
cmpq %rcx, %rax
jne .LBB1_4
.LBB1_5: # %._crit_edge
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdlPv
movl %r12d, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11test_reducePii, .Lfunc_end1-_Z11test_reducePii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $1024, %rcx # imm = 0x400
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rax,4), %ebp
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB2_8
.LBB2_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
movl $1024, %esi # imm = 0x400
callq _Z11test_reducePii
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%r14)
je .LBB2_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB2_12
.LBB2_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce0PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce0PiS_,@object # @_Z7reduce0PiS_
.section .rodata,"a",@progbits
.globl _Z7reduce0PiS_
.p2align 3, 0x0
_Z7reduce0PiS_:
.quad _Z22__device_stub__reduce0PiS_
.size _Z7reduce0PiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max CPU "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max GPU "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reduce0PiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce0PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce0PiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7reduce0PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*00b0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P1 BRA 0x2c0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*00e0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.L.U32 R10, R5, 0x1, RZ ; /* 0x00000001050a7819 */
/* 0x000fc800000006ff */
/*0110*/ I2F.U32.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e220000209000 */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R10 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0a */
/*0130*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fcc0003f45070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0180*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fd200078e02ff */
/*0190*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a031210 */
/* 0x000fc80007ffe1ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103031824 */
/* 0x000fe200078e0a0a */
/*0210*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @!P1 LEA R2, R5, R0, 0x2 ; /* 0x0000000005029211 */
/* 0x000fe200078e10ff */
/*0240*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe20000004800 */
/*0250*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fc80000000f00 */
/*0260*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0270*/ @!P1 IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103039824 */
/* 0x001fca00078e0202 */
/*0280*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*02b0*/ @!P1 BRA 0x100 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce0PiS_
.globl _Z7reduce0PiS_
.p2align 8
.type _Z7reduce0PiS_,@function
_Z7reduce0PiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_mov_b32 s5, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce0PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce0PiS_, .Lfunc_end0-_Z7reduce0PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce0PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce0PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d61d_00000000-6_reduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7reduce0PiS_PiS_
.type _Z28__device_stub__Z7reduce0PiS_PiS_, @function
_Z28__device_stub__Z7reduce0PiS_PiS_:
.LFB4058:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce0PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4058:
.size _Z28__device_stub__Z7reduce0PiS_PiS_, .-_Z28__device_stub__Z7reduce0PiS_PiS_
.globl _Z7reduce0PiS_
.type _Z7reduce0PiS_, @function
_Z7reduce0PiS_:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce0PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _Z7reduce0PiS_, .-_Z7reduce0PiS_
.globl _Z11test_reducePii
.type _Z11test_reducePii, @function
_Z11test_reducePii:
.LFB4032:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal 31(%rsi), %ebp
testl %esi, %esi
cmovns %esi, %ebp
sarl $5, %ebp
movslq %ebp, %r13
movabsq $2305843009213693950, %rax
cmpq %r13, %rax
jb .L12
movq %rdi, %r15
movl %esi, %ebx
salq $2, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r12
movslq %ebx, %r14
salq $2, %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl %ebp, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $128, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
cmpl $31, %ebx
jle .L19
movl $0, %eax
movl $0, %ebx
.L17:
addl (%r12,%rax,4), %ebx
addq $1, %rax
cmpl %eax, %ebp
jg .L17
.L16:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $4, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl %ebx, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L23:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7reduce0PiS_PiS_
jmp .L13
.L19:
movl $0, %ebx
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.size _Z11test_reducePii, .-_Z11test_reducePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Max CPU "
.LC1:
.string "Max GPU "
.text
.globl main
.type main, @function
main:
.LFB4033:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $4096, %edi
call _Znam@PLT
movq %rax, %rbp
movl $1, %eax
.L26:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $1025, %rax
jne .L26
movq %rbp, %rax
leaq 4096(%rbp), %rcx
movl $0, %edx
.L27:
addl (%rax), %edx
movl %edx, %ebx
addq $4, %rax
cmpq %rcx, %rax
jne .L27
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, %esi
movq %rbp, %rdi
call _Z11test_reducePii
movl %eax, %ebx
leaq .LC1(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4033:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7reduce0PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce0PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__reduce0PiS_ # -- Begin function _Z22__device_stub__reduce0PiS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce0PiS_,@function
_Z22__device_stub__reduce0PiS_: # @_Z22__device_stub__reduce0PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce0PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce0PiS_, .Lfunc_end0-_Z22__device_stub__reduce0PiS_
.cfi_endproc
# -- End function
.globl _Z11test_reducePii # -- Begin function _Z11test_reducePii
.p2align 4, 0x90
.type _Z11test_reducePii,@function
_Z11test_reducePii: # @_Z11test_reducePii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
leal 31(%r14), %ebp
testl %esi, %esi
cmovnsl %esi, %ebp
movq %rdi, %r12
sarl $5, %ebp
movslq %ebp, %r15
shlq $2, %r15
cmpl $-31, %esi
movq $-1, %rdi
cmovgeq %r15, %rdi
callq _Znam
movq %rax, %rbx
movslq %r14d, %r13
shlq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rbp), %rdi
orq $32, %rdx
xorl %r12d, %r12d
movl $128, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce0PiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $32, %r14d
jl .LBB1_5
# %bb.3: # %.lr.ph.preheader
movl %ebp, %eax
xorl %ecx, %ecx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %r12d
incq %rcx
cmpq %rcx, %rax
jne .LBB1_4
.LBB1_5: # %._crit_edge
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdlPv
movl %r12d, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11test_reducePii, .Lfunc_end1-_Z11test_reducePii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $1024, %rcx # imm = 0x400
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rax,4), %ebp
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB2_8
.LBB2_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
movl $1024, %esi # imm = 0x400
callq _Z11test_reducePii
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%r14)
je .LBB2_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB2_12
.LBB2_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce0PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce0PiS_,@object # @_Z7reduce0PiS_
.section .rodata,"a",@progbits
.globl _Z7reduce0PiS_
.p2align 3, 0x0
_Z7reduce0PiS_:
.quad _Z22__device_stub__reduce0PiS_
.size _Z7reduce0PiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max CPU "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max GPU "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reduce0PiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce0PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce0PiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////BEG
__global__ void reduce0(int*g_idata, int*g_odata){
//shared memory for one block of threads
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
if(tid % (2*s) == 0){
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce1(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
int index = 2 * s * tid;
if (index < blockDim.x) {
sdata[index] += sdata[index + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce2(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////////END
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
// Helper function for using CUDA to reduce vectors in parallel.
cudaError_t reduceWithCuda(int *c, const int *a, unsigned int size){
int *dev_a = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int)); // (size OR 1) * sizeof(int)
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
//blocks per grid, threads per block. Num of threads = x*y // <<<x, y >>>
// Launch a kernel on the GPU with one thread for each element.
reduce0<<<1, size>>>(dev_a, dev_c);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "reduce0 launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
return cudaStatus;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
cudaError_t cudaStatus = reduceWithCuda(c, a, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
int scan;
scanf("%d", &scan);
return 0;
} | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7reduce2PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0100*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7reduce1PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R4, c[0x0][0x0], R5 ; /* 0x0000000004027a24 */
/* 0x001fca00078e0205 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05270 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*00b0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P1 BRA 0x1b0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R0, 0x1 ; /* 0x0000000100007802 */
/* 0x001fca0000000f00 */
/*00f0*/ IMAD.SHL.U32 R6, R0, 0x2, RZ ; /* 0x0000000200067824 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fca00078e02ff */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IADD3 R2, R7, R0, RZ ; /* 0x0000000007029210 */
/* 0x000fe40007ffe0ff */
/*0130*/ @!P1 LDS R0, [R7.X4] ; /* 0x0000000007009984 */
/* 0x000fe80000004800 */
/*0140*/ @!P1 LDS R3, [R2.X4] ; /* 0x0000000002039984 */
/* 0x000e240000004800 */
/*0150*/ @!P1 IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100039824 */
/* 0x001fe200078e0203 */
/*0160*/ MOV R0, R6 ; /* 0x0000000600007202 */
/* 0x000fc80000000f00 */
/*0170*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f26070 */
/*01a0*/ @!P1 BRA 0xf0 ; /* 0xffffff4000009947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7reduce0PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*00b0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P1 BRA 0x2c0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*00e0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.L.U32 R10, R5, 0x1, RZ ; /* 0x00000001050a7819 */
/* 0x000fc800000006ff */
/*0110*/ I2F.U32.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e220000209000 */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R10 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0a */
/*0130*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fcc0003f45070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0180*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fd200078e02ff */
/*0190*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a031210 */
/* 0x000fc80007ffe1ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103031824 */
/* 0x000fe200078e0a0a */
/*0210*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @!P1 LEA R2, R5, R0, 0x2 ; /* 0x0000000005029211 */
/* 0x000fe200078e10ff */
/*0240*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe20000004800 */
/*0250*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fc80000000f00 */
/*0260*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0270*/ @!P1 IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103039824 */
/* 0x001fca00078e0202 */
/*0280*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*02b0*/ @!P1 BRA 0x100 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////BEG
__global__ void reduce0(int*g_idata, int*g_odata){
//shared memory for one block of threads
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
if(tid % (2*s) == 0){
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce1(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
int index = 2 * s * tid;
if (index < blockDim.x) {
sdata[index] += sdata[index + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce2(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////////END
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
// Helper function for using CUDA to reduce vectors in parallel.
cudaError_t reduceWithCuda(int *c, const int *a, unsigned int size){
int *dev_a = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int)); // (size OR 1) * sizeof(int)
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
//blocks per grid, threads per block. Num of threads = x*y // <<<x, y >>>
// Launch a kernel on the GPU with one thread for each element.
reduce0<<<1, size>>>(dev_a, dev_c);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "reduce0 launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
return cudaStatus;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
cudaError_t cudaStatus = reduceWithCuda(c, a, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
int scan;
scanf("%d", &scan);
return 0;
} | .file "tmpxft_00122b27_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7reduce0PiS_PiS_
.type _Z28__device_stub__Z7reduce0PiS_PiS_, @function
_Z28__device_stub__Z7reduce0PiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce0PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z7reduce0PiS_PiS_, .-_Z28__device_stub__Z7reduce0PiS_PiS_
.globl _Z7reduce0PiS_
.type _Z7reduce0PiS_, @function
_Z7reduce0PiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce0PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7reduce0PiS_, .-_Z7reduce0PiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "reduce0 launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z14reduceWithCudaPiPKij
.type _Z14reduceWithCudaPiPKij, @function
_Z14reduceWithCudaPiPKij:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L22
movl %r13d, %r14d
salq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L23
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L24
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L25
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L17:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L22:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl %ebx, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L24:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L25:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7reduce0PiS_PiS_
jmp .L17
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L28:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z14reduceWithCudaPiPKij, .-_Z14reduceWithCudaPiPKij
.section .rodata.str1.1
.LC5:
.string "addWithCuda failed!"
.section .rodata.str1.8
.align 8
.LC6:
.string "{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n"
.section .rodata.str1.1
.LC7:
.string "cudaDeviceReset failed!"
.LC8:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $4, 28(%rsp)
movl $5, 32(%rsp)
pxor %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movl $0, 64(%rsp)
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
movl $5, %edx
call _Z14reduceWithCudaPiPKij
testl %eax, %eax
jne .L36
subq $8, %rsp
.cfi_def_cfa_offset 104
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl 76(%rsp), %r9d
movl 72(%rsp), %r8d
movl 68(%rsp), %ecx
movl 64(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L37
leaq 12(%rsp), %rsi
leaq .LC8(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, %eax
.L30:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L30
.L37:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L30
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.globl _Z28__device_stub__Z7reduce1PiS_PiS_
.type _Z28__device_stub__Z7reduce1PiS_PiS_, @function
_Z28__device_stub__Z7reduce1PiS_PiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce1PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z7reduce1PiS_PiS_, .-_Z28__device_stub__Z7reduce1PiS_PiS_
.globl _Z7reduce1PiS_
.type _Z7reduce1PiS_, @function
_Z7reduce1PiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce1PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7reduce1PiS_, .-_Z7reduce1PiS_
.globl _Z28__device_stub__Z7reduce2PiS_PiS_
.type _Z28__device_stub__Z7reduce2PiS_PiS_, @function
_Z28__device_stub__Z7reduce2PiS_PiS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce2PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z28__device_stub__Z7reduce2PiS_PiS_, .-_Z28__device_stub__Z7reduce2PiS_PiS_
.globl _Z7reduce2PiS_
.type _Z7reduce2PiS_, @function
_Z7reduce2PiS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce2PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z7reduce2PiS_, .-_Z7reduce2PiS_
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.1
.LC9:
.string "addKernel launch failed: %s\n"
.text
.globl _Z11addWithCudaPiPKiS1_j
.type _Z11addWithCudaPiPKiS1_j, @function
_Z11addWithCudaPiPKiS1_j:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L76
movl %ebp, %r15d
salq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L77
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L78
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L79
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L80
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L81
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L71:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L83
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L84
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L65
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L76:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L65:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L85
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L78:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L79:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L80:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L81:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L82:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
jmp .L71
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L84:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L85:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11addWithCudaPiPKiS1_j, .-_Z11addWithCudaPiPKiS1_j
.section .rodata.str1.1
.LC10:
.string "_Z9addKernelPiPKiS1_"
.LC11:
.string "_Z7reduce2PiS_"
.LC12:
.string "_Z7reduce1PiS_"
.LC13:
.string "_Z7reduce0PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce2PiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce1PiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce0PiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////BEG
__global__ void reduce0(int*g_idata, int*g_odata){
//shared memory for one block of threads
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
if(tid % (2*s) == 0){
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce1(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
int index = 2 * s * tid;
if (index < blockDim.x) {
sdata[index] += sdata[index + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce2(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////////END
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
// Helper function for using CUDA to reduce vectors in parallel.
cudaError_t reduceWithCuda(int *c, const int *a, unsigned int size){
int *dev_a = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int)); // (size OR 1) * sizeof(int)
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
//blocks per grid, threads per block. Num of threads = x*y // <<<x, y >>>
// Launch a kernel on the GPU with one thread for each element.
reduce0<<<1, size>>>(dev_a, dev_c);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "reduce0 launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
return cudaStatus;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
cudaError_t cudaStatus = reduceWithCuda(c, a, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
int scan;
scanf("%d", &scan);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////BEG
__global__ void reduce0(int*g_idata, int*g_odata){
//shared memory for one block of threads
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
if(tid % (2*s) == 0){
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce1(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
int index = 2 * s * tid;
if (index < blockDim.x) {
sdata[index] += sdata[index + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce2(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////////END
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
// Helper function for using CUDA to reduce vectors in parallel.
hipError_t reduceWithCuda(int *c, const int *a, unsigned int size){
int *dev_a = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int)); // (size OR 1) * sizeof(int)
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
//blocks per grid, threads per block. Num of threads = x*y // <<<x, y >>>
// Launch a kernel on the GPU with one thread for each element.
reduce0<<<1, size>>>(dev_a, dev_c);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "reduce0 launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
return cudaStatus;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
hipError_t cudaStatus = reduceWithCuda(c, a, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
int scan;
scanf("%d", &scan);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////BEG
__global__ void reduce0(int*g_idata, int*g_odata){
//shared memory for one block of threads
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
if(tid % (2*s) == 0){
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce1(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
int index = 2 * s * tid;
if (index < blockDim.x) {
sdata[index] += sdata[index + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce2(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////////END
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
// Helper function for using CUDA to reduce vectors in parallel.
hipError_t reduceWithCuda(int *c, const int *a, unsigned int size){
int *dev_a = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int)); // (size OR 1) * sizeof(int)
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
//blocks per grid, threads per block. Num of threads = x*y // <<<x, y >>>
// Launch a kernel on the GPU with one thread for each element.
reduce0<<<1, size>>>(dev_a, dev_c);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "reduce0 launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
return cudaStatus;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
hipError_t cudaStatus = reduceWithCuda(c, a, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
int scan;
scanf("%d", &scan);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce0PiS_
.globl _Z7reduce0PiS_
.p2align 8
.type _Z7reduce0PiS_,@function
_Z7reduce0PiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_mov_b32 s5, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce0PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce0PiS_, .Lfunc_end0-_Z7reduce0PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7reduce1PiS_
.globl _Z7reduce1PiS_
.p2align 8
.type _Z7reduce1PiS_,@function
_Z7reduce1PiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v2, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
s_mov_b32 s5, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
.LBB1_3:
s_lshl_b32 s4, s5, 1
s_mov_b32 s6, exec_lo
v_mul_lo_u32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
v_add_nc_u32_e32 v2, s5, v1
v_lshl_add_u32 v1, v1, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce1PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7reduce1PiS_, .Lfunc_end1-_Z7reduce1PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7reduce2PiS_
.globl _Z7reduce2PiS_
.p2align 8
.type _Z7reduce2PiS_,@function
_Z7reduce2PiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB2_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB2_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB2_1
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB2_1
.LBB2_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce2PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7reduce2PiS_, .Lfunc_end2-_Z7reduce2PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z9addKernelPiPKiS1_, .Lfunc_end3-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce0PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce0PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce1PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce1PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce2PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce2PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////BEG
__global__ void reduce0(int*g_idata, int*g_odata){
//shared memory for one block of threads
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
if(tid % (2*s) == 0){
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce1(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=1; s < blockDim.x; s *= 2) {
int index = 2 * s * tid;
if (index < blockDim.x) {
sdata[index] += sdata[index + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void reduce2(int*g_idata, int*g_odata){
extern __shared__ int sdata[];
// each thread loadsone element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if(tid == 0) g_odata[blockIdx.x] = sdata[0];
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////////END
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
// Helper function for using CUDA to reduce vectors in parallel.
hipError_t reduceWithCuda(int *c, const int *a, unsigned int size){
int *dev_a = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int)); // (size OR 1) * sizeof(int)
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
//blocks per grid, threads per block. Num of threads = x*y // <<<x, y >>>
// Launch a kernel on the GPU with one thread for each element.
reduce0<<<1, size>>>(dev_a, dev_c);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "reduce0 launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
return cudaStatus;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
hipError_t cudaStatus = reduceWithCuda(c, a, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
int scan;
scanf("%d", &scan);
return 0;
} | .text
.file "kernel.hip"
.globl _Z22__device_stub__reduce0PiS_ # -- Begin function _Z22__device_stub__reduce0PiS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce0PiS_,@function
_Z22__device_stub__reduce0PiS_: # @_Z22__device_stub__reduce0PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce0PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce0PiS_, .Lfunc_end0-_Z22__device_stub__reduce0PiS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__reduce1PiS_ # -- Begin function _Z22__device_stub__reduce1PiS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce1PiS_,@function
_Z22__device_stub__reduce1PiS_: # @_Z22__device_stub__reduce1PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce1PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__reduce1PiS_, .Lfunc_end1-_Z22__device_stub__reduce1PiS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__reduce2PiS_ # -- Begin function _Z22__device_stub__reduce2PiS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce2PiS_,@function
_Z22__device_stub__reduce2PiS_: # @_Z22__device_stub__reduce2PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce2PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z22__device_stub__reduce2PiS_, .Lfunc_end2-_Z22__device_stub__reduce2PiS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end3-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.globl _Z14reduceWithCudaPiPKij # -- Begin function _Z14reduceWithCudaPiPKij
.p2align 4, 0x90
.type _Z14reduceWithCudaPiPKij,@function
_Z14reduceWithCudaPiPKij: # @_Z14reduceWithCudaPiPKij
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r12
movq %rdi, %rbx
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB4_11
# %bb.1:
movl %ebp, %r15d
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.2:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.3:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_12
# %bb.4:
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r15
orq $1, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce0PiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_17
# %bb.7:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_18
# %bb.8:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB4_16
# %bb.9:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB4_15
.LBB4_10:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
jmp .LBB4_13
.LBB4_11:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $63, %esi
jmp .LBB4_14
.LBB4_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
.LBB4_13:
movl $17, %esi
.LBB4_14:
movl $1, %edx
.LBB4_15:
callq fwrite@PLT
.LBB4_16:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_17:
.cfi_def_cfa_offset 144
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB4_16
.LBB4_18:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB4_16
.Lfunc_end4:
.size _Z14reduceWithCudaPiPKij, .Lfunc_end4-_Z14reduceWithCudaPiPKij
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPiPKiS1_j # -- Begin function _Z11addWithCudaPiPKiS1_j
.p2align 4, 0x90
.type _Z11addWithCudaPiPKiS1_j,@function
_Z11addWithCudaPiPKiS1_j: # @_Z11addWithCudaPiPKiS1_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB5_18
# %bb.1:
movl %ebp, %r15d
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_13
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_13
# %bb.6:
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r15
orq $1, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB5_19
# %bb.9:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_20
# %bb.10:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB5_17
# %bb.11:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB5_16
.LBB5_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
jmp .LBB5_14
.LBB5_13:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
.LBB5_14:
movl $17, %esi
.LBB5_15:
movl $1, %edx
.LBB5_16:
callq fwrite@PLT
.LBB5_17:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_18:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $63, %esi
jmp .LBB5_15
.LBB5_19:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_17
.LBB5_20:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB5_17
.Lfunc_end5:
.size _Z11addWithCudaPiPKiS1_j, .Lfunc_end5-_Z11addWithCudaPiPKiS1_j
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI6_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movaps .LCPI6_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 32(%rsp)
movl $5, 48(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movl $5, %edx
callq _Z14reduceWithCudaPiPKij
testl %eax, %eax
jne .LBB6_1
# %bb.3:
movl (%rsp), %esi
movl 4(%rsp), %edx
movl 8(%rsp), %ecx
movl 12(%rsp), %r8d
movl 16(%rsp), %r9d
xorl %ebx, %ebx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
callq hipDeviceReset
testl %eax, %eax
jne .LBB6_4
# %bb.5:
leaq 28(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq __isoc23_scanf
.LBB6_6:
movl %ebx, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB6_1:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $19, %esi
jmp .LBB6_2
.LBB6_4:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $22, %esi
.LBB6_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %ebx
jmp .LBB6_6
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce0PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce1PiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce2PiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce0PiS_,@object # @_Z7reduce0PiS_
.section .rodata,"a",@progbits
.globl _Z7reduce0PiS_
.p2align 3, 0x0
_Z7reduce0PiS_:
.quad _Z22__device_stub__reduce0PiS_
.size _Z7reduce0PiS_, 8
.type _Z7reduce1PiS_,@object # @_Z7reduce1PiS_
.globl _Z7reduce1PiS_
.p2align 3, 0x0
_Z7reduce1PiS_:
.quad _Z22__device_stub__reduce1PiS_
.size _Z7reduce1PiS_, 8
.type _Z7reduce2PiS_,@object # @_Z7reduce2PiS_
.globl _Z7reduce2PiS_
.p2align 3, 0x0
_Z7reduce2PiS_:
.quad _Z22__device_stub__reduce2PiS_
.size _Z7reduce2PiS_, 8
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str, 64
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc failed!"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy failed!"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "reduce0 launch failed: %s\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.4, 72
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "addKernel launch failed: %s\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "addWithCuda failed!"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n"
.size .L.str.7, 51
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipDeviceReset failed!"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reduce0PiS_"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7reduce1PiS_"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7reduce2PiS_"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_4, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce0PiS_
.addrsig_sym _Z22__device_stub__reduce1PiS_
.addrsig_sym _Z22__device_stub__reduce2PiS_
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce0PiS_
.addrsig_sym _Z7reduce1PiS_
.addrsig_sym _Z7reduce2PiS_
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7reduce2PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0100*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7reduce1PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R4, c[0x0][0x0], R5 ; /* 0x0000000004027a24 */
/* 0x001fca00078e0205 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05270 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*00b0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P1 BRA 0x1b0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R0, 0x1 ; /* 0x0000000100007802 */
/* 0x001fca0000000f00 */
/*00f0*/ IMAD.SHL.U32 R6, R0, 0x2, RZ ; /* 0x0000000200067824 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fca00078e02ff */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IADD3 R2, R7, R0, RZ ; /* 0x0000000007029210 */
/* 0x000fe40007ffe0ff */
/*0130*/ @!P1 LDS R0, [R7.X4] ; /* 0x0000000007009984 */
/* 0x000fe80000004800 */
/*0140*/ @!P1 LDS R3, [R2.X4] ; /* 0x0000000002039984 */
/* 0x000e240000004800 */
/*0150*/ @!P1 IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100039824 */
/* 0x001fe200078e0203 */
/*0160*/ MOV R0, R6 ; /* 0x0000000600007202 */
/* 0x000fc80000000f00 */
/*0170*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f26070 */
/*01a0*/ @!P1 BRA 0xf0 ; /* 0xffffff4000009947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7reduce0PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*00b0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P1 BRA 0x2c0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*00e0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.L.U32 R10, R5, 0x1, RZ ; /* 0x00000001050a7819 */
/* 0x000fc800000006ff */
/*0110*/ I2F.U32.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e220000209000 */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R10 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0a */
/*0130*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fcc0003f45070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0180*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fd200078e02ff */
/*0190*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a031210 */
/* 0x000fc80007ffe1ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103031824 */
/* 0x000fe200078e0a0a */
/*0210*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @!P1 LEA R2, R5, R0, 0x2 ; /* 0x0000000005029211 */
/* 0x000fe200078e10ff */
/*0240*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe20000004800 */
/*0250*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fc80000000f00 */
/*0260*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0270*/ @!P1 IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103039824 */
/* 0x001fca00078e0202 */
/*0280*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*02b0*/ @!P1 BRA 0x100 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce0PiS_
.globl _Z7reduce0PiS_
.p2align 8
.type _Z7reduce0PiS_,@function
_Z7reduce0PiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_mov_b32 s5, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce0PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce0PiS_, .Lfunc_end0-_Z7reduce0PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7reduce1PiS_
.globl _Z7reduce1PiS_
.p2align 8
.type _Z7reduce1PiS_,@function
_Z7reduce1PiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v2, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
s_mov_b32 s5, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
.LBB1_3:
s_lshl_b32 s4, s5, 1
s_mov_b32 s6, exec_lo
v_mul_lo_u32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
v_add_nc_u32_e32 v2, s5, v1
v_lshl_add_u32 v1, v1, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce1PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7reduce1PiS_, .Lfunc_end1-_Z7reduce1PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7reduce2PiS_
.globl _Z7reduce2PiS_
.p2align 8
.type _Z7reduce2PiS_,@function
_Z7reduce2PiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB2_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB2_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB2_1
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB2_1
.LBB2_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce2PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7reduce2PiS_, .Lfunc_end2-_Z7reduce2PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z9addKernelPiPKiS1_, .Lfunc_end3-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce0PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce0PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce1PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce1PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce2PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce2PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00122b27_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7reduce0PiS_PiS_
.type _Z28__device_stub__Z7reduce0PiS_PiS_, @function
_Z28__device_stub__Z7reduce0PiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce0PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z7reduce0PiS_PiS_, .-_Z28__device_stub__Z7reduce0PiS_PiS_
.globl _Z7reduce0PiS_
.type _Z7reduce0PiS_, @function
_Z7reduce0PiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce0PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7reduce0PiS_, .-_Z7reduce0PiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "reduce0 launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z14reduceWithCudaPiPKij
.type _Z14reduceWithCudaPiPKij, @function
_Z14reduceWithCudaPiPKij:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L22
movl %r13d, %r14d
salq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L23
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L24
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L25
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L17:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L22:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl %ebx, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L24:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L25:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7reduce0PiS_PiS_
jmp .L17
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L28:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z14reduceWithCudaPiPKij, .-_Z14reduceWithCudaPiPKij
.section .rodata.str1.1
.LC5:
.string "addWithCuda failed!"
.section .rodata.str1.8
.align 8
.LC6:
.string "{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n"
.section .rodata.str1.1
.LC7:
.string "cudaDeviceReset failed!"
.LC8:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $4, 28(%rsp)
movl $5, 32(%rsp)
pxor %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movl $0, 64(%rsp)
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
movl $5, %edx
call _Z14reduceWithCudaPiPKij
testl %eax, %eax
jne .L36
subq $8, %rsp
.cfi_def_cfa_offset 104
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl 76(%rsp), %r9d
movl 72(%rsp), %r8d
movl 68(%rsp), %ecx
movl 64(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L37
leaq 12(%rsp), %rsi
leaq .LC8(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, %eax
.L30:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L30
.L37:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L30
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.globl _Z28__device_stub__Z7reduce1PiS_PiS_
.type _Z28__device_stub__Z7reduce1PiS_PiS_, @function
_Z28__device_stub__Z7reduce1PiS_PiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce1PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z7reduce1PiS_PiS_, .-_Z28__device_stub__Z7reduce1PiS_PiS_
.globl _Z7reduce1PiS_
.type _Z7reduce1PiS_, @function
_Z7reduce1PiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce1PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7reduce1PiS_, .-_Z7reduce1PiS_
.globl _Z28__device_stub__Z7reduce2PiS_PiS_
.type _Z28__device_stub__Z7reduce2PiS_PiS_, @function
_Z28__device_stub__Z7reduce2PiS_PiS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce2PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z28__device_stub__Z7reduce2PiS_PiS_, .-_Z28__device_stub__Z7reduce2PiS_PiS_
.globl _Z7reduce2PiS_
.type _Z7reduce2PiS_, @function
_Z7reduce2PiS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce2PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z7reduce2PiS_, .-_Z7reduce2PiS_
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.1
.LC9:
.string "addKernel launch failed: %s\n"
.text
.globl _Z11addWithCudaPiPKiS1_j
.type _Z11addWithCudaPiPKiS1_j, @function
_Z11addWithCudaPiPKiS1_j:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L76
movl %ebp, %r15d
salq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L77
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L78
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L79
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L80
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L81
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L71:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L83
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L84
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L65
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L76:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L65:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L85
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L78:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L79:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L80:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L81:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L82:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
jmp .L71
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L84:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L65
.L85:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11addWithCudaPiPKiS1_j, .-_Z11addWithCudaPiPKiS1_j
.section .rodata.str1.1
.LC10:
.string "_Z9addKernelPiPKiS1_"
.LC11:
.string "_Z7reduce2PiS_"
.LC12:
.string "_Z7reduce1PiS_"
.LC13:
.string "_Z7reduce0PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce2PiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce1PiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce0PiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z22__device_stub__reduce0PiS_ # -- Begin function _Z22__device_stub__reduce0PiS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce0PiS_,@function
_Z22__device_stub__reduce0PiS_: # @_Z22__device_stub__reduce0PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce0PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce0PiS_, .Lfunc_end0-_Z22__device_stub__reduce0PiS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__reduce1PiS_ # -- Begin function _Z22__device_stub__reduce1PiS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce1PiS_,@function
_Z22__device_stub__reduce1PiS_: # @_Z22__device_stub__reduce1PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce1PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__reduce1PiS_, .Lfunc_end1-_Z22__device_stub__reduce1PiS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__reduce2PiS_ # -- Begin function _Z22__device_stub__reduce2PiS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce2PiS_,@function
_Z22__device_stub__reduce2PiS_: # @_Z22__device_stub__reduce2PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce2PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z22__device_stub__reduce2PiS_, .Lfunc_end2-_Z22__device_stub__reduce2PiS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end3-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.globl _Z14reduceWithCudaPiPKij # -- Begin function _Z14reduceWithCudaPiPKij
.p2align 4, 0x90
.type _Z14reduceWithCudaPiPKij,@function
_Z14reduceWithCudaPiPKij: # @_Z14reduceWithCudaPiPKij
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r12
movq %rdi, %rbx
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB4_11
# %bb.1:
movl %ebp, %r15d
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.2:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.3:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_12
# %bb.4:
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r15
orq $1, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce0PiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_17
# %bb.7:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_18
# %bb.8:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB4_16
# %bb.9:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB4_15
.LBB4_10:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
jmp .LBB4_13
.LBB4_11:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $63, %esi
jmp .LBB4_14
.LBB4_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
.LBB4_13:
movl $17, %esi
.LBB4_14:
movl $1, %edx
.LBB4_15:
callq fwrite@PLT
.LBB4_16:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_17:
.cfi_def_cfa_offset 144
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB4_16
.LBB4_18:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB4_16
.Lfunc_end4:
.size _Z14reduceWithCudaPiPKij, .Lfunc_end4-_Z14reduceWithCudaPiPKij
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPiPKiS1_j # -- Begin function _Z11addWithCudaPiPKiS1_j
.p2align 4, 0x90
.type _Z11addWithCudaPiPKiS1_j,@function
_Z11addWithCudaPiPKiS1_j: # @_Z11addWithCudaPiPKiS1_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB5_18
# %bb.1:
movl %ebp, %r15d
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_13
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_13
# %bb.6:
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r15
orq $1, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB5_19
# %bb.9:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_20
# %bb.10:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB5_17
# %bb.11:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB5_16
.LBB5_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
jmp .LBB5_14
.LBB5_13:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
.LBB5_14:
movl $17, %esi
.LBB5_15:
movl $1, %edx
.LBB5_16:
callq fwrite@PLT
.LBB5_17:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_18:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $63, %esi
jmp .LBB5_15
.LBB5_19:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_17
.LBB5_20:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB5_17
.Lfunc_end5:
.size _Z11addWithCudaPiPKiS1_j, .Lfunc_end5-_Z11addWithCudaPiPKiS1_j
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI6_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movaps .LCPI6_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 32(%rsp)
movl $5, 48(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movl $5, %edx
callq _Z14reduceWithCudaPiPKij
testl %eax, %eax
jne .LBB6_1
# %bb.3:
movl (%rsp), %esi
movl 4(%rsp), %edx
movl 8(%rsp), %ecx
movl 12(%rsp), %r8d
movl 16(%rsp), %r9d
xorl %ebx, %ebx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
callq hipDeviceReset
testl %eax, %eax
jne .LBB6_4
# %bb.5:
leaq 28(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq __isoc23_scanf
.LBB6_6:
movl %ebx, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB6_1:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $19, %esi
jmp .LBB6_2
.LBB6_4:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $22, %esi
.LBB6_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %ebx
jmp .LBB6_6
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce0PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce1PiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce2PiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce0PiS_,@object # @_Z7reduce0PiS_
.section .rodata,"a",@progbits
.globl _Z7reduce0PiS_
.p2align 3, 0x0
_Z7reduce0PiS_:
.quad _Z22__device_stub__reduce0PiS_
.size _Z7reduce0PiS_, 8
.type _Z7reduce1PiS_,@object # @_Z7reduce1PiS_
.globl _Z7reduce1PiS_
.p2align 3, 0x0
_Z7reduce1PiS_:
.quad _Z22__device_stub__reduce1PiS_
.size _Z7reduce1PiS_, 8
.type _Z7reduce2PiS_,@object # @_Z7reduce2PiS_
.globl _Z7reduce2PiS_
.p2align 3, 0x0
_Z7reduce2PiS_:
.quad _Z22__device_stub__reduce2PiS_
.size _Z7reduce2PiS_, 8
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str, 64
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc failed!"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy failed!"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "reduce0 launch failed: %s\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.4, 72
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "addKernel launch failed: %s\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "addWithCuda failed!"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n"
.size .L.str.7, 51
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipDeviceReset failed!"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reduce0PiS_"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7reduce1PiS_"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7reduce2PiS_"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_4, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce0PiS_
.addrsig_sym _Z22__device_stub__reduce1PiS_
.addrsig_sym _Z22__device_stub__reduce2PiS_
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce0PiS_
.addrsig_sym _Z7reduce1PiS_
.addrsig_sym _Z7reduce2PiS_
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
#define max 20
#define min 0
#define dato 10
using namespace std;
__global__ void busqueda_bin(int* x, int *a, int* flag)
{
int i = threadIdx.x;
if (*(a + i) == *x)
*(flag + i) = 1;
else
*(flag + i) = 0;
}
int main()
{
int* a;
int* x;
int* flag;
int* d_flag = 0;
int* dev_a = 0;
int* b = 0;
x = new int[1];
a = new int[max];
flag = new int[max];
*x = dato;
cout << "Busqueda Binaria" << endl << "Dato: " << *x << endl << "Datos:\t";
srand(time(0));
for (int i = min; i < max; i++)
* (a + i) = rand()%20;
for (int i = min; i < max; i++)
cout << *(a + i) << "\t";
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudasetdevice failed! do you have a cuda-capable gpu installed?");
goto Error;
}
//Reservar memoria en GPU
cudaStatus = cudaMalloc((void**)& d_flag, max * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)& dev_a, max * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)& b, sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, max * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(b, x, sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
//Launch a kernel on the GPU with one thread for each element.
busqueda_bin<<<1, max>>>(b, dev_a, d_flag);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(flag, d_flag, max * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(b);
cudaFree(dev_a);
cudaFree(d_flag);
cout << endl << "Flag:\t";
for (int i = min; i < max; i++)
cout << *(flag + i) << "\t";
delete[] a, flag;
return 0;
} | code for sm_80
Function : _Z12busqueda_binPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fca0000000f00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0070*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fcc00078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x004fc80003f05270 */
/*00b0*/ SEL R9, RZ, 0x1, P0 ; /* 0x00000001ff097807 */
/* 0x000fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
#define max 20
#define min 0
#define dato 10
using namespace std;
__global__ void busqueda_bin(int* x, int *a, int* flag)
{
int i = threadIdx.x;
if (*(a + i) == *x)
*(flag + i) = 1;
else
*(flag + i) = 0;
}
int main()
{
int* a;
int* x;
int* flag;
int* d_flag = 0;
int* dev_a = 0;
int* b = 0;
x = new int[1];
a = new int[max];
flag = new int[max];
*x = dato;
cout << "Busqueda Binaria" << endl << "Dato: " << *x << endl << "Datos:\t";
srand(time(0));
for (int i = min; i < max; i++)
* (a + i) = rand()%20;
for (int i = min; i < max; i++)
cout << *(a + i) << "\t";
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudasetdevice failed! do you have a cuda-capable gpu installed?");
goto Error;
}
//Reservar memoria en GPU
cudaStatus = cudaMalloc((void**)& d_flag, max * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)& dev_a, max * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)& b, sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, max * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(b, x, sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
//Launch a kernel on the GPU with one thread for each element.
busqueda_bin<<<1, max>>>(b, dev_a, d_flag);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(flag, d_flag, max * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(b);
cudaFree(dev_a);
cudaFree(d_flag);
cout << endl << "Flag:\t";
for (int i = min; i < max; i++)
cout << *(flag + i) << "\t";
delete[] a, flag;
return 0;
} | .file "tmpxft_00069c87_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_
.type _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_, @function
_Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12busqueda_binPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_, .-_Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_
.globl _Z12busqueda_binPiS_S_
.type _Z12busqueda_binPiS_S_, @function
_Z12busqueda_binPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12busqueda_binPiS_S_, .-_Z12busqueda_binPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Busqueda Binaria"
.LC1:
.string "Dato: "
.LC2:
.string "Datos:\t"
.LC3:
.string "\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "cudasetdevice failed! do you have a cuda-capable gpu installed?"
.section .rodata.str1.1
.LC5:
.string "cudaMalloc failed!"
.LC6:
.string "cudaMemcpy failed!"
.LC7:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.section .rodata.str1.1
.LC9:
.string "Flag:\t"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movl $4, %edi
call _Znam@PLT
movq %rax, %r15
movl $80, %edi
call _Znam@PLT
movq %rax, %r14
movl $80, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $10, (%r15)
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%r15), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r14, %rbx
leaq 80(%r14), %rbp
movq %r14, %r12
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%r12)
addq $4, %r12
cmpq %rbp, %r12
jne .L12
leaq _ZSt4cout(%rip), %r13
leaq .LC3(%rip), %r12
.L13:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L30
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq 32(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
movl $20, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L21:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L38
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L15
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L30:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L15:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rsp), %r13
movq %r13, %rbx
addq $80, %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC3(%rip), %rbp
.L24:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L24
movq %r14, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L32:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L33:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L34:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L35:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L36:
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_
jmp .L21
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L38:
movl %eax, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12busqueda_binPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12busqueda_binPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
#define max 20
#define min 0
#define dato 10
using namespace std;
__global__ void busqueda_bin(int* x, int *a, int* flag)
{
int i = threadIdx.x;
if (*(a + i) == *x)
*(flag + i) = 1;
else
*(flag + i) = 0;
}
int main()
{
int* a;
int* x;
int* flag;
int* d_flag = 0;
int* dev_a = 0;
int* b = 0;
x = new int[1];
a = new int[max];
flag = new int[max];
*x = dato;
cout << "Busqueda Binaria" << endl << "Dato: " << *x << endl << "Datos:\t";
srand(time(0));
for (int i = min; i < max; i++)
* (a + i) = rand()%20;
for (int i = min; i < max; i++)
cout << *(a + i) << "\t";
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudasetdevice failed! do you have a cuda-capable gpu installed?");
goto Error;
}
//Reservar memoria en GPU
cudaStatus = cudaMalloc((void**)& d_flag, max * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)& dev_a, max * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)& b, sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, max * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(b, x, sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
//Launch a kernel on the GPU with one thread for each element.
busqueda_bin<<<1, max>>>(b, dev_a, d_flag);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(flag, d_flag, max * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(b);
cudaFree(dev_a);
cudaFree(d_flag);
cout << endl << "Flag:\t";
for (int i = min; i < max; i++)
cout << *(flag + i) << "\t";
delete[] a, flag;
return 0;
} | #include "hip/hip_runtime.h"
#include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
#define max 20
#define min 0
#define dato 10
using namespace std;
__global__ void busqueda_bin(int* x, int *a, int* flag)
{
int i = threadIdx.x;
if (*(a + i) == *x)
*(flag + i) = 1;
else
*(flag + i) = 0;
}
int main()
{
int* a;
int* x;
int* flag;
int* d_flag = 0;
int* dev_a = 0;
int* b = 0;
x = new int[1];
a = new int[max];
flag = new int[max];
*x = dato;
cout << "Busqueda Binaria" << endl << "Dato: " << *x << endl << "Datos:\t";
srand(time(0));
for (int i = min; i < max; i++)
* (a + i) = rand()%20;
for (int i = min; i < max; i++)
cout << *(a + i) << "\t";
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "cudasetdevice failed! do you have a cuda-capable gpu installed?");
goto Error;
}
//Reservar memoria en GPU
cudaStatus = hipMalloc((void**)& d_flag, max * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)& dev_a, max * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)& b, sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, max * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(b, x, sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
//Launch a kernel on the GPU with one thread for each element.
busqueda_bin<<<1, max>>>(b, dev_a, d_flag);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(flag, d_flag, max * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(b);
hipFree(dev_a);
hipFree(d_flag);
cout << endl << "Flag:\t";
for (int i = min; i < max; i++)
cout << *(flag + i) << "\t";
delete[] a, flag;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
#define max 20
#define min 0
#define dato 10
using namespace std;
__global__ void busqueda_bin(int* x, int *a, int* flag)
{
int i = threadIdx.x;
if (*(a + i) == *x)
*(flag + i) = 1;
else
*(flag + i) = 0;
}
int main()
{
int* a;
int* x;
int* flag;
int* d_flag = 0;
int* dev_a = 0;
int* b = 0;
x = new int[1];
a = new int[max];
flag = new int[max];
*x = dato;
cout << "Busqueda Binaria" << endl << "Dato: " << *x << endl << "Datos:\t";
srand(time(0));
for (int i = min; i < max; i++)
* (a + i) = rand()%20;
for (int i = min; i < max; i++)
cout << *(a + i) << "\t";
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "cudasetdevice failed! do you have a cuda-capable gpu installed?");
goto Error;
}
//Reservar memoria en GPU
cudaStatus = hipMalloc((void**)& d_flag, max * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)& dev_a, max * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)& b, sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, max * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(b, x, sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
//Launch a kernel on the GPU with one thread for each element.
busqueda_bin<<<1, max>>>(b, dev_a, d_flag);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(flag, d_flag, max * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(b);
hipFree(dev_a);
hipFree(d_flag);
cout << endl << "Flag:\t";
for (int i = min; i < max; i++)
cout << *(flag + i) << "\t";
delete[] a, flag;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12busqueda_binPiS_S_
.globl _Z12busqueda_binPiS_S_
.p2align 8
.type _Z12busqueda_binPiS_S_,@function
_Z12busqueda_binPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[6:7]
s_load_b32 s2, s[4:5], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
v_cndmask_b32_e64 v1, 0, 1, vcc_lo
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12busqueda_binPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12busqueda_binPiS_S_, .Lfunc_end0-_Z12busqueda_binPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12busqueda_binPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12busqueda_binPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
#define max 20
#define min 0
#define dato 10
using namespace std;
__global__ void busqueda_bin(int* x, int *a, int* flag)
{
int i = threadIdx.x;
if (*(a + i) == *x)
*(flag + i) = 1;
else
*(flag + i) = 0;
}
int main()
{
int* a;
int* x;
int* flag;
int* d_flag = 0;
int* dev_a = 0;
int* b = 0;
x = new int[1];
a = new int[max];
flag = new int[max];
*x = dato;
cout << "Busqueda Binaria" << endl << "Dato: " << *x << endl << "Datos:\t";
srand(time(0));
for (int i = min; i < max; i++)
* (a + i) = rand()%20;
for (int i = min; i < max; i++)
cout << *(a + i) << "\t";
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "cudasetdevice failed! do you have a cuda-capable gpu installed?");
goto Error;
}
//Reservar memoria en GPU
cudaStatus = hipMalloc((void**)& d_flag, max * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)& dev_a, max * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)& b, sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, max * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(b, x, sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
//Launch a kernel on the GPU with one thread for each element.
busqueda_bin<<<1, max>>>(b, dev_a, d_flag);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(flag, d_flag, max * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(b);
hipFree(dev_a);
hipFree(d_flag);
cout << endl << "Flag:\t";
for (int i = min; i < max; i++)
cout << *(flag + i) << "\t";
delete[] a, flag;
return 0;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__busqueda_binPiS_S_ # -- Begin function _Z27__device_stub__busqueda_binPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__busqueda_binPiS_S_,@function
_Z27__device_stub__busqueda_binPiS_S_: # @_Z27__device_stub__busqueda_binPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12busqueda_binPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__busqueda_binPiS_S_, .Lfunc_end0-_Z27__device_stub__busqueda_binPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
movl $4, %edi
callq _Znam
movq %rax, %r15
movl $80, %edi
callq _Znam
movq %rax, %rbx
movl $80, %edi
callq _Znam
movq %rax, %r14
movl $10, (%r15)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_37
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_3
# %bb.2:
movzbl 67(%r12), %eax
jmp .LBB1_4
.LBB1_3:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rax, %r12
movl $.L.str.1, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15), %esi
movq %r12, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_37
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
cmpb $0, 56(%r12)
je .LBB1_7
# %bb.6:
movzbl 67(%r12), %ecx
jmp .LBB1_8
.LBB1_7:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.2, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $20, %r12
jne .LBB1_9
# %bb.10: # %.preheader.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $20, %r12
jne .LBB1_11
# %bb.12:
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_13
# %bb.14:
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_15
# %bb.16:
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_15
# %bb.17:
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_15
# %bb.18:
movq 8(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.19:
movq (%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.20:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 19(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_22
# %bb.21:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12busqueda_binPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_22:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_23
# %bb.24:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_25
# %bb.26:
movq 16(%rsp), %rsi
movl $80, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_30
.LBB1_27:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
jmp .LBB1_28
.LBB1_15:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
.LBB1_28:
movl $17, %esi
.LBB1_29:
movl $1, %edx
callq fwrite@PLT
.LBB1_30:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_37
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i49
cmpb $0, 56(%r15)
je .LBB1_33
# %bb.32:
movzbl 67(%r15), %eax
jmp .LBB1_34
.LBB1_33:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit52
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.9, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_35: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq $20, %r15
jne .LBB1_35
# %bb.36:
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $64, %esi
jmp .LBB1_29
.LBB1_23:
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_30
.LBB1_25:
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_30
.LBB1_37:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12busqueda_binPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12busqueda_binPiS_S_,@object # @_Z12busqueda_binPiS_S_
.section .rodata,"a",@progbits
.globl _Z12busqueda_binPiS_S_
.p2align 3, 0x0
_Z12busqueda_binPiS_S_:
.quad _Z27__device_stub__busqueda_binPiS_S_
.size _Z12busqueda_binPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Busqueda Binaria"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Dato: "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Datos:\t"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\t"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cudasetdevice failed! do you have a cuda-capable gpu installed?"
.size .L.str.4, 65
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMalloc failed!"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy failed!"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "addKernel launch failed: %s\n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.8, 72
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Flag:\t"
.size .L.str.9, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12busqueda_binPiS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__busqueda_binPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12busqueda_binPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12busqueda_binPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fca0000000f00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0070*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fcc00078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x004fc80003f05270 */
/*00b0*/ SEL R9, RZ, 0x1, P0 ; /* 0x00000001ff097807 */
/* 0x000fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12busqueda_binPiS_S_
.globl _Z12busqueda_binPiS_S_
.p2align 8
.type _Z12busqueda_binPiS_S_,@function
_Z12busqueda_binPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[6:7]
s_load_b32 s2, s[4:5], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
v_cndmask_b32_e64 v1, 0, 1, vcc_lo
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12busqueda_binPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12busqueda_binPiS_S_, .Lfunc_end0-_Z12busqueda_binPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12busqueda_binPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12busqueda_binPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00069c87_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_
.type _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_, @function
_Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12busqueda_binPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_, .-_Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_
.globl _Z12busqueda_binPiS_S_
.type _Z12busqueda_binPiS_S_, @function
_Z12busqueda_binPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12busqueda_binPiS_S_, .-_Z12busqueda_binPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Busqueda Binaria"
.LC1:
.string "Dato: "
.LC2:
.string "Datos:\t"
.LC3:
.string "\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "cudasetdevice failed! do you have a cuda-capable gpu installed?"
.section .rodata.str1.1
.LC5:
.string "cudaMalloc failed!"
.LC6:
.string "cudaMemcpy failed!"
.LC7:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.section .rodata.str1.1
.LC9:
.string "Flag:\t"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movl $4, %edi
call _Znam@PLT
movq %rax, %r15
movl $80, %edi
call _Znam@PLT
movq %rax, %r14
movl $80, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $10, (%r15)
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%r15), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r14, %rbx
leaq 80(%r14), %rbp
movq %r14, %r12
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%r12)
addq $4, %r12
cmpq %rbp, %r12
jne .L12
leaq _ZSt4cout(%rip), %r13
leaq .LC3(%rip), %r12
.L13:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L30
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq 32(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
movl $20, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L21:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L38
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L15
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L30:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L15:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rsp), %r13
movq %r13, %rbx
addq $80, %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC3(%rip), %rbp
.L24:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L24
movq %r14, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L32:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L33:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L34:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L35:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L36:
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z12busqueda_binPiS_S_PiS_S_
jmp .L21
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L38:
movl %eax, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12busqueda_binPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12busqueda_binPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__busqueda_binPiS_S_ # -- Begin function _Z27__device_stub__busqueda_binPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__busqueda_binPiS_S_,@function
_Z27__device_stub__busqueda_binPiS_S_: # @_Z27__device_stub__busqueda_binPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12busqueda_binPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__busqueda_binPiS_S_, .Lfunc_end0-_Z27__device_stub__busqueda_binPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
movl $4, %edi
callq _Znam
movq %rax, %r15
movl $80, %edi
callq _Znam
movq %rax, %rbx
movl $80, %edi
callq _Znam
movq %rax, %r14
movl $10, (%r15)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_37
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_3
# %bb.2:
movzbl 67(%r12), %eax
jmp .LBB1_4
.LBB1_3:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rax, %r12
movl $.L.str.1, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15), %esi
movq %r12, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_37
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
cmpb $0, 56(%r12)
je .LBB1_7
# %bb.6:
movzbl 67(%r12), %ecx
jmp .LBB1_8
.LBB1_7:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.2, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $20, %r12
jne .LBB1_9
# %bb.10: # %.preheader.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $20, %r12
jne .LBB1_11
# %bb.12:
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_13
# %bb.14:
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_15
# %bb.16:
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_15
# %bb.17:
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_15
# %bb.18:
movq 8(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.19:
movq (%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.20:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 19(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_22
# %bb.21:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12busqueda_binPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_22:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_23
# %bb.24:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_25
# %bb.26:
movq 16(%rsp), %rsi
movl $80, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_30
.LBB1_27:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
jmp .LBB1_28
.LBB1_15:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
.LBB1_28:
movl $17, %esi
.LBB1_29:
movl $1, %edx
callq fwrite@PLT
.LBB1_30:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_37
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i49
cmpb $0, 56(%r15)
je .LBB1_33
# %bb.32:
movzbl 67(%r15), %eax
jmp .LBB1_34
.LBB1_33:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit52
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.9, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_35: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq $20, %r15
jne .LBB1_35
# %bb.36:
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $64, %esi
jmp .LBB1_29
.LBB1_23:
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_30
.LBB1_25:
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_30
.LBB1_37:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12busqueda_binPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12busqueda_binPiS_S_,@object # @_Z12busqueda_binPiS_S_
.section .rodata,"a",@progbits
.globl _Z12busqueda_binPiS_S_
.p2align 3, 0x0
_Z12busqueda_binPiS_S_:
.quad _Z27__device_stub__busqueda_binPiS_S_
.size _Z12busqueda_binPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Busqueda Binaria"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Dato: "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Datos:\t"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\t"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cudasetdevice failed! do you have a cuda-capable gpu installed?"
.size .L.str.4, 65
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMalloc failed!"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy failed!"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "addKernel launch failed: %s\n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.8, 72
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Flag:\t"
.size .L.str.9, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12busqueda_binPiS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__busqueda_binPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12busqueda_binPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
__global__ void kernel( void ) { }
int main()
{
kernel<<< 1, 1 >>>();
printf("Hello World!\n");
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
__global__ void kernel( void ) { }
int main()
{
kernel<<< 1, 1 >>>();
printf("Hello World!\n");
return EXIT_SUCCESS;
} | .file "tmpxft_001988da_00000000-6_cuda_ex_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
__global__ void kernel( void ) { }
int main()
{
kernel<<< 1, 1 >>>();
printf("Hello World!\n");
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void kernel( void ) { }
int main()
{
kernel<<< 1, 1 >>>();
printf("Hello World!\n");
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void kernel( void ) { }
int main()
{
kernel<<< 1, 1 >>>();
printf("Hello World!\n");
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void kernel( void ) { }
int main()
{
kernel<<< 1, 1 >>>();
printf("Hello World!\n");
return EXIT_SUCCESS;
} | .text
.file "cuda_ex_1.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001988da_00000000-6_cuda_ex_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_ex_1.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include<cstdio>
using namespace std;
__global__ void mini1(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int mini=7888888;
for(int i=block;i<min(256+block,n);i++)
{
if(mini>a[i])
{
mini=a[i];
}
}
b[blockIdx.x]=mini;
}
int main()
{
cout<<"Enter the size of array"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
cudaMalloc(&ad,size);
cudaMemcpy(ad,a,size,cudaMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
cudaMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
while(n>1)
{
mini1<<<grids,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
cudaMemcpy(ad,bd,n*sizeof(int),cudaMemcpyDeviceToDevice);
}
int ans[2];
cudaMemcpy(ans,ad,4,cudaMemcpyDeviceToHost);
cout<<"The minimum element is"<<ans[0]<<endl;
} | code for sm_80
Function : _Z5mini1PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, 0x785ff8 ; /* 0x00785ff8ff057424 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.SHL.U32 R6, R0, 0x100, RZ ; /* 0x0000010000067824 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R2, R6, 0x100, RZ ; /* 0x0000010006027810 */
/* 0x000fc80007ffe0ff */
/*0060*/ IMNMX R3, R2, c[0x0][0x170], PT ; /* 0x00005c0002037a17 */
/* 0x000fc80003800200 */
/*0070*/ ISETP.GE.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x800 ; /* 0x0000077000000947 */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R2, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff027a12 */
/* 0x000fe200078e33ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x785ff8 ; /* 0x00785ff8ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R3, -R6, -0x101, RZ ; /* 0xfffffeff06037810 */
/* 0x000fc80007ffe1ff */
/*00c0*/ IMNMX R7, R2, R3, !PT ; /* 0x0000000302077217 */
/* 0x000fc80007800200 */
/*00d0*/ IADD3 R2, -R6, -0x2, -R7 ; /* 0xfffffffe06027810 */
/* 0x000fe40007ffe907 */
/*00e0*/ LOP3.LUT R3, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff037212 */
/* 0x000fe400078e33ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fc60003f06070 */
/*0100*/ IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103037824 */
/* 0x000fca00078e0a06 */
/*0110*/ LOP3.LUT R4, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x000fca00078ec0ff */
/*0120*/ @!P0 BRA 0x730 ; /* 0x0000060000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R7, R4, R7, R6 ; /* 0x0000000704077210 */
/* 0x000fe20007ffe006 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, 0x785ff8 ; /* 0x00785ff8ff057424 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a07 */
/*0170*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc600078e0203 */
/*0180*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f3e0ff */
/*01a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*01b0*/ @!P0 BRA 0x630 ; /* 0x0000047000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x470 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R18, [R2.64+-0x8] ; /* 0xfffff80402127981 */
/* 0x0000a8000c1e1900 */
/*0220*/ LDG.E R17, [R2.64+-0x4] ; /* 0xfffffc0402117981 */
/* 0x0000e8000c1e1900 */
/*0230*/ LDG.E R20, [R2.64] ; /* 0x0000000402147981 */
/* 0x000128000c1e1900 */
/*0240*/ LDG.E R22, [R2.64+0x4] ; /* 0x0000040402167981 */
/* 0x000168000c1e1900 */
/*0250*/ LDG.E R24, [R2.64+0x8] ; /* 0x0000080402187981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R26, [R2.64+0xc] ; /* 0x00000c04021a7981 */
/* 0x000168000c1e1900 */
/*0270*/ LDG.E R28, [R2.64+0x10] ; /* 0x00001004021c7981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R16, [R2.64+0x14] ; /* 0x0000140402107981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R15, [R2.64+0x18] ; /* 0x00001804020f7981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R13, [R2.64+0x20] ; /* 0x00002004020d7981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R12, [R2.64+0x24] ; /* 0x00002404020c7981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002804020b7981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0402097981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R10, [R2.64+0x30] ; /* 0x00003004020a7981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340402087981 */
/* 0x000162000c1e1900 */
/*0310*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*0320*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fe40003f24270 */
/*0340*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fca0007f5e0ff */
/*0350*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0360*/ IMNMX R18, R18, R5, PT ; /* 0x0000000512127217 */
/* 0x004fc80003800200 */
/*0370*/ IMNMX R17, R18, R17, PT ; /* 0x0000001112117217 */
/* 0x008fc80003800200 */
/*0380*/ IMNMX R17, R17, R20, PT ; /* 0x0000001411117217 */
/* 0x010fc80003800200 */
/*0390*/ IMNMX R17, R17, R22, PT ; /* 0x0000001611117217 */
/* 0x020fc80003800200 */
/*03a0*/ IMNMX R17, R17, R24, PT ; /* 0x0000001811117217 */
/* 0x000fc80003800200 */
/*03b0*/ IMNMX R17, R17, R26, PT ; /* 0x0000001a11117217 */
/* 0x000fc80003800200 */
/*03c0*/ IMNMX R17, R17, R28, PT ; /* 0x0000001c11117217 */
/* 0x000fc80003800200 */
/*03d0*/ IMNMX R16, R17, R16, PT ; /* 0x0000001011107217 */
/* 0x000fc80003800200 */
/*03e0*/ IMNMX R15, R16, R15, PT ; /* 0x0000000f100f7217 */
/* 0x000fc80003800200 */
/*03f0*/ IMNMX R14, R15, R14, PT ; /* 0x0000000e0f0e7217 */
/* 0x000fc80003800200 */
/*0400*/ IMNMX R13, R14, R13, PT ; /* 0x0000000d0e0d7217 */
/* 0x000fc80003800200 */
/*0410*/ IMNMX R12, R13, R12, PT ; /* 0x0000000c0d0c7217 */
/* 0x000fc80003800200 */
/*0420*/ IMNMX R12, R12, R11, PT ; /* 0x0000000b0c0c7217 */
/* 0x000fc80003800200 */
/*0430*/ IMNMX R9, R12, R9, PT ; /* 0x000000090c097217 */
/* 0x000fc80003800200 */
/*0440*/ IMNMX R9, R9, R10, PT ; /* 0x0000000a09097217 */
/* 0x000fc80003800200 */
/*0450*/ IMNMX R5, R9, R8, PT ; /* 0x0000000809057217 */
/* 0x000fe20003800200 */
/*0460*/ @P1 BRA 0x210 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0470*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0490*/ @!P1 BRA 0x610 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*04a0*/ LDG.E R8, [R2.64+-0x8] ; /* 0xfffff80402087981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0402097981 */
/* 0x000ee8000c1e1900 */
/*04c0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000f68000c1e1900 */
/*04e0*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000168000c1e1900 */
/*04f0*/ LDG.E R17, [R2.64+0xc] ; /* 0x00000c0402117981 */
/* 0x000168000c1e1900 */
/*0500*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000168000c1e1900 */
/*0510*/ LDG.E R21, [R2.64+0x14] ; /* 0x0000140402157981 */
/* 0x000162000c1e1900 */
/*0520*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0530*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0540*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IMNMX R8, R5, R8, PT ; /* 0x0000000805087217 */
/* 0x004fc80003800200 */
/*0560*/ IMNMX R8, R8, R9, PT ; /* 0x0000000908087217 */
/* 0x008fe40003800200 */
/*0570*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fe40007f3e0ff */
/*0580*/ IMNMX R8, R8, R11, PT ; /* 0x0000000b08087217 */
/* 0x010fc60003800200 */
/*0590*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e0603 */
/*05a0*/ IMNMX R8, R8, R13, PT ; /* 0x0000000d08087217 */
/* 0x020fe20003800200 */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0009 */
/*05c0*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*05d0*/ IMNMX R8, R8, R15, PT ; /* 0x0000000f08087217 */
/* 0x000fc80003800200 */
/*05e0*/ IMNMX R8, R8, R17, PT ; /* 0x0000001108087217 */
/* 0x000fc80003800200 */
/*05f0*/ IMNMX R8, R8, R19, PT ; /* 0x0000001308087217 */
/* 0x000fc80003800200 */
/*0600*/ IMNMX R5, R8, R21, PT ; /* 0x0000001508057217 */
/* 0x000fe40003800200 */
/*0610*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0620*/ @!P0 BRA 0x730 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R8, [R2.64+-0x8] ; /* 0xfffff80402087981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0402097981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000f28000c1e1900 */
/*0660*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000f62000c1e1900 */
/*0670*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*0680*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0690*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f05270 */
/*06a0*/ IMNMX R8, R8, R5, PT ; /* 0x0000000508087217 */
/* 0x004fc80003800200 */
/*06b0*/ IMNMX R8, R8, R9, PT ; /* 0x0000000908087217 */
/* 0x008fe40003800200 */
/*06c0*/ IADD3 R9, P1, R2, 0x10, RZ ; /* 0x0000001002097810 */
/* 0x000fe40007f3e0ff */
/*06d0*/ IMNMX R8, R8, R11, PT ; /* 0x0000000b08087217 */
/* 0x010fc60003800200 */
/*06e0*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e0603 */
/*06f0*/ IMNMX R5, R8, R13, PT ; /* 0x0000000d08057217 */
/* 0x020fe20003800200 */
/*0700*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0009 */
/*0710*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0720*/ @P0 BRA 0x630 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0730*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0740*/ @!P0 BRA 0x800 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0760*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*0770*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0007 */
/*0790*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*07c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*07d0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*07e0*/ IMNMX R5, R2, R5, PT ; /* 0x0000000502057217 */
/* 0x004fd20003800200 */
/*07f0*/ @P0 BRA 0x770 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0800*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0810*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0820*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<cstdio>
using namespace std;
__global__ void mini1(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int mini=7888888;
for(int i=block;i<min(256+block,n);i++)
{
if(mini>a[i])
{
mini=a[i];
}
}
b[blockIdx.x]=mini;
}
int main()
{
cout<<"Enter the size of array"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
cudaMalloc(&ad,size);
cudaMemcpy(ad,a,size,cudaMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
cudaMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
while(n>1)
{
mini1<<<grids,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
cudaMemcpy(ad,bd,n*sizeof(int),cudaMemcpyDeviceToDevice);
}
int ans[2];
cudaMemcpy(ans,ad,4,cudaMemcpyDeviceToHost);
cout<<"The minimum element is"<<ans[0]<<endl;
} | .file "tmpxft_0016494a_00000000-6_A1_MIN.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z5mini1PiS_iPiS_i
.type _Z27__device_stub__Z5mini1PiS_iPiS_i, @function
_Z27__device_stub__Z5mini1PiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5mini1PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z5mini1PiS_iPiS_i, .-_Z27__device_stub__Z5mini1PiS_iPiS_i
.globl _Z5mini1PiS_i
.type _Z5mini1PiS_i, @function
_Z5mini1PiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5mini1PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5mini1PiS_i, .-_Z5mini1PiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the size of array"
.LC5:
.string "The minimum element is"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r12
pushq %rbx
subq $64, %rsp
.cfi_offset 12, -24
.cfi_offset 3, -32
movq %fs:40, %rax
movq %rax, -24(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq -76(%rbp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl -76(%rbp), %esi
movslq %esi, %rcx
leaq 15(,%rcx,4), %rax
movq %rax, %rdi
andq $-16, %rdi
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L12:
cmpq %rdx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rdi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %rbx
testl %esi, %esi
jle .L15
movl $1, %eax
.L16:
movl %eax, -4(%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rcx
jne .L16
.L15:
sall $2, %esi
movslq %esi, %r12
leaq -72(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC6(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC2(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L17
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L17:
cvttss2sil %xmm3, %ebx
movslq %ebx, %rsi
salq $2, %rsi
leaq -64(%rbp), %rdi
call cudaMalloc@PLT
movl $1, -56(%rbp)
movl $1, -52(%rbp)
movl $1, -48(%rbp)
cmpl $1, -76(%rbp)
jg .L21
.L18:
leaq -32(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -72(%rbp), %rsi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -32(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -24(%rbp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
leaq -16(%rbp), %rsp
popq %rbx
popq %r12
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L27:
.cfi_restore_state
movl -76(%rbp), %edx
movq -64(%rbp), %rsi
movq -72(%rbp), %rdi
call _Z27__device_stub__Z5mini1PiS_iPiS_i
jmp .L19
.L20:
cvttss2sil %xmm2, %edx
movl %edx, -76(%rbp)
movslq %edx, %rdx
salq $2, %rdx
movl $3, %ecx
movq -64(%rbp), %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $1, -76(%rbp)
jle .L18
.L21:
movl %ebx, -44(%rbp)
movl $1, -40(%rbp)
movl -48(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -56(%rbp), %rdx
movq -44(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC6(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC2(%rip), %xmm5
ucomiss %xmm1, %xmm5
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC4(%rip), %xmm6
andps %xmm6, %xmm2
addss %xmm2, %xmm1
movss .LC6(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z5mini1PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5mini1PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 998244352
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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