system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<cstdio>
using namespace std;
__global__ void mini1(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int mini=7888888;
for(int i=block;i<min(256+block,n);i++)
{
if(mini>a[i])
{
mini=a[i];
}
}
b[blockIdx.x]=mini;
}
int main()
{
cout<<"Enter the size of array"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
cudaMalloc(&ad,size);
cudaMemcpy(ad,a,size,cudaMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
cudaMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
while(n>1)
{
mini1<<<grids,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
cudaMemcpy(ad,bd,n*sizeof(int),cudaMemcpyDeviceToDevice);
}
int ans[2];
cudaMemcpy(ans,ad,4,cudaMemcpyDeviceToHost);
cout<<"The minimum element is"<<ans[0]<<endl;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstdio>
using namespace std;
__global__ void mini1(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int mini=7888888;
for(int i=block;i<min(256+block,n);i++)
{
if(mini>a[i])
{
mini=a[i];
}
}
b[blockIdx.x]=mini;
}
int main()
{
cout<<"Enter the size of array"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
hipMalloc(&ad,size);
hipMemcpy(ad,a,size,hipMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
hipMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
while(n>1)
{
mini1<<<grids,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
hipMemcpy(ad,bd,n*sizeof(int),hipMemcpyDeviceToDevice);
}
int ans[2];
hipMemcpy(ans,ad,4,hipMemcpyDeviceToHost);
cout<<"The minimum element is"<<ans[0]<<endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstdio>
using namespace std;
__global__ void mini1(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int mini=7888888;
for(int i=block;i<min(256+block,n);i++)
{
if(mini>a[i])
{
mini=a[i];
}
}
b[blockIdx.x]=mini;
}
int main()
{
cout<<"Enter the size of array"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
hipMalloc(&ad,size);
hipMemcpy(ad,a,size,hipMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
hipMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
while(n>1)
{
mini1<<<grids,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
hipMemcpy(ad,bd,n*sizeof(int),hipMemcpyDeviceToDevice);
}
int ans[2];
hipMemcpy(ans,ad,4,hipMemcpyDeviceToHost);
cout<<"The minimum element is"<<ans[0]<<endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5mini1PiS_i
.globl _Z5mini1PiS_i
.p2align 8
.type _Z5mini1PiS_i,@function
_Z5mini1PiS_i:
s_load_b32 s3, s[0:1], 0x10
s_lshl_b32 s4, s15, 8
s_mov_b32 s2, s15
s_mov_b32 s5, 0x785ff8
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s3
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
s_add_i32 s10, s4, 0x100
s_lshl_b64 s[8:9], s[4:5], 2
s_min_i32 s3, s10, s3
s_mov_b32 s5, 0x785ff8
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
.LBB0_2:
s_load_b32 s8, s[6:7], 0x0
s_add_i32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_min_i32 s5, s5, s8
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_ge_i32 s4, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5mini1PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5mini1PiS_i, .Lfunc_end0-_Z5mini1PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5mini1PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z5mini1PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstdio>
using namespace std;
__global__ void mini1(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int mini=7888888;
for(int i=block;i<min(256+block,n);i++)
{
if(mini>a[i])
{
mini=a[i];
}
}
b[blockIdx.x]=mini;
}
int main()
{
cout<<"Enter the size of array"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
hipMalloc(&ad,size);
hipMemcpy(ad,a,size,hipMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
hipMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
while(n>1)
{
mini1<<<grids,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
hipMemcpy(ad,bd,n*sizeof(int),hipMemcpyDeviceToDevice);
}
int ans[2];
hipMemcpy(ans,ad,4,hipMemcpyDeviceToHost);
cout<<"The minimum element is"<<ans[0]<<endl;
} | .text
.file "A1_MIN.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__mini1PiS_i # -- Begin function _Z20__device_stub__mini1PiS_i
.p2align 4, 0x90
.type _Z20__device_stub__mini1PiS_i,@function
_Z20__device_stub__mini1PiS_i: # @_Z20__device_stub__mini1PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5mini1PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__mini1PiS_i, .Lfunc_end0-_Z20__device_stub__mini1PiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq -44(%rbp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq %rsp, -104(%rbp) # 8-byte Spill
movl -44(%rbp), %eax
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%rbx,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB1_6
.LBB1_7: # %._crit_edge
shll $2, %eax
movslq %eax, %r14
leaq -56(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movq -56(%rbp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r14d
movslq %r14d, %rsi
shlq $2, %rsi
leaq -72(%rbp), %rdi
callq hipMalloc
cmpl $2, -44(%rbp)
jl .LBB1_12
# %bb.8: # %.lr.ph24
movabsq $4294967296, %rbx # imm = 0x100000000
movl %r14d, %r14d
orq %rbx, %r14
incq %rbx
leaq -120(%rbp), %r13
leaq -112(%rbp), %r15
leaq -96(%rbp), %r12
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movl %eax, -44(%rbp)
movq -56(%rbp), %rdi
movq -72(%rbp), %rsi
movslq %eax, %rdx
shlq $2, %rdx
movl $3, %ecx
callq hipMemcpy
cmpl $1, -44(%rbp)
jle .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq -56(%rbp), %rax
movq -72(%rbp), %rcx
movl -44(%rbp), %edx
movq %rax, -168(%rbp)
movq %rcx, -160(%rbp)
movl %edx, -60(%rbp)
leaq -168(%rbp), %rax
movq %rax, -96(%rbp)
leaq -160(%rbp), %rax
movq %rax, -88(%rbp)
leaq -60(%rbp), %rax
movq %rax, -80(%rbp)
leaq -152(%rbp), %rdi
leaq -136(%rbp), %rsi
movq %r13, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq -152(%rbp), %rsi
movl -144(%rbp), %edx
movq -136(%rbp), %rcx
movl -128(%rbp), %r8d
movl $_Z5mini1PiS_i, %edi
movq %r12, %r9
pushq -112(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB1_11
.LBB1_12: # %._crit_edge25
movq -56(%rbp), %rsi
leaq -96(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl -96(%rbp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -104(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_17:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5mini1PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5mini1PiS_i,@object # @_Z5mini1PiS_i
.section .rodata,"a",@progbits
.globl _Z5mini1PiS_i
.p2align 3, 0x0
_Z5mini1PiS_i:
.quad _Z20__device_stub__mini1PiS_i
.size _Z5mini1PiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the size of array"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "The minimum element is"
.size .L.str.1, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5mini1PiS_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__mini1PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5mini1PiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5mini1PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, 0x785ff8 ; /* 0x00785ff8ff057424 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.SHL.U32 R6, R0, 0x100, RZ ; /* 0x0000010000067824 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R2, R6, 0x100, RZ ; /* 0x0000010006027810 */
/* 0x000fc80007ffe0ff */
/*0060*/ IMNMX R3, R2, c[0x0][0x170], PT ; /* 0x00005c0002037a17 */
/* 0x000fc80003800200 */
/*0070*/ ISETP.GE.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x800 ; /* 0x0000077000000947 */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R2, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff027a12 */
/* 0x000fe200078e33ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x785ff8 ; /* 0x00785ff8ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R3, -R6, -0x101, RZ ; /* 0xfffffeff06037810 */
/* 0x000fc80007ffe1ff */
/*00c0*/ IMNMX R7, R2, R3, !PT ; /* 0x0000000302077217 */
/* 0x000fc80007800200 */
/*00d0*/ IADD3 R2, -R6, -0x2, -R7 ; /* 0xfffffffe06027810 */
/* 0x000fe40007ffe907 */
/*00e0*/ LOP3.LUT R3, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff037212 */
/* 0x000fe400078e33ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fc60003f06070 */
/*0100*/ IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103037824 */
/* 0x000fca00078e0a06 */
/*0110*/ LOP3.LUT R4, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x000fca00078ec0ff */
/*0120*/ @!P0 BRA 0x730 ; /* 0x0000060000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R7, R4, R7, R6 ; /* 0x0000000704077210 */
/* 0x000fe20007ffe006 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, 0x785ff8 ; /* 0x00785ff8ff057424 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a07 */
/*0170*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc600078e0203 */
/*0180*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f3e0ff */
/*01a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*01b0*/ @!P0 BRA 0x630 ; /* 0x0000047000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x470 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R18, [R2.64+-0x8] ; /* 0xfffff80402127981 */
/* 0x0000a8000c1e1900 */
/*0220*/ LDG.E R17, [R2.64+-0x4] ; /* 0xfffffc0402117981 */
/* 0x0000e8000c1e1900 */
/*0230*/ LDG.E R20, [R2.64] ; /* 0x0000000402147981 */
/* 0x000128000c1e1900 */
/*0240*/ LDG.E R22, [R2.64+0x4] ; /* 0x0000040402167981 */
/* 0x000168000c1e1900 */
/*0250*/ LDG.E R24, [R2.64+0x8] ; /* 0x0000080402187981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R26, [R2.64+0xc] ; /* 0x00000c04021a7981 */
/* 0x000168000c1e1900 */
/*0270*/ LDG.E R28, [R2.64+0x10] ; /* 0x00001004021c7981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R16, [R2.64+0x14] ; /* 0x0000140402107981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R15, [R2.64+0x18] ; /* 0x00001804020f7981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R13, [R2.64+0x20] ; /* 0x00002004020d7981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R12, [R2.64+0x24] ; /* 0x00002404020c7981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002804020b7981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0402097981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R10, [R2.64+0x30] ; /* 0x00003004020a7981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340402087981 */
/* 0x000162000c1e1900 */
/*0310*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*0320*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fe40003f24270 */
/*0340*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fca0007f5e0ff */
/*0350*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0360*/ IMNMX R18, R18, R5, PT ; /* 0x0000000512127217 */
/* 0x004fc80003800200 */
/*0370*/ IMNMX R17, R18, R17, PT ; /* 0x0000001112117217 */
/* 0x008fc80003800200 */
/*0380*/ IMNMX R17, R17, R20, PT ; /* 0x0000001411117217 */
/* 0x010fc80003800200 */
/*0390*/ IMNMX R17, R17, R22, PT ; /* 0x0000001611117217 */
/* 0x020fc80003800200 */
/*03a0*/ IMNMX R17, R17, R24, PT ; /* 0x0000001811117217 */
/* 0x000fc80003800200 */
/*03b0*/ IMNMX R17, R17, R26, PT ; /* 0x0000001a11117217 */
/* 0x000fc80003800200 */
/*03c0*/ IMNMX R17, R17, R28, PT ; /* 0x0000001c11117217 */
/* 0x000fc80003800200 */
/*03d0*/ IMNMX R16, R17, R16, PT ; /* 0x0000001011107217 */
/* 0x000fc80003800200 */
/*03e0*/ IMNMX R15, R16, R15, PT ; /* 0x0000000f100f7217 */
/* 0x000fc80003800200 */
/*03f0*/ IMNMX R14, R15, R14, PT ; /* 0x0000000e0f0e7217 */
/* 0x000fc80003800200 */
/*0400*/ IMNMX R13, R14, R13, PT ; /* 0x0000000d0e0d7217 */
/* 0x000fc80003800200 */
/*0410*/ IMNMX R12, R13, R12, PT ; /* 0x0000000c0d0c7217 */
/* 0x000fc80003800200 */
/*0420*/ IMNMX R12, R12, R11, PT ; /* 0x0000000b0c0c7217 */
/* 0x000fc80003800200 */
/*0430*/ IMNMX R9, R12, R9, PT ; /* 0x000000090c097217 */
/* 0x000fc80003800200 */
/*0440*/ IMNMX R9, R9, R10, PT ; /* 0x0000000a09097217 */
/* 0x000fc80003800200 */
/*0450*/ IMNMX R5, R9, R8, PT ; /* 0x0000000809057217 */
/* 0x000fe20003800200 */
/*0460*/ @P1 BRA 0x210 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0470*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0490*/ @!P1 BRA 0x610 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*04a0*/ LDG.E R8, [R2.64+-0x8] ; /* 0xfffff80402087981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0402097981 */
/* 0x000ee8000c1e1900 */
/*04c0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000f68000c1e1900 */
/*04e0*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000168000c1e1900 */
/*04f0*/ LDG.E R17, [R2.64+0xc] ; /* 0x00000c0402117981 */
/* 0x000168000c1e1900 */
/*0500*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000168000c1e1900 */
/*0510*/ LDG.E R21, [R2.64+0x14] ; /* 0x0000140402157981 */
/* 0x000162000c1e1900 */
/*0520*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0530*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0540*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IMNMX R8, R5, R8, PT ; /* 0x0000000805087217 */
/* 0x004fc80003800200 */
/*0560*/ IMNMX R8, R8, R9, PT ; /* 0x0000000908087217 */
/* 0x008fe40003800200 */
/*0570*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fe40007f3e0ff */
/*0580*/ IMNMX R8, R8, R11, PT ; /* 0x0000000b08087217 */
/* 0x010fc60003800200 */
/*0590*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e0603 */
/*05a0*/ IMNMX R8, R8, R13, PT ; /* 0x0000000d08087217 */
/* 0x020fe20003800200 */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0009 */
/*05c0*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*05d0*/ IMNMX R8, R8, R15, PT ; /* 0x0000000f08087217 */
/* 0x000fc80003800200 */
/*05e0*/ IMNMX R8, R8, R17, PT ; /* 0x0000001108087217 */
/* 0x000fc80003800200 */
/*05f0*/ IMNMX R8, R8, R19, PT ; /* 0x0000001308087217 */
/* 0x000fc80003800200 */
/*0600*/ IMNMX R5, R8, R21, PT ; /* 0x0000001508057217 */
/* 0x000fe40003800200 */
/*0610*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0620*/ @!P0 BRA 0x730 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R8, [R2.64+-0x8] ; /* 0xfffff80402087981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0402097981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000f28000c1e1900 */
/*0660*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000f62000c1e1900 */
/*0670*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*0680*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0690*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f05270 */
/*06a0*/ IMNMX R8, R8, R5, PT ; /* 0x0000000508087217 */
/* 0x004fc80003800200 */
/*06b0*/ IMNMX R8, R8, R9, PT ; /* 0x0000000908087217 */
/* 0x008fe40003800200 */
/*06c0*/ IADD3 R9, P1, R2, 0x10, RZ ; /* 0x0000001002097810 */
/* 0x000fe40007f3e0ff */
/*06d0*/ IMNMX R8, R8, R11, PT ; /* 0x0000000b08087217 */
/* 0x010fc60003800200 */
/*06e0*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e0603 */
/*06f0*/ IMNMX R5, R8, R13, PT ; /* 0x0000000d08057217 */
/* 0x020fe20003800200 */
/*0700*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0009 */
/*0710*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0720*/ @P0 BRA 0x630 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0730*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0740*/ @!P0 BRA 0x800 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0760*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*0770*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0007 */
/*0790*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*07c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*07d0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*07e0*/ IMNMX R5, R2, R5, PT ; /* 0x0000000502057217 */
/* 0x004fd20003800200 */
/*07f0*/ @P0 BRA 0x770 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0800*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0810*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0820*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5mini1PiS_i
.globl _Z5mini1PiS_i
.p2align 8
.type _Z5mini1PiS_i,@function
_Z5mini1PiS_i:
s_load_b32 s3, s[0:1], 0x10
s_lshl_b32 s4, s15, 8
s_mov_b32 s2, s15
s_mov_b32 s5, 0x785ff8
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s3
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
s_add_i32 s10, s4, 0x100
s_lshl_b64 s[8:9], s[4:5], 2
s_min_i32 s3, s10, s3
s_mov_b32 s5, 0x785ff8
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
.LBB0_2:
s_load_b32 s8, s[6:7], 0x0
s_add_i32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_min_i32 s5, s5, s8
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_ge_i32 s4, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5mini1PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5mini1PiS_i, .Lfunc_end0-_Z5mini1PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5mini1PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z5mini1PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016494a_00000000-6_A1_MIN.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z5mini1PiS_iPiS_i
.type _Z27__device_stub__Z5mini1PiS_iPiS_i, @function
_Z27__device_stub__Z5mini1PiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5mini1PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z5mini1PiS_iPiS_i, .-_Z27__device_stub__Z5mini1PiS_iPiS_i
.globl _Z5mini1PiS_i
.type _Z5mini1PiS_i, @function
_Z5mini1PiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5mini1PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5mini1PiS_i, .-_Z5mini1PiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the size of array"
.LC5:
.string "The minimum element is"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r12
pushq %rbx
subq $64, %rsp
.cfi_offset 12, -24
.cfi_offset 3, -32
movq %fs:40, %rax
movq %rax, -24(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq -76(%rbp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl -76(%rbp), %esi
movslq %esi, %rcx
leaq 15(,%rcx,4), %rax
movq %rax, %rdi
andq $-16, %rdi
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L12:
cmpq %rdx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rdi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %rbx
testl %esi, %esi
jle .L15
movl $1, %eax
.L16:
movl %eax, -4(%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rcx
jne .L16
.L15:
sall $2, %esi
movslq %esi, %r12
leaq -72(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC6(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC2(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L17
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L17:
cvttss2sil %xmm3, %ebx
movslq %ebx, %rsi
salq $2, %rsi
leaq -64(%rbp), %rdi
call cudaMalloc@PLT
movl $1, -56(%rbp)
movl $1, -52(%rbp)
movl $1, -48(%rbp)
cmpl $1, -76(%rbp)
jg .L21
.L18:
leaq -32(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -72(%rbp), %rsi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -32(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -24(%rbp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
leaq -16(%rbp), %rsp
popq %rbx
popq %r12
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L27:
.cfi_restore_state
movl -76(%rbp), %edx
movq -64(%rbp), %rsi
movq -72(%rbp), %rdi
call _Z27__device_stub__Z5mini1PiS_iPiS_i
jmp .L19
.L20:
cvttss2sil %xmm2, %edx
movl %edx, -76(%rbp)
movslq %edx, %rdx
salq $2, %rdx
movl $3, %ecx
movq -64(%rbp), %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $1, -76(%rbp)
jle .L18
.L21:
movl %ebx, -44(%rbp)
movl $1, -40(%rbp)
movl -48(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -56(%rbp), %rdx
movq -44(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC6(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC2(%rip), %xmm5
ucomiss %xmm1, %xmm5
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC4(%rip), %xmm6
andps %xmm6, %xmm2
addss %xmm2, %xmm1
movss .LC6(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z5mini1PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5mini1PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 998244352
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "A1_MIN.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__mini1PiS_i # -- Begin function _Z20__device_stub__mini1PiS_i
.p2align 4, 0x90
.type _Z20__device_stub__mini1PiS_i,@function
_Z20__device_stub__mini1PiS_i: # @_Z20__device_stub__mini1PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5mini1PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__mini1PiS_i, .Lfunc_end0-_Z20__device_stub__mini1PiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq -44(%rbp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq %rsp, -104(%rbp) # 8-byte Spill
movl -44(%rbp), %eax
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%rbx,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB1_6
.LBB1_7: # %._crit_edge
shll $2, %eax
movslq %eax, %r14
leaq -56(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movq -56(%rbp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r14d
movslq %r14d, %rsi
shlq $2, %rsi
leaq -72(%rbp), %rdi
callq hipMalloc
cmpl $2, -44(%rbp)
jl .LBB1_12
# %bb.8: # %.lr.ph24
movabsq $4294967296, %rbx # imm = 0x100000000
movl %r14d, %r14d
orq %rbx, %r14
incq %rbx
leaq -120(%rbp), %r13
leaq -112(%rbp), %r15
leaq -96(%rbp), %r12
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movl %eax, -44(%rbp)
movq -56(%rbp), %rdi
movq -72(%rbp), %rsi
movslq %eax, %rdx
shlq $2, %rdx
movl $3, %ecx
callq hipMemcpy
cmpl $1, -44(%rbp)
jle .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq -56(%rbp), %rax
movq -72(%rbp), %rcx
movl -44(%rbp), %edx
movq %rax, -168(%rbp)
movq %rcx, -160(%rbp)
movl %edx, -60(%rbp)
leaq -168(%rbp), %rax
movq %rax, -96(%rbp)
leaq -160(%rbp), %rax
movq %rax, -88(%rbp)
leaq -60(%rbp), %rax
movq %rax, -80(%rbp)
leaq -152(%rbp), %rdi
leaq -136(%rbp), %rsi
movq %r13, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq -152(%rbp), %rsi
movl -144(%rbp), %edx
movq -136(%rbp), %rcx
movl -128(%rbp), %r8d
movl $_Z5mini1PiS_i, %edi
movq %r12, %r9
pushq -112(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB1_11
.LBB1_12: # %._crit_edge25
movq -56(%rbp), %rsi
leaq -96(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl -96(%rbp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -104(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_17:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5mini1PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5mini1PiS_i,@object # @_Z5mini1PiS_i
.section .rodata,"a",@progbits
.globl _Z5mini1PiS_i
.p2align 3, 0x0
_Z5mini1PiS_i:
.quad _Z20__device_stub__mini1PiS_i
.size _Z5mini1PiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the size of array"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "The minimum element is"
.size .L.str.1, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5mini1PiS_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__mini1PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5mini1PiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
extern "C"
__global__ void kern(int *out)
{
out[0] = 1;
} | code for sm_80
Function : kern
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
extern "C"
__global__ void kern(int *out)
{
out[0] = 1;
} | .file "tmpxft_00052ee1_00000000-6_ptxKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4kernPiPi
.type _Z23__device_stub__Z4kernPiPi, @function
_Z23__device_stub__Z4kernPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kern(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z4kernPiPi, .-_Z23__device_stub__Z4kernPiPi
.globl kern
.type kern, @function
kern:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4kernPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kern, .-kern
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kern"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kern(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
extern "C"
__global__ void kern(int *out)
{
out[0] = 1;
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void kern(int *out)
{
out[0] = 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void kern(int *out)
{
out[0] = 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kern
.globl kern
.p2align 8
.type kern,@function
kern:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kern
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kern, .Lfunc_end0-kern
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kern
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: kern.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void kern(int *out)
{
out[0] = 1;
} | .text
.file "ptxKernel.hip"
.globl __device_stub__kern # -- Begin function __device_stub__kern
.p2align 4, 0x90
.type __device_stub__kern,@function
__device_stub__kern: # @__device_stub__kern
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $kern, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__kern, .Lfunc_end0-__device_stub__kern
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kern, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type kern,@object # @kern
.section .rodata,"a",@progbits
.globl kern
.p2align 3, 0x0
kern:
.quad __device_stub__kern
.size kern, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kern"
.size .L__unnamed_1, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kern
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kern
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : kern
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kern
.globl kern
.p2align 8
.type kern,@function
kern:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kern
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kern, .Lfunc_end0-kern
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kern
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: kern.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00052ee1_00000000-6_ptxKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4kernPiPi
.type _Z23__device_stub__Z4kernPiPi, @function
_Z23__device_stub__Z4kernPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kern(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z4kernPiPi, .-_Z23__device_stub__Z4kernPiPi
.globl kern
.type kern, @function
kern:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4kernPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kern, .-kern
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kern"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kern(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ptxKernel.hip"
.globl __device_stub__kern # -- Begin function __device_stub__kern
.p2align 4, 0x90
.type __device_stub__kern,@function
__device_stub__kern: # @__device_stub__kern
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $kern, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__kern, .Lfunc_end0-__device_stub__kern
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kern, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type kern,@object # @kern
.section .rodata,"a",@progbits
.globl kern
.p2align 3, 0x0
kern:
.quad __device_stub__kern
.size kern, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kern"
.size .L__unnamed_1, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kern
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kern
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include <time.h>
#include <cuda.h>
// Forward Declarations
#define BLOCKSIZE 1024
#ifndef Nsize
#define Nsize 1024
#endif
void printArray(int k);
__global__ void add(int d_a[], int *d_answer);
int* a;
int answer;
int main(){
cudaError_t err;
int deviceCount;
err = cudaGetDeviceCount(&deviceCount);
printf("Device count: %s\n",cudaGetErrorString(err));
printf("There are %d devices\n", deviceCount);
err = cudaSetDevice(0);
printf("Device selection: %s\n",cudaGetErrorString(err));
a = (int*)malloc(Nsize * sizeof(int));
// Fill the array
int i; /* counter */
time_t t;
//srand((unsigned) time(&t));
for(i = 0; i < Nsize; i++)
a[i] = rand() % 23;
printArray(Nsize);
// Allocate space on the GPU
int* d_Array; /* d_ means "device" */
int* d_answer;
err = cudaMalloc(&d_Array, Nsize * sizeof(int));
printf("Malloc device rules: %s\n",cudaGetErrorString(err));
err = cudaMalloc(&d_answer, sizeof(long));
printf("Malloc device rules: %s\n",cudaGetErrorString(err));
// Copy the array to the card
// destination, then source
err = cudaMemcpy(d_Array, a, Nsize * sizeof(int), cudaMemcpyHostToDevice);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
err = cudaMemcpy(d_answer, &answer, sizeof(int), cudaMemcpyHostToDevice);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
// Set up the kernel
int blockSize = BLOCKSIZE;
int numBlocks = 1;
dim3 dimGrid(numBlocks);
dim3 dimBlock(blockSize);
// Launch the kernel
add <<< dimGrid, dimBlock >>> (d_Array, d_answer);
// Retrieve the results from the card
err = cudaMemcpy(&answer, d_answer, sizeof(int), cudaMemcpyDeviceToHost);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
err = cudaMemcpy(a, d_Array, Nsize*sizeof(int), cudaMemcpyDeviceToHost);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
// Inspect the results.
printf("%i\n", answer);
printArray(20);
}
void printArray(int k){
int i;
for(i = 0; i < k; i++)
printf("%d ", a[i]);
printf("\n");
}
__global__ void add(int d_a[], int *d_answer){
int idx = threadIdx.x;
if(idx >= Nsize){
return;
}
__shared__ int a[BLOCKSIZE];
a[idx] = d_a[idx];
__syncthreads();
for (int i = 0; i < (log2f(BLOCKSIZE)); i++){
int neighbor = idx ^ (1<<i);
int his = 0;
if(neighbor >= Nsize){
his = 0;
}
else{
his = a[neighbor];
}
int my = a[idx];
int holder = my + his;
__syncthreads();
a[idx] = holder;
__syncthreads();
}
*d_answer = a[idx];
} | code for sm_80
Function : _Z3addPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R5, 0x3ff, PT ; /* 0x000003ff0500780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0202 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x0000a2000c1e1900 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 1.443359375, -0.2030029296875 ; /* 0x3dc6b27fff007435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R3, 0x34000000 ; /* 0x3400000000037802 */
/* 0x001fd20000000f00 */
/*00a0*/ FFMA R0, RZ, R0, -0.16845393180847167969 ; /* 0xbe2c7f30ff007423 */
/* 0x000fc80000000000 */
/*00b0*/ FFMA R0, RZ, R0, 0.1716887056827545166 ; /* 0x3e2fcf2aff007423 */
/* 0x000fe40000000000 */
/*00c0*/ FFMA R3, R3, 83886080, RZ ; /* 0x4ca0000003037823 */
/* 0x000fe400000000ff */
/*00d0*/ FFMA R0, RZ, R0, -0.17900948226451873779 ; /* 0xbe374e43ff007423 */
/* 0x000fc80000000000 */
/*00e0*/ FFMA R0, RZ, R0, 0.20512372255325317383 ; /* 0x3e520bf4ff007423 */
/* 0x000fc80000000000 */
/*00f0*/ FFMA R0, RZ, R0, -0.24046532809734344482 ; /* 0xbe763c8bff007423 */
/* 0x000fc80000000000 */
/*0100*/ FFMA R0, RZ, R0, 0.28857114911079406738 ; /* 0x3e93bf99ff007423 */
/* 0x000fc80000000000 */
/*0110*/ FFMA R0, RZ, R0, -0.36067417263984680176 ; /* 0xbeb8aa49ff007423 */
/* 0x000fc80000000000 */
/*0120*/ FFMA R0, RZ, R0, 0.48089820146560668945 ; /* 0x3ef6384aff007423 */
/* 0x000fc80000000000 */
/*0130*/ FFMA R0, RZ, R0, -0.72134751081466674805 ; /* 0xbf38aa3bff007423 */
/* 0x000fc80000000000 */
/*0140*/ FMUL R0, RZ, R0 ; /* 0x00000000ff007220 */
/* 0x000fc80000400000 */
/*0150*/ FFMA R0, RZ, 1.4426950216293334961, R0 ; /* 0x3fb8aa3bff007823 */
/* 0x000fca0000000000 */
/*0160*/ FSETP.GT.AND P0, PT, R3, -R0, PT ; /* 0x800000000300720b */
/* 0x000fe20003f04000 */
/*0170*/ FADD R0, R0, R3 ; /* 0x0000000300007221 */
/* 0x000fe20000000000 */
/*0180*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fee0000010000 */
/*01a0*/ @!P0 BRA 0x2b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x001fe40008000000 */
/*01c0*/ UMOV UR8, 0x1 ; /* 0x0000000100087882 */
/* 0x000fc40000000000 */
/*01d0*/ USHF.L.U32 UR5, UR8, UR4, URZ ; /* 0x0000000408057299 */
/* 0x000fe2000800063f */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*01f0*/ LDS R2, [R5.X4] ; /* 0x0000000005027984 */
/* 0x000fe20000004800 */
/*0200*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc6000fffe03f */
/*0210*/ LOP3.LUT R4, R5, UR5, RZ, 0x3c, !PT ; /* 0x0000000505047c12 */
/* 0x000fc8000f8e3cff */
/*0220*/ ISETP.GT.AND P0, PT, R4, 0x3ff, PT ; /* 0x000003ff0400780c */
/* 0x000fda0003f04270 */
/*0230*/ @!P0 LDS R3, [R4.X4] ; /* 0x0000000004038984 */
/* 0x000e240000004800 */
/*0240*/ IADD3 R2, R2, R3, RZ ; /* 0x0000000302027210 */
/* 0x001fe40007ffe0ff */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ I2F R3, UR4 ; /* 0x0000000400037d06 */
/* 0x000e240008201400 */
/*0270*/ FSETP.GT.AND P0, PT, R0, R3, PT ; /* 0x000000030000720b */
/* 0x001fe20003f04000 */
/*0280*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0001e80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*02a0*/ @P0 BRA 0x1d0 ; /* 0xffffff2000000947 */
/* 0x001fea000383ffff */
/*02b0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x001e220000004800 */
/*02c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fc40000000f00 */
/*02d0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include <time.h>
#include <cuda.h>
// Forward Declarations
#define BLOCKSIZE 1024
#ifndef Nsize
#define Nsize 1024
#endif
void printArray(int k);
__global__ void add(int d_a[], int *d_answer);
int* a;
int answer;
int main(){
cudaError_t err;
int deviceCount;
err = cudaGetDeviceCount(&deviceCount);
printf("Device count: %s\n",cudaGetErrorString(err));
printf("There are %d devices\n", deviceCount);
err = cudaSetDevice(0);
printf("Device selection: %s\n",cudaGetErrorString(err));
a = (int*)malloc(Nsize * sizeof(int));
// Fill the array
int i; /* counter */
time_t t;
//srand((unsigned) time(&t));
for(i = 0; i < Nsize; i++)
a[i] = rand() % 23;
printArray(Nsize);
// Allocate space on the GPU
int* d_Array; /* d_ means "device" */
int* d_answer;
err = cudaMalloc(&d_Array, Nsize * sizeof(int));
printf("Malloc device rules: %s\n",cudaGetErrorString(err));
err = cudaMalloc(&d_answer, sizeof(long));
printf("Malloc device rules: %s\n",cudaGetErrorString(err));
// Copy the array to the card
// destination, then source
err = cudaMemcpy(d_Array, a, Nsize * sizeof(int), cudaMemcpyHostToDevice);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
err = cudaMemcpy(d_answer, &answer, sizeof(int), cudaMemcpyHostToDevice);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
// Set up the kernel
int blockSize = BLOCKSIZE;
int numBlocks = 1;
dim3 dimGrid(numBlocks);
dim3 dimBlock(blockSize);
// Launch the kernel
add <<< dimGrid, dimBlock >>> (d_Array, d_answer);
// Retrieve the results from the card
err = cudaMemcpy(&answer, d_answer, sizeof(int), cudaMemcpyDeviceToHost);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
err = cudaMemcpy(a, d_Array, Nsize*sizeof(int), cudaMemcpyDeviceToHost);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
// Inspect the results.
printf("%i\n", answer);
printArray(20);
}
void printArray(int k){
int i;
for(i = 0; i < k; i++)
printf("%d ", a[i]);
printf("\n");
}
__global__ void add(int d_a[], int *d_answer){
int idx = threadIdx.x;
if(idx >= Nsize){
return;
}
__shared__ int a[BLOCKSIZE];
a[idx] = d_a[idx];
__syncthreads();
for (int i = 0; i < (log2f(BLOCKSIZE)); i++){
int neighbor = idx ^ (1<<i);
int his = 0;
if(neighbor >= Nsize){
his = 0;
}
else{
his = a[neighbor];
}
int my = a[idx];
int holder = my + his;
__syncthreads();
a[idx] = holder;
__syncthreads();
}
*d_answer = a[idx];
} | .file "tmpxft_000aa074_00000000-6_butterfly.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z10printArrayi
.type _Z10printArrayi, @function
_Z10printArrayi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %edi, %edi
jle .L4
movslq %edi, %rdi
leaq 0(,%rdi,4), %rbp
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
movq a(%rip), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10printArrayi, .-_Z10printArrayi
.globl _Z24__device_stub__Z3addPiS_PiS_
.type _Z24__device_stub__Z3addPiS_PiS_, @function
_Z24__device_stub__Z3addPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z24__device_stub__Z3addPiS_PiS_, .-_Z24__device_stub__Z3addPiS_PiS_
.globl _Z3addPiS_
.type _Z3addPiS_, @function
_Z3addPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_, .-_Z3addPiS_
.section .rodata.str1.1
.LC2:
.string "Device count: %s\n"
.LC3:
.string "There are %d devices\n"
.LC4:
.string "Device selection: %s\n"
.LC5:
.string "Malloc device rules: %s\n"
.LC6:
.string "cuda memory error: %s\n"
.LC7:
.string "%i\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, a(%rip)
movl $0, %ebx
.L17:
call rand@PLT
movslq %eax, %rdx
imulq $-1307163959, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $4, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $23, %edx, %edx
subl %edx, %eax
movq a(%rip), %rdx
movl %eax, (%rdx,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L17
movl $1024, %edi
call _Z10printArrayi
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4096, %edx
movq a(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4, %edx
leaq answer(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
leaq answer(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
movq a(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl answer(%rip), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $20, %edi
call _Z10printArrayi
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z24__device_stub__Z3addPiS_PiS_
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3addPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl answer
.bss
.align 4
.type answer, @object
.size answer, 4
answer:
.zero 4
.globl a
.align 8
.type a, @object
.size a, 8
a:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include <time.h>
#include <cuda.h>
// Forward Declarations
#define BLOCKSIZE 1024
#ifndef Nsize
#define Nsize 1024
#endif
void printArray(int k);
__global__ void add(int d_a[], int *d_answer);
int* a;
int answer;
int main(){
cudaError_t err;
int deviceCount;
err = cudaGetDeviceCount(&deviceCount);
printf("Device count: %s\n",cudaGetErrorString(err));
printf("There are %d devices\n", deviceCount);
err = cudaSetDevice(0);
printf("Device selection: %s\n",cudaGetErrorString(err));
a = (int*)malloc(Nsize * sizeof(int));
// Fill the array
int i; /* counter */
time_t t;
//srand((unsigned) time(&t));
for(i = 0; i < Nsize; i++)
a[i] = rand() % 23;
printArray(Nsize);
// Allocate space on the GPU
int* d_Array; /* d_ means "device" */
int* d_answer;
err = cudaMalloc(&d_Array, Nsize * sizeof(int));
printf("Malloc device rules: %s\n",cudaGetErrorString(err));
err = cudaMalloc(&d_answer, sizeof(long));
printf("Malloc device rules: %s\n",cudaGetErrorString(err));
// Copy the array to the card
// destination, then source
err = cudaMemcpy(d_Array, a, Nsize * sizeof(int), cudaMemcpyHostToDevice);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
err = cudaMemcpy(d_answer, &answer, sizeof(int), cudaMemcpyHostToDevice);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
// Set up the kernel
int blockSize = BLOCKSIZE;
int numBlocks = 1;
dim3 dimGrid(numBlocks);
dim3 dimBlock(blockSize);
// Launch the kernel
add <<< dimGrid, dimBlock >>> (d_Array, d_answer);
// Retrieve the results from the card
err = cudaMemcpy(&answer, d_answer, sizeof(int), cudaMemcpyDeviceToHost);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
err = cudaMemcpy(a, d_Array, Nsize*sizeof(int), cudaMemcpyDeviceToHost);
printf("cuda memory error: %s\n",cudaGetErrorString(err));
// Inspect the results.
printf("%i\n", answer);
printArray(20);
}
void printArray(int k){
int i;
for(i = 0; i < k; i++)
printf("%d ", a[i]);
printf("\n");
}
__global__ void add(int d_a[], int *d_answer){
int idx = threadIdx.x;
if(idx >= Nsize){
return;
}
__shared__ int a[BLOCKSIZE];
a[idx] = d_a[idx];
__syncthreads();
for (int i = 0; i < (log2f(BLOCKSIZE)); i++){
int neighbor = idx ^ (1<<i);
int his = 0;
if(neighbor >= Nsize){
his = 0;
}
else{
his = a[neighbor];
}
int my = a[idx];
int holder = my + his;
__syncthreads();
a[idx] = holder;
__syncthreads();
}
*d_answer = a[idx];
} | #include<stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
// Forward Declarations
#define BLOCKSIZE 1024
#ifndef Nsize
#define Nsize 1024
#endif
void printArray(int k);
__global__ void add(int d_a[], int *d_answer);
int* a;
int answer;
int main(){
hipError_t err;
int deviceCount;
err = hipGetDeviceCount(&deviceCount);
printf("Device count: %s\n",hipGetErrorString(err));
printf("There are %d devices\n", deviceCount);
err = hipSetDevice(0);
printf("Device selection: %s\n",hipGetErrorString(err));
a = (int*)malloc(Nsize * sizeof(int));
// Fill the array
int i; /* counter */
time_t t;
//srand((unsigned) time(&t));
for(i = 0; i < Nsize; i++)
a[i] = rand() % 23;
printArray(Nsize);
// Allocate space on the GPU
int* d_Array; /* d_ means "device" */
int* d_answer;
err = hipMalloc(&d_Array, Nsize * sizeof(int));
printf("Malloc device rules: %s\n",hipGetErrorString(err));
err = hipMalloc(&d_answer, sizeof(long));
printf("Malloc device rules: %s\n",hipGetErrorString(err));
// Copy the array to the card
// destination, then source
err = hipMemcpy(d_Array, a, Nsize * sizeof(int), hipMemcpyHostToDevice);
printf("cuda memory error: %s\n",hipGetErrorString(err));
err = hipMemcpy(d_answer, &answer, sizeof(int), hipMemcpyHostToDevice);
printf("cuda memory error: %s\n",hipGetErrorString(err));
// Set up the kernel
int blockSize = BLOCKSIZE;
int numBlocks = 1;
dim3 dimGrid(numBlocks);
dim3 dimBlock(blockSize);
// Launch the kernel
add <<< dimGrid, dimBlock >>> (d_Array, d_answer);
// Retrieve the results from the card
err = hipMemcpy(&answer, d_answer, sizeof(int), hipMemcpyDeviceToHost);
printf("cuda memory error: %s\n",hipGetErrorString(err));
err = hipMemcpy(a, d_Array, Nsize*sizeof(int), hipMemcpyDeviceToHost);
printf("cuda memory error: %s\n",hipGetErrorString(err));
// Inspect the results.
printf("%i\n", answer);
printArray(20);
}
void printArray(int k){
int i;
for(i = 0; i < k; i++)
printf("%d ", a[i]);
printf("\n");
}
__global__ void add(int d_a[], int *d_answer){
int idx = threadIdx.x;
if(idx >= Nsize){
return;
}
__shared__ int a[BLOCKSIZE];
a[idx] = d_a[idx];
__syncthreads();
for (int i = 0; i < (log2f(BLOCKSIZE)); i++){
int neighbor = idx ^ (1<<i);
int his = 0;
if(neighbor >= Nsize){
his = 0;
}
else{
his = a[neighbor];
}
int my = a[idx];
int holder = my + his;
__syncthreads();
a[idx] = holder;
__syncthreads();
}
*d_answer = a[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
// Forward Declarations
#define BLOCKSIZE 1024
#ifndef Nsize
#define Nsize 1024
#endif
void printArray(int k);
__global__ void add(int d_a[], int *d_answer);
int* a;
int answer;
int main(){
hipError_t err;
int deviceCount;
err = hipGetDeviceCount(&deviceCount);
printf("Device count: %s\n",hipGetErrorString(err));
printf("There are %d devices\n", deviceCount);
err = hipSetDevice(0);
printf("Device selection: %s\n",hipGetErrorString(err));
a = (int*)malloc(Nsize * sizeof(int));
// Fill the array
int i; /* counter */
time_t t;
//srand((unsigned) time(&t));
for(i = 0; i < Nsize; i++)
a[i] = rand() % 23;
printArray(Nsize);
// Allocate space on the GPU
int* d_Array; /* d_ means "device" */
int* d_answer;
err = hipMalloc(&d_Array, Nsize * sizeof(int));
printf("Malloc device rules: %s\n",hipGetErrorString(err));
err = hipMalloc(&d_answer, sizeof(long));
printf("Malloc device rules: %s\n",hipGetErrorString(err));
// Copy the array to the card
// destination, then source
err = hipMemcpy(d_Array, a, Nsize * sizeof(int), hipMemcpyHostToDevice);
printf("cuda memory error: %s\n",hipGetErrorString(err));
err = hipMemcpy(d_answer, &answer, sizeof(int), hipMemcpyHostToDevice);
printf("cuda memory error: %s\n",hipGetErrorString(err));
// Set up the kernel
int blockSize = BLOCKSIZE;
int numBlocks = 1;
dim3 dimGrid(numBlocks);
dim3 dimBlock(blockSize);
// Launch the kernel
add <<< dimGrid, dimBlock >>> (d_Array, d_answer);
// Retrieve the results from the card
err = hipMemcpy(&answer, d_answer, sizeof(int), hipMemcpyDeviceToHost);
printf("cuda memory error: %s\n",hipGetErrorString(err));
err = hipMemcpy(a, d_Array, Nsize*sizeof(int), hipMemcpyDeviceToHost);
printf("cuda memory error: %s\n",hipGetErrorString(err));
// Inspect the results.
printf("%i\n", answer);
printArray(20);
}
void printArray(int k){
int i;
for(i = 0; i < k; i++)
printf("%d ", a[i]);
printf("\n");
}
__global__ void add(int d_a[], int *d_answer){
int idx = threadIdx.x;
if(idx >= Nsize){
return;
}
__shared__ int a[BLOCKSIZE];
a[idx] = d_a[idx];
__syncthreads();
for (int i = 0; i < (log2f(BLOCKSIZE)); i++){
int neighbor = idx ^ (1<<i);
int his = 0;
if(neighbor >= Nsize){
his = 0;
}
else{
his = a[neighbor];
}
int my = a[idx];
int holder = my + his;
__syncthreads();
a[idx] = holder;
__syncthreads();
}
*d_answer = a[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_
.globl _Z3addPiS_
.p2align 8
.type _Z3addPiS_,@function
_Z3addPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s3
ds_load_b32 v3, v1
s_add_i32 s2, s2, 1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 10
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_2:
s_lshl_b32 s3, 1, s2
v_mov_b32_e32 v2, 0
v_xor_b32_e32 v3, s3, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x400, v3
s_cbranch_execz .LBB0_1
v_lshlrev_b32_e32 v2, 2, v3
ds_load_b32 v2, v2
s_branch .LBB0_1
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v1
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_, .Lfunc_end0-_Z3addPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
// Forward Declarations
#define BLOCKSIZE 1024
#ifndef Nsize
#define Nsize 1024
#endif
void printArray(int k);
__global__ void add(int d_a[], int *d_answer);
int* a;
int answer;
int main(){
hipError_t err;
int deviceCount;
err = hipGetDeviceCount(&deviceCount);
printf("Device count: %s\n",hipGetErrorString(err));
printf("There are %d devices\n", deviceCount);
err = hipSetDevice(0);
printf("Device selection: %s\n",hipGetErrorString(err));
a = (int*)malloc(Nsize * sizeof(int));
// Fill the array
int i; /* counter */
time_t t;
//srand((unsigned) time(&t));
for(i = 0; i < Nsize; i++)
a[i] = rand() % 23;
printArray(Nsize);
// Allocate space on the GPU
int* d_Array; /* d_ means "device" */
int* d_answer;
err = hipMalloc(&d_Array, Nsize * sizeof(int));
printf("Malloc device rules: %s\n",hipGetErrorString(err));
err = hipMalloc(&d_answer, sizeof(long));
printf("Malloc device rules: %s\n",hipGetErrorString(err));
// Copy the array to the card
// destination, then source
err = hipMemcpy(d_Array, a, Nsize * sizeof(int), hipMemcpyHostToDevice);
printf("cuda memory error: %s\n",hipGetErrorString(err));
err = hipMemcpy(d_answer, &answer, sizeof(int), hipMemcpyHostToDevice);
printf("cuda memory error: %s\n",hipGetErrorString(err));
// Set up the kernel
int blockSize = BLOCKSIZE;
int numBlocks = 1;
dim3 dimGrid(numBlocks);
dim3 dimBlock(blockSize);
// Launch the kernel
add <<< dimGrid, dimBlock >>> (d_Array, d_answer);
// Retrieve the results from the card
err = hipMemcpy(&answer, d_answer, sizeof(int), hipMemcpyDeviceToHost);
printf("cuda memory error: %s\n",hipGetErrorString(err));
err = hipMemcpy(a, d_Array, Nsize*sizeof(int), hipMemcpyDeviceToHost);
printf("cuda memory error: %s\n",hipGetErrorString(err));
// Inspect the results.
printf("%i\n", answer);
printArray(20);
}
void printArray(int k){
int i;
for(i = 0; i < k; i++)
printf("%d ", a[i]);
printf("\n");
}
__global__ void add(int d_a[], int *d_answer){
int idx = threadIdx.x;
if(idx >= Nsize){
return;
}
__shared__ int a[BLOCKSIZE];
a[idx] = d_a[idx];
__syncthreads();
for (int i = 0; i < (log2f(BLOCKSIZE)); i++){
int neighbor = idx ^ (1<<i);
int his = 0;
if(neighbor >= Nsize){
his = 0;
}
else{
his = a[neighbor];
}
int my = a[idx];
int holder = my + his;
__syncthreads();
a[idx] = holder;
__syncthreads();
}
*d_answer = a[idx];
} | .text
.file "butterfly.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
leaq 28(%rsp), %rdi
callq hipGetDeviceCount
movl %eax, %edi
callq hipGetErrorString
xorl %ebx, %ebx
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl 28(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, a(%rip)
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-1307163959, %rax, %rcx # imm = 0xB21642C9
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $4, %ecx
addl %edx, %ecx
leal (%rcx,%rcx,2), %edx
shll $3, %edx
subl %edx, %ecx
addl %eax, %ecx
movq a(%rip), %rax
movl %ecx, (%rax,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_1
# %bb.2: # %.lr.ph.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq a(%rip), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_3
# %bb.4: # %_Z10printArrayi.exit
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
movq a(%rip), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $answer, %esi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq 8(%rsp), %rsi
movl $answer, %edi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq a(%rip), %rdi
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl answer(%rip), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_7: # %.lr.ph.i20
# =>This Inner Loop Header: Depth=1
movq a(%rip), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $20, %rbx
jne .LBB0_7
# %bb.8: # %_Z10printArrayi.exit25
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z10printArrayi # -- Begin function _Z10printArrayi
.p2align 4, 0x90
.type _Z10printArrayi,@function
_Z10printArrayi: # @_Z10printArrayi
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq a(%rip), %rax
movl (%rax,%r14,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %rbx
jne .LBB1_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB1_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z10printArrayi, .Lfunc_end1-_Z10printArrayi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_ # -- Begin function _Z18__device_stub__addPiS_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_,@function
_Z18__device_stub__addPiS_: # @_Z18__device_stub__addPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z18__device_stub__addPiS_, .Lfunc_end2-_Z18__device_stub__addPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type a,@object # @a
.bss
.globl a
.p2align 3, 0x0
a:
.quad 0
.size a, 8
.type answer,@object # @answer
.globl answer
.p2align 2, 0x0
answer:
.long 0 # 0x0
.size answer, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device count: %s\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "There are %d devices\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device selection: %s\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Malloc device rules: %s\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cuda memory error: %s\n"
.size .L.str.4, 23
.type _Z3addPiS_,@object # @_Z3addPiS_
.section .rodata,"a",@progbits
.globl _Z3addPiS_
.p2align 3, 0x0
_Z3addPiS_:
.quad _Z18__device_stub__addPiS_
.size _Z3addPiS_, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "%i\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym answer
.addrsig_sym _Z3addPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R5, 0x3ff, PT ; /* 0x000003ff0500780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0202 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x0000a2000c1e1900 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 1.443359375, -0.2030029296875 ; /* 0x3dc6b27fff007435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R3, 0x34000000 ; /* 0x3400000000037802 */
/* 0x001fd20000000f00 */
/*00a0*/ FFMA R0, RZ, R0, -0.16845393180847167969 ; /* 0xbe2c7f30ff007423 */
/* 0x000fc80000000000 */
/*00b0*/ FFMA R0, RZ, R0, 0.1716887056827545166 ; /* 0x3e2fcf2aff007423 */
/* 0x000fe40000000000 */
/*00c0*/ FFMA R3, R3, 83886080, RZ ; /* 0x4ca0000003037823 */
/* 0x000fe400000000ff */
/*00d0*/ FFMA R0, RZ, R0, -0.17900948226451873779 ; /* 0xbe374e43ff007423 */
/* 0x000fc80000000000 */
/*00e0*/ FFMA R0, RZ, R0, 0.20512372255325317383 ; /* 0x3e520bf4ff007423 */
/* 0x000fc80000000000 */
/*00f0*/ FFMA R0, RZ, R0, -0.24046532809734344482 ; /* 0xbe763c8bff007423 */
/* 0x000fc80000000000 */
/*0100*/ FFMA R0, RZ, R0, 0.28857114911079406738 ; /* 0x3e93bf99ff007423 */
/* 0x000fc80000000000 */
/*0110*/ FFMA R0, RZ, R0, -0.36067417263984680176 ; /* 0xbeb8aa49ff007423 */
/* 0x000fc80000000000 */
/*0120*/ FFMA R0, RZ, R0, 0.48089820146560668945 ; /* 0x3ef6384aff007423 */
/* 0x000fc80000000000 */
/*0130*/ FFMA R0, RZ, R0, -0.72134751081466674805 ; /* 0xbf38aa3bff007423 */
/* 0x000fc80000000000 */
/*0140*/ FMUL R0, RZ, R0 ; /* 0x00000000ff007220 */
/* 0x000fc80000400000 */
/*0150*/ FFMA R0, RZ, 1.4426950216293334961, R0 ; /* 0x3fb8aa3bff007823 */
/* 0x000fca0000000000 */
/*0160*/ FSETP.GT.AND P0, PT, R3, -R0, PT ; /* 0x800000000300720b */
/* 0x000fe20003f04000 */
/*0170*/ FADD R0, R0, R3 ; /* 0x0000000300007221 */
/* 0x000fe20000000000 */
/*0180*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fee0000010000 */
/*01a0*/ @!P0 BRA 0x2b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x001fe40008000000 */
/*01c0*/ UMOV UR8, 0x1 ; /* 0x0000000100087882 */
/* 0x000fc40000000000 */
/*01d0*/ USHF.L.U32 UR5, UR8, UR4, URZ ; /* 0x0000000408057299 */
/* 0x000fe2000800063f */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*01f0*/ LDS R2, [R5.X4] ; /* 0x0000000005027984 */
/* 0x000fe20000004800 */
/*0200*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc6000fffe03f */
/*0210*/ LOP3.LUT R4, R5, UR5, RZ, 0x3c, !PT ; /* 0x0000000505047c12 */
/* 0x000fc8000f8e3cff */
/*0220*/ ISETP.GT.AND P0, PT, R4, 0x3ff, PT ; /* 0x000003ff0400780c */
/* 0x000fda0003f04270 */
/*0230*/ @!P0 LDS R3, [R4.X4] ; /* 0x0000000004038984 */
/* 0x000e240000004800 */
/*0240*/ IADD3 R2, R2, R3, RZ ; /* 0x0000000302027210 */
/* 0x001fe40007ffe0ff */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ I2F R3, UR4 ; /* 0x0000000400037d06 */
/* 0x000e240008201400 */
/*0270*/ FSETP.GT.AND P0, PT, R0, R3, PT ; /* 0x000000030000720b */
/* 0x001fe20003f04000 */
/*0280*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0001e80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*02a0*/ @P0 BRA 0x1d0 ; /* 0xffffff2000000947 */
/* 0x001fea000383ffff */
/*02b0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x001e220000004800 */
/*02c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fc40000000f00 */
/*02d0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_
.globl _Z3addPiS_
.p2align 8
.type _Z3addPiS_,@function
_Z3addPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s3
ds_load_b32 v3, v1
s_add_i32 s2, s2, 1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 10
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_2:
s_lshl_b32 s3, 1, s2
v_mov_b32_e32 v2, 0
v_xor_b32_e32 v3, s3, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x400, v3
s_cbranch_execz .LBB0_1
v_lshlrev_b32_e32 v2, 2, v3
ds_load_b32 v2, v2
s_branch .LBB0_1
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v1
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_, .Lfunc_end0-_Z3addPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aa074_00000000-6_butterfly.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z10printArrayi
.type _Z10printArrayi, @function
_Z10printArrayi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %edi, %edi
jle .L4
movslq %edi, %rdi
leaq 0(,%rdi,4), %rbp
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
movq a(%rip), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10printArrayi, .-_Z10printArrayi
.globl _Z24__device_stub__Z3addPiS_PiS_
.type _Z24__device_stub__Z3addPiS_PiS_, @function
_Z24__device_stub__Z3addPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z24__device_stub__Z3addPiS_PiS_, .-_Z24__device_stub__Z3addPiS_PiS_
.globl _Z3addPiS_
.type _Z3addPiS_, @function
_Z3addPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_, .-_Z3addPiS_
.section .rodata.str1.1
.LC2:
.string "Device count: %s\n"
.LC3:
.string "There are %d devices\n"
.LC4:
.string "Device selection: %s\n"
.LC5:
.string "Malloc device rules: %s\n"
.LC6:
.string "cuda memory error: %s\n"
.LC7:
.string "%i\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, a(%rip)
movl $0, %ebx
.L17:
call rand@PLT
movslq %eax, %rdx
imulq $-1307163959, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $4, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $23, %edx, %edx
subl %edx, %eax
movq a(%rip), %rdx
movl %eax, (%rdx,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L17
movl $1024, %edi
call _Z10printArrayi
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4096, %edx
movq a(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4, %edx
leaq answer(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
leaq answer(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
movq a(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl answer(%rip), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $20, %edi
call _Z10printArrayi
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z24__device_stub__Z3addPiS_PiS_
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3addPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl answer
.bss
.align 4
.type answer, @object
.size answer, 4
answer:
.zero 4
.globl a
.align 8
.type a, @object
.size a, 8
a:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "butterfly.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
leaq 28(%rsp), %rdi
callq hipGetDeviceCount
movl %eax, %edi
callq hipGetErrorString
xorl %ebx, %ebx
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl 28(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, a(%rip)
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-1307163959, %rax, %rcx # imm = 0xB21642C9
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $4, %ecx
addl %edx, %ecx
leal (%rcx,%rcx,2), %edx
shll $3, %edx
subl %edx, %ecx
addl %eax, %ecx
movq a(%rip), %rax
movl %ecx, (%rax,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_1
# %bb.2: # %.lr.ph.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq a(%rip), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_3
# %bb.4: # %_Z10printArrayi.exit
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
movq a(%rip), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $answer, %esi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq 8(%rsp), %rsi
movl $answer, %edi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq a(%rip), %rdi
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl answer(%rip), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_7: # %.lr.ph.i20
# =>This Inner Loop Header: Depth=1
movq a(%rip), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $20, %rbx
jne .LBB0_7
# %bb.8: # %_Z10printArrayi.exit25
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z10printArrayi # -- Begin function _Z10printArrayi
.p2align 4, 0x90
.type _Z10printArrayi,@function
_Z10printArrayi: # @_Z10printArrayi
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq a(%rip), %rax
movl (%rax,%r14,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %rbx
jne .LBB1_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB1_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z10printArrayi, .Lfunc_end1-_Z10printArrayi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_ # -- Begin function _Z18__device_stub__addPiS_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_,@function
_Z18__device_stub__addPiS_: # @_Z18__device_stub__addPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z18__device_stub__addPiS_, .Lfunc_end2-_Z18__device_stub__addPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type a,@object # @a
.bss
.globl a
.p2align 3, 0x0
a:
.quad 0
.size a, 8
.type answer,@object # @answer
.globl answer
.p2align 2, 0x0
answer:
.long 0 # 0x0
.size answer, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device count: %s\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "There are %d devices\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device selection: %s\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Malloc device rules: %s\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cuda memory error: %s\n"
.size .L.str.4, 23
.type _Z3addPiS_,@object # @_Z3addPiS_
.section .rodata,"a",@progbits
.globl _Z3addPiS_
.p2align 3, 0x0
_Z3addPiS_:
.quad _Z18__device_stub__addPiS_
.size _Z3addPiS_, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "%i\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym answer
.addrsig_sym _Z3addPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <ctime>
#include <iostream>
#include <iomanip>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
#define THREADPERWARP 32
#define SMNUM 80
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS]; /* values at time t */
float *cudaValues;
int cudaArraySize;
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, tmp;
/* Calculate initial values based on sine curve */
//float fac = 2.0 * PI;
float fac = 6.2831853;
//k = 0.0;
tmp = tpoints - 1;
for (j = 0; j < tpoints; ++j) {
x = static_cast<float>(j)/tmp;
values[j] = sin (fac * x);
}
/* Initialize old values array */
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
printf("0.0000 ");
for (i = 1; i < tpoints; ++i) {
printf("%6.4f ", values[i]);
if (i%10 == 9)
printf("\n");
}
}
__global__ void cudaExecute(float* cudaAns,int howMany,int tpoints,int tIteration)
{
float cudaValues,cudaOld,cudaNew;
double cudaTwiceValue;
double valuePar = 2.0 - static_cast<float>(0.09) * 2.0;
for(int block=0;block<howMany;++block)
{
int ansIndex=block*(SMNUM*THREADPERWARP) + blockIdx.x*blockDim.x + threadIdx.x;
cudaValues = cudaAns[ansIndex];
cudaOld = cudaValues;
for(int iter=0;iter<tIteration;++iter)
{
cudaTwiceValue = valuePar * cudaValues;
cudaNew = (cudaTwiceValue) - cudaOld;
//cudaNew = (2.0 * cudaValues)
// - cudaOld
// + (static_cast<float>(0.09) * (-2.0)*cudaValues);
cudaOld=cudaValues;
cudaValues=cudaNew;
}
cudaAns[ansIndex]=cudaValues;
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
int howManyBlock=tpoints/(SMNUM*THREADPERWARP);
if(tpoints%(SMNUM*THREADPERWARP)!=0)
++howManyBlock;
cudaArraySize = tpoints*sizeof(float);
printf("Initializing points on the line...\n");
cudaMalloc((void**)&cudaValues,cudaArraySize);
init_line();
cudaMemcpy(cudaValues,values,cudaArraySize,cudaMemcpyHostToDevice);
cudaExecute<<<SMNUM,THREADPERWARP>>>(cudaValues,howManyBlock,tpoints,nsteps);
cudaMemcpy(values,cudaValues,cudaArraySize-4,cudaMemcpyDeviceToHost);
//update();
printf("Updating all points for all time steps...\n");
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} | code for sm_80
Function : _Z11cudaExecutePfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fda0003f01270 */
/*0050*/ @P0 BRA 0xe0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R0, R0, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc00007812 */
/* 0x000fc800078ec0ff */
/*00a0*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xa0 ; /* 0xffffffc000007947 */
/* 0x000fea000383ffff */
/*00e0*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0120*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0130*/ LOP3.LUT R18, R4.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304127812 */
/* 0x040fe400078ec0ff */
/*0140*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0150*/ IADD3 R6, -R18, c[0x0][0x170], RZ ; /* 0x00005c0012067a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ IMAD R5, R2, c[0x0][0x0], R5 ; /* 0x0000000002057a24 */
/* 0x001fc400078e0205 */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x002fe400078e00ff */
/*0180*/ IMAD R2, R0, 0xa00, R5 ; /* 0x00000a0000027824 */
/* 0x000fc800078e0205 */
/*0190*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*01a0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*01c0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f26270 */
/*01e0*/ IMAD.MOV.U32 R19, RZ, RZ, R8 ; /* 0x000000ffff137224 */
/* 0x004fcc00078e0008 */
/*01f0*/ @!P0 BRA 0x8b0 ; /* 0x000006b000008947 */
/* 0x001fea0003800000 */
/*0200*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0210*/ IMAD.MOV.U32 R19, RZ, RZ, R8 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0008 */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fd400078e0006 */
/*0230*/ @!P0 BRA 0x7b0 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.GT.AND P2, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f44270 */
/*0250*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0260*/ @!P2 BRA 0x5c0 ; /* 0x000003500000a947 */
/* 0x000fea0003800000 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0280*/ F2F.F64.F32 R10, R19 ; /* 0x00000013000a7310 */
/* 0x002fe20000201800 */
/*0290*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc80007ffe0ff */
/*02a0*/ ISETP.GT.AND P2, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fc60003f44270 */
/*02b0*/ F2F.F64.F32 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e240000201800 */
/*02c0*/ DFMA R12, R10, c[0x2][0x0], -R8 ; /* 0x008000000a0c7a2b */
/* 0x001e140000000808 */
/*02d0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*02e0*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*02f0*/ DFMA R10, R14, c[0x2][0x0], -R10 ; /* 0x008000000e0a7a2b */
/* 0x001e14000000080a */
/*0300*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*0310*/ F2F.F64.F32 R16, R10 ; /* 0x0000000a00107310 */
/* 0x001e240000201800 */
/*0320*/ DFMA R14, R16, c[0x2][0x0], -R14 ; /* 0x00800000100e7a2b */
/* 0x001e14000000080e */
/*0330*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e300000301000 */
/*0340*/ F2F.F64.F32 R20, R14 ; /* 0x0000000e00147310 */
/* 0x001e240000201800 */
/*0350*/ DFMA R16, R20, c[0x2][0x0], -R16 ; /* 0x0080000014107a2b */
/* 0x001e140000000810 */
/*0360*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*0370*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x001e240000201800 */
/*0380*/ DFMA R20, R8, c[0x2][0x0], -R20 ; /* 0x0080000008147a2b */
/* 0x001e140000000814 */
/*0390*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x001e300000301000 */
/*03a0*/ F2F.F64.F32 R12, R20 ; /* 0x00000014000c7310 */
/* 0x001e240000201800 */
/*03b0*/ DFMA R8, R12, c[0x2][0x0], -R8 ; /* 0x008000000c087a2b */
/* 0x001e140000000808 */
/*03c0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e300000301000 */
/*03d0*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */
/* 0x001e240000201800 */
/*03e0*/ DFMA R12, R10, c[0x2][0x0], -R12 ; /* 0x008000000a0c7a2b */
/* 0x001e14000000080c */
/*03f0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*0400*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0410*/ DFMA R10, R14, c[0x2][0x0], -R10 ; /* 0x008000000e0a7a2b */
/* 0x001e0c000000080a */
/*0420*/ F2F.F32.F64 R19, R10 ; /* 0x0000000a00137310 */
/* 0x001e300000301000 */
/*0430*/ F2F.F64.F32 R16, R19 ; /* 0x0000001300107310 */
/* 0x001e240000201800 */
/*0440*/ DFMA R14, R16, c[0x2][0x0], -R14 ; /* 0x00800000100e7a2b */
/* 0x001e14000000080e */
/*0450*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e300000301000 */
/*0460*/ F2F.F64.F32 R20, R14 ; /* 0x0000000e00147310 */
/* 0x001e240000201800 */
/*0470*/ DFMA R16, R20, c[0x2][0x0], -R16 ; /* 0x0080000014107a2b */
/* 0x001e0c0000000810 */
/*0480*/ F2F.F32.F64 R22, R16 ; /* 0x0000001000167310 */
/* 0x001e300000301000 */
/*0490*/ F2F.F64.F32 R8, R22 ; /* 0x0000001600087310 */
/* 0x001e240000201800 */
/*04a0*/ DFMA R20, R8, c[0x2][0x0], -R20 ; /* 0x0080000008147a2b */
/* 0x001e140000000814 */
/*04b0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x001e300000301000 */
/*04c0*/ F2F.F64.F32 R12, R20 ; /* 0x00000014000c7310 */
/* 0x001e240000201800 */
/*04d0*/ DFMA R10, R12, c[0x2][0x0], -R8 ; /* 0x008000000c0a7a2b */
/* 0x001e140000000808 */
/*04e0*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*04f0*/ F2F.F64.F32 R8, R10 ; /* 0x0000000a00087310 */
/* 0x001e240000201800 */
/*0500*/ DFMA R12, R8, c[0x2][0x0], -R12 ; /* 0x00800000080c7a2b */
/* 0x001e14000000080c */
/*0510*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*0520*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0530*/ DFMA R16, R14, c[0x2][0x0], -R8 ; /* 0x008000000e107a2b */
/* 0x001e140000000808 */
/*0540*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*0550*/ F2F.F64.F32 R22, R16 ; /* 0x0000001000167310 */
/* 0x001e240000201800 */
/*0560*/ DFMA R8, R22, c[0x2][0x0], -R14 ; /* 0x0080000016087a2b */
/* 0x001e14000000080e */
/*0570*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e300000301000 */
/*0580*/ F2F.F64.F32 R14, R8 ; /* 0x00000008000e7310 */
/* 0x001e240000201800 */
/*0590*/ DFMA R14, R14, c[0x2][0x0], -R22 ; /* 0x008000000e0e7a2b */
/* 0x001e0c0000000816 */
/*05a0*/ F2F.F32.F64 R19, R14 ; /* 0x0000000e00137310 */
/* 0x0010620000301000 */
/*05b0*/ @P2 BRA 0x280 ; /* 0xfffffcc000002947 */
/* 0x000fea000383ffff */
/*05c0*/ ISETP.GT.AND P2, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f44270 */
/*05d0*/ @!P2 BRA 0x790 ; /* 0x000001b00000a947 */
/* 0x000fea0003800000 */
/*05e0*/ F2F.F64.F32 R10, R19 ; /* 0x00000013000a7310 */
/* 0x002fe20000201800 */
/*05f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0600*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fca0007ffe0ff */
/*0610*/ F2F.F64.F32 R8, R8 ; /* 0x0000000800087310 */
/* 0x000e640000201800 */
/*0620*/ DFMA R12, R10, c[0x2][0x0], -R8 ; /* 0x008000000a0c7a2b */
/* 0x002e540000000808 */
/*0630*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x002e700000301000 */
/*0640*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x003e240000201800 */
/*0650*/ DFMA R10, R14, c[0x2][0x0], -R10 ; /* 0x008000000e0a7a2b */
/* 0x001e0c000000080a */
/*0660*/ F2F.F32.F64 R22, R10 ; /* 0x0000000a00167310 */
/* 0x001e300000301000 */
/*0670*/ F2F.F64.F32 R16, R22 ; /* 0x0000001600107310 */
/* 0x001e240000201800 */
/*0680*/ DFMA R14, R16, c[0x2][0x0], -R14 ; /* 0x00800000100e7a2b */
/* 0x001e14000000080e */
/*0690*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e300000301000 */
/*06a0*/ F2F.F64.F32 R20, R14 ; /* 0x0000000e00147310 */
/* 0x001e240000201800 */
/*06b0*/ DFMA R16, R20, c[0x2][0x0], -R16 ; /* 0x0080000014107a2b */
/* 0x001e140000000810 */
/*06c0*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*06d0*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x001e240000201800 */
/*06e0*/ DFMA R20, R8, c[0x2][0x0], -R20 ; /* 0x0080000008147a2b */
/* 0x001e140000000814 */
/*06f0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x001e300000301000 */
/*0700*/ F2F.F64.F32 R12, R20 ; /* 0x00000014000c7310 */
/* 0x001e240000201800 */
/*0710*/ DFMA R10, R12, c[0x2][0x0], -R8 ; /* 0x008000000c0a7a2b */
/* 0x001e140000000808 */
/*0720*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*0730*/ F2F.F64.F32 R22, R10 ; /* 0x0000000a00167310 */
/* 0x001e240000201800 */
/*0740*/ DFMA R8, R22, c[0x2][0x0], -R12 ; /* 0x0080000016087a2b */
/* 0x001e14000000080c */
/*0750*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e300000301000 */
/*0760*/ F2F.F64.F32 R12, R8 ; /* 0x00000008000c7310 */
/* 0x001e240000201800 */
/*0770*/ DFMA R12, R12, c[0x2][0x0], -R22 ; /* 0x008000000c0c7a2b */
/* 0x001e0c0000000816 */
/*0780*/ F2F.F32.F64 R19, R12 ; /* 0x0000000c00137310 */
/* 0x00106a0000301000 */
/*0790*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*07a0*/ @!P0 BRA 0x8b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*07b0*/ F2F.F64.F32 R10, R19 ; /* 0x00000013000a7310 */
/* 0x002fe20000201800 */
/*07c0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*07d0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f05270 */
/*07e0*/ F2F.F64.F32 R8, R8 ; /* 0x0000000800087310 */
/* 0x000e640000201800 */
/*07f0*/ DFMA R12, R10, c[0x2][0x0], -R8 ; /* 0x008000000a0c7a2b */
/* 0x003e140000000808 */
/*0800*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*0810*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0820*/ DFMA R10, R14, c[0x2][0x0], -R10 ; /* 0x008000000e0a7a2b */
/* 0x001e14000000080a */
/*0830*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*0840*/ F2F.F64.F32 R16, R10 ; /* 0x0000000a00107310 */
/* 0x001e240000201800 */
/*0850*/ DFMA R14, R16, c[0x2][0x0], -R14 ; /* 0x00800000100e7a2b */
/* 0x001e0c000000080e */
/*0860*/ F2F.F32.F64 R8, R14 ; /* 0x0000000e00087310 */
/* 0x001e300000301000 */
/*0870*/ F2F.F64.F32 R20, R8 ; /* 0x0000000800147310 */
/* 0x001e240000201800 */
/*0880*/ DFMA R20, R20, c[0x2][0x0], -R16 ; /* 0x0080000014147a2b */
/* 0x001e0c0000000810 */
/*0890*/ F2F.F32.F64 R19, R20 ; /* 0x0000001400137310 */
/* 0x0010640000301000 */
/*08a0*/ @P0 BRA 0x7b0 ; /* 0xffffff0000000947 */
/* 0x003fea000383ffff */
/*08b0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fda0003f05270 */
/*08c0*/ @!P0 BRA 0x9a0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08d0*/ F2F.F64.F32 R12, R19 ; /* 0x00000013000c7310 */
/* 0x003fe20000201800 */
/*08e0*/ ISETP.NE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fce0003f05270 */
/*08f0*/ F2F.F64.F32 R8, R8 ; /* 0x0000000800087310 */
/* 0x000e240000201800 */
/*0900*/ DFMA R10, R12, c[0x2][0x0], -R8 ; /* 0x008000000c0a7a2b */
/* 0x001e0c0000000808 */
/*0910*/ F2F.F32.F64 R19, R10 ; /* 0x0000000a00137310 */
/* 0x0010620000301000 */
/*0920*/ @!P0 BRA 0x9a0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0930*/ F2F.F64.F32 R10, R19 ; /* 0x00000013000a7310 */
/* 0x003e220000201800 */
/*0940*/ ISETP.NE.AND P0, PT, R18, 0x2, PT ; /* 0x000000021200780c */
/* 0x000fe20003f05270 */
/*0950*/ DFMA R8, R10, c[0x2][0x0], -R12 ; /* 0x008000000a087a2b */
/* 0x001e0c000000080c */
/*0960*/ F2F.F32.F64 R19, R8 ; /* 0x0000000800137310 */
/* 0x001e300000301000 */
/*0970*/ @P0 F2F.F64.F32 R12, R19 ; /* 0x00000013000c0310 */
/* 0x001e240000201800 */
/*0980*/ @P0 DFMA R10, R12, c[0x2][0x0], -R10 ; /* 0x008000000c0a0a2b */
/* 0x001e0c000000080a */
/*0990*/ @P0 F2F.F32.F64 R19, R10 ; /* 0x0000000a00130310 */
/* 0x00106a0000301000 */
/*09a0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0023e2000c101904 */
/*09b0*/ @!P1 BRA 0x170 ; /* 0xfffff7b000009947 */
/* 0x000fea000383ffff */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ BRA 0x9d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <ctime>
#include <iostream>
#include <iomanip>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
#define THREADPERWARP 32
#define SMNUM 80
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS]; /* values at time t */
float *cudaValues;
int cudaArraySize;
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, tmp;
/* Calculate initial values based on sine curve */
//float fac = 2.0 * PI;
float fac = 6.2831853;
//k = 0.0;
tmp = tpoints - 1;
for (j = 0; j < tpoints; ++j) {
x = static_cast<float>(j)/tmp;
values[j] = sin (fac * x);
}
/* Initialize old values array */
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
printf("0.0000 ");
for (i = 1; i < tpoints; ++i) {
printf("%6.4f ", values[i]);
if (i%10 == 9)
printf("\n");
}
}
__global__ void cudaExecute(float* cudaAns,int howMany,int tpoints,int tIteration)
{
float cudaValues,cudaOld,cudaNew;
double cudaTwiceValue;
double valuePar = 2.0 - static_cast<float>(0.09) * 2.0;
for(int block=0;block<howMany;++block)
{
int ansIndex=block*(SMNUM*THREADPERWARP) + blockIdx.x*blockDim.x + threadIdx.x;
cudaValues = cudaAns[ansIndex];
cudaOld = cudaValues;
for(int iter=0;iter<tIteration;++iter)
{
cudaTwiceValue = valuePar * cudaValues;
cudaNew = (cudaTwiceValue) - cudaOld;
//cudaNew = (2.0 * cudaValues)
// - cudaOld
// + (static_cast<float>(0.09) * (-2.0)*cudaValues);
cudaOld=cudaValues;
cudaValues=cudaNew;
}
cudaAns[ansIndex]=cudaValues;
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
int howManyBlock=tpoints/(SMNUM*THREADPERWARP);
if(tpoints%(SMNUM*THREADPERWARP)!=0)
++howManyBlock;
cudaArraySize = tpoints*sizeof(float);
printf("Initializing points on the line...\n");
cudaMalloc((void**)&cudaValues,cudaArraySize);
init_line();
cudaMemcpy(cudaValues,values,cudaArraySize,cudaMemcpyHostToDevice);
cudaExecute<<<SMNUM,THREADPERWARP>>>(cudaValues,howManyBlock,tpoints,nsteps);
cudaMemcpy(values,cudaValues,cudaArraySize-4,cudaMemcpyDeviceToHost);
//update();
printf("Updating all points for all time steps...\n");
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} | .file "tmpxft_001b4640_00000000-6_wave.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s"
.section .rodata.str1.8
.align 8
.LC2:
.string "Invalid. Please enter value between %d and %d\n"
.align 8
.LC3:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC4:
.string "Invalid. Please enter value between 1 and %d\n"
.align 8
.LC5:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z11check_paramv
.type _Z11check_paramv, @function
_Z11check_paramv:
.LFB3949:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L5:
movl tpoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L14
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, tpoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L5
movl $1000000, %ecx
movl $20, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L14:
leaq .LC3(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L8:
movl nsteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L15
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, nsteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L8
movl $1000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L15:
movl tpoints(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size _Z11check_paramv, .-_Z11check_paramv
.globl _Z9init_linev
.type _Z9init_linev, @function
_Z9init_linev:
.LFB3950:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movl tpoints(%rip), %ebp
leal -1(%rbp), %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
movss %xmm2, 12(%rsp)
testl %ebp, %ebp
jle .L17
movslq %ebp, %rbp
movl $0, %ebx
leaq values(%rip), %r12
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
divss 12(%rsp), %xmm0
mulss .LC6(%rip), %xmm0
call sinf@PLT
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L19
.L17:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _Z9init_linev, .-_Z9init_linev
.section .rodata.str1.1
.LC7:
.string "0.0000 "
.LC8:
.string "%6.4f "
.LC9:
.string "\n"
.text
.globl _Z10printfinalv
.type _Z10printfinalv, @function
_Z10printfinalv:
.LFB3951:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $1, tpoints(%rip)
jle .L22
movl $1, %ebx
leaq values(%rip), %r12
leaq .LC8(%rip), %rbp
leaq .LC9(%rip), %r13
jmp .L25
.L24:
addq $1, %rbx
cmpl %ebx, tpoints(%rip)
jle .L22
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9, %edx
jne .L24
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L22:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _Z10printfinalv, .-_Z10printfinalv
.globl _Z34__device_stub__Z11cudaExecutePfiiiPfiii
.type _Z34__device_stub__Z11cudaExecutePfiiiPfiii, @function
_Z34__device_stub__Z11cudaExecutePfiiiPfiii:
.LFB3977:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11cudaExecutePfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z34__device_stub__Z11cudaExecutePfiiiPfiii, .-_Z34__device_stub__Z11cudaExecutePfiiiPfiii
.globl _Z11cudaExecutePfiii
.type _Z11cudaExecutePfiii, @function
_Z11cudaExecutePfiii:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11cudaExecutePfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z11cudaExecutePfiii, .-_Z11cudaExecutePfiii
.section .rodata.str1.1
.LC10:
.string "%d"
.section .rodata.str1.8
.align 8
.LC11:
.string "Initializing points on the line...\n"
.align 8
.LC12:
.string "Updating all points for all time steps...\n"
.section .rodata.str1.1
.LC13:
.string "Printing final results...\n"
.LC14:
.string "\nDone.\n\n"
.text
.globl main
.type main, @function
main:
.LFB3952:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq tpoints(%rip), %rdx
leaq .LC10(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq nsteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
call _Z11check_paramv
movl tpoints(%rip), %eax
movslq %eax, %rbx
imulq $1717986919, %rbx, %rbx
sarq $42, %rbx
cltd
subl %edx, %ebx
leal (%rbx,%rbx,4), %edx
sall $9, %edx
movl %eax, %ecx
subl %edx, %ecx
cmpl $1, %ecx
sbbl $-1, %ebx
sall $2, %eax
movl %eax, cudaArraySize(%rip)
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq cudaArraySize(%rip), %rsi
leaq cudaValues(%rip), %rdi
call cudaMalloc@PLT
call _Z9init_linev
movslq cudaArraySize(%rip), %rdx
movl $1, %ecx
leaq values(%rip), %rsi
movq cudaValues(%rip), %rdi
call cudaMemcpy@PLT
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $80, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L38:
movl cudaArraySize(%rip), %eax
leal -4(%rax), %edx
movslq %edx, %rdx
movl $2, %ecx
movq cudaValues(%rip), %rsi
leaq values(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10printfinalv
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl nsteps(%rip), %ecx
movl tpoints(%rip), %edx
movl %ebx, %esi
movq cudaValues(%rip), %rdi
call _Z34__device_stub__Z11cudaExecutePfiiiPfiii
jmp .L38
.cfi_endproc
.LFE3952:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z11cudaExecutePfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z11cudaExecutePfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl cudaArraySize
.bss
.align 4
.type cudaArraySize, @object
.size cudaArraySize, 4
cudaArraySize:
.zero 4
.globl cudaValues
.align 8
.type cudaValues, @object
.size cudaValues, 8
cudaValues:
.zero 8
.globl values
.align 32
.type values, @object
.size values, 4000000
values:
.zero 4000000
.globl rcode
.align 4
.type rcode, @object
.size rcode, 4
rcode:
.zero 4
.globl tpoints
.align 4
.type tpoints, @object
.size tpoints, 4
tpoints:
.zero 4
.globl nsteps
.align 4
.type nsteps, @object
.size nsteps, 4
nsteps:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1086918619
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <ctime>
#include <iostream>
#include <iomanip>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
#define THREADPERWARP 32
#define SMNUM 80
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS]; /* values at time t */
float *cudaValues;
int cudaArraySize;
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, tmp;
/* Calculate initial values based on sine curve */
//float fac = 2.0 * PI;
float fac = 6.2831853;
//k = 0.0;
tmp = tpoints - 1;
for (j = 0; j < tpoints; ++j) {
x = static_cast<float>(j)/tmp;
values[j] = sin (fac * x);
}
/* Initialize old values array */
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
printf("0.0000 ");
for (i = 1; i < tpoints; ++i) {
printf("%6.4f ", values[i]);
if (i%10 == 9)
printf("\n");
}
}
__global__ void cudaExecute(float* cudaAns,int howMany,int tpoints,int tIteration)
{
float cudaValues,cudaOld,cudaNew;
double cudaTwiceValue;
double valuePar = 2.0 - static_cast<float>(0.09) * 2.0;
for(int block=0;block<howMany;++block)
{
int ansIndex=block*(SMNUM*THREADPERWARP) + blockIdx.x*blockDim.x + threadIdx.x;
cudaValues = cudaAns[ansIndex];
cudaOld = cudaValues;
for(int iter=0;iter<tIteration;++iter)
{
cudaTwiceValue = valuePar * cudaValues;
cudaNew = (cudaTwiceValue) - cudaOld;
//cudaNew = (2.0 * cudaValues)
// - cudaOld
// + (static_cast<float>(0.09) * (-2.0)*cudaValues);
cudaOld=cudaValues;
cudaValues=cudaNew;
}
cudaAns[ansIndex]=cudaValues;
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
int howManyBlock=tpoints/(SMNUM*THREADPERWARP);
if(tpoints%(SMNUM*THREADPERWARP)!=0)
++howManyBlock;
cudaArraySize = tpoints*sizeof(float);
printf("Initializing points on the line...\n");
cudaMalloc((void**)&cudaValues,cudaArraySize);
init_line();
cudaMemcpy(cudaValues,values,cudaArraySize,cudaMemcpyHostToDevice);
cudaExecute<<<SMNUM,THREADPERWARP>>>(cudaValues,howManyBlock,tpoints,nsteps);
cudaMemcpy(values,cudaValues,cudaArraySize-4,cudaMemcpyDeviceToHost);
//update();
printf("Updating all points for all time steps...\n");
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <ctime>
#include <iostream>
#include <iomanip>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
#define THREADPERWARP 32
#define SMNUM 80
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS]; /* values at time t */
float *cudaValues;
int cudaArraySize;
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, tmp;
/* Calculate initial values based on sine curve */
//float fac = 2.0 * PI;
float fac = 6.2831853;
//k = 0.0;
tmp = tpoints - 1;
for (j = 0; j < tpoints; ++j) {
x = static_cast<float>(j)/tmp;
values[j] = sin (fac * x);
}
/* Initialize old values array */
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
printf("0.0000 ");
for (i = 1; i < tpoints; ++i) {
printf("%6.4f ", values[i]);
if (i%10 == 9)
printf("\n");
}
}
__global__ void cudaExecute(float* cudaAns,int howMany,int tpoints,int tIteration)
{
float cudaValues,cudaOld,cudaNew;
double cudaTwiceValue;
double valuePar = 2.0 - static_cast<float>(0.09) * 2.0;
for(int block=0;block<howMany;++block)
{
int ansIndex=block*(SMNUM*THREADPERWARP) + blockIdx.x*blockDim.x + threadIdx.x;
cudaValues = cudaAns[ansIndex];
cudaOld = cudaValues;
for(int iter=0;iter<tIteration;++iter)
{
cudaTwiceValue = valuePar * cudaValues;
cudaNew = (cudaTwiceValue) - cudaOld;
//cudaNew = (2.0 * cudaValues)
// - cudaOld
// + (static_cast<float>(0.09) * (-2.0)*cudaValues);
cudaOld=cudaValues;
cudaValues=cudaNew;
}
cudaAns[ansIndex]=cudaValues;
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
int howManyBlock=tpoints/(SMNUM*THREADPERWARP);
if(tpoints%(SMNUM*THREADPERWARP)!=0)
++howManyBlock;
cudaArraySize = tpoints*sizeof(float);
printf("Initializing points on the line...\n");
hipMalloc((void**)&cudaValues,cudaArraySize);
init_line();
hipMemcpy(cudaValues,values,cudaArraySize,hipMemcpyHostToDevice);
cudaExecute<<<SMNUM,THREADPERWARP>>>(cudaValues,howManyBlock,tpoints,nsteps);
hipMemcpy(values,cudaValues,cudaArraySize-4,hipMemcpyDeviceToHost);
//update();
printf("Updating all points for all time steps...\n");
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <ctime>
#include <iostream>
#include <iomanip>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
#define THREADPERWARP 32
#define SMNUM 80
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS]; /* values at time t */
float *cudaValues;
int cudaArraySize;
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, tmp;
/* Calculate initial values based on sine curve */
//float fac = 2.0 * PI;
float fac = 6.2831853;
//k = 0.0;
tmp = tpoints - 1;
for (j = 0; j < tpoints; ++j) {
x = static_cast<float>(j)/tmp;
values[j] = sin (fac * x);
}
/* Initialize old values array */
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
printf("0.0000 ");
for (i = 1; i < tpoints; ++i) {
printf("%6.4f ", values[i]);
if (i%10 == 9)
printf("\n");
}
}
__global__ void cudaExecute(float* cudaAns,int howMany,int tpoints,int tIteration)
{
float cudaValues,cudaOld,cudaNew;
double cudaTwiceValue;
double valuePar = 2.0 - static_cast<float>(0.09) * 2.0;
for(int block=0;block<howMany;++block)
{
int ansIndex=block*(SMNUM*THREADPERWARP) + blockIdx.x*blockDim.x + threadIdx.x;
cudaValues = cudaAns[ansIndex];
cudaOld = cudaValues;
for(int iter=0;iter<tIteration;++iter)
{
cudaTwiceValue = valuePar * cudaValues;
cudaNew = (cudaTwiceValue) - cudaOld;
//cudaNew = (2.0 * cudaValues)
// - cudaOld
// + (static_cast<float>(0.09) * (-2.0)*cudaValues);
cudaOld=cudaValues;
cudaValues=cudaNew;
}
cudaAns[ansIndex]=cudaValues;
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
int howManyBlock=tpoints/(SMNUM*THREADPERWARP);
if(tpoints%(SMNUM*THREADPERWARP)!=0)
++howManyBlock;
cudaArraySize = tpoints*sizeof(float);
printf("Initializing points on the line...\n");
hipMalloc((void**)&cudaValues,cudaArraySize);
init_line();
hipMemcpy(cudaValues,values,cudaArraySize,hipMemcpyHostToDevice);
cudaExecute<<<SMNUM,THREADPERWARP>>>(cudaValues,howManyBlock,tpoints,nsteps);
hipMemcpy(values,cudaValues,cudaArraySize-4,hipMemcpyDeviceToHost);
//update();
printf("Updating all points for all time steps...\n");
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11cudaExecutePfiii
.globl _Z11cudaExecutePfiii
.p2align 8
.type _Z11cudaExecutePfiii,@function
_Z11cudaExecutePfiii:
s_load_b32 s6, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, 0x3ffd1eb8
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s4, 0xffff
s_cmp_gt_i32 s7, 0
s_mul_i32 s15, s15, s0
s_cselect_b32 s1, -1, 0
s_brev_b32 s4, 10
v_cndmask_b32_e64 v1, 0, 1, s1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s1, s1, 1
global_store_b32 v[1:2], v3, off
s_cmp_eq_u32 s1, s6
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mul_i32 s8, s1, 0xa00
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v1, s15, s8, v0
s_mov_b32 s8, s7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_and_b32 vcc_lo, exec_lo, s0
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_mov_b32_e32 v4, v3
s_cbranch_vccnz .LBB0_2
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v3
v_cvt_f64_f32_e32 v[3:4], v4
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s8, 0
v_cvt_f64_f32_e32 v[5:6], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[5:6], s[4:5], -v[3:4]
v_cvt_f32_f64_e32 v3, v[3:4]
v_mov_b32_e32 v4, v7
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11cudaExecutePfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11cudaExecutePfiii, .Lfunc_end0-_Z11cudaExecutePfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11cudaExecutePfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11cudaExecutePfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <ctime>
#include <iostream>
#include <iomanip>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
#define THREADPERWARP 32
#define SMNUM 80
void check_param(void);
void init_line(void);
void update (void);
void printfinal (void);
int nsteps, /* number of time steps */
tpoints, /* total points along string */
rcode; /* generic return code */
float values[MAXPOINTS]; /* values at time t */
float *cudaValues;
int cudaArraySize;
/**********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points, number of iterations */
while ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: "
,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if ((tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n",
MINPOINTS, MAXPOINTS);
}
while ((nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints, nsteps);
}
/**********************************************************************
* Initialize points on line
*********************************************************************/
void init_line(void)
{
int i, j;
float x, tmp;
/* Calculate initial values based on sine curve */
//float fac = 2.0 * PI;
float fac = 6.2831853;
//k = 0.0;
tmp = tpoints - 1;
for (j = 0; j < tpoints; ++j) {
x = static_cast<float>(j)/tmp;
values[j] = sin (fac * x);
}
/* Initialize old values array */
}
/**********************************************************************
* Print final results
*********************************************************************/
void printfinal()
{
int i;
printf("0.0000 ");
for (i = 1; i < tpoints; ++i) {
printf("%6.4f ", values[i]);
if (i%10 == 9)
printf("\n");
}
}
__global__ void cudaExecute(float* cudaAns,int howMany,int tpoints,int tIteration)
{
float cudaValues,cudaOld,cudaNew;
double cudaTwiceValue;
double valuePar = 2.0 - static_cast<float>(0.09) * 2.0;
for(int block=0;block<howMany;++block)
{
int ansIndex=block*(SMNUM*THREADPERWARP) + blockIdx.x*blockDim.x + threadIdx.x;
cudaValues = cudaAns[ansIndex];
cudaOld = cudaValues;
for(int iter=0;iter<tIteration;++iter)
{
cudaTwiceValue = valuePar * cudaValues;
cudaNew = (cudaTwiceValue) - cudaOld;
//cudaNew = (2.0 * cudaValues)
// - cudaOld
// + (static_cast<float>(0.09) * (-2.0)*cudaValues);
cudaOld=cudaValues;
cudaValues=cudaNew;
}
cudaAns[ansIndex]=cudaValues;
}
}
/**********************************************************************
* Main program
*********************************************************************/
int main(int argc, char *argv[])
{
sscanf(argv[1],"%d",&tpoints);
sscanf(argv[2],"%d",&nsteps);
check_param();
int howManyBlock=tpoints/(SMNUM*THREADPERWARP);
if(tpoints%(SMNUM*THREADPERWARP)!=0)
++howManyBlock;
cudaArraySize = tpoints*sizeof(float);
printf("Initializing points on the line...\n");
hipMalloc((void**)&cudaValues,cudaArraySize);
init_line();
hipMemcpy(cudaValues,values,cudaArraySize,hipMemcpyHostToDevice);
cudaExecute<<<SMNUM,THREADPERWARP>>>(cudaValues,howManyBlock,tpoints,nsteps);
hipMemcpy(values,cudaValues,cudaArraySize-4,hipMemcpyDeviceToHost);
//update();
printf("Updating all points for all time steps...\n");
printf("Printing final results...\n");
printfinal();
printf("\nDone.\n\n");
return 0;
} | .text
.file "wave.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11check_paramv # -- Begin function _Z11check_paramv
.p2align 4, 0x90
.type _Z11check_paramv,@function
_Z11check_paramv: # @_Z11check_paramv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %.preheader
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB0_10
.LBB0_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nsteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_9
.LBB0_10: # %._crit_edge
movl tpoints(%rip), %esi
movl $.L.str.5, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11check_paramv, .Lfunc_end0-_Z11check_paramv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9init_linev
.LCPI1_0:
.long 0x40c90fdb # float 6.28318548
.text
.globl _Z9init_linev
.p2align 4, 0x90
.type _Z9init_linev,@function
_Z9init_linev: # @_Z9init_linev
.cfi_startproc
# %bb.0:
movl tpoints(%rip), %eax
testl %eax, %eax
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
decl %eax
cvtsi2ss %eax, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
divss 12(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
callq sin
cvtsd2ss %xmm0, %xmm0
movss %xmm0, values(,%rbx,4)
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jl .LBB1_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z9init_linev, .Lfunc_end1-_Z9init_linev
.cfi_endproc
# -- End function
.globl _Z10printfinalv # -- Begin function _Z10printfinalv
.p2align 4, 0x90
.type _Z10printfinalv,@function
_Z10printfinalv: # @_Z10printfinalv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
cmpl $2, tpoints(%rip)
jl .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl $1, %ebx
movl $3435973837, %r14d # imm = 0xCCCCCCCD
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jge .LBB2_5
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r14, %rax
shrq $35, %rax
addl %eax, %eax
leal (%rax,%rax,4), %eax
movl %ebx, %ebp
subl %eax, %ebp
movss values(,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
cmpl $9, %ebp
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_4
.LBB2_5: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10printfinalv, .Lfunc_end2-_Z10printfinalv
.cfi_endproc
# -- End function
.globl _Z26__device_stub__cudaExecutePfiii # -- Begin function _Z26__device_stub__cudaExecutePfiii
.p2align 4, 0x90
.type _Z26__device_stub__cudaExecutePfiii,@function
_Z26__device_stub__cudaExecutePfiii: # @_Z26__device_stub__cudaExecutePfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11cudaExecutePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z26__device_stub__cudaExecutePfiii, .Lfunc_end3-_Z26__device_stub__cudaExecutePfiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x40c90fdb # float 6.28318548
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $.L.str.9, %esi
movl $tpoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movl $.L.str.9, %esi
movl $nsteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
callq _Z11check_paramv
movslq tpoints(%rip), %rax
imulq $1717986919, %rax, %rbx # imm = 0x66666667
movq %rbx, %rcx
shrq $63, %rcx
sarq $42, %rbx
addl %ecx, %ebx
imull $-858993459, %eax, %ecx # imm = 0xCCCCCCCD
addl $429496320, %ecx # imm = 0x19999800
rorl $9, %ecx
cmpl $1677721, %ecx # imm = 0x199999
sbbl $-1, %ebx
leal (,%rax,4), %eax
movl %eax, cudaArraySize(%rip)
movl $.Lstr, %edi
callq puts@PLT
movslq cudaArraySize(%rip), %rsi
movl $cudaValues, %edi
callq hipMalloc
movl tpoints(%rip), %eax
testl %eax, %eax
jle .LBB4_3
# %bb.1: # %.lr.ph.i.preheader
decl %eax
cvtsi2ss %eax, %xmm0
movss %xmm0, 8(%rsp) # 4-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
divss 8(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
callq sin
cvtsd2ss %xmm0, %xmm0
movss %xmm0, values(,%r14,4)
incq %r14
movslq tpoints(%rip), %rax
cmpq %rax, %r14
jl .LBB4_2
.LBB4_3: # %_Z9init_linev.exit
movq cudaValues(%rip), %rdi
movslq cudaArraySize(%rip), %rdx
movl $values, %esi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 48(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4:
movq cudaValues(%rip), %rax
movl tpoints(%rip), %ecx
movl nsteps(%rip), %edx
movq %rax, 72(%rsp)
movl %ebx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11cudaExecutePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_5:
movq cudaValues(%rip), %rsi
movslq cudaArraySize(%rip), %rdx
addq $-4, %rdx
movl $values, %edi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
cmpl $2, tpoints(%rip)
jl .LBB4_10
# %bb.6: # %.lr.ph.i9.preheader
movl $1, %ebx
movl $3435973837, %r14d # imm = 0xCCCCCCCD
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_7 Depth=1
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jge .LBB4_10
.LBB4_7: # %.lr.ph.i9
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r14, %rax
shrq $35, %rax
addl %eax, %eax
leal (%rax,%rax,4), %eax
movl %ebx, %ebp
subl %eax, %ebp
movss values(,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
cmpl $9, %ebp
jne .LBB4_9
# %bb.8: # in Loop: Header=BB4_7 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB4_9
.LBB4_10: # %_Z10printfinalv.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11cudaExecutePfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type nsteps,@object # @nsteps
.bss
.globl nsteps
.p2align 2, 0x0
nsteps:
.long 0 # 0x0
.size nsteps, 4
.type tpoints,@object # @tpoints
.globl tpoints
.p2align 2, 0x0
tpoints:
.long 0 # 0x0
.size tpoints, 4
.type rcode,@object # @rcode
.globl rcode
.p2align 2, 0x0
rcode:
.long 0 # 0x0
.size rcode, 4
.type values,@object # @values
.globl values
.p2align 4, 0x0
values:
.zero 4000000
.size values, 4000000
.type cudaValues,@object # @cudaValues
.globl cudaValues
.p2align 3, 0x0
cudaValues:
.quad 0
.size cudaValues, 8
.type cudaArraySize,@object # @cudaArraySize
.globl cudaArraySize
.p2align 2, 0x0
cudaArraySize:
.long 0 # 0x0
.size cudaArraySize, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid. Please enter value between %d and %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid. Please enter value between 1 and %d\n"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.5, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "0.0000 "
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%6.4f "
.size .L.str.7, 7
.type _Z11cudaExecutePfiii,@object # @_Z11cudaExecutePfiii
.section .rodata,"a",@progbits
.globl _Z11cudaExecutePfiii
.p2align 3, 0x0
_Z11cudaExecutePfiii:
.quad _Z26__device_stub__cudaExecutePfiii
.size _Z11cudaExecutePfiii, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11cudaExecutePfiii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps..."
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results..."
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone.\n"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__cudaExecutePfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nsteps
.addrsig_sym tpoints
.addrsig_sym values
.addrsig_sym cudaValues
.addrsig_sym _Z11cudaExecutePfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11cudaExecutePfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fda0003f01270 */
/*0050*/ @P0 BRA 0xe0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R0, R0, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc00007812 */
/* 0x000fc800078ec0ff */
/*00a0*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xa0 ; /* 0xffffffc000007947 */
/* 0x000fea000383ffff */
/*00e0*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0120*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0130*/ LOP3.LUT R18, R4.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304127812 */
/* 0x040fe400078ec0ff */
/*0140*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0150*/ IADD3 R6, -R18, c[0x0][0x170], RZ ; /* 0x00005c0012067a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ IMAD R5, R2, c[0x0][0x0], R5 ; /* 0x0000000002057a24 */
/* 0x001fc400078e0205 */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x002fe400078e00ff */
/*0180*/ IMAD R2, R0, 0xa00, R5 ; /* 0x00000a0000027824 */
/* 0x000fc800078e0205 */
/*0190*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*01a0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*01c0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f26270 */
/*01e0*/ IMAD.MOV.U32 R19, RZ, RZ, R8 ; /* 0x000000ffff137224 */
/* 0x004fcc00078e0008 */
/*01f0*/ @!P0 BRA 0x8b0 ; /* 0x000006b000008947 */
/* 0x001fea0003800000 */
/*0200*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0210*/ IMAD.MOV.U32 R19, RZ, RZ, R8 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0008 */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fd400078e0006 */
/*0230*/ @!P0 BRA 0x7b0 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.GT.AND P2, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f44270 */
/*0250*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0260*/ @!P2 BRA 0x5c0 ; /* 0x000003500000a947 */
/* 0x000fea0003800000 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0280*/ F2F.F64.F32 R10, R19 ; /* 0x00000013000a7310 */
/* 0x002fe20000201800 */
/*0290*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc80007ffe0ff */
/*02a0*/ ISETP.GT.AND P2, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fc60003f44270 */
/*02b0*/ F2F.F64.F32 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e240000201800 */
/*02c0*/ DFMA R12, R10, c[0x2][0x0], -R8 ; /* 0x008000000a0c7a2b */
/* 0x001e140000000808 */
/*02d0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*02e0*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*02f0*/ DFMA R10, R14, c[0x2][0x0], -R10 ; /* 0x008000000e0a7a2b */
/* 0x001e14000000080a */
/*0300*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*0310*/ F2F.F64.F32 R16, R10 ; /* 0x0000000a00107310 */
/* 0x001e240000201800 */
/*0320*/ DFMA R14, R16, c[0x2][0x0], -R14 ; /* 0x00800000100e7a2b */
/* 0x001e14000000080e */
/*0330*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e300000301000 */
/*0340*/ F2F.F64.F32 R20, R14 ; /* 0x0000000e00147310 */
/* 0x001e240000201800 */
/*0350*/ DFMA R16, R20, c[0x2][0x0], -R16 ; /* 0x0080000014107a2b */
/* 0x001e140000000810 */
/*0360*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*0370*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x001e240000201800 */
/*0380*/ DFMA R20, R8, c[0x2][0x0], -R20 ; /* 0x0080000008147a2b */
/* 0x001e140000000814 */
/*0390*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x001e300000301000 */
/*03a0*/ F2F.F64.F32 R12, R20 ; /* 0x00000014000c7310 */
/* 0x001e240000201800 */
/*03b0*/ DFMA R8, R12, c[0x2][0x0], -R8 ; /* 0x008000000c087a2b */
/* 0x001e140000000808 */
/*03c0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e300000301000 */
/*03d0*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */
/* 0x001e240000201800 */
/*03e0*/ DFMA R12, R10, c[0x2][0x0], -R12 ; /* 0x008000000a0c7a2b */
/* 0x001e14000000080c */
/*03f0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*0400*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0410*/ DFMA R10, R14, c[0x2][0x0], -R10 ; /* 0x008000000e0a7a2b */
/* 0x001e0c000000080a */
/*0420*/ F2F.F32.F64 R19, R10 ; /* 0x0000000a00137310 */
/* 0x001e300000301000 */
/*0430*/ F2F.F64.F32 R16, R19 ; /* 0x0000001300107310 */
/* 0x001e240000201800 */
/*0440*/ DFMA R14, R16, c[0x2][0x0], -R14 ; /* 0x00800000100e7a2b */
/* 0x001e14000000080e */
/*0450*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e300000301000 */
/*0460*/ F2F.F64.F32 R20, R14 ; /* 0x0000000e00147310 */
/* 0x001e240000201800 */
/*0470*/ DFMA R16, R20, c[0x2][0x0], -R16 ; /* 0x0080000014107a2b */
/* 0x001e0c0000000810 */
/*0480*/ F2F.F32.F64 R22, R16 ; /* 0x0000001000167310 */
/* 0x001e300000301000 */
/*0490*/ F2F.F64.F32 R8, R22 ; /* 0x0000001600087310 */
/* 0x001e240000201800 */
/*04a0*/ DFMA R20, R8, c[0x2][0x0], -R20 ; /* 0x0080000008147a2b */
/* 0x001e140000000814 */
/*04b0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x001e300000301000 */
/*04c0*/ F2F.F64.F32 R12, R20 ; /* 0x00000014000c7310 */
/* 0x001e240000201800 */
/*04d0*/ DFMA R10, R12, c[0x2][0x0], -R8 ; /* 0x008000000c0a7a2b */
/* 0x001e140000000808 */
/*04e0*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*04f0*/ F2F.F64.F32 R8, R10 ; /* 0x0000000a00087310 */
/* 0x001e240000201800 */
/*0500*/ DFMA R12, R8, c[0x2][0x0], -R12 ; /* 0x00800000080c7a2b */
/* 0x001e14000000080c */
/*0510*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*0520*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0530*/ DFMA R16, R14, c[0x2][0x0], -R8 ; /* 0x008000000e107a2b */
/* 0x001e140000000808 */
/*0540*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*0550*/ F2F.F64.F32 R22, R16 ; /* 0x0000001000167310 */
/* 0x001e240000201800 */
/*0560*/ DFMA R8, R22, c[0x2][0x0], -R14 ; /* 0x0080000016087a2b */
/* 0x001e14000000080e */
/*0570*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e300000301000 */
/*0580*/ F2F.F64.F32 R14, R8 ; /* 0x00000008000e7310 */
/* 0x001e240000201800 */
/*0590*/ DFMA R14, R14, c[0x2][0x0], -R22 ; /* 0x008000000e0e7a2b */
/* 0x001e0c0000000816 */
/*05a0*/ F2F.F32.F64 R19, R14 ; /* 0x0000000e00137310 */
/* 0x0010620000301000 */
/*05b0*/ @P2 BRA 0x280 ; /* 0xfffffcc000002947 */
/* 0x000fea000383ffff */
/*05c0*/ ISETP.GT.AND P2, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f44270 */
/*05d0*/ @!P2 BRA 0x790 ; /* 0x000001b00000a947 */
/* 0x000fea0003800000 */
/*05e0*/ F2F.F64.F32 R10, R19 ; /* 0x00000013000a7310 */
/* 0x002fe20000201800 */
/*05f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0600*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fca0007ffe0ff */
/*0610*/ F2F.F64.F32 R8, R8 ; /* 0x0000000800087310 */
/* 0x000e640000201800 */
/*0620*/ DFMA R12, R10, c[0x2][0x0], -R8 ; /* 0x008000000a0c7a2b */
/* 0x002e540000000808 */
/*0630*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x002e700000301000 */
/*0640*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x003e240000201800 */
/*0650*/ DFMA R10, R14, c[0x2][0x0], -R10 ; /* 0x008000000e0a7a2b */
/* 0x001e0c000000080a */
/*0660*/ F2F.F32.F64 R22, R10 ; /* 0x0000000a00167310 */
/* 0x001e300000301000 */
/*0670*/ F2F.F64.F32 R16, R22 ; /* 0x0000001600107310 */
/* 0x001e240000201800 */
/*0680*/ DFMA R14, R16, c[0x2][0x0], -R14 ; /* 0x00800000100e7a2b */
/* 0x001e14000000080e */
/*0690*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e300000301000 */
/*06a0*/ F2F.F64.F32 R20, R14 ; /* 0x0000000e00147310 */
/* 0x001e240000201800 */
/*06b0*/ DFMA R16, R20, c[0x2][0x0], -R16 ; /* 0x0080000014107a2b */
/* 0x001e140000000810 */
/*06c0*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*06d0*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x001e240000201800 */
/*06e0*/ DFMA R20, R8, c[0x2][0x0], -R20 ; /* 0x0080000008147a2b */
/* 0x001e140000000814 */
/*06f0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x001e300000301000 */
/*0700*/ F2F.F64.F32 R12, R20 ; /* 0x00000014000c7310 */
/* 0x001e240000201800 */
/*0710*/ DFMA R10, R12, c[0x2][0x0], -R8 ; /* 0x008000000c0a7a2b */
/* 0x001e140000000808 */
/*0720*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*0730*/ F2F.F64.F32 R22, R10 ; /* 0x0000000a00167310 */
/* 0x001e240000201800 */
/*0740*/ DFMA R8, R22, c[0x2][0x0], -R12 ; /* 0x0080000016087a2b */
/* 0x001e14000000080c */
/*0750*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e300000301000 */
/*0760*/ F2F.F64.F32 R12, R8 ; /* 0x00000008000c7310 */
/* 0x001e240000201800 */
/*0770*/ DFMA R12, R12, c[0x2][0x0], -R22 ; /* 0x008000000c0c7a2b */
/* 0x001e0c0000000816 */
/*0780*/ F2F.F32.F64 R19, R12 ; /* 0x0000000c00137310 */
/* 0x00106a0000301000 */
/*0790*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*07a0*/ @!P0 BRA 0x8b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*07b0*/ F2F.F64.F32 R10, R19 ; /* 0x00000013000a7310 */
/* 0x002fe20000201800 */
/*07c0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*07d0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f05270 */
/*07e0*/ F2F.F64.F32 R8, R8 ; /* 0x0000000800087310 */
/* 0x000e640000201800 */
/*07f0*/ DFMA R12, R10, c[0x2][0x0], -R8 ; /* 0x008000000a0c7a2b */
/* 0x003e140000000808 */
/*0800*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*0810*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0820*/ DFMA R10, R14, c[0x2][0x0], -R10 ; /* 0x008000000e0a7a2b */
/* 0x001e14000000080a */
/*0830*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*0840*/ F2F.F64.F32 R16, R10 ; /* 0x0000000a00107310 */
/* 0x001e240000201800 */
/*0850*/ DFMA R14, R16, c[0x2][0x0], -R14 ; /* 0x00800000100e7a2b */
/* 0x001e0c000000080e */
/*0860*/ F2F.F32.F64 R8, R14 ; /* 0x0000000e00087310 */
/* 0x001e300000301000 */
/*0870*/ F2F.F64.F32 R20, R8 ; /* 0x0000000800147310 */
/* 0x001e240000201800 */
/*0880*/ DFMA R20, R20, c[0x2][0x0], -R16 ; /* 0x0080000014147a2b */
/* 0x001e0c0000000810 */
/*0890*/ F2F.F32.F64 R19, R20 ; /* 0x0000001400137310 */
/* 0x0010640000301000 */
/*08a0*/ @P0 BRA 0x7b0 ; /* 0xffffff0000000947 */
/* 0x003fea000383ffff */
/*08b0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fda0003f05270 */
/*08c0*/ @!P0 BRA 0x9a0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08d0*/ F2F.F64.F32 R12, R19 ; /* 0x00000013000c7310 */
/* 0x003fe20000201800 */
/*08e0*/ ISETP.NE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fce0003f05270 */
/*08f0*/ F2F.F64.F32 R8, R8 ; /* 0x0000000800087310 */
/* 0x000e240000201800 */
/*0900*/ DFMA R10, R12, c[0x2][0x0], -R8 ; /* 0x008000000c0a7a2b */
/* 0x001e0c0000000808 */
/*0910*/ F2F.F32.F64 R19, R10 ; /* 0x0000000a00137310 */
/* 0x0010620000301000 */
/*0920*/ @!P0 BRA 0x9a0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0930*/ F2F.F64.F32 R10, R19 ; /* 0x00000013000a7310 */
/* 0x003e220000201800 */
/*0940*/ ISETP.NE.AND P0, PT, R18, 0x2, PT ; /* 0x000000021200780c */
/* 0x000fe20003f05270 */
/*0950*/ DFMA R8, R10, c[0x2][0x0], -R12 ; /* 0x008000000a087a2b */
/* 0x001e0c000000080c */
/*0960*/ F2F.F32.F64 R19, R8 ; /* 0x0000000800137310 */
/* 0x001e300000301000 */
/*0970*/ @P0 F2F.F64.F32 R12, R19 ; /* 0x00000013000c0310 */
/* 0x001e240000201800 */
/*0980*/ @P0 DFMA R10, R12, c[0x2][0x0], -R10 ; /* 0x008000000c0a0a2b */
/* 0x001e0c000000080a */
/*0990*/ @P0 F2F.F32.F64 R19, R10 ; /* 0x0000000a00130310 */
/* 0x00106a0000301000 */
/*09a0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0023e2000c101904 */
/*09b0*/ @!P1 BRA 0x170 ; /* 0xfffff7b000009947 */
/* 0x000fea000383ffff */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ BRA 0x9d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11cudaExecutePfiii
.globl _Z11cudaExecutePfiii
.p2align 8
.type _Z11cudaExecutePfiii,@function
_Z11cudaExecutePfiii:
s_load_b32 s6, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, 0x3ffd1eb8
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s4, 0xffff
s_cmp_gt_i32 s7, 0
s_mul_i32 s15, s15, s0
s_cselect_b32 s1, -1, 0
s_brev_b32 s4, 10
v_cndmask_b32_e64 v1, 0, 1, s1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s1, s1, 1
global_store_b32 v[1:2], v3, off
s_cmp_eq_u32 s1, s6
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mul_i32 s8, s1, 0xa00
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v1, s15, s8, v0
s_mov_b32 s8, s7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_and_b32 vcc_lo, exec_lo, s0
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_mov_b32_e32 v4, v3
s_cbranch_vccnz .LBB0_2
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v3
v_cvt_f64_f32_e32 v[3:4], v4
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s8, 0
v_cvt_f64_f32_e32 v[5:6], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[5:6], s[4:5], -v[3:4]
v_cvt_f32_f64_e32 v3, v[3:4]
v_mov_b32_e32 v4, v7
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11cudaExecutePfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11cudaExecutePfiii, .Lfunc_end0-_Z11cudaExecutePfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11cudaExecutePfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11cudaExecutePfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b4640_00000000-6_wave.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s"
.section .rodata.str1.8
.align 8
.LC2:
.string "Invalid. Please enter value between %d and %d\n"
.align 8
.LC3:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC4:
.string "Invalid. Please enter value between 1 and %d\n"
.align 8
.LC5:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z11check_paramv
.type _Z11check_paramv, @function
_Z11check_paramv:
.LFB3949:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L5:
movl tpoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L14
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, tpoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L5
movl $1000000, %ecx
movl $20, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L14:
leaq .LC3(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L8:
movl nsteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L15
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, nsteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L8
movl $1000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L15:
movl tpoints(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size _Z11check_paramv, .-_Z11check_paramv
.globl _Z9init_linev
.type _Z9init_linev, @function
_Z9init_linev:
.LFB3950:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movl tpoints(%rip), %ebp
leal -1(%rbp), %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
movss %xmm2, 12(%rsp)
testl %ebp, %ebp
jle .L17
movslq %ebp, %rbp
movl $0, %ebx
leaq values(%rip), %r12
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
divss 12(%rsp), %xmm0
mulss .LC6(%rip), %xmm0
call sinf@PLT
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L19
.L17:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _Z9init_linev, .-_Z9init_linev
.section .rodata.str1.1
.LC7:
.string "0.0000 "
.LC8:
.string "%6.4f "
.LC9:
.string "\n"
.text
.globl _Z10printfinalv
.type _Z10printfinalv, @function
_Z10printfinalv:
.LFB3951:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $1, tpoints(%rip)
jle .L22
movl $1, %ebx
leaq values(%rip), %r12
leaq .LC8(%rip), %rbp
leaq .LC9(%rip), %r13
jmp .L25
.L24:
addq $1, %rbx
cmpl %ebx, tpoints(%rip)
jle .L22
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $9, %edx
jne .L24
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L22:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _Z10printfinalv, .-_Z10printfinalv
.globl _Z34__device_stub__Z11cudaExecutePfiiiPfiii
.type _Z34__device_stub__Z11cudaExecutePfiiiPfiii, @function
_Z34__device_stub__Z11cudaExecutePfiiiPfiii:
.LFB3977:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11cudaExecutePfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z34__device_stub__Z11cudaExecutePfiiiPfiii, .-_Z34__device_stub__Z11cudaExecutePfiiiPfiii
.globl _Z11cudaExecutePfiii
.type _Z11cudaExecutePfiii, @function
_Z11cudaExecutePfiii:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11cudaExecutePfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z11cudaExecutePfiii, .-_Z11cudaExecutePfiii
.section .rodata.str1.1
.LC10:
.string "%d"
.section .rodata.str1.8
.align 8
.LC11:
.string "Initializing points on the line...\n"
.align 8
.LC12:
.string "Updating all points for all time steps...\n"
.section .rodata.str1.1
.LC13:
.string "Printing final results...\n"
.LC14:
.string "\nDone.\n\n"
.text
.globl main
.type main, @function
main:
.LFB3952:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq tpoints(%rip), %rdx
leaq .LC10(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq nsteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
call _Z11check_paramv
movl tpoints(%rip), %eax
movslq %eax, %rbx
imulq $1717986919, %rbx, %rbx
sarq $42, %rbx
cltd
subl %edx, %ebx
leal (%rbx,%rbx,4), %edx
sall $9, %edx
movl %eax, %ecx
subl %edx, %ecx
cmpl $1, %ecx
sbbl $-1, %ebx
sall $2, %eax
movl %eax, cudaArraySize(%rip)
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq cudaArraySize(%rip), %rsi
leaq cudaValues(%rip), %rdi
call cudaMalloc@PLT
call _Z9init_linev
movslq cudaArraySize(%rip), %rdx
movl $1, %ecx
leaq values(%rip), %rsi
movq cudaValues(%rip), %rdi
call cudaMemcpy@PLT
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $80, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L38:
movl cudaArraySize(%rip), %eax
leal -4(%rax), %edx
movslq %edx, %rdx
movl $2, %ecx
movq cudaValues(%rip), %rsi
leaq values(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10printfinalv
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl nsteps(%rip), %ecx
movl tpoints(%rip), %edx
movl %ebx, %esi
movq cudaValues(%rip), %rdi
call _Z34__device_stub__Z11cudaExecutePfiiiPfiii
jmp .L38
.cfi_endproc
.LFE3952:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z11cudaExecutePfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z11cudaExecutePfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl cudaArraySize
.bss
.align 4
.type cudaArraySize, @object
.size cudaArraySize, 4
cudaArraySize:
.zero 4
.globl cudaValues
.align 8
.type cudaValues, @object
.size cudaValues, 8
cudaValues:
.zero 8
.globl values
.align 32
.type values, @object
.size values, 4000000
values:
.zero 4000000
.globl rcode
.align 4
.type rcode, @object
.size rcode, 4
rcode:
.zero 4
.globl tpoints
.align 4
.type tpoints, @object
.size tpoints, 4
tpoints:
.zero 4
.globl nsteps
.align 4
.type nsteps, @object
.size nsteps, 4
nsteps:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1086918619
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "wave.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11check_paramv # -- Begin function _Z11check_paramv
.p2align 4, 0x90
.type _Z11check_paramv,@function
_Z11check_paramv: # @_Z11check_paramv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %.preheader
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB0_10
.LBB0_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nsteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_9
.LBB0_10: # %._crit_edge
movl tpoints(%rip), %esi
movl $.L.str.5, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11check_paramv, .Lfunc_end0-_Z11check_paramv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9init_linev
.LCPI1_0:
.long 0x40c90fdb # float 6.28318548
.text
.globl _Z9init_linev
.p2align 4, 0x90
.type _Z9init_linev,@function
_Z9init_linev: # @_Z9init_linev
.cfi_startproc
# %bb.0:
movl tpoints(%rip), %eax
testl %eax, %eax
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
decl %eax
cvtsi2ss %eax, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
divss 12(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
callq sin
cvtsd2ss %xmm0, %xmm0
movss %xmm0, values(,%rbx,4)
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jl .LBB1_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z9init_linev, .Lfunc_end1-_Z9init_linev
.cfi_endproc
# -- End function
.globl _Z10printfinalv # -- Begin function _Z10printfinalv
.p2align 4, 0x90
.type _Z10printfinalv,@function
_Z10printfinalv: # @_Z10printfinalv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
cmpl $2, tpoints(%rip)
jl .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl $1, %ebx
movl $3435973837, %r14d # imm = 0xCCCCCCCD
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jge .LBB2_5
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r14, %rax
shrq $35, %rax
addl %eax, %eax
leal (%rax,%rax,4), %eax
movl %ebx, %ebp
subl %eax, %ebp
movss values(,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
cmpl $9, %ebp
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_4
.LBB2_5: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10printfinalv, .Lfunc_end2-_Z10printfinalv
.cfi_endproc
# -- End function
.globl _Z26__device_stub__cudaExecutePfiii # -- Begin function _Z26__device_stub__cudaExecutePfiii
.p2align 4, 0x90
.type _Z26__device_stub__cudaExecutePfiii,@function
_Z26__device_stub__cudaExecutePfiii: # @_Z26__device_stub__cudaExecutePfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11cudaExecutePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z26__device_stub__cudaExecutePfiii, .Lfunc_end3-_Z26__device_stub__cudaExecutePfiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x40c90fdb # float 6.28318548
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $.L.str.9, %esi
movl $tpoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movl $.L.str.9, %esi
movl $nsteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
callq _Z11check_paramv
movslq tpoints(%rip), %rax
imulq $1717986919, %rax, %rbx # imm = 0x66666667
movq %rbx, %rcx
shrq $63, %rcx
sarq $42, %rbx
addl %ecx, %ebx
imull $-858993459, %eax, %ecx # imm = 0xCCCCCCCD
addl $429496320, %ecx # imm = 0x19999800
rorl $9, %ecx
cmpl $1677721, %ecx # imm = 0x199999
sbbl $-1, %ebx
leal (,%rax,4), %eax
movl %eax, cudaArraySize(%rip)
movl $.Lstr, %edi
callq puts@PLT
movslq cudaArraySize(%rip), %rsi
movl $cudaValues, %edi
callq hipMalloc
movl tpoints(%rip), %eax
testl %eax, %eax
jle .LBB4_3
# %bb.1: # %.lr.ph.i.preheader
decl %eax
cvtsi2ss %eax, %xmm0
movss %xmm0, 8(%rsp) # 4-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
divss 8(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
callq sin
cvtsd2ss %xmm0, %xmm0
movss %xmm0, values(,%r14,4)
incq %r14
movslq tpoints(%rip), %rax
cmpq %rax, %r14
jl .LBB4_2
.LBB4_3: # %_Z9init_linev.exit
movq cudaValues(%rip), %rdi
movslq cudaArraySize(%rip), %rdx
movl $values, %esi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 48(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4:
movq cudaValues(%rip), %rax
movl tpoints(%rip), %ecx
movl nsteps(%rip), %edx
movq %rax, 72(%rsp)
movl %ebx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11cudaExecutePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_5:
movq cudaValues(%rip), %rsi
movslq cudaArraySize(%rip), %rdx
addq $-4, %rdx
movl $values, %edi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
cmpl $2, tpoints(%rip)
jl .LBB4_10
# %bb.6: # %.lr.ph.i9.preheader
movl $1, %ebx
movl $3435973837, %r14d # imm = 0xCCCCCCCD
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_7 Depth=1
incq %rbx
movslq tpoints(%rip), %rax
cmpq %rax, %rbx
jge .LBB4_10
.LBB4_7: # %.lr.ph.i9
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r14, %rax
shrq $35, %rax
addl %eax, %eax
leal (%rax,%rax,4), %eax
movl %ebx, %ebp
subl %eax, %ebp
movss values(,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
cmpl $9, %ebp
jne .LBB4_9
# %bb.8: # in Loop: Header=BB4_7 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB4_9
.LBB4_10: # %_Z10printfinalv.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11cudaExecutePfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type nsteps,@object # @nsteps
.bss
.globl nsteps
.p2align 2, 0x0
nsteps:
.long 0 # 0x0
.size nsteps, 4
.type tpoints,@object # @tpoints
.globl tpoints
.p2align 2, 0x0
tpoints:
.long 0 # 0x0
.size tpoints, 4
.type rcode,@object # @rcode
.globl rcode
.p2align 2, 0x0
rcode:
.long 0 # 0x0
.size rcode, 4
.type values,@object # @values
.globl values
.p2align 4, 0x0
values:
.zero 4000000
.size values, 4000000
.type cudaValues,@object # @cudaValues
.globl cudaValues
.p2align 3, 0x0
cudaValues:
.quad 0
.size cudaValues, 8
.type cudaArraySize,@object # @cudaArraySize
.globl cudaArraySize
.p2align 2, 0x0
cudaArraySize:
.long 0 # 0x0
.size cudaArraySize, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid. Please enter value between %d and %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid. Please enter value between 1 and %d\n"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.5, 31
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "0.0000 "
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%6.4f "
.size .L.str.7, 7
.type _Z11cudaExecutePfiii,@object # @_Z11cudaExecutePfiii
.section .rodata,"a",@progbits
.globl _Z11cudaExecutePfiii
.p2align 3, 0x0
_Z11cudaExecutePfiii:
.quad _Z26__device_stub__cudaExecutePfiii
.size _Z11cudaExecutePfiii, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11cudaExecutePfiii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps..."
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results..."
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone.\n"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__cudaExecutePfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nsteps
.addrsig_sym tpoints
.addrsig_sym values
.addrsig_sym cudaValues
.addrsig_sym _Z11cudaExecutePfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#define iMin(a, b) (a<b?a:b)
const int N = 17*1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = iMin(16, (N+threadsPerBlock-1)/threadsPerBlock);
// kernel code for adding two vector elements
__global__ void vecDot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp=0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
// write partial sum of products into cache
cache[cacheIndex] = temp;
// synchronize threads in block
__syncthreads();
// reduction of vector across threads in block
int i=blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex+i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
c[blockIdx.x] = cache[0];
}
int main(void)
{
int i;
float *a, *b, c, *cPartial;
float *devPtrA, *devPtrB, *devPtrCPartial;
// allocate memory for large vectors
a = (float*) malloc(N*sizeof(float));
b = (float*) malloc(N*sizeof(float));
cPartial = (float*) malloc(blocksPerGrid*sizeof(float));
// initialize arrays
for (i=0; i < N; i++) {
a[i] = 1;
b[i] = 2;
}
// allocate CUDA memory for arrays
int memsize = N*sizeof(float);
int memsizePartial = blocksPerGrid*sizeof(float);
cudaMalloc((void**)&devPtrA, memsize);
cudaMalloc((void**)&devPtrB, memsize);
cudaMalloc((void**)&devPtrCPartial, memsizePartial);
// copy host data to CUDA memory
cudaMemcpy(devPtrA, a, memsize, cudaMemcpyHostToDevice);
cudaMemcpy(devPtrB, b, memsize, cudaMemcpyHostToDevice);
// call add function on CUDA GPU
vecDot<<<blocksPerGrid, threadsPerBlock>>>(devPtrA, devPtrB, devPtrCPartial);
// copy results back
cudaMemcpy(cPartial, devPtrCPartial, memsizePartial, cudaMemcpyDeviceToHost);
// compute final result
c = 0;
for (i=0; i < blocksPerGrid; i++)
c += cPartial[i];
printf("a*b = %f\n", c);
cudaFree(devPtrA);
cudaFree(devPtrB);
cudaFree(devPtrCPartial);
free (a);
free (b);
free (cPartial);
return 0;
} | code for sm_80
Function : _Z6vecDotPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fca00078e0208 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x43ff, PT ; /* 0x000043ff0000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x4400, PT ; /* 0x000044000000780c */
/* 0x000fe20003f06270 */
/*0120*/ FFMA R6, R5, R2, R6 ; /* 0x0000000205067223 */
/* 0x004fd80000000006 */
/*0130*/ @!P0 BRA 0xa0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ STS [R8.X4], R6 ; /* 0x0000000608007388 */
/* 0x0001e20000004800 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01b0*/ @!P1 BRA 0x2a0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01c0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01d0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01e0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01f0*/ @!P1 LEA R2, R3.reuse, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x040fe200078e10ff */
/*0200*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fe20000000000 */
/*0230*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0240*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0250*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x0001e80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0290*/ @P1 BRA 0x1e0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0002 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#define iMin(a, b) (a<b?a:b)
const int N = 17*1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = iMin(16, (N+threadsPerBlock-1)/threadsPerBlock);
// kernel code for adding two vector elements
__global__ void vecDot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp=0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
// write partial sum of products into cache
cache[cacheIndex] = temp;
// synchronize threads in block
__syncthreads();
// reduction of vector across threads in block
int i=blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex+i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
c[blockIdx.x] = cache[0];
}
int main(void)
{
int i;
float *a, *b, c, *cPartial;
float *devPtrA, *devPtrB, *devPtrCPartial;
// allocate memory for large vectors
a = (float*) malloc(N*sizeof(float));
b = (float*) malloc(N*sizeof(float));
cPartial = (float*) malloc(blocksPerGrid*sizeof(float));
// initialize arrays
for (i=0; i < N; i++) {
a[i] = 1;
b[i] = 2;
}
// allocate CUDA memory for arrays
int memsize = N*sizeof(float);
int memsizePartial = blocksPerGrid*sizeof(float);
cudaMalloc((void**)&devPtrA, memsize);
cudaMalloc((void**)&devPtrB, memsize);
cudaMalloc((void**)&devPtrCPartial, memsizePartial);
// copy host data to CUDA memory
cudaMemcpy(devPtrA, a, memsize, cudaMemcpyHostToDevice);
cudaMemcpy(devPtrB, b, memsize, cudaMemcpyHostToDevice);
// call add function on CUDA GPU
vecDot<<<blocksPerGrid, threadsPerBlock>>>(devPtrA, devPtrB, devPtrCPartial);
// copy results back
cudaMemcpy(cPartial, devPtrCPartial, memsizePartial, cudaMemcpyDeviceToHost);
// compute final result
c = 0;
for (i=0; i < blocksPerGrid; i++)
c += cPartial[i];
printf("a*b = %f\n", c);
cudaFree(devPtrA);
cudaFree(devPtrB);
cudaFree(devPtrCPartial);
free (a);
free (b);
free (cPartial);
return 0;
} | .file "tmpxft_0014e1b3_00000000-6_vecdot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecDotPfS_S_PfS_S_
.type _Z29__device_stub__Z6vecDotPfS_S_PfS_S_, @function
_Z29__device_stub__Z6vecDotPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecDotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6vecDotPfS_S_PfS_S_, .-_Z29__device_stub__Z6vecDotPfS_S_PfS_S_
.globl _Z6vecDotPfS_S_
.type _Z6vecDotPfS_S_, @function
_Z6vecDotPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecDotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecDotPfS_S_, .-_Z6vecDotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "a*b = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $69632, %edi
call malloc@PLT
movq %rax, %rbp
movl $69632, %edi
call malloc@PLT
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $69632, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $69632, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $69632, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $69632, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $69632, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rax
leaq 64(%r12), %rdx
pxor %xmm0, %xmm0
.L14:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L14
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6vecDotPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6vecDotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecDotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#define iMin(a, b) (a<b?a:b)
const int N = 17*1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = iMin(16, (N+threadsPerBlock-1)/threadsPerBlock);
// kernel code for adding two vector elements
__global__ void vecDot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp=0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
// write partial sum of products into cache
cache[cacheIndex] = temp;
// synchronize threads in block
__syncthreads();
// reduction of vector across threads in block
int i=blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex+i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
c[blockIdx.x] = cache[0];
}
int main(void)
{
int i;
float *a, *b, c, *cPartial;
float *devPtrA, *devPtrB, *devPtrCPartial;
// allocate memory for large vectors
a = (float*) malloc(N*sizeof(float));
b = (float*) malloc(N*sizeof(float));
cPartial = (float*) malloc(blocksPerGrid*sizeof(float));
// initialize arrays
for (i=0; i < N; i++) {
a[i] = 1;
b[i] = 2;
}
// allocate CUDA memory for arrays
int memsize = N*sizeof(float);
int memsizePartial = blocksPerGrid*sizeof(float);
cudaMalloc((void**)&devPtrA, memsize);
cudaMalloc((void**)&devPtrB, memsize);
cudaMalloc((void**)&devPtrCPartial, memsizePartial);
// copy host data to CUDA memory
cudaMemcpy(devPtrA, a, memsize, cudaMemcpyHostToDevice);
cudaMemcpy(devPtrB, b, memsize, cudaMemcpyHostToDevice);
// call add function on CUDA GPU
vecDot<<<blocksPerGrid, threadsPerBlock>>>(devPtrA, devPtrB, devPtrCPartial);
// copy results back
cudaMemcpy(cPartial, devPtrCPartial, memsizePartial, cudaMemcpyDeviceToHost);
// compute final result
c = 0;
for (i=0; i < blocksPerGrid; i++)
c += cPartial[i];
printf("a*b = %f\n", c);
cudaFree(devPtrA);
cudaFree(devPtrB);
cudaFree(devPtrCPartial);
free (a);
free (b);
free (cPartial);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define iMin(a, b) (a<b?a:b)
const int N = 17*1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = iMin(16, (N+threadsPerBlock-1)/threadsPerBlock);
// kernel code for adding two vector elements
__global__ void vecDot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp=0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
// write partial sum of products into cache
cache[cacheIndex] = temp;
// synchronize threads in block
__syncthreads();
// reduction of vector across threads in block
int i=blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex+i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
c[blockIdx.x] = cache[0];
}
int main(void)
{
int i;
float *a, *b, c, *cPartial;
float *devPtrA, *devPtrB, *devPtrCPartial;
// allocate memory for large vectors
a = (float*) malloc(N*sizeof(float));
b = (float*) malloc(N*sizeof(float));
cPartial = (float*) malloc(blocksPerGrid*sizeof(float));
// initialize arrays
for (i=0; i < N; i++) {
a[i] = 1;
b[i] = 2;
}
// allocate CUDA memory for arrays
int memsize = N*sizeof(float);
int memsizePartial = blocksPerGrid*sizeof(float);
hipMalloc((void**)&devPtrA, memsize);
hipMalloc((void**)&devPtrB, memsize);
hipMalloc((void**)&devPtrCPartial, memsizePartial);
// copy host data to CUDA memory
hipMemcpy(devPtrA, a, memsize, hipMemcpyHostToDevice);
hipMemcpy(devPtrB, b, memsize, hipMemcpyHostToDevice);
// call add function on CUDA GPU
vecDot<<<blocksPerGrid, threadsPerBlock>>>(devPtrA, devPtrB, devPtrCPartial);
// copy results back
hipMemcpy(cPartial, devPtrCPartial, memsizePartial, hipMemcpyDeviceToHost);
// compute final result
c = 0;
for (i=0; i < blocksPerGrid; i++)
c += cPartial[i];
printf("a*b = %f\n", c);
hipFree(devPtrA);
hipFree(devPtrB);
hipFree(devPtrCPartial);
free (a);
free (b);
free (cPartial);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define iMin(a, b) (a<b?a:b)
const int N = 17*1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = iMin(16, (N+threadsPerBlock-1)/threadsPerBlock);
// kernel code for adding two vector elements
__global__ void vecDot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp=0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
// write partial sum of products into cache
cache[cacheIndex] = temp;
// synchronize threads in block
__syncthreads();
// reduction of vector across threads in block
int i=blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex+i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
c[blockIdx.x] = cache[0];
}
int main(void)
{
int i;
float *a, *b, c, *cPartial;
float *devPtrA, *devPtrB, *devPtrCPartial;
// allocate memory for large vectors
a = (float*) malloc(N*sizeof(float));
b = (float*) malloc(N*sizeof(float));
cPartial = (float*) malloc(blocksPerGrid*sizeof(float));
// initialize arrays
for (i=0; i < N; i++) {
a[i] = 1;
b[i] = 2;
}
// allocate CUDA memory for arrays
int memsize = N*sizeof(float);
int memsizePartial = blocksPerGrid*sizeof(float);
hipMalloc((void**)&devPtrA, memsize);
hipMalloc((void**)&devPtrB, memsize);
hipMalloc((void**)&devPtrCPartial, memsizePartial);
// copy host data to CUDA memory
hipMemcpy(devPtrA, a, memsize, hipMemcpyHostToDevice);
hipMemcpy(devPtrB, b, memsize, hipMemcpyHostToDevice);
// call add function on CUDA GPU
vecDot<<<blocksPerGrid, threadsPerBlock>>>(devPtrA, devPtrB, devPtrCPartial);
// copy results back
hipMemcpy(cPartial, devPtrCPartial, memsizePartial, hipMemcpyDeviceToHost);
// compute final result
c = 0;
for (i=0; i < blocksPerGrid; i++)
c += cPartial[i];
printf("a*b = %f\n", c);
hipFree(devPtrA);
hipFree(devPtrB);
hipFree(devPtrCPartial);
free (a);
free (b);
free (cPartial);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecDotPfS_S_
.globl _Z6vecDotPfS_S_
.p2align 8
.type _Z6vecDotPfS_S_,@function
_Z6vecDotPfS_S_:
s_load_b32 s3, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x4400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x43ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecDotPfS_S_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecDotPfS_S_, .Lfunc_end0-_Z6vecDotPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecDotPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecDotPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define iMin(a, b) (a<b?a:b)
const int N = 17*1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = iMin(16, (N+threadsPerBlock-1)/threadsPerBlock);
// kernel code for adding two vector elements
__global__ void vecDot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp=0;
while (tid < N) {
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
// write partial sum of products into cache
cache[cacheIndex] = temp;
// synchronize threads in block
__syncthreads();
// reduction of vector across threads in block
int i=blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex+i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
c[blockIdx.x] = cache[0];
}
int main(void)
{
int i;
float *a, *b, c, *cPartial;
float *devPtrA, *devPtrB, *devPtrCPartial;
// allocate memory for large vectors
a = (float*) malloc(N*sizeof(float));
b = (float*) malloc(N*sizeof(float));
cPartial = (float*) malloc(blocksPerGrid*sizeof(float));
// initialize arrays
for (i=0; i < N; i++) {
a[i] = 1;
b[i] = 2;
}
// allocate CUDA memory for arrays
int memsize = N*sizeof(float);
int memsizePartial = blocksPerGrid*sizeof(float);
hipMalloc((void**)&devPtrA, memsize);
hipMalloc((void**)&devPtrB, memsize);
hipMalloc((void**)&devPtrCPartial, memsizePartial);
// copy host data to CUDA memory
hipMemcpy(devPtrA, a, memsize, hipMemcpyHostToDevice);
hipMemcpy(devPtrB, b, memsize, hipMemcpyHostToDevice);
// call add function on CUDA GPU
vecDot<<<blocksPerGrid, threadsPerBlock>>>(devPtrA, devPtrB, devPtrCPartial);
// copy results back
hipMemcpy(cPartial, devPtrCPartial, memsizePartial, hipMemcpyDeviceToHost);
// compute final result
c = 0;
for (i=0; i < blocksPerGrid; i++)
c += cPartial[i];
printf("a*b = %f\n", c);
hipFree(devPtrA);
hipFree(devPtrB);
hipFree(devPtrCPartial);
free (a);
free (b);
free (cPartial);
return 0;
} | .text
.file "vecdot.hip"
.globl _Z21__device_stub__vecDotPfS_S_ # -- Begin function _Z21__device_stub__vecDotPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecDotPfS_S_,@function
_Z21__device_stub__vecDotPfS_S_: # @_Z21__device_stub__vecDotPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecDotPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecDotPfS_S_, .Lfunc_end0-_Z21__device_stub__vecDotPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $69632, %edi # imm = 0x11000
callq malloc
movq %rax, %rbx
movl $69632, %edi # imm = 0x11000
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $17408, %rax # imm = 0x4400
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $69632, %esi # imm = 0x11000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $69632, %esi # imm = 0x11000
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $69632, %edx # imm = 0x11000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $69632, %edx # imm = 0x11000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecDotPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addss (%r15,%rax,4), %xmm0
incq %rax
cmpq $16, %rax
jne .LBB1_5
# %bb.6:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecDotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecDotPfS_S_,@object # @_Z6vecDotPfS_S_
.section .rodata,"a",@progbits
.globl _Z6vecDotPfS_S_
.p2align 3, 0x0
_Z6vecDotPfS_S_:
.quad _Z21__device_stub__vecDotPfS_S_
.size _Z6vecDotPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a*b = %f\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecDotPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecDotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecDotPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecDotPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fca00078e0208 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x43ff, PT ; /* 0x000043ff0000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x4400, PT ; /* 0x000044000000780c */
/* 0x000fe20003f06270 */
/*0120*/ FFMA R6, R5, R2, R6 ; /* 0x0000000205067223 */
/* 0x004fd80000000006 */
/*0130*/ @!P0 BRA 0xa0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ STS [R8.X4], R6 ; /* 0x0000000608007388 */
/* 0x0001e20000004800 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01b0*/ @!P1 BRA 0x2a0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01c0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01d0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01e0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01f0*/ @!P1 LEA R2, R3.reuse, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x040fe200078e10ff */
/*0200*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fe20000000000 */
/*0230*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0240*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0250*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x0001e80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0290*/ @P1 BRA 0x1e0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0002 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecDotPfS_S_
.globl _Z6vecDotPfS_S_
.p2align 8
.type _Z6vecDotPfS_S_,@function
_Z6vecDotPfS_S_:
s_load_b32 s3, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x4400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x43ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecDotPfS_S_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecDotPfS_S_, .Lfunc_end0-_Z6vecDotPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecDotPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecDotPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014e1b3_00000000-6_vecdot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecDotPfS_S_PfS_S_
.type _Z29__device_stub__Z6vecDotPfS_S_PfS_S_, @function
_Z29__device_stub__Z6vecDotPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecDotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6vecDotPfS_S_PfS_S_, .-_Z29__device_stub__Z6vecDotPfS_S_PfS_S_
.globl _Z6vecDotPfS_S_
.type _Z6vecDotPfS_S_, @function
_Z6vecDotPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecDotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecDotPfS_S_, .-_Z6vecDotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "a*b = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $69632, %edi
call malloc@PLT
movq %rax, %rbp
movl $69632, %edi
call malloc@PLT
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $69632, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $69632, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $69632, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $69632, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $69632, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rax
leaq 64(%r12), %rdx
pxor %xmm0, %xmm0
.L14:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L14
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6vecDotPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6vecDotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecDotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecdot.hip"
.globl _Z21__device_stub__vecDotPfS_S_ # -- Begin function _Z21__device_stub__vecDotPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecDotPfS_S_,@function
_Z21__device_stub__vecDotPfS_S_: # @_Z21__device_stub__vecDotPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecDotPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecDotPfS_S_, .Lfunc_end0-_Z21__device_stub__vecDotPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $69632, %edi # imm = 0x11000
callq malloc
movq %rax, %rbx
movl $69632, %edi # imm = 0x11000
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $17408, %rax # imm = 0x4400
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $69632, %esi # imm = 0x11000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $69632, %esi # imm = 0x11000
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $69632, %edx # imm = 0x11000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $69632, %edx # imm = 0x11000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecDotPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addss (%r15,%rax,4), %xmm0
incq %rax
cmpq $16, %rax
jne .LBB1_5
# %bb.6:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecDotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecDotPfS_S_,@object # @_Z6vecDotPfS_S_
.section .rodata,"a",@progbits
.globl _Z6vecDotPfS_S_
.p2align 3, 0x0
_Z6vecDotPfS_S_:
.quad _Z21__device_stub__vecDotPfS_S_
.size _Z6vecDotPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a*b = %f\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecDotPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecDotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecDotPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include "intermediateVelocity.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void zeroInside(int *ghostTags, double *value, int points)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= points)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not inside
value[i] = (ghostTags[i] != 0) * value[i];
}
__global__//note dx and dy must be equal and uniform at the point the boundary atm for the second line (forcing for the inside) to work
void updateRHS1_luo_Y(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= nx*(ny-1))
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x) + (nx-1)*ny;
// if not outtag & if not in tag rhs if out tag outside interpolation
rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
}
__global__
void updateRHS1_luo_X(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= (nx-1)*ny)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not outtag & if not in tag rhs if out tag outside interpolation //flag inside interpolation?
//rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
rhs[i] = (ghostTagsUV[i] == -1) * rhs[i];
}
} // end of namespace kernels | code for sm_80
Function : _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x190] ; /* 0x0000640000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e260000002500 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0060*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0203 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee2000c1e1b00 */
/*0100*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0110*/ ISETP.NE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x004fc80003f05270 */
/*0120*/ FSEL R9, RZ, 1.875, P0 ; /* 0x3ff00000ff097808 */
/* 0x000fcc0000000000 */
/*0130*/ DMUL R6, R6, R8 ; /* 0x0000000806067228 */
/* 0x008e0e0000000000 */
/*0140*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R23, SR_TID.X ; /* 0x0000000000177919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR6, c[0x0][0x190] ; /* 0x0000640000067ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIADD3 UR4, UR7, -0x1, URZ ; /* 0xffffffff07047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0050*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe2000f8e023f */
/*0060*/ IMAD R23, R0, c[0x0][0x0], R23 ; /* 0x0000000000177a24 */
/* 0x001fca00078e0217 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fda000bf06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff007624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x8 ; /* 0x00000008ff0c7424 */
/* 0x000fc600078e00ff */
/*00c0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fca0007ffe0ff */
/*00d0*/ IMAD R23, R0, c[0x0][0x194], R23 ; /* 0x0000650000177a24 */
/* 0x000fc800078e0217 */
/*00e0*/ IMAD.WIDE R2, R23, R12, c[0x0][0x180] ; /* 0x0000600017027625 */
/* 0x000fc800078e020c */
/*00f0*/ IMAD.WIDE R8, R23, R12, c[0x0][0x178] ; /* 0x00005e0017087625 */
/* 0x000fe400078e020c */
/*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0110*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.WIDE R6, R23, R4, c[0x0][0x160] ; /* 0x0000580017067625 */
/* 0x000fca00078e0204 */
/*0140*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ee2000c1e1900 */
/*0150*/ IMAD.WIDE R4, R23, R4, c[0x0][0x168] ; /* 0x00005a0017047625 */
/* 0x000fcc00078e0204 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f22000c1e1900 */
/*0170*/ IMAD.WIDE R12, R23, R12, c[0x0][0x170] ; /* 0x00005c00170c7625 */
/* 0x000fca00078e020c */
/*0180*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000162000c1e1b00 */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*01a0*/ BSSY B0, 0x340 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*01b0*/ DADD R20, R2, R8 ; /* 0x0000000002147229 */
/* 0x004e4c0000000008 */
/*01c0*/ MUFU.RCP64H R15, R21 ; /* 0x00000015000f7308 */
/* 0x002e620000001800 */
/*01d0*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x008fe20003f05270 */
/*01e0*/ DFMA R8, -R20, R14, 1 ; /* 0x3ff000001408742b */
/* 0x002e4c000000010e */
/*01f0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x002e4c0000000008 */
/*0200*/ DFMA R8, R14, R8, R14 ; /* 0x000000080e08722b */
/* 0x0022a4000000000e */
/*0210*/ FSEL R15, RZ, 1.875, !P0 ; /* 0x3ff00000ff0f7808 */
/* 0x002fe20004000000 */
/*0220*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0230*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x010fe40003f06270 */
/*0240*/ DFMA R6, -R20, R8, 1 ; /* 0x3ff000001406742b */
/* 0x004e640000000108 */
/*0250*/ ISETP.EQ.AND P0, PT, R0, -0x1, !P0 ; /* 0xffffffff0000780c */
/* 0x000fe40004702270 */
/*0260*/ DMUL R2, R2, R14 ; /* 0x0000000e02027228 */
/* 0x000fc80000000000 */
/*0270*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x002e4c0000000008 */
/*0280*/ DMUL R8, R2, R6 ; /* 0x0000000602087228 */
/* 0x002e620000000000 */
/*0290*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fca0003f2e200 */
/*02a0*/ DFMA R14, -R20, R8, R2 ; /* 0x00000008140e722b */
/* 0x002e4c0000000102 */
/*02b0*/ DFMA R6, R6, R14, R8 ; /* 0x0000000e0606722b */
/* 0x0022a40000000008 */
/*02c0*/ SEL R8, RZ, 0x1, !P0 ; /* 0x00000001ff087807 */
/* 0x002fcc0004000000 */
/*02d0*/ I2F.F64.U32 R8, R8 ; /* 0x0000000800087312 */
/* 0x000e640000201800 */
/*02e0*/ FFMA R0, RZ, R21, R7 ; /* 0x00000015ff007223 */
/* 0x004fca0000000007 */
/*02f0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0300*/ @P0 BRA P1, 0x330 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0310*/ MOV R24, 0x330 ; /* 0x0000033000187802 */
/* 0x003fe40000000f00 */
/*0320*/ CALL.REL.NOINC 0x3b0 ; /* 0x0000008000007944 */
/* 0x020fea0003c00000 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*0340*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fc800078e00ff */
/*0350*/ IMAD.WIDE R2, R23, R2, c[0x0][0x188] ; /* 0x0000620017027625 */
/* 0x000fcc00078e0202 */
/*0360*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*0370*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x004e0c0000000000 */
/*0380*/ DFMA R6, R8, R10, R6 ; /* 0x0000000a0806722b */
/* 0x021e0e0000000006 */
/*0390*/ STG.E.64 [R12.64], R6 ; /* 0x000000060c007986 */
/* 0x001fe2000c101b04 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ FSETP.GEU.AND P0, PT, |R21|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001500780b */
/* 0x040fe20003f0e200 */
/*03c0*/ IMAD.MOV.U32 R4, RZ, RZ, R20.reuse ; /* 0x000000ffff047224 */
/* 0x100fe200078e0014 */
/*03d0*/ LOP3.LUT R6, R21, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff15067812 */
/* 0x000fe200078ec0ff */
/*03e0*/ IMAD.MOV.U32 R5, RZ, RZ, R21 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0015 */
/*03f0*/ FSETP.GEU.AND P2, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f4e200 */
/*0400*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff167424 */
/* 0x000fe200078e00ff */
/*0410*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0420*/ IMAD.MOV.U32 R6, RZ, RZ, R20 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0014 */
/*0430*/ LOP3.LUT R25, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003197812 */
/* 0x000fe200078ec0ff */
/*0440*/ IMAD.MOV.U32 R26, RZ, RZ, 0x1 ; /* 0x00000001ff1a7424 */
/* 0x000fe200078e00ff */
/*0450*/ LOP3.LUT R20, R21, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000015147812 */
/* 0x000fe200078ec0ff */
/*0460*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0002 */
/*0470*/ BSSY B1, 0x970 ; /* 0x000004f000017945 */
/* 0x000fe20003800000 */
/*0480*/ @!P0 DMUL R6, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004068828 */
/* 0x000e220000000000 */
/*0490*/ ISETP.GE.U32.AND P1, PT, R25, R20, PT ; /* 0x000000141900720c */
/* 0x000fc60003f26070 */
/*04a0*/ @!P2 LOP3.LUT R0, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000500a812 */
/* 0x000fe200078ec0ff */
/*04b0*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*04c0*/ MUFU.RCP64H R27, R7 ; /* 0x00000007001b7308 */
/* 0x001e220000001800 */
/*04d0*/ SEL R15, R22.reuse, 0x63400000, !P1 ; /* 0x63400000160f7807 */
/* 0x040fe40004800000 */
/*04e0*/ @!P2 ISETP.GE.U32.AND P3, PT, R25, R0, PT ; /* 0x000000001900a20c */
/* 0x000fe20003f66070 */
/*04f0*/ IMAD.MOV.U32 R0, RZ, RZ, R25 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0019 */
/*0500*/ LOP3.LUT R15, R15, 0x800fffff, R3, 0xf8, !PT ; /* 0x800fffff0f0f7812 */
/* 0x000fe400078ef803 */
/*0510*/ @!P2 SEL R19, R22, 0x63400000, !P3 ; /* 0x634000001613a807 */
/* 0x000fc80005800000 */
/*0520*/ @!P2 LOP3.LUT R19, R19, 0x80000000, R3, 0xf8, !PT ; /* 0x800000001313a812 */
/* 0x000fc800078ef803 */
/*0530*/ @!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313a812 */
/* 0x000fe200078efcff */
/*0540*/ DFMA R16, R26, -R6, 1 ; /* 0x3ff000001a10742b */
/* 0x001e0a0000000806 */
/*0550*/ @!P2 DFMA R14, R14, 2, -R18 ; /* 0x400000000e0ea82b */
/* 0x000fc80000000812 */
/*0560*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0570*/ DFMA R16, R26, R16, R26 ; /* 0x000000101a10722b */
/* 0x001062000000001a */
/*0580*/ @!P2 LOP3.LUT R0, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f00a812 */
/* 0x000fe200078ec0ff */
/*0590*/ IMAD.MOV.U32 R27, RZ, RZ, R20 ; /* 0x000000ffff1b7224 */
/* 0x001fe200078e0014 */
/*05a0*/ @!P0 LOP3.LUT R27, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000071b8812 */
/* 0x000fe400078ec0ff */
/*05b0*/ IADD3 R20, R0, -0x1, RZ ; /* 0xffffffff00147810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ DFMA R18, R16, -R6, 1 ; /* 0x3ff000001012742b */
/* 0x002e220000000806 */
/*05d0*/ IADD3 R26, R27, -0x1, RZ ; /* 0xffffffff1b1a7810 */
/* 0x000fe40007ffe0ff */
/*05e0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*05f0*/ DFMA R16, R16, R18, R16 ; /* 0x000000121010722b */
/* 0x001e220000000010 */
/*0600*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fca0000704470 */
/*0610*/ DMUL R18, R16, R14 ; /* 0x0000000e10127228 */
/* 0x001e0c0000000000 */
/*0620*/ DFMA R20, R18, -R6, R14 ; /* 0x800000061214722b */
/* 0x001e0c000000000e */
/*0630*/ DFMA R20, R16, R20, R18 ; /* 0x000000141014722b */
/* 0x0010620000000012 */
/*0640*/ @P0 BRA 0x810 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0650*/ LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005027812 */
/* 0x000fc800078ec0ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R25.reuse, R2, PT ; /* 0x000000021900720c */
/* 0x040fe20003f06070 */
/*0670*/ IMAD.IADD R0, R25, 0x1, -R2 ; /* 0x0000000119007824 */
/* 0x000fe400078e0a02 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0690*/ SEL R3, R22, 0x63400000, !P0 ; /* 0x6340000016037807 */
/* 0x000fe40004000000 */
/*06a0*/ IMNMX R0, R0, -0x46a00000, !PT ; /* 0xb960000000007817 */
/* 0x000fc80007800200 */
/*06b0*/ IMNMX R0, R0, 0x46a00000, PT ; /* 0x46a0000000007817 */
/* 0x000fca0003800200 */
/*06c0*/ IMAD.IADD R0, R0, 0x1, -R3 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a03 */
/*06d0*/ IADD3 R3, R0, 0x7fe00000, RZ ; /* 0x7fe0000000037810 */
/* 0x000fcc0007ffe0ff */
/*06e0*/ DMUL R16, R20, R2 ; /* 0x0000000214107228 */
/* 0x003e140000000000 */
/*06f0*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x001fda0003f0c200 */
/*0700*/ @P0 BRA 0x960 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0710*/ DFMA R6, R20, -R6, R14 ; /* 0x800000061406722b */
/* 0x000e22000000000e */
/*0720*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd200078e00ff */
/*0730*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0740*/ LOP3.LUT R15, R7, 0x80000000, R5, 0x48, !PT ; /* 0x80000000070f7812 */
/* 0x000fc800078e4805 */
/*0750*/ LOP3.LUT R3, R15, R3, RZ, 0xfc, !PT ; /* 0x000000030f037212 */
/* 0x000fce00078efcff */
/*0760*/ @!P0 BRA 0x960 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD.MOV R5, RZ, RZ, -R0 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a00 */
/*0780*/ DMUL.RP R2, R20, R2 ; /* 0x0000000214027228 */
/* 0x000e220000008000 */
/*0790*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*07a0*/ DFMA R4, R16, -R4, R20 ; /* 0x800000041004722b */
/* 0x000e460000000014 */
/*07b0*/ LOP3.LUT R15, R3, R15, RZ, 0x3c, !PT ; /* 0x0000000f030f7212 */
/* 0x001fc600078e3cff */
/*07c0*/ IADD3 R4, -R0, -0x43300000, RZ ; /* 0xbcd0000000047810 */
/* 0x002fc80007ffe1ff */
/*07d0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*07e0*/ FSEL R16, R2, R16, !P0 ; /* 0x0000001002107208 */
/* 0x000fe40004000000 */
/*07f0*/ FSEL R17, R15, R17, !P0 ; /* 0x000000110f117208 */
/* 0x000fe20004000000 */
/*0800*/ BRA 0x960 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0810*/ DSETP.NAN.AND P0, PT, R2, R2, PT ; /* 0x000000020200722a */
/* 0x000e9c0003f08000 */
/*0820*/ @P0 BRA 0x940 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0830*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0840*/ @P0 BRA 0x910 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0850*/ ISETP.NE.AND P0, PT, R0, R27, PT ; /* 0x0000001b0000720c */
/* 0x000fe20003f05270 */
/*0860*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x001fe400078e00ff */
/*0870*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ; /* 0xfff80000ff117424 */
/* 0x000fd400078e00ff */
/*0880*/ @!P0 BRA 0x960 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0890*/ ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fe40003f05270 */
/*08a0*/ LOP3.LUT R17, R3, 0x80000000, R5, 0x48, !PT ; /* 0x8000000003117812 */
/* 0x000fe400078e4805 */
/*08b0*/ ISETP.EQ.OR P0, PT, R27, RZ, !P0 ; /* 0x000000ff1b00720c */
/* 0x000fda0004702670 */
/*08c0*/ @P0 LOP3.LUT R0, R17, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000011000812 */
/* 0x000fe200078efcff */
/*08d0*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff108224 */
/* 0x000fe400078e00ff */
/*08e0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff100224 */
/* 0x000fe400078e00ff */
/*08f0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R0 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0000 */
/*0900*/ BRA 0x960 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0910*/ LOP3.LUT R17, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005117812 */
/* 0x001fe200078efcff */
/*0920*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0004 */
/*0930*/ BRA 0x960 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R17, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000003117812 */
/* 0x001fe200078efcff */
/*0950*/ IMAD.MOV.U32 R16, RZ, RZ, R2 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0002 */
/*0960*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0970*/ IMAD.MOV.U32 R25, RZ, RZ, 0x0 ; /* 0x00000000ff197424 */
/* 0x000fe400078e00ff */
/*0980*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0010 */
/*0990*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0011 */
/*09a0*/ RET.REL.NODEC R24 0x0 ; /* 0xfffff65018007950 */
/* 0x000fec0003c3ffff */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN7kernels10zeroInsideEPiPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0203 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00c0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee2000c1e1b00 */
/*00d0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc80003f05270 */
/*00f0*/ FSEL R9, RZ, 1.875, !P0 ; /* 0x3ff00000ff097808 */
/* 0x000fcc0004000000 */
/*0100*/ DMUL R6, R6, R8 ; /* 0x0000000806067228 */
/* 0x008e0e0000000000 */
/*0110*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include "intermediateVelocity.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void zeroInside(int *ghostTags, double *value, int points)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= points)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not inside
value[i] = (ghostTags[i] != 0) * value[i];
}
__global__//note dx and dy must be equal and uniform at the point the boundary atm for the second line (forcing for the inside) to work
void updateRHS1_luo_Y(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= nx*(ny-1))
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x) + (nx-1)*ny;
// if not outtag & if not in tag rhs if out tag outside interpolation
rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
}
__global__
void updateRHS1_luo_X(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= (nx-1)*ny)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not outtag & if not in tag rhs if out tag outside interpolation //flag inside interpolation?
//rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
rhs[i] = (ghostTagsUV[i] == -1) * rhs[i];
}
} // end of namespace kernels | .file "tmpxft_000aa6f3_00000000-6_intermediateVelocity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi
.type _Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi, @function
_Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN7kernels10zeroInsideEPiPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi, .-_Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi
.globl _ZN7kernels10zeroInsideEPiPdi
.type _ZN7kernels10zeroInsideEPiPdi, @function
_ZN7kernels10zeroInsideEPiPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN7kernels10zeroInsideEPiPdi, .-_ZN7kernels10zeroInsideEPiPdi
.globl _Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
.type _Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii, @function
_Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii, .-_Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
.globl _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.type _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, @function
_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, .-_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.globl _Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
.type _Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii, @function
_Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii, .-_Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
.globl _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.type _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, @function
_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, .-_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii"
.align 8
.LC1:
.string "_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_ZN7kernels10zeroInsideEPiPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels10zeroInsideEPiPdi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include "intermediateVelocity.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void zeroInside(int *ghostTags, double *value, int points)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= points)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not inside
value[i] = (ghostTags[i] != 0) * value[i];
}
__global__//note dx and dy must be equal and uniform at the point the boundary atm for the second line (forcing for the inside) to work
void updateRHS1_luo_Y(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= nx*(ny-1))
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x) + (nx-1)*ny;
// if not outtag & if not in tag rhs if out tag outside interpolation
rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
}
__global__
void updateRHS1_luo_X(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= (nx-1)*ny)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not outtag & if not in tag rhs if out tag outside interpolation //flag inside interpolation?
//rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
rhs[i] = (ghostTagsUV[i] == -1) * rhs[i];
}
} // end of namespace kernels | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include <hip/hip_runtime.h>
#include "intermediateVelocity.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void zeroInside(int *ghostTags, double *value, int points)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= points)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not inside
value[i] = (ghostTags[i] != 0) * value[i];
}
__global__//note dx and dy must be equal and uniform at the point the boundary atm for the second line (forcing for the inside) to work
void updateRHS1_luo_Y(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= nx*(ny-1))
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x) + (nx-1)*ny;
// if not outtag & if not in tag rhs if out tag outside interpolation
rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
}
__global__
void updateRHS1_luo_X(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= (nx-1)*ny)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not outtag & if not in tag rhs if out tag outside interpolation //flag inside interpolation?
//rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
rhs[i] = (ghostTagsUV[i] == -1) * rhs[i];
}
} // end of namespace kernels |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include <hip/hip_runtime.h>
#include "intermediateVelocity.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void zeroInside(int *ghostTags, double *value, int points)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= points)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not inside
value[i] = (ghostTags[i] != 0) * value[i];
}
__global__//note dx and dy must be equal and uniform at the point the boundary atm for the second line (forcing for the inside) to work
void updateRHS1_luo_Y(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= nx*(ny-1))
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x) + (nx-1)*ny;
// if not outtag & if not in tag rhs if out tag outside interpolation
rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
}
__global__
void updateRHS1_luo_X(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= (nx-1)*ny)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not outtag & if not in tag rhs if out tag outside interpolation //flag inside interpolation?
//rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
rhs[i] = (ghostTagsUV[i] == -1) * rhs[i];
}
} // end of namespace kernels | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _ZN7kernels10zeroInsideEPiPdi
.globl _ZN7kernels10zeroInsideEPiPdi
.p2align 8
.type _ZN7kernels10zeroInsideEPiPdi,@function
_ZN7kernels10zeroInsideEPiPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[3:4], off
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
v_mov_b32_e32 v4, 0
v_cndmask_b32_e64 v5, 0, 0x3ff00000, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN7kernels10zeroInsideEPiPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _ZN7kernels10zeroInsideEPiPdi, .Lfunc_end0-_ZN7kernels10zeroInsideEPiPdi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.globl _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.p2align 8
.type _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii,@function
_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_add_i32 s4, s3, -1
s_mul_i32 s4, s4, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_2
s_add_i32 s2, s2, -1
s_load_b256 s[4:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v3, vcc_lo
global_load_b32 v18, v[4:5], off
global_load_b64 v[4:5], v[6:7], off
global_load_b64 v[6:7], v[8:9], off
v_mov_b32_e32 v8, 0
s_waitcnt vmcnt(2)
v_cmp_ne_u32_e32 vcc_lo, -1, v18
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[4:5], v[6:7]
v_cndmask_b32_e64 v9, 0, 0x3ff00000, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mul_f64 v[4:5], v[4:5], v[8:9]
global_load_b32 v19, v[0:1], off
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[14:15], v[2:3], off
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[12:13], v[10:11]
v_fma_f64 v[8:9], -v[8:9], v[16:17], v[12:13]
s_waitcnt vmcnt(2)
v_cmp_gt_i32_e64 s0, 1, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
v_cmp_eq_u32_e32 vcc_lo, -1, v18
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
v_cndmask_b32_e64 v6, 0, 1, s0
v_cvt_f64_u32_e32 v[6:7], v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], v[4:5]
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], v[14:15], v[6:7], v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, .Lfunc_end1-_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.globl _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.p2align 8
.type _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii,@function
_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_add_i32 s2, s2, -1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mul_i32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[3:4], off
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(1)
v_cmp_eq_u32_e32 vcc_lo, -1, v4
v_mov_b32_e32 v4, 0
v_cndmask_b32_e64 v5, 0, 0x3ff00000, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, .Lfunc_end2-_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN7kernels10zeroInsideEPiPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN7kernels10zeroInsideEPiPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include <hip/hip_runtime.h>
#include "intermediateVelocity.h"
/**
* \namespace kernels
* \brief Contains all the custom-written CUDA kernels.
*/
namespace kernels
{
__global__
void zeroInside(int *ghostTags, double *value, int points)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= points)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not inside
value[i] = (ghostTags[i] != 0) * value[i];
}
__global__//note dx and dy must be equal and uniform at the point the boundary atm for the second line (forcing for the inside) to work
void updateRHS1_luo_Y(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= nx*(ny-1))
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x) + (nx-1)*ny;
// if not outtag & if not in tag rhs if out tag outside interpolation
rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
}
__global__
void updateRHS1_luo_X(int *hybridTagsUV, int *ghostTagsUV, double *rhs, double *distance_from_intersection_to_node, double *distance_between_nodes_at_IB, double *uv, int nx, int ny)
{
if (threadIdx.x + (blockDim.x * blockIdx.x) >= (nx-1)*ny)
return;
int i = threadIdx.x + (blockDim.x * blockIdx.x);
// if not outtag & if not in tag rhs if out tag outside interpolation //flag inside interpolation?
//rhs[i] = (hybridTagsUV[i]==-1) * (ghostTagsUV[i]<=0) * (rhs[i]) + (hybridTagsUV[i]!=-1) * distance_between_nodes_at_IB[i]/(distance_from_intersection_to_node[i]+distance_between_nodes_at_IB[i]) * uv[i];
rhs[i] = (ghostTagsUV[i] == -1) * rhs[i];
}
} // end of namespace kernels | .text
.file "intermediateVelocity.hip"
.globl _ZN7kernels25__device_stub__zeroInsideEPiPdi # -- Begin function _ZN7kernels25__device_stub__zeroInsideEPiPdi
.p2align 4, 0x90
.type _ZN7kernels25__device_stub__zeroInsideEPiPdi,@function
_ZN7kernels25__device_stub__zeroInsideEPiPdi: # @_ZN7kernels25__device_stub__zeroInsideEPiPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN7kernels10zeroInsideEPiPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _ZN7kernels25__device_stub__zeroInsideEPiPdi, .Lfunc_end0-_ZN7kernels25__device_stub__zeroInsideEPiPdi
.cfi_endproc
# -- End function
.globl _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii # -- Begin function _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.p2align 4, 0x90
.type _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii,@function
_ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii: # @_ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, .Lfunc_end1-_ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.cfi_endproc
# -- End function
.globl _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii # -- Begin function _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.p2align 4, 0x90
.type _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii,@function
_ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii: # @_ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, .Lfunc_end2-_ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels10zeroInsideEPiPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN7kernels10zeroInsideEPiPdi,@object # @_ZN7kernels10zeroInsideEPiPdi
.section .rodata,"a",@progbits
.globl _ZN7kernels10zeroInsideEPiPdi
.p2align 3, 0x0
_ZN7kernels10zeroInsideEPiPdi:
.quad _ZN7kernels25__device_stub__zeroInsideEPiPdi
.size _ZN7kernels10zeroInsideEPiPdi, 8
.type _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii,@object # @_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.globl _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.p2align 3, 0x0
_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii:
.quad _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.size _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, 8
.type _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii,@object # @_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.globl _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.p2align 3, 0x0
_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii:
.quad _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.size _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN7kernels10zeroInsideEPiPdi"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii"
.size .L__unnamed_2, 49
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii"
.size .L__unnamed_3, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN7kernels25__device_stub__zeroInsideEPiPdi
.addrsig_sym _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.addrsig_sym _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN7kernels10zeroInsideEPiPdi
.addrsig_sym _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.addrsig_sym _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aa6f3_00000000-6_intermediateVelocity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi
.type _Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi, @function
_Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN7kernels10zeroInsideEPiPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi, .-_Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi
.globl _ZN7kernels10zeroInsideEPiPdi
.type _ZN7kernels10zeroInsideEPiPdi, @function
_ZN7kernels10zeroInsideEPiPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__ZN7kernels10zeroInsideEPiPdiPiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN7kernels10zeroInsideEPiPdi, .-_ZN7kernels10zeroInsideEPiPdi
.globl _Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
.type _Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii, @function
_Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii, .-_Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
.globl _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.type _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, @function
_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z62__device_stub__ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, .-_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.globl _Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
.type _Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii, @function
_Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii, .-_Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
.globl _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.type _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, @function
_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z62__device_stub__ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_iiPiS_PdS0_S0_S0_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, .-_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii"
.align 8
.LC1:
.string "_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_ZN7kernels10zeroInsideEPiPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN7kernels10zeroInsideEPiPdi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "intermediateVelocity.hip"
.globl _ZN7kernels25__device_stub__zeroInsideEPiPdi # -- Begin function _ZN7kernels25__device_stub__zeroInsideEPiPdi
.p2align 4, 0x90
.type _ZN7kernels25__device_stub__zeroInsideEPiPdi,@function
_ZN7kernels25__device_stub__zeroInsideEPiPdi: # @_ZN7kernels25__device_stub__zeroInsideEPiPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN7kernels10zeroInsideEPiPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _ZN7kernels25__device_stub__zeroInsideEPiPdi, .Lfunc_end0-_ZN7kernels25__device_stub__zeroInsideEPiPdi
.cfi_endproc
# -- End function
.globl _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii # -- Begin function _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.p2align 4, 0x90
.type _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii,@function
_ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii: # @_ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, .Lfunc_end1-_ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.cfi_endproc
# -- End function
.globl _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii # -- Begin function _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.p2align 4, 0x90
.type _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii,@function
_ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii: # @_ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, .Lfunc_end2-_ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels10zeroInsideEPiPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN7kernels10zeroInsideEPiPdi,@object # @_ZN7kernels10zeroInsideEPiPdi
.section .rodata,"a",@progbits
.globl _ZN7kernels10zeroInsideEPiPdi
.p2align 3, 0x0
_ZN7kernels10zeroInsideEPiPdi:
.quad _ZN7kernels25__device_stub__zeroInsideEPiPdi
.size _ZN7kernels10zeroInsideEPiPdi, 8
.type _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii,@object # @_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.globl _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.p2align 3, 0x0
_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii:
.quad _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.size _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii, 8
.type _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii,@object # @_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.globl _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.p2align 3, 0x0
_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii:
.quad _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.size _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN7kernels10zeroInsideEPiPdi"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii"
.size .L__unnamed_2, 49
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii"
.size .L__unnamed_3, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN7kernels25__device_stub__zeroInsideEPiPdi
.addrsig_sym _ZN7kernels31__device_stub__updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.addrsig_sym _ZN7kernels31__device_stub__updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN7kernels10zeroInsideEPiPdi
.addrsig_sym _ZN7kernels16updateRHS1_luo_YEPiS0_PdS1_S1_S1_ii
.addrsig_sym _ZN7kernels16updateRHS1_luo_XEPiS0_PdS1_S1_S1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <pthread.h>
#define MAX_THREAD 24
/*
0123456789
0 oooooooooo
1 o@@@@@@@@o Problem solving example
2 o@@@@@@@@o 8 * 6 matrix
3 o@@@@@@@@o + 1px padding around matrix
4 o@@@@@@@@o
5 o@@@@@@@@o
6 o@@@@@@@@o
7 oooooooooo
*/
int nprocs, display, gen, width, height;
int** arr;
int** tmp;
pthread_barrier_t tbarrier;
struct timespec begin, end;
//CUDA and Thread
void dump();
//single & multi thread
int setPixel(int x, int y);
void* Thread(void *args);
void nextGenPixel(int start, int end, int width);
void copyAndResetData(int start, int end, int width);
typedef struct{
int start;
int end;
} bound;
__device__ int cudaNeighbor(int *mem, int index, int width){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = mem[index];
int neighbor = mem[index-width-1]+mem[index-width]+mem[index-width+1]+
mem[index-1]+mem[index+1]+mem[index+width-1]+mem[index+width]+mem[index+width+1];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
__global__ void my_kernel(int *cuda_mem, int *cuda_tmp, int height, int width, int gen){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(blockIdx.x == 0 || blockIdx.x == height-1 || threadIdx.x == 0 || threadIdx.x == width-1){
//Do nothing
}else{
cuda_tmp[index] = cudaNeighbor(cuda_mem, index, width);
}
cuda_mem[index] = cuda_tmp[index];
cuda_tmp[index] = 0;
}
int main(int argc, char *argv[]){
pthread_t thread[MAX_THREAD];
FILE *fp;
char buffer[20];
int x, y, size;
//This is for convert 2d array to 1d
int *mat_1d, *mat_1d_tmp;
int *cuda_mem, *cuda_tmp;
char *x_map, *y_map;
if(argc!=7){
printf("Parameter Error!\n");
printf("./glife <input file> <display> <nprocs> <# of generation> <width> <height>\n");
exit(1);
}
display = atoi(argv[2]);
nprocs = atoi(argv[3]);
gen = atoi(argv[4]);
width = atoi(argv[5]);
height = atoi(argv[6]);
//Make matrix
arr = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
arr[i] = (int*)malloc(sizeof(int) * (width+2));
}
tmp = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
tmp[i] = (int*)malloc(sizeof(int) * (width+2));
}
//length = (height+2) * (width+2);
size = (height+2) * (width+2) * sizeof(int);
mat_1d = (int*)malloc(size);
mat_1d_tmp = (int*)malloc(size);
//Initialize
for(int a=0; a<height+2; a++){
for(int b=0; b<width+2; b++){
arr[a][b] = 0;
tmp[a][b] = 0;
mat_1d[a*(width+2)+b] = 0;
mat_1d_tmp[a*(width+2)+b] = 0;
}
}
if((fp=fopen(argv[1],"r")) == NULL){
fprintf(stderr, "error");
exit(2);
}
//Mapping
while(fgets(buffer, 20, fp) != NULL){
y_map = strtok(buffer, " ");
x_map = strtok(NULL, " ");
y = atoi(y_map);
x = atoi(x_map);
arr[x][y] = 1;
mat_1d[x*(width+2) +y] = 1;
}
if(nprocs == 0){
//CUDA
clock_gettime(CLOCK_MONOTONIC, &begin);
cudaMalloc(&cuda_mem, size);
cudaMalloc(&cuda_tmp, size);
cudaMemcpy(cuda_mem, mat_1d, size, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_tmp, mat_1d_tmp, size, cudaMemcpyHostToDevice);
for(int i=0; i<gen; i++){
//Kernel code
my_kernel<<< height+2 , width+2 >>>(cuda_mem, cuda_tmp, height+2, width+2, gen);
cudaDeviceSynchronize();
}
cudaMemcpy(mat_1d, cuda_mem, size, cudaMemcpyDeviceToHost);
cudaMemcpy(mat_1d_tmp, cuda_tmp, size, cudaMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &end);
for(int i=0;i<height+2;i++){
for(int j=0;j<width+2;j++){
arr[i][j] = mat_1d[i*(width+2) +j ];
}
}
}else{
//SINGLE AND MULTI THREAD
//Divide height into nprocs pieces
bound section[MAX_THREAD];
int x = 0;
int y = 0;
int div = height/nprocs;
for(int k=0; k<nprocs; k++){
if(k == (nprocs-1)){
y = height;
section[k].start = x;
section[k].end = y;
}else{
y+=div;
section[k].start = x;
section[k].end = y;
x+=div;
}
}
pthread_barrier_init(&tbarrier, NULL, nprocs);
clock_gettime(CLOCK_MONOTONIC, &begin);
for(int i=0; i<nprocs; i++){
pthread_create(&thread[i], NULL, Thread, §ion[i]);
}
for(int j=0; j<nprocs; j++){
pthread_join(thread[j], NULL);
}
clock_gettime(CLOCK_MONOTONIC, &end);
pthread_barrier_destroy(&tbarrier);
}
printf("Execution time : %2.3f sec\n",(end.tv_sec - begin.tv_sec)+(end.tv_nsec-begin.tv_nsec)/1000000000.0);
if(display == 1){
dump();
}
free(arr);
free(tmp);
free(mat_1d);
free(mat_1d_tmp);
cudaFree(cuda_mem);
cudaFree(cuda_tmp);
return 0;
}
void *Thread(void *args){
//get args with struct
bound *section = (bound*)args;
for(int i=0; i<gen; i++){
nextGenPixel(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
copyAndResetData(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
}
}
void nextGenPixel(int start, int end, int wdth){
int head = start;
int tail = end;
if(head == 0){
head = 1;
}
if(tail == height){
tail++;
}
for(int i=head; i<tail; i++){
for(int j=1; j<=wdth; j++){
tmp[i][j]=setPixel(i,j);
}
}
}
void copyAndResetData(int start, int end, int wdth){
int tail = end;
if(tail == height){
tail +=2;
}
for(int a=start; a<tail; a++){
for(int b=0; b<wdth+2; b++){
arr[a][b] = tmp[a][b];
tmp[a][b] = 0;
}
}
}
int setPixel(int x, int y){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = arr[x][y];
int neighbor = arr[x-1][y-1]+arr[x][y-1]+arr[x+1][y-1]+arr[x+1][y]+arr[x+1][y+1]+arr[x][y+1]+arr[x-1][y+1]+arr[x-1][y];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
void dump(){
// print arr info
printf("%d x %d matrix\n", width, height);
printf("========================================\n");
for(int a=1; a<=height; a++){
for(int b=1; b<=width; b++){
if(arr[a][b]==1){
printf("o");
}else{
printf("-");
}
}
printf("\n");
}
printf("========================================\n");
} | code for sm_80
Function : _Z9my_kernelPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0030*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe2000fffe13f */
/*0070*/ BSSY B0, 0x360 ; /* 0x000002e000007945 */
/* 0x000fea0003800000 */
/*0080*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf05270 */
/*0090*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fc6000fffe13f */
/*00a0*/ ISETP.EQ.OR P0, PT, R0.reuse, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x040fe20004702670 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fe200078e0203 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fe20000702670 */
/*00e0*/ IMAD.WIDE R4, R0, R17, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc600078e0211 */
/*00f0*/ ISETP.EQ.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fe20008702670 */
/*0100*/ IMAD.WIDE R2, R0, R17, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fd800078e0211 */
/*0110*/ @P0 BRA 0x340 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*0120*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe20000000800 */
/*0130*/ IADD3 R8, R0.reuse, -c[0x0][0x174], RZ ; /* 0x80005d0000087a10 */
/* 0x040fe20007ffe0ff */
/*0140*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fe2000f8e333f */
/*0150*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011400 */
/*0160*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000406020e7981 */
/* 0x000ea2000c1e1900 */
/*0170*/ LEA R12, P0, R0, c[0x0][0x160], 0x2 ; /* 0x00005800000c7a11 */
/* 0x000fe200078010ff */
/*0180*/ IMAD.WIDE R8, R8, R17, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe400078e0211 */
/*0190*/ IADD3 R6, R0.reuse, UR5, RZ ; /* 0x0000000500067c10 */
/* 0x040fe4000fffe0ff */
/*01a0*/ IADD3 R10, R0, UR4, RZ ; /* 0x00000004000a7c10 */
/* 0x000fc4000fffe0ff */
/*01b0*/ LEA.HI.X R13, R0, c[0x0][0x164], R11, 0x2, P0 ; /* 0x00005900000d7a11 */
/* 0x000fe200000f140b */
/*01c0*/ IMAD.WIDE R6, R6, R17.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe200078e0211 */
/*01d0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x0000e8000c1e1900 */
/*01e0*/ LDG.E R15, [R6.64] ; /* 0x00000006060f7981 */
/* 0x000ee2000c1e1900 */
/*01f0*/ IMAD.WIDE R10, R10, R17, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc600078e0211 */
/*0200*/ LDG.E R0, [R6.64+0x8] ; /* 0x0000080606007981 */
/* 0x000ee2000c1e1900 */
/*0210*/ IMAD.WIDE R12, R17, c[0x0][0x174], R12 ; /* 0x00005d00110c7a25 */
/* 0x000fc600078e020c */
/*0220*/ LDG.E R17, [R2.64+-0x4] ; /* 0xfffffc0602117981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R16, [R12.64] ; /* 0x000000060c107981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004060c137981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x001f62000c1e1900 */
/*0270*/ IADD3 R0, R0, R8, R15 ; /* 0x0000000800007210 */
/* 0x008fc80007ffe00f */
/*0280*/ IADD3 R0, R14, R0, R17 ; /* 0x000000000e007210 */
/* 0x004fc80007ffe011 */
/*0290*/ IADD3 R0, R16, R0, R11 ; /* 0x0000000010007210 */
/* 0x010fca0007ffe00b */
/*02a0*/ IMAD.IADD R0, R0, 0x1, R19 ; /* 0x0000000100007824 */
/* 0x020fca00078e0213 */
/*02b0*/ LOP3.LUT R6, R0.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x0000000100067812 */
/* 0x040fe400078efcff */
/*02c0*/ ISETP.NE.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f05270 */
/*02d0*/ ISETP.NE.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f25270 */
/*02e0*/ ISETP.EQ.AND P0, PT, R9.reuse, RZ, !P0 ; /* 0x000000ff0900720c */
/* 0x040fe40004702270 */
/*02f0*/ ISETP.EQ.AND P1, PT, R9, 0x1, !P1 ; /* 0x000000010900780c */
/* 0x000fc80004f22270 */
/*0300*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80000703570 */
/*0310*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0320*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101906 */
/*0330*/ BRA 0x350 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000164000c1e1900 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x020fe8000c101906 */
/*0370*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101906 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <pthread.h>
#define MAX_THREAD 24
/*
0123456789
0 oooooooooo
1 o@@@@@@@@o Problem solving example
2 o@@@@@@@@o 8 * 6 matrix
3 o@@@@@@@@o + 1px padding around matrix
4 o@@@@@@@@o
5 o@@@@@@@@o
6 o@@@@@@@@o
7 oooooooooo
*/
int nprocs, display, gen, width, height;
int** arr;
int** tmp;
pthread_barrier_t tbarrier;
struct timespec begin, end;
//CUDA and Thread
void dump();
//single & multi thread
int setPixel(int x, int y);
void* Thread(void *args);
void nextGenPixel(int start, int end, int width);
void copyAndResetData(int start, int end, int width);
typedef struct{
int start;
int end;
} bound;
__device__ int cudaNeighbor(int *mem, int index, int width){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = mem[index];
int neighbor = mem[index-width-1]+mem[index-width]+mem[index-width+1]+
mem[index-1]+mem[index+1]+mem[index+width-1]+mem[index+width]+mem[index+width+1];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
__global__ void my_kernel(int *cuda_mem, int *cuda_tmp, int height, int width, int gen){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(blockIdx.x == 0 || blockIdx.x == height-1 || threadIdx.x == 0 || threadIdx.x == width-1){
//Do nothing
}else{
cuda_tmp[index] = cudaNeighbor(cuda_mem, index, width);
}
cuda_mem[index] = cuda_tmp[index];
cuda_tmp[index] = 0;
}
int main(int argc, char *argv[]){
pthread_t thread[MAX_THREAD];
FILE *fp;
char buffer[20];
int x, y, size;
//This is for convert 2d array to 1d
int *mat_1d, *mat_1d_tmp;
int *cuda_mem, *cuda_tmp;
char *x_map, *y_map;
if(argc!=7){
printf("Parameter Error!\n");
printf("./glife <input file> <display> <nprocs> <# of generation> <width> <height>\n");
exit(1);
}
display = atoi(argv[2]);
nprocs = atoi(argv[3]);
gen = atoi(argv[4]);
width = atoi(argv[5]);
height = atoi(argv[6]);
//Make matrix
arr = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
arr[i] = (int*)malloc(sizeof(int) * (width+2));
}
tmp = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
tmp[i] = (int*)malloc(sizeof(int) * (width+2));
}
//length = (height+2) * (width+2);
size = (height+2) * (width+2) * sizeof(int);
mat_1d = (int*)malloc(size);
mat_1d_tmp = (int*)malloc(size);
//Initialize
for(int a=0; a<height+2; a++){
for(int b=0; b<width+2; b++){
arr[a][b] = 0;
tmp[a][b] = 0;
mat_1d[a*(width+2)+b] = 0;
mat_1d_tmp[a*(width+2)+b] = 0;
}
}
if((fp=fopen(argv[1],"r")) == NULL){
fprintf(stderr, "error");
exit(2);
}
//Mapping
while(fgets(buffer, 20, fp) != NULL){
y_map = strtok(buffer, " ");
x_map = strtok(NULL, " ");
y = atoi(y_map);
x = atoi(x_map);
arr[x][y] = 1;
mat_1d[x*(width+2) +y] = 1;
}
if(nprocs == 0){
//CUDA
clock_gettime(CLOCK_MONOTONIC, &begin);
cudaMalloc(&cuda_mem, size);
cudaMalloc(&cuda_tmp, size);
cudaMemcpy(cuda_mem, mat_1d, size, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_tmp, mat_1d_tmp, size, cudaMemcpyHostToDevice);
for(int i=0; i<gen; i++){
//Kernel code
my_kernel<<< height+2 , width+2 >>>(cuda_mem, cuda_tmp, height+2, width+2, gen);
cudaDeviceSynchronize();
}
cudaMemcpy(mat_1d, cuda_mem, size, cudaMemcpyDeviceToHost);
cudaMemcpy(mat_1d_tmp, cuda_tmp, size, cudaMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &end);
for(int i=0;i<height+2;i++){
for(int j=0;j<width+2;j++){
arr[i][j] = mat_1d[i*(width+2) +j ];
}
}
}else{
//SINGLE AND MULTI THREAD
//Divide height into nprocs pieces
bound section[MAX_THREAD];
int x = 0;
int y = 0;
int div = height/nprocs;
for(int k=0; k<nprocs; k++){
if(k == (nprocs-1)){
y = height;
section[k].start = x;
section[k].end = y;
}else{
y+=div;
section[k].start = x;
section[k].end = y;
x+=div;
}
}
pthread_barrier_init(&tbarrier, NULL, nprocs);
clock_gettime(CLOCK_MONOTONIC, &begin);
for(int i=0; i<nprocs; i++){
pthread_create(&thread[i], NULL, Thread, §ion[i]);
}
for(int j=0; j<nprocs; j++){
pthread_join(thread[j], NULL);
}
clock_gettime(CLOCK_MONOTONIC, &end);
pthread_barrier_destroy(&tbarrier);
}
printf("Execution time : %2.3f sec\n",(end.tv_sec - begin.tv_sec)+(end.tv_nsec-begin.tv_nsec)/1000000000.0);
if(display == 1){
dump();
}
free(arr);
free(tmp);
free(mat_1d);
free(mat_1d_tmp);
cudaFree(cuda_mem);
cudaFree(cuda_tmp);
return 0;
}
void *Thread(void *args){
//get args with struct
bound *section = (bound*)args;
for(int i=0; i<gen; i++){
nextGenPixel(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
copyAndResetData(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
}
}
void nextGenPixel(int start, int end, int wdth){
int head = start;
int tail = end;
if(head == 0){
head = 1;
}
if(tail == height){
tail++;
}
for(int i=head; i<tail; i++){
for(int j=1; j<=wdth; j++){
tmp[i][j]=setPixel(i,j);
}
}
}
void copyAndResetData(int start, int end, int wdth){
int tail = end;
if(tail == height){
tail +=2;
}
for(int a=start; a<tail; a++){
for(int b=0; b<wdth+2; b++){
arr[a][b] = tmp[a][b];
tmp[a][b] = 0;
}
}
}
int setPixel(int x, int y){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = arr[x][y];
int neighbor = arr[x-1][y-1]+arr[x][y-1]+arr[x+1][y-1]+arr[x+1][y]+arr[x+1][y+1]+arr[x][y+1]+arr[x-1][y+1]+arr[x-1][y];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
void dump(){
// print arr info
printf("%d x %d matrix\n", width, height);
printf("========================================\n");
for(int a=1; a<=height; a++){
for(int b=1; b<=width; b++){
if(arr[a][b]==1){
printf("o");
}else{
printf("-");
}
}
printf("\n");
}
printf("========================================\n");
} | .file "tmpxft_001a9c58_00000000-6_gameoflife.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12cudaNeighborPiii
.type _Z12cudaNeighborPiii, @function
_Z12cudaNeighborPiii:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z12cudaNeighborPiii, .-_Z12cudaNeighborPiii
.globl _Z16copyAndResetDataiii
.type _Z16copyAndResetDataiii, @function
_Z16copyAndResetDataiii:
.LFB2071:
.cfi_startproc
endbr64
movl %edx, %r9d
cmpl %esi, height(%rip)
je .L14
.L6:
cmpl %edi, %esi
jle .L5
movslq %edi, %rax
leaq 0(,%rax,8), %rdx
subl %edi, %esi
leaq (%rsi,%rax), %r8
salq $3, %r8
leal 1(%r9), %eax
leaq 4(,%rax,4), %rdi
jmp .L8
.L14:
addl $2, %esi
jmp .L6
.L9:
movq tmp(%rip), %rcx
movq (%rcx,%rdx), %rcx
movl (%rcx,%rax), %esi
movq arr(%rip), %rcx
movq (%rcx,%rdx), %rcx
movl %esi, (%rcx,%rax)
movq tmp(%rip), %rcx
movq (%rcx,%rdx), %rcx
movl $0, (%rcx,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L9
.L10:
addq $8, %rdx
cmpq %r8, %rdx
je .L5
.L8:
movl $0, %eax
cmpl $-1, %r9d
jge .L9
jmp .L10
.L5:
ret
.cfi_endproc
.LFE2071:
.size _Z16copyAndResetDataiii, .-_Z16copyAndResetDataiii
.globl _Z8setPixelii
.type _Z8setPixelii, @function
_Z8setPixelii:
.LFB2072:
.cfi_startproc
endbr64
movq arr(%rip), %rdx
movslq %edi, %rdi
leaq 0(,%rdi,8), %r8
movq (%rdx,%rdi,8), %rdi
movslq %esi, %rsi
leaq 0(,%rsi,4), %rax
movl (%rdi,%rsi,4), %r9d
movq -8(%rdx,%r8), %rcx
movq 8(%rdx,%r8), %r8
movl -4(%rdi,%rax), %edx
addl -4(%rcx,%rax), %edx
addl -4(%r8,%rax), %edx
addl (%r8,%rsi,4), %edx
addl 4(%r8,%rax), %edx
addl 4(%rdi,%rax), %edx
addl 4(%rcx,%rax), %edx
addl (%rcx,%rsi,4), %edx
leal -2(%rdx), %eax
cmpl $1, %eax
ja .L19
movl $1, %eax
cmpl $1, %r9d
je .L15
.L19:
testl %r9d, %r9d
sete %cl
cmpl $3, %edx
sete %al
movzbl %al, %eax
andl %ecx, %eax
.L15:
ret
.cfi_endproc
.LFE2072:
.size _Z8setPixelii, .-_Z8setPixelii
.globl _Z12nextGenPixeliii
.type _Z12nextGenPixeliii, @function
_Z12nextGenPixeliii:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %r13d
movl %esi, %ecx
movl %edx, 4(%rsp)
testl %edi, %edi
movl $1, %eax
cmove %eax, %r13d
cmpl %esi, height(%rip)
sete %al
movzbl %al, %eax
addl %eax, %ecx
movl %ecx, (%rsp)
cmpl %ecx, %r13d
jge .L20
movslq %r13d, %r14
salq $3, %r14
leal 1(%rdx), %r15d
jmp .L24
.L25:
movq tmp(%rip), %rax
movq %rbp, %r12
addq (%rax,%r14), %r12
movl %ebx, %esi
movl %r13d, %edi
call _Z8setPixelii
movl %eax, (%r12)
addl $1, %ebx
addq $4, %rbp
cmpl %r15d, %ebx
jne .L25
.L27:
addl $1, %r13d
addq $8, %r14
cmpl %r13d, (%rsp)
je .L20
.L24:
movl $4, %ebp
movl $1, %ebx
cmpl $0, 4(%rsp)
jg .L25
jmp .L27
.L20:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z12nextGenPixeliii, .-_Z12nextGenPixeliii
.globl _Z6ThreadPv
.type _Z6ThreadPv, @function
_Z6ThreadPv:
.LFB2069:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq tbarrier(%rip), %rbp
.L33:
movl 4(%rbx), %esi
movl (%rbx), %edi
movl width(%rip), %edx
call _Z12nextGenPixeliii
movq %rbp, %rdi
call pthread_barrier_wait@PLT
movl 4(%rbx), %esi
movl (%rbx), %edi
movl width(%rip), %edx
call _Z16copyAndResetDataiii
movq %rbp, %rdi
call pthread_barrier_wait@PLT
jmp .L33
.cfi_endproc
.LFE2069:
.size _Z6ThreadPv, .-_Z6ThreadPv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d x %d matrix\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "========================================\n"
.section .rodata.str1.1
.LC2:
.string "o"
.LC3:
.string "-"
.LC4:
.string "\n"
.text
.globl _Z4dumpv
.type _Z4dumpv, @function
_Z4dumpv:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl height(%rip), %ecx
movl width(%rip), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, %ebp
movl $1, %r13d
leaq .LC3(%rip), %r12
leaq .LC2(%rip), %r14
leaq .LC4(%rip), %r15
cmpl $0, height(%rip)
jg .L36
.L37:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L39:
addq $1, %rbx
leal 1(%rbx), %eax
cmpl %eax, width(%rip)
jl .L41
.L40:
movq arr(%rip), %rax
movq (%rax,%rbp), %rax
cmpl $1, 4(%rax,%rbx,4)
jne .L38
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L41:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq $8, %rbp
cmpl %r13d, height(%rip)
jl .L37
.L36:
movl $0, %ebx
cmpl $0, width(%rip)
jg .L40
jmp .L41
.cfi_endproc
.LFE2073:
.size _Z4dumpv, .-_Z4dumpv
.globl _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii
.type _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii, @function
_Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9my_kernelPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii, .-_Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii
.globl _Z9my_kernelPiS_iii
.type _Z9my_kernelPiS_iii, @function
_Z9my_kernelPiS_iii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z9my_kernelPiS_iii, .-_Z9my_kernelPiS_iii
.section .rodata.str1.1
.LC5:
.string "Parameter Error!\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "./glife <input file> <display> <nprocs> <# of generation> <width> <height>\n"
.section .rodata.str1.1
.LC7:
.string "r"
.LC8:
.string "error"
.LC9:
.string " "
.LC11:
.string "Execution time : %2.3f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2068:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $488, %rsp
.cfi_def_cfa_offset 544
movq %fs:40, %rax
movq %rax, 472(%rsp)
xorl %eax, %eax
cmpl $7, %edi
jne .L104
movq %rsi, %r12
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, display(%rip)
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, nprocs(%rip)
movq 32(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, gen(%rip)
movq 40(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, width(%rip)
movq 48(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, height(%rip)
leal 2(%rax), %r15d
movslq %r15d, %rax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, arr(%rip)
cmpl $-1, %ebx
jl .L58
leal 1(%rbx), %eax
leaq 8(,%rax,8), %r13
movl $0, %ebp
.L59:
movl width(%rip), %eax
leal 2(%rax), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbp, %r14
addq arr(%rip), %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%r14)
addq $8, %rbp
cmpq %r13, %rbp
jne .L59
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, tmp(%rip)
movl $0, %ebp
.L60:
movq %rbp, %r14
addq tmp(%rip), %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%r14)
addq $8, %rbp
cmpq %r13, %rbp
jne .L60
movl width(%rip), %eax
addl $2, %eax
imull %r15d, %eax
sall $2, %eax
movslq %eax, %r15
movq %r15, 8(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0, %r8d
jmp .L84
.L104:
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movq arr(%rip), %rax
movq (%rax,%rsi), %rax
movl $0, (%rax,%rdx,4)
movq tmp(%rip), %rax
movq (%rax,%rsi), %rax
movl $0, (%rax,%rdx,4)
movl width(%rip), %ecx
leal 2(%rcx), %eax
imull %edi, %eax
addl %edx, %eax
cltq
movl $0, (%rbx,%rax,4)
movl $0, 0(%rbp,%rax,4)
addq $1, %rdx
leal -1(%rdx), %eax
cmpl %eax, %ecx
jge .L62
.L65:
addq $1, %r8
leal -1(%r8), %eax
cmpl %eax, height(%rip)
jl .L63
.L84:
movl %r8d, %edi
leaq 0(,%r8,8), %rsi
movl $0, %edx
cmpl $-1, width(%rip)
jge .L62
jmp .L65
.L101:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $2, %edi
call exit@PLT
.L67:
leaq 448(%rsp), %rdi
movq %r14, %rsi
call strtok@PLT
movq %rax, %r12
movq %r14, %rsi
movl $0, %edi
call strtok@PLT
movq %rax, %r13
movl $10, %edx
movl $0, %esi
movq %r12, %rdi
call __isoc23_strtol@PLT
movq %rax, %r12
movl $10, %edx
movl $0, %esi
movq %r13, %rdi
call __isoc23_strtol@PLT
movq %rax, %rdx
movslq %eax, %rsi
movslq %r12d, %rcx
movq arr(%rip), %rax
movq (%rax,%rsi,8), %rax
movl $1, (%rax,%rcx,4)
movl width(%rip), %eax
addl $2, %eax
imull %edx, %eax
addl %r12d, %eax
cltq
movl $1, (%rbx,%rax,4)
.L66:
leaq 448(%rsp), %rdi
movq %r15, %rcx
movl $20, %edx
movl $20, %esi
call __fgets_chk@PLT
testq %rax, %rax
jne .L67
movl nprocs(%rip), %r12d
testl %r12d, %r12d
je .L105
movl height(%rip), %r10d
movl %r10d, %eax
cltd
idivl %r12d
testl %r12d, %r12d
jle .L77
leaq 256(%rsp), %rcx
movl $0, %edx
movl $0, %edi
movl $0, %esi
leal -1(%r12), %r9d
jmp .L79
.L105:
leaq begin(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
leaq 24(%rsp), %rdi
movq 8(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, gen(%rip)
jg .L71
.L69:
movl $2, %ecx
movq 8(%rsp), %r15
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r15, %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq end(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $0, %r8d
cmpl $-1, height(%rip)
jge .L72
jmp .L73
.L70:
call cudaDeviceSynchronize@PLT
addl $1, %r12d
cmpl %r12d, gen(%rip)
jle .L69
.L71:
movl width(%rip), %eax
addl $2, %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl height(%rip), %eax
addl $2, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L70
movl width(%rip), %eax
leal 2(%rax), %ecx
movl height(%rip), %eax
leal 2(%rax), %edx
movl gen(%rip), %r8d
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii
jmp .L70
.L74:
addl $2, %eax
imull %edi, %eax
addl %edx, %eax
cltq
movl (%rbx,%rax,4), %ecx
movq arr(%rip), %rax
movq (%rax,%rsi), %rax
movl %ecx, (%rax,%rdx,4)
movl width(%rip), %eax
addq $1, %rdx
leal -1(%rdx), %ecx
cmpl %ecx, %eax
jge .L74
.L76:
addq $1, %r8
leal -1(%r8), %eax
cmpl %eax, height(%rip)
jl .L73
.L72:
movl %r8d, %edi
movl width(%rip), %eax
leaq 0(,%r8,8), %rsi
movl $0, %edx
cmpl $-1, %eax
jge .L74
jmp .L76
.L87:
movl %r10d, %edi
movl %esi, %r8d
.L78:
movl %esi, (%rcx)
movl %edi, 4(%rcx)
addl $1, %edx
addq $8, %rcx
cmpl %edx, %r12d
je .L77
movl %r8d, %esi
.L79:
cmpl %edx, %r9d
je .L87
addl %eax, %edi
leal (%rax,%rsi), %r8d
jmp .L78
.L77:
movl %r12d, %edx
movl $0, %esi
leaq tbarrier(%rip), %rdi
call pthread_barrier_init@PLT
leaq begin(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $0, nprocs(%rip)
jle .L80
leaq 64(%rsp), %r13
movl $0, %r12d
leaq _Z6ThreadPv(%rip), %r14
.L81:
leaq 256(%rsp,%r12,8), %rcx
movq %r14, %rdx
movl $0, %esi
movq %r13, %rdi
call pthread_create@PLT
movl nprocs(%rip), %eax
addq $1, %r12
addq $8, %r13
cmpl %r12d, %eax
jg .L81
testl %eax, %eax
jle .L80
movl $0, %r12d
.L82:
movq 64(%rsp,%r12,8), %rdi
movl $0, %esi
call pthread_join@PLT
addq $1, %r12
cmpl %r12d, nprocs(%rip)
jg .L82
.L80:
leaq end(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
leaq tbarrier(%rip), %rdi
call pthread_barrier_destroy@PLT
.L73:
movq 8+end(%rip), %rax
subq 8+begin(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
movq end(%rip), %rax
subq begin(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $1, display(%rip)
je .L106
.L83:
movq arr(%rip), %rdi
call free@PLT
movq tmp(%rip), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 472(%rsp), %rax
subq %fs:40, %rax
jne .L107
movl $0, %eax
addq $488, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore_state
call _Z4dumpv
jmp .L83
.L58:
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, tmp(%rip)
movl width(%rip), %eax
addl $2, %eax
imull %r15d, %eax
sall $2, %eax
movslq %eax, %r15
movq %r15, 8(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
.L63:
movq 8(%r12), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %r15
testq %rax, %rax
je .L101
leaq .LC9(%rip), %r14
jmp .L66
.L107:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9my_kernelPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9my_kernelPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl end
.bss
.align 16
.type end, @object
.size end, 16
end:
.zero 16
.globl begin
.align 16
.type begin, @object
.size begin, 16
begin:
.zero 16
.globl tbarrier
.align 32
.type tbarrier, @object
.size tbarrier, 32
tbarrier:
.zero 32
.globl tmp
.align 8
.type tmp, @object
.size tmp, 8
tmp:
.zero 8
.globl arr
.align 8
.type arr, @object
.size arr, 8
arr:
.zero 8
.globl height
.align 4
.type height, @object
.size height, 4
height:
.zero 4
.globl width
.align 4
.type width, @object
.size width, 4
width:
.zero 4
.globl gen
.align 4
.type gen, @object
.size gen, 4
gen:
.zero 4
.globl display
.align 4
.type display, @object
.size display, 4
display:
.zero 4
.globl nprocs
.align 4
.type nprocs, @object
.size nprocs, 4
nprocs:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <pthread.h>
#define MAX_THREAD 24
/*
0123456789
0 oooooooooo
1 o@@@@@@@@o Problem solving example
2 o@@@@@@@@o 8 * 6 matrix
3 o@@@@@@@@o + 1px padding around matrix
4 o@@@@@@@@o
5 o@@@@@@@@o
6 o@@@@@@@@o
7 oooooooooo
*/
int nprocs, display, gen, width, height;
int** arr;
int** tmp;
pthread_barrier_t tbarrier;
struct timespec begin, end;
//CUDA and Thread
void dump();
//single & multi thread
int setPixel(int x, int y);
void* Thread(void *args);
void nextGenPixel(int start, int end, int width);
void copyAndResetData(int start, int end, int width);
typedef struct{
int start;
int end;
} bound;
__device__ int cudaNeighbor(int *mem, int index, int width){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = mem[index];
int neighbor = mem[index-width-1]+mem[index-width]+mem[index-width+1]+
mem[index-1]+mem[index+1]+mem[index+width-1]+mem[index+width]+mem[index+width+1];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
__global__ void my_kernel(int *cuda_mem, int *cuda_tmp, int height, int width, int gen){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(blockIdx.x == 0 || blockIdx.x == height-1 || threadIdx.x == 0 || threadIdx.x == width-1){
//Do nothing
}else{
cuda_tmp[index] = cudaNeighbor(cuda_mem, index, width);
}
cuda_mem[index] = cuda_tmp[index];
cuda_tmp[index] = 0;
}
int main(int argc, char *argv[]){
pthread_t thread[MAX_THREAD];
FILE *fp;
char buffer[20];
int x, y, size;
//This is for convert 2d array to 1d
int *mat_1d, *mat_1d_tmp;
int *cuda_mem, *cuda_tmp;
char *x_map, *y_map;
if(argc!=7){
printf("Parameter Error!\n");
printf("./glife <input file> <display> <nprocs> <# of generation> <width> <height>\n");
exit(1);
}
display = atoi(argv[2]);
nprocs = atoi(argv[3]);
gen = atoi(argv[4]);
width = atoi(argv[5]);
height = atoi(argv[6]);
//Make matrix
arr = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
arr[i] = (int*)malloc(sizeof(int) * (width+2));
}
tmp = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
tmp[i] = (int*)malloc(sizeof(int) * (width+2));
}
//length = (height+2) * (width+2);
size = (height+2) * (width+2) * sizeof(int);
mat_1d = (int*)malloc(size);
mat_1d_tmp = (int*)malloc(size);
//Initialize
for(int a=0; a<height+2; a++){
for(int b=0; b<width+2; b++){
arr[a][b] = 0;
tmp[a][b] = 0;
mat_1d[a*(width+2)+b] = 0;
mat_1d_tmp[a*(width+2)+b] = 0;
}
}
if((fp=fopen(argv[1],"r")) == NULL){
fprintf(stderr, "error");
exit(2);
}
//Mapping
while(fgets(buffer, 20, fp) != NULL){
y_map = strtok(buffer, " ");
x_map = strtok(NULL, " ");
y = atoi(y_map);
x = atoi(x_map);
arr[x][y] = 1;
mat_1d[x*(width+2) +y] = 1;
}
if(nprocs == 0){
//CUDA
clock_gettime(CLOCK_MONOTONIC, &begin);
cudaMalloc(&cuda_mem, size);
cudaMalloc(&cuda_tmp, size);
cudaMemcpy(cuda_mem, mat_1d, size, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_tmp, mat_1d_tmp, size, cudaMemcpyHostToDevice);
for(int i=0; i<gen; i++){
//Kernel code
my_kernel<<< height+2 , width+2 >>>(cuda_mem, cuda_tmp, height+2, width+2, gen);
cudaDeviceSynchronize();
}
cudaMemcpy(mat_1d, cuda_mem, size, cudaMemcpyDeviceToHost);
cudaMemcpy(mat_1d_tmp, cuda_tmp, size, cudaMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &end);
for(int i=0;i<height+2;i++){
for(int j=0;j<width+2;j++){
arr[i][j] = mat_1d[i*(width+2) +j ];
}
}
}else{
//SINGLE AND MULTI THREAD
//Divide height into nprocs pieces
bound section[MAX_THREAD];
int x = 0;
int y = 0;
int div = height/nprocs;
for(int k=0; k<nprocs; k++){
if(k == (nprocs-1)){
y = height;
section[k].start = x;
section[k].end = y;
}else{
y+=div;
section[k].start = x;
section[k].end = y;
x+=div;
}
}
pthread_barrier_init(&tbarrier, NULL, nprocs);
clock_gettime(CLOCK_MONOTONIC, &begin);
for(int i=0; i<nprocs; i++){
pthread_create(&thread[i], NULL, Thread, §ion[i]);
}
for(int j=0; j<nprocs; j++){
pthread_join(thread[j], NULL);
}
clock_gettime(CLOCK_MONOTONIC, &end);
pthread_barrier_destroy(&tbarrier);
}
printf("Execution time : %2.3f sec\n",(end.tv_sec - begin.tv_sec)+(end.tv_nsec-begin.tv_nsec)/1000000000.0);
if(display == 1){
dump();
}
free(arr);
free(tmp);
free(mat_1d);
free(mat_1d_tmp);
cudaFree(cuda_mem);
cudaFree(cuda_tmp);
return 0;
}
void *Thread(void *args){
//get args with struct
bound *section = (bound*)args;
for(int i=0; i<gen; i++){
nextGenPixel(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
copyAndResetData(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
}
}
void nextGenPixel(int start, int end, int wdth){
int head = start;
int tail = end;
if(head == 0){
head = 1;
}
if(tail == height){
tail++;
}
for(int i=head; i<tail; i++){
for(int j=1; j<=wdth; j++){
tmp[i][j]=setPixel(i,j);
}
}
}
void copyAndResetData(int start, int end, int wdth){
int tail = end;
if(tail == height){
tail +=2;
}
for(int a=start; a<tail; a++){
for(int b=0; b<wdth+2; b++){
arr[a][b] = tmp[a][b];
tmp[a][b] = 0;
}
}
}
int setPixel(int x, int y){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = arr[x][y];
int neighbor = arr[x-1][y-1]+arr[x][y-1]+arr[x+1][y-1]+arr[x+1][y]+arr[x+1][y+1]+arr[x][y+1]+arr[x-1][y+1]+arr[x-1][y];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
void dump(){
// print arr info
printf("%d x %d matrix\n", width, height);
printf("========================================\n");
for(int a=1; a<=height; a++){
for(int b=1; b<=width; b++){
if(arr[a][b]==1){
printf("o");
}else{
printf("-");
}
}
printf("\n");
}
printf("========================================\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <pthread.h>
#define MAX_THREAD 24
/*
0123456789
0 oooooooooo
1 o@@@@@@@@o Problem solving example
2 o@@@@@@@@o 8 * 6 matrix
3 o@@@@@@@@o + 1px padding around matrix
4 o@@@@@@@@o
5 o@@@@@@@@o
6 o@@@@@@@@o
7 oooooooooo
*/
int nprocs, display, gen, width, height;
int** arr;
int** tmp;
pthread_barrier_t tbarrier;
struct timespec begin, end;
//CUDA and Thread
void dump();
//single & multi thread
int setPixel(int x, int y);
void* Thread(void *args);
void nextGenPixel(int start, int end, int width);
void copyAndResetData(int start, int end, int width);
typedef struct{
int start;
int end;
} bound;
__device__ int cudaNeighbor(int *mem, int index, int width){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = mem[index];
int neighbor = mem[index-width-1]+mem[index-width]+mem[index-width+1]+
mem[index-1]+mem[index+1]+mem[index+width-1]+mem[index+width]+mem[index+width+1];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
__global__ void my_kernel(int *cuda_mem, int *cuda_tmp, int height, int width, int gen){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(blockIdx.x == 0 || blockIdx.x == height-1 || threadIdx.x == 0 || threadIdx.x == width-1){
//Do nothing
}else{
cuda_tmp[index] = cudaNeighbor(cuda_mem, index, width);
}
cuda_mem[index] = cuda_tmp[index];
cuda_tmp[index] = 0;
}
int main(int argc, char *argv[]){
pthread_t thread[MAX_THREAD];
FILE *fp;
char buffer[20];
int x, y, size;
//This is for convert 2d array to 1d
int *mat_1d, *mat_1d_tmp;
int *cuda_mem, *cuda_tmp;
char *x_map, *y_map;
if(argc!=7){
printf("Parameter Error!\n");
printf("./glife <input file> <display> <nprocs> <# of generation> <width> <height>\n");
exit(1);
}
display = atoi(argv[2]);
nprocs = atoi(argv[3]);
gen = atoi(argv[4]);
width = atoi(argv[5]);
height = atoi(argv[6]);
//Make matrix
arr = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
arr[i] = (int*)malloc(sizeof(int) * (width+2));
}
tmp = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
tmp[i] = (int*)malloc(sizeof(int) * (width+2));
}
//length = (height+2) * (width+2);
size = (height+2) * (width+2) * sizeof(int);
mat_1d = (int*)malloc(size);
mat_1d_tmp = (int*)malloc(size);
//Initialize
for(int a=0; a<height+2; a++){
for(int b=0; b<width+2; b++){
arr[a][b] = 0;
tmp[a][b] = 0;
mat_1d[a*(width+2)+b] = 0;
mat_1d_tmp[a*(width+2)+b] = 0;
}
}
if((fp=fopen(argv[1],"r")) == NULL){
fprintf(stderr, "error");
exit(2);
}
//Mapping
while(fgets(buffer, 20, fp) != NULL){
y_map = strtok(buffer, " ");
x_map = strtok(NULL, " ");
y = atoi(y_map);
x = atoi(x_map);
arr[x][y] = 1;
mat_1d[x*(width+2) +y] = 1;
}
if(nprocs == 0){
//CUDA
clock_gettime(CLOCK_MONOTONIC, &begin);
hipMalloc(&cuda_mem, size);
hipMalloc(&cuda_tmp, size);
hipMemcpy(cuda_mem, mat_1d, size, hipMemcpyHostToDevice);
hipMemcpy(cuda_tmp, mat_1d_tmp, size, hipMemcpyHostToDevice);
for(int i=0; i<gen; i++){
//Kernel code
my_kernel<<< height+2 , width+2 >>>(cuda_mem, cuda_tmp, height+2, width+2, gen);
hipDeviceSynchronize();
}
hipMemcpy(mat_1d, cuda_mem, size, hipMemcpyDeviceToHost);
hipMemcpy(mat_1d_tmp, cuda_tmp, size, hipMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &end);
for(int i=0;i<height+2;i++){
for(int j=0;j<width+2;j++){
arr[i][j] = mat_1d[i*(width+2) +j ];
}
}
}else{
//SINGLE AND MULTI THREAD
//Divide height into nprocs pieces
bound section[MAX_THREAD];
int x = 0;
int y = 0;
int div = height/nprocs;
for(int k=0; k<nprocs; k++){
if(k == (nprocs-1)){
y = height;
section[k].start = x;
section[k].end = y;
}else{
y+=div;
section[k].start = x;
section[k].end = y;
x+=div;
}
}
pthread_barrier_init(&tbarrier, NULL, nprocs);
clock_gettime(CLOCK_MONOTONIC, &begin);
for(int i=0; i<nprocs; i++){
pthread_create(&thread[i], NULL, Thread, §ion[i]);
}
for(int j=0; j<nprocs; j++){
pthread_join(thread[j], NULL);
}
clock_gettime(CLOCK_MONOTONIC, &end);
pthread_barrier_destroy(&tbarrier);
}
printf("Execution time : %2.3f sec\n",(end.tv_sec - begin.tv_sec)+(end.tv_nsec-begin.tv_nsec)/1000000000.0);
if(display == 1){
dump();
}
free(arr);
free(tmp);
free(mat_1d);
free(mat_1d_tmp);
hipFree(cuda_mem);
hipFree(cuda_tmp);
return 0;
}
void *Thread(void *args){
//get args with struct
bound *section = (bound*)args;
for(int i=0; i<gen; i++){
nextGenPixel(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
copyAndResetData(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
}
}
void nextGenPixel(int start, int end, int wdth){
int head = start;
int tail = end;
if(head == 0){
head = 1;
}
if(tail == height){
tail++;
}
for(int i=head; i<tail; i++){
for(int j=1; j<=wdth; j++){
tmp[i][j]=setPixel(i,j);
}
}
}
void copyAndResetData(int start, int end, int wdth){
int tail = end;
if(tail == height){
tail +=2;
}
for(int a=start; a<tail; a++){
for(int b=0; b<wdth+2; b++){
arr[a][b] = tmp[a][b];
tmp[a][b] = 0;
}
}
}
int setPixel(int x, int y){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = arr[x][y];
int neighbor = arr[x-1][y-1]+arr[x][y-1]+arr[x+1][y-1]+arr[x+1][y]+arr[x+1][y+1]+arr[x][y+1]+arr[x-1][y+1]+arr[x-1][y];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
void dump(){
// print arr info
printf("%d x %d matrix\n", width, height);
printf("========================================\n");
for(int a=1; a<=height; a++){
for(int b=1; b<=width; b++){
if(arr[a][b]==1){
printf("o");
}else{
printf("-");
}
}
printf("\n");
}
printf("========================================\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <pthread.h>
#define MAX_THREAD 24
/*
0123456789
0 oooooooooo
1 o@@@@@@@@o Problem solving example
2 o@@@@@@@@o 8 * 6 matrix
3 o@@@@@@@@o + 1px padding around matrix
4 o@@@@@@@@o
5 o@@@@@@@@o
6 o@@@@@@@@o
7 oooooooooo
*/
int nprocs, display, gen, width, height;
int** arr;
int** tmp;
pthread_barrier_t tbarrier;
struct timespec begin, end;
//CUDA and Thread
void dump();
//single & multi thread
int setPixel(int x, int y);
void* Thread(void *args);
void nextGenPixel(int start, int end, int width);
void copyAndResetData(int start, int end, int width);
typedef struct{
int start;
int end;
} bound;
__device__ int cudaNeighbor(int *mem, int index, int width){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = mem[index];
int neighbor = mem[index-width-1]+mem[index-width]+mem[index-width+1]+
mem[index-1]+mem[index+1]+mem[index+width-1]+mem[index+width]+mem[index+width+1];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
__global__ void my_kernel(int *cuda_mem, int *cuda_tmp, int height, int width, int gen){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(blockIdx.x == 0 || blockIdx.x == height-1 || threadIdx.x == 0 || threadIdx.x == width-1){
//Do nothing
}else{
cuda_tmp[index] = cudaNeighbor(cuda_mem, index, width);
}
cuda_mem[index] = cuda_tmp[index];
cuda_tmp[index] = 0;
}
int main(int argc, char *argv[]){
pthread_t thread[MAX_THREAD];
FILE *fp;
char buffer[20];
int x, y, size;
//This is for convert 2d array to 1d
int *mat_1d, *mat_1d_tmp;
int *cuda_mem, *cuda_tmp;
char *x_map, *y_map;
if(argc!=7){
printf("Parameter Error!\n");
printf("./glife <input file> <display> <nprocs> <# of generation> <width> <height>\n");
exit(1);
}
display = atoi(argv[2]);
nprocs = atoi(argv[3]);
gen = atoi(argv[4]);
width = atoi(argv[5]);
height = atoi(argv[6]);
//Make matrix
arr = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
arr[i] = (int*)malloc(sizeof(int) * (width+2));
}
tmp = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
tmp[i] = (int*)malloc(sizeof(int) * (width+2));
}
//length = (height+2) * (width+2);
size = (height+2) * (width+2) * sizeof(int);
mat_1d = (int*)malloc(size);
mat_1d_tmp = (int*)malloc(size);
//Initialize
for(int a=0; a<height+2; a++){
for(int b=0; b<width+2; b++){
arr[a][b] = 0;
tmp[a][b] = 0;
mat_1d[a*(width+2)+b] = 0;
mat_1d_tmp[a*(width+2)+b] = 0;
}
}
if((fp=fopen(argv[1],"r")) == NULL){
fprintf(stderr, "error");
exit(2);
}
//Mapping
while(fgets(buffer, 20, fp) != NULL){
y_map = strtok(buffer, " ");
x_map = strtok(NULL, " ");
y = atoi(y_map);
x = atoi(x_map);
arr[x][y] = 1;
mat_1d[x*(width+2) +y] = 1;
}
if(nprocs == 0){
//CUDA
clock_gettime(CLOCK_MONOTONIC, &begin);
hipMalloc(&cuda_mem, size);
hipMalloc(&cuda_tmp, size);
hipMemcpy(cuda_mem, mat_1d, size, hipMemcpyHostToDevice);
hipMemcpy(cuda_tmp, mat_1d_tmp, size, hipMemcpyHostToDevice);
for(int i=0; i<gen; i++){
//Kernel code
my_kernel<<< height+2 , width+2 >>>(cuda_mem, cuda_tmp, height+2, width+2, gen);
hipDeviceSynchronize();
}
hipMemcpy(mat_1d, cuda_mem, size, hipMemcpyDeviceToHost);
hipMemcpy(mat_1d_tmp, cuda_tmp, size, hipMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &end);
for(int i=0;i<height+2;i++){
for(int j=0;j<width+2;j++){
arr[i][j] = mat_1d[i*(width+2) +j ];
}
}
}else{
//SINGLE AND MULTI THREAD
//Divide height into nprocs pieces
bound section[MAX_THREAD];
int x = 0;
int y = 0;
int div = height/nprocs;
for(int k=0; k<nprocs; k++){
if(k == (nprocs-1)){
y = height;
section[k].start = x;
section[k].end = y;
}else{
y+=div;
section[k].start = x;
section[k].end = y;
x+=div;
}
}
pthread_barrier_init(&tbarrier, NULL, nprocs);
clock_gettime(CLOCK_MONOTONIC, &begin);
for(int i=0; i<nprocs; i++){
pthread_create(&thread[i], NULL, Thread, §ion[i]);
}
for(int j=0; j<nprocs; j++){
pthread_join(thread[j], NULL);
}
clock_gettime(CLOCK_MONOTONIC, &end);
pthread_barrier_destroy(&tbarrier);
}
printf("Execution time : %2.3f sec\n",(end.tv_sec - begin.tv_sec)+(end.tv_nsec-begin.tv_nsec)/1000000000.0);
if(display == 1){
dump();
}
free(arr);
free(tmp);
free(mat_1d);
free(mat_1d_tmp);
hipFree(cuda_mem);
hipFree(cuda_tmp);
return 0;
}
void *Thread(void *args){
//get args with struct
bound *section = (bound*)args;
for(int i=0; i<gen; i++){
nextGenPixel(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
copyAndResetData(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
}
}
void nextGenPixel(int start, int end, int wdth){
int head = start;
int tail = end;
if(head == 0){
head = 1;
}
if(tail == height){
tail++;
}
for(int i=head; i<tail; i++){
for(int j=1; j<=wdth; j++){
tmp[i][j]=setPixel(i,j);
}
}
}
void copyAndResetData(int start, int end, int wdth){
int tail = end;
if(tail == height){
tail +=2;
}
for(int a=start; a<tail; a++){
for(int b=0; b<wdth+2; b++){
arr[a][b] = tmp[a][b];
tmp[a][b] = 0;
}
}
}
int setPixel(int x, int y){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = arr[x][y];
int neighbor = arr[x-1][y-1]+arr[x][y-1]+arr[x+1][y-1]+arr[x+1][y]+arr[x+1][y+1]+arr[x][y+1]+arr[x-1][y+1]+arr[x-1][y];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
void dump(){
// print arr info
printf("%d x %d matrix\n", width, height);
printf("========================================\n");
for(int a=1; a<=height; a++){
for(int b=1; b<=width; b++){
if(arr[a][b]==1){
printf("o");
}else{
printf("-");
}
}
printf("\n");
}
printf("========================================\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9my_kernelPiS_iii
.globl _Z9my_kernelPiS_iii
.p2align 8
.type _Z9my_kernelPiS_iii,@function
_Z9my_kernelPiS_iii:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s8, 0xffff
s_cmp_lg_u32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_cselect_b32 s1, -1, 0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s2
s_cselect_b32 s2, -1, 0
s_add_i32 s0, s3, -1
s_and_b32 s1, s1, s2
v_cmp_ne_u32_e64 s0, s0, v0
v_ashrrev_i32_e32 v2, 31, v1
s_and_b32 s1, vcc_lo, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s8, s0
s_cbranch_execz .LBB0_2
v_subrev_nc_u32_e32 v3, s3, v1
v_add_nc_u32_e32 v5, s3, v1
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-4
global_load_b64 v[3:4], v[3:4], off
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_clause 0x3
global_load_b32 v11, v[9:10], off offset:-4
global_load_b64 v[9:10], v[9:10], off
global_load_b32 v12, v[5:6], off offset:-4
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(4)
v_add_nc_u32_e32 v0, v3, v0
s_waitcnt vmcnt(2)
v_cmp_eq_u32_e32 vcc_lo, 1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add3_u32 v0, v0, v4, v11
v_cmp_gt_u32_e64 s0, 2, v9
s_waitcnt vmcnt(1)
v_add3_u32 v0, v0, v10, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, v5, v6
v_cmp_eq_u32_e64 s1, 2, v0
v_cmp_eq_u32_e64 s2, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 s1, vcc_lo, s1
s_and_b32 s0, s0, s2
v_add_co_u32 v3, vcc_lo, s6, v7
s_or_b32 s0, s1, s0
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v8, vcc_lo
v_cndmask_b32_e64 v0, 0, 1, s0
global_store_b32 v[3:4], v0, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9my_kernelPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9my_kernelPiS_iii, .Lfunc_end0-_Z9my_kernelPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9my_kernelPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9my_kernelPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <pthread.h>
#define MAX_THREAD 24
/*
0123456789
0 oooooooooo
1 o@@@@@@@@o Problem solving example
2 o@@@@@@@@o 8 * 6 matrix
3 o@@@@@@@@o + 1px padding around matrix
4 o@@@@@@@@o
5 o@@@@@@@@o
6 o@@@@@@@@o
7 oooooooooo
*/
int nprocs, display, gen, width, height;
int** arr;
int** tmp;
pthread_barrier_t tbarrier;
struct timespec begin, end;
//CUDA and Thread
void dump();
//single & multi thread
int setPixel(int x, int y);
void* Thread(void *args);
void nextGenPixel(int start, int end, int width);
void copyAndResetData(int start, int end, int width);
typedef struct{
int start;
int end;
} bound;
__device__ int cudaNeighbor(int *mem, int index, int width){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = mem[index];
int neighbor = mem[index-width-1]+mem[index-width]+mem[index-width+1]+
mem[index-1]+mem[index+1]+mem[index+width-1]+mem[index+width]+mem[index+width+1];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
__global__ void my_kernel(int *cuda_mem, int *cuda_tmp, int height, int width, int gen){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(blockIdx.x == 0 || blockIdx.x == height-1 || threadIdx.x == 0 || threadIdx.x == width-1){
//Do nothing
}else{
cuda_tmp[index] = cudaNeighbor(cuda_mem, index, width);
}
cuda_mem[index] = cuda_tmp[index];
cuda_tmp[index] = 0;
}
int main(int argc, char *argv[]){
pthread_t thread[MAX_THREAD];
FILE *fp;
char buffer[20];
int x, y, size;
//This is for convert 2d array to 1d
int *mat_1d, *mat_1d_tmp;
int *cuda_mem, *cuda_tmp;
char *x_map, *y_map;
if(argc!=7){
printf("Parameter Error!\n");
printf("./glife <input file> <display> <nprocs> <# of generation> <width> <height>\n");
exit(1);
}
display = atoi(argv[2]);
nprocs = atoi(argv[3]);
gen = atoi(argv[4]);
width = atoi(argv[5]);
height = atoi(argv[6]);
//Make matrix
arr = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
arr[i] = (int*)malloc(sizeof(int) * (width+2));
}
tmp = (int**)malloc(sizeof(int*) * (height+2));
for(int i=0; i<height+2; i++){
tmp[i] = (int*)malloc(sizeof(int) * (width+2));
}
//length = (height+2) * (width+2);
size = (height+2) * (width+2) * sizeof(int);
mat_1d = (int*)malloc(size);
mat_1d_tmp = (int*)malloc(size);
//Initialize
for(int a=0; a<height+2; a++){
for(int b=0; b<width+2; b++){
arr[a][b] = 0;
tmp[a][b] = 0;
mat_1d[a*(width+2)+b] = 0;
mat_1d_tmp[a*(width+2)+b] = 0;
}
}
if((fp=fopen(argv[1],"r")) == NULL){
fprintf(stderr, "error");
exit(2);
}
//Mapping
while(fgets(buffer, 20, fp) != NULL){
y_map = strtok(buffer, " ");
x_map = strtok(NULL, " ");
y = atoi(y_map);
x = atoi(x_map);
arr[x][y] = 1;
mat_1d[x*(width+2) +y] = 1;
}
if(nprocs == 0){
//CUDA
clock_gettime(CLOCK_MONOTONIC, &begin);
hipMalloc(&cuda_mem, size);
hipMalloc(&cuda_tmp, size);
hipMemcpy(cuda_mem, mat_1d, size, hipMemcpyHostToDevice);
hipMemcpy(cuda_tmp, mat_1d_tmp, size, hipMemcpyHostToDevice);
for(int i=0; i<gen; i++){
//Kernel code
my_kernel<<< height+2 , width+2 >>>(cuda_mem, cuda_tmp, height+2, width+2, gen);
hipDeviceSynchronize();
}
hipMemcpy(mat_1d, cuda_mem, size, hipMemcpyDeviceToHost);
hipMemcpy(mat_1d_tmp, cuda_tmp, size, hipMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &end);
for(int i=0;i<height+2;i++){
for(int j=0;j<width+2;j++){
arr[i][j] = mat_1d[i*(width+2) +j ];
}
}
}else{
//SINGLE AND MULTI THREAD
//Divide height into nprocs pieces
bound section[MAX_THREAD];
int x = 0;
int y = 0;
int div = height/nprocs;
for(int k=0; k<nprocs; k++){
if(k == (nprocs-1)){
y = height;
section[k].start = x;
section[k].end = y;
}else{
y+=div;
section[k].start = x;
section[k].end = y;
x+=div;
}
}
pthread_barrier_init(&tbarrier, NULL, nprocs);
clock_gettime(CLOCK_MONOTONIC, &begin);
for(int i=0; i<nprocs; i++){
pthread_create(&thread[i], NULL, Thread, §ion[i]);
}
for(int j=0; j<nprocs; j++){
pthread_join(thread[j], NULL);
}
clock_gettime(CLOCK_MONOTONIC, &end);
pthread_barrier_destroy(&tbarrier);
}
printf("Execution time : %2.3f sec\n",(end.tv_sec - begin.tv_sec)+(end.tv_nsec-begin.tv_nsec)/1000000000.0);
if(display == 1){
dump();
}
free(arr);
free(tmp);
free(mat_1d);
free(mat_1d_tmp);
hipFree(cuda_mem);
hipFree(cuda_tmp);
return 0;
}
void *Thread(void *args){
//get args with struct
bound *section = (bound*)args;
for(int i=0; i<gen; i++){
nextGenPixel(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
copyAndResetData(section[0].start, section[0].end, width);
pthread_barrier_wait(&tbarrier);
}
}
void nextGenPixel(int start, int end, int wdth){
int head = start;
int tail = end;
if(head == 0){
head = 1;
}
if(tail == height){
tail++;
}
for(int i=head; i<tail; i++){
for(int j=1; j<=wdth; j++){
tmp[i][j]=setPixel(i,j);
}
}
}
void copyAndResetData(int start, int end, int wdth){
int tail = end;
if(tail == height){
tail +=2;
}
for(int a=start; a<tail; a++){
for(int b=0; b<wdth+2; b++){
arr[a][b] = tmp[a][b];
tmp[a][b] = 0;
}
}
}
int setPixel(int x, int y){
//live cell with 2 or 3 neighbors -> keep live
//dead cell with 3 neighbors -> revive
//other cases : die
int current = arr[x][y];
int neighbor = arr[x-1][y-1]+arr[x][y-1]+arr[x+1][y-1]+arr[x+1][y]+arr[x+1][y+1]+arr[x][y+1]+arr[x-1][y+1]+arr[x-1][y];
if((current == 1 && neighbor == 2) || (current == 1 && neighbor == 3) || (current == 0 && neighbor == 3)){
return 1;
}else{
return 0;
}
}
void dump(){
// print arr info
printf("%d x %d matrix\n", width, height);
printf("========================================\n");
for(int a=1; a<=height; a++){
for(int b=1; b<=width; b++){
if(arr[a][b]==1){
printf("o");
}else{
printf("-");
}
}
printf("\n");
}
printf("========================================\n");
} | .text
.file "gameoflife.hip"
.globl _Z24__device_stub__my_kernelPiS_iii # -- Begin function _Z24__device_stub__my_kernelPiS_iii
.p2align 4, 0x90
.type _Z24__device_stub__my_kernelPiS_iii,@function
_Z24__device_stub__my_kernelPiS_iii: # @_Z24__device_stub__my_kernelPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9my_kernelPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__my_kernelPiS_iii, .Lfunc_end0-_Z24__device_stub__my_kernelPiS_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $520, %rsp # imm = 0x208
.cfi_def_cfa_offset 576
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $7, %edi
jne .LBB1_45
# %bb.1:
movq %rsi, %rbx
movq 16(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, display(%rip)
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nprocs(%rip)
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, gen(%rip)
movq 40(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, width(%rip)
movq %rbx, 40(%rsp) # 8-byte Spill
movq 48(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %ebx, height(%rip)
leal 2(%rax), %ebp
movslq %ebx, %r15
leaq 16(,%r15,8), %r14
movq %r14, %rdi
callq malloc
movq %rax, arr(%rip)
cmpl $-1, %r15d
jl .LBB1_4
# %bb.2: # %.lr.ph
movslq width(%rip), %rax
leaq 8(,%rax,4), %r15
cmpl $2, %ebp
movl $1, %r13d
cmovgel %ebp, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq malloc
movq arr(%rip), %rcx
movq %rax, (%rcx,%r12,8)
incq %r12
cmpq %r12, %r13
jne .LBB1_3
.LBB1_4: # %._crit_edge
movq %r14, %rdi
callq malloc
movq %rax, tmp(%rip)
cmpl $-1, %ebx
jl .LBB1_7
# %bb.5: # %.lr.ph114
movslq width(%rip), %rax
leaq 8(,%rax,4), %rbx
cmpl $2, %ebp
movl $1, %r14d
cmovgel %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq malloc
movq tmp(%rip), %rcx
movq %rax, (%rcx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_6
.LBB1_7: # %._crit_edge115
movl width(%rip), %eax
addl $2, %eax
imull %eax, %ebp
shll $2, %ebp
movslq %ebp, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, 32(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r14
cmpl $-1, height(%rip)
jl .LBB1_13
# %bb.8: # %.preheader110.lr.ph
movq arr(%rip), %rax
movq tmp(%rip), %rcx
xorl %edx, %edx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # %._crit_edge118
# in Loop: Header=BB1_9 Depth=1
leaq 1(%rdx), %rsi
movslq height(%rip), %rdi
cmpq %rdi, %rdx
movq %rsi, %rdx
jg .LBB1_13
.LBB1_9: # %.preheader110
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
cmpl $-1, width(%rip)
jl .LBB1_12
# %bb.10: # %.lr.ph117
# in Loop: Header=BB1_9 Depth=1
movq (%rax,%rdx,8), %rsi
movq (%rcx,%rdx,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%rsi,%r8,4)
movl $0, (%rdi,%r8,4)
movl width(%rip), %r9d
addl $2, %r9d
imull %edx, %r9d
addl %r8d, %r9d
movslq %r9d, %r9
movl $0, (%rbx,%r9,4)
movl $0, (%r14,%r9,4)
leaq 1(%r8), %r9
movslq width(%rip), %r10
cmpq %r10, %r8
movq %r9, %r8
jle .LBB1_11
jmp .LBB1_12
.LBB1_13: # %._crit_edge120
movq 40(%rsp), %rax # 8-byte Reload
movq 8(%rax), %rdi
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB1_46
# %bb.14: # %.preheader109
movq %rax, %r12
leaq 96(%rsp), %rdi
movl $20, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB1_17
# %bb.15:
leaq 96(%rsp), %r13
.p2align 4, 0x90
.LBB1_16: # %.lr.ph122
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %esi
movq %r13, %rdi
callq strtok
movq %rax, %rbp
movl $.L.str.4, %esi
xorl %edi, %edi
callq strtok
movq %rax, %r15
movq %rbp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq arr(%rip), %rcx
cltq
movq (%rcx,%rax,8), %rcx
movslq %ebp, %rdx
movl $1, (%rcx,%rdx,4)
movl width(%rip), %ecx
addl $2, %ecx
imull %ecx, %eax
addl %eax, %edx
movslq %edx, %rax
movl $1, (%rbx,%rax,4)
movq %r13, %rdi
movl $20, %esi
movq %r12, %rdx
callq fgets
testq %rax, %rax
jne .LBB1_16
.LBB1_17: # %._crit_edge123
movl nprocs(%rip), %ecx
testq %rcx, %rcx
je .LBB1_18
# %bb.29:
movl height(%rip), %esi
movl %esi, %eax
cltd
idivl %ecx
testl %ecx, %ecx
jle .LBB1_33
# %bb.30: # %.lr.ph128
leal -1(%rcx), %edx
xorl %edi, %edi
xorl %r9d, %r9d
xorl %r8d, %r8d
jmp .LBB1_31
.p2align 4, 0x90
.LBB1_43: # in Loop: Header=BB1_31 Depth=1
addl %eax, %r9d
movl %r8d, 128(%rsp,%rdi,8)
movl %r9d, 132(%rsp,%rdi,8)
addl %eax, %r8d
.LBB1_44: # in Loop: Header=BB1_31 Depth=1
incq %rdi
cmpq %rdi, %rcx
je .LBB1_33
.LBB1_31: # =>This Inner Loop Header: Depth=1
cmpq %rdi, %rdx
jne .LBB1_43
# %bb.32: # in Loop: Header=BB1_31 Depth=1
movl %r8d, 128(%rsp,%rdi,8)
movl %esi, 132(%rsp,%rdi,8)
movl %esi, %r9d
jmp .LBB1_44
.LBB1_33: # %._crit_edge129
movl $tbarrier, %edi
xorl %esi, %esi
movl %ecx, %edx
callq pthread_barrier_init
movl $begin, %esi
movl $1, %edi
callq clock_gettime
cmpl $0, nprocs(%rip)
jle .LBB1_36
# %bb.34: # %.lr.ph132.preheader
leaq 128(%rsp), %r15
leaq 320(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_35: # %.lr.ph132
# =>This Inner Loop Header: Depth=1
movl $_Z6ThreadPv, %edx
movq %r12, %rdi
xorl %esi, %esi
movq %r15, %rcx
callq pthread_create
incq %r13
movslq nprocs(%rip), %rax
addq $8, %r15
addq $8, %r12
cmpq %rax, %r13
jl .LBB1_35
.LBB1_36: # %.preheader108
cmpl $0, nprocs(%rip)
jle .LBB1_39
# %bb.37: # %.lr.ph134.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_38: # %.lr.ph134
# =>This Inner Loop Header: Depth=1
movq 320(%rsp,%r15,8), %rdi
xorl %esi, %esi
callq pthread_join
incq %r15
movslq nprocs(%rip), %rax
cmpq %rax, %r15
jl .LBB1_38
.LBB1_39: # %._crit_edge135
movl $end, %esi
movl $1, %edi
callq clock_gettime
movl $tbarrier, %edi
callq pthread_barrier_destroy
jmp .LBB1_40
.LBB1_18:
movl $begin, %esi
movl $1, %edi
callq clock_gettime
leaq 8(%rsp), %rdi
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
cmpl $0, gen(%rip)
jle .LBB1_23
# %bb.19: # %.lr.ph138
xorl %r15d, %r15d
movabsq $4294967296, %rbp # imm = 0x100000000
leaq 48(%rsp), %r12
leaq 320(%rsp), %r13
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_22: # in Loop: Header=BB1_20 Depth=1
callq hipDeviceSynchronize
incl %r15d
cmpl gen(%rip), %r15d
jge .LBB1_23
.LBB1_20: # =>This Inner Loop Header: Depth=1
movl height(%rip), %edi
addl $2, %edi
movl width(%rip), %edx
addl $2, %edx
orq %rbp, %rdi
orq %rbp, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_22
# %bb.21: # in Loop: Header=BB1_20 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl height(%rip), %edx
addl $2, %edx
movl width(%rip), %esi
addl $2, %esi
movl gen(%rip), %edi
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
movl %esi, 24(%rsp)
movl %edi, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 320(%rsp)
leaq 80(%rsp), %rax
movq %rax, 328(%rsp)
leaq 28(%rsp), %rax
movq %rax, 336(%rsp)
leaq 24(%rsp), %rax
movq %rax, 344(%rsp)
leaq 20(%rsp), %rax
movq %rax, 352(%rsp)
leaq 128(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z9my_kernelPiS_iii, %edi
movq %r13, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_22
.LBB1_23: # %._crit_edge139
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $end, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, height(%rip)
jl .LBB1_40
# %bb.24: # %.preheader.lr.ph
movq arr(%rip), %rax
xorl %ecx, %ecx
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_28: # %._crit_edge142
# in Loop: Header=BB1_25 Depth=1
leaq 1(%rcx), %rdx
movslq height(%rip), %rsi
cmpq %rsi, %rcx
movq %rdx, %rcx
jg .LBB1_40
.LBB1_25: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_27 Depth 2
movl width(%rip), %edx
cmpl $-1, %edx
jl .LBB1_28
# %bb.26: # %.lr.ph141
# in Loop: Header=BB1_25 Depth=1
addl $2, %edx
movq (%rax,%rcx,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_27: # Parent Loop BB1_25 Depth=1
# => This Inner Loop Header: Depth=2
imull %ecx, %edx
addl %edi, %edx
movslq %edx, %rdx
movl (%rbx,%rdx,4), %edx
movl %edx, (%rsi,%rdi,4)
incq %rdi
movslq width(%rip), %rdx
addq $2, %rdx
cmpq %rdx, %rdi
jl .LBB1_27
jmp .LBB1_28
.LBB1_40: # %.loopexit
movq end(%rip), %rax
subq begin(%rip), %rax
cvtsi2sd %rax, %xmm1
movq end+8(%rip), %rax
subq begin+8(%rip), %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
cmpl $1, display(%rip)
jne .LBB1_42
# %bb.41:
callq _Z4dumpv
.LBB1_42:
movq arr(%rip), %rdi
callq free
movq tmp(%rip), %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $520, %rsp # imm = 0x208
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_45:
.cfi_def_cfa_offset 576
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_46:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $5, %esi
movl $1, %edx
callq fwrite@PLT
movl $2, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z6ThreadPv # -- Begin function _Z6ThreadPv
.p2align 4, 0x90
.type _Z6ThreadPv,@function
_Z6ThreadPv: # @_Z6ThreadPv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
movq %rdi, (%rsp) # 8-byte Spill
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_13: # %_Z16copyAndResetDataiii.exit
# in Loop: Header=BB2_1 Depth=1
movl $tbarrier, %edi
callq pthread_barrier_wait
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_9 Depth 2
# Child Loop BB2_11 Depth 3
movl (%r14), %edi
cmpl $1, %edi
adcl $0, %edi
movl 4(%r14), %eax
xorl %r8d, %r8d
cmpl %eax, height(%rip)
sete %r8b
addl %eax, %r8d
cmpl %r8d, %edi
jge .LBB2_7
# %bb.2: # %.preheader.lr.ph.i
# in Loop: Header=BB2_1 Depth=1
movl width(%rip), %eax
movq arr(%rip), %rcx
movq tmp(%rip), %rdx
leal 1(%rax), %esi
movslq %edi, %rdi
movslq %r8d, %r8
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_6: # %._crit_edge.i
# in Loop: Header=BB2_3 Depth=2
incq %rdi
cmpq %r8, %rdi
je .LBB2_7
.LBB2_3: # %.preheader.i
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_5 Depth 3
testl %eax, %eax
jle .LBB2_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB2_3 Depth=2
movq -8(%rcx,%rdi,8), %r9
movq (%rcx,%rdi,8), %r10
movq 8(%rcx,%rdi,8), %r11
movq (%rdx,%rdi,8), %r14
movl $1, %r15d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movl -4(%r10,%r15,4), %ebx
addl -4(%r9,%r15,4), %ebx
addl -4(%r11,%r15,4), %ebx
addl (%r11,%r15,4), %ebx
addl 4(%r11,%r15,4), %ebx
addl 4(%r10,%r15,4), %ebx
addl 4(%r9,%r15,4), %ebx
movl (%r10,%r15,4), %r12d
addl (%r9,%r15,4), %ebx
movl %r12d, %r13d
xorl $1, %r13d
movl %ebx, %ebp
xorl $2, %ebp
orl %r13d, %ebp
sete %bpl
cmpl $3, %ebx
sete %bl
cmpl $2, %r12d
setb %r12b
andb %bl, %r12b
orb %bpl, %r12b
movzbl %r12b, %ebx
movl %ebx, (%r14,%r15,4)
leaq 1(%r15), %rbx
movq %rbx, %r15
cmpq %rbx, %rsi
jne .LBB2_5
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_7: # %_Z12nextGenPixeliii.exit
# in Loop: Header=BB2_1 Depth=1
movl $tbarrier, %edi
callq pthread_barrier_wait
movq (%rsp), %r14 # 8-byte Reload
movslq (%r14), %rax
movl 4(%r14), %ecx
cmpl %ecx, height(%rip)
leal 2(%rcx), %r8d
cmovnel %ecx, %r8d
cmpl %eax, %r8d
jle .LBB2_13
# %bb.8: # %.preheader.lr.ph.i7
# in Loop: Header=BB2_1 Depth=1
movl width(%rip), %ecx
movq tmp(%rip), %rdx
movq arr(%rip), %rsi
leal 2(%rcx), %edi
movslq %r8d, %r8
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_12: # %._crit_edge.i9
# in Loop: Header=BB2_9 Depth=2
incq %rax
cmpq %r8, %rax
je .LBB2_13
.LBB2_9: # %.preheader.i8
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_11 Depth 3
cmpl $-1, %ecx
jl .LBB2_12
# %bb.10: # %.lr.ph.i10
# in Loop: Header=BB2_9 Depth=2
movq (%rdx,%rax,8), %r9
movq (%rsi,%rax,8), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_11: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_9 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9,%r11,4), %ebx
movl %ebx, (%r10,%r11,4)
movl $0, (%r9,%r11,4)
incq %r11
cmpq %r11, %rdi
jne .LBB2_11
jmp .LBB2_12
.Lfunc_end2:
.size _Z6ThreadPv, .Lfunc_end2-_Z6ThreadPv
.cfi_endproc
# -- End function
.globl _Z4dumpv # -- Begin function _Z4dumpv
.p2align 4, 0x90
.type _Z4dumpv,@function
_Z4dumpv: # @_Z4dumpv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl width(%rip), %esi
movl height(%rip), %edx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, height(%rip)
jle .LBB3_8
# %bb.1: # %.preheader.preheader
movl $1, %ebx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%rbx), %rax
movslq height(%rip), %rcx
cmpq %rcx, %rbx
movq %rax, %rbx
jge .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, width(%rip)
jle .LBB3_7
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
xorl %r14d, %r14d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # %.lr.ph
# in Loop: Header=BB3_4 Depth=2
callq putchar@PLT
movslq width(%rip), %rax
incq %r14
cmpq %rax, %r14
jge .LBB3_7
.LBB3_4: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movq arr(%rip), %rax
movq (%rax,%rbx,8), %rax
cmpl $1, 4(%rax,%r14,4)
movl $111, %edi
je .LBB3_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB3_4 Depth=2
movl $45, %edi
jmp .LBB3_6
.LBB3_8: # %._crit_edge15
movl $.Lstr.3, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z4dumpv, .Lfunc_end3-_Z4dumpv
.cfi_endproc
# -- End function
.globl _Z12nextGenPixeliii # -- Begin function _Z12nextGenPixeliii
.p2align 4, 0x90
.type _Z12nextGenPixeliii,@function
_Z12nextGenPixeliii: # @_Z12nextGenPixeliii
.cfi_startproc
# %bb.0:
cmpl $1, %edi
adcl $0, %edi
xorl %r8d, %r8d
cmpl %esi, height(%rip)
# kill: def $edx killed $edx def $rdx
sete %r8b
addl %esi, %r8d
cmpl %r8d, %edi
jge .LBB4_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq arr(%rip), %rax
movq tmp(%rip), %rcx
leal 1(%rdx), %esi
movslq %edi, %rdi
movslq %r8d, %r8
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %rdi
cmpq %r8, %rdi
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %edx, %edx
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movq -8(%rax,%rdi,8), %r9
movq (%rax,%rdi,8), %r10
movq 8(%rax,%rdi,8), %r11
movq (%rcx,%rdi,8), %rbx
movl $1, %r14d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl -4(%r10,%r14,4), %ebp
addl -4(%r9,%r14,4), %ebp
addl -4(%r11,%r14,4), %ebp
addl (%r11,%r14,4), %ebp
addl 4(%r11,%r14,4), %ebp
addl 4(%r10,%r14,4), %ebp
addl 4(%r9,%r14,4), %ebp
movl (%r10,%r14,4), %r15d
addl (%r9,%r14,4), %ebp
movl %r15d, %r12d
xorl $1, %r12d
movl %ebp, %r13d
xorl $2, %r13d
orl %r12d, %r13d
sete %r12b
cmpl $3, %ebp
sete %bpl
cmpl $2, %r15d
setb %r15b
andb %bpl, %r15b
orb %r12b, %r15b
movzbl %r15b, %ebp
movl %ebp, (%rbx,%r14,4)
leaq 1(%r14), %r15
movq %r15, %r14
cmpq %r15, %rsi
jne .LBB4_4
jmp .LBB4_5
.LBB4_6:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_7: # %._crit_edge22
retq
.Lfunc_end4:
.size _Z12nextGenPixeliii, .Lfunc_end4-_Z12nextGenPixeliii
.cfi_endproc
# -- End function
.globl _Z16copyAndResetDataiii # -- Begin function _Z16copyAndResetDataiii
.p2align 4, 0x90
.type _Z16copyAndResetDataiii,@function
_Z16copyAndResetDataiii: # @_Z16copyAndResetDataiii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
# kill: def $esi killed $esi def $rsi
cmpl %esi, height(%rip)
leal 2(%rsi), %r8d
cmovnel %esi, %r8d
cmpl %edi, %r8d
jle .LBB5_7
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq tmp(%rip), %rax
movq arr(%rip), %rcx
leal 2(%rdx), %esi
movslq %edi, %rdi
movslq %r8d, %r8
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %rdi
cmpq %r8, %rdi
je .LBB5_6
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
cmpl $-1, %edx
jl .LBB5_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movq (%rax,%rdi,8), %r9
movq (%rcx,%rdi,8), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r9,%r11,4), %ebx
movl %ebx, (%r10,%r11,4)
movl $0, (%r9,%r11,4)
incq %r11
cmpq %r11, %rsi
jne .LBB5_4
jmp .LBB5_5
.LBB5_6:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB5_7: # %._crit_edge21
retq
.Lfunc_end5:
.size _Z16copyAndResetDataiii, .Lfunc_end5-_Z16copyAndResetDataiii
.cfi_endproc
# -- End function
.globl _Z8setPixelii # -- Begin function _Z8setPixelii
.p2align 4, 0x90
.type _Z8setPixelii,@function
_Z8setPixelii: # @_Z8setPixelii
.cfi_startproc
# %bb.0:
movq arr(%rip), %rax
movslq %edi, %rcx
movq -8(%rax,%rcx,8), %rdx
movq (%rax,%rcx,8), %rdi
movslq %esi, %rsi
movl -4(%rdi,%rsi,4), %r8d
addl -4(%rdx,%rsi,4), %r8d
movl (%rdi,%rsi,4), %r9d
movq 8(%rax,%rcx,8), %rax
addl -4(%rax,%rsi,4), %r8d
addl (%rax,%rsi,4), %r8d
addl 4(%rax,%rsi,4), %r8d
addl 4(%rdi,%rsi,4), %r8d
addl 4(%rdx,%rsi,4), %r8d
addl (%rdx,%rsi,4), %r8d
movl %r9d, %eax
xorl $1, %eax
movl %r8d, %ecx
xorl $2, %ecx
orl %eax, %ecx
sete %al
cmpl $3, %r8d
sete %cl
cmpl $2, %r9d
setb %dl
andb %cl, %dl
orb %al, %dl
movzbl %dl, %eax
retq
.Lfunc_end6:
.size _Z8setPixelii, .Lfunc_end6-_Z8setPixelii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9my_kernelPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type nprocs,@object # @nprocs
.bss
.globl nprocs
.p2align 2, 0x0
nprocs:
.long 0 # 0x0
.size nprocs, 4
.type display,@object # @display
.globl display
.p2align 2, 0x0
display:
.long 0 # 0x0
.size display, 4
.type gen,@object # @gen
.globl gen
.p2align 2, 0x0
gen:
.long 0 # 0x0
.size gen, 4
.type width,@object # @width
.globl width
.p2align 2, 0x0
width:
.long 0 # 0x0
.size width, 4
.type height,@object # @height
.globl height
.p2align 2, 0x0
height:
.long 0 # 0x0
.size height, 4
.type arr,@object # @arr
.globl arr
.p2align 3, 0x0
arr:
.quad 0
.size arr, 8
.type tmp,@object # @tmp
.globl tmp
.p2align 3, 0x0
tmp:
.quad 0
.size tmp, 8
.type tbarrier,@object # @tbarrier
.globl tbarrier
.p2align 3, 0x0
tbarrier:
.zero 32
.size tbarrier, 32
.type begin,@object # @begin
.globl begin
.p2align 3, 0x0
begin:
.zero 16
.size begin, 16
.type end,@object # @end
.globl end
.p2align 3, 0x0
end:
.zero 16
.size end, 16
.type _Z9my_kernelPiS_iii,@object # @_Z9my_kernelPiS_iii
.section .rodata,"a",@progbits
.globl _Z9my_kernelPiS_iii
.p2align 3, 0x0
_Z9my_kernelPiS_iii:
.quad _Z24__device_stub__my_kernelPiS_iii
.size _Z9my_kernelPiS_iii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "error"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Execution time : %2.3f sec\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d x %d matrix\n"
.size .L.str.6, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9my_kernelPiS_iii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Parameter Error!"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "./glife <input file> <display> <nprocs> <# of generation> <width> <height>"
.size .Lstr.1, 75
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "========================================"
.size .Lstr.3, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__my_kernelPiS_iii
.addrsig_sym _Z6ThreadPv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym tbarrier
.addrsig_sym begin
.addrsig_sym end
.addrsig_sym _Z9my_kernelPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9my_kernelPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0030*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe2000fffe13f */
/*0070*/ BSSY B0, 0x360 ; /* 0x000002e000007945 */
/* 0x000fea0003800000 */
/*0080*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf05270 */
/*0090*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fc6000fffe13f */
/*00a0*/ ISETP.EQ.OR P0, PT, R0.reuse, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x040fe20004702670 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fe200078e0203 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fe20000702670 */
/*00e0*/ IMAD.WIDE R4, R0, R17, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc600078e0211 */
/*00f0*/ ISETP.EQ.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fe20008702670 */
/*0100*/ IMAD.WIDE R2, R0, R17, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fd800078e0211 */
/*0110*/ @P0 BRA 0x340 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*0120*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe20000000800 */
/*0130*/ IADD3 R8, R0.reuse, -c[0x0][0x174], RZ ; /* 0x80005d0000087a10 */
/* 0x040fe20007ffe0ff */
/*0140*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fe2000f8e333f */
/*0150*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011400 */
/*0160*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000406020e7981 */
/* 0x000ea2000c1e1900 */
/*0170*/ LEA R12, P0, R0, c[0x0][0x160], 0x2 ; /* 0x00005800000c7a11 */
/* 0x000fe200078010ff */
/*0180*/ IMAD.WIDE R8, R8, R17, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe400078e0211 */
/*0190*/ IADD3 R6, R0.reuse, UR5, RZ ; /* 0x0000000500067c10 */
/* 0x040fe4000fffe0ff */
/*01a0*/ IADD3 R10, R0, UR4, RZ ; /* 0x00000004000a7c10 */
/* 0x000fc4000fffe0ff */
/*01b0*/ LEA.HI.X R13, R0, c[0x0][0x164], R11, 0x2, P0 ; /* 0x00005900000d7a11 */
/* 0x000fe200000f140b */
/*01c0*/ IMAD.WIDE R6, R6, R17.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe200078e0211 */
/*01d0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x0000e8000c1e1900 */
/*01e0*/ LDG.E R15, [R6.64] ; /* 0x00000006060f7981 */
/* 0x000ee2000c1e1900 */
/*01f0*/ IMAD.WIDE R10, R10, R17, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc600078e0211 */
/*0200*/ LDG.E R0, [R6.64+0x8] ; /* 0x0000080606007981 */
/* 0x000ee2000c1e1900 */
/*0210*/ IMAD.WIDE R12, R17, c[0x0][0x174], R12 ; /* 0x00005d00110c7a25 */
/* 0x000fc600078e020c */
/*0220*/ LDG.E R17, [R2.64+-0x4] ; /* 0xfffffc0602117981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R16, [R12.64] ; /* 0x000000060c107981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004060c137981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x001f62000c1e1900 */
/*0270*/ IADD3 R0, R0, R8, R15 ; /* 0x0000000800007210 */
/* 0x008fc80007ffe00f */
/*0280*/ IADD3 R0, R14, R0, R17 ; /* 0x000000000e007210 */
/* 0x004fc80007ffe011 */
/*0290*/ IADD3 R0, R16, R0, R11 ; /* 0x0000000010007210 */
/* 0x010fca0007ffe00b */
/*02a0*/ IMAD.IADD R0, R0, 0x1, R19 ; /* 0x0000000100007824 */
/* 0x020fca00078e0213 */
/*02b0*/ LOP3.LUT R6, R0.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x0000000100067812 */
/* 0x040fe400078efcff */
/*02c0*/ ISETP.NE.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f05270 */
/*02d0*/ ISETP.NE.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f25270 */
/*02e0*/ ISETP.EQ.AND P0, PT, R9.reuse, RZ, !P0 ; /* 0x000000ff0900720c */
/* 0x040fe40004702270 */
/*02f0*/ ISETP.EQ.AND P1, PT, R9, 0x1, !P1 ; /* 0x000000010900780c */
/* 0x000fc80004f22270 */
/*0300*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80000703570 */
/*0310*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0320*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101906 */
/*0330*/ BRA 0x350 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000164000c1e1900 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x020fe8000c101906 */
/*0370*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101906 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9my_kernelPiS_iii
.globl _Z9my_kernelPiS_iii
.p2align 8
.type _Z9my_kernelPiS_iii,@function
_Z9my_kernelPiS_iii:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s8, 0xffff
s_cmp_lg_u32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_cselect_b32 s1, -1, 0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s2
s_cselect_b32 s2, -1, 0
s_add_i32 s0, s3, -1
s_and_b32 s1, s1, s2
v_cmp_ne_u32_e64 s0, s0, v0
v_ashrrev_i32_e32 v2, 31, v1
s_and_b32 s1, vcc_lo, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s8, s0
s_cbranch_execz .LBB0_2
v_subrev_nc_u32_e32 v3, s3, v1
v_add_nc_u32_e32 v5, s3, v1
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-4
global_load_b64 v[3:4], v[3:4], off
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_clause 0x3
global_load_b32 v11, v[9:10], off offset:-4
global_load_b64 v[9:10], v[9:10], off
global_load_b32 v12, v[5:6], off offset:-4
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(4)
v_add_nc_u32_e32 v0, v3, v0
s_waitcnt vmcnt(2)
v_cmp_eq_u32_e32 vcc_lo, 1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add3_u32 v0, v0, v4, v11
v_cmp_gt_u32_e64 s0, 2, v9
s_waitcnt vmcnt(1)
v_add3_u32 v0, v0, v10, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, v5, v6
v_cmp_eq_u32_e64 s1, 2, v0
v_cmp_eq_u32_e64 s2, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 s1, vcc_lo, s1
s_and_b32 s0, s0, s2
v_add_co_u32 v3, vcc_lo, s6, v7
s_or_b32 s0, s1, s0
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v8, vcc_lo
v_cndmask_b32_e64 v0, 0, 1, s0
global_store_b32 v[3:4], v0, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9my_kernelPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9my_kernelPiS_iii, .Lfunc_end0-_Z9my_kernelPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9my_kernelPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9my_kernelPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a9c58_00000000-6_gameoflife.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12cudaNeighborPiii
.type _Z12cudaNeighborPiii, @function
_Z12cudaNeighborPiii:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z12cudaNeighborPiii, .-_Z12cudaNeighborPiii
.globl _Z16copyAndResetDataiii
.type _Z16copyAndResetDataiii, @function
_Z16copyAndResetDataiii:
.LFB2071:
.cfi_startproc
endbr64
movl %edx, %r9d
cmpl %esi, height(%rip)
je .L14
.L6:
cmpl %edi, %esi
jle .L5
movslq %edi, %rax
leaq 0(,%rax,8), %rdx
subl %edi, %esi
leaq (%rsi,%rax), %r8
salq $3, %r8
leal 1(%r9), %eax
leaq 4(,%rax,4), %rdi
jmp .L8
.L14:
addl $2, %esi
jmp .L6
.L9:
movq tmp(%rip), %rcx
movq (%rcx,%rdx), %rcx
movl (%rcx,%rax), %esi
movq arr(%rip), %rcx
movq (%rcx,%rdx), %rcx
movl %esi, (%rcx,%rax)
movq tmp(%rip), %rcx
movq (%rcx,%rdx), %rcx
movl $0, (%rcx,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L9
.L10:
addq $8, %rdx
cmpq %r8, %rdx
je .L5
.L8:
movl $0, %eax
cmpl $-1, %r9d
jge .L9
jmp .L10
.L5:
ret
.cfi_endproc
.LFE2071:
.size _Z16copyAndResetDataiii, .-_Z16copyAndResetDataiii
.globl _Z8setPixelii
.type _Z8setPixelii, @function
_Z8setPixelii:
.LFB2072:
.cfi_startproc
endbr64
movq arr(%rip), %rdx
movslq %edi, %rdi
leaq 0(,%rdi,8), %r8
movq (%rdx,%rdi,8), %rdi
movslq %esi, %rsi
leaq 0(,%rsi,4), %rax
movl (%rdi,%rsi,4), %r9d
movq -8(%rdx,%r8), %rcx
movq 8(%rdx,%r8), %r8
movl -4(%rdi,%rax), %edx
addl -4(%rcx,%rax), %edx
addl -4(%r8,%rax), %edx
addl (%r8,%rsi,4), %edx
addl 4(%r8,%rax), %edx
addl 4(%rdi,%rax), %edx
addl 4(%rcx,%rax), %edx
addl (%rcx,%rsi,4), %edx
leal -2(%rdx), %eax
cmpl $1, %eax
ja .L19
movl $1, %eax
cmpl $1, %r9d
je .L15
.L19:
testl %r9d, %r9d
sete %cl
cmpl $3, %edx
sete %al
movzbl %al, %eax
andl %ecx, %eax
.L15:
ret
.cfi_endproc
.LFE2072:
.size _Z8setPixelii, .-_Z8setPixelii
.globl _Z12nextGenPixeliii
.type _Z12nextGenPixeliii, @function
_Z12nextGenPixeliii:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %r13d
movl %esi, %ecx
movl %edx, 4(%rsp)
testl %edi, %edi
movl $1, %eax
cmove %eax, %r13d
cmpl %esi, height(%rip)
sete %al
movzbl %al, %eax
addl %eax, %ecx
movl %ecx, (%rsp)
cmpl %ecx, %r13d
jge .L20
movslq %r13d, %r14
salq $3, %r14
leal 1(%rdx), %r15d
jmp .L24
.L25:
movq tmp(%rip), %rax
movq %rbp, %r12
addq (%rax,%r14), %r12
movl %ebx, %esi
movl %r13d, %edi
call _Z8setPixelii
movl %eax, (%r12)
addl $1, %ebx
addq $4, %rbp
cmpl %r15d, %ebx
jne .L25
.L27:
addl $1, %r13d
addq $8, %r14
cmpl %r13d, (%rsp)
je .L20
.L24:
movl $4, %ebp
movl $1, %ebx
cmpl $0, 4(%rsp)
jg .L25
jmp .L27
.L20:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z12nextGenPixeliii, .-_Z12nextGenPixeliii
.globl _Z6ThreadPv
.type _Z6ThreadPv, @function
_Z6ThreadPv:
.LFB2069:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq tbarrier(%rip), %rbp
.L33:
movl 4(%rbx), %esi
movl (%rbx), %edi
movl width(%rip), %edx
call _Z12nextGenPixeliii
movq %rbp, %rdi
call pthread_barrier_wait@PLT
movl 4(%rbx), %esi
movl (%rbx), %edi
movl width(%rip), %edx
call _Z16copyAndResetDataiii
movq %rbp, %rdi
call pthread_barrier_wait@PLT
jmp .L33
.cfi_endproc
.LFE2069:
.size _Z6ThreadPv, .-_Z6ThreadPv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d x %d matrix\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "========================================\n"
.section .rodata.str1.1
.LC2:
.string "o"
.LC3:
.string "-"
.LC4:
.string "\n"
.text
.globl _Z4dumpv
.type _Z4dumpv, @function
_Z4dumpv:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl height(%rip), %ecx
movl width(%rip), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, %ebp
movl $1, %r13d
leaq .LC3(%rip), %r12
leaq .LC2(%rip), %r14
leaq .LC4(%rip), %r15
cmpl $0, height(%rip)
jg .L36
.L37:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L39:
addq $1, %rbx
leal 1(%rbx), %eax
cmpl %eax, width(%rip)
jl .L41
.L40:
movq arr(%rip), %rax
movq (%rax,%rbp), %rax
cmpl $1, 4(%rax,%rbx,4)
jne .L38
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L41:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq $8, %rbp
cmpl %r13d, height(%rip)
jl .L37
.L36:
movl $0, %ebx
cmpl $0, width(%rip)
jg .L40
jmp .L41
.cfi_endproc
.LFE2073:
.size _Z4dumpv, .-_Z4dumpv
.globl _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii
.type _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii, @function
_Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9my_kernelPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii, .-_Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii
.globl _Z9my_kernelPiS_iii
.type _Z9my_kernelPiS_iii, @function
_Z9my_kernelPiS_iii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z9my_kernelPiS_iii, .-_Z9my_kernelPiS_iii
.section .rodata.str1.1
.LC5:
.string "Parameter Error!\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "./glife <input file> <display> <nprocs> <# of generation> <width> <height>\n"
.section .rodata.str1.1
.LC7:
.string "r"
.LC8:
.string "error"
.LC9:
.string " "
.LC11:
.string "Execution time : %2.3f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2068:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $488, %rsp
.cfi_def_cfa_offset 544
movq %fs:40, %rax
movq %rax, 472(%rsp)
xorl %eax, %eax
cmpl $7, %edi
jne .L104
movq %rsi, %r12
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, display(%rip)
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, nprocs(%rip)
movq 32(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, gen(%rip)
movq 40(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, width(%rip)
movq 48(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, height(%rip)
leal 2(%rax), %r15d
movslq %r15d, %rax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, arr(%rip)
cmpl $-1, %ebx
jl .L58
leal 1(%rbx), %eax
leaq 8(,%rax,8), %r13
movl $0, %ebp
.L59:
movl width(%rip), %eax
leal 2(%rax), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbp, %r14
addq arr(%rip), %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%r14)
addq $8, %rbp
cmpq %r13, %rbp
jne .L59
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, tmp(%rip)
movl $0, %ebp
.L60:
movq %rbp, %r14
addq tmp(%rip), %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%r14)
addq $8, %rbp
cmpq %r13, %rbp
jne .L60
movl width(%rip), %eax
addl $2, %eax
imull %r15d, %eax
sall $2, %eax
movslq %eax, %r15
movq %r15, 8(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0, %r8d
jmp .L84
.L104:
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movq arr(%rip), %rax
movq (%rax,%rsi), %rax
movl $0, (%rax,%rdx,4)
movq tmp(%rip), %rax
movq (%rax,%rsi), %rax
movl $0, (%rax,%rdx,4)
movl width(%rip), %ecx
leal 2(%rcx), %eax
imull %edi, %eax
addl %edx, %eax
cltq
movl $0, (%rbx,%rax,4)
movl $0, 0(%rbp,%rax,4)
addq $1, %rdx
leal -1(%rdx), %eax
cmpl %eax, %ecx
jge .L62
.L65:
addq $1, %r8
leal -1(%r8), %eax
cmpl %eax, height(%rip)
jl .L63
.L84:
movl %r8d, %edi
leaq 0(,%r8,8), %rsi
movl $0, %edx
cmpl $-1, width(%rip)
jge .L62
jmp .L65
.L101:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $2, %edi
call exit@PLT
.L67:
leaq 448(%rsp), %rdi
movq %r14, %rsi
call strtok@PLT
movq %rax, %r12
movq %r14, %rsi
movl $0, %edi
call strtok@PLT
movq %rax, %r13
movl $10, %edx
movl $0, %esi
movq %r12, %rdi
call __isoc23_strtol@PLT
movq %rax, %r12
movl $10, %edx
movl $0, %esi
movq %r13, %rdi
call __isoc23_strtol@PLT
movq %rax, %rdx
movslq %eax, %rsi
movslq %r12d, %rcx
movq arr(%rip), %rax
movq (%rax,%rsi,8), %rax
movl $1, (%rax,%rcx,4)
movl width(%rip), %eax
addl $2, %eax
imull %edx, %eax
addl %r12d, %eax
cltq
movl $1, (%rbx,%rax,4)
.L66:
leaq 448(%rsp), %rdi
movq %r15, %rcx
movl $20, %edx
movl $20, %esi
call __fgets_chk@PLT
testq %rax, %rax
jne .L67
movl nprocs(%rip), %r12d
testl %r12d, %r12d
je .L105
movl height(%rip), %r10d
movl %r10d, %eax
cltd
idivl %r12d
testl %r12d, %r12d
jle .L77
leaq 256(%rsp), %rcx
movl $0, %edx
movl $0, %edi
movl $0, %esi
leal -1(%r12), %r9d
jmp .L79
.L105:
leaq begin(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
leaq 24(%rsp), %rdi
movq 8(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, gen(%rip)
jg .L71
.L69:
movl $2, %ecx
movq 8(%rsp), %r15
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r15, %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq end(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $0, %r8d
cmpl $-1, height(%rip)
jge .L72
jmp .L73
.L70:
call cudaDeviceSynchronize@PLT
addl $1, %r12d
cmpl %r12d, gen(%rip)
jle .L69
.L71:
movl width(%rip), %eax
addl $2, %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl height(%rip), %eax
addl $2, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L70
movl width(%rip), %eax
leal 2(%rax), %ecx
movl height(%rip), %eax
leal 2(%rax), %edx
movl gen(%rip), %r8d
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9my_kernelPiS_iiiPiS_iii
jmp .L70
.L74:
addl $2, %eax
imull %edi, %eax
addl %edx, %eax
cltq
movl (%rbx,%rax,4), %ecx
movq arr(%rip), %rax
movq (%rax,%rsi), %rax
movl %ecx, (%rax,%rdx,4)
movl width(%rip), %eax
addq $1, %rdx
leal -1(%rdx), %ecx
cmpl %ecx, %eax
jge .L74
.L76:
addq $1, %r8
leal -1(%r8), %eax
cmpl %eax, height(%rip)
jl .L73
.L72:
movl %r8d, %edi
movl width(%rip), %eax
leaq 0(,%r8,8), %rsi
movl $0, %edx
cmpl $-1, %eax
jge .L74
jmp .L76
.L87:
movl %r10d, %edi
movl %esi, %r8d
.L78:
movl %esi, (%rcx)
movl %edi, 4(%rcx)
addl $1, %edx
addq $8, %rcx
cmpl %edx, %r12d
je .L77
movl %r8d, %esi
.L79:
cmpl %edx, %r9d
je .L87
addl %eax, %edi
leal (%rax,%rsi), %r8d
jmp .L78
.L77:
movl %r12d, %edx
movl $0, %esi
leaq tbarrier(%rip), %rdi
call pthread_barrier_init@PLT
leaq begin(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $0, nprocs(%rip)
jle .L80
leaq 64(%rsp), %r13
movl $0, %r12d
leaq _Z6ThreadPv(%rip), %r14
.L81:
leaq 256(%rsp,%r12,8), %rcx
movq %r14, %rdx
movl $0, %esi
movq %r13, %rdi
call pthread_create@PLT
movl nprocs(%rip), %eax
addq $1, %r12
addq $8, %r13
cmpl %r12d, %eax
jg .L81
testl %eax, %eax
jle .L80
movl $0, %r12d
.L82:
movq 64(%rsp,%r12,8), %rdi
movl $0, %esi
call pthread_join@PLT
addq $1, %r12
cmpl %r12d, nprocs(%rip)
jg .L82
.L80:
leaq end(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
leaq tbarrier(%rip), %rdi
call pthread_barrier_destroy@PLT
.L73:
movq 8+end(%rip), %rax
subq 8+begin(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
movq end(%rip), %rax
subq begin(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $1, display(%rip)
je .L106
.L83:
movq arr(%rip), %rdi
call free@PLT
movq tmp(%rip), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 472(%rsp), %rax
subq %fs:40, %rax
jne .L107
movl $0, %eax
addq $488, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore_state
call _Z4dumpv
jmp .L83
.L58:
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, tmp(%rip)
movl width(%rip), %eax
addl $2, %eax
imull %r15d, %eax
sall $2, %eax
movslq %eax, %r15
movq %r15, 8(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
.L63:
movq 8(%r12), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %r15
testq %rax, %rax
je .L101
leaq .LC9(%rip), %r14
jmp .L66
.L107:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9my_kernelPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9my_kernelPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl end
.bss
.align 16
.type end, @object
.size end, 16
end:
.zero 16
.globl begin
.align 16
.type begin, @object
.size begin, 16
begin:
.zero 16
.globl tbarrier
.align 32
.type tbarrier, @object
.size tbarrier, 32
tbarrier:
.zero 32
.globl tmp
.align 8
.type tmp, @object
.size tmp, 8
tmp:
.zero 8
.globl arr
.align 8
.type arr, @object
.size arr, 8
arr:
.zero 8
.globl height
.align 4
.type height, @object
.size height, 4
height:
.zero 4
.globl width
.align 4
.type width, @object
.size width, 4
width:
.zero 4
.globl gen
.align 4
.type gen, @object
.size gen, 4
gen:
.zero 4
.globl display
.align 4
.type display, @object
.size display, 4
display:
.zero 4
.globl nprocs
.align 4
.type nprocs, @object
.size nprocs, 4
nprocs:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gameoflife.hip"
.globl _Z24__device_stub__my_kernelPiS_iii # -- Begin function _Z24__device_stub__my_kernelPiS_iii
.p2align 4, 0x90
.type _Z24__device_stub__my_kernelPiS_iii,@function
_Z24__device_stub__my_kernelPiS_iii: # @_Z24__device_stub__my_kernelPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9my_kernelPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__my_kernelPiS_iii, .Lfunc_end0-_Z24__device_stub__my_kernelPiS_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $520, %rsp # imm = 0x208
.cfi_def_cfa_offset 576
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $7, %edi
jne .LBB1_45
# %bb.1:
movq %rsi, %rbx
movq 16(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, display(%rip)
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nprocs(%rip)
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, gen(%rip)
movq 40(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, width(%rip)
movq %rbx, 40(%rsp) # 8-byte Spill
movq 48(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %ebx, height(%rip)
leal 2(%rax), %ebp
movslq %ebx, %r15
leaq 16(,%r15,8), %r14
movq %r14, %rdi
callq malloc
movq %rax, arr(%rip)
cmpl $-1, %r15d
jl .LBB1_4
# %bb.2: # %.lr.ph
movslq width(%rip), %rax
leaq 8(,%rax,4), %r15
cmpl $2, %ebp
movl $1, %r13d
cmovgel %ebp, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq malloc
movq arr(%rip), %rcx
movq %rax, (%rcx,%r12,8)
incq %r12
cmpq %r12, %r13
jne .LBB1_3
.LBB1_4: # %._crit_edge
movq %r14, %rdi
callq malloc
movq %rax, tmp(%rip)
cmpl $-1, %ebx
jl .LBB1_7
# %bb.5: # %.lr.ph114
movslq width(%rip), %rax
leaq 8(,%rax,4), %rbx
cmpl $2, %ebp
movl $1, %r14d
cmovgel %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq malloc
movq tmp(%rip), %rcx
movq %rax, (%rcx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_6
.LBB1_7: # %._crit_edge115
movl width(%rip), %eax
addl $2, %eax
imull %eax, %ebp
shll $2, %ebp
movslq %ebp, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, 32(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r14
cmpl $-1, height(%rip)
jl .LBB1_13
# %bb.8: # %.preheader110.lr.ph
movq arr(%rip), %rax
movq tmp(%rip), %rcx
xorl %edx, %edx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # %._crit_edge118
# in Loop: Header=BB1_9 Depth=1
leaq 1(%rdx), %rsi
movslq height(%rip), %rdi
cmpq %rdi, %rdx
movq %rsi, %rdx
jg .LBB1_13
.LBB1_9: # %.preheader110
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
cmpl $-1, width(%rip)
jl .LBB1_12
# %bb.10: # %.lr.ph117
# in Loop: Header=BB1_9 Depth=1
movq (%rax,%rdx,8), %rsi
movq (%rcx,%rdx,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%rsi,%r8,4)
movl $0, (%rdi,%r8,4)
movl width(%rip), %r9d
addl $2, %r9d
imull %edx, %r9d
addl %r8d, %r9d
movslq %r9d, %r9
movl $0, (%rbx,%r9,4)
movl $0, (%r14,%r9,4)
leaq 1(%r8), %r9
movslq width(%rip), %r10
cmpq %r10, %r8
movq %r9, %r8
jle .LBB1_11
jmp .LBB1_12
.LBB1_13: # %._crit_edge120
movq 40(%rsp), %rax # 8-byte Reload
movq 8(%rax), %rdi
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB1_46
# %bb.14: # %.preheader109
movq %rax, %r12
leaq 96(%rsp), %rdi
movl $20, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB1_17
# %bb.15:
leaq 96(%rsp), %r13
.p2align 4, 0x90
.LBB1_16: # %.lr.ph122
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %esi
movq %r13, %rdi
callq strtok
movq %rax, %rbp
movl $.L.str.4, %esi
xorl %edi, %edi
callq strtok
movq %rax, %r15
movq %rbp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq arr(%rip), %rcx
cltq
movq (%rcx,%rax,8), %rcx
movslq %ebp, %rdx
movl $1, (%rcx,%rdx,4)
movl width(%rip), %ecx
addl $2, %ecx
imull %ecx, %eax
addl %eax, %edx
movslq %edx, %rax
movl $1, (%rbx,%rax,4)
movq %r13, %rdi
movl $20, %esi
movq %r12, %rdx
callq fgets
testq %rax, %rax
jne .LBB1_16
.LBB1_17: # %._crit_edge123
movl nprocs(%rip), %ecx
testq %rcx, %rcx
je .LBB1_18
# %bb.29:
movl height(%rip), %esi
movl %esi, %eax
cltd
idivl %ecx
testl %ecx, %ecx
jle .LBB1_33
# %bb.30: # %.lr.ph128
leal -1(%rcx), %edx
xorl %edi, %edi
xorl %r9d, %r9d
xorl %r8d, %r8d
jmp .LBB1_31
.p2align 4, 0x90
.LBB1_43: # in Loop: Header=BB1_31 Depth=1
addl %eax, %r9d
movl %r8d, 128(%rsp,%rdi,8)
movl %r9d, 132(%rsp,%rdi,8)
addl %eax, %r8d
.LBB1_44: # in Loop: Header=BB1_31 Depth=1
incq %rdi
cmpq %rdi, %rcx
je .LBB1_33
.LBB1_31: # =>This Inner Loop Header: Depth=1
cmpq %rdi, %rdx
jne .LBB1_43
# %bb.32: # in Loop: Header=BB1_31 Depth=1
movl %r8d, 128(%rsp,%rdi,8)
movl %esi, 132(%rsp,%rdi,8)
movl %esi, %r9d
jmp .LBB1_44
.LBB1_33: # %._crit_edge129
movl $tbarrier, %edi
xorl %esi, %esi
movl %ecx, %edx
callq pthread_barrier_init
movl $begin, %esi
movl $1, %edi
callq clock_gettime
cmpl $0, nprocs(%rip)
jle .LBB1_36
# %bb.34: # %.lr.ph132.preheader
leaq 128(%rsp), %r15
leaq 320(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_35: # %.lr.ph132
# =>This Inner Loop Header: Depth=1
movl $_Z6ThreadPv, %edx
movq %r12, %rdi
xorl %esi, %esi
movq %r15, %rcx
callq pthread_create
incq %r13
movslq nprocs(%rip), %rax
addq $8, %r15
addq $8, %r12
cmpq %rax, %r13
jl .LBB1_35
.LBB1_36: # %.preheader108
cmpl $0, nprocs(%rip)
jle .LBB1_39
# %bb.37: # %.lr.ph134.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_38: # %.lr.ph134
# =>This Inner Loop Header: Depth=1
movq 320(%rsp,%r15,8), %rdi
xorl %esi, %esi
callq pthread_join
incq %r15
movslq nprocs(%rip), %rax
cmpq %rax, %r15
jl .LBB1_38
.LBB1_39: # %._crit_edge135
movl $end, %esi
movl $1, %edi
callq clock_gettime
movl $tbarrier, %edi
callq pthread_barrier_destroy
jmp .LBB1_40
.LBB1_18:
movl $begin, %esi
movl $1, %edi
callq clock_gettime
leaq 8(%rsp), %rdi
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
cmpl $0, gen(%rip)
jle .LBB1_23
# %bb.19: # %.lr.ph138
xorl %r15d, %r15d
movabsq $4294967296, %rbp # imm = 0x100000000
leaq 48(%rsp), %r12
leaq 320(%rsp), %r13
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_22: # in Loop: Header=BB1_20 Depth=1
callq hipDeviceSynchronize
incl %r15d
cmpl gen(%rip), %r15d
jge .LBB1_23
.LBB1_20: # =>This Inner Loop Header: Depth=1
movl height(%rip), %edi
addl $2, %edi
movl width(%rip), %edx
addl $2, %edx
orq %rbp, %rdi
orq %rbp, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_22
# %bb.21: # in Loop: Header=BB1_20 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl height(%rip), %edx
addl $2, %edx
movl width(%rip), %esi
addl $2, %esi
movl gen(%rip), %edi
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
movl %esi, 24(%rsp)
movl %edi, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 320(%rsp)
leaq 80(%rsp), %rax
movq %rax, 328(%rsp)
leaq 28(%rsp), %rax
movq %rax, 336(%rsp)
leaq 24(%rsp), %rax
movq %rax, 344(%rsp)
leaq 20(%rsp), %rax
movq %rax, 352(%rsp)
leaq 128(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z9my_kernelPiS_iii, %edi
movq %r13, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_22
.LBB1_23: # %._crit_edge139
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $end, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, height(%rip)
jl .LBB1_40
# %bb.24: # %.preheader.lr.ph
movq arr(%rip), %rax
xorl %ecx, %ecx
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_28: # %._crit_edge142
# in Loop: Header=BB1_25 Depth=1
leaq 1(%rcx), %rdx
movslq height(%rip), %rsi
cmpq %rsi, %rcx
movq %rdx, %rcx
jg .LBB1_40
.LBB1_25: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_27 Depth 2
movl width(%rip), %edx
cmpl $-1, %edx
jl .LBB1_28
# %bb.26: # %.lr.ph141
# in Loop: Header=BB1_25 Depth=1
addl $2, %edx
movq (%rax,%rcx,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_27: # Parent Loop BB1_25 Depth=1
# => This Inner Loop Header: Depth=2
imull %ecx, %edx
addl %edi, %edx
movslq %edx, %rdx
movl (%rbx,%rdx,4), %edx
movl %edx, (%rsi,%rdi,4)
incq %rdi
movslq width(%rip), %rdx
addq $2, %rdx
cmpq %rdx, %rdi
jl .LBB1_27
jmp .LBB1_28
.LBB1_40: # %.loopexit
movq end(%rip), %rax
subq begin(%rip), %rax
cvtsi2sd %rax, %xmm1
movq end+8(%rip), %rax
subq begin+8(%rip), %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
cmpl $1, display(%rip)
jne .LBB1_42
# %bb.41:
callq _Z4dumpv
.LBB1_42:
movq arr(%rip), %rdi
callq free
movq tmp(%rip), %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $520, %rsp # imm = 0x208
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_45:
.cfi_def_cfa_offset 576
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_46:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $5, %esi
movl $1, %edx
callq fwrite@PLT
movl $2, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z6ThreadPv # -- Begin function _Z6ThreadPv
.p2align 4, 0x90
.type _Z6ThreadPv,@function
_Z6ThreadPv: # @_Z6ThreadPv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
movq %rdi, (%rsp) # 8-byte Spill
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_13: # %_Z16copyAndResetDataiii.exit
# in Loop: Header=BB2_1 Depth=1
movl $tbarrier, %edi
callq pthread_barrier_wait
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_9 Depth 2
# Child Loop BB2_11 Depth 3
movl (%r14), %edi
cmpl $1, %edi
adcl $0, %edi
movl 4(%r14), %eax
xorl %r8d, %r8d
cmpl %eax, height(%rip)
sete %r8b
addl %eax, %r8d
cmpl %r8d, %edi
jge .LBB2_7
# %bb.2: # %.preheader.lr.ph.i
# in Loop: Header=BB2_1 Depth=1
movl width(%rip), %eax
movq arr(%rip), %rcx
movq tmp(%rip), %rdx
leal 1(%rax), %esi
movslq %edi, %rdi
movslq %r8d, %r8
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_6: # %._crit_edge.i
# in Loop: Header=BB2_3 Depth=2
incq %rdi
cmpq %r8, %rdi
je .LBB2_7
.LBB2_3: # %.preheader.i
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_5 Depth 3
testl %eax, %eax
jle .LBB2_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB2_3 Depth=2
movq -8(%rcx,%rdi,8), %r9
movq (%rcx,%rdi,8), %r10
movq 8(%rcx,%rdi,8), %r11
movq (%rdx,%rdi,8), %r14
movl $1, %r15d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movl -4(%r10,%r15,4), %ebx
addl -4(%r9,%r15,4), %ebx
addl -4(%r11,%r15,4), %ebx
addl (%r11,%r15,4), %ebx
addl 4(%r11,%r15,4), %ebx
addl 4(%r10,%r15,4), %ebx
addl 4(%r9,%r15,4), %ebx
movl (%r10,%r15,4), %r12d
addl (%r9,%r15,4), %ebx
movl %r12d, %r13d
xorl $1, %r13d
movl %ebx, %ebp
xorl $2, %ebp
orl %r13d, %ebp
sete %bpl
cmpl $3, %ebx
sete %bl
cmpl $2, %r12d
setb %r12b
andb %bl, %r12b
orb %bpl, %r12b
movzbl %r12b, %ebx
movl %ebx, (%r14,%r15,4)
leaq 1(%r15), %rbx
movq %rbx, %r15
cmpq %rbx, %rsi
jne .LBB2_5
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_7: # %_Z12nextGenPixeliii.exit
# in Loop: Header=BB2_1 Depth=1
movl $tbarrier, %edi
callq pthread_barrier_wait
movq (%rsp), %r14 # 8-byte Reload
movslq (%r14), %rax
movl 4(%r14), %ecx
cmpl %ecx, height(%rip)
leal 2(%rcx), %r8d
cmovnel %ecx, %r8d
cmpl %eax, %r8d
jle .LBB2_13
# %bb.8: # %.preheader.lr.ph.i7
# in Loop: Header=BB2_1 Depth=1
movl width(%rip), %ecx
movq tmp(%rip), %rdx
movq arr(%rip), %rsi
leal 2(%rcx), %edi
movslq %r8d, %r8
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_12: # %._crit_edge.i9
# in Loop: Header=BB2_9 Depth=2
incq %rax
cmpq %r8, %rax
je .LBB2_13
.LBB2_9: # %.preheader.i8
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_11 Depth 3
cmpl $-1, %ecx
jl .LBB2_12
# %bb.10: # %.lr.ph.i10
# in Loop: Header=BB2_9 Depth=2
movq (%rdx,%rax,8), %r9
movq (%rsi,%rax,8), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_11: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_9 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9,%r11,4), %ebx
movl %ebx, (%r10,%r11,4)
movl $0, (%r9,%r11,4)
incq %r11
cmpq %r11, %rdi
jne .LBB2_11
jmp .LBB2_12
.Lfunc_end2:
.size _Z6ThreadPv, .Lfunc_end2-_Z6ThreadPv
.cfi_endproc
# -- End function
.globl _Z4dumpv # -- Begin function _Z4dumpv
.p2align 4, 0x90
.type _Z4dumpv,@function
_Z4dumpv: # @_Z4dumpv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl width(%rip), %esi
movl height(%rip), %edx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, height(%rip)
jle .LBB3_8
# %bb.1: # %.preheader.preheader
movl $1, %ebx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%rbx), %rax
movslq height(%rip), %rcx
cmpq %rcx, %rbx
movq %rax, %rbx
jge .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, width(%rip)
jle .LBB3_7
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
xorl %r14d, %r14d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # %.lr.ph
# in Loop: Header=BB3_4 Depth=2
callq putchar@PLT
movslq width(%rip), %rax
incq %r14
cmpq %rax, %r14
jge .LBB3_7
.LBB3_4: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movq arr(%rip), %rax
movq (%rax,%rbx,8), %rax
cmpl $1, 4(%rax,%r14,4)
movl $111, %edi
je .LBB3_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB3_4 Depth=2
movl $45, %edi
jmp .LBB3_6
.LBB3_8: # %._crit_edge15
movl $.Lstr.3, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z4dumpv, .Lfunc_end3-_Z4dumpv
.cfi_endproc
# -- End function
.globl _Z12nextGenPixeliii # -- Begin function _Z12nextGenPixeliii
.p2align 4, 0x90
.type _Z12nextGenPixeliii,@function
_Z12nextGenPixeliii: # @_Z12nextGenPixeliii
.cfi_startproc
# %bb.0:
cmpl $1, %edi
adcl $0, %edi
xorl %r8d, %r8d
cmpl %esi, height(%rip)
# kill: def $edx killed $edx def $rdx
sete %r8b
addl %esi, %r8d
cmpl %r8d, %edi
jge .LBB4_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq arr(%rip), %rax
movq tmp(%rip), %rcx
leal 1(%rdx), %esi
movslq %edi, %rdi
movslq %r8d, %r8
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %rdi
cmpq %r8, %rdi
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %edx, %edx
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movq -8(%rax,%rdi,8), %r9
movq (%rax,%rdi,8), %r10
movq 8(%rax,%rdi,8), %r11
movq (%rcx,%rdi,8), %rbx
movl $1, %r14d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl -4(%r10,%r14,4), %ebp
addl -4(%r9,%r14,4), %ebp
addl -4(%r11,%r14,4), %ebp
addl (%r11,%r14,4), %ebp
addl 4(%r11,%r14,4), %ebp
addl 4(%r10,%r14,4), %ebp
addl 4(%r9,%r14,4), %ebp
movl (%r10,%r14,4), %r15d
addl (%r9,%r14,4), %ebp
movl %r15d, %r12d
xorl $1, %r12d
movl %ebp, %r13d
xorl $2, %r13d
orl %r12d, %r13d
sete %r12b
cmpl $3, %ebp
sete %bpl
cmpl $2, %r15d
setb %r15b
andb %bpl, %r15b
orb %r12b, %r15b
movzbl %r15b, %ebp
movl %ebp, (%rbx,%r14,4)
leaq 1(%r14), %r15
movq %r15, %r14
cmpq %r15, %rsi
jne .LBB4_4
jmp .LBB4_5
.LBB4_6:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_7: # %._crit_edge22
retq
.Lfunc_end4:
.size _Z12nextGenPixeliii, .Lfunc_end4-_Z12nextGenPixeliii
.cfi_endproc
# -- End function
.globl _Z16copyAndResetDataiii # -- Begin function _Z16copyAndResetDataiii
.p2align 4, 0x90
.type _Z16copyAndResetDataiii,@function
_Z16copyAndResetDataiii: # @_Z16copyAndResetDataiii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
# kill: def $esi killed $esi def $rsi
cmpl %esi, height(%rip)
leal 2(%rsi), %r8d
cmovnel %esi, %r8d
cmpl %edi, %r8d
jle .LBB5_7
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq tmp(%rip), %rax
movq arr(%rip), %rcx
leal 2(%rdx), %esi
movslq %edi, %rdi
movslq %r8d, %r8
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %rdi
cmpq %r8, %rdi
je .LBB5_6
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
cmpl $-1, %edx
jl .LBB5_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movq (%rax,%rdi,8), %r9
movq (%rcx,%rdi,8), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r9,%r11,4), %ebx
movl %ebx, (%r10,%r11,4)
movl $0, (%r9,%r11,4)
incq %r11
cmpq %r11, %rsi
jne .LBB5_4
jmp .LBB5_5
.LBB5_6:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB5_7: # %._crit_edge21
retq
.Lfunc_end5:
.size _Z16copyAndResetDataiii, .Lfunc_end5-_Z16copyAndResetDataiii
.cfi_endproc
# -- End function
.globl _Z8setPixelii # -- Begin function _Z8setPixelii
.p2align 4, 0x90
.type _Z8setPixelii,@function
_Z8setPixelii: # @_Z8setPixelii
.cfi_startproc
# %bb.0:
movq arr(%rip), %rax
movslq %edi, %rcx
movq -8(%rax,%rcx,8), %rdx
movq (%rax,%rcx,8), %rdi
movslq %esi, %rsi
movl -4(%rdi,%rsi,4), %r8d
addl -4(%rdx,%rsi,4), %r8d
movl (%rdi,%rsi,4), %r9d
movq 8(%rax,%rcx,8), %rax
addl -4(%rax,%rsi,4), %r8d
addl (%rax,%rsi,4), %r8d
addl 4(%rax,%rsi,4), %r8d
addl 4(%rdi,%rsi,4), %r8d
addl 4(%rdx,%rsi,4), %r8d
addl (%rdx,%rsi,4), %r8d
movl %r9d, %eax
xorl $1, %eax
movl %r8d, %ecx
xorl $2, %ecx
orl %eax, %ecx
sete %al
cmpl $3, %r8d
sete %cl
cmpl $2, %r9d
setb %dl
andb %cl, %dl
orb %al, %dl
movzbl %dl, %eax
retq
.Lfunc_end6:
.size _Z8setPixelii, .Lfunc_end6-_Z8setPixelii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9my_kernelPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type nprocs,@object # @nprocs
.bss
.globl nprocs
.p2align 2, 0x0
nprocs:
.long 0 # 0x0
.size nprocs, 4
.type display,@object # @display
.globl display
.p2align 2, 0x0
display:
.long 0 # 0x0
.size display, 4
.type gen,@object # @gen
.globl gen
.p2align 2, 0x0
gen:
.long 0 # 0x0
.size gen, 4
.type width,@object # @width
.globl width
.p2align 2, 0x0
width:
.long 0 # 0x0
.size width, 4
.type height,@object # @height
.globl height
.p2align 2, 0x0
height:
.long 0 # 0x0
.size height, 4
.type arr,@object # @arr
.globl arr
.p2align 3, 0x0
arr:
.quad 0
.size arr, 8
.type tmp,@object # @tmp
.globl tmp
.p2align 3, 0x0
tmp:
.quad 0
.size tmp, 8
.type tbarrier,@object # @tbarrier
.globl tbarrier
.p2align 3, 0x0
tbarrier:
.zero 32
.size tbarrier, 32
.type begin,@object # @begin
.globl begin
.p2align 3, 0x0
begin:
.zero 16
.size begin, 16
.type end,@object # @end
.globl end
.p2align 3, 0x0
end:
.zero 16
.size end, 16
.type _Z9my_kernelPiS_iii,@object # @_Z9my_kernelPiS_iii
.section .rodata,"a",@progbits
.globl _Z9my_kernelPiS_iii
.p2align 3, 0x0
_Z9my_kernelPiS_iii:
.quad _Z24__device_stub__my_kernelPiS_iii
.size _Z9my_kernelPiS_iii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "error"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Execution time : %2.3f sec\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d x %d matrix\n"
.size .L.str.6, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9my_kernelPiS_iii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Parameter Error!"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "./glife <input file> <display> <nprocs> <# of generation> <width> <height>"
.size .Lstr.1, 75
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "========================================"
.size .Lstr.3, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__my_kernelPiS_iii
.addrsig_sym _Z6ThreadPv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym tbarrier
.addrsig_sym begin
.addrsig_sym end
.addrsig_sym _Z9my_kernelPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdint.h>
#include <cuda.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName, int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we don't touch other types
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
uint8_t max_val;
fscanf(f, "%hhu", &max_val);
if (max_val > 255)
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we assume 1 byte per value
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(char * fileName, int numChannels, int width, int height, uint8_t * pixels)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
void compare2Pnms(char * fileName1, char * fileName2)
{
int numChannels1, width1, height1;
uint8_t * pixels1;
readPnm(fileName1, numChannels1, width1, height1, pixels1);
int numChannels2, width2, height2;
uint8_t * pixels2;
readPnm(fileName2, numChannels2, width2, height2, pixels2);
if (numChannels1 != numChannels2)
{
printf("'%s' is DIFFERENT from '%s' (num channels: %i vs %i)\n", fileName1, fileName2, numChannels1, numChannels2);
return;
}
if (width1 != width2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, width1, width2);
return;
}
if (height1 != height2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, height1, height2);
return;
}
float mae = 0;
for (int i = 0; i < width1 * height1 * numChannels1; i++)
{
mae += abs((int)pixels1[i]-(int)pixels2[i]);
}
mae /= (width1 * height1 * numChannels1);
printf("The average pixel difference between '%s' and '%s': %f\n", fileName1, fileName2, mae);
}
void convertRgb2GrayByHost(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int size = width * height;
for(int i = 0; i < size; i++){
outPixels[i] = 0.299 * inPixels[i*3] +
0.114 * inPixels[i*3 + 2] +
0.587 * inPixels[i*3 + 1];
}
}
__global__ void convertRgb2GrayByDevice(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int i_r = blockIdx.y * blockDim.y + threadIdx.y;
int i_c = blockIdx.x * blockDim.x + threadIdx.x;
if(i_c < width && i_r < height){
outPixels[i_r * width + i_c] = 0.299 * inPixels[(i_r * width + i_c)*3] +
0.114 * inPixels[(i_r * width + i_c)*3 + 2] +
0.587 * inPixels[(i_r * width + i_c)*3 + 1];
}
}
int main(int argc, char ** argv)
{
// -----READ INPUT DATA-----
if (argc < 5 || argc > 7)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
printf("Image size (width x height): %i x %i\n", width, height);
// -----PROCESS INPUT DATA-----
uint8_t * outPixels= (uint8_t *)malloc(width * height);
GpuTimer timer;
timer.Start();
if (strcmp(argv[4], "cpu") == 0){ // Use CPU
convertRgb2GrayByHost(inPixels, outPixels, width, height);
}
else // Use GPU
{
// TODO: Query and print GPU name and compute capability
cudaDeviceProp prop;
CHECK(cudaGetDeviceProperties(&prop, 0));
printf("GPU name: %s\n", prop.name);
printf("GPU compute capability: %d\n", prop.major);
// TODO: Allocate device memories
uint8_t *d_inPixels, *d_outPixels;
CHECK(cudaMalloc(&d_inPixels, width * height * numChannels));
CHECK(cudaMalloc(&d_outPixels, width * height));
// TODO: Copy data to device memories
CHECK(cudaMemcpy(d_inPixels, inPixels, width * height * numChannels, cudaMemcpyHostToDevice));
// TODO: Set block size (already done for you) and grid size,
// and invoke kernel function with these settings (remember to check kernel error)
dim3 blockSize(32, 32); // Default
if (argc == 7)
{
blockSize.x = atoi(argv[5]);
blockSize.y = atoi(argv[6]);
}
dim3 gridSize((width-1)/blockSize.x + 1, (height-1)/blockSize.y + 1);
printf("Block size: %d x %d\n", blockSize.x, blockSize.y);
printf("Grid size: %d x %d\n", gridSize.x, gridSize.y);
convertRgb2GrayByDevice<<<gridSize, blockSize>>>(d_inPixels, d_outPixels, width, height);
// TODO: Copy result from device memories
CHECK(cudaMemcpy(outPixels, d_outPixels, width * height, cudaMemcpyDeviceToHost));
// TODO: Free device memories
cudaFree(d_inPixels);
cudaFree(d_outPixels);
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time: %f ms\n", time);
// -----WRITE OUTPUT DATA TO FILE-----
writePnm(argv[2], 1, width, height, outPixels);
free(inPixels);
free(outPixels);
// -----CHECK CORRECTNESS-----
compare2Pnms(argv[2], argv[3]);
} | code for sm_80
Function : _Z23convertRgb2GrayByDevicePhS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x170], R3 ; /* 0x00005c0000007a24 */
/* 0x000fe200078e0203 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R3, R0, 0x3, RZ ; /* 0x0000000300037824 */
/* 0x000fca00078e02ff */
/*00d0*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00f0*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x00000204020b7981 */
/* 0x000ea8000c1e1100 */
/*0100*/ LDG.E.U8 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee8000c1e1100 */
/*0110*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010402087981 */
/* 0x000f22000c1e1100 */
/*0120*/ I2F.F64.U16 R6, R11 ; /* 0x0000000b00067312 */
/* 0x004e300000101800 */
/*0130*/ I2F.F64.U16 R4, R10 ; /* 0x0000000a00047312 */
/* 0x008e700000101800 */
/*0140*/ I2F.F64.U16 R8, R8 ; /* 0x0000000800087312 */
/* 0x010ea20000101800 */
/*0150*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e4c0000000000 */
/*0160*/ DFMA R4, R4, c[0x2][0x8], R6 ; /* 0x0080020004047a2b */
/* 0x0020a40000000006 */
/*0170*/ IADD3 R6, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x001fc80007f1e0ff */
/*0180*/ LEA.HI.X.SX32 R7, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000077a11 */
/* 0x000fe200000f0eff */
/*0190*/ DFMA R4, R8, c[0x2][0x10], R4 ; /* 0x0080040008047a2b */
/* 0x004e140000000004 */
/*01a0*/ F2I.U32.F64.TRUNC R5, R4 ; /* 0x0000000400057311 */
/* 0x001e24000030d000 */
/*01b0*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x001fe2000c101104 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdint.h>
#include <cuda.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName, int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we don't touch other types
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
uint8_t max_val;
fscanf(f, "%hhu", &max_val);
if (max_val > 255)
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we assume 1 byte per value
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(char * fileName, int numChannels, int width, int height, uint8_t * pixels)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
void compare2Pnms(char * fileName1, char * fileName2)
{
int numChannels1, width1, height1;
uint8_t * pixels1;
readPnm(fileName1, numChannels1, width1, height1, pixels1);
int numChannels2, width2, height2;
uint8_t * pixels2;
readPnm(fileName2, numChannels2, width2, height2, pixels2);
if (numChannels1 != numChannels2)
{
printf("'%s' is DIFFERENT from '%s' (num channels: %i vs %i)\n", fileName1, fileName2, numChannels1, numChannels2);
return;
}
if (width1 != width2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, width1, width2);
return;
}
if (height1 != height2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, height1, height2);
return;
}
float mae = 0;
for (int i = 0; i < width1 * height1 * numChannels1; i++)
{
mae += abs((int)pixels1[i]-(int)pixels2[i]);
}
mae /= (width1 * height1 * numChannels1);
printf("The average pixel difference between '%s' and '%s': %f\n", fileName1, fileName2, mae);
}
void convertRgb2GrayByHost(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int size = width * height;
for(int i = 0; i < size; i++){
outPixels[i] = 0.299 * inPixels[i*3] +
0.114 * inPixels[i*3 + 2] +
0.587 * inPixels[i*3 + 1];
}
}
__global__ void convertRgb2GrayByDevice(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int i_r = blockIdx.y * blockDim.y + threadIdx.y;
int i_c = blockIdx.x * blockDim.x + threadIdx.x;
if(i_c < width && i_r < height){
outPixels[i_r * width + i_c] = 0.299 * inPixels[(i_r * width + i_c)*3] +
0.114 * inPixels[(i_r * width + i_c)*3 + 2] +
0.587 * inPixels[(i_r * width + i_c)*3 + 1];
}
}
int main(int argc, char ** argv)
{
// -----READ INPUT DATA-----
if (argc < 5 || argc > 7)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
printf("Image size (width x height): %i x %i\n", width, height);
// -----PROCESS INPUT DATA-----
uint8_t * outPixels= (uint8_t *)malloc(width * height);
GpuTimer timer;
timer.Start();
if (strcmp(argv[4], "cpu") == 0){ // Use CPU
convertRgb2GrayByHost(inPixels, outPixels, width, height);
}
else // Use GPU
{
// TODO: Query and print GPU name and compute capability
cudaDeviceProp prop;
CHECK(cudaGetDeviceProperties(&prop, 0));
printf("GPU name: %s\n", prop.name);
printf("GPU compute capability: %d\n", prop.major);
// TODO: Allocate device memories
uint8_t *d_inPixels, *d_outPixels;
CHECK(cudaMalloc(&d_inPixels, width * height * numChannels));
CHECK(cudaMalloc(&d_outPixels, width * height));
// TODO: Copy data to device memories
CHECK(cudaMemcpy(d_inPixels, inPixels, width * height * numChannels, cudaMemcpyHostToDevice));
// TODO: Set block size (already done for you) and grid size,
// and invoke kernel function with these settings (remember to check kernel error)
dim3 blockSize(32, 32); // Default
if (argc == 7)
{
blockSize.x = atoi(argv[5]);
blockSize.y = atoi(argv[6]);
}
dim3 gridSize((width-1)/blockSize.x + 1, (height-1)/blockSize.y + 1);
printf("Block size: %d x %d\n", blockSize.x, blockSize.y);
printf("Grid size: %d x %d\n", gridSize.x, gridSize.y);
convertRgb2GrayByDevice<<<gridSize, blockSize>>>(d_inPixels, d_outPixels, width, height);
// TODO: Copy result from device memories
CHECK(cudaMemcpy(outPixels, d_outPixels, width * height, cudaMemcpyDeviceToHost));
// TODO: Free device memories
cudaFree(d_inPixels);
cudaFree(d_outPixels);
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time: %f ms\n", time);
// -----WRITE OUTPUT DATA TO FILE-----
writePnm(argv[2], 1, width, height, outPixels);
free(inPixels);
free(outPixels);
// -----CHECK CORRECTNESS-----
compare2Pnms(argv[2], argv[3]);
} | .file "tmpxft_001aa234_00000000-6_bt1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "Cannot read %s\n"
.LC2:
.string "%s"
.LC3:
.string "P2"
.LC4:
.string "P3"
.LC5:
.string "%i"
.LC6:
.string "%hhu"
.text
.globl _Z7readPnmPcRiS0_S0_RPh
.type _Z7readPnmPcRiS0_S0_RPh, @function
_Z7readPnmPcRiS0_S0_RPh:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 8(%rsp)
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %r14
movq %r8, %r15
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L13
movq %rax, %rbp
leaq 21(%rsp), %rbx
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
je .L9
movq %rbx, %rdi
leaq .LC4(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L14
movl $3, %eax
jmp .L5
.L13:
movq 8(%rsp), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L14:
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L9:
movl $1, %eax
.L5:
movl %eax, (%r12)
movq %r13, %rdx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r14, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 20(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 0(%r13), %edi
imull (%r14), %edi
imull (%r12), %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, (%r15)
movl 0(%r13), %eax
imull (%r14), %eax
imull (%r12), %eax
testl %eax, %eax
jle .L6
movl $0, %ebx
.L7:
movq %rbx, %rdx
addq (%r15), %rdx
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
movl 0(%r13), %eax
imull (%r14), %eax
imull (%r12), %eax
cmpl %ebx, %eax
jg .L7
.L6:
movq %rbp, %rdi
call fclose@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _Z7readPnmPcRiS0_S0_RPh, .-_Z7readPnmPcRiS0_S0_RPh
.section .rodata.str1.1
.LC7:
.string "w"
.LC8:
.string "Cannot write %s\n"
.LC9:
.string "P2\n"
.LC10:
.string "P3\n"
.LC11:
.string "%i\n%i\n255\n"
.LC12:
.string "%hhu\n"
.text
.globl _Z8writePnmPciiiPh
.type _Z8writePnmPciiiPh, @function
_Z8writePnmPciiiPh:
.LFB2067:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r15
movl %esi, %r13d
movl %edx, %ebx
movl %ecx, %r14d
movq %r8, %r12
leaq .LC7(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L25
movq %rax, %rbp
cmpl $1, %r13d
je .L26
cmpl $3, %r13d
jne .L20
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L19:
movl %r14d, %r8d
movl %ebx, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
imull %r14d, %ebx
imull %r13d, %ebx
movl %ebx, %r8d
testl %ebx, %ebx
jle .L21
movq %r12, %rbx
movslq %r8d, %r8
addq %r8, %r12
leaq .LC12(%rip), %r13
.L22:
movzbl (%rbx), %ecx
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L22
.L21:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq %r15, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L20:
movq %rax, %rdi
call fclose@PLT
movq %r15, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z8writePnmPciiiPh, .-_Z8writePnmPciiiPh
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC14:
.string "'%s' is DIFFERENT from '%s' (num channels: %i vs %i)\n"
.align 8
.LC15:
.string "'%s' is DIFFERENT from '%s' (width: %i vs %i)\n"
.align 8
.LC16:
.string "The average pixel difference between '%s' and '%s': %f\n"
.text
.globl _Z12compare2PnmsPcS_
.type _Z12compare2PnmsPcS_, @function
_Z12compare2PnmsPcS_:
.LFB2068:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rcx
leaq 4(%rsp), %rdx
movq %rsp, %rsi
leaq 24(%rsp), %r8
call _Z7readPnmPcRiS0_S0_RPh
leaq 20(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rsi
leaq 32(%rsp), %r8
movq %rbp, %rdi
call _Z7readPnmPcRiS0_S0_RPh
movl (%rsp), %r8d
movl 12(%rsp), %r9d
cmpl %r9d, %r8d
jne .L39
movl 4(%rsp), %eax
movl 16(%rsp), %r9d
cmpl %r9d, %eax
jne .L40
movl 8(%rsp), %edx
movl 20(%rsp), %r9d
cmpl %r9d, %edx
jne .L31
imull %edx, %eax
imull %eax, %r8d
pxor %xmm0, %xmm0
testl %r8d, %r8d
jle .L33
movq 24(%rsp), %r9
movq 32(%rsp), %rdi
movslq %r8d, %rsi
movl $0, %edx
pxor %xmm0, %xmm0
.L34:
movzbl (%r9,%rdx), %eax
movzbl (%rdi,%rdx), %ecx
subl %ecx, %eax
movl %eax, %ecx
negl %ecx
cmovns %ecx, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addss %xmm1, %xmm0
addq $1, %rdx
cmpq %rdx, %rsi
jne .L34
.L33:
pxor %xmm1, %xmm1
cvtsi2ssl %r8d, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rcx
movq %rbx, %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L27
.L39:
movq %rbp, %rcx
movq %rbx, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L27:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl %eax, %r8d
movq %rbp, %rcx
movq %rbx, %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.L31:
movl %edx, %r8d
movq %rbp, %rcx
movq %rbx, %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _Z12compare2PnmsPcS_, .-_Z12compare2PnmsPcS_
.globl _Z21convertRgb2GrayByHostPhS_ii
.type _Z21convertRgb2GrayByHostPhS_ii, @function
_Z21convertRgb2GrayByHostPhS_ii:
.LFB2069:
.cfi_startproc
endbr64
imull %ecx, %edx
testl %edx, %edx
jle .L42
movq %rsi, %rax
movslq %edx, %rdx
addq %rdx, %rsi
movsd .LC17(%rip), %xmm4
movsd .LC18(%rip), %xmm3
movsd .LC19(%rip), %xmm2
.L44:
movzbl (%rdi), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd %xmm4, %xmm0
movzbl 2(%rdi), %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
mulsd %xmm3, %xmm1
addsd %xmm1, %xmm0
movzbl 1(%rdi), %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
mulsd %xmm2, %xmm1
addsd %xmm1, %xmm0
cvttsd2sil %xmm0, %edx
movb %dl, (%rax)
addq $3, %rdi
addq $1, %rax
cmpq %rsi, %rax
jne .L44
.L42:
ret
.cfi_endproc
.LFE2069:
.size _Z21convertRgb2GrayByHostPhS_ii, .-_Z21convertRgb2GrayByHostPhS_ii
.globl _Z47__device_stub__Z23convertRgb2GrayByDevicePhS_iiPhS_ii
.type _Z47__device_stub__Z23convertRgb2GrayByDevicePhS_iiPhS_ii, @function
_Z47__device_stub__Z23convertRgb2GrayByDevicePhS_iiPhS_ii:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23convertRgb2GrayByDevicePhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z47__device_stub__Z23convertRgb2GrayByDevicePhS_iiPhS_ii, .-_Z47__device_stub__Z23convertRgb2GrayByDevicePhS_iiPhS_ii
.globl _Z23convertRgb2GrayByDevicePhS_ii
.type _Z23convertRgb2GrayByDevicePhS_ii, @function
_Z23convertRgb2GrayByDevicePhS_ii:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23convertRgb2GrayByDevicePhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z23convertRgb2GrayByDevicePhS_ii, .-_Z23convertRgb2GrayByDevicePhS_ii
.section .rodata.str1.8
.align 8
.LC20:
.string "The number of arguments is invalid\n"
.align 8
.LC21:
.string "Image size (width x height): %i x %i\n"
.section .rodata.str1.1
.LC22:
.string "cpu"
.section .rodata.str1.8
.align 8
.LC23:
.string "/home/ubuntu/Datasets/stackv2/train-structured/TruongNgocTai/TH_01/master/bt1.cu"
.section .rodata.str1.1
.LC24:
.string "Error: %s:%d, "
.LC25:
.string "code: %d, reason: %s\n"
.LC26:
.string "GPU name: %s\n"
.LC27:
.string "GPU compute capability: %d\n"
.LC28:
.string "Block size: %d x %d\n"
.LC29:
.string "Grid size: %d x %d\n"
.LC30:
.string "Processing time: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2070
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
leal -5(%rdi), %eax
cmpl $2, %eax
ja .L72
movl %edi, %ebp
movq %rsi, %rbx
leaq 12(%rsp), %rcx
leaq 8(%rsp), %rdx
leaq 4(%rsp), %rsi
movq 8(%rbx), %rdi
leaq 16(%rsp), %r8
.LEHB0:
call _Z7readPnmPcRiS0_S0_RPh
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %edi
imull 12(%rsp), %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, %r12
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
.LEHE0:
movl $0, %esi
movq 64(%rsp), %rdi
.LEHB1:
call cudaEventRecord@PLT
.LEHE1:
jmp .L73
.L72:
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
.LEHE2:
movl $1, %eax
jmp .L54
.L73:
movq 32(%rbx), %rdi
leaq .LC22(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L57
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call _Z21convertRgb2GrayByHostPhS_ii
.L58:
movl $0, %esi
movq 72(%rsp), %rdi
.LEHB3:
call cudaEventRecord@PLT
jmp .L74
.L57:
leaq 80(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L75
leaq 80(%rsp), %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L76
.L75:
movl $206, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r13d, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L76:
movl 440(%rsp), %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %r13d
movl 8(%rsp), %esi
imull 12(%rsp), %esi
imull %r13d, %esi
movslq %esi, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L77
movl 8(%rsp), %esi
imull 12(%rsp), %esi
movslq %esi, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
jmp .L78
.L77:
movl $213, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r14d, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
movl %eax, %r14d
testl %eax, %eax
jne .L79
movl 8(%rsp), %edx
imull 12(%rsp), %edx
imull %r13d, %edx
movslq %edx, %rdx
movl $1, %ecx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L80
.L79:
movl $214, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r14d, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L80:
movl %eax, %r13d
testl %eax, %eax
jne .L81
movl $1, 48(%rsp)
cmpl $7, %ebp
je .L82
movl $32, %r14d
movl $32, %r15d
.L63:
movl 12(%rsp), %eax
subl $1, %eax
movl $0, %edx
divl %r14d
leal 1(%rax), %ebp
movl 8(%rsp), %eax
subl $1, %eax
movl $0, %edx
divl %r15d
leal 1(%rax), %r13d
movl $1, 60(%rsp)
movl %r14d, %ecx
movl %r15d, %edx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L83
.L81:
movl $217, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r13d, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L82:
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r15d
movq 48(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
jmp .L63
.L83:
movl %ebp, %ecx
movl %r13d, %edx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 52(%rsp)
movl %ebp, 56(%rsp)
movl %r15d, 40(%rsp)
movl %r14d, 44(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L64
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z47__device_stub__Z23convertRgb2GrayByDevicePhS_iiPhS_ii
.L64:
movl 8(%rsp), %edx
imull 12(%rsp), %edx
movslq %edx, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L84
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L85
.L84:
movl $234, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L85:
movq 32(%rsp), %rdi
call cudaFree@PLT
jmp .L58
.L74:
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rbx), %rdi
movq %r12, %r8
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl $1, %esi
call _Z8writePnmPciiiPh
movq 16(%rsp), %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rbx), %rsi
movq 16(%rbx), %rdi
call _Z12compare2PnmsPcS_
.LEHE3:
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movl $0, %eax
.L54:
movq 1112(%rsp), %rdx
subq %fs:40, %rdx
jne .L86
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2070:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2070-.LLSDACSB2070
.LLSDACSB2070:
.uleb128 .LEHB0-.LFB2070
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2070
.uleb128 .LEHE1-.LEHB1
.uleb128 .L70-.LFB2070
.uleb128 0
.uleb128 .LEHB2-.LFB2070
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB2070
.uleb128 .LEHE3-.LEHB3
.uleb128 .L70-.LFB2070
.uleb128 0
.uleb128 .LEHB4-.LFB2070
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE2070:
.text
.size main, .-main
.section .rodata.str1.8
.align 8
.LC31:
.string "_Z23convertRgb2GrayByDevicePhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z23convertRgb2GrayByDevicePhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC17:
.long -446676599
.long 1070801616
.align 8
.LC18:
.long -1614907703
.long 1069362970
.align 8
.LC19:
.long 962072674
.long 1071827124
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdint.h>
#include <cuda.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName, int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we don't touch other types
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
uint8_t max_val;
fscanf(f, "%hhu", &max_val);
if (max_val > 255)
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we assume 1 byte per value
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(char * fileName, int numChannels, int width, int height, uint8_t * pixels)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
void compare2Pnms(char * fileName1, char * fileName2)
{
int numChannels1, width1, height1;
uint8_t * pixels1;
readPnm(fileName1, numChannels1, width1, height1, pixels1);
int numChannels2, width2, height2;
uint8_t * pixels2;
readPnm(fileName2, numChannels2, width2, height2, pixels2);
if (numChannels1 != numChannels2)
{
printf("'%s' is DIFFERENT from '%s' (num channels: %i vs %i)\n", fileName1, fileName2, numChannels1, numChannels2);
return;
}
if (width1 != width2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, width1, width2);
return;
}
if (height1 != height2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, height1, height2);
return;
}
float mae = 0;
for (int i = 0; i < width1 * height1 * numChannels1; i++)
{
mae += abs((int)pixels1[i]-(int)pixels2[i]);
}
mae /= (width1 * height1 * numChannels1);
printf("The average pixel difference between '%s' and '%s': %f\n", fileName1, fileName2, mae);
}
void convertRgb2GrayByHost(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int size = width * height;
for(int i = 0; i < size; i++){
outPixels[i] = 0.299 * inPixels[i*3] +
0.114 * inPixels[i*3 + 2] +
0.587 * inPixels[i*3 + 1];
}
}
__global__ void convertRgb2GrayByDevice(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int i_r = blockIdx.y * blockDim.y + threadIdx.y;
int i_c = blockIdx.x * blockDim.x + threadIdx.x;
if(i_c < width && i_r < height){
outPixels[i_r * width + i_c] = 0.299 * inPixels[(i_r * width + i_c)*3] +
0.114 * inPixels[(i_r * width + i_c)*3 + 2] +
0.587 * inPixels[(i_r * width + i_c)*3 + 1];
}
}
int main(int argc, char ** argv)
{
// -----READ INPUT DATA-----
if (argc < 5 || argc > 7)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
printf("Image size (width x height): %i x %i\n", width, height);
// -----PROCESS INPUT DATA-----
uint8_t * outPixels= (uint8_t *)malloc(width * height);
GpuTimer timer;
timer.Start();
if (strcmp(argv[4], "cpu") == 0){ // Use CPU
convertRgb2GrayByHost(inPixels, outPixels, width, height);
}
else // Use GPU
{
// TODO: Query and print GPU name and compute capability
cudaDeviceProp prop;
CHECK(cudaGetDeviceProperties(&prop, 0));
printf("GPU name: %s\n", prop.name);
printf("GPU compute capability: %d\n", prop.major);
// TODO: Allocate device memories
uint8_t *d_inPixels, *d_outPixels;
CHECK(cudaMalloc(&d_inPixels, width * height * numChannels));
CHECK(cudaMalloc(&d_outPixels, width * height));
// TODO: Copy data to device memories
CHECK(cudaMemcpy(d_inPixels, inPixels, width * height * numChannels, cudaMemcpyHostToDevice));
// TODO: Set block size (already done for you) and grid size,
// and invoke kernel function with these settings (remember to check kernel error)
dim3 blockSize(32, 32); // Default
if (argc == 7)
{
blockSize.x = atoi(argv[5]);
blockSize.y = atoi(argv[6]);
}
dim3 gridSize((width-1)/blockSize.x + 1, (height-1)/blockSize.y + 1);
printf("Block size: %d x %d\n", blockSize.x, blockSize.y);
printf("Grid size: %d x %d\n", gridSize.x, gridSize.y);
convertRgb2GrayByDevice<<<gridSize, blockSize>>>(d_inPixels, d_outPixels, width, height);
// TODO: Copy result from device memories
CHECK(cudaMemcpy(outPixels, d_outPixels, width * height, cudaMemcpyDeviceToHost));
// TODO: Free device memories
cudaFree(d_inPixels);
cudaFree(d_outPixels);
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time: %f ms\n", time);
// -----WRITE OUTPUT DATA TO FILE-----
writePnm(argv[2], 1, width, height, outPixels);
free(inPixels);
free(outPixels);
// -----CHECK CORRECTNESS-----
compare2Pnms(argv[2], argv[3]);
} | #include <stdio.h>
#include <stdint.h>
#include <hip/hip_runtime.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName, int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we don't touch other types
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
uint8_t max_val;
fscanf(f, "%hhu", &max_val);
if (max_val > 255)
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we assume 1 byte per value
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(char * fileName, int numChannels, int width, int height, uint8_t * pixels)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
void compare2Pnms(char * fileName1, char * fileName2)
{
int numChannels1, width1, height1;
uint8_t * pixels1;
readPnm(fileName1, numChannels1, width1, height1, pixels1);
int numChannels2, width2, height2;
uint8_t * pixels2;
readPnm(fileName2, numChannels2, width2, height2, pixels2);
if (numChannels1 != numChannels2)
{
printf("'%s' is DIFFERENT from '%s' (num channels: %i vs %i)\n", fileName1, fileName2, numChannels1, numChannels2);
return;
}
if (width1 != width2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, width1, width2);
return;
}
if (height1 != height2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, height1, height2);
return;
}
float mae = 0;
for (int i = 0; i < width1 * height1 * numChannels1; i++)
{
mae += abs((int)pixels1[i]-(int)pixels2[i]);
}
mae /= (width1 * height1 * numChannels1);
printf("The average pixel difference between '%s' and '%s': %f\n", fileName1, fileName2, mae);
}
void convertRgb2GrayByHost(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int size = width * height;
for(int i = 0; i < size; i++){
outPixels[i] = 0.299 * inPixels[i*3] +
0.114 * inPixels[i*3 + 2] +
0.587 * inPixels[i*3 + 1];
}
}
__global__ void convertRgb2GrayByDevice(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int i_r = blockIdx.y * blockDim.y + threadIdx.y;
int i_c = blockIdx.x * blockDim.x + threadIdx.x;
if(i_c < width && i_r < height){
outPixels[i_r * width + i_c] = 0.299 * inPixels[(i_r * width + i_c)*3] +
0.114 * inPixels[(i_r * width + i_c)*3 + 2] +
0.587 * inPixels[(i_r * width + i_c)*3 + 1];
}
}
int main(int argc, char ** argv)
{
// -----READ INPUT DATA-----
if (argc < 5 || argc > 7)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
printf("Image size (width x height): %i x %i\n", width, height);
// -----PROCESS INPUT DATA-----
uint8_t * outPixels= (uint8_t *)malloc(width * height);
GpuTimer timer;
timer.Start();
if (strcmp(argv[4], "cpu") == 0){ // Use CPU
convertRgb2GrayByHost(inPixels, outPixels, width, height);
}
else // Use GPU
{
// TODO: Query and print GPU name and compute capability
hipDeviceProp_t prop;
CHECK(hipGetDeviceProperties(&prop, 0));
printf("GPU name: %s\n", prop.name);
printf("GPU compute capability: %d\n", prop.major);
// TODO: Allocate device memories
uint8_t *d_inPixels, *d_outPixels;
CHECK(hipMalloc(&d_inPixels, width * height * numChannels));
CHECK(hipMalloc(&d_outPixels, width * height));
// TODO: Copy data to device memories
CHECK(hipMemcpy(d_inPixels, inPixels, width * height * numChannels, hipMemcpyHostToDevice));
// TODO: Set block size (already done for you) and grid size,
// and invoke kernel function with these settings (remember to check kernel error)
dim3 blockSize(32, 32); // Default
if (argc == 7)
{
blockSize.x = atoi(argv[5]);
blockSize.y = atoi(argv[6]);
}
dim3 gridSize((width-1)/blockSize.x + 1, (height-1)/blockSize.y + 1);
printf("Block size: %d x %d\n", blockSize.x, blockSize.y);
printf("Grid size: %d x %d\n", gridSize.x, gridSize.y);
convertRgb2GrayByDevice<<<gridSize, blockSize>>>(d_inPixels, d_outPixels, width, height);
// TODO: Copy result from device memories
CHECK(hipMemcpy(outPixels, d_outPixels, width * height, hipMemcpyDeviceToHost));
// TODO: Free device memories
hipFree(d_inPixels);
hipFree(d_outPixels);
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time: %f ms\n", time);
// -----WRITE OUTPUT DATA TO FILE-----
writePnm(argv[2], 1, width, height, outPixels);
free(inPixels);
free(outPixels);
// -----CHECK CORRECTNESS-----
compare2Pnms(argv[2], argv[3]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdint.h>
#include <hip/hip_runtime.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName, int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we don't touch other types
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
uint8_t max_val;
fscanf(f, "%hhu", &max_val);
if (max_val > 255)
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we assume 1 byte per value
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(char * fileName, int numChannels, int width, int height, uint8_t * pixels)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
void compare2Pnms(char * fileName1, char * fileName2)
{
int numChannels1, width1, height1;
uint8_t * pixels1;
readPnm(fileName1, numChannels1, width1, height1, pixels1);
int numChannels2, width2, height2;
uint8_t * pixels2;
readPnm(fileName2, numChannels2, width2, height2, pixels2);
if (numChannels1 != numChannels2)
{
printf("'%s' is DIFFERENT from '%s' (num channels: %i vs %i)\n", fileName1, fileName2, numChannels1, numChannels2);
return;
}
if (width1 != width2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, width1, width2);
return;
}
if (height1 != height2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, height1, height2);
return;
}
float mae = 0;
for (int i = 0; i < width1 * height1 * numChannels1; i++)
{
mae += abs((int)pixels1[i]-(int)pixels2[i]);
}
mae /= (width1 * height1 * numChannels1);
printf("The average pixel difference between '%s' and '%s': %f\n", fileName1, fileName2, mae);
}
void convertRgb2GrayByHost(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int size = width * height;
for(int i = 0; i < size; i++){
outPixels[i] = 0.299 * inPixels[i*3] +
0.114 * inPixels[i*3 + 2] +
0.587 * inPixels[i*3 + 1];
}
}
__global__ void convertRgb2GrayByDevice(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int i_r = blockIdx.y * blockDim.y + threadIdx.y;
int i_c = blockIdx.x * blockDim.x + threadIdx.x;
if(i_c < width && i_r < height){
outPixels[i_r * width + i_c] = 0.299 * inPixels[(i_r * width + i_c)*3] +
0.114 * inPixels[(i_r * width + i_c)*3 + 2] +
0.587 * inPixels[(i_r * width + i_c)*3 + 1];
}
}
int main(int argc, char ** argv)
{
// -----READ INPUT DATA-----
if (argc < 5 || argc > 7)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
printf("Image size (width x height): %i x %i\n", width, height);
// -----PROCESS INPUT DATA-----
uint8_t * outPixels= (uint8_t *)malloc(width * height);
GpuTimer timer;
timer.Start();
if (strcmp(argv[4], "cpu") == 0){ // Use CPU
convertRgb2GrayByHost(inPixels, outPixels, width, height);
}
else // Use GPU
{
// TODO: Query and print GPU name and compute capability
hipDeviceProp_t prop;
CHECK(hipGetDeviceProperties(&prop, 0));
printf("GPU name: %s\n", prop.name);
printf("GPU compute capability: %d\n", prop.major);
// TODO: Allocate device memories
uint8_t *d_inPixels, *d_outPixels;
CHECK(hipMalloc(&d_inPixels, width * height * numChannels));
CHECK(hipMalloc(&d_outPixels, width * height));
// TODO: Copy data to device memories
CHECK(hipMemcpy(d_inPixels, inPixels, width * height * numChannels, hipMemcpyHostToDevice));
// TODO: Set block size (already done for you) and grid size,
// and invoke kernel function with these settings (remember to check kernel error)
dim3 blockSize(32, 32); // Default
if (argc == 7)
{
blockSize.x = atoi(argv[5]);
blockSize.y = atoi(argv[6]);
}
dim3 gridSize((width-1)/blockSize.x + 1, (height-1)/blockSize.y + 1);
printf("Block size: %d x %d\n", blockSize.x, blockSize.y);
printf("Grid size: %d x %d\n", gridSize.x, gridSize.y);
convertRgb2GrayByDevice<<<gridSize, blockSize>>>(d_inPixels, d_outPixels, width, height);
// TODO: Copy result from device memories
CHECK(hipMemcpy(outPixels, d_outPixels, width * height, hipMemcpyDeviceToHost));
// TODO: Free device memories
hipFree(d_inPixels);
hipFree(d_outPixels);
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time: %f ms\n", time);
// -----WRITE OUTPUT DATA TO FILE-----
writePnm(argv[2], 1, width, height, outPixels);
free(inPixels);
free(outPixels);
// -----CHECK CORRECTNESS-----
compare2Pnms(argv[2], argv[3]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23convertRgb2GrayByDevicePhS_ii
.globl _Z23convertRgb2GrayByDevicePhS_ii
.p2align 8
.type _Z23convertRgb2GrayByDevicePhS_ii,@function
_Z23convertRgb2GrayByDevicePhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3fbd2f1a
s_mov_b32 s0, 0x9fbe76c9
s_clause 0x2
global_load_u8 v3, v[0:1], off offset:2
global_load_u8 v4, v[0:1], off
global_load_u8 v5, v[0:1], off offset:1
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[0:1], v3
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[3:4], v4
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[0:1], v[0:1], s[0:1]
s_mov_b32 s1, 0x3fd322d0
s_mov_b32 s0, 0xe5604189
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[0:1], v[3:4], s[0:1], v[0:1]
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[3:4], v5
s_mov_b32 s1, 0x3fe2c8b4
s_mov_b32 s0, 0x39581062
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[0:1], v[3:4], s[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v3, v[0:1]
v_ashrrev_i32_e32 v1, 31, v2
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23convertRgb2GrayByDevicePhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23convertRgb2GrayByDevicePhS_ii, .Lfunc_end0-_Z23convertRgb2GrayByDevicePhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23convertRgb2GrayByDevicePhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23convertRgb2GrayByDevicePhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdint.h>
#include <hip/hip_runtime.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void readPnm(char * fileName, int &numChannels, int &width, int &height, uint8_t * &pixels)
{
FILE * f = fopen(fileName, "r");
if (f == NULL)
{
printf("Cannot read %s\n", fileName);
exit(EXIT_FAILURE);
}
char type[3];
fscanf(f, "%s", type);
if (strcmp(type, "P2") == 0)
numChannels = 1;
else if (strcmp(type, "P3") == 0)
numChannels = 3;
else
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we don't touch other types
exit(EXIT_FAILURE);
}
fscanf(f, "%i", &width);
fscanf(f, "%i", &height);
uint8_t max_val;
fscanf(f, "%hhu", &max_val);
if (max_val > 255)
{
fclose(f);
printf("Cannot read %s\n", fileName); // In this exercise, we assume 1 byte per value
exit(EXIT_FAILURE);
}
pixels = (uint8_t *)malloc(width * height * numChannels);
for (int i = 0; i < width * height * numChannels; i++)
fscanf(f, "%hhu", &pixels[i]);
fclose(f);
}
void writePnm(char * fileName, int numChannels, int width, int height, uint8_t * pixels)
{
FILE * f = fopen(fileName, "w");
if (f == NULL)
{
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
if (numChannels == 1)
fprintf(f, "P2\n");
else if (numChannels == 3)
fprintf(f, "P3\n");
else
{
fclose(f);
printf("Cannot write %s\n", fileName);
exit(EXIT_FAILURE);
}
fprintf(f, "%i\n%i\n255\n", width, height);
for (int i = 0; i < width * height * numChannels; i++)
fprintf(f, "%hhu\n", pixels[i]);
fclose(f);
}
void compare2Pnms(char * fileName1, char * fileName2)
{
int numChannels1, width1, height1;
uint8_t * pixels1;
readPnm(fileName1, numChannels1, width1, height1, pixels1);
int numChannels2, width2, height2;
uint8_t * pixels2;
readPnm(fileName2, numChannels2, width2, height2, pixels2);
if (numChannels1 != numChannels2)
{
printf("'%s' is DIFFERENT from '%s' (num channels: %i vs %i)\n", fileName1, fileName2, numChannels1, numChannels2);
return;
}
if (width1 != width2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, width1, width2);
return;
}
if (height1 != height2)
{
printf("'%s' is DIFFERENT from '%s' (width: %i vs %i)\n", fileName1, fileName2, height1, height2);
return;
}
float mae = 0;
for (int i = 0; i < width1 * height1 * numChannels1; i++)
{
mae += abs((int)pixels1[i]-(int)pixels2[i]);
}
mae /= (width1 * height1 * numChannels1);
printf("The average pixel difference between '%s' and '%s': %f\n", fileName1, fileName2, mae);
}
void convertRgb2GrayByHost(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int size = width * height;
for(int i = 0; i < size; i++){
outPixels[i] = 0.299 * inPixels[i*3] +
0.114 * inPixels[i*3 + 2] +
0.587 * inPixels[i*3 + 1];
}
}
__global__ void convertRgb2GrayByDevice(uint8_t * inPixels, uint8_t * outPixels, int width, int height)
{
// TODO
int i_r = blockIdx.y * blockDim.y + threadIdx.y;
int i_c = blockIdx.x * blockDim.x + threadIdx.x;
if(i_c < width && i_r < height){
outPixels[i_r * width + i_c] = 0.299 * inPixels[(i_r * width + i_c)*3] +
0.114 * inPixels[(i_r * width + i_c)*3 + 2] +
0.587 * inPixels[(i_r * width + i_c)*3 + 1];
}
}
int main(int argc, char ** argv)
{
// -----READ INPUT DATA-----
if (argc < 5 || argc > 7)
{
printf("The number of arguments is invalid\n");
return EXIT_FAILURE;
}
int numChannels, width, height;
uint8_t * inPixels;
readPnm(argv[1], numChannels, width, height, inPixels);
printf("Image size (width x height): %i x %i\n", width, height);
// -----PROCESS INPUT DATA-----
uint8_t * outPixels= (uint8_t *)malloc(width * height);
GpuTimer timer;
timer.Start();
if (strcmp(argv[4], "cpu") == 0){ // Use CPU
convertRgb2GrayByHost(inPixels, outPixels, width, height);
}
else // Use GPU
{
// TODO: Query and print GPU name and compute capability
hipDeviceProp_t prop;
CHECK(hipGetDeviceProperties(&prop, 0));
printf("GPU name: %s\n", prop.name);
printf("GPU compute capability: %d\n", prop.major);
// TODO: Allocate device memories
uint8_t *d_inPixels, *d_outPixels;
CHECK(hipMalloc(&d_inPixels, width * height * numChannels));
CHECK(hipMalloc(&d_outPixels, width * height));
// TODO: Copy data to device memories
CHECK(hipMemcpy(d_inPixels, inPixels, width * height * numChannels, hipMemcpyHostToDevice));
// TODO: Set block size (already done for you) and grid size,
// and invoke kernel function with these settings (remember to check kernel error)
dim3 blockSize(32, 32); // Default
if (argc == 7)
{
blockSize.x = atoi(argv[5]);
blockSize.y = atoi(argv[6]);
}
dim3 gridSize((width-1)/blockSize.x + 1, (height-1)/blockSize.y + 1);
printf("Block size: %d x %d\n", blockSize.x, blockSize.y);
printf("Grid size: %d x %d\n", gridSize.x, gridSize.y);
convertRgb2GrayByDevice<<<gridSize, blockSize>>>(d_inPixels, d_outPixels, width, height);
// TODO: Copy result from device memories
CHECK(hipMemcpy(outPixels, d_outPixels, width * height, hipMemcpyDeviceToHost));
// TODO: Free device memories
hipFree(d_inPixels);
hipFree(d_outPixels);
}
timer.Stop();
float time = timer.Elapsed();
printf("Processing time: %f ms\n", time);
// -----WRITE OUTPUT DATA TO FILE-----
writePnm(argv[2], 1, width, height, outPixels);
free(inPixels);
free(outPixels);
// -----CHECK CORRECTNESS-----
compare2Pnms(argv[2], argv[3]);
} | .text
.file "bt1.hip"
.globl _Z7readPnmPcRiS0_S0_RPh # -- Begin function _Z7readPnmPcRiS0_S0_RPh
.p2align 4, 0x90
.type _Z7readPnmPcRiS0_S0_RPh,@function
_Z7readPnmPcRiS0_S0_RPh: # @_Z7readPnmPcRiS0_S0_RPh
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbp
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB0_9
# %bb.1:
movq %rax, %r13
leaq 4(%rsp), %rdx
movl $.L.str.2, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movzwl 4(%rsp), %eax
xorl $12880, %eax # imm = 0x3250
movzbl 6(%rsp), %ecx
orw %ax, %cx
je .LBB0_2
# %bb.7:
movzwl 4(%rsp), %ecx
xorl $13136, %ecx # imm = 0x3350
movzbl 6(%rsp), %edx
movl $3, %eax
orw %cx, %dx
je .LBB0_3
# %bb.8:
movq %r13, %rdi
callq fclose
.LBB0_9:
movl $.L.str.1, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB0_2:
movl $1, %eax
.LBB0_3:
movl %eax, (%r12)
movl $.L.str.5, %esi
movq %r13, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.5, %esi
movq %r13, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
leaq 7(%rsp), %rdx
movl $.L.str.6, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq (%r15), %rax
movslq (%r14), %rcx
imulq %rax, %rcx
movslq (%r12), %rdi
imulq %rcx, %rdi
callq malloc
movq %rax, (%rbx)
movl (%r14), %eax
imull (%r15), %eax
imull (%r12), %eax
testl %eax, %eax
jle .LBB0_6
# %bb.4: # %.lr.ph.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx), %rdx
addq %rbp, %rdx
movl $.L.str.6, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq (%r15), %rax
movslq (%r14), %rcx
imulq %rax, %rcx
movslq (%r12), %rax
imulq %rcx, %rax
cmpq %rax, %rbp
jl .LBB0_5
.LBB0_6: # %._crit_edge
movq %r13, %rdi
callq fclose
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7readPnmPcRiS0_S0_RPh, .Lfunc_end0-_Z7readPnmPcRiS0_S0_RPh
.cfi_endproc
# -- End function
.globl _Z8writePnmPciiiPh # -- Begin function _Z8writePnmPciiiPh
.p2align 4, 0x90
.type _Z8writePnmPciiiPh,@function
_Z8writePnmPciiiPh: # @_Z8writePnmPciiiPh
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movl %ecx, %r15d
movl %edx, %r12d
movl %esi, %ebp
movq %rdi, %r13
movl $.L.str.7, %esi
callq fopen
testq %rax, %rax
je .LBB1_9
# %bb.1:
movq %rax, %r14
movl $.L.str.9, %edi
cmpl $1, %ebp
je .LBB1_4
# %bb.2:
cmpl $3, %ebp
jne .LBB1_8
# %bb.3:
movl $.L.str.10, %edi
.LBB1_4:
movl $3, %esi
movl $1, %edx
movq %r14, %rcx
callq fwrite@PLT
movl $.L.str.11, %esi
movq %r14, %rdi
movl %r12d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq fprintf
imull %r12d, %ebp
imull %r15d, %ebp
testl %ebp, %ebp
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%r12), %edx
movl $.L.str.12, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %r12
cmpq %r12, %r15
jne .LBB1_6
.LBB1_7: # %._crit_edge
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB1_8:
.cfi_def_cfa_offset 64
movq %r14, %rdi
callq fclose
.LBB1_9:
movl $.L.str.8, %edi
movq %r13, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z8writePnmPciiiPh, .Lfunc_end1-_Z8writePnmPciiiPh
.cfi_endproc
# -- End function
.globl _Z12compare2PnmsPcS_ # -- Begin function _Z12compare2PnmsPcS_
.p2align 4, 0x90
.type _Z12compare2PnmsPcS_,@function
_Z12compare2PnmsPcS_: # @_Z12compare2PnmsPcS_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 20(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rcx
leaq 32(%rsp), %r8
callq _Z7readPnmPcRiS0_S0_RPh
leaq 8(%rsp), %rsi
leaq 4(%rsp), %rdx
movq %rsp, %rcx
leaq 24(%rsp), %r8
movq %rbx, %rdi
callq _Z7readPnmPcRiS0_S0_RPh
movl 20(%rsp), %eax
movl 8(%rsp), %r8d
cmpl %r8d, %eax
jne .LBB2_1
# %bb.2:
movl 16(%rsp), %ecx
movl 4(%rsp), %r8d
cmpl %r8d, %ecx
jne .LBB2_3
# %bb.5:
movl 12(%rsp), %r9d
movl (%rsp), %r8d
cmpl %r8d, %r9d
jne .LBB2_12
# %bb.6: # %.preheader
imull %eax, %ecx
imull %r9d, %ecx
testl %ecx, %ecx
jle .LBB2_7
# %bb.10: # %.lr.ph
movq 32(%rsp), %rax
movq 24(%rsp), %rdx
movl %ecx, %esi
xorps %xmm0, %xmm0
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movzbl (%rax,%rdi), %r8d
movzbl (%rdx,%rdi), %r9d
subl %r9d, %r8d
movl %r8d, %r9d
negl %r9d
cmovsl %r8d, %r9d
movzbl %r9b, %r8d
xorps %xmm1, %xmm1
cvtsi2ss %r8d, %xmm1
addss %xmm1, %xmm0
incq %rdi
cmpq %rdi, %rsi
jne .LBB2_11
jmp .LBB2_8
.LBB2_1:
movl $.L.str.13, %edi
movq %r14, %rsi
movq %rbx, %rdx
movl %eax, %ecx
jmp .LBB2_4
.LBB2_3:
movl $.L.str.14, %edi
movq %r14, %rsi
movq %rbx, %rdx
jmp .LBB2_4
.LBB2_12:
movl $.L.str.14, %edi
movq %r14, %rsi
movq %rbx, %rdx
movl %r9d, %ecx
.LBB2_4:
xorl %eax, %eax
callq printf
.LBB2_9:
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 64
xorps %xmm0, %xmm0
.LBB2_8: # %._crit_edge
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movq %r14, %rsi
movq %rbx, %rdx
movb $1, %al
callq printf
jmp .LBB2_9
.Lfunc_end2:
.size _Z12compare2PnmsPcS_, .Lfunc_end2-_Z12compare2PnmsPcS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z21convertRgb2GrayByHostPhS_ii
.LCPI3_0:
.quad 0x3fd322d0e5604189 # double 0.29899999999999999
.LCPI3_1:
.quad 0x3fbd2f1a9fbe76c9 # double 0.114
.LCPI3_2:
.quad 0x3fe2c8b439581062 # double 0.58699999999999997
.text
.globl _Z21convertRgb2GrayByHostPhS_ii
.p2align 4, 0x90
.type _Z21convertRgb2GrayByHostPhS_ii,@function
_Z21convertRgb2GrayByHostPhS_ii: # @_Z21convertRgb2GrayByHostPhS_ii
.cfi_startproc
# %bb.0:
imull %ecx, %edx
testl %edx, %edx
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
addq $2, %rdi
xorl %ecx, %ecx
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI3_2(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl -2(%rdi), %edx
xorps %xmm3, %xmm3
cvtsi2sd %edx, %xmm3
mulsd %xmm0, %xmm3
movzbl (%rdi), %edx
xorps %xmm4, %xmm4
cvtsi2sd %edx, %xmm4
mulsd %xmm1, %xmm4
addsd %xmm3, %xmm4
movzbl -1(%rdi), %edx
xorps %xmm3, %xmm3
cvtsi2sd %edx, %xmm3
mulsd %xmm2, %xmm3
addsd %xmm4, %xmm3
cvttsd2si %xmm3, %edx
movb %dl, (%rsi,%rcx)
incq %rcx
addq $3, %rdi
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z21convertRgb2GrayByHostPhS_ii, .Lfunc_end3-_Z21convertRgb2GrayByHostPhS_ii
.cfi_endproc
# -- End function
.globl _Z38__device_stub__convertRgb2GrayByDevicePhS_ii # -- Begin function _Z38__device_stub__convertRgb2GrayByDevicePhS_ii
.p2align 4, 0x90
.type _Z38__device_stub__convertRgb2GrayByDevicePhS_ii,@function
_Z38__device_stub__convertRgb2GrayByDevicePhS_ii: # @_Z38__device_stub__convertRgb2GrayByDevicePhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23convertRgb2GrayByDevicePhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z38__device_stub__convertRgb2GrayByDevicePhS_ii, .Lfunc_end4-_Z38__device_stub__convertRgb2GrayByDevicePhS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x3fd322d0e5604189 # double 0.29899999999999999
.LCPI5_1:
.quad 0x3fbd2f1a9fbe76c9 # double 0.114
.LCPI5_2:
.quad 0x3fe2c8b439581062 # double 0.58699999999999997
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 1696
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %r15d
leal -8(%r15), %eax
cmpl $-4, %eax
ja .LBB5_2
# %bb.1:
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
jmp .LBB5_50
.LBB5_2:
movq %rsi, %rbx
movq 8(%rsi), %rdi
.cfi_escape 0x2e, 0x00
leaq 52(%rsp), %rsi
leaq 4(%rsp), %rdx
movq %rsp, %rcx
leaq 40(%rsp), %r8
callq _Z7readPnmPcRiS0_S0_RPh
movl 4(%rsp), %esi
movl (%rsp), %edx
.cfi_escape 0x2e, 0x00
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movslq 4(%rsp), %rax
movslq (%rsp), %rdi
imulq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r14
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipEventCreate
movq 8(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp1:
# %bb.3: # %_ZN8GpuTimer5StartEv.exit
movq 32(%rbx), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.18, %esi
callq strcmp
testl %eax, %eax
je .LBB5_4
# %bb.8:
.Ltmp2:
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
.Ltmp3:
# %bb.9:
testl %eax, %eax
jne .LBB5_10
# %bb.14:
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rsi
movl $.L.str.22, %edi
xorl %eax, %eax
callq printf
movl 528(%rsp), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movl (%rsp), %eax
imull 4(%rsp), %eax
movl 52(%rsp), %ebp
imull %ebp, %eax
movslq %eax, %rsi
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq hipMalloc
.Ltmp8:
# %bb.15: # %_ZL9hipMallocIhE10hipError_tPPT_m.exit
testl %eax, %eax
jne .LBB5_16
# %bb.19:
movslq 4(%rsp), %rax
movslq (%rsp), %rsi
imulq %rax, %rsi
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipMalloc
.Ltmp13:
# %bb.20: # %_ZL9hipMallocIhE10hipError_tPPT_m.exit62
testl %eax, %eax
jne .LBB5_21
# %bb.24:
movq 32(%rsp), %rdi
imull 4(%rsp), %ebp
movq 40(%rsp), %rsi
imull (%rsp), %ebp
movslq %ebp, %rdx
.Ltmp17:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp18:
# %bb.25:
testl %eax, %eax
jne .LBB5_26
# %bb.29:
cmpl $7, %r15d
jne .LBB5_30
# %bb.31:
movq 40(%rbx), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %r12d
movq 48(%rbx), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
shlq $32, %r15
orq %r12, %r15
jmp .LBB5_32
.LBB5_4:
movl (%rsp), %ecx
imull 4(%rsp), %ecx
testl %ecx, %ecx
jle .LBB5_43
# %bb.5: # %.lr.ph.preheader.i
movq 40(%rsp), %rax
movl %ecx, %ecx
addq $2, %rax
xorl %edx, %edx
movsd .LCPI5_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI5_2(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB5_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movzbl -2(%rax), %esi
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
mulsd %xmm0, %xmm3
movzbl (%rax), %esi
xorps %xmm4, %xmm4
cvtsi2sd %esi, %xmm4
mulsd %xmm1, %xmm4
addsd %xmm3, %xmm4
movzbl -1(%rax), %esi
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
mulsd %xmm2, %xmm3
addsd %xmm4, %xmm3
cvttsd2si %xmm3, %esi
movb %sil, (%r14,%rdx)
incq %rdx
addq $3, %rax
cmpq %rdx, %rcx
jne .LBB5_6
jmp .LBB5_43
.LBB5_30:
movabsq $137438953504, %r15 # imm = 0x2000000020
.LBB5_32:
movl 4(%rsp), %eax
decl %eax
xorl %edx, %edx
divl %r15d
# kill: def $eax killed $eax def $rax
leal 1(%rax), %r12d
movl (%rsp), %eax
decl %eax
movq %r15, %rcx
shrq $32, %rcx
xorl %edx, %edx
divl %ecx
# kill: def $eax killed $eax def $rax
leal 1(%rax), %r13d
movq %r13, %rbp
shlq $32, %rbp
orq %r12, %rbp
.cfi_escape 0x2e, 0x00
movl $.L.str.24, %edi
movl %r15d, %esi
movl %ecx, %edx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.25, %edi
movl %r12d, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp23:
# %bb.33:
testl %eax, %eax
jne .LBB5_36
# %bb.34:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movl 4(%rsp), %edx
movl (%rsp), %esi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %edx, 60(%rsp)
movl %esi, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp25:
# %bb.35: # %.noexc
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp26:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z23convertRgb2GrayByDevicePhS_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp27:
.LBB5_36:
movq 24(%rsp), %rsi
movslq 4(%rsp), %rax
movslq (%rsp), %rdx
imulq %rax, %rdx
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.37:
testl %eax, %eax
jne .LBB5_38
# %bb.41:
movq 32(%rsp), %rdi
.Ltmp33:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp34:
# %bb.42:
movq 24(%rsp), %rdi
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp36:
.LBB5_43: # %_Z21convertRgb2GrayByHostPhS_ii.exit
movq 16(%rsp), %rdi
.Ltmp38:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp39:
# %bb.44: # %_ZN8GpuTimer4StopEv.exit
movq 16(%rsp), %rdi
.Ltmp41:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp42:
# %bb.45: # %.noexc65
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp43:
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp44:
# %bb.46: # %_ZN8GpuTimer7ElapsedEv.exit
movss 168(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.26, %edi
movb $1, %al
callq printf
movq 16(%rbx), %rdi
movl 4(%rsp), %edx
movl (%rsp), %ecx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movq %r14, %r8
callq _Z8writePnmPciiiPh
movq 40(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq free
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
movq 16(%rbx), %rdi
movq 24(%rbx), %rsi
.Ltmp45:
.cfi_escape 0x2e, 0x00
callq _Z12compare2PnmsPcS_
.Ltmp46:
# %bb.47:
movq 8(%rsp), %rdi
.Ltmp53:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp54:
# %bb.48:
movq 16(%rsp), %rdi
.Ltmp55:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp56:
# %bb.49: # %_ZN8GpuTimerD2Ev.exit
xorl %eax, %eax
.LBB5_50:
addq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_10:
.cfi_def_cfa_offset 1696
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.19, %esi
movl $.L.str.20, %edx
movl $206, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp4:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp5:
# %bb.11:
.cfi_escape 0x2e, 0x00
jmp .LBB5_12
.LBB5_16:
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.19, %esi
movl $.L.str.20, %edx
movl $213, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp10:
# %bb.17:
.cfi_escape 0x2e, 0x00
jmp .LBB5_12
.LBB5_21:
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.19, %esi
movl $.L.str.20, %edx
movl $214, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp15:
# %bb.22:
.cfi_escape 0x2e, 0x00
jmp .LBB5_12
.LBB5_26:
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.19, %esi
movl $.L.str.20, %edx
movl $217, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp19:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp20:
# %bb.27:
.cfi_escape 0x2e, 0x00
jmp .LBB5_12
.LBB5_38:
movq stderr(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $.L.str.19, %esi
movl $.L.str.20, %edx
movl $234, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp31:
# %bb.39:
.cfi_escape 0x2e, 0x00
.LBB5_12:
movl $.L.str.21, %esi
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq exit
.LBB5_56:
.Ltmp57:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB5_55:
.Ltmp37:
jmp .LBB5_52
.LBB5_7:
.Ltmp40:
jmp .LBB5_52
.LBB5_51:
.Ltmp47:
jmp .LBB5_52
.LBB5_40:
.Ltmp32:
jmp .LBB5_52
.LBB5_28:
.Ltmp21:
jmp .LBB5_52
.LBB5_23:
.Ltmp16:
jmp .LBB5_52
.LBB5_18:
.Ltmp11:
jmp .LBB5_52
.LBB5_13:
.Ltmp6:
.LBB5_52:
movq %rax, %rbx
movq 8(%rsp), %rdi
.Ltmp48:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp49:
# %bb.53:
movq 16(%rsp), %rdi
.Ltmp50:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp51:
# %bb.54: # %_ZN8GpuTimerD2Ev.exit67
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB5_57:
.Ltmp52:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table5:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp8-.Ltmp7 # Call between .Ltmp7 and .Ltmp8
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp27-.Ltmp22 # Call between .Ltmp22 and .Ltmp27
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp36-.Ltmp33 # Call between .Ltmp33 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp46-.Ltmp41 # Call between .Ltmp41 and .Ltmp46
.uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp53-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp56-.Ltmp53 # Call between .Ltmp53 and .Ltmp56
.uleb128 .Ltmp57-.Lfunc_begin0 # jumps to .Ltmp57
.byte 1 # On action: 1
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp48-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp51-.Ltmp48 # Call between .Ltmp48 and .Ltmp51
.uleb128 .Ltmp52-.Lfunc_begin0 # jumps to .Ltmp52
.byte 1 # On action: 1
.uleb128 .Ltmp51-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Lfunc_end5-.Ltmp51 # Call between .Ltmp51 and .Lfunc_end5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end6:
.size __clang_call_terminate, .Lfunc_end6-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23convertRgb2GrayByDevicePhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cannot read %s\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "P2"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "P3"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%i"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%hhu"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "w"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Cannot write %s\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "P2\n"
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "P3\n"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%i\n%i\n255\n"
.size .L.str.11, 11
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%hhu\n"
.size .L.str.12, 6
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "'%s' is DIFFERENT from '%s' (num channels: %i vs %i)\n"
.size .L.str.13, 54
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "'%s' is DIFFERENT from '%s' (width: %i vs %i)\n"
.size .L.str.14, 47
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "The average pixel difference between '%s' and '%s': %f\n"
.size .L.str.15, 56
.type _Z23convertRgb2GrayByDevicePhS_ii,@object # @_Z23convertRgb2GrayByDevicePhS_ii
.section .rodata,"a",@progbits
.globl _Z23convertRgb2GrayByDevicePhS_ii
.p2align 3, 0x0
_Z23convertRgb2GrayByDevicePhS_ii:
.quad _Z38__device_stub__convertRgb2GrayByDevicePhS_ii
.size _Z23convertRgb2GrayByDevicePhS_ii, 8
.type .L.str.17,@object # @.str.17
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.17:
.asciz "Image size (width x height): %i x %i\n"
.size .L.str.17, 38
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "cpu"
.size .L.str.18, 4
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Error: %s:%d, "
.size .L.str.19, 15
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/TruongNgocTai/TH_01/master/bt1.hip"
.size .L.str.20, 92
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "code: %d, reason: %s\n"
.size .L.str.21, 22
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "GPU name: %s\n"
.size .L.str.22, 14
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "GPU compute capability: %d\n"
.size .L.str.23, 28
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Block size: %d x %d\n"
.size .L.str.24, 21
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Grid size: %d x %d\n"
.size .L.str.25, 20
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "Processing time: %f ms\n"
.size .L.str.26, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23convertRgb2GrayByDevicePhS_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The number of arguments is invalid"
.size .Lstr, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__convertRgb2GrayByDevicePhS_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z23convertRgb2GrayByDevicePhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23convertRgb2GrayByDevicePhS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x170], R3 ; /* 0x00005c0000007a24 */
/* 0x000fe200078e0203 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R3, R0, 0x3, RZ ; /* 0x0000000300037824 */
/* 0x000fca00078e02ff */
/*00d0*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00f0*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x00000204020b7981 */
/* 0x000ea8000c1e1100 */
/*0100*/ LDG.E.U8 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee8000c1e1100 */
/*0110*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010402087981 */
/* 0x000f22000c1e1100 */
/*0120*/ I2F.F64.U16 R6, R11 ; /* 0x0000000b00067312 */
/* 0x004e300000101800 */
/*0130*/ I2F.F64.U16 R4, R10 ; /* 0x0000000a00047312 */
/* 0x008e700000101800 */
/*0140*/ I2F.F64.U16 R8, R8 ; /* 0x0000000800087312 */
/* 0x010ea20000101800 */
/*0150*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e4c0000000000 */
/*0160*/ DFMA R4, R4, c[0x2][0x8], R6 ; /* 0x0080020004047a2b */
/* 0x0020a40000000006 */
/*0170*/ IADD3 R6, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x001fc80007f1e0ff */
/*0180*/ LEA.HI.X.SX32 R7, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000077a11 */
/* 0x000fe200000f0eff */
/*0190*/ DFMA R4, R8, c[0x2][0x10], R4 ; /* 0x0080040008047a2b */
/* 0x004e140000000004 */
/*01a0*/ F2I.U32.F64.TRUNC R5, R4 ; /* 0x0000000400057311 */
/* 0x001e24000030d000 */
/*01b0*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x001fe2000c101104 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23convertRgb2GrayByDevicePhS_ii
.globl _Z23convertRgb2GrayByDevicePhS_ii
.p2align 8
.type _Z23convertRgb2GrayByDevicePhS_ii,@function
_Z23convertRgb2GrayByDevicePhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3fbd2f1a
s_mov_b32 s0, 0x9fbe76c9
s_clause 0x2
global_load_u8 v3, v[0:1], off offset:2
global_load_u8 v4, v[0:1], off
global_load_u8 v5, v[0:1], off offset:1
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[0:1], v3
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[3:4], v4
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[0:1], v[0:1], s[0:1]
s_mov_b32 s1, 0x3fd322d0
s_mov_b32 s0, 0xe5604189
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[0:1], v[3:4], s[0:1], v[0:1]
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[3:4], v5
s_mov_b32 s1, 0x3fe2c8b4
s_mov_b32 s0, 0x39581062
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[0:1], v[3:4], s[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v3, v[0:1]
v_ashrrev_i32_e32 v1, 31, v2
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23convertRgb2GrayByDevicePhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23convertRgb2GrayByDevicePhS_ii, .Lfunc_end0-_Z23convertRgb2GrayByDevicePhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23convertRgb2GrayByDevicePhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23convertRgb2GrayByDevicePhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <curand.h>
#include <curand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void Backup(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *R_output, unsigned char *G_output,
unsigned char *B_output){
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_output[offset] = R_input[offset];
G_output[offset] = G_input[offset];
B_output[offset] = B_input[offset];
} | code for sm_80
Function : _Z6BackupPhS_S_mS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0080*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fca00078e0200 */
/*0090*/ SHF.R.S32.HI R12, RZ, 0x1f, R0 ; /* 0x0000001fff0c7819 */
/* 0x000fe40000011400 */
/*00a0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R3, R12, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000c037a10 */
/* 0x000fca00007fe4ff */
/*00c0*/ LDG.E.U8 R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1100 */
/*00d0*/ IADD3 R4, P0, R0.reuse, c[0x0][0x180], RZ ; /* 0x0000600000047a10 */
/* 0x040fe40007f1e0ff */
/*00e0*/ IADD3 R6, P1, R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x000fe40007f3e0ff */
/*00f0*/ IADD3.X R5, R12.reuse, c[0x0][0x184], RZ, P0, !PT ; /* 0x000061000c057a10 */
/* 0x040fe400007fe4ff */
/*0100*/ IADD3.X R7, R12, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000c077a10 */
/* 0x000fc60000ffe4ff */
/*0110*/ STG.E.U8 [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fe8000c101104 */
/*0120*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1100 */
/*0130*/ IADD3 R8, P0, R0.reuse, c[0x0][0x188], RZ ; /* 0x0000620000087a10 */
/* 0x040fe40007f1e0ff */
/*0140*/ IADD3 R10, P1, R0, c[0x0][0x170], RZ ; /* 0x00005c00000a7a10 */
/* 0x000fe40007f3e0ff */
/*0150*/ IADD3.X R9, R12.reuse, c[0x0][0x18c], RZ, P0, !PT ; /* 0x000063000c097a10 */
/* 0x040fe400007fe4ff */
/*0160*/ IADD3.X R11, R12, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000c0b7a10 */
/* 0x000fc60000ffe4ff */
/*0170*/ STG.E.U8 [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe8000c101104 */
/*0180*/ LDG.E.U8 R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1100 */
/*0190*/ IADD3 R2, P0, R0, c[0x0][0x190], RZ ; /* 0x0000640000027a10 */
/* 0x000fc80007f1e0ff */
/*01a0*/ IADD3.X R3, R12, c[0x0][0x194], RZ, P0, !PT ; /* 0x000065000c037a10 */
/* 0x000fca00007fe4ff */
/*01b0*/ STG.E.U8 [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x004fe2000c101104 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <curand.h>
#include <curand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void Backup(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *R_output, unsigned char *G_output,
unsigned char *B_output){
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_output[offset] = R_input[offset];
G_output[offset] = G_input[offset];
B_output[offset] = B_input[offset];
} | .file "tmpxft_000fcd15_00000000-6_backup.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_
.type _Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_, @function
_Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_:
.LFB2265:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6BackupPhS_S_mS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2265:
.size _Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_, .-_Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_
.globl _Z6BackupPhS_S_mS_S_S_
.type _Z6BackupPhS_S_mS_S_S_, @function
_Z6BackupPhS_S_mS_S_S_:
.LFB2266:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size _Z6BackupPhS_S_mS_S_S_, .-_Z6BackupPhS_S_mS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6BackupPhS_S_mS_S_S_"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2268:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6BackupPhS_S_mS_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2268:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <curand.h>
#include <curand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void Backup(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *R_output, unsigned char *G_output,
unsigned char *B_output){
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_output[offset] = R_input[offset];
G_output[offset] = G_input[offset];
B_output[offset] = B_input[offset];
} | #include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void Backup(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *R_output, unsigned char *G_output,
unsigned char *B_output){
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_output[offset] = R_input[offset];
G_output[offset] = G_input[offset];
B_output[offset] = B_input[offset];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void Backup(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *R_output, unsigned char *G_output,
unsigned char *B_output){
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_output[offset] = R_input[offset];
G_output[offset] = G_input[offset];
B_output[offset] = B_input[offset];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6BackupPhS_S_mS_S_S_
.globl _Z6BackupPhS_S_mS_S_S_
.p2align 8
.type _Z6BackupPhS_S_mS_S_S_,@function
_Z6BackupPhS_S_mS_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b128 s[8:11], s[0:1], 0x20
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x30
v_add3_u32 v4, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
global_load_u8 v6, v[0:1], off
v_add_co_u32 v0, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v6, off
global_load_u8 v6, v[2:3], off
v_add_co_u32 v0, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v6, off
global_load_u8 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6BackupPhS_S_mS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6BackupPhS_S_mS_S_S_, .Lfunc_end0-_Z6BackupPhS_S_mS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6BackupPhS_S_mS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6BackupPhS_S_mS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void Backup(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *R_output, unsigned char *G_output,
unsigned char *B_output){
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_output[offset] = R_input[offset];
G_output[offset] = G_input[offset];
B_output[offset] = B_input[offset];
} | .text
.file "backup.hip"
.globl _Z21__device_stub__BackupPhS_S_mS_S_S_ # -- Begin function _Z21__device_stub__BackupPhS_S_mS_S_S_
.p2align 4, 0x90
.type _Z21__device_stub__BackupPhS_S_mS_S_S_,@function
_Z21__device_stub__BackupPhS_S_mS_S_S_: # @_Z21__device_stub__BackupPhS_S_mS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6BackupPhS_S_mS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__BackupPhS_S_mS_S_S_, .Lfunc_end0-_Z21__device_stub__BackupPhS_S_mS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6BackupPhS_S_mS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6BackupPhS_S_mS_S_S_,@object # @_Z6BackupPhS_S_mS_S_S_
.section .rodata,"a",@progbits
.globl _Z6BackupPhS_S_mS_S_S_
.p2align 3, 0x0
_Z6BackupPhS_S_mS_S_S_:
.quad _Z21__device_stub__BackupPhS_S_mS_S_S_
.size _Z6BackupPhS_S_mS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6BackupPhS_S_mS_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__BackupPhS_S_mS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6BackupPhS_S_mS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6BackupPhS_S_mS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0080*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fca00078e0200 */
/*0090*/ SHF.R.S32.HI R12, RZ, 0x1f, R0 ; /* 0x0000001fff0c7819 */
/* 0x000fe40000011400 */
/*00a0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R3, R12, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000c037a10 */
/* 0x000fca00007fe4ff */
/*00c0*/ LDG.E.U8 R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1100 */
/*00d0*/ IADD3 R4, P0, R0.reuse, c[0x0][0x180], RZ ; /* 0x0000600000047a10 */
/* 0x040fe40007f1e0ff */
/*00e0*/ IADD3 R6, P1, R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x000fe40007f3e0ff */
/*00f0*/ IADD3.X R5, R12.reuse, c[0x0][0x184], RZ, P0, !PT ; /* 0x000061000c057a10 */
/* 0x040fe400007fe4ff */
/*0100*/ IADD3.X R7, R12, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000c077a10 */
/* 0x000fc60000ffe4ff */
/*0110*/ STG.E.U8 [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fe8000c101104 */
/*0120*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1100 */
/*0130*/ IADD3 R8, P0, R0.reuse, c[0x0][0x188], RZ ; /* 0x0000620000087a10 */
/* 0x040fe40007f1e0ff */
/*0140*/ IADD3 R10, P1, R0, c[0x0][0x170], RZ ; /* 0x00005c00000a7a10 */
/* 0x000fe40007f3e0ff */
/*0150*/ IADD3.X R9, R12.reuse, c[0x0][0x18c], RZ, P0, !PT ; /* 0x000063000c097a10 */
/* 0x040fe400007fe4ff */
/*0160*/ IADD3.X R11, R12, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000c0b7a10 */
/* 0x000fc60000ffe4ff */
/*0170*/ STG.E.U8 [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe8000c101104 */
/*0180*/ LDG.E.U8 R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1100 */
/*0190*/ IADD3 R2, P0, R0, c[0x0][0x190], RZ ; /* 0x0000640000027a10 */
/* 0x000fc80007f1e0ff */
/*01a0*/ IADD3.X R3, R12, c[0x0][0x194], RZ, P0, !PT ; /* 0x000065000c037a10 */
/* 0x000fca00007fe4ff */
/*01b0*/ STG.E.U8 [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x004fe2000c101104 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6BackupPhS_S_mS_S_S_
.globl _Z6BackupPhS_S_mS_S_S_
.p2align 8
.type _Z6BackupPhS_S_mS_S_S_,@function
_Z6BackupPhS_S_mS_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b128 s[8:11], s[0:1], 0x20
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x30
v_add3_u32 v4, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
global_load_u8 v6, v[0:1], off
v_add_co_u32 v0, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v6, off
global_load_u8 v6, v[2:3], off
v_add_co_u32 v0, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v6, off
global_load_u8 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6BackupPhS_S_mS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6BackupPhS_S_mS_S_S_, .Lfunc_end0-_Z6BackupPhS_S_mS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6BackupPhS_S_mS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6BackupPhS_S_mS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fcd15_00000000-6_backup.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_
.type _Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_, @function
_Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_:
.LFB2265:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6BackupPhS_S_mS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2265:
.size _Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_, .-_Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_
.globl _Z6BackupPhS_S_mS_S_S_
.type _Z6BackupPhS_S_mS_S_S_, @function
_Z6BackupPhS_S_mS_S_S_:
.LFB2266:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z6BackupPhS_S_mS_S_S_PhS_S_mS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size _Z6BackupPhS_S_mS_S_S_, .-_Z6BackupPhS_S_mS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6BackupPhS_S_mS_S_S_"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2268:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6BackupPhS_S_mS_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2268:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "backup.hip"
.globl _Z21__device_stub__BackupPhS_S_mS_S_S_ # -- Begin function _Z21__device_stub__BackupPhS_S_mS_S_S_
.p2align 4, 0x90
.type _Z21__device_stub__BackupPhS_S_mS_S_S_,@function
_Z21__device_stub__BackupPhS_S_mS_S_S_: # @_Z21__device_stub__BackupPhS_S_mS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6BackupPhS_S_mS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__BackupPhS_S_mS_S_S_, .Lfunc_end0-_Z21__device_stub__BackupPhS_S_mS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6BackupPhS_S_mS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6BackupPhS_S_mS_S_S_,@object # @_Z6BackupPhS_S_mS_S_S_
.section .rodata,"a",@progbits
.globl _Z6BackupPhS_S_mS_S_S_
.p2align 3, 0x0
_Z6BackupPhS_S_mS_S_S_:
.quad _Z21__device_stub__BackupPhS_S_mS_S_S_
.size _Z6BackupPhS_S_mS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6BackupPhS_S_mS_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__BackupPhS_S_mS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6BackupPhS_S_mS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void update(float * weights, float * grad,float lr,int N)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
if(x<N)
weights[x] -= lr*grad[x];
grad[x] = 0.0;
} | code for sm_80
Function : _Z6updatePfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x100 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R4.reuse, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x040fe200078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xf0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ FFMA R7, -R0, c[0x0][0x170], R7 ; /* 0x00005c0000077a23 */
/* 0x004fca0000000107 */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void update(float * weights, float * grad,float lr,int N)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
if(x<N)
weights[x] -= lr*grad[x];
grad[x] = 0.0;
} | .file "tmpxft_0012872e_00000000-6_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6updatePfS_fiPfS_fi
.type _Z29__device_stub__Z6updatePfS_fiPfS_fi, @function
_Z29__device_stub__Z6updatePfS_fiPfS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6updatePfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6updatePfS_fiPfS_fi, .-_Z29__device_stub__Z6updatePfS_fiPfS_fi
.globl _Z6updatePfS_fi
.type _Z6updatePfS_fi, @function
_Z6updatePfS_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6updatePfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6updatePfS_fi, .-_Z6updatePfS_fi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6updatePfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void update(float * weights, float * grad,float lr,int N)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
if(x<N)
weights[x] -= lr*grad[x];
grad[x] = 0.0;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update(float * weights, float * grad,float lr,int N)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
if(x<N)
weights[x] -= lr*grad[x];
grad[x] = 0.0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update(float * weights, float * grad,float lr,int N)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
if(x<N)
weights[x] -= lr*grad[x];
grad[x] = 0.0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6updatePfS_fi
.globl _Z6updatePfS_fi
.p2align 8
.type _Z6updatePfS_fi,@function
_Z6updatePfS_fi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x10
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_fma_f32 v0, -v0, s0, v5
global_store_b32 v[3:4], v0, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updatePfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6updatePfS_fi, .Lfunc_end0-_Z6updatePfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updatePfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6updatePfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update(float * weights, float * grad,float lr,int N)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
if(x<N)
weights[x] -= lr*grad[x];
grad[x] = 0.0;
} | .text
.file "update.hip"
.globl _Z21__device_stub__updatePfS_fi # -- Begin function _Z21__device_stub__updatePfS_fi
.p2align 4, 0x90
.type _Z21__device_stub__updatePfS_fi,@function
_Z21__device_stub__updatePfS_fi: # @_Z21__device_stub__updatePfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__updatePfS_fi, .Lfunc_end0-_Z21__device_stub__updatePfS_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6updatePfS_fi,@object # @_Z6updatePfS_fi
.section .rodata,"a",@progbits
.globl _Z6updatePfS_fi
.p2align 3, 0x0
_Z6updatePfS_fi:
.quad _Z21__device_stub__updatePfS_fi
.size _Z6updatePfS_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6updatePfS_fi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__updatePfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6updatePfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6updatePfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x100 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R4.reuse, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x040fe200078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xf0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ FFMA R7, -R0, c[0x0][0x170], R7 ; /* 0x00005c0000077a23 */
/* 0x004fca0000000107 */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6updatePfS_fi
.globl _Z6updatePfS_fi
.p2align 8
.type _Z6updatePfS_fi,@function
_Z6updatePfS_fi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x10
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_fma_f32 v0, -v0, s0, v5
global_store_b32 v[3:4], v0, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updatePfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6updatePfS_fi, .Lfunc_end0-_Z6updatePfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updatePfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6updatePfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012872e_00000000-6_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6updatePfS_fiPfS_fi
.type _Z29__device_stub__Z6updatePfS_fiPfS_fi, @function
_Z29__device_stub__Z6updatePfS_fiPfS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6updatePfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6updatePfS_fiPfS_fi, .-_Z29__device_stub__Z6updatePfS_fiPfS_fi
.globl _Z6updatePfS_fi
.type _Z6updatePfS_fi, @function
_Z6updatePfS_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6updatePfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6updatePfS_fi, .-_Z6updatePfS_fi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6updatePfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update.hip"
.globl _Z21__device_stub__updatePfS_fi # -- Begin function _Z21__device_stub__updatePfS_fi
.p2align 4, 0x90
.type _Z21__device_stub__updatePfS_fi,@function
_Z21__device_stub__updatePfS_fi: # @_Z21__device_stub__updatePfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__updatePfS_fi, .Lfunc_end0-_Z21__device_stub__updatePfS_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6updatePfS_fi,@object # @_Z6updatePfS_fi
.section .rodata,"a",@progbits
.globl _Z6updatePfS_fi
.p2align 3, 0x0
_Z6updatePfS_fi:
.quad _Z21__device_stub__updatePfS_fi
.size _Z6updatePfS_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6updatePfS_fi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__updatePfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6updatePfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "device_launch_parameters.h"
#include <stdio.h>
#define arraySize 5
#define threadPerBlock 5
// Kernel Function for Rank sort
__global__ void addKernel(int *d_a, int *d_b) {
int count = 0;
int tid = threadIdx.x;
int ttid = blockIdx.x * threadPerBlock + tid;
int val = d_a[ttid];
__shared__ int cache[threadPerBlock];
for (int i = tid; i < arraySize; i += threadPerBlock) {
cache[tid] = d_a[i];
__syncthreads();
for (int j = 0; j < threadPerBlock; ++j)
if (val > cache[j])
count++;
__syncthreads();
}
d_b[count] = val;
}
int main() {
// Define Host and Device Array
int h_a[arraySize] = {5, 9, 3, 4, 8};
int h_b[arraySize];
int *d_a, *d_b;
// Allocate Memory on the device
cudaMalloc((void **)&d_b, arraySize * sizeof(int));
cudaMalloc((void **)&d_a, arraySize * sizeof(int));
// Copy input vector from host memory to device memory.
cudaMemcpy(d_a, h_a, arraySize * sizeof(int), cudaMemcpyHostToDevice);
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<arraySize / threadPerBlock, threadPerBlock>>>(d_a, d_b);
// Wait for device to finish operations
cudaDeviceSynchronize();
// Copy output vector from GPU buffer to host memory.
cudaMemcpy(h_b, d_b, arraySize * sizeof(int), cudaMemcpyDeviceToHost);
printf("The Enumeration sorted Array is: \n");
for (int i = 0; i < arraySize; i++) {
printf("%d\n", h_b[i]);
}
// Free up device memory
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | code for sm_80
Function : _Z9addKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R3, R3, 0x5, R19 ; /* 0x0000000503037824 */
/* 0x001fc800078e0213 */
/*0060*/ IMAD.WIDE R2, R3, R18, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0212 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R19, 0x4, PT ; /* 0x000000041300780c */
/* 0x000fe20003f04270 */
/*0090*/ BSSY B0, 0x980 ; /* 0x000008e000007945 */
/* 0x000fe20003800000 */
/*00a0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fd6000001ff00 */
/*00b0*/ @P0 BRA 0x970 ; /* 0x000008b000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMNMX R2, RZ, R19, !PT ; /* 0x00000013ff027217 */
/* 0x001fe20007800200 */
/*00d0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.SHL.U32 R17, R19.reuse, 0x4, RZ ; /* 0x0000000413117824 */
/* 0x040fe200078e00ff */
/*00f0*/ IADD3 R4, -R19, 0x4, R2 ; /* 0x0000000413047810 */
/* 0x000fc80007ffe102 */
/*0100*/ ISETP.GE.U32.AND P1, PT, R4.reuse, 0xf, PT ; /* 0x0000000f0400780c */
/* 0x040fe20003f26070 */
/*0110*/ IMAD.WIDE.U32 R2, R4, -0x33333333, RZ ; /* 0xcccccccd04027825 */
/* 0x000fca00078e00ff */
/*0120*/ SHF.R.U32.HI R21, RZ, 0x2, R3 ; /* 0x00000002ff157819 */
/* 0x000fc80000011603 */
/*0130*/ IADD3 R16, R21, 0x1, RZ ; /* 0x0000000115107810 */
/* 0x000fc80007ffe0ff */
/*0140*/ LOP3.LUT R16, R16, 0x3, RZ, 0xc0, !PT ; /* 0x0000000310107812 */
/* 0x000fc800078ec0ff */
/*0150*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0160*/ @!P1 BRA 0x770 ; /* 0x0000060000009947 */
/* 0x000fd80003800000 */
/*0170*/ IMAD.WIDE R2, R19, R18, c[0x0][0x160] ; /* 0x0000580013027625 */
/* 0x000fc800078e0212 */
/*0180*/ IMAD.IADD R21, R21, 0x1, -R16 ; /* 0x0000000115157824 */
/* 0x000fe200078e0a10 */
/*0190*/ IADD3 R2, P1, R2, 0x28, RZ ; /* 0x0000002802027810 */
/* 0x000fe20007f3e0ff */
/*01a0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fca00008e0603 */
/*01c0*/ LDG.E R4, [R2.64+-0x28] ; /* 0xffffd80402047981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*01e0*/ STS [R17], R4 ; /* 0x0000000411007388 */
/* 0x004fe80000000800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0200*/ LDS R25, [0x10] ; /* 0x00001000ff197984 */
/* 0x000fe80000000800 */
/*0210*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e280000000c00 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ LDG.E R22, [R2.64+-0x14] ; /* 0xffffec0402167981 */
/* 0x000ea8000c1e1900 */
/*0240*/ STS [R17], R22 ; /* 0x0000001611007388 */
/* 0x0043e80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS R27, [0x10] ; /* 0x00001000ff1b7984 */
/* 0x000fe80000000800 */
/*0270*/ LDS.128 R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x000ea80000000c00 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ STS [R17], R24 ; /* 0x0000001811007388 */
/* 0x008fe80000000800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ LDS R23, [0x10] ; /* 0x00001000ff177984 */
/* 0x000fe80000000800 */
/*02d0*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000ee80000000c00 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140402167981 */
/* 0x002f22000c1e1900 */
/*0300*/ ISETP.GT.AND P1, PT, R0, R8, PT ; /* 0x000000080000720c */
/* 0x021fc40003f24270 */
/*0310*/ ISETP.GT.AND P2, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe40003f44270 */
/*0320*/ IADD3 R8, R20, 0x1, RZ ; /* 0x0000000114087810 */
/* 0x000fe40007ffe0ff */
/*0330*/ IADD3 R21, R21, -0x4, RZ ; /* 0xfffffffc15157810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R19, R19, 0x14, RZ ; /* 0x0000001413137810 */
/* 0x000fca0007ffe0ff */
/*0350*/ @!P1 IMAD.MOV R8, RZ, RZ, R20 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0214 */
/*0360*/ ISETP.GT.AND P1, PT, R0, R10, PT ; /* 0x0000000a0000720c */
/* 0x000fc80003f24270 */
/*0370*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0380*/ @!P2 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0208 */
/*0390*/ ISETP.GT.AND P2, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fc80003f44270 */
/*03a0*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ @!P1 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0209 */
/*03c0*/ ISETP.GT.AND P1, PT, R0, R25, PT ; /* 0x000000190000720c */
/* 0x000fc80003f24270 */
/*03d0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ @!P2 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0208 */
/*03f0*/ ISETP.GT.AND P2, PT, R0, R12, PT ; /* 0x0000000c0000720c */
/* 0x004fc80003f44270 */
/*0400*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fc60007ffe0ff */
/*0410*/ @!P1 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0209 */
/*0420*/ ISETP.GT.AND P1, PT, R0, R13, PT ; /* 0x0000000d0000720c */
/* 0x000fc80003f24270 */
/*0430*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0440*/ @!P2 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0208 */
/*0450*/ ISETP.GT.AND P2, PT, R0, R14, PT ; /* 0x0000000e0000720c */
/* 0x000fc80003f44270 */
/*0460*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fc60007ffe0ff */
/*0470*/ @!P1 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0209 */
/*0480*/ ISETP.GT.AND P1, PT, R0, R15, PT ; /* 0x0000000f0000720c */
/* 0x000fc80003f24270 */
/*0490*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ @!P2 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0208 */
/*04b0*/ ISETP.GT.AND P2, PT, R0, R27, PT ; /* 0x0000001b0000720c */
/* 0x000fc80003f44270 */
/*04c0*/ IADD3 R12, R9, 0x1, RZ ; /* 0x00000001090c7810 */
/* 0x000fc60007ffe0ff */
/*04d0*/ @!P1 IMAD.MOV R12, RZ, RZ, R9 ; /* 0x000000ffff0c9224 */
/* 0x000fe200078e0209 */
/*04e0*/ ISETP.GT.AND P1, PT, R0, R4, PT ; /* 0x000000040000720c */
/* 0x008fc80003f24270 */
/*04f0*/ IADD3 R4, R12, 0x1, RZ ; /* 0x000000010c047810 */
/* 0x000fe20007ffe0ff */
/*0500*/ @!P2 IMAD.MOV R4, RZ, RZ, R12 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e020c */
/*0510*/ ISETP.GT.AND P2, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fc80003f44270 */
/*0520*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fc60007ffe0ff */
/*0530*/ @!P1 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0204 */
/*0540*/ ISETP.GT.AND P1, PT, R0, R6, PT ; /* 0x000000060000720c */
/* 0x000fc80003f24270 */
/*0550*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fe20007ffe0ff */
/*0560*/ @!P2 IMAD.MOV R4, RZ, RZ, R5 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0205 */
/*0570*/ ISETP.GT.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fc80003f44270 */
/*0580*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fc60007ffe0ff */
/*0590*/ @!P1 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0204 */
/*05a0*/ ISETP.GT.AND P1, PT, R0, R23, PT ; /* 0x000000170000720c */
/* 0x000fc80003f24270 */
/*05b0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ @!P2 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff04a224 */
/* 0x000fca00078e0206 */
/*05d0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ @!P1 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fca00078e0204 */
/*05f0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*0600*/ STS [R17], R22 ; /* 0x0000001611007388 */
/* 0x010fe80000000800 */
/*0610*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0620*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e280000000c00 */
/*0630*/ LDS R5, [0x10] ; /* 0x00001000ff057984 */
/* 0x000e680000000800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0650*/ ISETP.GT.AND P2, PT, R0, R8, PT ; /* 0x000000080000720c */
/* 0x001fc40003f44270 */
/*0660*/ ISETP.GT.AND P1, PT, R0.reuse, R9, PT ; /* 0x000000090000720c */
/* 0x040fe40003f24270 */
/*0670*/ ISETP.GT.AND P3, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fd20003f64270 */
/*0680*/ @!P2 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0206 */
/*0690*/ ISETP.GT.AND P2, PT, R0, R10, PT ; /* 0x0000000a0000720c */
/* 0x000fc80003f44270 */
/*06a0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ @!P1 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0204 */
/*06c0*/ ISETP.GT.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x002fc80003f24270 */
/*06d0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fc60007ffe0ff */
/*06e0*/ @!P2 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0206 */
/*06f0*/ ISETP.NE.AND P2, PT, R21, -0x1, PT ; /* 0xffffffff1500780c */
/* 0x000fc80003f45270 */
/*0700*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*0710*/ @!P3 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff05b224 */
/* 0x000fe200078e0204 */
/*0720*/ IADD3 R2, P3, R2, 0x50, RZ ; /* 0x0000005002027810 */
/* 0x000fc80007f7e0ff */
/*0730*/ IADD3 R20, R5, 0x1, RZ ; /* 0x0000000105147810 */
/* 0x000fe20007ffe0ff */
/*0740*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe400018e0603 */
/*0750*/ @!P1 IMAD.MOV R20, RZ, RZ, R5 ; /* 0x000000ffff149224 */
/* 0x000fe200078e0205 */
/*0760*/ @P2 BRA 0x1c0 ; /* 0xfffffa5000002947 */
/* 0x000fea000383ffff */
/*0770*/ @!P0 BRA 0x960 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD.WIDE R18, R19, R18, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fc800078e0212 */
/*0790*/ IMAD.MOV.U32 R2, RZ, RZ, R18 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0012 */
/*07a0*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0013 */
/*07b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*07d0*/ IADD3 R16, R16, -0x1, RZ ; /* 0xffffffff10107810 */
/* 0x000fe40007ffe0ff */
/*07e0*/ IADD3 R18, P2, R18, 0x14, RZ ; /* 0x0000001412127810 */
/* 0x000fca0007f5e0ff */
/*07f0*/ IMAD.X R19, RZ, RZ, R19, P2 ; /* 0x000000ffff137224 */
/* 0x000fe200010e0613 */
/*0800*/ STS [R17], R2 ; /* 0x0000000211007388 */
/* 0x004fe80000000800 */
/*0810*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0820*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e280000000c00 */
/*0830*/ LDS R9, [0x10] ; /* 0x00001000ff097984 */
/* 0x000e680000000800 */
/*0840*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0850*/ ISETP.GT.AND P0, PT, R0, R4, PT ; /* 0x000000040000720c */
/* 0x021fc40003f04270 */
/*0860*/ ISETP.GT.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f24270 */
/*0870*/ IADD3 R4, R20, 0x1, RZ ; /* 0x0000000114047810 */
/* 0x000fd20007ffe0ff */
/*0880*/ @!P0 IMAD.MOV R4, RZ, RZ, R20 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0214 */
/*0890*/ ISETP.GT.AND P0, PT, R0, R6, PT ; /* 0x000000060000720c */
/* 0x000fc80003f04270 */
/*08a0*/ IADD3 R3, R4, 0x1, RZ ; /* 0x0000000104037810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ @!P1 IMAD.MOV R3, RZ, RZ, R4 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0204 */
/*08c0*/ ISETP.GT.AND P1, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fc80003f24270 */
/*08d0*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fc60007ffe0ff */
/*08e0*/ @!P0 IMAD.MOV R2, RZ, RZ, R3 ; /* 0x000000ffff028224 */
/* 0x000fe200078e0203 */
/*08f0*/ ISETP.GT.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x002fc80003f04270 */
/*0900*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*0910*/ @!P1 IMAD.MOV R3, RZ, RZ, R2 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0202 */
/*0920*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fc80003f25270 */
/*0930*/ IADD3 R20, R3, 0x1, RZ ; /* 0x0000000103147810 */
/* 0x000fc60007ffe0ff */
/*0940*/ @!P0 IMAD.MOV R20, RZ, RZ, R3 ; /* 0x000000ffff148224 */
/* 0x000fcc00078e0203 */
/*0950*/ @P1 BRA 0x790 ; /* 0xfffffe3000001947 */
/* 0x000fea000383ffff */
/*0960*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ; /* 0x0000001fff157819 */
/* 0x000fe40000011414 */
/*0970*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0980*/ LEA R2, P0, R20, c[0x0][0x168], 0x2 ; /* 0x00005a0014027a11 */
/* 0x000fc800078010ff */
/*0990*/ LEA.HI.X R3, R20, c[0x0][0x16c], R21, 0x2, P0 ; /* 0x00005b0014037a11 */
/* 0x000fca00000f1415 */
/*09a0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x020fe2000c101904 */
/*09b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "device_launch_parameters.h"
#include <stdio.h>
#define arraySize 5
#define threadPerBlock 5
// Kernel Function for Rank sort
__global__ void addKernel(int *d_a, int *d_b) {
int count = 0;
int tid = threadIdx.x;
int ttid = blockIdx.x * threadPerBlock + tid;
int val = d_a[ttid];
__shared__ int cache[threadPerBlock];
for (int i = tid; i < arraySize; i += threadPerBlock) {
cache[tid] = d_a[i];
__syncthreads();
for (int j = 0; j < threadPerBlock; ++j)
if (val > cache[j])
count++;
__syncthreads();
}
d_b[count] = val;
}
int main() {
// Define Host and Device Array
int h_a[arraySize] = {5, 9, 3, 4, 8};
int h_b[arraySize];
int *d_a, *d_b;
// Allocate Memory on the device
cudaMalloc((void **)&d_b, arraySize * sizeof(int));
cudaMalloc((void **)&d_a, arraySize * sizeof(int));
// Copy input vector from host memory to device memory.
cudaMemcpy(d_a, h_a, arraySize * sizeof(int), cudaMemcpyHostToDevice);
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<arraySize / threadPerBlock, threadPerBlock>>>(d_a, d_b);
// Wait for device to finish operations
cudaDeviceSynchronize();
// Copy output vector from GPU buffer to host memory.
cudaMemcpy(h_b, d_b, arraySize * sizeof(int), cudaMemcpyDeviceToHost);
printf("The Enumeration sorted Array is: \n");
for (int i = 0; i < arraySize; i++) {
printf("%d\n", h_b[i]);
}
// Free up device memory
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | .file "tmpxft_0012ecd8_00000000-6_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9addKernelPiS_PiS_
.type _Z30__device_stub__Z9addKernelPiS_PiS_, @function
_Z30__device_stub__Z9addKernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9addKernelPiS_PiS_, .-_Z30__device_stub__Z9addKernelPiS_PiS_
.globl _Z9addKernelPiS_
.type _Z9addKernelPiS_, @function
_Z9addKernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9addKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addKernelPiS_, .-_Z9addKernelPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "The Enumeration sorted Array is: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $5, 48(%rsp)
movl $9, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $8, 64(%rsp)
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rbx
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 100(%rsp), %r12
leaq .LC1(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9addKernelPiS_PiS_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9addKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "device_launch_parameters.h"
#include <stdio.h>
#define arraySize 5
#define threadPerBlock 5
// Kernel Function for Rank sort
__global__ void addKernel(int *d_a, int *d_b) {
int count = 0;
int tid = threadIdx.x;
int ttid = blockIdx.x * threadPerBlock + tid;
int val = d_a[ttid];
__shared__ int cache[threadPerBlock];
for (int i = tid; i < arraySize; i += threadPerBlock) {
cache[tid] = d_a[i];
__syncthreads();
for (int j = 0; j < threadPerBlock; ++j)
if (val > cache[j])
count++;
__syncthreads();
}
d_b[count] = val;
}
int main() {
// Define Host and Device Array
int h_a[arraySize] = {5, 9, 3, 4, 8};
int h_b[arraySize];
int *d_a, *d_b;
// Allocate Memory on the device
cudaMalloc((void **)&d_b, arraySize * sizeof(int));
cudaMalloc((void **)&d_a, arraySize * sizeof(int));
// Copy input vector from host memory to device memory.
cudaMemcpy(d_a, h_a, arraySize * sizeof(int), cudaMemcpyHostToDevice);
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<arraySize / threadPerBlock, threadPerBlock>>>(d_a, d_b);
// Wait for device to finish operations
cudaDeviceSynchronize();
// Copy output vector from GPU buffer to host memory.
cudaMemcpy(h_b, d_b, arraySize * sizeof(int), cudaMemcpyDeviceToHost);
printf("The Enumeration sorted Array is: \n");
for (int i = 0; i < arraySize; i++) {
printf("%d\n", h_b[i]);
}
// Free up device memory
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define arraySize 5
#define threadPerBlock 5
// Kernel Function for Rank sort
__global__ void addKernel(int *d_a, int *d_b) {
int count = 0;
int tid = threadIdx.x;
int ttid = blockIdx.x * threadPerBlock + tid;
int val = d_a[ttid];
__shared__ int cache[threadPerBlock];
for (int i = tid; i < arraySize; i += threadPerBlock) {
cache[tid] = d_a[i];
__syncthreads();
for (int j = 0; j < threadPerBlock; ++j)
if (val > cache[j])
count++;
__syncthreads();
}
d_b[count] = val;
}
int main() {
// Define Host and Device Array
int h_a[arraySize] = {5, 9, 3, 4, 8};
int h_b[arraySize];
int *d_a, *d_b;
// Allocate Memory on the device
hipMalloc((void **)&d_b, arraySize * sizeof(int));
hipMalloc((void **)&d_a, arraySize * sizeof(int));
// Copy input vector from host memory to device memory.
hipMemcpy(d_a, h_a, arraySize * sizeof(int), hipMemcpyHostToDevice);
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<arraySize / threadPerBlock, threadPerBlock>>>(d_a, d_b);
// Wait for device to finish operations
hipDeviceSynchronize();
// Copy output vector from GPU buffer to host memory.
hipMemcpy(h_b, d_b, arraySize * sizeof(int), hipMemcpyDeviceToHost);
printf("The Enumeration sorted Array is: \n");
for (int i = 0; i < arraySize; i++) {
printf("%d\n", h_b[i]);
}
// Free up device memory
hipFree(d_a);
hipFree(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define arraySize 5
#define threadPerBlock 5
// Kernel Function for Rank sort
__global__ void addKernel(int *d_a, int *d_b) {
int count = 0;
int tid = threadIdx.x;
int ttid = blockIdx.x * threadPerBlock + tid;
int val = d_a[ttid];
__shared__ int cache[threadPerBlock];
for (int i = tid; i < arraySize; i += threadPerBlock) {
cache[tid] = d_a[i];
__syncthreads();
for (int j = 0; j < threadPerBlock; ++j)
if (val > cache[j])
count++;
__syncthreads();
}
d_b[count] = val;
}
int main() {
// Define Host and Device Array
int h_a[arraySize] = {5, 9, 3, 4, 8};
int h_b[arraySize];
int *d_a, *d_b;
// Allocate Memory on the device
hipMalloc((void **)&d_b, arraySize * sizeof(int));
hipMalloc((void **)&d_a, arraySize * sizeof(int));
// Copy input vector from host memory to device memory.
hipMemcpy(d_a, h_a, arraySize * sizeof(int), hipMemcpyHostToDevice);
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<arraySize / threadPerBlock, threadPerBlock>>>(d_a, d_b);
// Wait for device to finish operations
hipDeviceSynchronize();
// Copy output vector from GPU buffer to host memory.
hipMemcpy(h_b, d_b, arraySize * sizeof(int), hipMemcpyDeviceToHost);
printf("The Enumeration sorted Array is: \n");
for (int i = 0; i < arraySize; i++) {
printf("%d\n", h_b[i]);
}
// Free up device memory
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_
.globl _Z9addKernelPiS_
.p2align 8
.type _Z9addKernelPiS_,@function
_Z9addKernelPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, 5, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_cmpx_gt_u32_e32 5, v0
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
global_load_b32 v2, v0, s[2:3]
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
v_mov_b32_e32 v0, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 20
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v3, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc0 .LBB0_2
v_mov_b32_e32 v2, 0
s_barrier
buffer_gl0_inv
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_
.amdhsa_group_segment_fixed_size 20
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_, .Lfunc_end0-_Z9addKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 20
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define arraySize 5
#define threadPerBlock 5
// Kernel Function for Rank sort
__global__ void addKernel(int *d_a, int *d_b) {
int count = 0;
int tid = threadIdx.x;
int ttid = blockIdx.x * threadPerBlock + tid;
int val = d_a[ttid];
__shared__ int cache[threadPerBlock];
for (int i = tid; i < arraySize; i += threadPerBlock) {
cache[tid] = d_a[i];
__syncthreads();
for (int j = 0; j < threadPerBlock; ++j)
if (val > cache[j])
count++;
__syncthreads();
}
d_b[count] = val;
}
int main() {
// Define Host and Device Array
int h_a[arraySize] = {5, 9, 3, 4, 8};
int h_b[arraySize];
int *d_a, *d_b;
// Allocate Memory on the device
hipMalloc((void **)&d_b, arraySize * sizeof(int));
hipMalloc((void **)&d_a, arraySize * sizeof(int));
// Copy input vector from host memory to device memory.
hipMemcpy(d_a, h_a, arraySize * sizeof(int), hipMemcpyHostToDevice);
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<arraySize / threadPerBlock, threadPerBlock>>>(d_a, d_b);
// Wait for device to finish operations
hipDeviceSynchronize();
// Copy output vector from GPU buffer to host memory.
hipMemcpy(h_b, d_b, arraySize * sizeof(int), hipMemcpyDeviceToHost);
printf("The Enumeration sorted Array is: \n");
for (int i = 0; i < arraySize; i++) {
printf("%d\n", h_b[i]);
}
// Free up device memory
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.file "sort.hip"
.globl _Z24__device_stub__addKernelPiS_ # -- Begin function _Z24__device_stub__addKernelPiS_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_,@function
_Z24__device_stub__addKernelPiS_: # @_Z24__device_stub__addKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiS_, .Lfunc_end0-_Z24__device_stub__addKernelPiS_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 5 # 0x5
.long 9 # 0x9
.long 3 # 0x3
.long 4 # 0x4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [5,9,3,4]
movaps %xmm0, 112(%rsp)
movl $8, 128(%rsp)
movq %rsp, %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9addKernelPiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 16(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiS_,@object # @_Z9addKernelPiS_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_
.p2align 3, 0x0
_Z9addKernelPiS_:
.quad _Z24__device_stub__addKernelPiS_
.size _Z9addKernelPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The Enumeration sorted Array is: "
.size .Lstr, 34
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R3, R3, 0x5, R19 ; /* 0x0000000503037824 */
/* 0x001fc800078e0213 */
/*0060*/ IMAD.WIDE R2, R3, R18, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0212 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R19, 0x4, PT ; /* 0x000000041300780c */
/* 0x000fe20003f04270 */
/*0090*/ BSSY B0, 0x980 ; /* 0x000008e000007945 */
/* 0x000fe20003800000 */
/*00a0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fd6000001ff00 */
/*00b0*/ @P0 BRA 0x970 ; /* 0x000008b000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMNMX R2, RZ, R19, !PT ; /* 0x00000013ff027217 */
/* 0x001fe20007800200 */
/*00d0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.SHL.U32 R17, R19.reuse, 0x4, RZ ; /* 0x0000000413117824 */
/* 0x040fe200078e00ff */
/*00f0*/ IADD3 R4, -R19, 0x4, R2 ; /* 0x0000000413047810 */
/* 0x000fc80007ffe102 */
/*0100*/ ISETP.GE.U32.AND P1, PT, R4.reuse, 0xf, PT ; /* 0x0000000f0400780c */
/* 0x040fe20003f26070 */
/*0110*/ IMAD.WIDE.U32 R2, R4, -0x33333333, RZ ; /* 0xcccccccd04027825 */
/* 0x000fca00078e00ff */
/*0120*/ SHF.R.U32.HI R21, RZ, 0x2, R3 ; /* 0x00000002ff157819 */
/* 0x000fc80000011603 */
/*0130*/ IADD3 R16, R21, 0x1, RZ ; /* 0x0000000115107810 */
/* 0x000fc80007ffe0ff */
/*0140*/ LOP3.LUT R16, R16, 0x3, RZ, 0xc0, !PT ; /* 0x0000000310107812 */
/* 0x000fc800078ec0ff */
/*0150*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0160*/ @!P1 BRA 0x770 ; /* 0x0000060000009947 */
/* 0x000fd80003800000 */
/*0170*/ IMAD.WIDE R2, R19, R18, c[0x0][0x160] ; /* 0x0000580013027625 */
/* 0x000fc800078e0212 */
/*0180*/ IMAD.IADD R21, R21, 0x1, -R16 ; /* 0x0000000115157824 */
/* 0x000fe200078e0a10 */
/*0190*/ IADD3 R2, P1, R2, 0x28, RZ ; /* 0x0000002802027810 */
/* 0x000fe20007f3e0ff */
/*01a0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fca00008e0603 */
/*01c0*/ LDG.E R4, [R2.64+-0x28] ; /* 0xffffd80402047981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*01e0*/ STS [R17], R4 ; /* 0x0000000411007388 */
/* 0x004fe80000000800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0200*/ LDS R25, [0x10] ; /* 0x00001000ff197984 */
/* 0x000fe80000000800 */
/*0210*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e280000000c00 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ LDG.E R22, [R2.64+-0x14] ; /* 0xffffec0402167981 */
/* 0x000ea8000c1e1900 */
/*0240*/ STS [R17], R22 ; /* 0x0000001611007388 */
/* 0x0043e80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS R27, [0x10] ; /* 0x00001000ff1b7984 */
/* 0x000fe80000000800 */
/*0270*/ LDS.128 R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x000ea80000000c00 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ STS [R17], R24 ; /* 0x0000001811007388 */
/* 0x008fe80000000800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ LDS R23, [0x10] ; /* 0x00001000ff177984 */
/* 0x000fe80000000800 */
/*02d0*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000ee80000000c00 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140402167981 */
/* 0x002f22000c1e1900 */
/*0300*/ ISETP.GT.AND P1, PT, R0, R8, PT ; /* 0x000000080000720c */
/* 0x021fc40003f24270 */
/*0310*/ ISETP.GT.AND P2, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe40003f44270 */
/*0320*/ IADD3 R8, R20, 0x1, RZ ; /* 0x0000000114087810 */
/* 0x000fe40007ffe0ff */
/*0330*/ IADD3 R21, R21, -0x4, RZ ; /* 0xfffffffc15157810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R19, R19, 0x14, RZ ; /* 0x0000001413137810 */
/* 0x000fca0007ffe0ff */
/*0350*/ @!P1 IMAD.MOV R8, RZ, RZ, R20 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0214 */
/*0360*/ ISETP.GT.AND P1, PT, R0, R10, PT ; /* 0x0000000a0000720c */
/* 0x000fc80003f24270 */
/*0370*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0380*/ @!P2 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0208 */
/*0390*/ ISETP.GT.AND P2, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fc80003f44270 */
/*03a0*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ @!P1 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0209 */
/*03c0*/ ISETP.GT.AND P1, PT, R0, R25, PT ; /* 0x000000190000720c */
/* 0x000fc80003f24270 */
/*03d0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ @!P2 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0208 */
/*03f0*/ ISETP.GT.AND P2, PT, R0, R12, PT ; /* 0x0000000c0000720c */
/* 0x004fc80003f44270 */
/*0400*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fc60007ffe0ff */
/*0410*/ @!P1 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0209 */
/*0420*/ ISETP.GT.AND P1, PT, R0, R13, PT ; /* 0x0000000d0000720c */
/* 0x000fc80003f24270 */
/*0430*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0440*/ @!P2 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0208 */
/*0450*/ ISETP.GT.AND P2, PT, R0, R14, PT ; /* 0x0000000e0000720c */
/* 0x000fc80003f44270 */
/*0460*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fc60007ffe0ff */
/*0470*/ @!P1 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0209 */
/*0480*/ ISETP.GT.AND P1, PT, R0, R15, PT ; /* 0x0000000f0000720c */
/* 0x000fc80003f24270 */
/*0490*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ @!P2 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0208 */
/*04b0*/ ISETP.GT.AND P2, PT, R0, R27, PT ; /* 0x0000001b0000720c */
/* 0x000fc80003f44270 */
/*04c0*/ IADD3 R12, R9, 0x1, RZ ; /* 0x00000001090c7810 */
/* 0x000fc60007ffe0ff */
/*04d0*/ @!P1 IMAD.MOV R12, RZ, RZ, R9 ; /* 0x000000ffff0c9224 */
/* 0x000fe200078e0209 */
/*04e0*/ ISETP.GT.AND P1, PT, R0, R4, PT ; /* 0x000000040000720c */
/* 0x008fc80003f24270 */
/*04f0*/ IADD3 R4, R12, 0x1, RZ ; /* 0x000000010c047810 */
/* 0x000fe20007ffe0ff */
/*0500*/ @!P2 IMAD.MOV R4, RZ, RZ, R12 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e020c */
/*0510*/ ISETP.GT.AND P2, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fc80003f44270 */
/*0520*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fc60007ffe0ff */
/*0530*/ @!P1 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0204 */
/*0540*/ ISETP.GT.AND P1, PT, R0, R6, PT ; /* 0x000000060000720c */
/* 0x000fc80003f24270 */
/*0550*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fe20007ffe0ff */
/*0560*/ @!P2 IMAD.MOV R4, RZ, RZ, R5 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0205 */
/*0570*/ ISETP.GT.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fc80003f44270 */
/*0580*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fc60007ffe0ff */
/*0590*/ @!P1 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0204 */
/*05a0*/ ISETP.GT.AND P1, PT, R0, R23, PT ; /* 0x000000170000720c */
/* 0x000fc80003f24270 */
/*05b0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ @!P2 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff04a224 */
/* 0x000fca00078e0206 */
/*05d0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ @!P1 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fca00078e0204 */
/*05f0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*0600*/ STS [R17], R22 ; /* 0x0000001611007388 */
/* 0x010fe80000000800 */
/*0610*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0620*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e280000000c00 */
/*0630*/ LDS R5, [0x10] ; /* 0x00001000ff057984 */
/* 0x000e680000000800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0650*/ ISETP.GT.AND P2, PT, R0, R8, PT ; /* 0x000000080000720c */
/* 0x001fc40003f44270 */
/*0660*/ ISETP.GT.AND P1, PT, R0.reuse, R9, PT ; /* 0x000000090000720c */
/* 0x040fe40003f24270 */
/*0670*/ ISETP.GT.AND P3, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fd20003f64270 */
/*0680*/ @!P2 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0206 */
/*0690*/ ISETP.GT.AND P2, PT, R0, R10, PT ; /* 0x0000000a0000720c */
/* 0x000fc80003f44270 */
/*06a0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ @!P1 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0204 */
/*06c0*/ ISETP.GT.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x002fc80003f24270 */
/*06d0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fc60007ffe0ff */
/*06e0*/ @!P2 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0206 */
/*06f0*/ ISETP.NE.AND P2, PT, R21, -0x1, PT ; /* 0xffffffff1500780c */
/* 0x000fc80003f45270 */
/*0700*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*0710*/ @!P3 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff05b224 */
/* 0x000fe200078e0204 */
/*0720*/ IADD3 R2, P3, R2, 0x50, RZ ; /* 0x0000005002027810 */
/* 0x000fc80007f7e0ff */
/*0730*/ IADD3 R20, R5, 0x1, RZ ; /* 0x0000000105147810 */
/* 0x000fe20007ffe0ff */
/*0740*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe400018e0603 */
/*0750*/ @!P1 IMAD.MOV R20, RZ, RZ, R5 ; /* 0x000000ffff149224 */
/* 0x000fe200078e0205 */
/*0760*/ @P2 BRA 0x1c0 ; /* 0xfffffa5000002947 */
/* 0x000fea000383ffff */
/*0770*/ @!P0 BRA 0x960 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD.WIDE R18, R19, R18, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fc800078e0212 */
/*0790*/ IMAD.MOV.U32 R2, RZ, RZ, R18 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0012 */
/*07a0*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0013 */
/*07b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*07d0*/ IADD3 R16, R16, -0x1, RZ ; /* 0xffffffff10107810 */
/* 0x000fe40007ffe0ff */
/*07e0*/ IADD3 R18, P2, R18, 0x14, RZ ; /* 0x0000001412127810 */
/* 0x000fca0007f5e0ff */
/*07f0*/ IMAD.X R19, RZ, RZ, R19, P2 ; /* 0x000000ffff137224 */
/* 0x000fe200010e0613 */
/*0800*/ STS [R17], R2 ; /* 0x0000000211007388 */
/* 0x004fe80000000800 */
/*0810*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0820*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e280000000c00 */
/*0830*/ LDS R9, [0x10] ; /* 0x00001000ff097984 */
/* 0x000e680000000800 */
/*0840*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0850*/ ISETP.GT.AND P0, PT, R0, R4, PT ; /* 0x000000040000720c */
/* 0x021fc40003f04270 */
/*0860*/ ISETP.GT.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f24270 */
/*0870*/ IADD3 R4, R20, 0x1, RZ ; /* 0x0000000114047810 */
/* 0x000fd20007ffe0ff */
/*0880*/ @!P0 IMAD.MOV R4, RZ, RZ, R20 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0214 */
/*0890*/ ISETP.GT.AND P0, PT, R0, R6, PT ; /* 0x000000060000720c */
/* 0x000fc80003f04270 */
/*08a0*/ IADD3 R3, R4, 0x1, RZ ; /* 0x0000000104037810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ @!P1 IMAD.MOV R3, RZ, RZ, R4 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0204 */
/*08c0*/ ISETP.GT.AND P1, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fc80003f24270 */
/*08d0*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fc60007ffe0ff */
/*08e0*/ @!P0 IMAD.MOV R2, RZ, RZ, R3 ; /* 0x000000ffff028224 */
/* 0x000fe200078e0203 */
/*08f0*/ ISETP.GT.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x002fc80003f04270 */
/*0900*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*0910*/ @!P1 IMAD.MOV R3, RZ, RZ, R2 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0202 */
/*0920*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fc80003f25270 */
/*0930*/ IADD3 R20, R3, 0x1, RZ ; /* 0x0000000103147810 */
/* 0x000fc60007ffe0ff */
/*0940*/ @!P0 IMAD.MOV R20, RZ, RZ, R3 ; /* 0x000000ffff148224 */
/* 0x000fcc00078e0203 */
/*0950*/ @P1 BRA 0x790 ; /* 0xfffffe3000001947 */
/* 0x000fea000383ffff */
/*0960*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ; /* 0x0000001fff157819 */
/* 0x000fe40000011414 */
/*0970*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0980*/ LEA R2, P0, R20, c[0x0][0x168], 0x2 ; /* 0x00005a0014027a11 */
/* 0x000fc800078010ff */
/*0990*/ LEA.HI.X R3, R20, c[0x0][0x16c], R21, 0x2, P0 ; /* 0x00005b0014037a11 */
/* 0x000fca00000f1415 */
/*09a0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x020fe2000c101904 */
/*09b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_
.globl _Z9addKernelPiS_
.p2align 8
.type _Z9addKernelPiS_,@function
_Z9addKernelPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, 5, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_cmpx_gt_u32_e32 5, v0
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
global_load_b32 v2, v0, s[2:3]
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
v_mov_b32_e32 v0, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 20
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v3, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc0 .LBB0_2
v_mov_b32_e32 v2, 0
s_barrier
buffer_gl0_inv
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_
.amdhsa_group_segment_fixed_size 20
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_, .Lfunc_end0-_Z9addKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 20
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012ecd8_00000000-6_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9addKernelPiS_PiS_
.type _Z30__device_stub__Z9addKernelPiS_PiS_, @function
_Z30__device_stub__Z9addKernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9addKernelPiS_PiS_, .-_Z30__device_stub__Z9addKernelPiS_PiS_
.globl _Z9addKernelPiS_
.type _Z9addKernelPiS_, @function
_Z9addKernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9addKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addKernelPiS_, .-_Z9addKernelPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "The Enumeration sorted Array is: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $5, 48(%rsp)
movl $9, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $8, 64(%rsp)
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rbx
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 100(%rsp), %r12
leaq .LC1(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9addKernelPiS_PiS_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9addKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sort.hip"
.globl _Z24__device_stub__addKernelPiS_ # -- Begin function _Z24__device_stub__addKernelPiS_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_,@function
_Z24__device_stub__addKernelPiS_: # @_Z24__device_stub__addKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiS_, .Lfunc_end0-_Z24__device_stub__addKernelPiS_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 5 # 0x5
.long 9 # 0x9
.long 3 # 0x3
.long 4 # 0x4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [5,9,3,4]
movaps %xmm0, 112(%rsp)
movl $8, 128(%rsp)
movq %rsp, %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9addKernelPiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 16(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiS_,@object # @_Z9addKernelPiS_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_
.p2align 3, 0x0
_Z9addKernelPiS_:
.quad _Z24__device_stub__addKernelPiS_
.size _Z9addKernelPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The Enumeration sorted Array is: "
.size .Lstr, 34
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void backward_sam_kernel(float *in_w_h_c_delta, int size, int channel_size, float *in_scales_c, float *out_from_delta, float *in_from_output, float *out_state_delta)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < size) {
out_state_delta[index] += in_w_h_c_delta[index] * in_from_output[index]; // l.delta * from (should be divided by channel_size?)
out_from_delta[index] += in_scales_c[index] * in_w_h_c_delta[index]; // input * l.delta
//out_state_delta[index] += in_w_h_c_delta[index];
//out_from_delta[index] = in_w_h_c_delta[index];
}
} | code for sm_80
Function : _Z19backward_sam_kernelPfiiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R10, R11, c[0x0][0x180] ; /* 0x000060000a047625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R2, R10.reuse, R11.reuse, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x0c0fe400078e020b */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R10, R11, c[0x0][0x188] ; /* 0x000062000a067625 */
/* 0x000fe400078e020b */
/*00c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ FFMA R13, R4, R9, R0 ; /* 0x00000009040d7223 */
/* 0x004fc40000000000 */
/*00f0*/ IMAD.WIDE R8, R10, R11, c[0x0][0x170] ; /* 0x00005c000a087625 */
/* 0x000fc800078e020b */
/*0100*/ IMAD.WIDE R10, R10, R11, c[0x0][0x178] ; /* 0x00005e000a0a7625 */
/* 0x000fe200078e020b */
/*0110*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*0120*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FFMA R15, R0, R9, R12 ; /* 0x00000009000f7223 */
/* 0x004fca000000000c */
/*0160*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void backward_sam_kernel(float *in_w_h_c_delta, int size, int channel_size, float *in_scales_c, float *out_from_delta, float *in_from_output, float *out_state_delta)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < size) {
out_state_delta[index] += in_w_h_c_delta[index] * in_from_output[index]; // l.delta * from (should be divided by channel_size?)
out_from_delta[index] += in_scales_c[index] * in_w_h_c_delta[index]; // input * l.delta
//out_state_delta[index] += in_w_h_c_delta[index];
//out_from_delta[index] = in_w_h_c_delta[index];
}
} | .file "tmpxft_001618b8_00000000-6_backward_sam_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_
.type _Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_, @function
_Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19backward_sam_kernelPfiiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_, .-_Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_
.globl _Z19backward_sam_kernelPfiiS_S_S_S_
.type _Z19backward_sam_kernelPfiiS_S_S_S_, @function
_Z19backward_sam_kernelPfiiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19backward_sam_kernelPfiiS_S_S_S_, .-_Z19backward_sam_kernelPfiiS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19backward_sam_kernelPfiiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19backward_sam_kernelPfiiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void backward_sam_kernel(float *in_w_h_c_delta, int size, int channel_size, float *in_scales_c, float *out_from_delta, float *in_from_output, float *out_state_delta)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < size) {
out_state_delta[index] += in_w_h_c_delta[index] * in_from_output[index]; // l.delta * from (should be divided by channel_size?)
out_from_delta[index] += in_scales_c[index] * in_w_h_c_delta[index]; // input * l.delta
//out_state_delta[index] += in_w_h_c_delta[index];
//out_from_delta[index] = in_w_h_c_delta[index];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void backward_sam_kernel(float *in_w_h_c_delta, int size, int channel_size, float *in_scales_c, float *out_from_delta, float *in_from_output, float *out_state_delta)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < size) {
out_state_delta[index] += in_w_h_c_delta[index] * in_from_output[index]; // l.delta * from (should be divided by channel_size?)
out_from_delta[index] += in_scales_c[index] * in_w_h_c_delta[index]; // input * l.delta
//out_state_delta[index] += in_w_h_c_delta[index];
//out_from_delta[index] = in_w_h_c_delta[index];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void backward_sam_kernel(float *in_w_h_c_delta, int size, int channel_size, float *in_scales_c, float *out_from_delta, float *in_from_output, float *out_state_delta)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < size) {
out_state_delta[index] += in_w_h_c_delta[index] * in_from_output[index]; // l.delta * from (should be divided by channel_size?)
out_from_delta[index] += in_scales_c[index] * in_w_h_c_delta[index]; // input * l.delta
//out_state_delta[index] += in_w_h_c_delta[index];
//out_from_delta[index] = in_w_h_c_delta[index];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19backward_sam_kernelPfiiS_S_S_S_
.globl _Z19backward_sam_kernelPfiiS_S_S_S_
.p2align 8
.type _Z19backward_sam_kernelPfiiS_S_S_S_,@function
_Z19backward_sam_kernelPfiiS_S_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b256 s[0:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
global_load_b32 v8, v[2:3], off
global_load_b32 v9, v[4:5], off
global_load_b32 v10, v[6:7], off
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v10, v8, v9
global_store_b32 v[6:7], v10, off
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v4, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19backward_sam_kernelPfiiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19backward_sam_kernelPfiiS_S_S_S_, .Lfunc_end0-_Z19backward_sam_kernelPfiiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19backward_sam_kernelPfiiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19backward_sam_kernelPfiiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void backward_sam_kernel(float *in_w_h_c_delta, int size, int channel_size, float *in_scales_c, float *out_from_delta, float *in_from_output, float *out_state_delta)
{
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < size) {
out_state_delta[index] += in_w_h_c_delta[index] * in_from_output[index]; // l.delta * from (should be divided by channel_size?)
out_from_delta[index] += in_scales_c[index] * in_w_h_c_delta[index]; // input * l.delta
//out_state_delta[index] += in_w_h_c_delta[index];
//out_from_delta[index] = in_w_h_c_delta[index];
}
} | .text
.file "backward_sam_kernel.hip"
.globl _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_ # -- Begin function _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.p2align 4, 0x90
.type _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_,@function
_Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_: # @_Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19backward_sam_kernelPfiiS_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_, .Lfunc_end0-_Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19backward_sam_kernelPfiiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19backward_sam_kernelPfiiS_S_S_S_,@object # @_Z19backward_sam_kernelPfiiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z19backward_sam_kernelPfiiS_S_S_S_
.p2align 3, 0x0
_Z19backward_sam_kernelPfiiS_S_S_S_:
.quad _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.size _Z19backward_sam_kernelPfiiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19backward_sam_kernelPfiiS_S_S_S_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19backward_sam_kernelPfiiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19backward_sam_kernelPfiiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R10, R11, c[0x0][0x180] ; /* 0x000060000a047625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R2, R10.reuse, R11.reuse, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x0c0fe400078e020b */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R10, R11, c[0x0][0x188] ; /* 0x000062000a067625 */
/* 0x000fe400078e020b */
/*00c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ FFMA R13, R4, R9, R0 ; /* 0x00000009040d7223 */
/* 0x004fc40000000000 */
/*00f0*/ IMAD.WIDE R8, R10, R11, c[0x0][0x170] ; /* 0x00005c000a087625 */
/* 0x000fc800078e020b */
/*0100*/ IMAD.WIDE R10, R10, R11, c[0x0][0x178] ; /* 0x00005e000a0a7625 */
/* 0x000fe200078e020b */
/*0110*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*0120*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FFMA R15, R0, R9, R12 ; /* 0x00000009000f7223 */
/* 0x004fca000000000c */
/*0160*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19backward_sam_kernelPfiiS_S_S_S_
.globl _Z19backward_sam_kernelPfiiS_S_S_S_
.p2align 8
.type _Z19backward_sam_kernelPfiiS_S_S_S_,@function
_Z19backward_sam_kernelPfiiS_S_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b256 s[0:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
global_load_b32 v8, v[2:3], off
global_load_b32 v9, v[4:5], off
global_load_b32 v10, v[6:7], off
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v10, v8, v9
global_store_b32 v[6:7], v10, off
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v4, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19backward_sam_kernelPfiiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19backward_sam_kernelPfiiS_S_S_S_, .Lfunc_end0-_Z19backward_sam_kernelPfiiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19backward_sam_kernelPfiiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19backward_sam_kernelPfiiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001618b8_00000000-6_backward_sam_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_
.type _Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_, @function
_Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19backward_sam_kernelPfiiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_, .-_Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_
.globl _Z19backward_sam_kernelPfiiS_S_S_S_
.type _Z19backward_sam_kernelPfiiS_S_S_S_, @function
_Z19backward_sam_kernelPfiiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z19backward_sam_kernelPfiiS_S_S_S_PfiiS_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19backward_sam_kernelPfiiS_S_S_S_, .-_Z19backward_sam_kernelPfiiS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19backward_sam_kernelPfiiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19backward_sam_kernelPfiiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "backward_sam_kernel.hip"
.globl _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_ # -- Begin function _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.p2align 4, 0x90
.type _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_,@function
_Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_: # @_Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19backward_sam_kernelPfiiS_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_, .Lfunc_end0-_Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19backward_sam_kernelPfiiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19backward_sam_kernelPfiiS_S_S_S_,@object # @_Z19backward_sam_kernelPfiiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z19backward_sam_kernelPfiiS_S_S_S_
.p2align 3, 0x0
_Z19backward_sam_kernelPfiiS_S_S_S_:
.quad _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.size _Z19backward_sam_kernelPfiiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19backward_sam_kernelPfiiS_S_S_S_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__backward_sam_kernelPfiiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19backward_sam_kernelPfiiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // nvcc sum_array.cu -o sum_array.out & ./sum_array.out
#include <stdio.h>
#define N 10
__global__ void vecAdd(int* a, int* b, int* c);
void print_array(int* a);
int main(void){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = N - i - 1;
}
printf("a -> "); print_array(a);
printf("b -> "); print_array(b);
printf("c -> "); print_array(c);
int size = N * sizeof(int);
cudaMalloc( (void**) &dev_a, size);
cudaMalloc( (void**) &dev_b, size);
cudaMalloc( (void**) &dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
vecAdd<<<1,N>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
printf("c -> "); print_array(c);
exit (0);
}
__global__ void vecAdd(int* a, int* b, int* c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
void print_array(int* a){
for(int i = 0; i < N; i++){
printf("%d ", a[i]);
}
printf("\n");
} | code for sm_80
Function : _Z6vecAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // nvcc sum_array.cu -o sum_array.out & ./sum_array.out
#include <stdio.h>
#define N 10
__global__ void vecAdd(int* a, int* b, int* c);
void print_array(int* a);
int main(void){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = N - i - 1;
}
printf("a -> "); print_array(a);
printf("b -> "); print_array(b);
printf("c -> "); print_array(c);
int size = N * sizeof(int);
cudaMalloc( (void**) &dev_a, size);
cudaMalloc( (void**) &dev_b, size);
cudaMalloc( (void**) &dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
vecAdd<<<1,N>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
printf("c -> "); print_array(c);
exit (0);
}
__global__ void vecAdd(int* a, int* b, int* c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
void print_array(int* a){
for(int i = 0; i < N; i++){
printf("%d ", a[i]);
}
printf("\n");
} | .file "tmpxft_0001cefd_00000000-6_sum_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPi
.type _Z11print_arrayPi, @function
_Z11print_arrayPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 40(%rdi), %r12
leaq .LC0(%rip), %rbp
.L4:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L4
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11print_arrayPi, .-_Z11print_arrayPi
.globl _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecAddPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.globl _Z6vecAddPiS_S_
.type _Z6vecAddPiS_S_, @function
_Z6vecAddPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6vecAddPiS_S_, .-_Z6vecAddPiS_S_
.section .rodata.str1.1
.LC2:
.string "a -> "
.LC3:
.string "b -> "
.LC4:
.string "c -> "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movl $9, %ecx
.L16:
movl %eax, 0(%rbp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call _Z11print_arrayPi
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call _Z11print_arrayPi
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call _Z11print_arrayPi
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call _Z11print_arrayPi
movl $0, %edi
call exit@PLT
.L21:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
jmp .L17
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6vecAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // nvcc sum_array.cu -o sum_array.out & ./sum_array.out
#include <stdio.h>
#define N 10
__global__ void vecAdd(int* a, int* b, int* c);
void print_array(int* a);
int main(void){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = N - i - 1;
}
printf("a -> "); print_array(a);
printf("b -> "); print_array(b);
printf("c -> "); print_array(c);
int size = N * sizeof(int);
cudaMalloc( (void**) &dev_a, size);
cudaMalloc( (void**) &dev_b, size);
cudaMalloc( (void**) &dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
vecAdd<<<1,N>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
printf("c -> "); print_array(c);
exit (0);
}
__global__ void vecAdd(int* a, int* b, int* c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
void print_array(int* a){
for(int i = 0; i < N; i++){
printf("%d ", a[i]);
}
printf("\n");
} | // nvcc sum_array.cu -o sum_array.out & ./sum_array.out
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 10
__global__ void vecAdd(int* a, int* b, int* c);
void print_array(int* a);
int main(void){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = N - i - 1;
}
printf("a -> "); print_array(a);
printf("b -> "); print_array(b);
printf("c -> "); print_array(c);
int size = N * sizeof(int);
hipMalloc( (void**) &dev_a, size);
hipMalloc( (void**) &dev_b, size);
hipMalloc( (void**) &dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
vecAdd<<<1,N>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
printf("c -> "); print_array(c);
exit (0);
}
__global__ void vecAdd(int* a, int* b, int* c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
void print_array(int* a){
for(int i = 0; i < N; i++){
printf("%d ", a[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // nvcc sum_array.cu -o sum_array.out & ./sum_array.out
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 10
__global__ void vecAdd(int* a, int* b, int* c);
void print_array(int* a);
int main(void){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = N - i - 1;
}
printf("a -> "); print_array(a);
printf("b -> "); print_array(b);
printf("c -> "); print_array(c);
int size = N * sizeof(int);
hipMalloc( (void**) &dev_a, size);
hipMalloc( (void**) &dev_b, size);
hipMalloc( (void**) &dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
vecAdd<<<1,N>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
printf("c -> "); print_array(c);
exit (0);
}
__global__ void vecAdd(int* a, int* b, int* c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
void print_array(int* a){
for(int i = 0; i < N; i++){
printf("%d ", a[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPiS_S_
.globl _Z6vecAddPiS_S_
.p2align 8
.type _Z6vecAddPiS_S_,@function
_Z6vecAddPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPiS_S_, .Lfunc_end0-_Z6vecAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // nvcc sum_array.cu -o sum_array.out & ./sum_array.out
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 10
__global__ void vecAdd(int* a, int* b, int* c);
void print_array(int* a);
int main(void){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = N - i - 1;
}
printf("a -> "); print_array(a);
printf("b -> "); print_array(b);
printf("c -> "); print_array(c);
int size = N * sizeof(int);
hipMalloc( (void**) &dev_a, size);
hipMalloc( (void**) &dev_b, size);
hipMalloc( (void**) &dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
vecAdd<<<1,N>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
printf("c -> "); print_array(c);
exit (0);
}
__global__ void vecAdd(int* a, int* b, int* c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
void print_array(int* a){
for(int i = 0; i < N; i++){
printf("%d ", a[i]);
}
printf("\n");
} | .text
.file "sum_array.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %r15
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $9, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%r15,%rcx,4)
movl %eax, (%r14,%rcx,4)
incq %rcx
decl %eax
cmpq $10, %rcx
jne .LBB0_1
# %bb.2:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB0_3
# %bb.4: # %_Z11print_arrayPi.exit
movl $10, %edi
callq putchar@PLT
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB0_5
# %bb.6: # %_Z11print_arrayPi.exit26
movl $10, %edi
callq putchar@PLT
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB0_7
# %bb.8: # %_Z11print_arrayPi.exit31
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $40, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_10:
movq (%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq _Z11print_arrayPi
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z11print_arrayPi # -- Begin function _Z11print_arrayPi
.p2align 4, 0x90
.type _Z11print_arrayPi,@function
_Z11print_arrayPi: # @_Z11print_arrayPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_1
# %bb.2:
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z11print_arrayPi, .Lfunc_end1-_Z11print_arrayPi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__vecAddPiS_S_ # -- Begin function _Z21__device_stub__vecAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_S_,@function
_Z21__device_stub__vecAddPiS_S_: # @_Z21__device_stub__vecAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__vecAddPiS_S_, .Lfunc_end2-_Z21__device_stub__vecAddPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a -> "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "b -> "
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "c -> "
.size .L.str.2, 6
.type _Z6vecAddPiS_S_,@object # @_Z6vecAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_S_
.p2align 3, 0x0
_Z6vecAddPiS_S_:
.quad _Z21__device_stub__vecAddPiS_S_
.size _Z6vecAddPiS_S_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPiS_S_
.globl _Z6vecAddPiS_S_
.p2align 8
.type _Z6vecAddPiS_S_,@function
_Z6vecAddPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPiS_S_, .Lfunc_end0-_Z6vecAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001cefd_00000000-6_sum_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPi
.type _Z11print_arrayPi, @function
_Z11print_arrayPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 40(%rdi), %r12
leaq .LC0(%rip), %rbp
.L4:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L4
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11print_arrayPi, .-_Z11print_arrayPi
.globl _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecAddPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.globl _Z6vecAddPiS_S_
.type _Z6vecAddPiS_S_, @function
_Z6vecAddPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6vecAddPiS_S_, .-_Z6vecAddPiS_S_
.section .rodata.str1.1
.LC2:
.string "a -> "
.LC3:
.string "b -> "
.LC4:
.string "c -> "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movl $9, %ecx
.L16:
movl %eax, 0(%rbp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call _Z11print_arrayPi
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call _Z11print_arrayPi
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call _Z11print_arrayPi
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call _Z11print_arrayPi
movl $0, %edi
call exit@PLT
.L21:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
jmp .L17
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6vecAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_array.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %r15
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $9, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%r15,%rcx,4)
movl %eax, (%r14,%rcx,4)
incq %rcx
decl %eax
cmpq $10, %rcx
jne .LBB0_1
# %bb.2:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB0_3
# %bb.4: # %_Z11print_arrayPi.exit
movl $10, %edi
callq putchar@PLT
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB0_5
# %bb.6: # %_Z11print_arrayPi.exit26
movl $10, %edi
callq putchar@PLT
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB0_7
# %bb.8: # %_Z11print_arrayPi.exit31
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $40, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_10:
movq (%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq _Z11print_arrayPi
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z11print_arrayPi # -- Begin function _Z11print_arrayPi
.p2align 4, 0x90
.type _Z11print_arrayPi,@function
_Z11print_arrayPi: # @_Z11print_arrayPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_1
# %bb.2:
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z11print_arrayPi, .Lfunc_end1-_Z11print_arrayPi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__vecAddPiS_S_ # -- Begin function _Z21__device_stub__vecAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_S_,@function
_Z21__device_stub__vecAddPiS_S_: # @_Z21__device_stub__vecAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__vecAddPiS_S_, .Lfunc_end2-_Z21__device_stub__vecAddPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a -> "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "b -> "
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "c -> "
.size .L.str.2, 6
.type _Z6vecAddPiS_S_,@object # @_Z6vecAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_S_
.p2align 3, 0x0
_Z6vecAddPiS_S_:
.quad _Z21__device_stub__vecAddPiS_S_
.size _Z6vecAddPiS_S_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void calc_histogram(char* dbuff, unsigned int* dcount, unsigned int size, float stride) {
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int start_pos = stride * index;
unsigned int stop_pos = start_pos + stride;
unsigned int lcount[10] = { 0 };
if (size < stop_pos) {
stop_pos = size;
}
for (unsigned int i = start_pos; i < stop_pos; i++) {
// Increment counter per occurances
if (dbuff[i] == '0') {
lcount[0] += 1;
} else if (dbuff[i] == '1') {
lcount[1] += 1;
} else if (dbuff[i] == '2') {
lcount[2] += 1;
} else if (dbuff[i] == '3') {
lcount[3] += 1;
} else if (dbuff[i] == '4') {
lcount[4] += 1;
} else if (dbuff[i] == '5') {
lcount[5] += 1;
} else if (dbuff[i] == '6') {
lcount[6] += 1;
} else if (dbuff[i] == '7') {
lcount[7] += 1;
} else if (dbuff[i] == '8') {
lcount[8] += 1;
} else if (dbuff[i] == '9') {
lcount[9] += 1;
}
}
__syncthreads();
dcount[0] += lcount[0];
dcount[1] += lcount[1];
dcount[2] += lcount[2];
dcount[3] += lcount[3];
dcount[4] += lcount[4];
dcount[5] += lcount[5];
dcount[6] += lcount[6];
dcount[7] += lcount[7];
dcount[8] += lcount[8];
dcount[9] += lcount[9];
} | code for sm_80
Function : _Z14calc_histogramPcPjjf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B1, 0xb60 ; /* 0x00000b2000017945 */
/* 0x000fe20003800000 */
/*0040*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0070*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0080*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fc400078e00ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fcc00078e0203 */
/*00c0*/ I2F.U32 R2, R2 ; /* 0x0000000200027306 */
/* 0x000e240000201000 */
/*00d0*/ FMUL R3, R2, c[0x0][0x174] ; /* 0x00005d0002037a20 */
/* 0x001fcc0000400000 */
/*00e0*/ F2I.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f000 */
/*00f0*/ I2F.U32 R0, R3 ; /* 0x0000000300007306 */
/* 0x001e240000201000 */
/*0100*/ FADD R11, R0, c[0x0][0x174] ; /* 0x00005d00000b7621 */
/* 0x001fc40000000000 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc800078e00ff */
/*0120*/ F2I.U32.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e24000020f000 */
/*0130*/ IMNMX.U32 R13, R11, c[0x0][0x170], PT ; /* 0x00005c000b0d7a17 */
/* 0x001fc80003800000 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R13, R3, PT ; /* 0x000000030d00720c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0xb50 ; /* 0x000009f000008947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0003 */
/*0170*/ LOP3.LUT R0, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff007212 */
/* 0x000fe200078e33ff */
/*0180*/ BSSY B0, 0x830 ; /* 0x000006a000007945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*01a0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*01b0*/ IADD3 R5, -R2, -0x2, RZ ; /* 0xfffffffe02057810 */
/* 0x000fe20007ffe1ff */
/*01c0*/ IMAD.IADD R13, R13, 0x1, -R2 ; /* 0x000000010d0d7824 */
/* 0x000fe200078e0a02 */
/*01d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01e0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*01f0*/ ISETP.NE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f05270 */
/*0200*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0210*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0220*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0230*/ LOP3.LUT R16, R13, 0x1, RZ, 0xc0, !PT ; /* 0x000000010d107812 */
/* 0x000fd200078ec0ff */
/*0240*/ @!P0 BRA 0x820 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R13, R13, 0x1, -R16 ; /* 0x000000010d0d7824 */
/* 0x000fe400078e0a10 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0270*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fca0007f1e0ff */
/*0280*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fca00000e06ff */
/*0290*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*02a0*/ IADD3 R13, R13, -0x2, RZ ; /* 0xfffffffe0d0d7810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ BSSY B2, 0x540 ; /* 0x0000028000027945 */
/* 0x000fe60003800000 */
/*02c0*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f05270 */
/*02d0*/ ISETP.NE.AND P1, PT, R4, 0x30, PT ; /* 0x000000300400780c */
/* 0x004fda0003f25270 */
/*02e0*/ @!P1 BRA 0x520 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*02f0*/ ISETP.NE.AND P1, PT, R4, 0x31, PT ; /* 0x000000310400780c */
/* 0x000fda0003f25270 */
/*0300*/ @!P1 BRA 0x500 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.NE.AND P1, PT, R4, 0x32, PT ; /* 0x000000320400780c */
/* 0x000fda0003f25270 */
/*0320*/ @!P1 BRA 0x4e0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0330*/ ISETP.NE.AND P1, PT, R4, 0x33, PT ; /* 0x000000330400780c */
/* 0x000fda0003f25270 */
/*0340*/ @!P1 BRA 0x4c0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0350*/ ISETP.NE.AND P1, PT, R4, 0x34, PT ; /* 0x000000340400780c */
/* 0x000fda0003f25270 */
/*0360*/ @!P1 BRA 0x4a0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.NE.AND P1, PT, R4, 0x35, PT ; /* 0x000000350400780c */
/* 0x000fda0003f25270 */
/*0380*/ @!P1 BRA 0x480 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.NE.AND P1, PT, R4, 0x36, PT ; /* 0x000000360400780c */
/* 0x000fda0003f25270 */
/*03a0*/ @!P1 BRA 0x460 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.NE.AND P1, PT, R4, 0x37, PT ; /* 0x000000370400780c */
/* 0x000fda0003f25270 */
/*03c0*/ @!P1 BRA 0x440 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*03d0*/ ISETP.NE.AND P1, PT, R4, 0x38, PT ; /* 0x000000380400780c */
/* 0x000fc80003f25270 */
/*03e0*/ ISETP.NE.AND P2, PT, R4, 0x39, P1 ; /* 0x000000390400780c */
/* 0x000fd20000f45270 */
/*03f0*/ @P1 IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100041810 */
/* 0x000fe40007ffe0ff */
/*0400*/ @!P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106069810 */
/* 0x000fe40007ffe0ff */
/*0410*/ @P2 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff042224 */
/* 0x000fc800078e0200 */
/*0420*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff001224 */
/* 0x000fe200078e0004 */
/*0430*/ BRA 0x530 ; /* 0x000000f000007947 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0450*/ BRA 0x530 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0470*/ BRA 0x530 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*0490*/ BRA 0x530 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*04a0*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ BRA 0x530 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ BRA 0x530 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*04e0*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*04f0*/ BRA 0x530 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0500*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*0510*/ BRA 0x530 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*0530*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0540*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fc80007ffe0ff */
/*0550*/ IADD3 R4, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fca0007f3e0ff */
/*0560*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff057624 */
/* 0x000fca00008e06ff */
/*0570*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0580*/ BSSY B2, 0x800 ; /* 0x0000027000027945 */
/* 0x000fe20003800000 */
/*0590*/ ISETP.NE.AND P1, PT, R4, 0x30, PT ; /* 0x000000300400780c */
/* 0x004fda0003f25270 */
/*05a0*/ @!P1 BRA 0x7e0 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.NE.AND P1, PT, R4, 0x31, PT ; /* 0x000000310400780c */
/* 0x000fda0003f25270 */
/*05c0*/ @!P1 BRA 0x7c0 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.NE.AND P1, PT, R4, 0x32, PT ; /* 0x000000320400780c */
/* 0x000fda0003f25270 */
/*05e0*/ @!P1 BRA 0x7a0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.NE.AND P1, PT, R4, 0x33, PT ; /* 0x000000330400780c */
/* 0x000fda0003f25270 */
/*0600*/ @!P1 BRA 0x780 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.NE.AND P1, PT, R4, 0x34, PT ; /* 0x000000340400780c */
/* 0x000fda0003f25270 */
/*0620*/ @!P1 BRA 0x760 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.NE.AND P1, PT, R4, 0x35, PT ; /* 0x000000350400780c */
/* 0x000fda0003f25270 */
/*0640*/ @!P1 BRA 0x740 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.NE.AND P1, PT, R4, 0x36, PT ; /* 0x000000360400780c */
/* 0x000fda0003f25270 */
/*0660*/ @!P1 BRA 0x720 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.NE.AND P1, PT, R4, 0x37, PT ; /* 0x000000370400780c */
/* 0x000fda0003f25270 */
/*0680*/ @!P1 BRA 0x700 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.NE.AND P1, PT, R4, 0x38, PT ; /* 0x000000380400780c */
/* 0x000fc80003f25270 */
/*06a0*/ ISETP.NE.AND P2, PT, R4, 0x39, P1 ; /* 0x000000390400780c */
/* 0x000fd20000f45270 */
/*06b0*/ @P1 IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100041810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ @!P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106069810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ @P2 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff042224 */
/* 0x000fc800078e0200 */
/*06e0*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff001224 */
/* 0x000fe200078e0004 */
/*06f0*/ BRA 0x7f0 ; /* 0x000000f000007947 */
/* 0x000fea0003800000 */
/*0700*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0710*/ BRA 0x7f0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0720*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0730*/ BRA 0x7f0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*0750*/ BRA 0x7f0 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0760*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe20007ffe0ff */
/*0770*/ BRA 0x7f0 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*0790*/ BRA 0x7f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07a0*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ BRA 0x7f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07c0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ BRA 0x7f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07e0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0800*/ IADD3 R2, R2, 0x2, RZ ; /* 0x0000000202027810 */
/* 0x000fe20007ffe0ff */
/*0810*/ @P0 BRA 0x270 ; /* 0xfffffa5000000947 */
/* 0x000fea000383ffff */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0006 */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*0860*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, R12 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000c */
/*0880*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000e */
/*0890*/ IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000b */
/*08a0*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0003 */
/*08b0*/ @!P0 BRA 0xb50 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*08c0*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fca0007f1e0ff */
/*08d0*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*08e0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*08f0*/ ISETP.NE.AND P0, PT, R2, 0x30, PT ; /* 0x000000300200780c */
/* 0x004fda0003f05270 */
/*0900*/ @!P0 BRA 0xb40 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0910*/ ISETP.NE.AND P0, PT, R2, 0x31, PT ; /* 0x000000310200780c */
/* 0x000fda0003f05270 */
/*0920*/ @!P0 BRA 0xb20 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.NE.AND P0, PT, R2, 0x32, PT ; /* 0x000000320200780c */
/* 0x000fda0003f05270 */
/*0940*/ @!P0 BRA 0xb00 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.NE.AND P0, PT, R2, 0x33, PT ; /* 0x000000330200780c */
/* 0x000fda0003f05270 */
/*0960*/ @!P0 BRA 0xae0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0970*/ ISETP.NE.AND P0, PT, R2, 0x34, PT ; /* 0x000000340200780c */
/* 0x000fda0003f05270 */
/*0980*/ @!P0 BRA 0xac0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0990*/ ISETP.NE.AND P0, PT, R2, 0x35, PT ; /* 0x000000350200780c */
/* 0x000fda0003f05270 */
/*09a0*/ @!P0 BRA 0xaa0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.NE.AND P0, PT, R2, 0x36, PT ; /* 0x000000360200780c */
/* 0x000fda0003f05270 */
/*09c0*/ @!P0 BRA 0xa80 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*09d0*/ ISETP.NE.AND P0, PT, R2, 0x37, PT ; /* 0x000000370200780c */
/* 0x000fda0003f05270 */
/*09e0*/ @!P0 BRA 0xa60 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*09f0*/ ISETP.NE.AND P0, PT, R2, 0x38, PT ; /* 0x000000380200780c */
/* 0x000fc80003f05270 */
/*0a00*/ ISETP.NE.AND P1, PT, R2, 0x39, P0 ; /* 0x000000390200780c */
/* 0x000fd20000725270 */
/*0a10*/ @P0 IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100020810 */
/* 0x000fe40007ffe0ff */
/*0a20*/ @!P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104048810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ @P1 IMAD.MOV R2, RZ, RZ, R0 ; /* 0x000000ffff021224 */
/* 0x000fc800078e0200 */
/*0a40*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff000224 */
/* 0x000fe200078e0002 */
/*0a50*/ BRA 0xb50 ; /* 0x000000f000007947 */
/* 0x000fea0003800000 */
/*0a60*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ BRA 0xb50 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0a80*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ BRA 0xb50 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ BRA 0xb50 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0ac0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ BRA 0xb50 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*0af0*/ BRA 0xb50 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b00*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*0b10*/ BRA 0xb50 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*0b30*/ BRA 0xb50 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b40*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b70*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0b80*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0b90*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x000ee8000c1e1900 */
/*0bb0*/ LDG.E R19, [R2.64+0x8] ; /* 0x0000080402137981 */
/* 0x000f28000c1e1900 */
/*0bc0*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000f68000c1e1900 */
/*0bd0*/ LDG.E R21, [R2.64+0x10] ; /* 0x0000100402157981 */
/* 0x000f68000c1e1900 */
/*0be0*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000f68000c1e1900 */
/*0bf0*/ LDG.E R23, [R2.64+0x18] ; /* 0x0000180402177981 */
/* 0x000f68000c1e1900 */
/*0c00*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000f68000c1e1900 */
/*0c10*/ LDG.E R13, [R2.64+0x20] ; /* 0x00002004020d7981 */
/* 0x000f68000c1e1900 */
/*0c20*/ LDG.E R11, [R2.64+0x24] ; /* 0x00002404020b7981 */
/* 0x000f62000c1e1900 */
/*0c30*/ IMAD.IADD R15, R14, 0x1, R15 ; /* 0x000000010e0f7824 */
/* 0x004fc400078e020f */
/*0c40*/ IMAD.IADD R17, R17, 0x1, R12 ; /* 0x0000000111117824 */
/* 0x008fc600078e020c */
/*0c50*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0c60*/ IMAD.IADD R19, R19, 0x1, R10 ; /* 0x0000000113137824 */
/* 0x010fc600078e020a */
/*0c70*/ STG.E [R2.64+0x4], R17 ; /* 0x0000041102007986 */
/* 0x000fe2000c101904 */
/*0c80*/ IMAD.IADD R9, R16, 0x1, R9 ; /* 0x0000000110097824 */
/* 0x020fc600078e0209 */
/*0c90*/ STG.E [R2.64+0x8], R19 ; /* 0x0000081302007986 */
/* 0x000fe2000c101904 */
/*0ca0*/ IMAD.IADD R21, R21, 0x1, R8 ; /* 0x0000000115157824 */
/* 0x000fc600078e0208 */
/*0cb0*/ STG.E [R2.64+0xc], R9 ; /* 0x00000c0902007986 */
/* 0x000fe2000c101904 */
/*0cc0*/ IMAD.IADD R7, R18, 0x1, R7 ; /* 0x0000000112077824 */
/* 0x000fc600078e0207 */
/*0cd0*/ STG.E [R2.64+0x10], R21 ; /* 0x0000101502007986 */
/* 0x000fe2000c101904 */
/*0ce0*/ IMAD.IADD R23, R23, 0x1, R6 ; /* 0x0000000117177824 */
/* 0x000fc600078e0206 */
/*0cf0*/ STG.E [R2.64+0x14], R7 ; /* 0x0000140702007986 */
/* 0x000fe2000c101904 */
/*0d00*/ IMAD.IADD R5, R20, 0x1, R5 ; /* 0x0000000114057824 */
/* 0x000fc600078e0205 */
/*0d10*/ STG.E [R2.64+0x18], R23 ; /* 0x0000181702007986 */
/* 0x000fe2000c101904 */
/*0d20*/ IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d7824 */
/* 0x000fc600078e0204 */
/*0d30*/ STG.E [R2.64+0x1c], R5 ; /* 0x00001c0502007986 */
/* 0x000fe2000c101904 */
/*0d40*/ IMAD.IADD R11, R11, 0x1, R0 ; /* 0x000000010b0b7824 */
/* 0x000fc600078e0200 */
/*0d50*/ STG.E [R2.64+0x20], R13 ; /* 0x0000200d02007986 */
/* 0x000fe8000c101904 */
/*0d60*/ STG.E [R2.64+0x24], R11 ; /* 0x0000240b02007986 */
/* 0x000fe2000c101904 */
/*0d70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d80*/ BRA 0xd80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void calc_histogram(char* dbuff, unsigned int* dcount, unsigned int size, float stride) {
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int start_pos = stride * index;
unsigned int stop_pos = start_pos + stride;
unsigned int lcount[10] = { 0 };
if (size < stop_pos) {
stop_pos = size;
}
for (unsigned int i = start_pos; i < stop_pos; i++) {
// Increment counter per occurances
if (dbuff[i] == '0') {
lcount[0] += 1;
} else if (dbuff[i] == '1') {
lcount[1] += 1;
} else if (dbuff[i] == '2') {
lcount[2] += 1;
} else if (dbuff[i] == '3') {
lcount[3] += 1;
} else if (dbuff[i] == '4') {
lcount[4] += 1;
} else if (dbuff[i] == '5') {
lcount[5] += 1;
} else if (dbuff[i] == '6') {
lcount[6] += 1;
} else if (dbuff[i] == '7') {
lcount[7] += 1;
} else if (dbuff[i] == '8') {
lcount[8] += 1;
} else if (dbuff[i] == '9') {
lcount[9] += 1;
}
}
__syncthreads();
dcount[0] += lcount[0];
dcount[1] += lcount[1];
dcount[2] += lcount[2];
dcount[3] += lcount[3];
dcount[4] += lcount[4];
dcount[5] += lcount[5];
dcount[6] += lcount[6];
dcount[7] += lcount[7];
dcount[8] += lcount[8];
dcount[9] += lcount[9];
} | .file "tmpxft_000c51e2_00000000-6_calc_histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf
.type _Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf, @function
_Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14calc_histogramPcPjjf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf, .-_Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf
.globl _Z14calc_histogramPcPjjf
.type _Z14calc_histogramPcPjjf, @function
_Z14calc_histogramPcPjjf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14calc_histogramPcPjjf, .-_Z14calc_histogramPcPjjf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14calc_histogramPcPjjf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14calc_histogramPcPjjf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void calc_histogram(char* dbuff, unsigned int* dcount, unsigned int size, float stride) {
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int start_pos = stride * index;
unsigned int stop_pos = start_pos + stride;
unsigned int lcount[10] = { 0 };
if (size < stop_pos) {
stop_pos = size;
}
for (unsigned int i = start_pos; i < stop_pos; i++) {
// Increment counter per occurances
if (dbuff[i] == '0') {
lcount[0] += 1;
} else if (dbuff[i] == '1') {
lcount[1] += 1;
} else if (dbuff[i] == '2') {
lcount[2] += 1;
} else if (dbuff[i] == '3') {
lcount[3] += 1;
} else if (dbuff[i] == '4') {
lcount[4] += 1;
} else if (dbuff[i] == '5') {
lcount[5] += 1;
} else if (dbuff[i] == '6') {
lcount[6] += 1;
} else if (dbuff[i] == '7') {
lcount[7] += 1;
} else if (dbuff[i] == '8') {
lcount[8] += 1;
} else if (dbuff[i] == '9') {
lcount[9] += 1;
}
}
__syncthreads();
dcount[0] += lcount[0];
dcount[1] += lcount[1];
dcount[2] += lcount[2];
dcount[3] += lcount[3];
dcount[4] += lcount[4];
dcount[5] += lcount[5];
dcount[6] += lcount[6];
dcount[7] += lcount[7];
dcount[8] += lcount[8];
dcount[9] += lcount[9];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calc_histogram(char* dbuff, unsigned int* dcount, unsigned int size, float stride) {
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int start_pos = stride * index;
unsigned int stop_pos = start_pos + stride;
unsigned int lcount[10] = { 0 };
if (size < stop_pos) {
stop_pos = size;
}
for (unsigned int i = start_pos; i < stop_pos; i++) {
// Increment counter per occurances
if (dbuff[i] == '0') {
lcount[0] += 1;
} else if (dbuff[i] == '1') {
lcount[1] += 1;
} else if (dbuff[i] == '2') {
lcount[2] += 1;
} else if (dbuff[i] == '3') {
lcount[3] += 1;
} else if (dbuff[i] == '4') {
lcount[4] += 1;
} else if (dbuff[i] == '5') {
lcount[5] += 1;
} else if (dbuff[i] == '6') {
lcount[6] += 1;
} else if (dbuff[i] == '7') {
lcount[7] += 1;
} else if (dbuff[i] == '8') {
lcount[8] += 1;
} else if (dbuff[i] == '9') {
lcount[9] += 1;
}
}
__syncthreads();
dcount[0] += lcount[0];
dcount[1] += lcount[1];
dcount[2] += lcount[2];
dcount[3] += lcount[3];
dcount[4] += lcount[4];
dcount[5] += lcount[5];
dcount[6] += lcount[6];
dcount[7] += lcount[7];
dcount[8] += lcount[8];
dcount[9] += lcount[9];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calc_histogram(char* dbuff, unsigned int* dcount, unsigned int size, float stride) {
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int start_pos = stride * index;
unsigned int stop_pos = start_pos + stride;
unsigned int lcount[10] = { 0 };
if (size < stop_pos) {
stop_pos = size;
}
for (unsigned int i = start_pos; i < stop_pos; i++) {
// Increment counter per occurances
if (dbuff[i] == '0') {
lcount[0] += 1;
} else if (dbuff[i] == '1') {
lcount[1] += 1;
} else if (dbuff[i] == '2') {
lcount[2] += 1;
} else if (dbuff[i] == '3') {
lcount[3] += 1;
} else if (dbuff[i] == '4') {
lcount[4] += 1;
} else if (dbuff[i] == '5') {
lcount[5] += 1;
} else if (dbuff[i] == '6') {
lcount[6] += 1;
} else if (dbuff[i] == '7') {
lcount[7] += 1;
} else if (dbuff[i] == '8') {
lcount[8] += 1;
} else if (dbuff[i] == '9') {
lcount[9] += 1;
}
}
__syncthreads();
dcount[0] += lcount[0];
dcount[1] += lcount[1];
dcount[2] += lcount[2];
dcount[3] += lcount[3];
dcount[4] += lcount[4];
dcount[5] += lcount[5];
dcount[6] += lcount[6];
dcount[7] += lcount[7];
dcount[8] += lcount[8];
dcount[9] += lcount[9];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14calc_histogramPcPjjf
.globl _Z14calc_histogramPcPjjf
.p2align 8
.type _Z14calc_histogramPcPjjf,@function
_Z14calc_histogramPcPjjf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v4, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
s_mov_b32 s5, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cvt_f32_u32_e32 v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, s3, v0
v_cvt_u32_f32_e32 v10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, v10
v_dual_add_f32 v1, s3, v0 :: v_dual_mov_b32 v0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v5, v1
v_mov_b32_e32 v1, 0
v_min_u32_e32 v11, s2, v5
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 v11, v10
s_cbranch_execz .LBB0_44
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v1, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v8, 0
s_branch .LBB0_6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s6
v_add_co_u32 v10, vcc_lo, v10, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_cmp_ge_u32_e32 vcc_lo, v10, v11
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_43
.LBB0_6:
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v12, vcc_lo
s_mov_b32 s6, exec_lo
global_load_u8 v13, v[13:14], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 52, v13
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_26
s_mov_b32 s7, exec_lo
v_cmpx_lt_i16_e32 54, v13
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_19
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 55, v13
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_16
s_mov_b32 s9, exec_lo
v_cmpx_lt_i16_e32 56, v13
s_xor_b32 s9, exec_lo, s9
s_cbranch_execz .LBB0_13
s_mov_b32 s10, exec_lo
v_cmpx_eq_u16_e32 57, v13
v_add_nc_u32_e32 v0, 1, v0
s_or_b32 exec_lo, exec_lo, s10
.LBB0_13:
s_and_not1_saveexec_b32 s9, s9
v_add_nc_u32_e32 v1, 1, v1
s_or_b32 exec_lo, exec_lo, s9
.LBB0_16:
s_and_not1_saveexec_b32 s8, s8
v_add_nc_u32_e32 v2, 1, v2
s_or_b32 exec_lo, exec_lo, s8
.LBB0_19:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_25
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 53, v13
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v3, 1, v3
s_and_not1_saveexec_b32 s8, s8
v_add_nc_u32_e32 v4, 1, v4
s_or_b32 exec_lo, exec_lo, s8
.LBB0_25:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
.LBB0_26:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_5
s_mov_b32 s7, exec_lo
v_cmpx_lt_i16_e32 49, v13
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_37
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 50, v13
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_34
s_mov_b32 s9, exec_lo
v_cmpx_lt_i16_e32 51, v13
s_xor_b32 s9, exec_lo, s9
v_add_nc_u32_e32 v5, 1, v5
s_and_not1_saveexec_b32 s9, s9
v_add_nc_u32_e32 v6, 1, v6
s_or_b32 exec_lo, exec_lo, s9
.LBB0_34:
s_and_not1_saveexec_b32 s8, s8
v_add_nc_u32_e32 v7, 1, v7
s_or_b32 exec_lo, exec_lo, s8
.LBB0_37:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_4
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 48, v13
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v8, 1, v8
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_3
s_mov_b32 s9, exec_lo
v_cmpx_eq_u16_e32 48, v13
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v9, 1, v9
s_branch .LBB0_2
.LBB0_43:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_44:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[8:9], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b256 s[0:7], s[8:9], 0x0
s_load_b64 s[10:11], s[8:9], 0x20
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v10, s1, v8
v_add_nc_u32_e32 v9, s0, v9
v_add_nc_u32_e32 v11, s2, v7
v_add_nc_u32_e32 v12, s3, v6
v_add_nc_u32_e32 v5, s4, v5
v_add_nc_u32_e32 v6, s5, v4
v_add_nc_u32_e32 v7, s6, v3
v_add_nc_u32_e32 v8, s7, v2
v_add_nc_u32_e32 v1, s10, v1
v_add_nc_u32_e32 v2, s11, v0
s_clause 0x2
global_store_b128 v13, v[9:12], s[8:9]
global_store_b128 v13, v[5:8], s[8:9] offset:16
global_store_b64 v13, v[1:2], s[8:9] offset:32
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14calc_histogramPcPjjf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14calc_histogramPcPjjf, .Lfunc_end0-_Z14calc_histogramPcPjjf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14calc_histogramPcPjjf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14calc_histogramPcPjjf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calc_histogram(char* dbuff, unsigned int* dcount, unsigned int size, float stride) {
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int start_pos = stride * index;
unsigned int stop_pos = start_pos + stride;
unsigned int lcount[10] = { 0 };
if (size < stop_pos) {
stop_pos = size;
}
for (unsigned int i = start_pos; i < stop_pos; i++) {
// Increment counter per occurances
if (dbuff[i] == '0') {
lcount[0] += 1;
} else if (dbuff[i] == '1') {
lcount[1] += 1;
} else if (dbuff[i] == '2') {
lcount[2] += 1;
} else if (dbuff[i] == '3') {
lcount[3] += 1;
} else if (dbuff[i] == '4') {
lcount[4] += 1;
} else if (dbuff[i] == '5') {
lcount[5] += 1;
} else if (dbuff[i] == '6') {
lcount[6] += 1;
} else if (dbuff[i] == '7') {
lcount[7] += 1;
} else if (dbuff[i] == '8') {
lcount[8] += 1;
} else if (dbuff[i] == '9') {
lcount[9] += 1;
}
}
__syncthreads();
dcount[0] += lcount[0];
dcount[1] += lcount[1];
dcount[2] += lcount[2];
dcount[3] += lcount[3];
dcount[4] += lcount[4];
dcount[5] += lcount[5];
dcount[6] += lcount[6];
dcount[7] += lcount[7];
dcount[8] += lcount[8];
dcount[9] += lcount[9];
} | .text
.file "calc_histogram.hip"
.globl _Z29__device_stub__calc_histogramPcPjjf # -- Begin function _Z29__device_stub__calc_histogramPcPjjf
.p2align 4, 0x90
.type _Z29__device_stub__calc_histogramPcPjjf,@function
_Z29__device_stub__calc_histogramPcPjjf: # @_Z29__device_stub__calc_histogramPcPjjf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14calc_histogramPcPjjf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__calc_histogramPcPjjf, .Lfunc_end0-_Z29__device_stub__calc_histogramPcPjjf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14calc_histogramPcPjjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14calc_histogramPcPjjf,@object # @_Z14calc_histogramPcPjjf
.section .rodata,"a",@progbits
.globl _Z14calc_histogramPcPjjf
.p2align 3, 0x0
_Z14calc_histogramPcPjjf:
.quad _Z29__device_stub__calc_histogramPcPjjf
.size _Z14calc_histogramPcPjjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14calc_histogramPcPjjf"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__calc_histogramPcPjjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14calc_histogramPcPjjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14calc_histogramPcPjjf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B1, 0xb60 ; /* 0x00000b2000017945 */
/* 0x000fe20003800000 */
/*0040*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0070*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0080*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fc400078e00ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fcc00078e0203 */
/*00c0*/ I2F.U32 R2, R2 ; /* 0x0000000200027306 */
/* 0x000e240000201000 */
/*00d0*/ FMUL R3, R2, c[0x0][0x174] ; /* 0x00005d0002037a20 */
/* 0x001fcc0000400000 */
/*00e0*/ F2I.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f000 */
/*00f0*/ I2F.U32 R0, R3 ; /* 0x0000000300007306 */
/* 0x001e240000201000 */
/*0100*/ FADD R11, R0, c[0x0][0x174] ; /* 0x00005d00000b7621 */
/* 0x001fc40000000000 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc800078e00ff */
/*0120*/ F2I.U32.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e24000020f000 */
/*0130*/ IMNMX.U32 R13, R11, c[0x0][0x170], PT ; /* 0x00005c000b0d7a17 */
/* 0x001fc80003800000 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R13, R3, PT ; /* 0x000000030d00720c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0xb50 ; /* 0x000009f000008947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0003 */
/*0170*/ LOP3.LUT R0, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff007212 */
/* 0x000fe200078e33ff */
/*0180*/ BSSY B0, 0x830 ; /* 0x000006a000007945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*01a0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*01b0*/ IADD3 R5, -R2, -0x2, RZ ; /* 0xfffffffe02057810 */
/* 0x000fe20007ffe1ff */
/*01c0*/ IMAD.IADD R13, R13, 0x1, -R2 ; /* 0x000000010d0d7824 */
/* 0x000fe200078e0a02 */
/*01d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01e0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*01f0*/ ISETP.NE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f05270 */
/*0200*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0210*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0220*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0230*/ LOP3.LUT R16, R13, 0x1, RZ, 0xc0, !PT ; /* 0x000000010d107812 */
/* 0x000fd200078ec0ff */
/*0240*/ @!P0 BRA 0x820 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R13, R13, 0x1, -R16 ; /* 0x000000010d0d7824 */
/* 0x000fe400078e0a10 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0270*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fca0007f1e0ff */
/*0280*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fca00000e06ff */
/*0290*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*02a0*/ IADD3 R13, R13, -0x2, RZ ; /* 0xfffffffe0d0d7810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ BSSY B2, 0x540 ; /* 0x0000028000027945 */
/* 0x000fe60003800000 */
/*02c0*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f05270 */
/*02d0*/ ISETP.NE.AND P1, PT, R4, 0x30, PT ; /* 0x000000300400780c */
/* 0x004fda0003f25270 */
/*02e0*/ @!P1 BRA 0x520 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*02f0*/ ISETP.NE.AND P1, PT, R4, 0x31, PT ; /* 0x000000310400780c */
/* 0x000fda0003f25270 */
/*0300*/ @!P1 BRA 0x500 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.NE.AND P1, PT, R4, 0x32, PT ; /* 0x000000320400780c */
/* 0x000fda0003f25270 */
/*0320*/ @!P1 BRA 0x4e0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0330*/ ISETP.NE.AND P1, PT, R4, 0x33, PT ; /* 0x000000330400780c */
/* 0x000fda0003f25270 */
/*0340*/ @!P1 BRA 0x4c0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0350*/ ISETP.NE.AND P1, PT, R4, 0x34, PT ; /* 0x000000340400780c */
/* 0x000fda0003f25270 */
/*0360*/ @!P1 BRA 0x4a0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.NE.AND P1, PT, R4, 0x35, PT ; /* 0x000000350400780c */
/* 0x000fda0003f25270 */
/*0380*/ @!P1 BRA 0x480 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.NE.AND P1, PT, R4, 0x36, PT ; /* 0x000000360400780c */
/* 0x000fda0003f25270 */
/*03a0*/ @!P1 BRA 0x460 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.NE.AND P1, PT, R4, 0x37, PT ; /* 0x000000370400780c */
/* 0x000fda0003f25270 */
/*03c0*/ @!P1 BRA 0x440 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*03d0*/ ISETP.NE.AND P1, PT, R4, 0x38, PT ; /* 0x000000380400780c */
/* 0x000fc80003f25270 */
/*03e0*/ ISETP.NE.AND P2, PT, R4, 0x39, P1 ; /* 0x000000390400780c */
/* 0x000fd20000f45270 */
/*03f0*/ @P1 IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100041810 */
/* 0x000fe40007ffe0ff */
/*0400*/ @!P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106069810 */
/* 0x000fe40007ffe0ff */
/*0410*/ @P2 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff042224 */
/* 0x000fc800078e0200 */
/*0420*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff001224 */
/* 0x000fe200078e0004 */
/*0430*/ BRA 0x530 ; /* 0x000000f000007947 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0450*/ BRA 0x530 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0470*/ BRA 0x530 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*0490*/ BRA 0x530 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*04a0*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ BRA 0x530 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ BRA 0x530 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*04e0*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*04f0*/ BRA 0x530 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0500*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*0510*/ BRA 0x530 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*0530*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0540*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fc80007ffe0ff */
/*0550*/ IADD3 R4, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fca0007f3e0ff */
/*0560*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff057624 */
/* 0x000fca00008e06ff */
/*0570*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0580*/ BSSY B2, 0x800 ; /* 0x0000027000027945 */
/* 0x000fe20003800000 */
/*0590*/ ISETP.NE.AND P1, PT, R4, 0x30, PT ; /* 0x000000300400780c */
/* 0x004fda0003f25270 */
/*05a0*/ @!P1 BRA 0x7e0 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.NE.AND P1, PT, R4, 0x31, PT ; /* 0x000000310400780c */
/* 0x000fda0003f25270 */
/*05c0*/ @!P1 BRA 0x7c0 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.NE.AND P1, PT, R4, 0x32, PT ; /* 0x000000320400780c */
/* 0x000fda0003f25270 */
/*05e0*/ @!P1 BRA 0x7a0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.NE.AND P1, PT, R4, 0x33, PT ; /* 0x000000330400780c */
/* 0x000fda0003f25270 */
/*0600*/ @!P1 BRA 0x780 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.NE.AND P1, PT, R4, 0x34, PT ; /* 0x000000340400780c */
/* 0x000fda0003f25270 */
/*0620*/ @!P1 BRA 0x760 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.NE.AND P1, PT, R4, 0x35, PT ; /* 0x000000350400780c */
/* 0x000fda0003f25270 */
/*0640*/ @!P1 BRA 0x740 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.NE.AND P1, PT, R4, 0x36, PT ; /* 0x000000360400780c */
/* 0x000fda0003f25270 */
/*0660*/ @!P1 BRA 0x720 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.NE.AND P1, PT, R4, 0x37, PT ; /* 0x000000370400780c */
/* 0x000fda0003f25270 */
/*0680*/ @!P1 BRA 0x700 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.NE.AND P1, PT, R4, 0x38, PT ; /* 0x000000380400780c */
/* 0x000fc80003f25270 */
/*06a0*/ ISETP.NE.AND P2, PT, R4, 0x39, P1 ; /* 0x000000390400780c */
/* 0x000fd20000f45270 */
/*06b0*/ @P1 IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100041810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ @!P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106069810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ @P2 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff042224 */
/* 0x000fc800078e0200 */
/*06e0*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff001224 */
/* 0x000fe200078e0004 */
/*06f0*/ BRA 0x7f0 ; /* 0x000000f000007947 */
/* 0x000fea0003800000 */
/*0700*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0710*/ BRA 0x7f0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0720*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0730*/ BRA 0x7f0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*0750*/ BRA 0x7f0 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0760*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe20007ffe0ff */
/*0770*/ BRA 0x7f0 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*0790*/ BRA 0x7f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07a0*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ BRA 0x7f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07c0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ BRA 0x7f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07e0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0800*/ IADD3 R2, R2, 0x2, RZ ; /* 0x0000000202027810 */
/* 0x000fe20007ffe0ff */
/*0810*/ @P0 BRA 0x270 ; /* 0xfffffa5000000947 */
/* 0x000fea000383ffff */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0006 */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*0860*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, R12 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000c */
/*0880*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000e */
/*0890*/ IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000b */
/*08a0*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0003 */
/*08b0*/ @!P0 BRA 0xb50 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*08c0*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fca0007f1e0ff */
/*08d0*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*08e0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*08f0*/ ISETP.NE.AND P0, PT, R2, 0x30, PT ; /* 0x000000300200780c */
/* 0x004fda0003f05270 */
/*0900*/ @!P0 BRA 0xb40 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0910*/ ISETP.NE.AND P0, PT, R2, 0x31, PT ; /* 0x000000310200780c */
/* 0x000fda0003f05270 */
/*0920*/ @!P0 BRA 0xb20 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.NE.AND P0, PT, R2, 0x32, PT ; /* 0x000000320200780c */
/* 0x000fda0003f05270 */
/*0940*/ @!P0 BRA 0xb00 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.NE.AND P0, PT, R2, 0x33, PT ; /* 0x000000330200780c */
/* 0x000fda0003f05270 */
/*0960*/ @!P0 BRA 0xae0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0970*/ ISETP.NE.AND P0, PT, R2, 0x34, PT ; /* 0x000000340200780c */
/* 0x000fda0003f05270 */
/*0980*/ @!P0 BRA 0xac0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0990*/ ISETP.NE.AND P0, PT, R2, 0x35, PT ; /* 0x000000350200780c */
/* 0x000fda0003f05270 */
/*09a0*/ @!P0 BRA 0xaa0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.NE.AND P0, PT, R2, 0x36, PT ; /* 0x000000360200780c */
/* 0x000fda0003f05270 */
/*09c0*/ @!P0 BRA 0xa80 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*09d0*/ ISETP.NE.AND P0, PT, R2, 0x37, PT ; /* 0x000000370200780c */
/* 0x000fda0003f05270 */
/*09e0*/ @!P0 BRA 0xa60 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*09f0*/ ISETP.NE.AND P0, PT, R2, 0x38, PT ; /* 0x000000380200780c */
/* 0x000fc80003f05270 */
/*0a00*/ ISETP.NE.AND P1, PT, R2, 0x39, P0 ; /* 0x000000390200780c */
/* 0x000fd20000725270 */
/*0a10*/ @P0 IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100020810 */
/* 0x000fe40007ffe0ff */
/*0a20*/ @!P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104048810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ @P1 IMAD.MOV R2, RZ, RZ, R0 ; /* 0x000000ffff021224 */
/* 0x000fc800078e0200 */
/*0a40*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff000224 */
/* 0x000fe200078e0002 */
/*0a50*/ BRA 0xb50 ; /* 0x000000f000007947 */
/* 0x000fea0003800000 */
/*0a60*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ BRA 0xb50 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0a80*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ BRA 0xb50 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ BRA 0xb50 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0ac0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ BRA 0xb50 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*0af0*/ BRA 0xb50 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b00*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*0b10*/ BRA 0xb50 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*0b30*/ BRA 0xb50 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b40*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b70*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0b80*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0b90*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x000ee8000c1e1900 */
/*0bb0*/ LDG.E R19, [R2.64+0x8] ; /* 0x0000080402137981 */
/* 0x000f28000c1e1900 */
/*0bc0*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000f68000c1e1900 */
/*0bd0*/ LDG.E R21, [R2.64+0x10] ; /* 0x0000100402157981 */
/* 0x000f68000c1e1900 */
/*0be0*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000f68000c1e1900 */
/*0bf0*/ LDG.E R23, [R2.64+0x18] ; /* 0x0000180402177981 */
/* 0x000f68000c1e1900 */
/*0c00*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000f68000c1e1900 */
/*0c10*/ LDG.E R13, [R2.64+0x20] ; /* 0x00002004020d7981 */
/* 0x000f68000c1e1900 */
/*0c20*/ LDG.E R11, [R2.64+0x24] ; /* 0x00002404020b7981 */
/* 0x000f62000c1e1900 */
/*0c30*/ IMAD.IADD R15, R14, 0x1, R15 ; /* 0x000000010e0f7824 */
/* 0x004fc400078e020f */
/*0c40*/ IMAD.IADD R17, R17, 0x1, R12 ; /* 0x0000000111117824 */
/* 0x008fc600078e020c */
/*0c50*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0c60*/ IMAD.IADD R19, R19, 0x1, R10 ; /* 0x0000000113137824 */
/* 0x010fc600078e020a */
/*0c70*/ STG.E [R2.64+0x4], R17 ; /* 0x0000041102007986 */
/* 0x000fe2000c101904 */
/*0c80*/ IMAD.IADD R9, R16, 0x1, R9 ; /* 0x0000000110097824 */
/* 0x020fc600078e0209 */
/*0c90*/ STG.E [R2.64+0x8], R19 ; /* 0x0000081302007986 */
/* 0x000fe2000c101904 */
/*0ca0*/ IMAD.IADD R21, R21, 0x1, R8 ; /* 0x0000000115157824 */
/* 0x000fc600078e0208 */
/*0cb0*/ STG.E [R2.64+0xc], R9 ; /* 0x00000c0902007986 */
/* 0x000fe2000c101904 */
/*0cc0*/ IMAD.IADD R7, R18, 0x1, R7 ; /* 0x0000000112077824 */
/* 0x000fc600078e0207 */
/*0cd0*/ STG.E [R2.64+0x10], R21 ; /* 0x0000101502007986 */
/* 0x000fe2000c101904 */
/*0ce0*/ IMAD.IADD R23, R23, 0x1, R6 ; /* 0x0000000117177824 */
/* 0x000fc600078e0206 */
/*0cf0*/ STG.E [R2.64+0x14], R7 ; /* 0x0000140702007986 */
/* 0x000fe2000c101904 */
/*0d00*/ IMAD.IADD R5, R20, 0x1, R5 ; /* 0x0000000114057824 */
/* 0x000fc600078e0205 */
/*0d10*/ STG.E [R2.64+0x18], R23 ; /* 0x0000181702007986 */
/* 0x000fe2000c101904 */
/*0d20*/ IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d7824 */
/* 0x000fc600078e0204 */
/*0d30*/ STG.E [R2.64+0x1c], R5 ; /* 0x00001c0502007986 */
/* 0x000fe2000c101904 */
/*0d40*/ IMAD.IADD R11, R11, 0x1, R0 ; /* 0x000000010b0b7824 */
/* 0x000fc600078e0200 */
/*0d50*/ STG.E [R2.64+0x20], R13 ; /* 0x0000200d02007986 */
/* 0x000fe8000c101904 */
/*0d60*/ STG.E [R2.64+0x24], R11 ; /* 0x0000240b02007986 */
/* 0x000fe2000c101904 */
/*0d70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d80*/ BRA 0xd80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14calc_histogramPcPjjf
.globl _Z14calc_histogramPcPjjf
.p2align 8
.type _Z14calc_histogramPcPjjf,@function
_Z14calc_histogramPcPjjf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v4, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
s_mov_b32 s5, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cvt_f32_u32_e32 v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, s3, v0
v_cvt_u32_f32_e32 v10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, v10
v_dual_add_f32 v1, s3, v0 :: v_dual_mov_b32 v0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v5, v1
v_mov_b32_e32 v1, 0
v_min_u32_e32 v11, s2, v5
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 v11, v10
s_cbranch_execz .LBB0_44
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v1, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v8, 0
s_branch .LBB0_6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s6
v_add_co_u32 v10, vcc_lo, v10, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_cmp_ge_u32_e32 vcc_lo, v10, v11
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_43
.LBB0_6:
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v12, vcc_lo
s_mov_b32 s6, exec_lo
global_load_u8 v13, v[13:14], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 52, v13
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_26
s_mov_b32 s7, exec_lo
v_cmpx_lt_i16_e32 54, v13
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_19
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 55, v13
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_16
s_mov_b32 s9, exec_lo
v_cmpx_lt_i16_e32 56, v13
s_xor_b32 s9, exec_lo, s9
s_cbranch_execz .LBB0_13
s_mov_b32 s10, exec_lo
v_cmpx_eq_u16_e32 57, v13
v_add_nc_u32_e32 v0, 1, v0
s_or_b32 exec_lo, exec_lo, s10
.LBB0_13:
s_and_not1_saveexec_b32 s9, s9
v_add_nc_u32_e32 v1, 1, v1
s_or_b32 exec_lo, exec_lo, s9
.LBB0_16:
s_and_not1_saveexec_b32 s8, s8
v_add_nc_u32_e32 v2, 1, v2
s_or_b32 exec_lo, exec_lo, s8
.LBB0_19:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_25
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 53, v13
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v3, 1, v3
s_and_not1_saveexec_b32 s8, s8
v_add_nc_u32_e32 v4, 1, v4
s_or_b32 exec_lo, exec_lo, s8
.LBB0_25:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
.LBB0_26:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_5
s_mov_b32 s7, exec_lo
v_cmpx_lt_i16_e32 49, v13
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_37
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 50, v13
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_34
s_mov_b32 s9, exec_lo
v_cmpx_lt_i16_e32 51, v13
s_xor_b32 s9, exec_lo, s9
v_add_nc_u32_e32 v5, 1, v5
s_and_not1_saveexec_b32 s9, s9
v_add_nc_u32_e32 v6, 1, v6
s_or_b32 exec_lo, exec_lo, s9
.LBB0_34:
s_and_not1_saveexec_b32 s8, s8
v_add_nc_u32_e32 v7, 1, v7
s_or_b32 exec_lo, exec_lo, s8
.LBB0_37:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_4
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 48, v13
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v8, 1, v8
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_3
s_mov_b32 s9, exec_lo
v_cmpx_eq_u16_e32 48, v13
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v9, 1, v9
s_branch .LBB0_2
.LBB0_43:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_44:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[8:9], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b256 s[0:7], s[8:9], 0x0
s_load_b64 s[10:11], s[8:9], 0x20
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v10, s1, v8
v_add_nc_u32_e32 v9, s0, v9
v_add_nc_u32_e32 v11, s2, v7
v_add_nc_u32_e32 v12, s3, v6
v_add_nc_u32_e32 v5, s4, v5
v_add_nc_u32_e32 v6, s5, v4
v_add_nc_u32_e32 v7, s6, v3
v_add_nc_u32_e32 v8, s7, v2
v_add_nc_u32_e32 v1, s10, v1
v_add_nc_u32_e32 v2, s11, v0
s_clause 0x2
global_store_b128 v13, v[9:12], s[8:9]
global_store_b128 v13, v[5:8], s[8:9] offset:16
global_store_b64 v13, v[1:2], s[8:9] offset:32
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14calc_histogramPcPjjf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14calc_histogramPcPjjf, .Lfunc_end0-_Z14calc_histogramPcPjjf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14calc_histogramPcPjjf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14calc_histogramPcPjjf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c51e2_00000000-6_calc_histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf
.type _Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf, @function
_Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14calc_histogramPcPjjf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf, .-_Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf
.globl _Z14calc_histogramPcPjjf
.type _Z14calc_histogramPcPjjf, @function
_Z14calc_histogramPcPjjf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14calc_histogramPcPjjfPcPjjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14calc_histogramPcPjjf, .-_Z14calc_histogramPcPjjf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14calc_histogramPcPjjf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14calc_histogramPcPjjf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calc_histogram.hip"
.globl _Z29__device_stub__calc_histogramPcPjjf # -- Begin function _Z29__device_stub__calc_histogramPcPjjf
.p2align 4, 0x90
.type _Z29__device_stub__calc_histogramPcPjjf,@function
_Z29__device_stub__calc_histogramPcPjjf: # @_Z29__device_stub__calc_histogramPcPjjf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14calc_histogramPcPjjf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__calc_histogramPcPjjf, .Lfunc_end0-_Z29__device_stub__calc_histogramPcPjjf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14calc_histogramPcPjjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14calc_histogramPcPjjf,@object # @_Z14calc_histogramPcPjjf
.section .rodata,"a",@progbits
.globl _Z14calc_histogramPcPjjf
.p2align 3, 0x0
_Z14calc_histogramPcPjjf:
.quad _Z29__device_stub__calc_histogramPcPjjf
.size _Z14calc_histogramPcPjjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14calc_histogramPcPjjf"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__calc_histogramPcPjjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14calc_histogramPcPjjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float* var_23,float var_24,float var_25,float var_26,float var_27,float var_28) {
if (comp >= +1.8035E-44f * var_1 - ldexpf(sinhf(+1.7007E6f), 2)) {
float tmp_1 = var_3 + -1.2161E24f;
comp = tmp_1 + var_4 / powf(coshf(sinhf(+1.0028E36f + (+1.4320E35f - var_5 / (var_6 + var_7)))), (-1.2913E35f / -1.0767E25f - sinf(var_8 + var_9)));
if (comp > (-1.9370E36f / coshf((var_10 + var_11)))) {
comp = var_12 * logf(var_13 / (var_14 + var_15 / -1.0214E-44f));
comp += var_16 * (var_17 / (var_18 * log10f(-1.8316E36f + var_19 / (var_20 * (var_21 - var_22)))));
}
for (int i=0; i < var_2; ++i) {
var_23[i] = (var_24 * fabsf(+1.6748E-43f));
comp += var_23[i] * log10f((+1.8275E-35f * +1.5333E34f));
}
if (comp == -1.2292E35f / (+1.4097E-14f * -1.3440E-43f / fabsf(var_25 - var_26 + +1.1116E-37f))) {
comp = (var_27 - logf(+1.7451E8f));
comp += (+1.0251E-44f * var_28);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float* tmp_24 = initPointer( atof(argv[24]) );
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0019e6a2_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff
.type _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff, @function
_Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $360, %rsp
.cfi_def_cfa_offset 368
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movl %edi, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 368(%rsp), %rax
movq %rax, 184(%rsp)
leaq 376(%rsp), %rax
movq %rax, 192(%rsp)
leaq 384(%rsp), %rax
movq %rax, 200(%rsp)
leaq 392(%rsp), %rax
movq %rax, 208(%rsp)
leaq 400(%rsp), %rax
movq %rax, 216(%rsp)
leaq 408(%rsp), %rax
movq %rax, 224(%rsp)
leaq 416(%rsp), %rax
movq %rax, 232(%rsp)
leaq 424(%rsp), %rax
movq %rax, 240(%rsp)
leaq 432(%rsp), %rax
movq %rax, 248(%rsp)
leaq 440(%rsp), %rax
movq %rax, 256(%rsp)
leaq 448(%rsp), %rax
movq %rax, 264(%rsp)
leaq 456(%rsp), %rax
movq %rax, 272(%rsp)
leaq 464(%rsp), %rax
movq %rax, 280(%rsp)
leaq 472(%rsp), %rax
movq %rax, 288(%rsp)
movq %rsp, %rax
movq %rax, 296(%rsp)
leaq 480(%rsp), %rax
movq %rax, 304(%rsp)
leaq 488(%rsp), %rax
movq %rax, 312(%rsp)
leaq 496(%rsp), %rax
movq %rax, 320(%rsp)
leaq 504(%rsp), %rax
movq %rax, 328(%rsp)
leaq 512(%rsp), %rax
movq %rax, 336(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 376
pushq 56(%rsp)
.cfi_def_cfa_offset 384
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computeffiffffffffffffffffffffPffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 368
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff, .-_Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff
.globl _Z7computeffiffffffffffffffffffffPffffff
.type _Z7computeffiffffffffffffffffffffPffffff, @function
_Z7computeffiffffffffffffffffffffPffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movss 320(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computeffiffffffffffffffffffffPffffff, .-_Z7computeffiffffffffffffffffffffPffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r12
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 244(%rsp)
movl $1, 248(%rsp)
movl $1, 232(%rsp)
movl $1, 236(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 244(%rsp), %rdx
movl $1, %ecx
movq 232(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 216(%rsp), %xmm0
subq $160, %rsp
.cfi_def_cfa_offset 448
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r12, %rsi
pxor %xmm7, %xmm7
cvtsd2ss 320(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 328(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 336(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 344(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 352(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 360(%rsp), %xmm2
movl %ebp, %edi
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
call _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff
addq $160, %rsp
.cfi_def_cfa_offset 288
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computeffiffffffffffffffffffffPffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computeffiffffffffffffffffffffPffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float* var_23,float var_24,float var_25,float var_26,float var_27,float var_28) {
if (comp >= +1.8035E-44f * var_1 - ldexpf(sinhf(+1.7007E6f), 2)) {
float tmp_1 = var_3 + -1.2161E24f;
comp = tmp_1 + var_4 / powf(coshf(sinhf(+1.0028E36f + (+1.4320E35f - var_5 / (var_6 + var_7)))), (-1.2913E35f / -1.0767E25f - sinf(var_8 + var_9)));
if (comp > (-1.9370E36f / coshf((var_10 + var_11)))) {
comp = var_12 * logf(var_13 / (var_14 + var_15 / -1.0214E-44f));
comp += var_16 * (var_17 / (var_18 * log10f(-1.8316E36f + var_19 / (var_20 * (var_21 - var_22)))));
}
for (int i=0; i < var_2; ++i) {
var_23[i] = (var_24 * fabsf(+1.6748E-43f));
comp += var_23[i] * log10f((+1.8275E-35f * +1.5333E34f));
}
if (comp == -1.2292E35f / (+1.4097E-14f * -1.3440E-43f / fabsf(var_25 - var_26 + +1.1116E-37f))) {
comp = (var_27 - logf(+1.7451E8f));
comp += (+1.0251E-44f * var_28);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float* tmp_24 = initPointer( atof(argv[24]) );
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float* var_23,float var_24,float var_25,float var_26,float var_27,float var_28) {
if (comp >= +1.8035E-44f * var_1 - ldexpf(sinhf(+1.7007E6f), 2)) {
float tmp_1 = var_3 + -1.2161E24f;
comp = tmp_1 + var_4 / powf(coshf(sinhf(+1.0028E36f + (+1.4320E35f - var_5 / (var_6 + var_7)))), (-1.2913E35f / -1.0767E25f - sinf(var_8 + var_9)));
if (comp > (-1.9370E36f / coshf((var_10 + var_11)))) {
comp = var_12 * logf(var_13 / (var_14 + var_15 / -1.0214E-44f));
comp += var_16 * (var_17 / (var_18 * log10f(-1.8316E36f + var_19 / (var_20 * (var_21 - var_22)))));
}
for (int i=0; i < var_2; ++i) {
var_23[i] = (var_24 * fabsf(+1.6748E-43f));
comp += var_23[i] * log10f((+1.8275E-35f * +1.5333E34f));
}
if (comp == -1.2292E35f / (+1.4097E-14f * -1.3440E-43f / fabsf(var_25 - var_26 + +1.1116E-37f))) {
comp = (var_27 - logf(+1.7451E8f));
comp += (+1.0251E-44f * var_28);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float* tmp_24 = initPointer( atof(argv[24]) );
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float* var_23,float var_24,float var_25,float var_26,float var_27,float var_28) {
if (comp >= +1.8035E-44f * var_1 - ldexpf(sinhf(+1.7007E6f), 2)) {
float tmp_1 = var_3 + -1.2161E24f;
comp = tmp_1 + var_4 / powf(coshf(sinhf(+1.0028E36f + (+1.4320E35f - var_5 / (var_6 + var_7)))), (-1.2913E35f / -1.0767E25f - sinf(var_8 + var_9)));
if (comp > (-1.9370E36f / coshf((var_10 + var_11)))) {
comp = var_12 * logf(var_13 / (var_14 + var_15 / -1.0214E-44f));
comp += var_16 * (var_17 / (var_18 * log10f(-1.8316E36f + var_19 / (var_20 * (var_21 - var_22)))));
}
for (int i=0; i < var_2; ++i) {
var_23[i] = (var_24 * fabsf(+1.6748E-43f));
comp += var_23[i] * log10f((+1.8275E-35f * +1.5333E34f));
}
if (comp == -1.2292E35f / (+1.4097E-14f * -1.3440E-43f / fabsf(var_25 - var_26 + +1.1116E-37f))) {
comp = (var_27 - logf(+1.7451E8f));
comp += (+1.0251E-44f * var_28);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float* tmp_24 = initPointer( atof(argv[24]) );
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computeffiffffffffffffffffffffPffffff # -- Begin function _Z22__device_stub__computeffiffffffffffffffffffffPffffff
.p2align 4, 0x90
.type _Z22__device_stub__computeffiffffffffffffffffffffPffffff,@function
_Z22__device_stub__computeffiffffffffffffffffffffPffffff: # @_Z22__device_stub__computeffiffffffffffffffffffffPffffff
.cfi_startproc
# %bb.0:
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 336
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movl %edi, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
movq %rsi, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 336(%rsp), %rax
movq %rax, 168(%rsp)
leaq 344(%rsp), %rax
movq %rax, 176(%rsp)
leaq 352(%rsp), %rax
movq %rax, 184(%rsp)
leaq 360(%rsp), %rax
movq %rax, 192(%rsp)
leaq 368(%rsp), %rax
movq %rax, 200(%rsp)
leaq 376(%rsp), %rax
movq %rax, 208(%rsp)
leaq 384(%rsp), %rax
movq %rax, 216(%rsp)
leaq 392(%rsp), %rax
movq %rax, 224(%rsp)
leaq 400(%rsp), %rax
movq %rax, 232(%rsp)
leaq 408(%rsp), %rax
movq %rax, 240(%rsp)
leaq 416(%rsp), %rax
movq %rax, 248(%rsp)
leaq 424(%rsp), %rax
movq %rax, 256(%rsp)
leaq 432(%rsp), %rax
movq %rax, 264(%rsp)
leaq 440(%rsp), %rax
movq %rax, 272(%rsp)
leaq 88(%rsp), %rax
movq %rax, 280(%rsp)
leaq 448(%rsp), %rax
movq %rax, 288(%rsp)
leaq 456(%rsp), %rax
movq %rax, 296(%rsp)
leaq 464(%rsp), %rax
movq %rax, 304(%rsp)
leaq 472(%rsp), %rax
movq %rax, 312(%rsp)
leaq 480(%rsp), %rax
movq %rax, 320(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computeffiffffffffffffffffffffPffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $344, %rsp # imm = 0x158
.cfi_adjust_cfa_offset -344
retq
.Lfunc_end0:
.size _Z22__device_stub__computeffiffffffffffffffffffffPffffff, .Lfunc_end0-_Z22__device_stub__computeffiffffffffffffffffffffPffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 176(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 184(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 192(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r15
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $10, %r12
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 200(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 208(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 216(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 224(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 232(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 144(%rsp)
movss %xmm9, 136(%rsp)
movss %xmm10, 128(%rsp)
movss %xmm11, 120(%rsp)
movss %xmm12, 112(%rsp)
movss %xmm13, 104(%rsp)
movss %xmm14, 96(%rsp)
movss %xmm15, 88(%rsp)
movss %xmm4, 80(%rsp)
movss %xmm5, 72(%rsp)
movss %xmm6, 64(%rsp)
movss %xmm7, 56(%rsp)
movss 168(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 48(%rsp)
movss 176(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 40(%rsp)
movss 184(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 32(%rsp)
movss 192(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 24(%rsp)
movss 200(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 16(%rsp)
movss 208(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 8(%rsp)
movss 216(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movl %ebx, %edi
movss 240(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 232(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 224(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 160(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r15, %rsi
callq _Z22__device_stub__computeffiffffffffffffffffffffPffffff
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computeffiffffffffffffffffffffPffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computeffiffffffffffffffffffffPffffff,@object # @_Z7computeffiffffffffffffffffffffPffffff
.section .rodata,"a",@progbits
.globl _Z7computeffiffffffffffffffffffffPffffff
.p2align 3, 0x0
_Z7computeffiffffffffffffffffffffPffffff:
.quad _Z22__device_stub__computeffiffffffffffffffffffffPffffff
.size _Z7computeffiffffffffffffffffffffPffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computeffiffffffffffffffffffffPffffff"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computeffiffffffffffffffffffffPffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computeffiffffffffffffffffffffPffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019e6a2_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff
.type _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff, @function
_Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $360, %rsp
.cfi_def_cfa_offset 368
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movl %edi, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 368(%rsp), %rax
movq %rax, 184(%rsp)
leaq 376(%rsp), %rax
movq %rax, 192(%rsp)
leaq 384(%rsp), %rax
movq %rax, 200(%rsp)
leaq 392(%rsp), %rax
movq %rax, 208(%rsp)
leaq 400(%rsp), %rax
movq %rax, 216(%rsp)
leaq 408(%rsp), %rax
movq %rax, 224(%rsp)
leaq 416(%rsp), %rax
movq %rax, 232(%rsp)
leaq 424(%rsp), %rax
movq %rax, 240(%rsp)
leaq 432(%rsp), %rax
movq %rax, 248(%rsp)
leaq 440(%rsp), %rax
movq %rax, 256(%rsp)
leaq 448(%rsp), %rax
movq %rax, 264(%rsp)
leaq 456(%rsp), %rax
movq %rax, 272(%rsp)
leaq 464(%rsp), %rax
movq %rax, 280(%rsp)
leaq 472(%rsp), %rax
movq %rax, 288(%rsp)
movq %rsp, %rax
movq %rax, 296(%rsp)
leaq 480(%rsp), %rax
movq %rax, 304(%rsp)
leaq 488(%rsp), %rax
movq %rax, 312(%rsp)
leaq 496(%rsp), %rax
movq %rax, 320(%rsp)
leaq 504(%rsp), %rax
movq %rax, 328(%rsp)
leaq 512(%rsp), %rax
movq %rax, 336(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 376
pushq 56(%rsp)
.cfi_def_cfa_offset 384
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computeffiffffffffffffffffffffPffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 368
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff, .-_Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff
.globl _Z7computeffiffffffffffffffffffffPffffff
.type _Z7computeffiffffffffffffffffffffPffffff, @function
_Z7computeffiffffffffffffffffffffPffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movss 320(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computeffiffffffffffffffffffffPffffff, .-_Z7computeffiffffffffffffffffffffPffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r12
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 244(%rsp)
movl $1, 248(%rsp)
movl $1, 232(%rsp)
movl $1, 236(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 244(%rsp), %rdx
movl $1, %ecx
movq 232(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 216(%rsp), %xmm0
subq $160, %rsp
.cfi_def_cfa_offset 448
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r12, %rsi
pxor %xmm7, %xmm7
cvtsd2ss 320(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 328(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 336(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 344(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 352(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 360(%rsp), %xmm2
movl %ebp, %edi
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
call _Z54__device_stub__Z7computeffiffffffffffffffffffffPffffffffiffffffffffffffffffffPffffff
addq $160, %rsp
.cfi_def_cfa_offset 288
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computeffiffffffffffffffffffffPffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computeffiffffffffffffffffffffPffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computeffiffffffffffffffffffffPffffff # -- Begin function _Z22__device_stub__computeffiffffffffffffffffffffPffffff
.p2align 4, 0x90
.type _Z22__device_stub__computeffiffffffffffffffffffffPffffff,@function
_Z22__device_stub__computeffiffffffffffffffffffffPffffff: # @_Z22__device_stub__computeffiffffffffffffffffffffPffffff
.cfi_startproc
# %bb.0:
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 336
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movl %edi, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
movq %rsi, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 336(%rsp), %rax
movq %rax, 168(%rsp)
leaq 344(%rsp), %rax
movq %rax, 176(%rsp)
leaq 352(%rsp), %rax
movq %rax, 184(%rsp)
leaq 360(%rsp), %rax
movq %rax, 192(%rsp)
leaq 368(%rsp), %rax
movq %rax, 200(%rsp)
leaq 376(%rsp), %rax
movq %rax, 208(%rsp)
leaq 384(%rsp), %rax
movq %rax, 216(%rsp)
leaq 392(%rsp), %rax
movq %rax, 224(%rsp)
leaq 400(%rsp), %rax
movq %rax, 232(%rsp)
leaq 408(%rsp), %rax
movq %rax, 240(%rsp)
leaq 416(%rsp), %rax
movq %rax, 248(%rsp)
leaq 424(%rsp), %rax
movq %rax, 256(%rsp)
leaq 432(%rsp), %rax
movq %rax, 264(%rsp)
leaq 440(%rsp), %rax
movq %rax, 272(%rsp)
leaq 88(%rsp), %rax
movq %rax, 280(%rsp)
leaq 448(%rsp), %rax
movq %rax, 288(%rsp)
leaq 456(%rsp), %rax
movq %rax, 296(%rsp)
leaq 464(%rsp), %rax
movq %rax, 304(%rsp)
leaq 472(%rsp), %rax
movq %rax, 312(%rsp)
leaq 480(%rsp), %rax
movq %rax, 320(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computeffiffffffffffffffffffffPffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $344, %rsp # imm = 0x158
.cfi_adjust_cfa_offset -344
retq
.Lfunc_end0:
.size _Z22__device_stub__computeffiffffffffffffffffffffPffffff, .Lfunc_end0-_Z22__device_stub__computeffiffffffffffffffffffffPffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 176(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 184(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 192(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r15
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $10, %r12
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 200(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 208(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 216(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 224(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 232(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 144(%rsp)
movss %xmm9, 136(%rsp)
movss %xmm10, 128(%rsp)
movss %xmm11, 120(%rsp)
movss %xmm12, 112(%rsp)
movss %xmm13, 104(%rsp)
movss %xmm14, 96(%rsp)
movss %xmm15, 88(%rsp)
movss %xmm4, 80(%rsp)
movss %xmm5, 72(%rsp)
movss %xmm6, 64(%rsp)
movss %xmm7, 56(%rsp)
movss 168(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 48(%rsp)
movss 176(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 40(%rsp)
movss 184(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 32(%rsp)
movss 192(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 24(%rsp)
movss 200(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 16(%rsp)
movss 208(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 8(%rsp)
movss 216(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movl %ebx, %edi
movss 240(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 232(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 224(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 160(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r15, %rsi
callq _Z22__device_stub__computeffiffffffffffffffffffffPffffff
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computeffiffffffffffffffffffffPffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computeffiffffffffffffffffffffPffffff,@object # @_Z7computeffiffffffffffffffffffffPffffff
.section .rodata,"a",@progbits
.globl _Z7computeffiffffffffffffffffffffPffffff
.p2align 3, 0x0
_Z7computeffiffffffffffffffffffffPffffff:
.quad _Z22__device_stub__computeffiffffffffffffffffffffPffffff
.size _Z7computeffiffffffffffffffffffffPffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computeffiffffffffffffffffffffPffffff"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computeffiffffffffffffffffffffPffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computeffiffffffffffffffffffffPffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void block_normalization_kernel(float* histograms, float* descriptor, int histograms_step, int block_grid_width, int block_grid_height, int block_width, int block_height, int num_bins, int cell_grid_width, int block_stride_x, int block_stride_y)
{
//TODO: make the buffer sizes dependent on an input or template parameter.
// Each thread block will process 8 hog blocks. Each hog block has 4 cells.
// Each cell has 9 bins.
__shared__ float s_blocks[9 * 4 * 8];
__shared__ float L1_norm[8];
int block_x = blockIdx.x * 8 + threadIdx.z;
if(block_x >= block_grid_width)
{
return;
}
int block_y = blockIdx.y;
if(block_y >= block_grid_height)
{
return;
}
int block_idx = block_y * blockDim.y + block_x;
int cell_x = block_x * block_stride_x + threadIdx.y % 2;
int cell_y = block_y * block_stride_y + threadIdx.y / 2;
int hist_idx = histograms_step * cell_y + num_bins * (cell_x) + threadIdx.x;
int s_blocks_idx = 9 * threadIdx.y + threadIdx.x;
s_blocks[s_blocks_idx] = histograms[hist_idx];
__syncthreads();
int thread_id = 36 * threadIdx.z + 9 * threadIdx.y + threadIdx.x;
int elements_per_block = block_height * block_width * num_bins;
if(thread_id < 8)
{
L1_norm[thread_id] = 0.0f;
for(int i = 0; i < elements_per_block; ++i)
{
L1_norm[thread_id] += s_blocks[elements_per_block * thread_id + i];
}
}
__syncthreads();
descriptor[elements_per_block * block_idx + s_blocks_idx] =
s_blocks[s_blocks_idx] / L1_norm[threadIdx.z];
} | code for sm_80
Function : _Z26block_normalization_kernelPfS_iiiiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.Z ; /* 0x0000000000007919 */
/* 0x000e240000002300 */
/*0030*/ IMAD R2, R3, 0x8, R0 ; /* 0x0000000803027824 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e240000002600 */
/*0070*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x001fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*00d0*/ LOP3.LUT R3, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105037812 */
/* 0x001fe400078ec0ff */
/*00e0*/ SHF.R.U32.HI R4, RZ, 0x1, R5 ; /* 0x00000001ff047819 */
/* 0x000fc60000011605 */
/*00f0*/ IMAD R3, R2, c[0x0][0x18c], R3 ; /* 0x0000630002037a24 */
/* 0x000fe400078e0203 */
/*0100*/ IMAD R4, R7, c[0x0][0x190], R4 ; /* 0x0000640007047a24 */
/* 0x000fe400078e0204 */
/*0110*/ IMAD R3, R3, c[0x0][0x184], R6 ; /* 0x0000610003037a24 */
/* 0x002fc800078e0206 */
/*0120*/ IMAD R3, R4, c[0x0][0x170], R3 ; /* 0x00005c0004037a24 */
/* 0x000fc800078e0203 */
/*0130*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fcc00078e0208 */
/*0140*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD R3, R5, 0x9, R6 ; /* 0x0000000905037824 */
/* 0x000fe200078e0206 */
/*0160*/ BSSY B0, 0x8e0 ; /* 0x0000077000007945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD R5, R0, 0x24, R3 ; /* 0x0000002400057824 */
/* 0x000fe400078e0203 */
/*0190*/ IMAD R4, R6, c[0x0][0x17c], RZ ; /* 0x00005f0006047a24 */
/* 0x000fe400078e02ff */
/*01a0*/ IMAD R2, R7, c[0x0][0x4], R2 ; /* 0x0000010007027a24 */
/* 0x000fe200078e0202 */
/*01b0*/ ISETP.GT.AND P0, PT, R5, 0x7, PT ; /* 0x000000070500780c */
/* 0x000fe20003f04270 */
/*01c0*/ IMAD R4, R4, c[0x0][0x184], RZ ; /* 0x0000610004047a24 */
/* 0x000fe200078e02ff */
/*01d0*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x0041e80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fee0000010000 */
/*01f0*/ @P0 BRA 0x8d0 ; /* 0x000006d000000947 */
/* 0x000fea0003800000 */
/*0200*/ STS [R5.X4+0x480], RZ ; /* 0x000480ff05007388 */
/* 0x0011e20000004800 */
/*0210*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0220*/ @!P0 BRA 0x8d0 ; /* 0x000006a000008947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R7, R4.reuse, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x041fe20007ffe0ff */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0250*/ LOP3.LUT R9, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304097812 */
/* 0x000fe200078ec0ff */
/*0260*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fda0003f06070 */
/*0280*/ @!P0 BRA 0x800 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R7, R4, -R9, RZ ; /* 0x8000000904077210 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD R8, R6, c[0x0][0x184], RZ ; /* 0x0000610006087a24 */
/* 0x000fe200078e02ff */
/*02b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*02c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f04270 */
/*02e0*/ IMAD R8, R8, c[0x0][0x17c], RZ ; /* 0x00005f0008087a24 */
/* 0x000fc800078e02ff */
/*02f0*/ IMAD R8, R5, R8, RZ ; /* 0x0000000805087224 */
/* 0x000fca00078e02ff */
/*0300*/ LEA R8, R8, 0x8, 0x2 ; /* 0x0000000808087811 */
/* 0x000fc600078e10ff */
/*0310*/ @!P0 BRA 0x730 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0340*/ @!P1 BRA 0x5b0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0360*/ LDS R15, [R8+-0x8] ; /* 0xfffff800080f7984 */
/* 0x000e220000000800 */
/*0370*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fe20007ffe0ff */
/*0380*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0390*/ LDS R17, [R8+-0x4] ; /* 0xfffffc0008117984 */
/* 0x000e620000000800 */
/*03a0*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fc60003f24270 */
/*03b0*/ LDS R18, [R8] ; /* 0x0000000008127984 */
/* 0x000ea80000000800 */
/*03c0*/ LDS R19, [R8+0x4] ; /* 0x0000040008137984 */
/* 0x000ee80000000800 */
/*03d0*/ LDS R20, [R8+0x8] ; /* 0x0000080008147984 */
/* 0x000f280000000800 */
/*03e0*/ LDS R11, [R8+0xc] ; /* 0x00000c00080b7984 */
/* 0x000f680000000800 */
/*03f0*/ LDS R10, [R8+0x10] ; /* 0x00001000080a7984 */
/* 0x000f680000000800 */
/*0400*/ LDS R14, [R8+0x14] ; /* 0x00001400080e7984 */
/* 0x000f680000000800 */
/*0410*/ LDS R13, [R8+0x18] ; /* 0x00001800080d7984 */
/* 0x000f680000000800 */
/*0420*/ LDS R12, [R8+0x1c] ; /* 0x00001c00080c7984 */
/* 0x000f620000000800 */
/*0430*/ FADD R16, R15, R16 ; /* 0x000000100f107221 */
/* 0x001fc60000000000 */
/*0440*/ LDS R21, [R8+0x34] ; /* 0x0000340008157984 */
/* 0x000fe20000000800 */
/*0450*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x002fc60000000000 */
/*0460*/ LDS R15, [R8+0x20] ; /* 0x00002000080f7984 */
/* 0x000e220000000800 */
/*0470*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x004fc60000000000 */
/*0480*/ LDS R16, [R8+0x24] ; /* 0x0000240008107984 */
/* 0x000e620000000800 */
/*0490*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x008fc60000000000 */
/*04a0*/ LDS R17, [R8+0x28] ; /* 0x0000280008117984 */
/* 0x000ea20000000800 */
/*04b0*/ FADD R20, R19, R20 ; /* 0x0000001413147221 */
/* 0x010fc60000000000 */
/*04c0*/ LDS R18, [R8+0x2c] ; /* 0x00002c0008127984 */
/* 0x000ee20000000800 */
/*04d0*/ FADD R11, R20, R11 ; /* 0x0000000b140b7221 */
/* 0x020fc60000000000 */
/*04e0*/ LDS R19, [R8+0x30] ; /* 0x0000300008137984 */
/* 0x0009620000000800 */
/*04f0*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x000fc80000000000 */
/*0500*/ FADD R14, R11, R14 ; /* 0x0000000e0b0e7221 */
/* 0x000fe20000000000 */
/*0510*/ IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008087810 */
/* 0x010fc60007ffe0ff */
/*0520*/ FADD R13, R14, R13 ; /* 0x0000000d0e0d7221 */
/* 0x000fc80000000000 */
/*0530*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x000fc80000000000 */
/*0540*/ FADD R15, R12, R15 ; /* 0x0000000f0c0f7221 */
/* 0x001fc80000000000 */
/*0550*/ FADD R16, R15, R16 ; /* 0x000000100f107221 */
/* 0x002fc80000000000 */
/*0560*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x004fc80000000000 */
/*0570*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x008fc80000000000 */
/*0580*/ FADD R18, R18, R19 ; /* 0x0000001312127221 */
/* 0x020fc80000000000 */
/*0590*/ FADD R16, R18, R21 ; /* 0x0000001512107221 */
/* 0x000fe20000000000 */
/*05a0*/ @P1 BRA 0x360 ; /* 0xfffffdb000001947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*05c0*/ @!P1 BRA 0x710 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*05d0*/ LDS R11, [R8+-0x8] ; /* 0xfffff800080b7984 */
/* 0x000e220000000800 */
/*05e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*05f0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0600*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0610*/ LDS R10, [R8+-0x4] ; /* 0xfffffc00080a7984 */
/* 0x000e680000000800 */
/*0620*/ LDS R13, [R8] ; /* 0x00000000080d7984 */
/* 0x000ea80000000800 */
/*0630*/ LDS R15, [R8+0x4] ; /* 0x00000400080f7984 */
/* 0x000ee80000000800 */
/*0640*/ LDS R17, [R8+0x8] ; /* 0x0000080008117984 */
/* 0x000f280000000800 */
/*0650*/ LDS R19, [R8+0xc] ; /* 0x00000c0008137984 */
/* 0x000f680000000800 */
/*0660*/ LDS R21, [R8+0x10] ; /* 0x0000100008157984 */
/* 0x000f680000000800 */
/*0670*/ LDS R23, [R8+0x14] ; /* 0x0000140008177984 */
/* 0x0001640000000800 */
/*0680*/ IADD3 R8, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x001fe20007ffe0ff */
/*0690*/ FADD R11, R16, R11 ; /* 0x0000000b100b7221 */
/* 0x000fc80000000000 */
/*06a0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x002fc80000000000 */
/*06b0*/ FADD R10, R10, R13 ; /* 0x0000000d0a0a7221 */
/* 0x004fc80000000000 */
/*06c0*/ FADD R10, R10, R15 ; /* 0x0000000f0a0a7221 */
/* 0x008fc80000000000 */
/*06d0*/ FADD R10, R10, R17 ; /* 0x000000110a0a7221 */
/* 0x010fc80000000000 */
/*06e0*/ FADD R10, R10, R19 ; /* 0x000000130a0a7221 */
/* 0x020fc80000000000 */
/*06f0*/ FADD R10, R10, R21 ; /* 0x000000150a0a7221 */
/* 0x000fc80000000000 */
/*0700*/ FADD R16, R10, R23 ; /* 0x000000170a107221 */
/* 0x000fe40000000000 */
/*0710*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0720*/ @!P0 BRA 0x800 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0730*/ LDS R11, [R8+-0x8] ; /* 0xfffff800080b7984 */
/* 0x000e220000000800 */
/*0740*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*0750*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0760*/ LDS R10, [R8+-0x4] ; /* 0xfffffc00080a7984 */
/* 0x000e620000000800 */
/*0770*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f05270 */
/*0780*/ LDS R13, [R8] ; /* 0x00000000080d7984 */
/* 0x000ea80000000800 */
/*0790*/ LDS R15, [R8+0x4] ; /* 0x00000400080f7984 */
/* 0x0007240000000800 */
/*07a0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x008fe20007ffe0ff */
/*07b0*/ FADD R11, R11, R16 ; /* 0x000000100b0b7221 */
/* 0x001fc80000000000 */
/*07c0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x002fc80000000000 */
/*07d0*/ FADD R10, R10, R13 ; /* 0x0000000d0a0a7221 */
/* 0x004fc80000000000 */
/*07e0*/ FADD R16, R10, R15 ; /* 0x0000000f0a107221 */
/* 0x010fe20000000000 */
/*07f0*/ @P0 BRA 0x730 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0800*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0810*/ @!P0 BRA 0x8c0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0820*/ IMAD R6, R6, c[0x0][0x184], RZ ; /* 0x0000610006067a24 */
/* 0x000fc800078e02ff */
/*0830*/ IMAD R6, R6, c[0x0][0x17c], RZ ; /* 0x00005f0006067a24 */
/* 0x000fc800078e02ff */
/*0840*/ IMAD R6, R5, R6, UR4 ; /* 0x0000000405067e24 */
/* 0x000fc8000f8e0206 */
/*0850*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*0860*/ LDS R7, [R6] ; /* 0x0000000006077984 */
/* 0x0000620000000800 */
/*0870*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fc80007ffe0ff */
/*0880*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0890*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fe20007ffe0ff */
/*08a0*/ FADD R16, R7, R16 ; /* 0x0000001007107221 */
/* 0x002fd40000000000 */
/*08b0*/ @P0 BRA 0x860 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*08c0*/ STS [R5.X4+0x480], R16 ; /* 0x0004801005007388 */
/* 0x0001e40000004800 */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*08e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08f0*/ BSSY B0, 0x9e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0900*/ LDS R5, [R0.X4+0x480] ; /* 0x0004800000057984 */
/* 0x000e280000004800 */
/*0910*/ LDS R8, [R3.X4] ; /* 0x0000000003087984 */
/* 0x000e620000004800 */
/*0920*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x001e300000001000 */
/*0930*/ FCHK P0, R8, R5 ; /* 0x0000000508007302 */
/* 0x002e620000000000 */
/*0940*/ FFMA R7, -R5, R6, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000106 */
/*0950*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0960*/ FFMA R6, R8, R7, RZ ; /* 0x0000000708067223 */
/* 0x000fc800000000ff */
/*0970*/ FFMA R9, -R5, R6, R8 ; /* 0x0000000605097223 */
/* 0x000fc80000000108 */
/*0980*/ FFMA R7, R7, R9, R6 ; /* 0x0000000907077223 */
/* 0x000fe20000000006 */
/*0990*/ @!P0 BRA 0x9d0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*09a0*/ MOV R0, 0x9c0 ; /* 0x000009c000007802 */
/* 0x000fe40000000f00 */
/*09b0*/ CALL.REL.NOINC 0xa30 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*09c0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0005 */
/*09d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*09f0*/ IMAD R2, R2, R4, R3 ; /* 0x0000000402027224 */
/* 0x000fc800078e0203 */
/*0a00*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0205 */
/*0a10*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0a20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a30*/ SHF.R.U32.HI R7, RZ, 0x17, R5.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011605 */
/*0a40*/ BSSY B1, 0x1090 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0a50*/ SHF.R.U32.HI R6, RZ, 0x17, R8 ; /* 0x00000017ff067819 */
/* 0x000fe20000011608 */
/*0a60*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0a70*/ LOP3.LUT R9, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07097812 */
/* 0x000fe400078ec0ff */
/*0a80*/ LOP3.LUT R7, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06077812 */
/* 0x000fe400078ec0ff */
/*0a90*/ IADD3 R13, R9, -0x1, RZ ; /* 0xffffffff090d7810 */
/* 0x000fe40007ffe0ff */
/*0aa0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*0ab0*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fe40003f04070 */
/*0ac0*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fe40000000f00 */
/*0ad0*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0ae0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0af0*/ @!P0 BRA 0xc70 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0b00*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0b10*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0b20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0b30*/ @P0 BRA 0x1070 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT P0, RZ, R11, 0x7fffffff, R10, 0xc8, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fda000780c80a */
/*0b50*/ @!P0 BRA 0x1050 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0b60*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*0b70*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0b80*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*0b90*/ @!P1 BRA !P2, 0x1050 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0ba0*/ LOP3.LUT P2, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000784c0ff */
/*0bb0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0bc0*/ @P1 BRA 0x1030 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0bd0*/ LOP3.LUT P1, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000782c0ff */
/*0be0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0bf0*/ @P0 BRA 0x1000 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0c00*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0c10*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*0c20*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0c30*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0c40*/ @!P0 FFMA R10, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f800000080a8823 */
/* 0x000fe400000000ff */
/*0c50*/ @!P1 FFMA R11, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f800000050b9823 */
/* 0x000fe200000000ff */
/*0c60*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0c70*/ LEA R8, R9, 0xc0800000, 0x17 ; /* 0xc080000009087811 */
/* 0x000fe200078eb8ff */
/*0c80*/ BSSY B2, 0xff0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0c90*/ IADD3 R7, R7, -0x7f, RZ ; /* 0xffffff8107077810 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ IADD3 R8, -R8, R11, RZ ; /* 0x0000000b08087210 */
/* 0x000fc40007ffe1ff */
/*0cb0*/ IADD3 R9, R7.reuse, 0x7f, -R9 ; /* 0x0000007f07097810 */
/* 0x040fe20007ffe809 */
/*0cc0*/ IMAD R10, R7, -0x800000, R10 ; /* 0xff800000070a7824 */
/* 0x000fe200078e020a */
/*0cd0*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e220000001000 */
/*0ce0*/ FADD.FTZ R11, -R8, -RZ ; /* 0x800000ff080b7221 */
/* 0x000fe40000010100 */
/*0cf0*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fe400078e0206 */
/*0d00*/ FFMA R12, R5, R11, 1 ; /* 0x3f800000050c7423 */
/* 0x001fc8000000000b */
/*0d10*/ FFMA R13, R5, R12, R5 ; /* 0x0000000c050d7223 */
/* 0x000fc80000000005 */
/*0d20*/ FFMA R5, R10, R13, RZ ; /* 0x0000000d0a057223 */
/* 0x000fc800000000ff */
/*0d30*/ FFMA R12, R11, R5, R10 ; /* 0x000000050b0c7223 */
/* 0x000fc8000000000a */
/*0d40*/ FFMA R12, R13, R12, R5 ; /* 0x0000000c0d0c7223 */
/* 0x000fc80000000005 */
/*0d50*/ FFMA R10, R11, R12, R10 ; /* 0x0000000c0b0a7223 */
/* 0x000fc8000000000a */
/*0d60*/ FFMA R5, R13, R10, R12 ; /* 0x0000000a0d057223 */
/* 0x000fca000000000c */
/*0d70*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fc80000011605 */
/*0d80*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*0d90*/ IMAD.IADD R11, R7, 0x1, R6 ; /* 0x00000001070b7824 */
/* 0x000fca00078e0206 */
/*0da0*/ IADD3 R7, R11, -0x1, RZ ; /* 0xffffffff0b077810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0dc0*/ @!P0 BRA 0xfd0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0dd0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0de0*/ @P0 BRA 0xfa0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0df0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0e00*/ @P0 BRA 0xfe0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0e10*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0e20*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0e30*/ @!P0 BRA 0xfe0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0e40*/ FFMA.RZ R6, R13, R10.reuse, R12.reuse ; /* 0x0000000a0d067223 */
/* 0x180fe2000000c00c */
/*0e50*/ IADD3 R9, R11, 0x20, RZ ; /* 0x000000200b097810 */
/* 0x000fe20007ffe0ff */
/*0e60*/ FFMA.RM R7, R13, R10.reuse, R12.reuse ; /* 0x0000000a0d077223 */
/* 0x180fe2000000400c */
/*0e70*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0e80*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0e90*/ FFMA.RP R6, R13, R10, R12 ; /* 0x0000000a0d067223 */
/* 0x000fe2000000800c */
/*0ea0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*0eb0*/ IMAD.MOV R10, RZ, RZ, -R11 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0b */
/*0ec0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0ed0*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fc40003f1d000 */
/*0ee0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0ef0*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0f00*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0f10*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0f20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0f30*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc40000011607 */
/*0f40*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0f50*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0f60*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0f70*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*0f80*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*0f90*/ BRA 0xfe0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0fa0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0fb0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0fc0*/ BRA 0xfe0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0fd0*/ LEA R5, R6, R5, 0x17 ; /* 0x0000000506057211 */
/* 0x000fe400078eb8ff */
/*0fe0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ff0*/ BRA 0x1080 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1000*/ LOP3.LUT R5, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b057812 */
/* 0x000fc800078e480a */
/*1010*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*1020*/ BRA 0x1080 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1030*/ LOP3.LUT R5, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b057812 */
/* 0x000fe200078e480a */
/*1040*/ BRA 0x1080 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1050*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*1060*/ BRA 0x1080 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1070*/ FADD.FTZ R5, R8, R5 ; /* 0x0000000508057221 */
/* 0x000fe40000010000 */
/*1080*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1090*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*10a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*10b0*/ RET.REL.NODEC R6 0x0 ; /* 0xffffef4006007950 */
/* 0x000fea0003c3ffff */
/*10c0*/ BRA 0x10c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void block_normalization_kernel(float* histograms, float* descriptor, int histograms_step, int block_grid_width, int block_grid_height, int block_width, int block_height, int num_bins, int cell_grid_width, int block_stride_x, int block_stride_y)
{
//TODO: make the buffer sizes dependent on an input or template parameter.
// Each thread block will process 8 hog blocks. Each hog block has 4 cells.
// Each cell has 9 bins.
__shared__ float s_blocks[9 * 4 * 8];
__shared__ float L1_norm[8];
int block_x = blockIdx.x * 8 + threadIdx.z;
if(block_x >= block_grid_width)
{
return;
}
int block_y = blockIdx.y;
if(block_y >= block_grid_height)
{
return;
}
int block_idx = block_y * blockDim.y + block_x;
int cell_x = block_x * block_stride_x + threadIdx.y % 2;
int cell_y = block_y * block_stride_y + threadIdx.y / 2;
int hist_idx = histograms_step * cell_y + num_bins * (cell_x) + threadIdx.x;
int s_blocks_idx = 9 * threadIdx.y + threadIdx.x;
s_blocks[s_blocks_idx] = histograms[hist_idx];
__syncthreads();
int thread_id = 36 * threadIdx.z + 9 * threadIdx.y + threadIdx.x;
int elements_per_block = block_height * block_width * num_bins;
if(thread_id < 8)
{
L1_norm[thread_id] = 0.0f;
for(int i = 0; i < elements_per_block; ++i)
{
L1_norm[thread_id] += s_blocks[elements_per_block * thread_id + i];
}
}
__syncthreads();
descriptor[elements_per_block * block_idx + s_blocks_idx] =
s_blocks[s_blocks_idx] / L1_norm[threadIdx.z];
} | .file "tmpxft_0016fb48_00000000-6_block_normalization_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii
.type _Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii, @function
_Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 216
pushq 40(%rsp)
.cfi_def_cfa_offset 224
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26block_normalization_kernelPfS_iiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii, .-_Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii
.globl _Z26block_normalization_kernelPfS_iiiiiiiii
.type _Z26block_normalization_kernelPfS_iiiiiiiii, @function
_Z26block_normalization_kernelPfS_iiiiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26block_normalization_kernelPfS_iiiiiiiii, .-_Z26block_normalization_kernelPfS_iiiiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26block_normalization_kernelPfS_iiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26block_normalization_kernelPfS_iiiiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.