system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void spaceFilterUpdate(const double *Params, const float *data, const float *U, const bool *UtU, const int *iC, const int *iW, float *dprod, const int *st, const int *id, const int *counter){
volatile __shared__ float sU[32*NrankMax];
volatile __shared__ int iU[32];
float x;
int tid, bid, ind, nt0, i, t, k, Nrank, NT, Nfilt, NchanU, Nchan;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
// just need to do this for all filters that have overlap with id[bid] and st[id]
// tidx still represents time, from -nt0 to nt0
// tidy loops through all filters that have overlap
if (tid<NchanU)
iU[tid] = iC[tid + NchanU * iW[bid]];
__syncthreads();
if (tid<NchanU)
for (k=0;k<Nrank;k++)
sU[tid + k * NchanU] = U[iU[tid] + Nchan * bid + Nchan * Nfilt * k];
__syncthreads();
for(ind=counter[1];ind<counter[0];ind++)
if (UtU[id[ind] + Nfilt *bid]){
t = st[ind] + tid - nt0;
// if this is a hit, threads compute all time offsets
if (t>=0 & t<NT){
for (k=0;k<Nrank;k++){
x = 0.0f;
for(i=0;i<NchanU;i++)
x += sU[i + NchanU*k] * data[t + NT * iU[i]];
dprod[t + NT*bid + k*NT*Nfilt] = x;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.globl _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.p2align 8
.type _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_,@function
_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_:
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s12, s15
s_waitcnt lgkmcnt(0)
s_load_b128 s[8:11], s[2:3], 0x48
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v1, s[10:11]
s_clause 0x2
s_load_b64 s[14:15], s[2:3], 0x30
s_load_b128 s[4:7], s[2:3], 0x0
s_load_b64 s[10:11], s[2:3], 0x20
s_delay_alu instid0(VALU_DEP_1)
v_readfirstlane_b32 s18, v1
v_cmp_lt_i32_e32 vcc_lo, v0, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[20:23], s[0:1], 0x20
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[12:13], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s16, s22, s16
s_addc_u32 s17, s23, s17
s_load_b32 s2, s[16:17], 0x0
s_mov_b64 s[16:17], src_shared_base
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s2, s18, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s20, v1
v_add_co_ci_u32_e64 v2, s2, s21, v2, s2
global_load_b32 v3, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0x180
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, -1, v1
v_cndmask_b32_e64 v1, 0, v1, s2
v_cndmask_b32_e64 v2, 0, s17, s2
s_waitcnt vmcnt(0)
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v1, s[14:15]
v_cvt_i32_f64_e32 v2, s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_readfirstlane_b32 s2, v1
v_readfirstlane_b32 s13, v2
v_readfirstlane_b32 s19, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_gt_i32 s2, 0
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_5
v_cvt_i32_f64_e32 v1, s[8:9]
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_lshl_b32 s6, s18, 2
s_mov_b32 s8, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0x180, v3
v_cmp_ne_u32_e32 vcc_lo, -1, v2
s_delay_alu instid0(VALU_DEP_4)
v_mul_lo_u32 v4, s12, v1
v_mul_lo_u32 v5, s13, v1
v_cndmask_b32_e32 v1, 0, v2, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
.p2align 6
.LBB0_4:
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s8, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, v4, v6
v_add_nc_u32_e32 v4, v4, v5
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
global_load_b32 v8, v[6:7], off
v_cndmask_b32_e64 v7, 0, s7, vcc_lo
v_cndmask_b32_e32 v6, 0, v3, vcc_lo
v_add_nc_u32_e32 v3, s6, v3
s_waitcnt vmcnt(0)
flat_store_b32 v[6:7], v8 dlc
s_waitcnt_vscnt null, 0x0
s_cbranch_scc1 .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
s_load_b64 s[2:3], s[0:1], 0x48
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v2, v1, s[2:3]
s_load_b32 s2, s[2:3], 0x4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s2, v2
s_cbranch_vccnz .LBB0_16
v_cvt_i32_f64_e32 v4, s[10:11]
v_cvt_i32_f64_e32 v3, s[4:5]
s_clause 0x3
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b64 s[10:11], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x30
s_load_b64 s[14:15], s[0:1], 0x40
s_cmp_lt_i32 s19, 1
s_mul_i32 s22, s12, s13
s_cselect_b32 s20, -1, 0
s_cmp_gt_i32 s18, 0
s_mov_b64 s[0:1], src_shared_base
s_cselect_b32 s21, -1, 0
s_lshl_b32 s23, s18, 2
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v0, v4
s_branch .LBB0_9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_8:
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s2, v2
s_cbranch_vccz .LBB0_16
.LBB0_9:
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s24, s14, s16
s_addc_u32 s25, s15, s17
s_load_b32 s0, s[24:25], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s0, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s0, 31
s_add_u32 s24, s10, s0
s_addc_u32 s25, s11, s3
global_load_u8 v0, v1, s[24:25]
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v0
s_cbranch_vccnz .LBB0_8
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
s_load_b32 s0, s[16:17], 0x0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 0, v0
v_cmp_ge_i32_e64 s0, v0, v3
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s20
s_xor_b32 s3, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_7
s_mov_b32 s3, 0
s_mov_b32 s16, 0
s_branch .LBB0_13
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_mul_i32 s17, s16, s13
s_add_i32 s16, s16, 1
s_add_i32 s17, s17, s12
s_add_i32 s3, s3, s23
v_mad_u64_u32 v[6:7], null, s17, v3, v[0:1]
s_cmp_lg_u32 s16, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v5, off
s_cbranch_scc0 .LBB0_7
.LBB0_13:
v_mov_b32_e32 v5, 0
s_and_not1_b32 vcc_lo, exec_lo, s21
s_cbranch_vccnz .LBB0_12
s_mov_b32 s17, 0
s_mov_b32 s24, s18
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_15:
s_add_i32 s25, s17, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s25, -1
s_cselect_b32 s25, s25, 0
s_cselect_b32 s26, s1, 0
s_add_i32 s27, s17, 0x180
v_dual_mov_b32 v6, s25 :: v_dual_mov_b32 v7, s26
s_cmp_lg_u32 s27, -1
s_cselect_b32 s25, s27, 0
s_cselect_b32 s26, s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v8, s25 :: v_dual_mov_b32 v9, s26
flat_load_b32 v10, v[6:7] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v8, v[8:9] glc dlc
s_waitcnt vmcnt(0)
s_add_i32 s24, s24, -1
s_add_i32 s17, s17, 4
s_cmp_lg_u32 s24, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v8, v3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v10, v6
s_cbranch_scc1 .LBB0_15
s_branch .LBB0_12
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 80
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, .Lfunc_end0-_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 80
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void spaceFilterUpdate(const double *Params, const float *data, const float *U, const bool *UtU, const int *iC, const int *iW, float *dprod, const int *st, const int *id, const int *counter){
volatile __shared__ float sU[32*NrankMax];
volatile __shared__ int iU[32];
float x;
int tid, bid, ind, nt0, i, t, k, Nrank, NT, Nfilt, NchanU, Nchan;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
// just need to do this for all filters that have overlap with id[bid] and st[id]
// tidx still represents time, from -nt0 to nt0
// tidy loops through all filters that have overlap
if (tid<NchanU)
iU[tid] = iC[tid + NchanU * iW[bid]];
__syncthreads();
if (tid<NchanU)
for (k=0;k<Nrank;k++)
sU[tid + k * NchanU] = U[iU[tid] + Nchan * bid + Nchan * Nfilt * k];
__syncthreads();
for(ind=counter[1];ind<counter[0];ind++)
if (UtU[id[ind] + Nfilt *bid]){
t = st[ind] + tid - nt0;
// if this is a hit, threads compute all time offsets
if (t>=0 & t<NT){
for (k=0;k<Nrank;k++){
x = 0.0f;
for(i=0;i<NchanU;i++)
x += sU[i + NchanU*k] * data[t + NT * iU[i]];
dprod[t + NT*bid + k*NT*Nfilt] = x;
}
}
}
} | .text
.file "spaceFilterUpdate.hip"
.globl _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_ # -- Begin function _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.p2align 4, 0x90
.type _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_,@function
_Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_: # @_Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, .Lfunc_end0-_Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_,@object # @_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.section .rodata,"a",@progbits
.globl _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.p2align 3, 0x0
_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_:
.quad _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.size _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bb227_00000000-6_spaceFilterUpdate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.type _Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_, @function
_Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq 280(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movq %rsp, %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_, .-_Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.globl _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.type _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, @function
_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, .-_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "spaceFilterUpdate.hip"
.globl _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_ # -- Begin function _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.p2align 4, 0x90
.type _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_,@function
_Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_: # @_Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, .Lfunc_end0-_Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_,@object # @_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.section .rodata,"a",@progbits
.globl _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.p2align 3, 0x0
_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_:
.quad _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.size _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <cuda.h>
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", cudaGetErrorString(_m_cudaStat),__LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
#define SIZE 2048
__host__ int main()
{
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//Âûäåëÿåì ïàìÿòü ïîä âåêòîðà
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
// printf("#%d\t%f\t %f\n", i, vec1[i], vec2[i]);
}
float* devVec1;
float* devVec2;
float* devVec3;
CUDA_CHECK_RETURN(cudaMalloc((void**)&devVec1, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(cudaMalloc((void**)&devVec2, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(cudaMalloc((void**)&devVec3, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(cudaMemcpy(devVec1, vec1, sizeof(float) * SIZE, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(devVec2, vec2, sizeof(float) * SIZE, cudaMemcpyHostToDevice));
dim3 block(512);
cudaEventRecord(start,0);
addVector <<<SIZE/512, block >>>(devVec1, devVec2, devVec3);
cudaEventRecord(stop, 0);
CUDA_CHECK_RETURN(cudaEventSynchronize(stop));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&elapsedTime, start, stop));
cudaEvent_t syncEvent;
CUDA_CHECK_RETURN(cudaEventCreate(&syncEvent));
CUDA_CHECK_RETURN(cudaEventRecord(syncEvent, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(syncEvent));
CUDA_CHECK_RETURN(cudaMemcpy(vec3, devVec3, sizeof(float) * SIZE, cudaMemcpyDeviceToHost));
for (int i = 0; i < SIZE; i++)
{
//printf("Element #%i: %.1f\n", i, vec3[i]);
}
fprintf(stderr,"gTest took %g\n",elapsedTime);
cudaEventDestroy(syncEvent);
cudaFree(devVec1);
cudaFree(devVec2);
cudaFree(devVec3);
delete[] vec1; vec1 = 0;
delete[] vec2; vec2 = 0;
delete[] vec3; vec3 = 0;
return 0;
} | code for sm_80
Function : _Z9addVectorPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <cuda.h>
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", cudaGetErrorString(_m_cudaStat),__LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
#define SIZE 2048
__host__ int main()
{
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//Âûäåëÿåì ïàìÿòü ïîä âåêòîðà
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
// printf("#%d\t%f\t %f\n", i, vec1[i], vec2[i]);
}
float* devVec1;
float* devVec2;
float* devVec3;
CUDA_CHECK_RETURN(cudaMalloc((void**)&devVec1, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(cudaMalloc((void**)&devVec2, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(cudaMalloc((void**)&devVec3, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(cudaMemcpy(devVec1, vec1, sizeof(float) * SIZE, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(devVec2, vec2, sizeof(float) * SIZE, cudaMemcpyHostToDevice));
dim3 block(512);
cudaEventRecord(start,0);
addVector <<<SIZE/512, block >>>(devVec1, devVec2, devVec3);
cudaEventRecord(stop, 0);
CUDA_CHECK_RETURN(cudaEventSynchronize(stop));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&elapsedTime, start, stop));
cudaEvent_t syncEvent;
CUDA_CHECK_RETURN(cudaEventCreate(&syncEvent));
CUDA_CHECK_RETURN(cudaEventRecord(syncEvent, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(syncEvent));
CUDA_CHECK_RETURN(cudaMemcpy(vec3, devVec3, sizeof(float) * SIZE, cudaMemcpyDeviceToHost));
for (int i = 0; i < SIZE; i++)
{
//printf("Element #%i: %.1f\n", i, vec3[i]);
}
fprintf(stderr,"gTest took %g\n",elapsedTime);
cudaEventDestroy(syncEvent);
cudaFree(devVec1);
cudaFree(devVec2);
cudaFree(devVec3);
delete[] vec1; vec1 = 0;
delete[] vec2; vec2 = 0;
delete[] vec3; vec3 = 0;
return 0;
} | .file "tmpxft_0016f392_00000000-6_cudaProgrammTesting.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.type _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, @function
_Z32__device_stub__Z9addVectorPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, .-_Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.globl _Z9addVectorPfS_S_
.type _Z9addVectorPfS_S_, @function
_Z9addVectorPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addVectorPfS_S_, .-_Z9addVectorPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Doshchinsky/GPU-Programming/master/Lab-2/cudaProgrammTesting.cu"
.align 8
.LC1:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "gTest took %g\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbp
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbx
movl $8192, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $2048, %rax
jne .L12
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq 48(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L18:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L36
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L37
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L38
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L39
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L40
movl $2, %ecx
movl $8192, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L41
movl $2048, %eax
.L24:
subl $1, %eax
jne .L24
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $44, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $45, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $46, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $48, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $49, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
jmp .L18
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $57, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $58, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $61, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $62, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $63, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $64, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9addVectorPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <cuda.h>
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", cudaGetErrorString(_m_cudaStat),__LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
#define SIZE 2048
__host__ int main()
{
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//Âûäåëÿåì ïàìÿòü ïîä âåêòîðà
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
// printf("#%d\t%f\t %f\n", i, vec1[i], vec2[i]);
}
float* devVec1;
float* devVec2;
float* devVec3;
CUDA_CHECK_RETURN(cudaMalloc((void**)&devVec1, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(cudaMalloc((void**)&devVec2, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(cudaMalloc((void**)&devVec3, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(cudaMemcpy(devVec1, vec1, sizeof(float) * SIZE, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(devVec2, vec2, sizeof(float) * SIZE, cudaMemcpyHostToDevice));
dim3 block(512);
cudaEventRecord(start,0);
addVector <<<SIZE/512, block >>>(devVec1, devVec2, devVec3);
cudaEventRecord(stop, 0);
CUDA_CHECK_RETURN(cudaEventSynchronize(stop));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&elapsedTime, start, stop));
cudaEvent_t syncEvent;
CUDA_CHECK_RETURN(cudaEventCreate(&syncEvent));
CUDA_CHECK_RETURN(cudaEventRecord(syncEvent, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(syncEvent));
CUDA_CHECK_RETURN(cudaMemcpy(vec3, devVec3, sizeof(float) * SIZE, cudaMemcpyDeviceToHost));
for (int i = 0; i < SIZE; i++)
{
//printf("Element #%i: %.1f\n", i, vec3[i]);
}
fprintf(stderr,"gTest took %g\n",elapsedTime);
cudaEventDestroy(syncEvent);
cudaFree(devVec1);
cudaFree(devVec2);
cudaFree(devVec3);
delete[] vec1; vec1 = 0;
delete[] vec2; vec2 = 0;
delete[] vec3; vec3 = 0;
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", hipGetErrorString(_m_cudaStat),__LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
#define SIZE 2048
__host__ int main()
{
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//Âûäåëÿåì ïàìÿòü ïîä âåêòîðà
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
// printf("#%d\t%f\t %f\n", i, vec1[i], vec2[i]);
}
float* devVec1;
float* devVec2;
float* devVec3;
CUDA_CHECK_RETURN(hipMalloc((void**)&devVec1, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(hipMalloc((void**)&devVec2, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(hipMalloc((void**)&devVec3, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(hipMemcpy(devVec1, vec1, sizeof(float) * SIZE, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMemcpy(devVec2, vec2, sizeof(float) * SIZE, hipMemcpyHostToDevice));
dim3 block(512);
hipEventRecord(start,0);
addVector <<<SIZE/512, block >>>(devVec1, devVec2, devVec3);
hipEventRecord(stop, 0);
CUDA_CHECK_RETURN(hipEventSynchronize(stop));
CUDA_CHECK_RETURN(hipEventElapsedTime(&elapsedTime, start, stop));
hipEvent_t syncEvent;
CUDA_CHECK_RETURN(hipEventCreate(&syncEvent));
CUDA_CHECK_RETURN(hipEventRecord(syncEvent, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(syncEvent));
CUDA_CHECK_RETURN(hipMemcpy(vec3, devVec3, sizeof(float) * SIZE, hipMemcpyDeviceToHost));
for (int i = 0; i < SIZE; i++)
{
//printf("Element #%i: %.1f\n", i, vec3[i]);
}
fprintf(stderr,"gTest took %g\n",elapsedTime);
hipEventDestroy(syncEvent);
hipFree(devVec1);
hipFree(devVec2);
hipFree(devVec3);
delete[] vec1; vec1 = 0;
delete[] vec2; vec2 = 0;
delete[] vec3; vec3 = 0;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", hipGetErrorString(_m_cudaStat),__LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
#define SIZE 2048
__host__ int main()
{
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//Âûäåëÿåì ïàìÿòü ïîä âåêòîðà
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
// printf("#%d\t%f\t %f\n", i, vec1[i], vec2[i]);
}
float* devVec1;
float* devVec2;
float* devVec3;
CUDA_CHECK_RETURN(hipMalloc((void**)&devVec1, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(hipMalloc((void**)&devVec2, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(hipMalloc((void**)&devVec3, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(hipMemcpy(devVec1, vec1, sizeof(float) * SIZE, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMemcpy(devVec2, vec2, sizeof(float) * SIZE, hipMemcpyHostToDevice));
dim3 block(512);
hipEventRecord(start,0);
addVector <<<SIZE/512, block >>>(devVec1, devVec2, devVec3);
hipEventRecord(stop, 0);
CUDA_CHECK_RETURN(hipEventSynchronize(stop));
CUDA_CHECK_RETURN(hipEventElapsedTime(&elapsedTime, start, stop));
hipEvent_t syncEvent;
CUDA_CHECK_RETURN(hipEventCreate(&syncEvent));
CUDA_CHECK_RETURN(hipEventRecord(syncEvent, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(syncEvent));
CUDA_CHECK_RETURN(hipMemcpy(vec3, devVec3, sizeof(float) * SIZE, hipMemcpyDeviceToHost));
for (int i = 0; i < SIZE; i++)
{
//printf("Element #%i: %.1f\n", i, vec3[i]);
}
fprintf(stderr,"gTest took %g\n",elapsedTime);
hipEventDestroy(syncEvent);
hipFree(devVec1);
hipFree(devVec2);
hipFree(devVec3);
delete[] vec1; vec1 = 0;
delete[] vec2; vec2 = 0;
delete[] vec3; vec3 = 0;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addVectorPfS_S_
.globl _Z9addVectorPfS_S_
.p2align 8
.type _Z9addVectorPfS_S_,@function
_Z9addVectorPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addVectorPfS_S_, .Lfunc_end0-_Z9addVectorPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addVectorPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", hipGetErrorString(_m_cudaStat),__LINE__, __FILE__);\
exit(1);\
}\
}
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
#define SIZE 2048
__host__ int main()
{
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//Âûäåëÿåì ïàìÿòü ïîä âåêòîðà
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
// printf("#%d\t%f\t %f\n", i, vec1[i], vec2[i]);
}
float* devVec1;
float* devVec2;
float* devVec3;
CUDA_CHECK_RETURN(hipMalloc((void**)&devVec1, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(hipMalloc((void**)&devVec2, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(hipMalloc((void**)&devVec3, sizeof(float) * SIZE));
CUDA_CHECK_RETURN(hipMemcpy(devVec1, vec1, sizeof(float) * SIZE, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMemcpy(devVec2, vec2, sizeof(float) * SIZE, hipMemcpyHostToDevice));
dim3 block(512);
hipEventRecord(start,0);
addVector <<<SIZE/512, block >>>(devVec1, devVec2, devVec3);
hipEventRecord(stop, 0);
CUDA_CHECK_RETURN(hipEventSynchronize(stop));
CUDA_CHECK_RETURN(hipEventElapsedTime(&elapsedTime, start, stop));
hipEvent_t syncEvent;
CUDA_CHECK_RETURN(hipEventCreate(&syncEvent));
CUDA_CHECK_RETURN(hipEventRecord(syncEvent, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(syncEvent));
CUDA_CHECK_RETURN(hipMemcpy(vec3, devVec3, sizeof(float) * SIZE, hipMemcpyDeviceToHost));
for (int i = 0; i < SIZE; i++)
{
//printf("Element #%i: %.1f\n", i, vec3[i]);
}
fprintf(stderr,"gTest took %g\n",elapsedTime);
hipEventDestroy(syncEvent);
hipFree(devVec1);
hipFree(devVec2);
hipFree(devVec3);
delete[] vec1; vec1 = 0;
delete[] vec2; vec2 = 0;
delete[] vec3; vec3 = 0;
return 0;
} | .text
.file "cudaProgrammTesting.hip"
.globl _Z24__device_stub__addVectorPfS_S_ # -- Begin function _Z24__device_stub__addVectorPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addVectorPfS_S_,@function
_Z24__device_stub__addVectorPfS_S_: # @_Z24__device_stub__addVectorPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addVectorPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addVectorPfS_S_, .Lfunc_end0-_Z24__device_stub__addVectorPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.4:
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.6:
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
# %bb.8:
movq 24(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
# %bb.10:
movq 16(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 508(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addVectorPfS_S_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_17
# %bb.18:
leaq 64(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_19
# %bb.20:
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_21
# %bb.22:
movq 64(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_23
# %bb.24:
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq stderr(%rip), %rdi
testl %eax, %eax
jne .LBB1_25
# %bb.27: # %.preheader.preheader
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
movq 64(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $44, %ecx
jmp .LBB1_26
.LBB1_5:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $45, %ecx
jmp .LBB1_26
.LBB1_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $46, %ecx
jmp .LBB1_26
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $48, %ecx
jmp .LBB1_26
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $49, %ecx
jmp .LBB1_26
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $57, %ecx
jmp .LBB1_26
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $58, %ecx
jmp .LBB1_26
.LBB1_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $61, %ecx
jmp .LBB1_26
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $62, %ecx
jmp .LBB1_26
.LBB1_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $63, %ecx
jmp .LBB1_26
.LBB1_25:
movq %rdi, %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $64, %ecx
.LBB1_26:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addVectorPfS_S_,@object # @_Z9addVectorPfS_S_
.section .rodata,"a",@progbits
.globl _Z9addVectorPfS_S_
.p2align 3, 0x0
_Z9addVectorPfS_S_:
.quad _Z24__device_stub__addVectorPfS_S_
.size _Z9addVectorPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %s at line %d in file %s\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Doshchinsky/GPU-Programming/master/Lab-2/cudaProgrammTesting.hip"
.size .L.str.1, 122
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "gTest took %g\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addVectorPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addVectorPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addVectorPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addVectorPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addVectorPfS_S_
.globl _Z9addVectorPfS_S_
.p2align 8
.type _Z9addVectorPfS_S_,@function
_Z9addVectorPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addVectorPfS_S_, .Lfunc_end0-_Z9addVectorPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addVectorPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016f392_00000000-6_cudaProgrammTesting.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.type _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, @function
_Z32__device_stub__Z9addVectorPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, .-_Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.globl _Z9addVectorPfS_S_
.type _Z9addVectorPfS_S_, @function
_Z9addVectorPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addVectorPfS_S_, .-_Z9addVectorPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Doshchinsky/GPU-Programming/master/Lab-2/cudaProgrammTesting.cu"
.align 8
.LC1:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "gTest took %g\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbp
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbx
movl $8192, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $2048, %rax
jne .L12
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq 48(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L18:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L36
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L37
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L38
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L39
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L40
movl $2, %ecx
movl $8192, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L41
movl $2048, %eax
.L24:
subl $1, %eax
jne .L24
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $44, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $45, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $46, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $48, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $49, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
jmp .L18
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $57, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $58, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $61, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $62, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $63, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $64, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9addVectorPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaProgrammTesting.hip"
.globl _Z24__device_stub__addVectorPfS_S_ # -- Begin function _Z24__device_stub__addVectorPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addVectorPfS_S_,@function
_Z24__device_stub__addVectorPfS_S_: # @_Z24__device_stub__addVectorPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addVectorPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addVectorPfS_S_, .Lfunc_end0-_Z24__device_stub__addVectorPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.4:
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.6:
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
# %bb.8:
movq 24(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
# %bb.10:
movq 16(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 508(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addVectorPfS_S_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_17
# %bb.18:
leaq 64(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_19
# %bb.20:
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_21
# %bb.22:
movq 64(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_23
# %bb.24:
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq stderr(%rip), %rdi
testl %eax, %eax
jne .LBB1_25
# %bb.27: # %.preheader.preheader
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
movq 64(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $44, %ecx
jmp .LBB1_26
.LBB1_5:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $45, %ecx
jmp .LBB1_26
.LBB1_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $46, %ecx
jmp .LBB1_26
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $48, %ecx
jmp .LBB1_26
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $49, %ecx
jmp .LBB1_26
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $57, %ecx
jmp .LBB1_26
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $58, %ecx
jmp .LBB1_26
.LBB1_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $61, %ecx
jmp .LBB1_26
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $62, %ecx
jmp .LBB1_26
.LBB1_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $63, %ecx
jmp .LBB1_26
.LBB1_25:
movq %rdi, %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $64, %ecx
.LBB1_26:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addVectorPfS_S_,@object # @_Z9addVectorPfS_S_
.section .rodata,"a",@progbits
.globl _Z9addVectorPfS_S_
.p2align 3, 0x0
_Z9addVectorPfS_S_:
.quad _Z24__device_stub__addVectorPfS_S_
.size _Z9addVectorPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %s at line %d in file %s\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Doshchinsky/GPU-Programming/master/Lab-2/cudaProgrammTesting.hip"
.size .L.str.1, 122
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "gTest took %g\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addVectorPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addVectorPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addVectorPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* check-thread-index.cu */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#define CHECK_CUDA_CALL(call) \
{ \
const cudaError_t error = call; \
\
if (error != cudaSuccess) { \
fprintf(stderr, "Error (%s:%d), code: %d, reason: %s\n", \
__FILE__, __LINE__, \
error, cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
} \
void printMatrix(int* matC, int row, int col)
{
int i;
int j;
int* pC = matC;
printf("Matrix (%d, %d)\n", row, col);
for (i = 0; i < row; ++i) {
for (j = 0; j < col; ++j)
printf("%2d ", pC[j]);
printf("\n");
pC += col;
}
printf("\n");
return;
}
__global__ void printThreadIndex(int* matA, int row, int col)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int i = y * col + x;
printf("threadIdx: (%d, %d, %d), blockIdx: (%d, %d, %d), "
"coordinate: (%d, %d), array index: %d, "
"matrix value: %d\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
x, y, i, matA[i]);
}
int main(int argc, char** argv)
{
int i;
int dev;
cudaDeviceProp deviceProp;
int matRow;
int matCol;
int numOfElements;
int numOfBytes;
int* hostMatA;
int* devMatA;
/* Setup device */
dev = 0;
CHECK_CUDA_CALL(cudaGetDeviceProperties(&deviceProp, dev));
printf("Using device %d: %s\n", dev, deviceProp.name);
CHECK_CUDA_CALL(cudaSetDevice(dev));
/* Set matrix size */
matCol = 8;
matRow = 6;
numOfElements = matRow * matCol;
numOfBytes = numOfElements * sizeof(int);
/* Allocate host memory */
hostMatA = (int*)calloc(numOfElements, sizeof(int));
for (i = 0; i < numOfElements; ++i)
hostMatA[i] = i;
printMatrix(hostMatA, matRow, matCol);
/* Allocate device memory */
CHECK_CUDA_CALL(cudaMalloc((void**)&devMatA, numOfBytes));
/* Set execution configuration */
dim3 block(4, 2);
dim3 grid((matCol + block.x - 1) / block.x, (matRow + block.y - 1) / block.y);
/* Transfer matrix data from host */
CHECK_CUDA_CALL(cudaMemcpy(devMatA, hostMatA, numOfBytes, cudaMemcpyHostToDevice));
/* Call kernel from host */
printThreadIndex<<<grid, block>>>(devMatA, matRow, matCol);
CHECK_CUDA_CALL(cudaDeviceSynchronize());
/* Free device and host memory */
CHECK_CUDA_CALL(cudaFree(devMatA));
free(hostMatA);
/* Reset device */
CHECK_CUDA_CALL(cudaDeviceReset());
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z16printThreadIndexPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x28, RZ ; /* 0xffffffd801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002100 */
/*0060*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e680000002500 */
/*0070*/ S2R R14, SR_CTAID.Y ; /* 0x00000000000e7919 */
/* 0x000e220000002600 */
/*0080*/ IMAD R2, R17, c[0x0][0x0], R12 ; /* 0x0000000011027a24 */
/* 0x002fc400078e020c */
/*0090*/ IMAD R3, R14, c[0x0][0x4], R13 ; /* 0x000001000e037a24 */
/* 0x001fc800078e020d */
/*00a0*/ IMAD R8, R3, c[0x0][0x16c], R2 ; /* 0x00005b0003087a24 */
/* 0x000fc800078e0202 */
/*00b0*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fca00078e0005 */
/*00c0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a2000c1e1900 */
/*00d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00e0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ S2R R16, SR_TID.Z ; /* 0x0000000000107919 */
/* 0x000e620000002300 */
/*0100*/ LDC.64 R10, c[0x4][R0] ; /* 0x01000000000a7b82 */
/* 0x0007260000000a00 */
/*0110*/ S2R R15, SR_CTAID.Z ; /* 0x00000000000f7919 */
/* 0x000f620000002700 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x001fe200078e00ff */
/*0140*/ STL.64 [R1], R12 ; /* 0x0000000c01007387 */
/* 0x0007e20000100a00 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*0160*/ STL.64 [R1+0x18], R2 ; /* 0x0000180201007387 */
/* 0x0007e80000100a00 */
/*0170*/ STL.64 [R1+0x8], R16 ; /* 0x0000081001007387 */
/* 0x0027e80000100a00 */
/*0180*/ STL.64 [R1+0x10], R14 ; /* 0x0000100e01007387 */
/* 0x0207e80000100a00 */
/*0190*/ STL.64 [R1+0x20], R8 ; /* 0x0000200801007387 */
/* 0x0047e40000100a00 */
/*01a0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x018fe40000000000 */
/*01b0*/ MOV R9, 0x220 ; /* 0x0000022000097802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R20, 0x1a0 ; /* 0x000001a000147802 */
/* 0x000fc40000000f00 */
/*01d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01f0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0200*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0210*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x000fea0003c00000 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* check-thread-index.cu */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#define CHECK_CUDA_CALL(call) \
{ \
const cudaError_t error = call; \
\
if (error != cudaSuccess) { \
fprintf(stderr, "Error (%s:%d), code: %d, reason: %s\n", \
__FILE__, __LINE__, \
error, cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
} \
void printMatrix(int* matC, int row, int col)
{
int i;
int j;
int* pC = matC;
printf("Matrix (%d, %d)\n", row, col);
for (i = 0; i < row; ++i) {
for (j = 0; j < col; ++j)
printf("%2d ", pC[j]);
printf("\n");
pC += col;
}
printf("\n");
return;
}
__global__ void printThreadIndex(int* matA, int row, int col)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int i = y * col + x;
printf("threadIdx: (%d, %d, %d), blockIdx: (%d, %d, %d), "
"coordinate: (%d, %d), array index: %d, "
"matrix value: %d\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
x, y, i, matA[i]);
}
int main(int argc, char** argv)
{
int i;
int dev;
cudaDeviceProp deviceProp;
int matRow;
int matCol;
int numOfElements;
int numOfBytes;
int* hostMatA;
int* devMatA;
/* Setup device */
dev = 0;
CHECK_CUDA_CALL(cudaGetDeviceProperties(&deviceProp, dev));
printf("Using device %d: %s\n", dev, deviceProp.name);
CHECK_CUDA_CALL(cudaSetDevice(dev));
/* Set matrix size */
matCol = 8;
matRow = 6;
numOfElements = matRow * matCol;
numOfBytes = numOfElements * sizeof(int);
/* Allocate host memory */
hostMatA = (int*)calloc(numOfElements, sizeof(int));
for (i = 0; i < numOfElements; ++i)
hostMatA[i] = i;
printMatrix(hostMatA, matRow, matCol);
/* Allocate device memory */
CHECK_CUDA_CALL(cudaMalloc((void**)&devMatA, numOfBytes));
/* Set execution configuration */
dim3 block(4, 2);
dim3 grid((matCol + block.x - 1) / block.x, (matRow + block.y - 1) / block.y);
/* Transfer matrix data from host */
CHECK_CUDA_CALL(cudaMemcpy(devMatA, hostMatA, numOfBytes, cudaMemcpyHostToDevice));
/* Call kernel from host */
printThreadIndex<<<grid, block>>>(devMatA, matRow, matCol);
CHECK_CUDA_CALL(cudaDeviceSynchronize());
/* Free device and host memory */
CHECK_CUDA_CALL(cudaFree(devMatA));
free(hostMatA);
/* Reset device */
CHECK_CUDA_CALL(cudaDeviceReset());
return EXIT_SUCCESS;
} | .file "tmpxft_0012409b_00000000-6_check-thread-index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix (%d, %d)\n"
.LC1:
.string "%2d "
.LC2:
.string "\n"
.text
.globl _Z11printMatrixPiii
.type _Z11printMatrixPiii, @function
_Z11printMatrixPiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebx
movl %esi, 8(%rsp)
movl %edx, %r14d
movl %edx, 12(%rsp)
movl %edx, %ecx
movl %esi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L4
movslq %r14d, %r15
salq $2, %r15
leaq 0(%r13,%r15), %rbp
movl $0, %r14d
leaq .LC1(%rip), %r12
jmp .L5
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r15, %r13
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 8(%rsp)
je .L4
.L5:
movq %r13, %rbx
cmpl $0, 12(%rsp)
jg .L6
jmp .L8
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPiii, .-_Z11printMatrixPiii
.globl _Z38__device_stub__Z16printThreadIndexPiiiPiii
.type _Z38__device_stub__Z16printThreadIndexPiiiPiii, @function
_Z38__device_stub__Z16printThreadIndexPiiiPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16printThreadIndexPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z16printThreadIndexPiiiPiii, .-_Z38__device_stub__Z16printThreadIndexPiiiPiii
.globl _Z16printThreadIndexPiii
.type _Z16printThreadIndexPiii, @function
_Z16printThreadIndexPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16printThreadIndexPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16printThreadIndexPiii, .-_Z16printThreadIndexPiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/sterngerlach/cuda-training/master/check-thread-index.cu"
.align 8
.LC4:
.string "Error (%s:%d), code: %d, reason: %s\n"
.section .rodata.str1.1
.LC5:
.string "Using device %d: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1080, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L33
leaq 32(%rsp), %rcx
movl $0, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
movl $4, %esi
movl $48, %edi
call calloc@PLT
movq %rax, %rbx
movl $0, %eax
.L23:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $48, %rax
jne .L23
movl $8, %edx
movl $6, %esi
movq %rbx, %rdi
call _Z11printMatrixPiii
movq %rsp, %rdi
movl $192, %esi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L35
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, %ecx
movl $192, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L36
movl $4, 8(%rsp)
movl $2, 12(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L26:
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L38
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L39
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebx, %r9d
movl $74, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebx, %r9d
movl $78, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebp, %r9d
movl $95, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebp, %r9d
movl $102, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
.cfi_restore_state
movl $8, %edx
movl $6, %esi
movq (%rsp), %rdi
call _Z38__device_stub__Z16printThreadIndexPiiiPiii
jmp .L26
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebp, %r9d
movl $106, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebp, %r9d
movl $109, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebx, %r9d
movl $113, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16printThreadIndexPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16printThreadIndexPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* check-thread-index.cu */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#define CHECK_CUDA_CALL(call) \
{ \
const cudaError_t error = call; \
\
if (error != cudaSuccess) { \
fprintf(stderr, "Error (%s:%d), code: %d, reason: %s\n", \
__FILE__, __LINE__, \
error, cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
} \
void printMatrix(int* matC, int row, int col)
{
int i;
int j;
int* pC = matC;
printf("Matrix (%d, %d)\n", row, col);
for (i = 0; i < row; ++i) {
for (j = 0; j < col; ++j)
printf("%2d ", pC[j]);
printf("\n");
pC += col;
}
printf("\n");
return;
}
__global__ void printThreadIndex(int* matA, int row, int col)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int i = y * col + x;
printf("threadIdx: (%d, %d, %d), blockIdx: (%d, %d, %d), "
"coordinate: (%d, %d), array index: %d, "
"matrix value: %d\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
x, y, i, matA[i]);
}
int main(int argc, char** argv)
{
int i;
int dev;
cudaDeviceProp deviceProp;
int matRow;
int matCol;
int numOfElements;
int numOfBytes;
int* hostMatA;
int* devMatA;
/* Setup device */
dev = 0;
CHECK_CUDA_CALL(cudaGetDeviceProperties(&deviceProp, dev));
printf("Using device %d: %s\n", dev, deviceProp.name);
CHECK_CUDA_CALL(cudaSetDevice(dev));
/* Set matrix size */
matCol = 8;
matRow = 6;
numOfElements = matRow * matCol;
numOfBytes = numOfElements * sizeof(int);
/* Allocate host memory */
hostMatA = (int*)calloc(numOfElements, sizeof(int));
for (i = 0; i < numOfElements; ++i)
hostMatA[i] = i;
printMatrix(hostMatA, matRow, matCol);
/* Allocate device memory */
CHECK_CUDA_CALL(cudaMalloc((void**)&devMatA, numOfBytes));
/* Set execution configuration */
dim3 block(4, 2);
dim3 grid((matCol + block.x - 1) / block.x, (matRow + block.y - 1) / block.y);
/* Transfer matrix data from host */
CHECK_CUDA_CALL(cudaMemcpy(devMatA, hostMatA, numOfBytes, cudaMemcpyHostToDevice));
/* Call kernel from host */
printThreadIndex<<<grid, block>>>(devMatA, matRow, matCol);
CHECK_CUDA_CALL(cudaDeviceSynchronize());
/* Free device and host memory */
CHECK_CUDA_CALL(cudaFree(devMatA));
free(hostMatA);
/* Reset device */
CHECK_CUDA_CALL(cudaDeviceReset());
return EXIT_SUCCESS;
} | /* check-thread-index.cu */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define CHECK_CUDA_CALL(call) \
{ \
const hipError_t error = call; \
\
if (error != hipSuccess) { \
fprintf(stderr, "Error (%s:%d), code: %d, reason: %s\n", \
__FILE__, __LINE__, \
error, hipGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
} \
void printMatrix(int* matC, int row, int col)
{
int i;
int j;
int* pC = matC;
printf("Matrix (%d, %d)\n", row, col);
for (i = 0; i < row; ++i) {
for (j = 0; j < col; ++j)
printf("%2d ", pC[j]);
printf("\n");
pC += col;
}
printf("\n");
return;
}
__global__ void printThreadIndex(int* matA, int row, int col)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int i = y * col + x;
printf("threadIdx: (%d, %d, %d), blockIdx: (%d, %d, %d), "
"coordinate: (%d, %d), array index: %d, "
"matrix value: %d\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
x, y, i, matA[i]);
}
int main(int argc, char** argv)
{
int i;
int dev;
hipDeviceProp_t deviceProp;
int matRow;
int matCol;
int numOfElements;
int numOfBytes;
int* hostMatA;
int* devMatA;
/* Setup device */
dev = 0;
CHECK_CUDA_CALL(hipGetDeviceProperties(&deviceProp, dev));
printf("Using device %d: %s\n", dev, deviceProp.name);
CHECK_CUDA_CALL(hipSetDevice(dev));
/* Set matrix size */
matCol = 8;
matRow = 6;
numOfElements = matRow * matCol;
numOfBytes = numOfElements * sizeof(int);
/* Allocate host memory */
hostMatA = (int*)calloc(numOfElements, sizeof(int));
for (i = 0; i < numOfElements; ++i)
hostMatA[i] = i;
printMatrix(hostMatA, matRow, matCol);
/* Allocate device memory */
CHECK_CUDA_CALL(hipMalloc((void**)&devMatA, numOfBytes));
/* Set execution configuration */
dim3 block(4, 2);
dim3 grid((matCol + block.x - 1) / block.x, (matRow + block.y - 1) / block.y);
/* Transfer matrix data from host */
CHECK_CUDA_CALL(hipMemcpy(devMatA, hostMatA, numOfBytes, hipMemcpyHostToDevice));
/* Call kernel from host */
printThreadIndex<<<grid, block>>>(devMatA, matRow, matCol);
CHECK_CUDA_CALL(hipDeviceSynchronize());
/* Free device and host memory */
CHECK_CUDA_CALL(hipFree(devMatA));
free(hostMatA);
/* Reset device */
CHECK_CUDA_CALL(hipDeviceReset());
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* check-thread-index.cu */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define CHECK_CUDA_CALL(call) \
{ \
const hipError_t error = call; \
\
if (error != hipSuccess) { \
fprintf(stderr, "Error (%s:%d), code: %d, reason: %s\n", \
__FILE__, __LINE__, \
error, hipGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
} \
void printMatrix(int* matC, int row, int col)
{
int i;
int j;
int* pC = matC;
printf("Matrix (%d, %d)\n", row, col);
for (i = 0; i < row; ++i) {
for (j = 0; j < col; ++j)
printf("%2d ", pC[j]);
printf("\n");
pC += col;
}
printf("\n");
return;
}
__global__ void printThreadIndex(int* matA, int row, int col)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int i = y * col + x;
printf("threadIdx: (%d, %d, %d), blockIdx: (%d, %d, %d), "
"coordinate: (%d, %d), array index: %d, "
"matrix value: %d\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
x, y, i, matA[i]);
}
int main(int argc, char** argv)
{
int i;
int dev;
hipDeviceProp_t deviceProp;
int matRow;
int matCol;
int numOfElements;
int numOfBytes;
int* hostMatA;
int* devMatA;
/* Setup device */
dev = 0;
CHECK_CUDA_CALL(hipGetDeviceProperties(&deviceProp, dev));
printf("Using device %d: %s\n", dev, deviceProp.name);
CHECK_CUDA_CALL(hipSetDevice(dev));
/* Set matrix size */
matCol = 8;
matRow = 6;
numOfElements = matRow * matCol;
numOfBytes = numOfElements * sizeof(int);
/* Allocate host memory */
hostMatA = (int*)calloc(numOfElements, sizeof(int));
for (i = 0; i < numOfElements; ++i)
hostMatA[i] = i;
printMatrix(hostMatA, matRow, matCol);
/* Allocate device memory */
CHECK_CUDA_CALL(hipMalloc((void**)&devMatA, numOfBytes));
/* Set execution configuration */
dim3 block(4, 2);
dim3 grid((matCol + block.x - 1) / block.x, (matRow + block.y - 1) / block.y);
/* Transfer matrix data from host */
CHECK_CUDA_CALL(hipMemcpy(devMatA, hostMatA, numOfBytes, hipMemcpyHostToDevice));
/* Call kernel from host */
printThreadIndex<<<grid, block>>>(devMatA, matRow, matCol);
CHECK_CUDA_CALL(hipDeviceSynchronize());
/* Free device and host memory */
CHECK_CUDA_CALL(hipFree(devMatA));
free(hostMatA);
/* Reset device */
CHECK_CUDA_CALL(hipDeviceReset());
return EXIT_SUCCESS;
} | .text
.file "check-thread-index.hip"
.globl _Z11printMatrixPiii # -- Begin function _Z11printMatrixPiii
.p2align 4, 0x90
.type _Z11printMatrixPiii,@function
_Z11printMatrixPiii: # @_Z11printMatrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movl $.L.str, %edi
movl %edx, 4(%rsp) # 4-byte Spill
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ebp
movl 4(%rsp), %eax # 4-byte Reload
movslq %eax, %r15
movl %eax, %r12d
shlq $2, %r15
xorl %r13d, %r13d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r13d
addq %r15, %r14
cmpl %ebp, %r13d
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge19
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPiii, .Lfunc_end0-_Z11printMatrixPiii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__printThreadIndexPiii # -- Begin function _Z31__device_stub__printThreadIndexPiii
.p2align 4, 0x90
.type _Z31__device_stub__printThreadIndexPiii,@function
_Z31__device_stub__printThreadIndexPiii: # @_Z31__device_stub__printThreadIndexPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16printThreadIndexPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__printThreadIndexPiii, .Lfunc_end1-_Z31__device_stub__printThreadIndexPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 104(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 104(%rsp), %rdx
movl $.L.str.5, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_4
# %bb.5:
movl $48, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $48, %rax
jne .LBB2_6
# %bb.7:
movl $.L.str, %edi
movl $6, %esi
movl $8, %edx
xorl %eax, %eax
callq printf
movq %rbx, %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_8: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_9: # %.lr.ph.i
# Parent Loop BB2_8 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $8, %r15
jne .LBB2_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB2_8 Depth=1
movl $10, %edi
callq putchar@PLT
addq $32, %r14
incl %ebp
cmpl $6, %ebp
jne .LBB2_8
# %bb.11: # %_Z11printMatrixPiii.exit
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $192, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movq 8(%rsp), %rdi
movl $192, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_14
# %bb.15:
movabsq $12884901890, %rdi # imm = 0x300000002
movabsq $8589934596, %rdx # imm = 0x200000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.16:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $6, 20(%rsp)
movl $8, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16printThreadIndexPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_17:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_18
# %bb.19:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_20
# %bb.21:
movq %rbx, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_22
# %bb.23:
xorl %eax, %eax
addq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 1616
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $74, %ecx
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $78, %ecx
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $95, %ecx
jmp .LBB2_2
.LBB2_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $102, %ecx
jmp .LBB2_2
.LBB2_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $106, %ecx
jmp .LBB2_2
.LBB2_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $109, %ecx
jmp .LBB2_2
.LBB2_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $113, %ecx
.LBB2_2:
movl %ebp, %r8d
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16printThreadIndexPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Matrix (%d, %d)\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%2d "
.size .L.str.1, 5
.type _Z16printThreadIndexPiii,@object # @_Z16printThreadIndexPiii
.section .rodata,"a",@progbits
.globl _Z16printThreadIndexPiii
.p2align 3, 0x0
_Z16printThreadIndexPiii:
.quad _Z31__device_stub__printThreadIndexPiii
.size _Z16printThreadIndexPiii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Error (%s:%d), code: %d, reason: %s\n"
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/sterngerlach/cuda-training/master/check-thread-index.hip"
.size .L.str.4, 114
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using device %d: %s\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16printThreadIndexPiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__printThreadIndexPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16printThreadIndexPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012409b_00000000-6_check-thread-index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix (%d, %d)\n"
.LC1:
.string "%2d "
.LC2:
.string "\n"
.text
.globl _Z11printMatrixPiii
.type _Z11printMatrixPiii, @function
_Z11printMatrixPiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebx
movl %esi, 8(%rsp)
movl %edx, %r14d
movl %edx, 12(%rsp)
movl %edx, %ecx
movl %esi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L4
movslq %r14d, %r15
salq $2, %r15
leaq 0(%r13,%r15), %rbp
movl $0, %r14d
leaq .LC1(%rip), %r12
jmp .L5
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r15, %r13
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 8(%rsp)
je .L4
.L5:
movq %r13, %rbx
cmpl $0, 12(%rsp)
jg .L6
jmp .L8
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPiii, .-_Z11printMatrixPiii
.globl _Z38__device_stub__Z16printThreadIndexPiiiPiii
.type _Z38__device_stub__Z16printThreadIndexPiiiPiii, @function
_Z38__device_stub__Z16printThreadIndexPiiiPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16printThreadIndexPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z16printThreadIndexPiiiPiii, .-_Z38__device_stub__Z16printThreadIndexPiiiPiii
.globl _Z16printThreadIndexPiii
.type _Z16printThreadIndexPiii, @function
_Z16printThreadIndexPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16printThreadIndexPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16printThreadIndexPiii, .-_Z16printThreadIndexPiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/sterngerlach/cuda-training/master/check-thread-index.cu"
.align 8
.LC4:
.string "Error (%s:%d), code: %d, reason: %s\n"
.section .rodata.str1.1
.LC5:
.string "Using device %d: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1080, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L33
leaq 32(%rsp), %rcx
movl $0, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
movl $4, %esi
movl $48, %edi
call calloc@PLT
movq %rax, %rbx
movl $0, %eax
.L23:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $48, %rax
jne .L23
movl $8, %edx
movl $6, %esi
movq %rbx, %rdi
call _Z11printMatrixPiii
movq %rsp, %rdi
movl $192, %esi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L35
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, %ecx
movl $192, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L36
movl $4, 8(%rsp)
movl $2, 12(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L26:
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L38
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L39
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebx, %r9d
movl $74, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebx, %r9d
movl $78, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebp, %r9d
movl $95, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebp, %r9d
movl $102, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
.cfi_restore_state
movl $8, %edx
movl $6, %esi
movq (%rsp), %rdi
call _Z38__device_stub__Z16printThreadIndexPiiiPiii
jmp .L26
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebp, %r9d
movl $106, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebp, %r9d
movl $109, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 1112
pushq %rax
.cfi_def_cfa_offset 1120
movl %ebx, %r9d
movl $113, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16printThreadIndexPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16printThreadIndexPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "check-thread-index.hip"
.globl _Z11printMatrixPiii # -- Begin function _Z11printMatrixPiii
.p2align 4, 0x90
.type _Z11printMatrixPiii,@function
_Z11printMatrixPiii: # @_Z11printMatrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movl $.L.str, %edi
movl %edx, 4(%rsp) # 4-byte Spill
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ebp
movl 4(%rsp), %eax # 4-byte Reload
movslq %eax, %r15
movl %eax, %r12d
shlq $2, %r15
xorl %r13d, %r13d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r13d
addq %r15, %r14
cmpl %ebp, %r13d
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge19
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPiii, .Lfunc_end0-_Z11printMatrixPiii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__printThreadIndexPiii # -- Begin function _Z31__device_stub__printThreadIndexPiii
.p2align 4, 0x90
.type _Z31__device_stub__printThreadIndexPiii,@function
_Z31__device_stub__printThreadIndexPiii: # @_Z31__device_stub__printThreadIndexPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16printThreadIndexPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__printThreadIndexPiii, .Lfunc_end1-_Z31__device_stub__printThreadIndexPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 104(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 104(%rsp), %rdx
movl $.L.str.5, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_4
# %bb.5:
movl $48, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $48, %rax
jne .LBB2_6
# %bb.7:
movl $.L.str, %edi
movl $6, %esi
movl $8, %edx
xorl %eax, %eax
callq printf
movq %rbx, %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_8: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_9: # %.lr.ph.i
# Parent Loop BB2_8 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $8, %r15
jne .LBB2_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB2_8 Depth=1
movl $10, %edi
callq putchar@PLT
addq $32, %r14
incl %ebp
cmpl $6, %ebp
jne .LBB2_8
# %bb.11: # %_Z11printMatrixPiii.exit
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $192, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movq 8(%rsp), %rdi
movl $192, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_14
# %bb.15:
movabsq $12884901890, %rdi # imm = 0x300000002
movabsq $8589934596, %rdx # imm = 0x200000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.16:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $6, 20(%rsp)
movl $8, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16printThreadIndexPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_17:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_18
# %bb.19:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_20
# %bb.21:
movq %rbx, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_22
# %bb.23:
xorl %eax, %eax
addq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 1616
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $74, %ecx
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $78, %ecx
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $95, %ecx
jmp .LBB2_2
.LBB2_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $102, %ecx
jmp .LBB2_2
.LBB2_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $106, %ecx
jmp .LBB2_2
.LBB2_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $109, %ecx
jmp .LBB2_2
.LBB2_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $113, %ecx
.LBB2_2:
movl %ebp, %r8d
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16printThreadIndexPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Matrix (%d, %d)\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%2d "
.size .L.str.1, 5
.type _Z16printThreadIndexPiii,@object # @_Z16printThreadIndexPiii
.section .rodata,"a",@progbits
.globl _Z16printThreadIndexPiii
.p2align 3, 0x0
_Z16printThreadIndexPiii:
.quad _Z31__device_stub__printThreadIndexPiii
.size _Z16printThreadIndexPiii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Error (%s:%d), code: %d, reason: %s\n"
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/sterngerlach/cuda-training/master/check-thread-index.hip"
.size .L.str.4, 114
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using device %d: %s\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16printThreadIndexPiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__printThreadIndexPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16printThreadIndexPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
const int listLength = 700;
__global__ void squareKernel(float* d_in, float *d_out, int threads_num) {
const unsigned int lid = threadIdx.x; // local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
if (gid < threads_num){
d_out[gid] = powf((d_in[gid]/(d_in[gid]-2.3)),3);
}// do computation
} | code for sm_80
Function : _Z12squareKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R10, R3, c[0x0][0x0], R10 ; /* 0x00000000030a7a24 */
/* 0x001fca00078e020a */
/*0040*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B0, 0x200 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*00c0*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x004e240000201800 */
/*00d0*/ DADD R6, R4, c[0x2][0x0] ; /* 0x0080000004067629 */
/* 0x001e220000000000 */
/*00e0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*00f0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e240000001800 */
/*0100*/ DFMA R12, -R6, R8, 1 ; /* 0x3ff00000060c742b */
/* 0x001e0c0000000108 */
/*0110*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0120*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001e0c0000000008 */
/*0130*/ DFMA R8, -R6, R12, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010c */
/*0140*/ DFMA R8, R12, R8, R12 ; /* 0x000000080c08722b */
/* 0x001e0c000000000c */
/*0150*/ DMUL R12, R4, R8 ; /* 0x00000008040c7228 */
/* 0x001e0c0000000000 */
/*0160*/ DFMA R2, -R6, R12, R4 ; /* 0x0000000c0602722b */
/* 0x001e0c0000000104 */
/*0170*/ DFMA R2, R8, R2, R12 ; /* 0x000000020802722b */
/* 0x001e14000000000c */
/*0180*/ FFMA R0, RZ, R7, R3 ; /* 0x00000007ff007223 */
/* 0x001fca0000000003 */
/*0190*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*01a0*/ @P0 BRA P1, 0x1f0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01b0*/ MOV R0, 0x1d0 ; /* 0x000001d000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x710 ; /* 0x0000054000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000c */
/*01e0*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x000fe40000000f00 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ F2F.F32.F64 R0, R2 ; /* 0x0000000200007310 */
/* 0x000ea20000301000 */
/*0210*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3a2c32e4 ; /* 0x3a2c32e4ff0c7424 */
/* 0x000fe200078e00ff */
/*0220*/ BSSY B0, 0x6d0 ; /* 0x000004a000007945 */
/* 0x000fe20003800000 */
/*0230*/ FMUL R5, |R0|.reuse, 16777216 ; /* 0x4b80000000057820 */
/* 0x044fe20000400200 */
/*0240*/ FSETP.GEU.AND P0, PT, |R0|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x040fe40003f0e200 */
/*0250*/ FSETP.NEU.AND P2, PT, R0, 1, PT ; /* 0x3f8000000000780b */
/* 0x000fe40003f4d000 */
/*0260*/ FSEL R5, R5, |R0|, !P0 ; /* 0x4000000005057208 */
/* 0x000fe40004000000 */
/*0270*/ FSEL R2, RZ, -24, P0 ; /* 0xc1c00000ff027808 */
/* 0x000fc40000000000 */
/*0280*/ IADD3 R4, R5, -0x3f3504f3, RZ ; /* 0xc0cafb0d05047810 */
/* 0x000fc80007ffe0ff */
/*0290*/ LOP3.LUT R4, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004047812 */
/* 0x000fc800078ec0ff */
/*02a0*/ I2F R7, R4 ; /* 0x0000000400077306 */
/* 0x000ea20000201400 */
/*02b0*/ IMAD.IADD R5, R5, 0x1, -R4 ; /* 0x0000000105057824 */
/* 0x000fc800078e0a04 */
/*02c0*/ FADD R6, R5.reuse, 1 ; /* 0x3f80000005067421 */
/* 0x040fe40000000000 */
/*02d0*/ FADD R5, R5, -1 ; /* 0xbf80000005057421 */
/* 0x000fc80000000000 */
/*02e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x000ee20000001000 */
/*02f0*/ FADD R3, R5, R5 ; /* 0x0000000505037221 */
/* 0x000fe40000000000 */
/*0300*/ FFMA R2, R7, 1.1920928955078125e-07, R2 ; /* 0x3400000007027823 */
/* 0x004fe40000000002 */
/*0310*/ FMUL R8, R6, R3 ; /* 0x0000000306087220 */
/* 0x008fc80000400000 */
/*0320*/ FADD R7, R5, -R8 ; /* 0x8000000805077221 */
/* 0x000fe40000000000 */
/*0330*/ FMUL R3, R8.reuse, R8 ; /* 0x0000000808037220 */
/* 0x040fe40000400000 */
/*0340*/ FFMA R9, R8, 1.4426950216293334961, R2 ; /* 0x3fb8aa3b08097823 */
/* 0x000fe40000000002 */
/*0350*/ FADD R7, R7, R7 ; /* 0x0000000707077221 */
/* 0x000fe40000000000 */
/*0360*/ FFMA R4, R3, R12, 0.0032181653659790754318 ; /* 0x3b52e7db03047423 */
/* 0x000fe4000000000c */
/*0370*/ FADD R11, R2, -R9 ; /* 0x80000009020b7221 */
/* 0x000fc40000000000 */
/*0380*/ FFMA R7, R5, -R8, R7 ; /* 0x8000000805077223 */
/* 0x000fe40000000007 */
/*0390*/ FFMA R4, R3.reuse, R4, 0.018033718690276145935 ; /* 0x3c93bb7303047423 */
/* 0x040fe40000000004 */
/*03a0*/ FFMA R2, R8, 1.4426950216293334961, R11 ; /* 0x3fb8aa3b08027823 */
/* 0x000fe4000000000b */
/*03b0*/ FMUL R7, R6, R7 ; /* 0x0000000706077220 */
/* 0x000fe40000400000 */
/*03c0*/ FFMA R4, R3, R4, 0.12022458761930465698 ; /* 0x3df6384f03047423 */
/* 0x000fe40000000004 */
/*03d0*/ FFMA R5, R7, 1.4426950216293334961, R2 ; /* 0x3fb8aa3b07057823 */
/* 0x000fc40000000002 */
/*03e0*/ FMUL R3, R3, R4 ; /* 0x0000000403037220 */
/* 0x000fe40000400000 */
/*03f0*/ FFMA R2, R8, 1.9251366722983220825e-08, R5 ; /* 0x32a55e3408027823 */
/* 0x000fe40000000005 */
/*0400*/ FMUL R4, R3, 3 ; /* 0x4040000003047820 */
/* 0x000fc80000400000 */
/*0410*/ FFMA R2, R7, R4, R2 ; /* 0x0000000407027223 */
/* 0x000fe40000000002 */
/*0420*/ IMAD.MOV.U32 R7, RZ, RZ, 0x391fcb8e ; /* 0x391fcb8eff077424 */
/* 0x000fe400078e00ff */
/*0430*/ FFMA R2, R8, R3, R2 ; /* 0x0000000308027223 */
/* 0x000fc80000000002 */
/*0440*/ FADD R4, R9, R2 ; /* 0x0000000209047221 */
/* 0x000fc80000000000 */
/*0450*/ FMUL R3, R4.reuse, 3 ; /* 0x4040000004037820 */
/* 0x040fe40000400000 */
/*0460*/ FADD R9, -R9, R4 ; /* 0x0000000409097221 */
/* 0x000fe40000000100 */
/*0470*/ FRND R6, R3 ; /* 0x0000000300067307 */
/* 0x000ea20000201000 */
/*0480*/ FFMA R4, R4, 3, -R3 ; /* 0x4040000004047823 */
/* 0x000fe20000000803 */
/*0490*/ FSETP.GEU.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f2e000 */
/*04a0*/ FADD R9, R2, -R9 ; /* 0x8000000902097221 */
/* 0x000fc80000000000 */
/*04b0*/ FFMA R4, R9, 3, R4 ; /* 0x4040000009047823 */
/* 0x000fe20000000004 */
/*04c0*/ F2I.NTZ R2, R3 ; /* 0x0000000300027305 */
/* 0x000ee20000203100 */
/*04d0*/ FADD R5, R3, -R6 ; /* 0x8000000603057221 */
/* 0x004fe20000000000 */
/*04e0*/ FSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fc60003f04000 */
/*04f0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x000fc80000000000 */
/*0500*/ FFMA R5, R4.reuse, R7, 0.0013391353422775864601 ; /* 0x3aaf85ed04057423 */
/* 0x040fe20000000007 */
/*0510*/ SEL R7, RZ, 0x83000000, P0 ; /* 0x83000000ff077807 */
/* 0x000fe40000000000 */
/*0520*/ FSETP.GT.AND P0, PT, |R3|, 152, PT ; /* 0x431800000300780b */
/* 0x000fe20003f04200 */
/*0530*/ FFMA R5, R4, R5, 0.0096188392490148544312 ; /* 0x3c1d985604057423 */
/* 0x000fe20000000005 */
/*0540*/ IADD3 R6, R7, 0x7f000000, RZ ; /* 0x7f00000007067810 */
/* 0x000fe40007ffe0ff */
/*0550*/ LEA R2, R2, -R7, 0x17 ; /* 0x8000000702027211 */
/* 0x008fe200078eb8ff */
/*0560*/ FFMA R5, R4, R5, 0.055503588169813156128 ; /* 0x3d6357bb04057423 */
/* 0x000fc80000000005 */
/*0570*/ FFMA R5, R4, R5, 0.24022644758224487305 ; /* 0x3e75fdec04057423 */
/* 0x000fc80000000005 */
/*0580*/ FFMA R5, R4, R5, 0.69314718246459960938 ; /* 0x3f31721804057423 */
/* 0x000fc80000000005 */
/*0590*/ FFMA R5, R4, R5, 1 ; /* 0x3f80000004057423 */
/* 0x000fc80000000005 */
/*05a0*/ FMUL R5, R5, R6 ; /* 0x0000000605057220 */
/* 0x000fc80000400000 */
/*05b0*/ FMUL R2, R5, R2 ; /* 0x0000000205027220 */
/* 0x000fe20000400000 */
/*05c0*/ @P0 FSEL R2, RZ, +INF , !P1 ; /* 0x7f800000ff020808 */
/* 0x000fe20004800000 */
/*05d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff057424 */
/* 0x000fe200078e00ff */
/*05e0*/ @!P2 BRA 0x6c0 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.GTU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f0c200 */
/*0600*/ @P0 BRA 0x6b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0610*/ FSETP.NEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fc80003f0d000 */
/*0620*/ FSETP.EQ.OR P0, PT, |R0|, +INF , !P0 ; /* 0x7f8000000000780b */
/* 0x000fda0004702600 */
/*0630*/ @P0 BRA 0x690 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fe20003f0e000 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0002 */
/*0660*/ @P0 BRA 0x6c0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0670*/ FADD R5, -R2, -RZ ; /* 0x800000ff02057221 */
/* 0x000fe20000000100 */
/*0680*/ BRA 0x6c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0690*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x000fe20000000000 */
/*06a0*/ BRA 0x6c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06b0*/ FADD R5, R0, 3 ; /* 0x4040000000057421 */
/* 0x000fe40000000000 */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ LEA R2, P0, R10, c[0x0][0x168], 0x2 ; /* 0x00005a000a027a11 */
/* 0x000fc800078010ff */
/*06e0*/ LEA.HI.X R3, R10, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b000a037a11 */
/* 0x000fca00000f14ff */
/*06f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0720*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0730*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x000fe200078ec0ff */
/*0740*/ BSSY B1, 0xca0 ; /* 0x0000055000017945 */
/* 0x000fe20003800000 */
/*0750*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe40003f4e200 */
/*0760*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0770*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0780*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe400078ec0ff */
/*0790*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc400078ec0ff */
/*07a0*/ MOV R12, 0x1ca00000 ; /* 0x1ca00000000c7802 */
/* 0x000fe20000000f00 */
/*07b0*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*07c0*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe40003f26070 */
/*07d0*/ MOV R17, R11 ; /* 0x0000000b00117202 */
/* 0x000fe20000000f00 */
/*07e0*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*07f0*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0800*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0810*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*0820*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*0830*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0840*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef805 */
/*0850*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*0860*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*0870*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef805 */
/*0880*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0890*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*08a0*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000802 */
/*08b0*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*08c0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*08d0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*08e0*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*08f0*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0900*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0910*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*0920*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0930*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*0940*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*0950*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*0960*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0970*/ @P0 BRA 0xb40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0980*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0990*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*09a0*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*09b0*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*09c0*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*09d0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*09e0*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0a00*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0a10*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*0a20*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0a30*/ @P0 BRA 0xc90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0a40*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*0a50*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0a60*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*0a70*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0a80*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*0a90*/ @!P0 BRA 0xc90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*0ab0*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0ad0*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fca0007ffe1ff */
/*0ae0*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0af0*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fce00078e3cff */
/*0b00*/ FSETP.NEU.AND P0, PT, |R3|, R11, PT ; /* 0x0000000b0300720b */
/* 0x004fc80003f0d200 */
/*0b10*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*0b20*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0b30*/ BRA 0xc90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0b40*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0b50*/ @P0 BRA 0xc70 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0b60*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0b70*/ @P0 BRA 0xc40 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0b80*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe200078e00ff */
/*0ba0*/ MOV R13, 0xfff80000 ; /* 0xfff80000000d7802 */
/* 0x000fd60000000f00 */
/*0bb0*/ @!P0 BRA 0xc90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0bd0*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0be0*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0bf0*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0c00*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0c10*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe200078e00ff */
/*0c20*/ @P0 MOV R13, R2 ; /* 0x00000002000d0202 */
/* 0x000fe20000000f00 */
/*0c30*/ BRA 0xc90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0c50*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0c60*/ BRA 0xc90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*0c80*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*0c90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ca0*/ MOV R2, R0 ; /* 0x0000000000027202 */
/* 0x000fe20000000f00 */
/*0cb0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0cc0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff33002007950 */
/* 0x000fea0003c3ffff */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
const int listLength = 700;
__global__ void squareKernel(float* d_in, float *d_out, int threads_num) {
const unsigned int lid = threadIdx.x; // local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
if (gid < threads_num){
d_out[gid] = powf((d_in[gid]/(d_in[gid]-2.3)),3);
}// do computation
} | .file "tmpxft_00186ba6_00000000-6_squareKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12squareKernelPfS_iPfS_i
.type _Z35__device_stub__Z12squareKernelPfS_iPfS_i, @function
_Z35__device_stub__Z12squareKernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12squareKernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12squareKernelPfS_iPfS_i, .-_Z35__device_stub__Z12squareKernelPfS_iPfS_i
.globl _Z12squareKernelPfS_i
.type _Z12squareKernelPfS_i, @function
_Z12squareKernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12squareKernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12squareKernelPfS_i, .-_Z12squareKernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12squareKernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12squareKernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
const int listLength = 700;
__global__ void squareKernel(float* d_in, float *d_out, int threads_num) {
const unsigned int lid = threadIdx.x; // local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
if (gid < threads_num){
d_out[gid] = powf((d_in[gid]/(d_in[gid]-2.3)),3);
}// do computation
} | #include <hip/hip_runtime.h>
#include "includes.h"
const int listLength = 700;
__global__ void squareKernel(float* d_in, float *d_out, int threads_num) {
const unsigned int lid = threadIdx.x; // local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
if (gid < threads_num){
d_out[gid] = powf((d_in[gid]/(d_in[gid]-2.3)),3);
}// do computation
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int listLength = 700;
__global__ void squareKernel(float* d_in, float *d_out, int threads_num) {
const unsigned int lid = threadIdx.x; // local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
if (gid < threads_num){
d_out[gid] = powf((d_in[gid]/(d_in[gid]-2.3)),3);
}// do computation
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12squareKernelPfS_i
.globl _Z12squareKernelPfS_i
.p2align 8
.type _Z12squareKernelPfS_i,@function
_Z12squareKernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0xc0026666
s_mov_b32 s0, 0x66666666
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s0, 0x3e76c4e1
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_div_scale_f64 v[12:13], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
v_frexp_mant_f32_e64 v3, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_ldexp_f32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, 1.0, v3
v_add_f32_e32 v6, -1.0, v3
v_add_f32_e32 v8, -1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v3, v8
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, v6, v5
v_mul_f32_e32 v9, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v7, v4, -v9
v_fmac_f32_e32 v4, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v9, v4
v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v9, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v9, v4
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v6, v3
v_add_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v8, v3
v_mul_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v7, v3
v_mul_f32_e32 v6, v4, v4
v_sub_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v3, v3, v5
v_fma_f32 v5, v4, v4, -v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v3, v3
v_fmac_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v6, v5
v_fmaak_f32 v8, s0, v7, 0x3e91f4c4
v_sub_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v8, v7, v8, 0x3ecccdef :: v_dual_sub_f32 v5, v5, v6
v_mul_f32_e32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v7, v8, -v9
v_fmac_f32_e32 v6, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v9, v6
v_dual_sub_f32 v9, v8, v9 :: v_dual_add_f32 v10, 0x3f2aaaaa, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v11, v4, v7 :: v_dual_sub_f32 v6, v6, v9
v_fma_f32 v12, v7, v4, -v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, 0xbf2aaaaa, v10
v_add_f32_e32 v6, 0x31739010, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v12, v7, v3
v_sub_f32_e32 v8, v8, v9
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v5, v4
v_ldexp_f32 v4, v4, 1
v_add_f32_e32 v7, v11, v12
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v10, v6
v_sub_f32_e32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v9, v7, v5
v_sub_f32_e32 v10, v7, v11
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v8, v7, v5, -v9
v_sub_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v7, v6
v_frexp_exp_i32_f32_e32 v6, v2
v_fmac_f32_e32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
v_add_f32_e32 v6, v9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v5, v5
v_sub_f32_e32 v9, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v10, 0x3f317218, v5 :: v_dual_add_f32 v7, v4, v6
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, v5, 0x3f317218, -v10
v_add_f32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v5, v5, 0xb102e308, v9 :: v_dual_sub_f32 v4, v7, v4
v_sub_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v4 :: v_dual_add_f32 v4, v10, v5
v_add_f32_e32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v8, v4, v6 :: v_dual_sub_f32 v7, v6, v7
v_sub_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v10, v4, v10 :: v_dual_sub_f32 v3, v3, v7
v_sub_f32_e32 v11, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v5, v5, v10 :: v_dual_sub_f32 v6, v6, v9
v_sub_f32_e32 v4, v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v5, v3 :: v_dual_add_f32 v4, v6, v4
v_sub_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v7, v4
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v5, v5, v7
v_add_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v3, v3, v5 :: v_dual_sub_f32 v6, v9, v8
v_cndmask_b32_e64 v5, 0x40400000, 1.0, vcc_lo
v_sub_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_add_f32_e32 v4, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v7, v5, v4 :: v_dual_sub_f32 v6, v4, v9
v_fma_f32 v4, v5, v4, -v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v6
v_cmp_class_f32_e64 vcc_lo, v7, 0x204
v_fmac_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v7, v4
v_cndmask_b32_e32 v6, v3, v7, vcc_lo
v_sub_f32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
v_sub_f32_e32 v3, v4, v3
v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v6, v8
v_trunc_f32_e32 v6, v5
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_mul_f32 v10, 0x3fb8aa3b, v9
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v3, v8, v3
v_fma_f32 v11, v9, 0x3fb8aa3b, -v10
v_rndne_f32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmamk_f32 v11, v9, 0x32a5705f, v11 :: v_dual_sub_f32 v10, v10, v12
v_cvt_i32_f32_e32 v7, v12
v_add_f32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v10, v7
v_dual_mul_f32 v7, 0.5, v5 :: v_dual_cndmask_b32 v4, 0, v4
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_trunc_f32_e32 v10, v7
v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v6, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_neq_f32_e64 s0, v10, v7
v_fma_f32 v3, v4, v3, v4
v_cmp_eq_f32_e64 s1, 0x7f800000, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
v_cndmask_b32_e64 v5, 1.0, v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v4, s1
v_cmp_eq_f32_e64 s1, 0, v2
v_bfi_b32 v3, 0x7fffffff, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v4, 0x7f800000, 0, s1
v_cndmask_b32_e64 v5, 0, v2, s0
v_cmp_class_f32_e64 s0, v2, 0x204
v_cndmask_b32_e32 v6, 0x7fc00000, v3, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v4, 0x7fffffff, v4, v5
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_or_b32 vcc_lo, s1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v2, v2
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12squareKernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12squareKernelPfS_i, .Lfunc_end0-_Z12squareKernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12squareKernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12squareKernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int listLength = 700;
__global__ void squareKernel(float* d_in, float *d_out, int threads_num) {
const unsigned int lid = threadIdx.x; // local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
if (gid < threads_num){
d_out[gid] = powf((d_in[gid]/(d_in[gid]-2.3)),3);
}// do computation
} | .text
.file "squareKernel.hip"
.globl _Z27__device_stub__squareKernelPfS_i # -- Begin function _Z27__device_stub__squareKernelPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__squareKernelPfS_i,@function
_Z27__device_stub__squareKernelPfS_i: # @_Z27__device_stub__squareKernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12squareKernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__squareKernelPfS_i, .Lfunc_end0-_Z27__device_stub__squareKernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12squareKernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12squareKernelPfS_i,@object # @_Z12squareKernelPfS_i
.section .rodata,"a",@progbits
.globl _Z12squareKernelPfS_i
.p2align 3, 0x0
_Z12squareKernelPfS_i:
.quad _Z27__device_stub__squareKernelPfS_i
.size _Z12squareKernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12squareKernelPfS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__squareKernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12squareKernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12squareKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R10, R3, c[0x0][0x0], R10 ; /* 0x00000000030a7a24 */
/* 0x001fca00078e020a */
/*0040*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B0, 0x200 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*00c0*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x004e240000201800 */
/*00d0*/ DADD R6, R4, c[0x2][0x0] ; /* 0x0080000004067629 */
/* 0x001e220000000000 */
/*00e0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*00f0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e240000001800 */
/*0100*/ DFMA R12, -R6, R8, 1 ; /* 0x3ff00000060c742b */
/* 0x001e0c0000000108 */
/*0110*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0120*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001e0c0000000008 */
/*0130*/ DFMA R8, -R6, R12, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010c */
/*0140*/ DFMA R8, R12, R8, R12 ; /* 0x000000080c08722b */
/* 0x001e0c000000000c */
/*0150*/ DMUL R12, R4, R8 ; /* 0x00000008040c7228 */
/* 0x001e0c0000000000 */
/*0160*/ DFMA R2, -R6, R12, R4 ; /* 0x0000000c0602722b */
/* 0x001e0c0000000104 */
/*0170*/ DFMA R2, R8, R2, R12 ; /* 0x000000020802722b */
/* 0x001e14000000000c */
/*0180*/ FFMA R0, RZ, R7, R3 ; /* 0x00000007ff007223 */
/* 0x001fca0000000003 */
/*0190*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*01a0*/ @P0 BRA P1, 0x1f0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01b0*/ MOV R0, 0x1d0 ; /* 0x000001d000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x710 ; /* 0x0000054000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000c */
/*01e0*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x000fe40000000f00 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ F2F.F32.F64 R0, R2 ; /* 0x0000000200007310 */
/* 0x000ea20000301000 */
/*0210*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3a2c32e4 ; /* 0x3a2c32e4ff0c7424 */
/* 0x000fe200078e00ff */
/*0220*/ BSSY B0, 0x6d0 ; /* 0x000004a000007945 */
/* 0x000fe20003800000 */
/*0230*/ FMUL R5, |R0|.reuse, 16777216 ; /* 0x4b80000000057820 */
/* 0x044fe20000400200 */
/*0240*/ FSETP.GEU.AND P0, PT, |R0|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x040fe40003f0e200 */
/*0250*/ FSETP.NEU.AND P2, PT, R0, 1, PT ; /* 0x3f8000000000780b */
/* 0x000fe40003f4d000 */
/*0260*/ FSEL R5, R5, |R0|, !P0 ; /* 0x4000000005057208 */
/* 0x000fe40004000000 */
/*0270*/ FSEL R2, RZ, -24, P0 ; /* 0xc1c00000ff027808 */
/* 0x000fc40000000000 */
/*0280*/ IADD3 R4, R5, -0x3f3504f3, RZ ; /* 0xc0cafb0d05047810 */
/* 0x000fc80007ffe0ff */
/*0290*/ LOP3.LUT R4, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004047812 */
/* 0x000fc800078ec0ff */
/*02a0*/ I2F R7, R4 ; /* 0x0000000400077306 */
/* 0x000ea20000201400 */
/*02b0*/ IMAD.IADD R5, R5, 0x1, -R4 ; /* 0x0000000105057824 */
/* 0x000fc800078e0a04 */
/*02c0*/ FADD R6, R5.reuse, 1 ; /* 0x3f80000005067421 */
/* 0x040fe40000000000 */
/*02d0*/ FADD R5, R5, -1 ; /* 0xbf80000005057421 */
/* 0x000fc80000000000 */
/*02e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x000ee20000001000 */
/*02f0*/ FADD R3, R5, R5 ; /* 0x0000000505037221 */
/* 0x000fe40000000000 */
/*0300*/ FFMA R2, R7, 1.1920928955078125e-07, R2 ; /* 0x3400000007027823 */
/* 0x004fe40000000002 */
/*0310*/ FMUL R8, R6, R3 ; /* 0x0000000306087220 */
/* 0x008fc80000400000 */
/*0320*/ FADD R7, R5, -R8 ; /* 0x8000000805077221 */
/* 0x000fe40000000000 */
/*0330*/ FMUL R3, R8.reuse, R8 ; /* 0x0000000808037220 */
/* 0x040fe40000400000 */
/*0340*/ FFMA R9, R8, 1.4426950216293334961, R2 ; /* 0x3fb8aa3b08097823 */
/* 0x000fe40000000002 */
/*0350*/ FADD R7, R7, R7 ; /* 0x0000000707077221 */
/* 0x000fe40000000000 */
/*0360*/ FFMA R4, R3, R12, 0.0032181653659790754318 ; /* 0x3b52e7db03047423 */
/* 0x000fe4000000000c */
/*0370*/ FADD R11, R2, -R9 ; /* 0x80000009020b7221 */
/* 0x000fc40000000000 */
/*0380*/ FFMA R7, R5, -R8, R7 ; /* 0x8000000805077223 */
/* 0x000fe40000000007 */
/*0390*/ FFMA R4, R3.reuse, R4, 0.018033718690276145935 ; /* 0x3c93bb7303047423 */
/* 0x040fe40000000004 */
/*03a0*/ FFMA R2, R8, 1.4426950216293334961, R11 ; /* 0x3fb8aa3b08027823 */
/* 0x000fe4000000000b */
/*03b0*/ FMUL R7, R6, R7 ; /* 0x0000000706077220 */
/* 0x000fe40000400000 */
/*03c0*/ FFMA R4, R3, R4, 0.12022458761930465698 ; /* 0x3df6384f03047423 */
/* 0x000fe40000000004 */
/*03d0*/ FFMA R5, R7, 1.4426950216293334961, R2 ; /* 0x3fb8aa3b07057823 */
/* 0x000fc40000000002 */
/*03e0*/ FMUL R3, R3, R4 ; /* 0x0000000403037220 */
/* 0x000fe40000400000 */
/*03f0*/ FFMA R2, R8, 1.9251366722983220825e-08, R5 ; /* 0x32a55e3408027823 */
/* 0x000fe40000000005 */
/*0400*/ FMUL R4, R3, 3 ; /* 0x4040000003047820 */
/* 0x000fc80000400000 */
/*0410*/ FFMA R2, R7, R4, R2 ; /* 0x0000000407027223 */
/* 0x000fe40000000002 */
/*0420*/ IMAD.MOV.U32 R7, RZ, RZ, 0x391fcb8e ; /* 0x391fcb8eff077424 */
/* 0x000fe400078e00ff */
/*0430*/ FFMA R2, R8, R3, R2 ; /* 0x0000000308027223 */
/* 0x000fc80000000002 */
/*0440*/ FADD R4, R9, R2 ; /* 0x0000000209047221 */
/* 0x000fc80000000000 */
/*0450*/ FMUL R3, R4.reuse, 3 ; /* 0x4040000004037820 */
/* 0x040fe40000400000 */
/*0460*/ FADD R9, -R9, R4 ; /* 0x0000000409097221 */
/* 0x000fe40000000100 */
/*0470*/ FRND R6, R3 ; /* 0x0000000300067307 */
/* 0x000ea20000201000 */
/*0480*/ FFMA R4, R4, 3, -R3 ; /* 0x4040000004047823 */
/* 0x000fe20000000803 */
/*0490*/ FSETP.GEU.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f2e000 */
/*04a0*/ FADD R9, R2, -R9 ; /* 0x8000000902097221 */
/* 0x000fc80000000000 */
/*04b0*/ FFMA R4, R9, 3, R4 ; /* 0x4040000009047823 */
/* 0x000fe20000000004 */
/*04c0*/ F2I.NTZ R2, R3 ; /* 0x0000000300027305 */
/* 0x000ee20000203100 */
/*04d0*/ FADD R5, R3, -R6 ; /* 0x8000000603057221 */
/* 0x004fe20000000000 */
/*04e0*/ FSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fc60003f04000 */
/*04f0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x000fc80000000000 */
/*0500*/ FFMA R5, R4.reuse, R7, 0.0013391353422775864601 ; /* 0x3aaf85ed04057423 */
/* 0x040fe20000000007 */
/*0510*/ SEL R7, RZ, 0x83000000, P0 ; /* 0x83000000ff077807 */
/* 0x000fe40000000000 */
/*0520*/ FSETP.GT.AND P0, PT, |R3|, 152, PT ; /* 0x431800000300780b */
/* 0x000fe20003f04200 */
/*0530*/ FFMA R5, R4, R5, 0.0096188392490148544312 ; /* 0x3c1d985604057423 */
/* 0x000fe20000000005 */
/*0540*/ IADD3 R6, R7, 0x7f000000, RZ ; /* 0x7f00000007067810 */
/* 0x000fe40007ffe0ff */
/*0550*/ LEA R2, R2, -R7, 0x17 ; /* 0x8000000702027211 */
/* 0x008fe200078eb8ff */
/*0560*/ FFMA R5, R4, R5, 0.055503588169813156128 ; /* 0x3d6357bb04057423 */
/* 0x000fc80000000005 */
/*0570*/ FFMA R5, R4, R5, 0.24022644758224487305 ; /* 0x3e75fdec04057423 */
/* 0x000fc80000000005 */
/*0580*/ FFMA R5, R4, R5, 0.69314718246459960938 ; /* 0x3f31721804057423 */
/* 0x000fc80000000005 */
/*0590*/ FFMA R5, R4, R5, 1 ; /* 0x3f80000004057423 */
/* 0x000fc80000000005 */
/*05a0*/ FMUL R5, R5, R6 ; /* 0x0000000605057220 */
/* 0x000fc80000400000 */
/*05b0*/ FMUL R2, R5, R2 ; /* 0x0000000205027220 */
/* 0x000fe20000400000 */
/*05c0*/ @P0 FSEL R2, RZ, +INF , !P1 ; /* 0x7f800000ff020808 */
/* 0x000fe20004800000 */
/*05d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff057424 */
/* 0x000fe200078e00ff */
/*05e0*/ @!P2 BRA 0x6c0 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.GTU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f0c200 */
/*0600*/ @P0 BRA 0x6b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0610*/ FSETP.NEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fc80003f0d000 */
/*0620*/ FSETP.EQ.OR P0, PT, |R0|, +INF , !P0 ; /* 0x7f8000000000780b */
/* 0x000fda0004702600 */
/*0630*/ @P0 BRA 0x690 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fe20003f0e000 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0002 */
/*0660*/ @P0 BRA 0x6c0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0670*/ FADD R5, -R2, -RZ ; /* 0x800000ff02057221 */
/* 0x000fe20000000100 */
/*0680*/ BRA 0x6c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0690*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x000fe20000000000 */
/*06a0*/ BRA 0x6c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06b0*/ FADD R5, R0, 3 ; /* 0x4040000000057421 */
/* 0x000fe40000000000 */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ LEA R2, P0, R10, c[0x0][0x168], 0x2 ; /* 0x00005a000a027a11 */
/* 0x000fc800078010ff */
/*06e0*/ LEA.HI.X R3, R10, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b000a037a11 */
/* 0x000fca00000f14ff */
/*06f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0720*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0730*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x000fe200078ec0ff */
/*0740*/ BSSY B1, 0xca0 ; /* 0x0000055000017945 */
/* 0x000fe20003800000 */
/*0750*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe40003f4e200 */
/*0760*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0770*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0780*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe400078ec0ff */
/*0790*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc400078ec0ff */
/*07a0*/ MOV R12, 0x1ca00000 ; /* 0x1ca00000000c7802 */
/* 0x000fe20000000f00 */
/*07b0*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*07c0*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe40003f26070 */
/*07d0*/ MOV R17, R11 ; /* 0x0000000b00117202 */
/* 0x000fe20000000f00 */
/*07e0*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*07f0*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0800*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0810*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*0820*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*0830*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0840*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef805 */
/*0850*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*0860*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*0870*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef805 */
/*0880*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0890*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*08a0*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000802 */
/*08b0*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*08c0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*08d0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*08e0*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*08f0*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0900*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0910*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*0920*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0930*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*0940*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*0950*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*0960*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0970*/ @P0 BRA 0xb40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0980*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0990*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*09a0*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*09b0*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*09c0*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*09d0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*09e0*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0a00*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0a10*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*0a20*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0a30*/ @P0 BRA 0xc90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0a40*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*0a50*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0a60*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*0a70*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0a80*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*0a90*/ @!P0 BRA 0xc90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*0ab0*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0ad0*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fca0007ffe1ff */
/*0ae0*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0af0*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fce00078e3cff */
/*0b00*/ FSETP.NEU.AND P0, PT, |R3|, R11, PT ; /* 0x0000000b0300720b */
/* 0x004fc80003f0d200 */
/*0b10*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*0b20*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0b30*/ BRA 0xc90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0b40*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0b50*/ @P0 BRA 0xc70 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0b60*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0b70*/ @P0 BRA 0xc40 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0b80*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe200078e00ff */
/*0ba0*/ MOV R13, 0xfff80000 ; /* 0xfff80000000d7802 */
/* 0x000fd60000000f00 */
/*0bb0*/ @!P0 BRA 0xc90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0bd0*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0be0*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0bf0*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0c00*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0c10*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe200078e00ff */
/*0c20*/ @P0 MOV R13, R2 ; /* 0x00000002000d0202 */
/* 0x000fe20000000f00 */
/*0c30*/ BRA 0xc90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0c50*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0c60*/ BRA 0xc90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*0c80*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*0c90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ca0*/ MOV R2, R0 ; /* 0x0000000000027202 */
/* 0x000fe20000000f00 */
/*0cb0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0cc0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff33002007950 */
/* 0x000fea0003c3ffff */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12squareKernelPfS_i
.globl _Z12squareKernelPfS_i
.p2align 8
.type _Z12squareKernelPfS_i,@function
_Z12squareKernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0xc0026666
s_mov_b32 s0, 0x66666666
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s0, 0x3e76c4e1
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_div_scale_f64 v[12:13], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
v_frexp_mant_f32_e64 v3, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_ldexp_f32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, 1.0, v3
v_add_f32_e32 v6, -1.0, v3
v_add_f32_e32 v8, -1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v3, v8
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, v6, v5
v_mul_f32_e32 v9, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v7, v4, -v9
v_fmac_f32_e32 v4, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v9, v4
v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v9, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v9, v4
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v6, v3
v_add_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v8, v3
v_mul_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v7, v3
v_mul_f32_e32 v6, v4, v4
v_sub_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v3, v3, v5
v_fma_f32 v5, v4, v4, -v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v3, v3
v_fmac_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v6, v5
v_fmaak_f32 v8, s0, v7, 0x3e91f4c4
v_sub_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v8, v7, v8, 0x3ecccdef :: v_dual_sub_f32 v5, v5, v6
v_mul_f32_e32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v7, v8, -v9
v_fmac_f32_e32 v6, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v9, v6
v_dual_sub_f32 v9, v8, v9 :: v_dual_add_f32 v10, 0x3f2aaaaa, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v11, v4, v7 :: v_dual_sub_f32 v6, v6, v9
v_fma_f32 v12, v7, v4, -v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, 0xbf2aaaaa, v10
v_add_f32_e32 v6, 0x31739010, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v12, v7, v3
v_sub_f32_e32 v8, v8, v9
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v5, v4
v_ldexp_f32 v4, v4, 1
v_add_f32_e32 v7, v11, v12
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v10, v6
v_sub_f32_e32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v9, v7, v5
v_sub_f32_e32 v10, v7, v11
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v8, v7, v5, -v9
v_sub_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v7, v6
v_frexp_exp_i32_f32_e32 v6, v2
v_fmac_f32_e32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
v_add_f32_e32 v6, v9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v5, v5
v_sub_f32_e32 v9, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v10, 0x3f317218, v5 :: v_dual_add_f32 v7, v4, v6
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, v5, 0x3f317218, -v10
v_add_f32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v5, v5, 0xb102e308, v9 :: v_dual_sub_f32 v4, v7, v4
v_sub_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v4 :: v_dual_add_f32 v4, v10, v5
v_add_f32_e32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v8, v4, v6 :: v_dual_sub_f32 v7, v6, v7
v_sub_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v10, v4, v10 :: v_dual_sub_f32 v3, v3, v7
v_sub_f32_e32 v11, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v5, v5, v10 :: v_dual_sub_f32 v6, v6, v9
v_sub_f32_e32 v4, v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v5, v3 :: v_dual_add_f32 v4, v6, v4
v_sub_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v7, v4
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v5, v5, v7
v_add_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v3, v3, v5 :: v_dual_sub_f32 v6, v9, v8
v_cndmask_b32_e64 v5, 0x40400000, 1.0, vcc_lo
v_sub_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_add_f32_e32 v4, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v7, v5, v4 :: v_dual_sub_f32 v6, v4, v9
v_fma_f32 v4, v5, v4, -v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v6
v_cmp_class_f32_e64 vcc_lo, v7, 0x204
v_fmac_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v7, v4
v_cndmask_b32_e32 v6, v3, v7, vcc_lo
v_sub_f32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
v_sub_f32_e32 v3, v4, v3
v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v6, v8
v_trunc_f32_e32 v6, v5
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_mul_f32 v10, 0x3fb8aa3b, v9
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v3, v8, v3
v_fma_f32 v11, v9, 0x3fb8aa3b, -v10
v_rndne_f32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmamk_f32 v11, v9, 0x32a5705f, v11 :: v_dual_sub_f32 v10, v10, v12
v_cvt_i32_f32_e32 v7, v12
v_add_f32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v10, v7
v_dual_mul_f32 v7, 0.5, v5 :: v_dual_cndmask_b32 v4, 0, v4
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_trunc_f32_e32 v10, v7
v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v6, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_neq_f32_e64 s0, v10, v7
v_fma_f32 v3, v4, v3, v4
v_cmp_eq_f32_e64 s1, 0x7f800000, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
v_cndmask_b32_e64 v5, 1.0, v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v4, s1
v_cmp_eq_f32_e64 s1, 0, v2
v_bfi_b32 v3, 0x7fffffff, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v4, 0x7f800000, 0, s1
v_cndmask_b32_e64 v5, 0, v2, s0
v_cmp_class_f32_e64 s0, v2, 0x204
v_cndmask_b32_e32 v6, 0x7fc00000, v3, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v4, 0x7fffffff, v4, v5
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_or_b32 vcc_lo, s1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v2, v2
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12squareKernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12squareKernelPfS_i, .Lfunc_end0-_Z12squareKernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12squareKernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12squareKernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00186ba6_00000000-6_squareKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12squareKernelPfS_iPfS_i
.type _Z35__device_stub__Z12squareKernelPfS_iPfS_i, @function
_Z35__device_stub__Z12squareKernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12squareKernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12squareKernelPfS_iPfS_i, .-_Z35__device_stub__Z12squareKernelPfS_iPfS_i
.globl _Z12squareKernelPfS_i
.type _Z12squareKernelPfS_i, @function
_Z12squareKernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12squareKernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12squareKernelPfS_i, .-_Z12squareKernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12squareKernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12squareKernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "squareKernel.hip"
.globl _Z27__device_stub__squareKernelPfS_i # -- Begin function _Z27__device_stub__squareKernelPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__squareKernelPfS_i,@function
_Z27__device_stub__squareKernelPfS_i: # @_Z27__device_stub__squareKernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12squareKernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__squareKernelPfS_i, .Lfunc_end0-_Z27__device_stub__squareKernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12squareKernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12squareKernelPfS_i,@object # @_Z12squareKernelPfS_i
.section .rodata,"a",@progbits
.globl _Z12squareKernelPfS_i
.p2align 3, 0x0
_Z12squareKernelPfS_i:
.quad _Z27__device_stub__squareKernelPfS_i
.size _Z12squareKernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12squareKernelPfS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__squareKernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12squareKernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void invierte(float *a, float *b) {
int id = threadIdx.x;
//int id = threadIdx.x + blockDim.x * blockIdx.x;// para n-bloques de 1 hilo
if (id < N)
{
b[id] = a[N-id];
}
} | code for sm_80
Function : _Z8inviertePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R4, 0x7, PT ; /* 0x000000070400780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ IADD3 R2, -R4, 0x8, RZ ; /* 0x0000000804027810 */
/* 0x000fe20007ffe1ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void invierte(float *a, float *b) {
int id = threadIdx.x;
//int id = threadIdx.x + blockDim.x * blockIdx.x;// para n-bloques de 1 hilo
if (id < N)
{
b[id] = a[N-id];
}
} | .file "tmpxft_000f2732_00000000-6_invierte.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8inviertePfS_PfS_
.type _Z29__device_stub__Z8inviertePfS_PfS_, @function
_Z29__device_stub__Z8inviertePfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8inviertePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8inviertePfS_PfS_, .-_Z29__device_stub__Z8inviertePfS_PfS_
.globl _Z8inviertePfS_
.type _Z8inviertePfS_, @function
_Z8inviertePfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8inviertePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8inviertePfS_, .-_Z8inviertePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8inviertePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8inviertePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void invierte(float *a, float *b) {
int id = threadIdx.x;
//int id = threadIdx.x + blockDim.x * blockIdx.x;// para n-bloques de 1 hilo
if (id < N)
{
b[id] = a[N-id];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void invierte(float *a, float *b) {
int id = threadIdx.x;
//int id = threadIdx.x + blockDim.x * blockIdx.x;// para n-bloques de 1 hilo
if (id < N)
{
b[id] = a[N-id];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void invierte(float *a, float *b) {
int id = threadIdx.x;
//int id = threadIdx.x + blockDim.x * blockIdx.x;// para n-bloques de 1 hilo
if (id < N)
{
b[id] = a[N-id];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8inviertePfS_
.globl _Z8inviertePfS_
.p2align 8
.type _Z8inviertePfS_,@function
_Z8inviertePfS_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_sub_nc_u32_e32 v1, 8, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8inviertePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8inviertePfS_, .Lfunc_end0-_Z8inviertePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8inviertePfS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z8inviertePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void invierte(float *a, float *b) {
int id = threadIdx.x;
//int id = threadIdx.x + blockDim.x * blockIdx.x;// para n-bloques de 1 hilo
if (id < N)
{
b[id] = a[N-id];
}
} | .text
.file "invierte.hip"
.globl _Z23__device_stub__inviertePfS_ # -- Begin function _Z23__device_stub__inviertePfS_
.p2align 4, 0x90
.type _Z23__device_stub__inviertePfS_,@function
_Z23__device_stub__inviertePfS_: # @_Z23__device_stub__inviertePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8inviertePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__inviertePfS_, .Lfunc_end0-_Z23__device_stub__inviertePfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8inviertePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8inviertePfS_,@object # @_Z8inviertePfS_
.section .rodata,"a",@progbits
.globl _Z8inviertePfS_
.p2align 3, 0x0
_Z8inviertePfS_:
.quad _Z23__device_stub__inviertePfS_
.size _Z8inviertePfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8inviertePfS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__inviertePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8inviertePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8inviertePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R4, 0x7, PT ; /* 0x000000070400780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ IADD3 R2, -R4, 0x8, RZ ; /* 0x0000000804027810 */
/* 0x000fe20007ffe1ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8inviertePfS_
.globl _Z8inviertePfS_
.p2align 8
.type _Z8inviertePfS_,@function
_Z8inviertePfS_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_sub_nc_u32_e32 v1, 8, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8inviertePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8inviertePfS_, .Lfunc_end0-_Z8inviertePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8inviertePfS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z8inviertePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f2732_00000000-6_invierte.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8inviertePfS_PfS_
.type _Z29__device_stub__Z8inviertePfS_PfS_, @function
_Z29__device_stub__Z8inviertePfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8inviertePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8inviertePfS_PfS_, .-_Z29__device_stub__Z8inviertePfS_PfS_
.globl _Z8inviertePfS_
.type _Z8inviertePfS_, @function
_Z8inviertePfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8inviertePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8inviertePfS_, .-_Z8inviertePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8inviertePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8inviertePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "invierte.hip"
.globl _Z23__device_stub__inviertePfS_ # -- Begin function _Z23__device_stub__inviertePfS_
.p2align 4, 0x90
.type _Z23__device_stub__inviertePfS_,@function
_Z23__device_stub__inviertePfS_: # @_Z23__device_stub__inviertePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8inviertePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__inviertePfS_, .Lfunc_end0-_Z23__device_stub__inviertePfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8inviertePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8inviertePfS_,@object # @_Z8inviertePfS_
.section .rodata,"a",@progbits
.globl _Z8inviertePfS_
.p2align 3, 0x0
_Z8inviertePfS_:
.quad _Z23__device_stub__inviertePfS_
.size _Z8inviertePfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8inviertePfS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__inviertePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8inviertePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
__device__ int get_global_index(){
return blockIdx.x * blockDim.x + threadIdx.x;
}
__device__ int get_constant(){
return 7;
}
__global__ void kernel1(int *array){
int index = get_global_index();
array[index] = get_constant();
}
__global__ void kernel2(int *array){
int index = get_global_index();
array[index] = get_global_index();
}
int main(){
int num_elements = 256;
int num_bytes = num_elements*sizeof(int);
int *device_array = 0;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
cudaMalloc((void**)&device_array, num_bytes);
int block_size = 128;
int grid_size = num_elements/block_size;
kernel1<<<grid_size, block_size>>>(device_array);
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
printf("kernel 1 results: \n");
int i;
for(i=0;i<num_elements;i++){
printf("%d ", host_array[i]);
}
printf("\n");
kernel2<<<grid_size, block_size>>>(device_array);
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
printf("kernel 2 results: \n");
for(i= 0; i< num_elements; i++){
printf("%d ", host_array[i]);
}
printf("\n");
return 0;
} | code for sm_80
Function : _Z7kernel2Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x7 ; /* 0x0000000700077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
__device__ int get_global_index(){
return blockIdx.x * blockDim.x + threadIdx.x;
}
__device__ int get_constant(){
return 7;
}
__global__ void kernel1(int *array){
int index = get_global_index();
array[index] = get_constant();
}
__global__ void kernel2(int *array){
int index = get_global_index();
array[index] = get_global_index();
}
int main(){
int num_elements = 256;
int num_bytes = num_elements*sizeof(int);
int *device_array = 0;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
cudaMalloc((void**)&device_array, num_bytes);
int block_size = 128;
int grid_size = num_elements/block_size;
kernel1<<<grid_size, block_size>>>(device_array);
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
printf("kernel 1 results: \n");
int i;
for(i=0;i<num_elements;i++){
printf("%d ", host_array[i]);
}
printf("\n");
kernel2<<<grid_size, block_size>>>(device_array);
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
printf("kernel 2 results: \n");
for(i= 0; i< num_elements; i++){
printf("%d ", host_array[i]);
}
printf("\n");
return 0;
} | .file "tmpxft_000fcece_00000000-6_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16get_global_indexv
.type _Z16get_global_indexv, @function
_Z16get_global_indexv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z16get_global_indexv, .-_Z16get_global_indexv
.globl _Z12get_constantv
.type _Z12get_constantv, @function
_Z12get_constantv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z12get_constantv, .-_Z12get_constantv
.globl _Z26__device_stub__Z7kernel1PiPi
.type _Z26__device_stub__Z7kernel1PiPi, @function
_Z26__device_stub__Z7kernel1PiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel1Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z7kernel1PiPi, .-_Z26__device_stub__Z7kernel1PiPi
.globl _Z7kernel1Pi
.type _Z7kernel1Pi, @function
_Z7kernel1Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel1PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7kernel1Pi, .-_Z7kernel1Pi
.globl _Z26__device_stub__Z7kernel2PiPi
.type _Z26__device_stub__Z7kernel2PiPi, @function
_Z26__device_stub__Z7kernel2PiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel2Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z26__device_stub__Z7kernel2PiPi, .-_Z26__device_stub__Z7kernel2PiPi
.globl _Z7kernel2Pi
.type _Z7kernel2Pi, @function
_Z7kernel2Pi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel2PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7kernel2Pi, .-_Z7kernel2Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel 1 results: \n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "kernel 2 results: \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L24:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rbx
leaq 1024(%r14), %r12
movq %r14, %rbp
leaq .LC1(%rip), %r13
.L25:
movl 0(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L25
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L26:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rbp
.L27:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L27
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7kernel1PiPi
jmp .L24
.L33:
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7kernel2PiPi
jmp .L26
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7kernel2Pi"
.LC5:
.string "_Z7kernel1Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2Pi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
__device__ int get_global_index(){
return blockIdx.x * blockDim.x + threadIdx.x;
}
__device__ int get_constant(){
return 7;
}
__global__ void kernel1(int *array){
int index = get_global_index();
array[index] = get_constant();
}
__global__ void kernel2(int *array){
int index = get_global_index();
array[index] = get_global_index();
}
int main(){
int num_elements = 256;
int num_bytes = num_elements*sizeof(int);
int *device_array = 0;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
cudaMalloc((void**)&device_array, num_bytes);
int block_size = 128;
int grid_size = num_elements/block_size;
kernel1<<<grid_size, block_size>>>(device_array);
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
printf("kernel 1 results: \n");
int i;
for(i=0;i<num_elements;i++){
printf("%d ", host_array[i]);
}
printf("\n");
kernel2<<<grid_size, block_size>>>(device_array);
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
printf("kernel 2 results: \n");
for(i= 0; i< num_elements; i++){
printf("%d ", host_array[i]);
}
printf("\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__device__ int get_global_index(){
return blockIdx.x * blockDim.x + threadIdx.x;
}
__device__ int get_constant(){
return 7;
}
__global__ void kernel1(int *array){
int index = get_global_index();
array[index] = get_constant();
}
__global__ void kernel2(int *array){
int index = get_global_index();
array[index] = get_global_index();
}
int main(){
int num_elements = 256;
int num_bytes = num_elements*sizeof(int);
int *device_array = 0;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
hipMalloc((void**)&device_array, num_bytes);
int block_size = 128;
int grid_size = num_elements/block_size;
kernel1<<<grid_size, block_size>>>(device_array);
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
printf("kernel 1 results: \n");
int i;
for(i=0;i<num_elements;i++){
printf("%d ", host_array[i]);
}
printf("\n");
kernel2<<<grid_size, block_size>>>(device_array);
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
printf("kernel 2 results: \n");
for(i= 0; i< num_elements; i++){
printf("%d ", host_array[i]);
}
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__device__ int get_global_index(){
return blockIdx.x * blockDim.x + threadIdx.x;
}
__device__ int get_constant(){
return 7;
}
__global__ void kernel1(int *array){
int index = get_global_index();
array[index] = get_constant();
}
__global__ void kernel2(int *array){
int index = get_global_index();
array[index] = get_global_index();
}
int main(){
int num_elements = 256;
int num_bytes = num_elements*sizeof(int);
int *device_array = 0;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
hipMalloc((void**)&device_array, num_bytes);
int block_size = 128;
int grid_size = num_elements/block_size;
kernel1<<<grid_size, block_size>>>(device_array);
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
printf("kernel 1 results: \n");
int i;
for(i=0;i<num_elements;i++){
printf("%d ", host_array[i]);
}
printf("\n");
kernel2<<<grid_size, block_size>>>(device_array);
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
printf("kernel 2 results: \n");
for(i= 0; i< num_elements; i++){
printf("%d ", host_array[i]);
}
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1Pi
.globl _Z7kernel1Pi
.p2align 8
.type _Z7kernel1Pi,@function
_Z7kernel1Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 7
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1Pi, .Lfunc_end0-_Z7kernel1Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2Pi
.globl _Z7kernel2Pi
.p2align 8
.type _Z7kernel2Pi,@function
_Z7kernel2Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2Pi, .Lfunc_end1-_Z7kernel2Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel2Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__device__ int get_global_index(){
return blockIdx.x * blockDim.x + threadIdx.x;
}
__device__ int get_constant(){
return 7;
}
__global__ void kernel1(int *array){
int index = get_global_index();
array[index] = get_constant();
}
__global__ void kernel2(int *array){
int index = get_global_index();
array[index] = get_global_index();
}
int main(){
int num_elements = 256;
int num_bytes = num_elements*sizeof(int);
int *device_array = 0;
int *host_array = 0;
host_array = (int *) malloc(num_bytes);
hipMalloc((void**)&device_array, num_bytes);
int block_size = 128;
int grid_size = num_elements/block_size;
kernel1<<<grid_size, block_size>>>(device_array);
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
printf("kernel 1 results: \n");
int i;
for(i=0;i<num_elements;i++){
printf("%d ", host_array[i]);
}
printf("\n");
kernel2<<<grid_size, block_size>>>(device_array);
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
printf("kernel 2 results: \n");
for(i= 0; i< num_elements; i++){
printf("%d ", host_array[i]);
}
printf("\n");
return 0;
} | .text
.file "device.hip"
.globl _Z22__device_stub__kernel1Pi # -- Begin function _Z22__device_stub__kernel1Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel1Pi,@function
_Z22__device_stub__kernel1Pi: # @_Z22__device_stub__kernel1Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel1Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1Pi, .Lfunc_end0-_Z22__device_stub__kernel1Pi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2Pi # -- Begin function _Z22__device_stub__kernel2Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel2Pi,@function
_Z22__device_stub__kernel2Pi: # @_Z22__device_stub__kernel2Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel2Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2Pi, .Lfunc_end1-_Z22__device_stub__kernel2Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967298, %r14 # imm = 0x100000002
movq $0, 8(%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 126(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7kernel1Pi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $256, %r12 # imm = 0x100
jne .LBB2_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7kernel2Pi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $256, %r14 # imm = 0x100
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2Pi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1Pi,@object # @_Z7kernel1Pi
.section .rodata,"a",@progbits
.globl _Z7kernel1Pi
.p2align 3, 0x0
_Z7kernel1Pi:
.quad _Z22__device_stub__kernel1Pi
.size _Z7kernel1Pi, 8
.type _Z7kernel2Pi,@object # @_Z7kernel2Pi
.globl _Z7kernel2Pi
.p2align 3, 0x0
_Z7kernel2Pi:
.quad _Z22__device_stub__kernel2Pi
.size _Z7kernel2Pi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1Pi"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2Pi"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "kernel 1 results: "
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "kernel 2 results: "
.size .Lstr.1, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1Pi
.addrsig_sym _Z22__device_stub__kernel2Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1Pi
.addrsig_sym _Z7kernel2Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernel2Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x7 ; /* 0x0000000700077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1Pi
.globl _Z7kernel1Pi
.p2align 8
.type _Z7kernel1Pi,@function
_Z7kernel1Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 7
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1Pi, .Lfunc_end0-_Z7kernel1Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2Pi
.globl _Z7kernel2Pi
.p2align 8
.type _Z7kernel2Pi,@function
_Z7kernel2Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2Pi, .Lfunc_end1-_Z7kernel2Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel2Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fcece_00000000-6_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16get_global_indexv
.type _Z16get_global_indexv, @function
_Z16get_global_indexv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z16get_global_indexv, .-_Z16get_global_indexv
.globl _Z12get_constantv
.type _Z12get_constantv, @function
_Z12get_constantv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z12get_constantv, .-_Z12get_constantv
.globl _Z26__device_stub__Z7kernel1PiPi
.type _Z26__device_stub__Z7kernel1PiPi, @function
_Z26__device_stub__Z7kernel1PiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel1Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z7kernel1PiPi, .-_Z26__device_stub__Z7kernel1PiPi
.globl _Z7kernel1Pi
.type _Z7kernel1Pi, @function
_Z7kernel1Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel1PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7kernel1Pi, .-_Z7kernel1Pi
.globl _Z26__device_stub__Z7kernel2PiPi
.type _Z26__device_stub__Z7kernel2PiPi, @function
_Z26__device_stub__Z7kernel2PiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel2Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z26__device_stub__Z7kernel2PiPi, .-_Z26__device_stub__Z7kernel2PiPi
.globl _Z7kernel2Pi
.type _Z7kernel2Pi, @function
_Z7kernel2Pi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel2PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7kernel2Pi, .-_Z7kernel2Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel 1 results: \n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "kernel 2 results: \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L24:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rbx
leaq 1024(%r14), %r12
movq %r14, %rbp
leaq .LC1(%rip), %r13
.L25:
movl 0(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L25
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L26:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rbp
.L27:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L27
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7kernel1PiPi
jmp .L24
.L33:
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7kernel2PiPi
jmp .L26
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7kernel2Pi"
.LC5:
.string "_Z7kernel1Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2Pi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "device.hip"
.globl _Z22__device_stub__kernel1Pi # -- Begin function _Z22__device_stub__kernel1Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel1Pi,@function
_Z22__device_stub__kernel1Pi: # @_Z22__device_stub__kernel1Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel1Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1Pi, .Lfunc_end0-_Z22__device_stub__kernel1Pi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2Pi # -- Begin function _Z22__device_stub__kernel2Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel2Pi,@function
_Z22__device_stub__kernel2Pi: # @_Z22__device_stub__kernel2Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel2Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2Pi, .Lfunc_end1-_Z22__device_stub__kernel2Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967298, %r14 # imm = 0x100000002
movq $0, 8(%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 126(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7kernel1Pi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $256, %r12 # imm = 0x100
jne .LBB2_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7kernel2Pi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $256, %r14 # imm = 0x100
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2Pi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1Pi,@object # @_Z7kernel1Pi
.section .rodata,"a",@progbits
.globl _Z7kernel1Pi
.p2align 3, 0x0
_Z7kernel1Pi:
.quad _Z22__device_stub__kernel1Pi
.size _Z7kernel1Pi, 8
.type _Z7kernel2Pi,@object # @_Z7kernel2Pi
.globl _Z7kernel2Pi
.p2align 3, 0x0
_Z7kernel2Pi:
.quad _Z22__device_stub__kernel2Pi
.size _Z7kernel2Pi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1Pi"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2Pi"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "kernel 1 results: "
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "kernel 2 results: "
.size .Lstr.1, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1Pi
.addrsig_sym _Z22__device_stub__kernel2Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1Pi
.addrsig_sym _Z7kernel2Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
int *elements;
} Matrix;
/* Thread block size */
#define BLOCK_SIZE 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const Matrix A, const Matrix B, Matrix C){
int Cvalue = 0;
int i;
int size = A.width;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int row = blockIdx.y*blockDim.y+threadIdx.y;
for(i=0;i<size;++i){
Cvalue += A.elements[row*size+i]*B.elements[i*size+col];
}
C.elements[row*size+col] = Cvalue;
}
void test(const Matrix C);
int main(int argc, char* argv[]){
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(int)*size*size;
h_A.width = size;h_B.width = size;h_C.width = size;
/* Allocate host memory */
h_A.elements = (int*)malloc(full_size);
h_B.elements = (int*)malloc(full_size);
h_C.elements = (int*)malloc(full_size);
for(i=0;i<size*size;++i){ scanf("%d", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%d", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;d_B.width = size;d_C.width = size;
cudaMalloc(&d_A.elements, full_size);
cudaMalloc(&d_B.elements, full_size);
cudaMalloc(&d_C.elements, full_size);
cudaEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
cudaMemcpy(d_A.elements, h_A.elements, full_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B.elements, h_B.elements, full_size, cudaMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C);
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_C.elements, d_C.elements, full_size, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C){
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%d ", C.elements[i*C.width+j]);
printf("\n");
}
} | code for sm_80
Function : _Z6MatMul6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x160] ; /* 0x0000580000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x160], RZ ; /* 0x0000580005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x178] ; /* 0x00005e0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x160], R2 ; /* 0x0000580003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x188] ; /* 0x0000620002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
int *elements;
} Matrix;
/* Thread block size */
#define BLOCK_SIZE 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const Matrix A, const Matrix B, Matrix C){
int Cvalue = 0;
int i;
int size = A.width;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int row = blockIdx.y*blockDim.y+threadIdx.y;
for(i=0;i<size;++i){
Cvalue += A.elements[row*size+i]*B.elements[i*size+col];
}
C.elements[row*size+col] = Cvalue;
}
void test(const Matrix C);
int main(int argc, char* argv[]){
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(int)*size*size;
h_A.width = size;h_B.width = size;h_C.width = size;
/* Allocate host memory */
h_A.elements = (int*)malloc(full_size);
h_B.elements = (int*)malloc(full_size);
h_C.elements = (int*)malloc(full_size);
for(i=0;i<size*size;++i){ scanf("%d", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%d", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;d_B.width = size;d_C.width = size;
cudaMalloc(&d_A.elements, full_size);
cudaMalloc(&d_B.elements, full_size);
cudaMalloc(&d_C.elements, full_size);
cudaEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
cudaMemcpy(d_A.elements, h_A.elements, full_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B.elements, h_B.elements, full_size, cudaMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C);
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_C.elements, d_C.elements, full_size, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C){
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%d ", C.elements[i*C.width+j]);
printf("\n");
}
} | .file "tmpxft_00157527_00000000-6_MMult1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z4test6Matrix
.type _Z4test6Matrix, @function
_Z4test6Matrix:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 4(%rsp)
testl %edi, %edi
jle .L3
movq %rsi, %r12
movslq %edi, %rdi
leaq 0(,%rdi,4), %r15
negq %rdi
leaq 0(,%rdi,4), %rax
movq %rax, 8(%rsp)
movq %r15, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
.L5:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L6:
movl (%rbx,%r12), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 4(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z4test6Matrix, .-_Z4test6Matrix
.globl _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_
.type _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_, @function
_Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6MatMul6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_, .-_Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.section .rodata.str1.1
.LC2:
.string "%d"
.LC3:
.string "Elapsed time = %f (s)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, 36(%rsp)
leaq 36(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 36(%rsp), %r13d
movl %r13d, %eax
movq %rax, 24(%rsp)
movl %r13d, %r12d
imull %r13d, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 16(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movl %r13d, %eax
imull %r13d, %eax
testl %eax, %eax
jle .L23
movl $0, %ebx
leaq .LC2(%rip), %r15
.L19:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 36(%rsp), %eax
movl %eax, %edx
imull %eax, %edx
addq $4, %rbp
cmpl %ebx, %edx
jg .L19
testl %edx, %edx
jle .L18
movq 8(%rsp), %rbp
movl $0, %ebx
leaq .LC2(%rip), %r15
.L20:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 36(%rsp), %eax
addq $4, %rbp
movl %eax, %edx
imull %eax, %edx
cmpl %ebx, %edx
jg .L20
.L18:
movl %eax, 80(%rsp)
movl %eax, 96(%rsp)
movl %eax, 112(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
shrl %r13d
movl %r13d, 68(%rsp)
movl %r13d, 72(%rsp)
movl $2, 56(%rsp)
movl $2, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
movl $2, %ecx
movq %r12, %rdx
movq 120(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 160(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 160(%rsp), %xmm0
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl 24(%rsp), %edi
movq %r14, %rsi
call _Z4test6Matrix
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %r13d, %eax
jmp .L18
.L27:
movdqa 80(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 144(%rsp)
movdqa 112(%rsp), %xmm3
movaps %xmm3, 160(%rsp)
leaq 160(%rsp), %rdx
leaq 144(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6MatMul6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatMul6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
int *elements;
} Matrix;
/* Thread block size */
#define BLOCK_SIZE 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const Matrix A, const Matrix B, Matrix C){
int Cvalue = 0;
int i;
int size = A.width;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int row = blockIdx.y*blockDim.y+threadIdx.y;
for(i=0;i<size;++i){
Cvalue += A.elements[row*size+i]*B.elements[i*size+col];
}
C.elements[row*size+col] = Cvalue;
}
void test(const Matrix C);
int main(int argc, char* argv[]){
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(int)*size*size;
h_A.width = size;h_B.width = size;h_C.width = size;
/* Allocate host memory */
h_A.elements = (int*)malloc(full_size);
h_B.elements = (int*)malloc(full_size);
h_C.elements = (int*)malloc(full_size);
for(i=0;i<size*size;++i){ scanf("%d", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%d", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;d_B.width = size;d_C.width = size;
cudaMalloc(&d_A.elements, full_size);
cudaMalloc(&d_B.elements, full_size);
cudaMalloc(&d_C.elements, full_size);
cudaEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
cudaMemcpy(d_A.elements, h_A.elements, full_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B.elements, h_B.elements, full_size, cudaMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C);
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_C.elements, d_C.elements, full_size, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C){
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%d ", C.elements[i*C.width+j]);
printf("\n");
}
} | #include <stdio.h>
#include <hip/hip_runtime.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
int *elements;
} Matrix;
/* Thread block size */
#define BLOCK_SIZE 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const Matrix A, const Matrix B, Matrix C){
int Cvalue = 0;
int i;
int size = A.width;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int row = blockIdx.y*blockDim.y+threadIdx.y;
for(i=0;i<size;++i){
Cvalue += A.elements[row*size+i]*B.elements[i*size+col];
}
C.elements[row*size+col] = Cvalue;
}
void test(const Matrix C);
int main(int argc, char* argv[]){
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(int)*size*size;
h_A.width = size;h_B.width = size;h_C.width = size;
/* Allocate host memory */
h_A.elements = (int*)malloc(full_size);
h_B.elements = (int*)malloc(full_size);
h_C.elements = (int*)malloc(full_size);
for(i=0;i<size*size;++i){ scanf("%d", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%d", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;d_B.width = size;d_C.width = size;
hipMalloc(&d_A.elements, full_size);
hipMalloc(&d_B.elements, full_size);
hipMalloc(&d_C.elements, full_size);
hipEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
hipMemcpy(d_A.elements, h_A.elements, full_size, hipMemcpyHostToDevice);
hipMemcpy(d_B.elements, h_B.elements, full_size, hipMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C);
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_C.elements, d_C.elements, full_size, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C){
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%d ", C.elements[i*C.width+j]);
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
int *elements;
} Matrix;
/* Thread block size */
#define BLOCK_SIZE 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const Matrix A, const Matrix B, Matrix C){
int Cvalue = 0;
int i;
int size = A.width;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int row = blockIdx.y*blockDim.y+threadIdx.y;
for(i=0;i<size;++i){
Cvalue += A.elements[row*size+i]*B.elements[i*size+col];
}
C.elements[row*size+col] = Cvalue;
}
void test(const Matrix C);
int main(int argc, char* argv[]){
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(int)*size*size;
h_A.width = size;h_B.width = size;h_C.width = size;
/* Allocate host memory */
h_A.elements = (int*)malloc(full_size);
h_B.elements = (int*)malloc(full_size);
h_C.elements = (int*)malloc(full_size);
for(i=0;i<size*size;++i){ scanf("%d", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%d", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;d_B.width = size;d_C.width = size;
hipMalloc(&d_A.elements, full_size);
hipMalloc(&d_B.elements, full_size);
hipMalloc(&d_C.elements, full_size);
hipEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
hipMemcpy(d_A.elements, h_A.elements, full_size, hipMemcpyHostToDevice);
hipMemcpy(d_B.elements, h_B.elements, full_size, hipMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C);
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_C.elements, d_C.elements, full_size, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C){
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%d ", C.elements[i*C.width+j]);
printf("\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatMul6MatrixS_S_
.globl _Z6MatMul6MatrixS_S_
.p2align 8
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_lshr_b32 s5, s5, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s6, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s4
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s5, s4
v_mov_b32_e32 v5, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s5, s5, -1
s_cmp_lg_u32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s4, v5
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatMul6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end0-_Z6MatMul6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatMul6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6MatMul6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
int *elements;
} Matrix;
/* Thread block size */
#define BLOCK_SIZE 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const Matrix A, const Matrix B, Matrix C){
int Cvalue = 0;
int i;
int size = A.width;
int col = blockIdx.x*blockDim.x+threadIdx.x;
int row = blockIdx.y*blockDim.y+threadIdx.y;
for(i=0;i<size;++i){
Cvalue += A.elements[row*size+i]*B.elements[i*size+col];
}
C.elements[row*size+col] = Cvalue;
}
void test(const Matrix C);
int main(int argc, char* argv[]){
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(int)*size*size;
h_A.width = size;h_B.width = size;h_C.width = size;
/* Allocate host memory */
h_A.elements = (int*)malloc(full_size);
h_B.elements = (int*)malloc(full_size);
h_C.elements = (int*)malloc(full_size);
for(i=0;i<size*size;++i){ scanf("%d", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%d", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;d_B.width = size;d_C.width = size;
hipMalloc(&d_A.elements, full_size);
hipMalloc(&d_B.elements, full_size);
hipMalloc(&d_C.elements, full_size);
hipEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
hipMemcpy(d_A.elements, h_A.elements, full_size, hipMemcpyHostToDevice);
hipMemcpy(d_B.elements, h_B.elements, full_size, hipMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C);
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_C.elements, d_C.elements, full_size, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C){
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%d ", C.elements[i*C.width+j]);
printf("\n");
}
} | .text
.file "MMult1.hip"
.globl _Z21__device_stub__MatMul6MatrixS_S_ # -- Begin function _Z21__device_stub__MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z21__device_stub__MatMul6MatrixS_S_,@function
_Z21__device_stub__MatMul6MatrixS_S_: # @_Z21__device_stub__MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 80(%rsp)
movq %rsi, 88(%rsp)
movl %edx, 64(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6MatMul6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__MatMul6MatrixS_S_, .Lfunc_end0-_Z21__device_stub__MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %ebp
movl %ebp, %eax
imull %ebp, %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r15
cmpl $0, 4(%rsp)
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r14, %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movl 4(%rsp), %eax
imull %eax, %eax
addq $4, %r13
cmpq %rax, %rbx
jb .LBB1_2
.LBB1_3: # %.preheader
movl 4(%rsp), %eax
testl %eax, %eax
je .LBB1_6
# %bb.4: # %.lr.ph49.preheader
movq 16(%rsp), %r13 # 8-byte Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph49
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movl 4(%rsp), %eax
movl %eax, %ecx
imull %ecx, %ecx
addq $4, %r13
cmpq %rcx, %rbx
jb .LBB1_5
.LBB1_6: # %._crit_edge
movl %eax, 64(%rsp)
movl %eax, 48(%rsp)
movl %eax, 32(%rsp)
leaq 72(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
movq %r14, 112(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
shrl %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movl 64(%rsp), %eax
movq 72(%rsp), %rcx
movl 48(%rsp), %edx
movq 56(%rsp), %rsi
movl 32(%rsp), %edi
movq 40(%rsp), %r8
movl %eax, 200(%rsp)
movq %rcx, 208(%rsp)
movl %edx, 184(%rsp)
movq %rsi, 192(%rsp)
movl %edi, 168(%rsp)
movq %r8, 176(%rsp)
leaq 200(%rsp), %rax
movq %rax, 80(%rsp)
leaq 184(%rsp), %rax
movq %rax, 88(%rsp)
leaq 168(%rsp), %rax
movq %rax, 96(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatMul6MatrixS_S_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movq stderr(%rip), %rdi
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %esi
movb $1, %al
callq fprintf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %ebp, %ebp
jle .LBB1_13
# %bb.9: # %.preheader.lr.ph.i
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_10: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
movl %r12d, %eax
leaq (%r15,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB1_11
# %bb.12: # %._crit_edge.i
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebp, %r12d
cmpq %rbp, %r13
jne .LBB1_10
.LBB1_13: # %_Z4test6Matrix.exit
movq 72(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z4test6Matrix # -- Begin function _Z4test6Matrix
.p2align 4, 0x90
.type _Z4test6Matrix,@function
_Z4test6Matrix: # @_Z4test6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB2_2
.LBB2_5: # %._crit_edge12
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z4test6Matrix, .Lfunc_end2-_Z4test6Matrix
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatMul6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatMul6MatrixS_S_,@object # @_Z6MatMul6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z6MatMul6MatrixS_S_
.p2align 3, 0x0
_Z6MatMul6MatrixS_S_:
.quad _Z21__device_stub__MatMul6MatrixS_S_
.size _Z6MatMul6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Elapsed time = %f (s)\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatMul6MatrixS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatMul6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatMul6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6MatMul6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x160] ; /* 0x0000580000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x160], RZ ; /* 0x0000580005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x178] ; /* 0x00005e0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x160], R2 ; /* 0x0000580003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x188] ; /* 0x0000620002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatMul6MatrixS_S_
.globl _Z6MatMul6MatrixS_S_
.p2align 8
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_lshr_b32 s5, s5, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s6, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s4
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s5, s4
v_mov_b32_e32 v5, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s5, s5, -1
s_cmp_lg_u32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s4, v5
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatMul6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end0-_Z6MatMul6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatMul6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6MatMul6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00157527_00000000-6_MMult1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z4test6Matrix
.type _Z4test6Matrix, @function
_Z4test6Matrix:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 4(%rsp)
testl %edi, %edi
jle .L3
movq %rsi, %r12
movslq %edi, %rdi
leaq 0(,%rdi,4), %r15
negq %rdi
leaq 0(,%rdi,4), %rax
movq %rax, 8(%rsp)
movq %r15, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
.L5:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L6:
movl (%rbx,%r12), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 4(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z4test6Matrix, .-_Z4test6Matrix
.globl _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_
.type _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_, @function
_Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6MatMul6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_, .-_Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.section .rodata.str1.1
.LC2:
.string "%d"
.LC3:
.string "Elapsed time = %f (s)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, 36(%rsp)
leaq 36(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 36(%rsp), %r13d
movl %r13d, %eax
movq %rax, 24(%rsp)
movl %r13d, %r12d
imull %r13d, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 16(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movl %r13d, %eax
imull %r13d, %eax
testl %eax, %eax
jle .L23
movl $0, %ebx
leaq .LC2(%rip), %r15
.L19:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 36(%rsp), %eax
movl %eax, %edx
imull %eax, %edx
addq $4, %rbp
cmpl %ebx, %edx
jg .L19
testl %edx, %edx
jle .L18
movq 8(%rsp), %rbp
movl $0, %ebx
leaq .LC2(%rip), %r15
.L20:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 36(%rsp), %eax
addq $4, %rbp
movl %eax, %edx
imull %eax, %edx
cmpl %ebx, %edx
jg .L20
.L18:
movl %eax, 80(%rsp)
movl %eax, 96(%rsp)
movl %eax, 112(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
shrl %r13d
movl %r13d, 68(%rsp)
movl %r13d, 72(%rsp)
movl $2, 56(%rsp)
movl $2, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
movl $2, %ecx
movq %r12, %rdx
movq 120(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 160(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 160(%rsp), %xmm0
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl 24(%rsp), %edi
movq %r14, %rsi
call _Z4test6Matrix
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %r13d, %eax
jmp .L18
.L27:
movdqa 80(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 144(%rsp)
movdqa 112(%rsp), %xmm3
movaps %xmm3, 160(%rsp)
leaq 160(%rsp), %rdx
leaq 144(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z34__device_stub__Z6MatMul6MatrixS_S_RK6MatrixS1_RS_
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6MatMul6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatMul6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MMult1.hip"
.globl _Z21__device_stub__MatMul6MatrixS_S_ # -- Begin function _Z21__device_stub__MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z21__device_stub__MatMul6MatrixS_S_,@function
_Z21__device_stub__MatMul6MatrixS_S_: # @_Z21__device_stub__MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 80(%rsp)
movq %rsi, 88(%rsp)
movl %edx, 64(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6MatMul6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__MatMul6MatrixS_S_, .Lfunc_end0-_Z21__device_stub__MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %ebp
movl %ebp, %eax
imull %ebp, %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r15
cmpl $0, 4(%rsp)
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r14, %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movl 4(%rsp), %eax
imull %eax, %eax
addq $4, %r13
cmpq %rax, %rbx
jb .LBB1_2
.LBB1_3: # %.preheader
movl 4(%rsp), %eax
testl %eax, %eax
je .LBB1_6
# %bb.4: # %.lr.ph49.preheader
movq 16(%rsp), %r13 # 8-byte Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph49
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movl 4(%rsp), %eax
movl %eax, %ecx
imull %ecx, %ecx
addq $4, %r13
cmpq %rcx, %rbx
jb .LBB1_5
.LBB1_6: # %._crit_edge
movl %eax, 64(%rsp)
movl %eax, 48(%rsp)
movl %eax, 32(%rsp)
leaq 72(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
movq %r14, 112(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
shrl %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movl 64(%rsp), %eax
movq 72(%rsp), %rcx
movl 48(%rsp), %edx
movq 56(%rsp), %rsi
movl 32(%rsp), %edi
movq 40(%rsp), %r8
movl %eax, 200(%rsp)
movq %rcx, 208(%rsp)
movl %edx, 184(%rsp)
movq %rsi, 192(%rsp)
movl %edi, 168(%rsp)
movq %r8, 176(%rsp)
leaq 200(%rsp), %rax
movq %rax, 80(%rsp)
leaq 184(%rsp), %rax
movq %rax, 88(%rsp)
leaq 168(%rsp), %rax
movq %rax, 96(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatMul6MatrixS_S_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movq stderr(%rip), %rdi
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %esi
movb $1, %al
callq fprintf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %ebp, %ebp
jle .LBB1_13
# %bb.9: # %.preheader.lr.ph.i
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_10: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
movl %r12d, %eax
leaq (%r15,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB1_11
# %bb.12: # %._crit_edge.i
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebp, %r12d
cmpq %rbp, %r13
jne .LBB1_10
.LBB1_13: # %_Z4test6Matrix.exit
movq 72(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z4test6Matrix # -- Begin function _Z4test6Matrix
.p2align 4, 0x90
.type _Z4test6Matrix,@function
_Z4test6Matrix: # @_Z4test6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB2_2
.LBB2_5: # %._crit_edge12
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z4test6Matrix, .Lfunc_end2-_Z4test6Matrix
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatMul6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatMul6MatrixS_S_,@object # @_Z6MatMul6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z6MatMul6MatrixS_S_
.p2align 3, 0x0
_Z6MatMul6MatrixS_S_:
.quad _Z21__device_stub__MatMul6MatrixS_S_
.size _Z6MatMul6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Elapsed time = %f (s)\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatMul6MatrixS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatMul6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatMul6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrix_mul_shared(float *ad,float *bd,float *cd,int N)
{
float pvalue=0;
int TILE=blockDim.x;
int ty=threadIdx.y;
int tx=threadIdx.x;
//allocate shared memory per block
__shared__ float ads[16][16];
__shared__ float bds[16][16];
//find Row and Column corresponding to a data element for each thread
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
//iterate through TILEs to traverse whole WIDTH
for(int i=0;i< N/TILE;++i)
{
//copy values of data TILE into shared memory
ads[ty][tx] = ad[Row * N + (i * TILE) + tx];
bds[ty][tx] = bd[(i * TILE + ty) * N + Col];
__syncthreads(); //synchronize to confirm that whole TILE has been copied
//calculate partial dot-product
for(int k=0;k<TILE;k++)
pvalue += ads[ty][k] * bds[k][tx];
__syncthreads(); //synchronize to confirm that whole partial product corresponding to all threads of the block has been calculated
}
//store dot product at corresponding positon in resultant Matrix
cd[Row * N + Col] = pvalue;
} | code for sm_80
Function : _Z17matrix_mul_sharedPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R5, c[0x0][0x0] ; /* 0x0000000000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002600 */
/*0040*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e620000209400 */
/*0060*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8e3c3f */
/*0070*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0090*/ ISETP.LE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf43270 */
/*00a0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e640000001000 */
/*00b0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0002a4000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x002fe200000001ff */
/*00e0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x004fc800078e0a03 */
/*00f0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*0100*/ IABS R4, c[0x0][0x178] ; /* 0x00005e0000047a13 */
/* 0x000fc80000000000 */
/*0110*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*0120*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e680000002100 */
/*0130*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0150*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0160*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f24070 */
/*0170*/ @!P1 IADD3 R0, R0, -R5.reuse, RZ ; /* 0x8000000500009210 */
/* 0x080fe40007ffe0ff */
/*0180*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f25270 */
/*01b0*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*01c0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e6c0000002500 */
/*01d0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01e0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*01f0*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff039a12 */
/* 0x000fc800078e33ff */
/*0200*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f06270 */
/*0210*/ IMAD R17, R17, c[0x0][0x4], R0 ; /* 0x0000010011117a24 */
/* 0x001fe400078e0200 */
/*0220*/ IMAD R4, R5, c[0x0][0x0], R2 ; /* 0x0000000005047a24 */
/* 0x002fd400078e0202 */
/*0230*/ @!P0 BRA 0xb80 ; /* 0x0000094000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0c7624 */
/* 0x000fe200078e00ff */
/*0250*/ SHF.L.U32 R7, R0, 0x6, RZ ; /* 0x0000000600077819 */
/* 0x000fe200000006ff */
/*0260*/ IMAD R5, R17, c[0x0][0x178], R2 ; /* 0x00005e0011057a24 */
/* 0x000fe200078e0202 */
/*0270*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R6, R12, -0x1, RZ ; /* 0xffffffff0c067810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD R13, R2, 0x4, R7 ; /* 0x00000004020d7824 */
/* 0x000fe200078e0207 */
/*02b0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe400078ec0ff */
/*02c0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f46070 */
/*02d0*/ LEA R6, R2, 0x480, 0x2 ; /* 0x0000048002067811 */
/* 0x000fc400078e10ff */
/*02e0*/ IADD3 R15, R7, 0x8, RZ ; /* 0x00000008070f7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ IADD3 R16, -R12, c[0x0][0x0], RZ ; /* 0x000000000c107a10 */
/* 0x000fe40007ffe1ff */
/*0300*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0310*/ IMAD R9, R14.reuse, c[0x0][0x0], R0 ; /* 0x000000000e097a24 */
/* 0x040fe400078e0200 */
/*0320*/ IMAD R10, R14, c[0x0][0x0], R5 ; /* 0x000000000e0a7a24 */
/* 0x000fe400078e0205 */
/*0330*/ IMAD R9, R9, c[0x0][0x178], R4 ; /* 0x00005e0009097a24 */
/* 0x000fca00078e0204 */
/*0340*/ IMAD.WIDE R10, R10, R8, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc800078e0208 */
/*0350*/ IMAD.WIDE R8, R9, R8, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fe400078e0208 */
/*0360*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee2000c1e1900 */
/*0380*/ MOV R18, c[0x0][0x0] ; /* 0x0000000000127a02 */
/* 0x000fe40000000f00 */
/*0390*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc40003f06270 */
/*03b0*/ ISETP.GE.AND P1, PT, R14, R3, PT ; /* 0x000000030e00720c */
/* 0x000fe20003f26270 */
/*03c0*/ STS [R13], R10 ; /* 0x0000000a0d007388 */
/* 0x0041e80000000800 */
/*03d0*/ STS [R13+0x400], R8 ; /* 0x000400080d007388 */
/* 0x0081e80000000800 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ @!P0 BRA 0xb60 ; /* 0x0000076000008947 */
/* 0x000fea0003800000 */
/*0400*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x001fe20008000000 */
/*0410*/ @!P2 BRA 0xa70 ; /* 0x000006500000a947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GT.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f04270 */
/*0430*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0440*/ IMAD.MOV.U32 R20, RZ, RZ, R15 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000f */
/*0450*/ MOV R19, R6 ; /* 0x0000000600137202 */
/* 0x000fc40000000f00 */
/*0460*/ MOV R18, R16 ; /* 0x0000001000127202 */
/* 0x000fd00000000f00 */
/*0470*/ @!P0 BRA 0x970 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.GT.AND P3, PT, R18, 0xc, PT ; /* 0x0000000c1200780c */
/* 0x000fe40003f64270 */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*04a0*/ @!P3 BRA 0x7a0 ; /* 0x000002f00000b947 */
/* 0x000fea0003800000 */
/*04b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04c0*/ LDS R24, [R19+-0x80] ; /* 0xffff800013187984 */
/* 0x000fe20000000800 */
/*04d0*/ IADD3 R18, R18, -0x10, RZ ; /* 0xfffffff012127810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*04f0*/ LDS.64 R10, [R20+-0x8] ; /* 0xfffff800140a7984 */
/* 0x000e220000000a00 */
/*0500*/ ISETP.GT.AND P3, PT, R18, 0xc, PT ; /* 0x0000000c1200780c */
/* 0x000fc60003f64270 */
/*0510*/ LDS R25, [R19+-0x40] ; /* 0xffffc00013197984 */
/* 0x000e680000000800 */
/*0520*/ LDS R23, [R19] ; /* 0x0000000013177984 */
/* 0x000fe80000000800 */
/*0530*/ LDS.64 R8, [R20] ; /* 0x0000000014087984 */
/* 0x000ea80000000a00 */
/*0540*/ LDS R22, [R19+0x40] ; /* 0x0000400013167984 */
/* 0x000ee20000000800 */
/*0550*/ FFMA R10, R24, R10, R21 ; /* 0x0000000a180a7223 */
/* 0x001fc60000000015 */
/*0560*/ LDS R21, [R19+0x80] ; /* 0x0000800013157984 */
/* 0x000fe20000000800 */
/*0570*/ FFMA R25, R25, R11, R10 ; /* 0x0000000b19197223 */
/* 0x002fc6000000000a */
/*0580*/ LDS.64 R10, [R20+0x8] ; /* 0x00000800140a7984 */
/* 0x000e220000000a00 */
/*0590*/ FFMA R8, R23, R8, R25 ; /* 0x0000000817087223 */
/* 0x004fc60000000019 */
/*05a0*/ LDS R25, [R19+0xc0] ; /* 0x0000c00013197984 */
/* 0x000e620000000800 */
/*05b0*/ FFMA R24, R22, R9, R8 ; /* 0x0000000916187223 */
/* 0x008fc60000000008 */
/*05c0*/ LDS R23, [R19+0x100] ; /* 0x0001000013177984 */
/* 0x000fe80000000800 */
/*05d0*/ LDS.64 R8, [R20+0x10] ; /* 0x0000100014087984 */
/* 0x000ea80000000a00 */
/*05e0*/ LDS R22, [R19+0x140] ; /* 0x0001400013167984 */
/* 0x000ee20000000800 */
/*05f0*/ FFMA R10, R21, R10, R24 ; /* 0x0000000a150a7223 */
/* 0x001fc60000000018 */
/*0600*/ LDS R21, [R19+0x180] ; /* 0x0001800013157984 */
/* 0x000fe20000000800 */
/*0610*/ FFMA R25, R25, R11, R10 ; /* 0x0000000b19197223 */
/* 0x002fc6000000000a */
/*0620*/ LDS.64 R10, [R20+0x18] ; /* 0x00001800140a7984 */
/* 0x000e220000000a00 */
/*0630*/ FFMA R8, R23, R8, R25 ; /* 0x0000000817087223 */
/* 0x004fc60000000019 */
/*0640*/ LDS R25, [R19+0x1c0] ; /* 0x0001c00013197984 */
/* 0x000e620000000800 */
/*0650*/ FFMA R24, R22, R9, R8 ; /* 0x0000000916187223 */
/* 0x008fc60000000008 */
/*0660*/ LDS R23, [R19+0x200] ; /* 0x0002000013177984 */
/* 0x000fe80000000800 */
/*0670*/ LDS.64 R8, [R20+0x20] ; /* 0x0000200014087984 */
/* 0x000ea80000000a00 */
/*0680*/ LDS R22, [R19+0x240] ; /* 0x0002400013167984 */
/* 0x000ee20000000800 */
/*0690*/ FFMA R10, R21, R10, R24 ; /* 0x0000000a150a7223 */
/* 0x001fc60000000018 */
/*06a0*/ LDS R21, [R19+0x280] ; /* 0x0002800013157984 */
/* 0x000fe80000000800 */
/*06b0*/ LDS R24, [R19+0x300] ; /* 0x0003000013187984 */
/* 0x000fe20000000800 */
/*06c0*/ FFMA R25, R25, R11, R10 ; /* 0x0000000b19197223 */
/* 0x002fc6000000000a */
/*06d0*/ LDS.64 R10, [R20+0x28] ; /* 0x00002800140a7984 */
/* 0x000e220000000a00 */
/*06e0*/ FFMA R8, R23, R8, R25 ; /* 0x0000000817087223 */
/* 0x004fc60000000019 */
/*06f0*/ LDS R23, [R19+0x2c0] ; /* 0x0002c00013177984 */
/* 0x000e620000000800 */
/*0700*/ FFMA R22, R22, R9, R8 ; /* 0x0000000916167223 */
/* 0x008fc60000000008 */
/*0710*/ LDS.64 R8, [R20+0x30] ; /* 0x0000300014087984 */
/* 0x0004e80000000a00 */
/*0720*/ LDS R25, [R19+0x340] ; /* 0x0003400013197984 */
/* 0x0009620000000800 */
/*0730*/ IADD3 R20, R20, 0x40, RZ ; /* 0x0000004014147810 */
/* 0x004fe40007ffe0ff */
/*0740*/ IADD3 R19, R19, 0x400, RZ ; /* 0x0000040013137810 */
/* 0x010fe20007ffe0ff */
/*0750*/ FFMA R10, R21, R10, R22 ; /* 0x0000000a150a7223 */
/* 0x001fc80000000016 */
/*0760*/ FFMA R11, R23, R11, R10 ; /* 0x0000000b170b7223 */
/* 0x002fc8000000000a */
/*0770*/ FFMA R8, R24, R8, R11 ; /* 0x0000000818087223 */
/* 0x008fc8000000000b */
/*0780*/ FFMA R21, R25, R9, R8 ; /* 0x0000000919157223 */
/* 0x020fe20000000008 */
/*0790*/ @P3 BRA 0x4c0 ; /* 0xfffffd2000003947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P3, PT, R18, 0x4, PT ; /* 0x000000041200780c */
/* 0x000fda0003f64270 */
/*07b0*/ @!P3 BRA 0x950 ; /* 0x000001900000b947 */
/* 0x000fea0003800000 */
/*07c0*/ LDS R24, [R19+-0x80] ; /* 0xffff800013187984 */
/* 0x000fe20000000800 */
/*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*07e0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*07f0*/ IADD3 R18, R18, -0x8, RZ ; /* 0xfffffff812127810 */
/* 0x000fe20007ffe0ff */
/*0800*/ LDS.64 R10, [R20+-0x8] ; /* 0xfffff800140a7984 */
/* 0x000e280000000a00 */
/*0810*/ LDS R25, [R19+-0x40] ; /* 0xffffc00013197984 */
/* 0x000e680000000800 */
/*0820*/ LDS R23, [R19] ; /* 0x0000000013177984 */
/* 0x000fe80000000800 */
/*0830*/ LDS.64 R8, [R20] ; /* 0x0000000014087984 */
/* 0x000ea80000000a00 */
/*0840*/ LDS R22, [R19+0x40] ; /* 0x0000400013167984 */
/* 0x000ee20000000800 */
/*0850*/ FFMA R10, R24, R10, R21 ; /* 0x0000000a180a7223 */
/* 0x001fc60000000015 */
/*0860*/ LDS R21, [R19+0x80] ; /* 0x0000800013157984 */
/* 0x000fe20000000800 */
/*0870*/ FFMA R25, R25, R11, R10 ; /* 0x0000000b19197223 */
/* 0x002fc6000000000a */
/*0880*/ LDS.64 R10, [R20+0x8] ; /* 0x00000800140a7984 */
/* 0x000e280000000a00 */
/*0890*/ LDS R24, [R19+0x100] ; /* 0x0001000013187984 */
/* 0x000fe20000000800 */
/*08a0*/ FFMA R8, R23, R8, R25 ; /* 0x0000000817087223 */
/* 0x004fc60000000019 */
/*08b0*/ LDS R23, [R19+0xc0] ; /* 0x0000c00013177984 */
/* 0x000e620000000800 */
/*08c0*/ FFMA R22, R22, R9, R8 ; /* 0x0000000916167223 */
/* 0x008fc60000000008 */
/*08d0*/ LDS.64 R8, [R20+0x10] ; /* 0x0000100014087984 */
/* 0x0004e80000000a00 */
/*08e0*/ LDS R25, [R19+0x140] ; /* 0x0001400013197984 */
/* 0x0009620000000800 */
/*08f0*/ IADD3 R20, R20, 0x20, RZ ; /* 0x0000002014147810 */
/* 0x004fe40007ffe0ff */
/*0900*/ IADD3 R19, R19, 0x200, RZ ; /* 0x0000020013137810 */
/* 0x010fe20007ffe0ff */
/*0910*/ FFMA R10, R21, R10, R22 ; /* 0x0000000a150a7223 */
/* 0x001fc80000000016 */
/*0920*/ FFMA R11, R23, R11, R10 ; /* 0x0000000b170b7223 */
/* 0x002fc8000000000a */
/*0930*/ FFMA R8, R24, R8, R11 ; /* 0x0000000818087223 */
/* 0x008fc8000000000b */
/*0940*/ FFMA R21, R25, R9, R8 ; /* 0x0000000919157223 */
/* 0x020fe40000000008 */
/*0950*/ ISETP.NE.OR P0, PT, R18, RZ, P0 ; /* 0x000000ff1200720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xa70 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0970*/ LDS R22, [R19+-0x80] ; /* 0xffff800013167984 */
/* 0x000fe20000000800 */
/*0980*/ IADD3 R18, R18, -0x4, RZ ; /* 0xfffffffc12127810 */
/* 0x000fe20007ffe0ff */
/*0990*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*09a0*/ LDS.64 R8, [R20+-0x8] ; /* 0xfffff80014087984 */
/* 0x000e220000000a00 */
/*09b0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc60003f05270 */
/*09c0*/ LDS R23, [R19+-0x40] ; /* 0xffffc00013177984 */
/* 0x000e680000000800 */
/*09d0*/ LDS R24, [R19] ; /* 0x0000000013187984 */
/* 0x000fe80000000800 */
/*09e0*/ LDS.64 R10, [R20] ; /* 0x00000000140a7984 */
/* 0x0004e80000000a00 */
/*09f0*/ LDS R25, [R19+0x40] ; /* 0x0000400013197984 */
/* 0x0009620000000800 */
/*0a00*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x004fc40007ffe0ff */
/*0a10*/ IADD3 R19, R19, 0x100, RZ ; /* 0x0000010013137810 */
/* 0x010fe20007ffe0ff */
/*0a20*/ FFMA R8, R22, R8, R21 ; /* 0x0000000816087223 */
/* 0x001fc80000000015 */
/*0a30*/ FFMA R9, R23, R9, R8 ; /* 0x0000000917097223 */
/* 0x002fc80000000008 */
/*0a40*/ FFMA R10, R24, R10, R9 ; /* 0x0000000a180a7223 */
/* 0x008fc80000000009 */
/*0a50*/ FFMA R21, R25, R11, R10 ; /* 0x0000000b19157223 */
/* 0x020fe2000000000a */
/*0a60*/ @P0 BRA 0x970 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0a70*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05270 */
/*0a80*/ @!P0 BRA 0xb60 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a90*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fe2000f8e00ff */
/*0aa0*/ ULEA UR5, UR4, 0x400, 0x6 ; /* 0x0000040004057891 */
/* 0x000fe2000f8e303f */
/*0ab0*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc60003f05270 */
/*0ac0*/ LEA R8, R8, R7, 0x2 ; /* 0x0000000708087211 */
/* 0x000fca00078e10ff */
/*0ad0*/ LDS R18, [R2.X4+UR5] ; /* 0x0000000502127984 */
/* 0x000fe80008004800 */
/*0ae0*/ LDS.128 R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000c00 */
/*0af0*/ FFMA R21, R18, R8, R21 ; /* 0x0000000812157223 */
/* 0x001fe20000000015 */
/*0b00*/ @!P0 BRA 0xb60 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0b10*/ ISETP.NE.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe20003f05270 */
/*0b20*/ LDS R8, [R2.X4+UR5+0x40] ; /* 0x0000400502087984 */
/* 0x000e180008004800 */
/*0b30*/ @P0 LDS R11, [R2.X4+UR5+0x80] ; /* 0x00008005020b0984 */
/* 0x000e620008004800 */
/*0b40*/ FFMA R21, R8, R9, R21 ; /* 0x0000000908157223 */
/* 0x001fc80000000015 */
/*0b50*/ @P0 FFMA R21, R11, R10, R21 ; /* 0x0000000a0b150223 */
/* 0x002fe40000000015 */
/*0b60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0b70*/ @!P1 BRA 0x300 ; /* 0xfffff78000009947 */
/* 0x000fea000383ffff */
/*0b80*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0b90*/ IMAD R2, R17, c[0x0][0x178], R4 ; /* 0x00005e0011027a24 */
/* 0x000fc800078e0204 */
/*0ba0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0bb0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrix_mul_shared(float *ad,float *bd,float *cd,int N)
{
float pvalue=0;
int TILE=blockDim.x;
int ty=threadIdx.y;
int tx=threadIdx.x;
//allocate shared memory per block
__shared__ float ads[16][16];
__shared__ float bds[16][16];
//find Row and Column corresponding to a data element for each thread
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
//iterate through TILEs to traverse whole WIDTH
for(int i=0;i< N/TILE;++i)
{
//copy values of data TILE into shared memory
ads[ty][tx] = ad[Row * N + (i * TILE) + tx];
bds[ty][tx] = bd[(i * TILE + ty) * N + Col];
__syncthreads(); //synchronize to confirm that whole TILE has been copied
//calculate partial dot-product
for(int k=0;k<TILE;k++)
pvalue += ads[ty][k] * bds[k][tx];
__syncthreads(); //synchronize to confirm that whole partial product corresponding to all threads of the block has been calculated
}
//store dot product at corresponding positon in resultant Matrix
cd[Row * N + Col] = pvalue;
} | .file "tmpxft_0006c4ca_00000000-6_matrix_mul_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matrix_mul_sharedPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i
.globl _Z17matrix_mul_sharedPfS_S_i
.type _Z17matrix_mul_sharedPfS_S_i, @function
_Z17matrix_mul_sharedPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17matrix_mul_sharedPfS_S_i, .-_Z17matrix_mul_sharedPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17matrix_mul_sharedPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrix_mul_sharedPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrix_mul_shared(float *ad,float *bd,float *cd,int N)
{
float pvalue=0;
int TILE=blockDim.x;
int ty=threadIdx.y;
int tx=threadIdx.x;
//allocate shared memory per block
__shared__ float ads[16][16];
__shared__ float bds[16][16];
//find Row and Column corresponding to a data element for each thread
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
//iterate through TILEs to traverse whole WIDTH
for(int i=0;i< N/TILE;++i)
{
//copy values of data TILE into shared memory
ads[ty][tx] = ad[Row * N + (i * TILE) + tx];
bds[ty][tx] = bd[(i * TILE + ty) * N + Col];
__syncthreads(); //synchronize to confirm that whole TILE has been copied
//calculate partial dot-product
for(int k=0;k<TILE;k++)
pvalue += ads[ty][k] * bds[k][tx];
__syncthreads(); //synchronize to confirm that whole partial product corresponding to all threads of the block has been calculated
}
//store dot product at corresponding positon in resultant Matrix
cd[Row * N + Col] = pvalue;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrix_mul_shared(float *ad,float *bd,float *cd,int N)
{
float pvalue=0;
int TILE=blockDim.x;
int ty=threadIdx.y;
int tx=threadIdx.x;
//allocate shared memory per block
__shared__ float ads[16][16];
__shared__ float bds[16][16];
//find Row and Column corresponding to a data element for each thread
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
//iterate through TILEs to traverse whole WIDTH
for(int i=0;i< N/TILE;++i)
{
//copy values of data TILE into shared memory
ads[ty][tx] = ad[Row * N + (i * TILE) + tx];
bds[ty][tx] = bd[(i * TILE + ty) * N + Col];
__syncthreads(); //synchronize to confirm that whole TILE has been copied
//calculate partial dot-product
for(int k=0;k<TILE;k++)
pvalue += ads[ty][k] * bds[k][tx];
__syncthreads(); //synchronize to confirm that whole partial product corresponding to all threads of the block has been calculated
}
//store dot product at corresponding positon in resultant Matrix
cd[Row * N + Col] = pvalue;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrix_mul_shared(float *ad,float *bd,float *cd,int N)
{
float pvalue=0;
int TILE=blockDim.x;
int ty=threadIdx.y;
int tx=threadIdx.x;
//allocate shared memory per block
__shared__ float ads[16][16];
__shared__ float bds[16][16];
//find Row and Column corresponding to a data element for each thread
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
//iterate through TILEs to traverse whole WIDTH
for(int i=0;i< N/TILE;++i)
{
//copy values of data TILE into shared memory
ads[ty][tx] = ad[Row * N + (i * TILE) + tx];
bds[ty][tx] = bd[(i * TILE + ty) * N + Col];
__syncthreads(); //synchronize to confirm that whole TILE has been copied
//calculate partial dot-product
for(int k=0;k<TILE;k++)
pvalue += ads[ty][k] * bds[k][tx];
__syncthreads(); //synchronize to confirm that whole partial product corresponding to all threads of the block has been calculated
}
//store dot product at corresponding positon in resultant Matrix
cd[Row * N + Col] = pvalue;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17matrix_mul_sharedPfS_S_i
.globl _Z17matrix_mul_sharedPfS_S_i
.p2align 8
.type _Z17matrix_mul_sharedPfS_S_i,@function
_Z17matrix_mul_sharedPfS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v6, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s4, 0xffff
s_ashr_i32 s7, s2, 31
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s6, 0, s3
s_add_i32 s8, s2, s7
s_lshr_b32 s4, s4, 16
s_xor_b32 s8, s8, s7
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s5, v1
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[3:4], null, s14, s3, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s5
s_mul_hi_u32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s6
s_mul_hi_u32 s5, s8, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s5, s3
s_sub_i32 s6, s8, s6
s_add_i32 s8, s5, 1
s_sub_i32 s9, s6, s3
s_cmp_ge_u32 s6, s3
s_cselect_b32 s5, s8, s5
s_cselect_b32 s6, s9, s6
s_add_i32 s8, s5, 1
s_cmp_ge_u32 s6, s3
s_mov_b32 s9, 0
s_cselect_b32 s4, s8, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s7
s_sub_i32 s8, s4, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v6
v_lshlrev_b32_e32 v7, 6, v2
s_max_u32 s10, s3, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0x400, v1
v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
v_add_nc_u32_e32 v5, v7, v1
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v6, v8, v7
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mul_i32 s11, s9, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v10, s11, v2
v_add_nc_u32_e32 v9, s11, v4
s_mov_b32 s11, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v10, s2, v[3:4]
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v13, v[9:10], off
global_load_b32 v11, v[11:12], off
v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v9, v8
s_waitcnt vmcnt(1)
ds_store_b32 v5, v13
s_waitcnt vmcnt(0)
ds_store_b32 v6, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
ds_load_b32 v11, v10
ds_load_b32 v12, v9
v_add_nc_u32_e32 v10, 4, v10
v_add_nc_u32_e32 v9, 64, v9
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, v11, v12
s_cbranch_scc0 .LBB0_3
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v1, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v0, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matrix_mul_sharedPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17matrix_mul_sharedPfS_S_i, .Lfunc_end0-_Z17matrix_mul_sharedPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matrix_mul_sharedPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matrix_mul_sharedPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrix_mul_shared(float *ad,float *bd,float *cd,int N)
{
float pvalue=0;
int TILE=blockDim.x;
int ty=threadIdx.y;
int tx=threadIdx.x;
//allocate shared memory per block
__shared__ float ads[16][16];
__shared__ float bds[16][16];
//find Row and Column corresponding to a data element for each thread
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
//iterate through TILEs to traverse whole WIDTH
for(int i=0;i< N/TILE;++i)
{
//copy values of data TILE into shared memory
ads[ty][tx] = ad[Row * N + (i * TILE) + tx];
bds[ty][tx] = bd[(i * TILE + ty) * N + Col];
__syncthreads(); //synchronize to confirm that whole TILE has been copied
//calculate partial dot-product
for(int k=0;k<TILE;k++)
pvalue += ads[ty][k] * bds[k][tx];
__syncthreads(); //synchronize to confirm that whole partial product corresponding to all threads of the block has been calculated
}
//store dot product at corresponding positon in resultant Matrix
cd[Row * N + Col] = pvalue;
} | .text
.file "matrix_mul_shared.hip"
.globl _Z32__device_stub__matrix_mul_sharedPfS_S_i # -- Begin function _Z32__device_stub__matrix_mul_sharedPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matrix_mul_sharedPfS_S_i,@function
_Z32__device_stub__matrix_mul_sharedPfS_S_i: # @_Z32__device_stub__matrix_mul_sharedPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matrix_mul_sharedPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__matrix_mul_sharedPfS_S_i, .Lfunc_end0-_Z32__device_stub__matrix_mul_sharedPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrix_mul_sharedPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17matrix_mul_sharedPfS_S_i,@object # @_Z17matrix_mul_sharedPfS_S_i
.section .rodata,"a",@progbits
.globl _Z17matrix_mul_sharedPfS_S_i
.p2align 3, 0x0
_Z17matrix_mul_sharedPfS_S_i:
.quad _Z32__device_stub__matrix_mul_sharedPfS_S_i
.size _Z17matrix_mul_sharedPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17matrix_mul_sharedPfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__matrix_mul_sharedPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17matrix_mul_sharedPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17matrix_mul_sharedPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R5, c[0x0][0x0] ; /* 0x0000000000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002600 */
/*0040*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e620000209400 */
/*0060*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8e3c3f */
/*0070*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0090*/ ISETP.LE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf43270 */
/*00a0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e640000001000 */
/*00b0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0002a4000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x002fe200000001ff */
/*00e0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x004fc800078e0a03 */
/*00f0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*0100*/ IABS R4, c[0x0][0x178] ; /* 0x00005e0000047a13 */
/* 0x000fc80000000000 */
/*0110*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*0120*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e680000002100 */
/*0130*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0150*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0160*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f24070 */
/*0170*/ @!P1 IADD3 R0, R0, -R5.reuse, RZ ; /* 0x8000000500009210 */
/* 0x080fe40007ffe0ff */
/*0180*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f25270 */
/*01b0*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*01c0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e6c0000002500 */
/*01d0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01e0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*01f0*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff039a12 */
/* 0x000fc800078e33ff */
/*0200*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f06270 */
/*0210*/ IMAD R17, R17, c[0x0][0x4], R0 ; /* 0x0000010011117a24 */
/* 0x001fe400078e0200 */
/*0220*/ IMAD R4, R5, c[0x0][0x0], R2 ; /* 0x0000000005047a24 */
/* 0x002fd400078e0202 */
/*0230*/ @!P0 BRA 0xb80 ; /* 0x0000094000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0c7624 */
/* 0x000fe200078e00ff */
/*0250*/ SHF.L.U32 R7, R0, 0x6, RZ ; /* 0x0000000600077819 */
/* 0x000fe200000006ff */
/*0260*/ IMAD R5, R17, c[0x0][0x178], R2 ; /* 0x00005e0011057a24 */
/* 0x000fe200078e0202 */
/*0270*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R6, R12, -0x1, RZ ; /* 0xffffffff0c067810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD R13, R2, 0x4, R7 ; /* 0x00000004020d7824 */
/* 0x000fe200078e0207 */
/*02b0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe400078ec0ff */
/*02c0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f46070 */
/*02d0*/ LEA R6, R2, 0x480, 0x2 ; /* 0x0000048002067811 */
/* 0x000fc400078e10ff */
/*02e0*/ IADD3 R15, R7, 0x8, RZ ; /* 0x00000008070f7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ IADD3 R16, -R12, c[0x0][0x0], RZ ; /* 0x000000000c107a10 */
/* 0x000fe40007ffe1ff */
/*0300*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0310*/ IMAD R9, R14.reuse, c[0x0][0x0], R0 ; /* 0x000000000e097a24 */
/* 0x040fe400078e0200 */
/*0320*/ IMAD R10, R14, c[0x0][0x0], R5 ; /* 0x000000000e0a7a24 */
/* 0x000fe400078e0205 */
/*0330*/ IMAD R9, R9, c[0x0][0x178], R4 ; /* 0x00005e0009097a24 */
/* 0x000fca00078e0204 */
/*0340*/ IMAD.WIDE R10, R10, R8, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc800078e0208 */
/*0350*/ IMAD.WIDE R8, R9, R8, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fe400078e0208 */
/*0360*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee2000c1e1900 */
/*0380*/ MOV R18, c[0x0][0x0] ; /* 0x0000000000127a02 */
/* 0x000fe40000000f00 */
/*0390*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc40003f06270 */
/*03b0*/ ISETP.GE.AND P1, PT, R14, R3, PT ; /* 0x000000030e00720c */
/* 0x000fe20003f26270 */
/*03c0*/ STS [R13], R10 ; /* 0x0000000a0d007388 */
/* 0x0041e80000000800 */
/*03d0*/ STS [R13+0x400], R8 ; /* 0x000400080d007388 */
/* 0x0081e80000000800 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ @!P0 BRA 0xb60 ; /* 0x0000076000008947 */
/* 0x000fea0003800000 */
/*0400*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x001fe20008000000 */
/*0410*/ @!P2 BRA 0xa70 ; /* 0x000006500000a947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GT.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f04270 */
/*0430*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0440*/ IMAD.MOV.U32 R20, RZ, RZ, R15 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000f */
/*0450*/ MOV R19, R6 ; /* 0x0000000600137202 */
/* 0x000fc40000000f00 */
/*0460*/ MOV R18, R16 ; /* 0x0000001000127202 */
/* 0x000fd00000000f00 */
/*0470*/ @!P0 BRA 0x970 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.GT.AND P3, PT, R18, 0xc, PT ; /* 0x0000000c1200780c */
/* 0x000fe40003f64270 */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*04a0*/ @!P3 BRA 0x7a0 ; /* 0x000002f00000b947 */
/* 0x000fea0003800000 */
/*04b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04c0*/ LDS R24, [R19+-0x80] ; /* 0xffff800013187984 */
/* 0x000fe20000000800 */
/*04d0*/ IADD3 R18, R18, -0x10, RZ ; /* 0xfffffff012127810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*04f0*/ LDS.64 R10, [R20+-0x8] ; /* 0xfffff800140a7984 */
/* 0x000e220000000a00 */
/*0500*/ ISETP.GT.AND P3, PT, R18, 0xc, PT ; /* 0x0000000c1200780c */
/* 0x000fc60003f64270 */
/*0510*/ LDS R25, [R19+-0x40] ; /* 0xffffc00013197984 */
/* 0x000e680000000800 */
/*0520*/ LDS R23, [R19] ; /* 0x0000000013177984 */
/* 0x000fe80000000800 */
/*0530*/ LDS.64 R8, [R20] ; /* 0x0000000014087984 */
/* 0x000ea80000000a00 */
/*0540*/ LDS R22, [R19+0x40] ; /* 0x0000400013167984 */
/* 0x000ee20000000800 */
/*0550*/ FFMA R10, R24, R10, R21 ; /* 0x0000000a180a7223 */
/* 0x001fc60000000015 */
/*0560*/ LDS R21, [R19+0x80] ; /* 0x0000800013157984 */
/* 0x000fe20000000800 */
/*0570*/ FFMA R25, R25, R11, R10 ; /* 0x0000000b19197223 */
/* 0x002fc6000000000a */
/*0580*/ LDS.64 R10, [R20+0x8] ; /* 0x00000800140a7984 */
/* 0x000e220000000a00 */
/*0590*/ FFMA R8, R23, R8, R25 ; /* 0x0000000817087223 */
/* 0x004fc60000000019 */
/*05a0*/ LDS R25, [R19+0xc0] ; /* 0x0000c00013197984 */
/* 0x000e620000000800 */
/*05b0*/ FFMA R24, R22, R9, R8 ; /* 0x0000000916187223 */
/* 0x008fc60000000008 */
/*05c0*/ LDS R23, [R19+0x100] ; /* 0x0001000013177984 */
/* 0x000fe80000000800 */
/*05d0*/ LDS.64 R8, [R20+0x10] ; /* 0x0000100014087984 */
/* 0x000ea80000000a00 */
/*05e0*/ LDS R22, [R19+0x140] ; /* 0x0001400013167984 */
/* 0x000ee20000000800 */
/*05f0*/ FFMA R10, R21, R10, R24 ; /* 0x0000000a150a7223 */
/* 0x001fc60000000018 */
/*0600*/ LDS R21, [R19+0x180] ; /* 0x0001800013157984 */
/* 0x000fe20000000800 */
/*0610*/ FFMA R25, R25, R11, R10 ; /* 0x0000000b19197223 */
/* 0x002fc6000000000a */
/*0620*/ LDS.64 R10, [R20+0x18] ; /* 0x00001800140a7984 */
/* 0x000e220000000a00 */
/*0630*/ FFMA R8, R23, R8, R25 ; /* 0x0000000817087223 */
/* 0x004fc60000000019 */
/*0640*/ LDS R25, [R19+0x1c0] ; /* 0x0001c00013197984 */
/* 0x000e620000000800 */
/*0650*/ FFMA R24, R22, R9, R8 ; /* 0x0000000916187223 */
/* 0x008fc60000000008 */
/*0660*/ LDS R23, [R19+0x200] ; /* 0x0002000013177984 */
/* 0x000fe80000000800 */
/*0670*/ LDS.64 R8, [R20+0x20] ; /* 0x0000200014087984 */
/* 0x000ea80000000a00 */
/*0680*/ LDS R22, [R19+0x240] ; /* 0x0002400013167984 */
/* 0x000ee20000000800 */
/*0690*/ FFMA R10, R21, R10, R24 ; /* 0x0000000a150a7223 */
/* 0x001fc60000000018 */
/*06a0*/ LDS R21, [R19+0x280] ; /* 0x0002800013157984 */
/* 0x000fe80000000800 */
/*06b0*/ LDS R24, [R19+0x300] ; /* 0x0003000013187984 */
/* 0x000fe20000000800 */
/*06c0*/ FFMA R25, R25, R11, R10 ; /* 0x0000000b19197223 */
/* 0x002fc6000000000a */
/*06d0*/ LDS.64 R10, [R20+0x28] ; /* 0x00002800140a7984 */
/* 0x000e220000000a00 */
/*06e0*/ FFMA R8, R23, R8, R25 ; /* 0x0000000817087223 */
/* 0x004fc60000000019 */
/*06f0*/ LDS R23, [R19+0x2c0] ; /* 0x0002c00013177984 */
/* 0x000e620000000800 */
/*0700*/ FFMA R22, R22, R9, R8 ; /* 0x0000000916167223 */
/* 0x008fc60000000008 */
/*0710*/ LDS.64 R8, [R20+0x30] ; /* 0x0000300014087984 */
/* 0x0004e80000000a00 */
/*0720*/ LDS R25, [R19+0x340] ; /* 0x0003400013197984 */
/* 0x0009620000000800 */
/*0730*/ IADD3 R20, R20, 0x40, RZ ; /* 0x0000004014147810 */
/* 0x004fe40007ffe0ff */
/*0740*/ IADD3 R19, R19, 0x400, RZ ; /* 0x0000040013137810 */
/* 0x010fe20007ffe0ff */
/*0750*/ FFMA R10, R21, R10, R22 ; /* 0x0000000a150a7223 */
/* 0x001fc80000000016 */
/*0760*/ FFMA R11, R23, R11, R10 ; /* 0x0000000b170b7223 */
/* 0x002fc8000000000a */
/*0770*/ FFMA R8, R24, R8, R11 ; /* 0x0000000818087223 */
/* 0x008fc8000000000b */
/*0780*/ FFMA R21, R25, R9, R8 ; /* 0x0000000919157223 */
/* 0x020fe20000000008 */
/*0790*/ @P3 BRA 0x4c0 ; /* 0xfffffd2000003947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P3, PT, R18, 0x4, PT ; /* 0x000000041200780c */
/* 0x000fda0003f64270 */
/*07b0*/ @!P3 BRA 0x950 ; /* 0x000001900000b947 */
/* 0x000fea0003800000 */
/*07c0*/ LDS R24, [R19+-0x80] ; /* 0xffff800013187984 */
/* 0x000fe20000000800 */
/*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*07e0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*07f0*/ IADD3 R18, R18, -0x8, RZ ; /* 0xfffffff812127810 */
/* 0x000fe20007ffe0ff */
/*0800*/ LDS.64 R10, [R20+-0x8] ; /* 0xfffff800140a7984 */
/* 0x000e280000000a00 */
/*0810*/ LDS R25, [R19+-0x40] ; /* 0xffffc00013197984 */
/* 0x000e680000000800 */
/*0820*/ LDS R23, [R19] ; /* 0x0000000013177984 */
/* 0x000fe80000000800 */
/*0830*/ LDS.64 R8, [R20] ; /* 0x0000000014087984 */
/* 0x000ea80000000a00 */
/*0840*/ LDS R22, [R19+0x40] ; /* 0x0000400013167984 */
/* 0x000ee20000000800 */
/*0850*/ FFMA R10, R24, R10, R21 ; /* 0x0000000a180a7223 */
/* 0x001fc60000000015 */
/*0860*/ LDS R21, [R19+0x80] ; /* 0x0000800013157984 */
/* 0x000fe20000000800 */
/*0870*/ FFMA R25, R25, R11, R10 ; /* 0x0000000b19197223 */
/* 0x002fc6000000000a */
/*0880*/ LDS.64 R10, [R20+0x8] ; /* 0x00000800140a7984 */
/* 0x000e280000000a00 */
/*0890*/ LDS R24, [R19+0x100] ; /* 0x0001000013187984 */
/* 0x000fe20000000800 */
/*08a0*/ FFMA R8, R23, R8, R25 ; /* 0x0000000817087223 */
/* 0x004fc60000000019 */
/*08b0*/ LDS R23, [R19+0xc0] ; /* 0x0000c00013177984 */
/* 0x000e620000000800 */
/*08c0*/ FFMA R22, R22, R9, R8 ; /* 0x0000000916167223 */
/* 0x008fc60000000008 */
/*08d0*/ LDS.64 R8, [R20+0x10] ; /* 0x0000100014087984 */
/* 0x0004e80000000a00 */
/*08e0*/ LDS R25, [R19+0x140] ; /* 0x0001400013197984 */
/* 0x0009620000000800 */
/*08f0*/ IADD3 R20, R20, 0x20, RZ ; /* 0x0000002014147810 */
/* 0x004fe40007ffe0ff */
/*0900*/ IADD3 R19, R19, 0x200, RZ ; /* 0x0000020013137810 */
/* 0x010fe20007ffe0ff */
/*0910*/ FFMA R10, R21, R10, R22 ; /* 0x0000000a150a7223 */
/* 0x001fc80000000016 */
/*0920*/ FFMA R11, R23, R11, R10 ; /* 0x0000000b170b7223 */
/* 0x002fc8000000000a */
/*0930*/ FFMA R8, R24, R8, R11 ; /* 0x0000000818087223 */
/* 0x008fc8000000000b */
/*0940*/ FFMA R21, R25, R9, R8 ; /* 0x0000000919157223 */
/* 0x020fe40000000008 */
/*0950*/ ISETP.NE.OR P0, PT, R18, RZ, P0 ; /* 0x000000ff1200720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xa70 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0970*/ LDS R22, [R19+-0x80] ; /* 0xffff800013167984 */
/* 0x000fe20000000800 */
/*0980*/ IADD3 R18, R18, -0x4, RZ ; /* 0xfffffffc12127810 */
/* 0x000fe20007ffe0ff */
/*0990*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*09a0*/ LDS.64 R8, [R20+-0x8] ; /* 0xfffff80014087984 */
/* 0x000e220000000a00 */
/*09b0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc60003f05270 */
/*09c0*/ LDS R23, [R19+-0x40] ; /* 0xffffc00013177984 */
/* 0x000e680000000800 */
/*09d0*/ LDS R24, [R19] ; /* 0x0000000013187984 */
/* 0x000fe80000000800 */
/*09e0*/ LDS.64 R10, [R20] ; /* 0x00000000140a7984 */
/* 0x0004e80000000a00 */
/*09f0*/ LDS R25, [R19+0x40] ; /* 0x0000400013197984 */
/* 0x0009620000000800 */
/*0a00*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x004fc40007ffe0ff */
/*0a10*/ IADD3 R19, R19, 0x100, RZ ; /* 0x0000010013137810 */
/* 0x010fe20007ffe0ff */
/*0a20*/ FFMA R8, R22, R8, R21 ; /* 0x0000000816087223 */
/* 0x001fc80000000015 */
/*0a30*/ FFMA R9, R23, R9, R8 ; /* 0x0000000917097223 */
/* 0x002fc80000000008 */
/*0a40*/ FFMA R10, R24, R10, R9 ; /* 0x0000000a180a7223 */
/* 0x008fc80000000009 */
/*0a50*/ FFMA R21, R25, R11, R10 ; /* 0x0000000b19157223 */
/* 0x020fe2000000000a */
/*0a60*/ @P0 BRA 0x970 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0a70*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05270 */
/*0a80*/ @!P0 BRA 0xb60 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a90*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fe2000f8e00ff */
/*0aa0*/ ULEA UR5, UR4, 0x400, 0x6 ; /* 0x0000040004057891 */
/* 0x000fe2000f8e303f */
/*0ab0*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc60003f05270 */
/*0ac0*/ LEA R8, R8, R7, 0x2 ; /* 0x0000000708087211 */
/* 0x000fca00078e10ff */
/*0ad0*/ LDS R18, [R2.X4+UR5] ; /* 0x0000000502127984 */
/* 0x000fe80008004800 */
/*0ae0*/ LDS.128 R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000c00 */
/*0af0*/ FFMA R21, R18, R8, R21 ; /* 0x0000000812157223 */
/* 0x001fe20000000015 */
/*0b00*/ @!P0 BRA 0xb60 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0b10*/ ISETP.NE.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe20003f05270 */
/*0b20*/ LDS R8, [R2.X4+UR5+0x40] ; /* 0x0000400502087984 */
/* 0x000e180008004800 */
/*0b30*/ @P0 LDS R11, [R2.X4+UR5+0x80] ; /* 0x00008005020b0984 */
/* 0x000e620008004800 */
/*0b40*/ FFMA R21, R8, R9, R21 ; /* 0x0000000908157223 */
/* 0x001fc80000000015 */
/*0b50*/ @P0 FFMA R21, R11, R10, R21 ; /* 0x0000000a0b150223 */
/* 0x002fe40000000015 */
/*0b60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0b70*/ @!P1 BRA 0x300 ; /* 0xfffff78000009947 */
/* 0x000fea000383ffff */
/*0b80*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0b90*/ IMAD R2, R17, c[0x0][0x178], R4 ; /* 0x00005e0011027a24 */
/* 0x000fc800078e0204 */
/*0ba0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0bb0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17matrix_mul_sharedPfS_S_i
.globl _Z17matrix_mul_sharedPfS_S_i
.p2align 8
.type _Z17matrix_mul_sharedPfS_S_i,@function
_Z17matrix_mul_sharedPfS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v6, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s4, 0xffff
s_ashr_i32 s7, s2, 31
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s6, 0, s3
s_add_i32 s8, s2, s7
s_lshr_b32 s4, s4, 16
s_xor_b32 s8, s8, s7
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s5, v1
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[3:4], null, s14, s3, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s5
s_mul_hi_u32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s6
s_mul_hi_u32 s5, s8, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s5, s3
s_sub_i32 s6, s8, s6
s_add_i32 s8, s5, 1
s_sub_i32 s9, s6, s3
s_cmp_ge_u32 s6, s3
s_cselect_b32 s5, s8, s5
s_cselect_b32 s6, s9, s6
s_add_i32 s8, s5, 1
s_cmp_ge_u32 s6, s3
s_mov_b32 s9, 0
s_cselect_b32 s4, s8, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s7
s_sub_i32 s8, s4, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v6
v_lshlrev_b32_e32 v7, 6, v2
s_max_u32 s10, s3, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0x400, v1
v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
v_add_nc_u32_e32 v5, v7, v1
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v6, v8, v7
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mul_i32 s11, s9, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v10, s11, v2
v_add_nc_u32_e32 v9, s11, v4
s_mov_b32 s11, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v10, s2, v[3:4]
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v13, v[9:10], off
global_load_b32 v11, v[11:12], off
v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v9, v8
s_waitcnt vmcnt(1)
ds_store_b32 v5, v13
s_waitcnt vmcnt(0)
ds_store_b32 v6, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
ds_load_b32 v11, v10
ds_load_b32 v12, v9
v_add_nc_u32_e32 v10, 4, v10
v_add_nc_u32_e32 v9, 64, v9
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, v11, v12
s_cbranch_scc0 .LBB0_3
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v1, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v0, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matrix_mul_sharedPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17matrix_mul_sharedPfS_S_i, .Lfunc_end0-_Z17matrix_mul_sharedPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matrix_mul_sharedPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matrix_mul_sharedPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006c4ca_00000000-6_matrix_mul_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matrix_mul_sharedPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i
.globl _Z17matrix_mul_sharedPfS_S_i
.type _Z17matrix_mul_sharedPfS_S_i, @function
_Z17matrix_mul_sharedPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matrix_mul_sharedPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17matrix_mul_sharedPfS_S_i, .-_Z17matrix_mul_sharedPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17matrix_mul_sharedPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrix_mul_sharedPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mul_shared.hip"
.globl _Z32__device_stub__matrix_mul_sharedPfS_S_i # -- Begin function _Z32__device_stub__matrix_mul_sharedPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matrix_mul_sharedPfS_S_i,@function
_Z32__device_stub__matrix_mul_sharedPfS_S_i: # @_Z32__device_stub__matrix_mul_sharedPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matrix_mul_sharedPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__matrix_mul_sharedPfS_S_i, .Lfunc_end0-_Z32__device_stub__matrix_mul_sharedPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrix_mul_sharedPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17matrix_mul_sharedPfS_S_i,@object # @_Z17matrix_mul_sharedPfS_S_i
.section .rodata,"a",@progbits
.globl _Z17matrix_mul_sharedPfS_S_i
.p2align 3, 0x0
_Z17matrix_mul_sharedPfS_S_i:
.quad _Z32__device_stub__matrix_mul_sharedPfS_S_i
.size _Z17matrix_mul_sharedPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17matrix_mul_sharedPfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__matrix_mul_sharedPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17matrix_mul_sharedPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void smoothing(float* input, float* output, double alpha, double beta, int length) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (j < length) {
output[j] = (float) (input[j] * (1.0 + alpha) - output[j] * alpha);
output[j+1] = (float) (input[j+1] * (1.0 + beta) - output[j+1] * beta);
}
} | code for sm_80
Function : _Z9smoothingPfS_ddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0205 */
/*00b0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff097624 */
/* 0x000fe400078e00ff */
/*00f0*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000f28000c1e1900 */
/*0100*/ DADD R8, R8, 1 ; /* 0x3ff0000008087429 */
/* 0x000fe20000000000 */
/*0110*/ F2F.F64.F32 R10, R14 ; /* 0x0000000e000a7310 */
/* 0x004e300000201800 */
/*0120*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x008e620000201800 */
/*0130*/ DMUL R10, R10, c[0x0][0x170] ; /* 0x00005c000a0a7a28 */
/* 0x001e4c0000000000 */
/*0140*/ DFMA R6, R6, R8, -R10 ; /* 0x000000080606722b */
/* 0x002e14000000080a */
/*0150*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*0170*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x000ea4000c1e1900 */
/*0180*/ F2F.F64.F32 R12, R16 ; /* 0x00000010000c7310 */
/* 0x010e220000201800 */
/*0190*/ MOV R10, c[0x0][0x178] ; /* 0x00005e00000a7a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fcc0000000f00 */
/*01b0*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x000fc80000000000 */
/*01c0*/ DMUL R12, R12, c[0x0][0x178] ; /* 0x00005e000c0c7a28 */
/* 0x001e220000000000 */
/*01d0*/ F2F.F64.F32 R8, R15 ; /* 0x0000000f00087310 */
/* 0x004e2a0000201800 */
/*01e0*/ DFMA R8, R8, R10, -R12 ; /* 0x0000000a0808722b */
/* 0x001e14000000080c */
/*01f0*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*0200*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x001fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void smoothing(float* input, float* output, double alpha, double beta, int length) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (j < length) {
output[j] = (float) (input[j] * (1.0 + alpha) - output[j] * alpha);
output[j+1] = (float) (input[j+1] * (1.0 + beta) - output[j+1] * beta);
}
} | .file "tmpxft_000b226c_00000000-6_smoothing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi
.type _Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi, @function
_Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9smoothingPfS_ddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi, .-_Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi
.globl _Z9smoothingPfS_ddi
.type _Z9smoothingPfS_ddi, @function
_Z9smoothingPfS_ddi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9smoothingPfS_ddi, .-_Z9smoothingPfS_ddi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9smoothingPfS_ddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9smoothingPfS_ddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void smoothing(float* input, float* output, double alpha, double beta, int length) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (j < length) {
output[j] = (float) (input[j] * (1.0 + alpha) - output[j] * alpha);
output[j+1] = (float) (input[j+1] * (1.0 + beta) - output[j+1] * beta);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smoothing(float* input, float* output, double alpha, double beta, int length) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (j < length) {
output[j] = (float) (input[j] * (1.0 + alpha) - output[j] * alpha);
output[j+1] = (float) (input[j+1] * (1.0 + beta) - output[j+1] * beta);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smoothing(float* input, float* output, double alpha, double beta, int length) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (j < length) {
output[j] = (float) (input[j] * (1.0 + alpha) - output[j] * alpha);
output[j+1] = (float) (input[j+1] * (1.0 + beta) - output[j+1] * beta);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9smoothingPfS_ddi
.globl _Z9smoothingPfS_ddi
.p2align 8
.type _Z9smoothingPfS_ddi,@function
_Z9smoothingPfS_ddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_or_b32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v7, v[3:4], off
v_add_f64 v[9:10], s[4:5], 1.0
global_load_b32 v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v5, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v13, v[5:6], off
s_waitcnt vmcnt(2)
v_cvt_f64_f32_e32 v[7:8], v7
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[11:12], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[7:8], s[4:5]
v_fma_f64 v[7:8], v[9:10], v[11:12], -v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[7:8]
global_store_b32 v[3:4], v2, off
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[0:1], v13
v_add_f64 v[2:3], s[6:7], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[6:7]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[7:8], v4
v_fma_f64 v[0:1], v[2:3], v[7:8], -v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v[5:6], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9smoothingPfS_ddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9smoothingPfS_ddi, .Lfunc_end0-_Z9smoothingPfS_ddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9smoothingPfS_ddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9smoothingPfS_ddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smoothing(float* input, float* output, double alpha, double beta, int length) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int j = i<<1;
if (j < length) {
output[j] = (float) (input[j] * (1.0 + alpha) - output[j] * alpha);
output[j+1] = (float) (input[j+1] * (1.0 + beta) - output[j+1] * beta);
}
} | .text
.file "smoothing.hip"
.globl _Z24__device_stub__smoothingPfS_ddi # -- Begin function _Z24__device_stub__smoothingPfS_ddi
.p2align 4, 0x90
.type _Z24__device_stub__smoothingPfS_ddi,@function
_Z24__device_stub__smoothingPfS_ddi: # @_Z24__device_stub__smoothingPfS_ddi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %edx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9smoothingPfS_ddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__smoothingPfS_ddi, .Lfunc_end0-_Z24__device_stub__smoothingPfS_ddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9smoothingPfS_ddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9smoothingPfS_ddi,@object # @_Z9smoothingPfS_ddi
.section .rodata,"a",@progbits
.globl _Z9smoothingPfS_ddi
.p2align 3, 0x0
_Z9smoothingPfS_ddi:
.quad _Z24__device_stub__smoothingPfS_ddi
.size _Z9smoothingPfS_ddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9smoothingPfS_ddi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__smoothingPfS_ddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9smoothingPfS_ddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9smoothingPfS_ddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0205 */
/*00b0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff097624 */
/* 0x000fe400078e00ff */
/*00f0*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000f28000c1e1900 */
/*0100*/ DADD R8, R8, 1 ; /* 0x3ff0000008087429 */
/* 0x000fe20000000000 */
/*0110*/ F2F.F64.F32 R10, R14 ; /* 0x0000000e000a7310 */
/* 0x004e300000201800 */
/*0120*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x008e620000201800 */
/*0130*/ DMUL R10, R10, c[0x0][0x170] ; /* 0x00005c000a0a7a28 */
/* 0x001e4c0000000000 */
/*0140*/ DFMA R6, R6, R8, -R10 ; /* 0x000000080606722b */
/* 0x002e14000000080a */
/*0150*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*0170*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x000ea4000c1e1900 */
/*0180*/ F2F.F64.F32 R12, R16 ; /* 0x00000010000c7310 */
/* 0x010e220000201800 */
/*0190*/ MOV R10, c[0x0][0x178] ; /* 0x00005e00000a7a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fcc0000000f00 */
/*01b0*/ DADD R10, R10, 1 ; /* 0x3ff000000a0a7429 */
/* 0x000fc80000000000 */
/*01c0*/ DMUL R12, R12, c[0x0][0x178] ; /* 0x00005e000c0c7a28 */
/* 0x001e220000000000 */
/*01d0*/ F2F.F64.F32 R8, R15 ; /* 0x0000000f00087310 */
/* 0x004e2a0000201800 */
/*01e0*/ DFMA R8, R8, R10, -R12 ; /* 0x0000000a0808722b */
/* 0x001e14000000080c */
/*01f0*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*0200*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x001fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9smoothingPfS_ddi
.globl _Z9smoothingPfS_ddi
.p2align 8
.type _Z9smoothingPfS_ddi,@function
_Z9smoothingPfS_ddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_or_b32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v7, v[3:4], off
v_add_f64 v[9:10], s[4:5], 1.0
global_load_b32 v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v5, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v13, v[5:6], off
s_waitcnt vmcnt(2)
v_cvt_f64_f32_e32 v[7:8], v7
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[11:12], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[7:8], s[4:5]
v_fma_f64 v[7:8], v[9:10], v[11:12], -v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[7:8]
global_store_b32 v[3:4], v2, off
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[0:1], v13
v_add_f64 v[2:3], s[6:7], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[6:7]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[7:8], v4
v_fma_f64 v[0:1], v[2:3], v[7:8], -v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v[5:6], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9smoothingPfS_ddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9smoothingPfS_ddi, .Lfunc_end0-_Z9smoothingPfS_ddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9smoothingPfS_ddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9smoothingPfS_ddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b226c_00000000-6_smoothing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi
.type _Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi, @function
_Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9smoothingPfS_ddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi, .-_Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi
.globl _Z9smoothingPfS_ddi
.type _Z9smoothingPfS_ddi, @function
_Z9smoothingPfS_ddi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9smoothingPfS_ddiPfS_ddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9smoothingPfS_ddi, .-_Z9smoothingPfS_ddi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9smoothingPfS_ddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9smoothingPfS_ddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "smoothing.hip"
.globl _Z24__device_stub__smoothingPfS_ddi # -- Begin function _Z24__device_stub__smoothingPfS_ddi
.p2align 4, 0x90
.type _Z24__device_stub__smoothingPfS_ddi,@function
_Z24__device_stub__smoothingPfS_ddi: # @_Z24__device_stub__smoothingPfS_ddi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %edx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9smoothingPfS_ddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__smoothingPfS_ddi, .Lfunc_end0-_Z24__device_stub__smoothingPfS_ddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9smoothingPfS_ddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9smoothingPfS_ddi,@object # @_Z9smoothingPfS_ddi
.section .rodata,"a",@progbits
.globl _Z9smoothingPfS_ddi
.p2align 3, 0x0
_Z9smoothingPfS_ddi:
.quad _Z24__device_stub__smoothingPfS_ddi
.size _Z9smoothingPfS_ddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9smoothingPfS_ddi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__smoothingPfS_ddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9smoothingPfS_ddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <pthread.h>
#define THREADS 4
int intervalsT=100000000;
double partialStore[]={0.0, 0.0, 0.0, 0.0};
// -:YOUR CODE HERE:-
void *threadRoutine(void *param) {
// -:YOUR CODE HERE:-
return 0;
}
void calculatePIHostMultiple(){
// -:YOUR CODE HERE:-
}
void calculatePIHostSingle(){
int i;
double height,x;
double store,base;
int intervals=100000000;
base=(double)(1.0/intervals);
for (i=0, store=0.0, x=0.0; i<intervals; i++) {
x = i * base;
height = 4/(1 + x * x);
store += base * height;
}
printf("PI (single th) =%f \n",store);
}
int main(){
calculatePIHostSingle();
calculatePIHostMultiple();
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <pthread.h>
#define THREADS 4
int intervalsT=100000000;
double partialStore[]={0.0, 0.0, 0.0, 0.0};
// -:YOUR CODE HERE:-
void *threadRoutine(void *param) {
// -:YOUR CODE HERE:-
return 0;
}
void calculatePIHostMultiple(){
// -:YOUR CODE HERE:-
}
void calculatePIHostSingle(){
int i;
double height,x;
double store,base;
int intervals=100000000;
base=(double)(1.0/intervals);
for (i=0, store=0.0, x=0.0; i<intervals; i++) {
x = i * base;
height = 4/(1 + x * x);
store += base * height;
}
printf("PI (single th) =%f \n",store);
}
int main(){
calculatePIHostSingle();
calculatePIHostMultiple();
} | .file "tmpxft_000e8faf_00000000-6_03pi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13threadRoutinePv
.type _Z13threadRoutinePv, @function
_Z13threadRoutinePv:
.LFB2067:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2067:
.size _Z13threadRoutinePv, .-_Z13threadRoutinePv
.globl _Z23calculatePIHostMultiplev
.type _Z23calculatePIHostMultiplev, @function
_Z23calculatePIHostMultiplev:
.LFB2068:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2068:
.size _Z23calculatePIHostMultiplev, .-_Z23calculatePIHostMultiplev
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "PI (single th) =%f \n"
.text
.globl _Z21calculatePIHostSinglev
.type _Z21calculatePIHostSinglev, @function
_Z21calculatePIHostSinglev:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pxor %xmm2, %xmm2
movl $0, %eax
movsd .LC1(%rip), %xmm3
movsd .LC2(%rip), %xmm5
movsd .LC3(%rip), %xmm4
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm3, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm5, %xmm0
movapd %xmm4, %xmm1
divsd %xmm0, %xmm1
mulsd %xmm3, %xmm1
addsd %xmm1, %xmm2
addl $1, %eax
cmpl $100000000, %eax
jne .L6
movapd %xmm2, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _Z21calculatePIHostSinglev, .-_Z21calculatePIHostSinglev
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21calculatePIHostSinglev
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl partialStore
.bss
.align 32
.type partialStore, @object
.size partialStore, 32
partialStore:
.zero 32
.globl intervalsT
.data
.align 4
.type intervalsT, @object
.size intervalsT, 4
intervalsT:
.long 100000000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -500134854
.long 1044740494
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <pthread.h>
#define THREADS 4
int intervalsT=100000000;
double partialStore[]={0.0, 0.0, 0.0, 0.0};
// -:YOUR CODE HERE:-
void *threadRoutine(void *param) {
// -:YOUR CODE HERE:-
return 0;
}
void calculatePIHostMultiple(){
// -:YOUR CODE HERE:-
}
void calculatePIHostSingle(){
int i;
double height,x;
double store,base;
int intervals=100000000;
base=(double)(1.0/intervals);
for (i=0, store=0.0, x=0.0; i<intervals; i++) {
x = i * base;
height = 4/(1 + x * x);
store += base * height;
}
printf("PI (single th) =%f \n",store);
}
int main(){
calculatePIHostSingle();
calculatePIHostMultiple();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <pthread.h>
#define THREADS 4
int intervalsT=100000000;
double partialStore[]={0.0, 0.0, 0.0, 0.0};
// -:YOUR CODE HERE:-
void *threadRoutine(void *param) {
// -:YOUR CODE HERE:-
return 0;
}
void calculatePIHostMultiple(){
// -:YOUR CODE HERE:-
}
void calculatePIHostSingle(){
int i;
double height,x;
double store,base;
int intervals=100000000;
base=(double)(1.0/intervals);
for (i=0, store=0.0, x=0.0; i<intervals; i++) {
x = i * base;
height = 4/(1 + x * x);
store += base * height;
}
printf("PI (single th) =%f \n",store);
}
int main(){
calculatePIHostSingle();
calculatePIHostMultiple();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <pthread.h>
#define THREADS 4
int intervalsT=100000000;
double partialStore[]={0.0, 0.0, 0.0, 0.0};
// -:YOUR CODE HERE:-
void *threadRoutine(void *param) {
// -:YOUR CODE HERE:-
return 0;
}
void calculatePIHostMultiple(){
// -:YOUR CODE HERE:-
}
void calculatePIHostSingle(){
int i;
double height,x;
double store,base;
int intervals=100000000;
base=(double)(1.0/intervals);
for (i=0, store=0.0, x=0.0; i<intervals; i++) {
x = i * base;
height = 4/(1 + x * x);
store += base * height;
}
printf("PI (single th) =%f \n",store);
}
int main(){
calculatePIHostSingle();
calculatePIHostMultiple();
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <pthread.h>
#define THREADS 4
int intervalsT=100000000;
double partialStore[]={0.0, 0.0, 0.0, 0.0};
// -:YOUR CODE HERE:-
void *threadRoutine(void *param) {
// -:YOUR CODE HERE:-
return 0;
}
void calculatePIHostMultiple(){
// -:YOUR CODE HERE:-
}
void calculatePIHostSingle(){
int i;
double height,x;
double store,base;
int intervals=100000000;
base=(double)(1.0/intervals);
for (i=0, store=0.0, x=0.0; i<intervals; i++) {
x = i * base;
height = 4/(1 + x * x);
store += base * height;
}
printf("PI (single th) =%f \n",store);
}
int main(){
calculatePIHostSingle();
calculatePIHostMultiple();
} | .text
.file "03pi.hip"
.globl _Z13threadRoutinePv # -- Begin function _Z13threadRoutinePv
.p2align 4, 0x90
.type _Z13threadRoutinePv,@function
_Z13threadRoutinePv: # @_Z13threadRoutinePv
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z13threadRoutinePv, .Lfunc_end0-_Z13threadRoutinePv
.cfi_endproc
# -- End function
.globl _Z23calculatePIHostMultiplev # -- Begin function _Z23calculatePIHostMultiplev
.p2align 4, 0x90
.type _Z23calculatePIHostMultiplev,@function
_Z23calculatePIHostMultiplev: # @_Z23calculatePIHostMultiplev
.cfi_startproc
# %bb.0:
retq
.Lfunc_end1:
.size _Z23calculatePIHostMultiplev, .Lfunc_end1-_Z23calculatePIHostMultiplev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z21calculatePIHostSinglev
.LCPI2_0:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.LCPI2_2:
.quad 0x4010000000000000 # double 4
.text
.globl _Z21calculatePIHostSinglev
.p2align 4, 0x90
.type _Z21calculatePIHostSinglev,@function
_Z21calculatePIHostSinglev: # @_Z21calculatePIHostSinglev
.cfi_startproc
# %bb.0:
xorpd %xmm1, %xmm1
movl $100000000, %eax # imm = 0x5F5E100
movsd .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI2_2(%rip), %xmm4 # xmm4 = mem[0],zero
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movapd %xmm1, %xmm5
mulsd %xmm2, %xmm5
mulsd %xmm5, %xmm5
addsd %xmm3, %xmm5
movapd %xmm4, %xmm6
divsd %xmm5, %xmm6
mulsd %xmm2, %xmm6
addsd %xmm6, %xmm0
addsd %xmm3, %xmm1
decl %eax
jne .LBB2_1
# %bb.2:
movl $.L.str, %edi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end2:
.size _Z21calculatePIHostSinglev, .Lfunc_end2-_Z21calculatePIHostSinglev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.LCPI3_1:
.quad 0x3ff0000000000000 # double 1
.LCPI3_2:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorpd %xmm1, %xmm1
movl $100000000, %eax # imm = 0x5F5E100
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI3_2(%rip), %xmm4 # xmm4 = mem[0],zero
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movapd %xmm1, %xmm5
mulsd %xmm2, %xmm5
mulsd %xmm5, %xmm5
addsd %xmm3, %xmm5
movapd %xmm4, %xmm6
divsd %xmm5, %xmm6
mulsd %xmm2, %xmm6
addsd %xmm6, %xmm0
addsd %xmm3, %xmm1
decl %eax
jne .LBB3_1
# %bb.2: # %_Z21calculatePIHostSinglev.exit
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type intervalsT,@object # @intervalsT
.data
.globl intervalsT
.p2align 2, 0x0
intervalsT:
.long 100000000 # 0x5f5e100
.size intervalsT, 4
.type partialStore,@object # @partialStore
.bss
.globl partialStore
.p2align 4, 0x0
partialStore:
.zero 32
.size partialStore, 32
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "PI (single th) =%f \n"
.size .L.str, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e8faf_00000000-6_03pi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13threadRoutinePv
.type _Z13threadRoutinePv, @function
_Z13threadRoutinePv:
.LFB2067:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2067:
.size _Z13threadRoutinePv, .-_Z13threadRoutinePv
.globl _Z23calculatePIHostMultiplev
.type _Z23calculatePIHostMultiplev, @function
_Z23calculatePIHostMultiplev:
.LFB2068:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2068:
.size _Z23calculatePIHostMultiplev, .-_Z23calculatePIHostMultiplev
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "PI (single th) =%f \n"
.text
.globl _Z21calculatePIHostSinglev
.type _Z21calculatePIHostSinglev, @function
_Z21calculatePIHostSinglev:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pxor %xmm2, %xmm2
movl $0, %eax
movsd .LC1(%rip), %xmm3
movsd .LC2(%rip), %xmm5
movsd .LC3(%rip), %xmm4
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm3, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm5, %xmm0
movapd %xmm4, %xmm1
divsd %xmm0, %xmm1
mulsd %xmm3, %xmm1
addsd %xmm1, %xmm2
addl $1, %eax
cmpl $100000000, %eax
jne .L6
movapd %xmm2, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _Z21calculatePIHostSinglev, .-_Z21calculatePIHostSinglev
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21calculatePIHostSinglev
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl partialStore
.bss
.align 32
.type partialStore, @object
.size partialStore, 32
partialStore:
.zero 32
.globl intervalsT
.data
.align 4
.type intervalsT, @object
.size intervalsT, 4
intervalsT:
.long 100000000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -500134854
.long 1044740494
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "03pi.hip"
.globl _Z13threadRoutinePv # -- Begin function _Z13threadRoutinePv
.p2align 4, 0x90
.type _Z13threadRoutinePv,@function
_Z13threadRoutinePv: # @_Z13threadRoutinePv
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z13threadRoutinePv, .Lfunc_end0-_Z13threadRoutinePv
.cfi_endproc
# -- End function
.globl _Z23calculatePIHostMultiplev # -- Begin function _Z23calculatePIHostMultiplev
.p2align 4, 0x90
.type _Z23calculatePIHostMultiplev,@function
_Z23calculatePIHostMultiplev: # @_Z23calculatePIHostMultiplev
.cfi_startproc
# %bb.0:
retq
.Lfunc_end1:
.size _Z23calculatePIHostMultiplev, .Lfunc_end1-_Z23calculatePIHostMultiplev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z21calculatePIHostSinglev
.LCPI2_0:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.LCPI2_2:
.quad 0x4010000000000000 # double 4
.text
.globl _Z21calculatePIHostSinglev
.p2align 4, 0x90
.type _Z21calculatePIHostSinglev,@function
_Z21calculatePIHostSinglev: # @_Z21calculatePIHostSinglev
.cfi_startproc
# %bb.0:
xorpd %xmm1, %xmm1
movl $100000000, %eax # imm = 0x5F5E100
movsd .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI2_2(%rip), %xmm4 # xmm4 = mem[0],zero
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movapd %xmm1, %xmm5
mulsd %xmm2, %xmm5
mulsd %xmm5, %xmm5
addsd %xmm3, %xmm5
movapd %xmm4, %xmm6
divsd %xmm5, %xmm6
mulsd %xmm2, %xmm6
addsd %xmm6, %xmm0
addsd %xmm3, %xmm1
decl %eax
jne .LBB2_1
# %bb.2:
movl $.L.str, %edi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end2:
.size _Z21calculatePIHostSinglev, .Lfunc_end2-_Z21calculatePIHostSinglev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.LCPI3_1:
.quad 0x3ff0000000000000 # double 1
.LCPI3_2:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorpd %xmm1, %xmm1
movl $100000000, %eax # imm = 0x5F5E100
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI3_2(%rip), %xmm4 # xmm4 = mem[0],zero
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movapd %xmm1, %xmm5
mulsd %xmm2, %xmm5
mulsd %xmm5, %xmm5
addsd %xmm3, %xmm5
movapd %xmm4, %xmm6
divsd %xmm5, %xmm6
mulsd %xmm2, %xmm6
addsd %xmm6, %xmm0
addsd %xmm3, %xmm1
decl %eax
jne .LBB3_1
# %bb.2: # %_Z21calculatePIHostSinglev.exit
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type intervalsT,@object # @intervalsT
.data
.globl intervalsT
.p2align 2, 0x0
intervalsT:
.long 100000000 # 0x5f5e100
.size intervalsT, 4
.type partialStore,@object # @partialStore
.bss
.globl partialStore
.p2align 4, 0x0
partialStore:
.zero 32
.size partialStore, 32
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "PI (single th) =%f \n"
.size .L.str, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
/* Vector addition: C = A + B.
*
* This sample is a very basic sample that implements element by element
* vector addition. It is the same as the sample illustrating Chapter 3
* of the programming guide with some additions like error checking.
*
*/
// Device code
extern "C" __global__ void VecAdd(const float* A, const float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | code for sm_80
Function : VecAdd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
/* Vector addition: C = A + B.
*
* This sample is a very basic sample that implements element by element
* vector addition. It is the same as the sample illustrating Chapter 3
* of the programming guide with some additions like error checking.
*
*/
// Device code
extern "C" __global__ void VecAdd(const float* A, const float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | .file "tmpxft_00106266_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi
.type _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi, @function
_Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq VecAdd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi, .-_Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi
.globl VecAdd
.type VecAdd, @function
VecAdd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size VecAdd, .-VecAdd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "VecAdd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq VecAdd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
/* Vector addition: C = A + B.
*
* This sample is a very basic sample that implements element by element
* vector addition. It is the same as the sample illustrating Chapter 3
* of the programming guide with some additions like error checking.
*
*/
// Device code
extern "C" __global__ void VecAdd(const float* A, const float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | #include <hip/hip_runtime.h>
/*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
/* Vector addition: C = A + B.
*
* This sample is a very basic sample that implements element by element
* vector addition. It is the same as the sample illustrating Chapter 3
* of the programming guide with some additions like error checking.
*
*/
// Device code
extern "C" __global__ void VecAdd(const float* A, const float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
/* Vector addition: C = A + B.
*
* This sample is a very basic sample that implements element by element
* vector addition. It is the same as the sample illustrating Chapter 3
* of the programming guide with some additions like error checking.
*
*/
// Device code
extern "C" __global__ void VecAdd(const float* A, const float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected VecAdd
.globl VecAdd
.p2align 8
.type VecAdd,@function
VecAdd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel VecAdd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size VecAdd, .Lfunc_end0-VecAdd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: VecAdd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: VecAdd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
/* Vector addition: C = A + B.
*
* This sample is a very basic sample that implements element by element
* vector addition. It is the same as the sample illustrating Chapter 3
* of the programming guide with some additions like error checking.
*
*/
// Device code
extern "C" __global__ void VecAdd(const float* A, const float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | .text
.file "vectorAdd.hip"
.globl __device_stub__VecAdd # -- Begin function __device_stub__VecAdd
.p2align 4, 0x90
.type __device_stub__VecAdd,@function
__device_stub__VecAdd: # @__device_stub__VecAdd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $VecAdd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__VecAdd, .Lfunc_end0-__device_stub__VecAdd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $VecAdd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type VecAdd,@object # @VecAdd
.section .rodata,"a",@progbits
.globl VecAdd
.p2align 3, 0x0
VecAdd:
.quad __device_stub__VecAdd
.size VecAdd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "VecAdd"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__VecAdd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym VecAdd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : VecAdd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected VecAdd
.globl VecAdd
.p2align 8
.type VecAdd,@function
VecAdd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel VecAdd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size VecAdd, .Lfunc_end0-VecAdd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: VecAdd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: VecAdd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00106266_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi
.type _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi, @function
_Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq VecAdd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi, .-_Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi
.globl VecAdd
.type VecAdd, @function
VecAdd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size VecAdd, .-VecAdd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "VecAdd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq VecAdd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd.hip"
.globl __device_stub__VecAdd # -- Begin function __device_stub__VecAdd
.p2align 4, 0x90
.type __device_stub__VecAdd,@function
__device_stub__VecAdd: # @__device_stub__VecAdd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $VecAdd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__VecAdd, .Lfunc_end0-__device_stub__VecAdd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $VecAdd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type VecAdd,@object # @VecAdd
.section .rodata,"a",@progbits
.globl VecAdd
.p2align 3, 0x0
VecAdd:
.quad __device_stub__VecAdd
.size VecAdd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "VecAdd"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__VecAdd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym VecAdd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void NegativeCorrelationForwardDivideKernel( float* outputPtr, int thisLayerSize, int inputModelCount )
{
// j: current layer neuron id
int j = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (j < thisLayerSize)
{
outputPtr[j] /= (float)inputModelCount;
}
} | code for sm_80
Function : _Z38NegativeCorrelationForwardDivideKernelPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ I2F R4, c[0x0][0x16c] ; /* 0x00005b0000047b06 */
/* 0x000e220000201400 */
/*00d0*/ BSSY B0, 0x190 ; /* 0x000000b000007945 */
/* 0x000fee0003800000 */
/*00e0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x001e240000001000 */
/*00f0*/ FFMA R0, -R4, R7, 1 ; /* 0x3f80000004007423 */
/* 0x001fc80000000107 */
/*0100*/ FFMA R0, R7, R0, R7 ; /* 0x0000000007007223 */
/* 0x000fe40000000007 */
/*0110*/ FCHK P0, R5, R4 ; /* 0x0000000405007302 */
/* 0x004e240000000000 */
/*0120*/ FFMA R7, R5, R0, RZ ; /* 0x0000000005077223 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, -R4, R7, R5 ; /* 0x0000000704067223 */
/* 0x000fc80000000105 */
/*0140*/ FFMA R7, R0, R6, R7 ; /* 0x0000000600077223 */
/* 0x000fe20000000007 */
/*0150*/ @!P0 BRA 0x180 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0160*/ MOV R0, 0x180 ; /* 0x0000018000007802 */
/* 0x000fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x1b0 ; /* 0x0000003000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ SHF.R.U32.HI R7, RZ, 0x17, R4.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011604 */
/*01c0*/ BSSY B1, 0x810 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01d0*/ SHF.R.U32.HI R6, RZ, 0x17, R5.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011605 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*01f0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0210*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0220*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*0230*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0250*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0260*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0270*/ @!P0 BRA 0x3f0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0280*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f1c200 */
/*0290*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02b0*/ @P0 BRA 0x7f0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02c0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*02d0*/ @!P0 BRA 0x7d0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*02e0*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*02f0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0300*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*0310*/ @!P1 BRA !P2, 0x7d0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0320*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0330*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0340*/ @P1 BRA 0x7b0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0350*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0360*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0370*/ @P0 BRA 0x780 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0380*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0390*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*03a0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*03b0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*03c0*/ @!P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005088823 */
/* 0x000fe400000000ff */
/*03d0*/ @!P1 FFMA R9, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004099823 */
/* 0x000fe200000000ff */
/*03e0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe200078eb8ff */
/*0400*/ BSSY B2, 0x770 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0410*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0420*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*0430*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*0440*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*0450*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0460*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*0470*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0480*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*0490*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*04a0*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*04b0*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*04c0*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*04d0*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*04e0*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*04f0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0500*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0510*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0520*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0530*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0540*/ @!P0 BRA 0x750 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0560*/ @P0 BRA 0x720 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0580*/ @P0 BRA 0x760 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05a0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05b0*/ @!P0 BRA 0x760 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05c0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*05d0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*05e0*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*05f0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0600*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0610*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0620*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0640*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0650*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0660*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0670*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0680*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0690*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06b0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*06c0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*06d0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*06e0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*06f0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0700*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0710*/ BRA 0x760 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0720*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0730*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x760 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0760*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x800 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0790*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x800 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*07c0*/ BRA 0x800 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07d0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*07e0*/ BRA 0x800 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07f0*/ FADD.FTZ R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe40000010000 */
/*0800*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*0820*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0830*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0840*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff7b004007950 */
/* 0x000fea0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void NegativeCorrelationForwardDivideKernel( float* outputPtr, int thisLayerSize, int inputModelCount )
{
// j: current layer neuron id
int j = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (j < thisLayerSize)
{
outputPtr[j] /= (float)inputModelCount;
}
} | .file "tmpxft_00058dcb_00000000-6_NegativeCorrelationForwardDivideKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii
.type _Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii, @function
_Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z38NegativeCorrelationForwardDivideKernelPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii, .-_Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii
.globl _Z38NegativeCorrelationForwardDivideKernelPfii
.type _Z38NegativeCorrelationForwardDivideKernelPfii, @function
_Z38NegativeCorrelationForwardDivideKernelPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z38NegativeCorrelationForwardDivideKernelPfii, .-_Z38NegativeCorrelationForwardDivideKernelPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z38NegativeCorrelationForwardDivideKernelPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z38NegativeCorrelationForwardDivideKernelPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void NegativeCorrelationForwardDivideKernel( float* outputPtr, int thisLayerSize, int inputModelCount )
{
// j: current layer neuron id
int j = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (j < thisLayerSize)
{
outputPtr[j] /= (float)inputModelCount;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NegativeCorrelationForwardDivideKernel( float* outputPtr, int thisLayerSize, int inputModelCount )
{
// j: current layer neuron id
int j = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (j < thisLayerSize)
{
outputPtr[j] /= (float)inputModelCount;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NegativeCorrelationForwardDivideKernel( float* outputPtr, int thisLayerSize, int inputModelCount )
{
// j: current layer neuron id
int j = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (j < thisLayerSize)
{
outputPtr[j] /= (float)inputModelCount;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z38NegativeCorrelationForwardDivideKernelPfii
.globl _Z38NegativeCorrelationForwardDivideKernelPfii
.p2align 8
.type _Z38NegativeCorrelationForwardDivideKernelPfii,@function
_Z38NegativeCorrelationForwardDivideKernelPfii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cvt_f32_i32_e32 v3, s0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z38NegativeCorrelationForwardDivideKernelPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z38NegativeCorrelationForwardDivideKernelPfii, .Lfunc_end0-_Z38NegativeCorrelationForwardDivideKernelPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z38NegativeCorrelationForwardDivideKernelPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z38NegativeCorrelationForwardDivideKernelPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NegativeCorrelationForwardDivideKernel( float* outputPtr, int thisLayerSize, int inputModelCount )
{
// j: current layer neuron id
int j = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (j < thisLayerSize)
{
outputPtr[j] /= (float)inputModelCount;
}
} | .text
.file "NegativeCorrelationForwardDivideKernel.hip"
.globl _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii # -- Begin function _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.p2align 4, 0x90
.type _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii,@function
_Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii: # @_Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z38NegativeCorrelationForwardDivideKernelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii, .Lfunc_end0-_Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z38NegativeCorrelationForwardDivideKernelPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z38NegativeCorrelationForwardDivideKernelPfii,@object # @_Z38NegativeCorrelationForwardDivideKernelPfii
.section .rodata,"a",@progbits
.globl _Z38NegativeCorrelationForwardDivideKernelPfii
.p2align 3, 0x0
_Z38NegativeCorrelationForwardDivideKernelPfii:
.quad _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.size _Z38NegativeCorrelationForwardDivideKernelPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z38NegativeCorrelationForwardDivideKernelPfii"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z38NegativeCorrelationForwardDivideKernelPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z38NegativeCorrelationForwardDivideKernelPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ I2F R4, c[0x0][0x16c] ; /* 0x00005b0000047b06 */
/* 0x000e220000201400 */
/*00d0*/ BSSY B0, 0x190 ; /* 0x000000b000007945 */
/* 0x000fee0003800000 */
/*00e0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x001e240000001000 */
/*00f0*/ FFMA R0, -R4, R7, 1 ; /* 0x3f80000004007423 */
/* 0x001fc80000000107 */
/*0100*/ FFMA R0, R7, R0, R7 ; /* 0x0000000007007223 */
/* 0x000fe40000000007 */
/*0110*/ FCHK P0, R5, R4 ; /* 0x0000000405007302 */
/* 0x004e240000000000 */
/*0120*/ FFMA R7, R5, R0, RZ ; /* 0x0000000005077223 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, -R4, R7, R5 ; /* 0x0000000704067223 */
/* 0x000fc80000000105 */
/*0140*/ FFMA R7, R0, R6, R7 ; /* 0x0000000600077223 */
/* 0x000fe20000000007 */
/*0150*/ @!P0 BRA 0x180 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0160*/ MOV R0, 0x180 ; /* 0x0000018000007802 */
/* 0x000fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x1b0 ; /* 0x0000003000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ SHF.R.U32.HI R7, RZ, 0x17, R4.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011604 */
/*01c0*/ BSSY B1, 0x810 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01d0*/ SHF.R.U32.HI R6, RZ, 0x17, R5.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011605 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*01f0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0210*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0220*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*0230*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0250*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0260*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0270*/ @!P0 BRA 0x3f0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0280*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f1c200 */
/*0290*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02b0*/ @P0 BRA 0x7f0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02c0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*02d0*/ @!P0 BRA 0x7d0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*02e0*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*02f0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0300*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*0310*/ @!P1 BRA !P2, 0x7d0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0320*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0330*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0340*/ @P1 BRA 0x7b0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0350*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0360*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0370*/ @P0 BRA 0x780 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0380*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0390*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*03a0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*03b0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*03c0*/ @!P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005088823 */
/* 0x000fe400000000ff */
/*03d0*/ @!P1 FFMA R9, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004099823 */
/* 0x000fe200000000ff */
/*03e0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe200078eb8ff */
/*0400*/ BSSY B2, 0x770 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0410*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0420*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*0430*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*0440*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*0450*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0460*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*0470*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0480*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*0490*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*04a0*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*04b0*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*04c0*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*04d0*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*04e0*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*04f0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0500*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0510*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0520*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0530*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0540*/ @!P0 BRA 0x750 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0560*/ @P0 BRA 0x720 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0580*/ @P0 BRA 0x760 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05a0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05b0*/ @!P0 BRA 0x760 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05c0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*05d0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*05e0*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*05f0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0600*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0610*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0620*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0640*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0650*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0660*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0670*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0680*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0690*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06b0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*06c0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*06d0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*06e0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*06f0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0700*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0710*/ BRA 0x760 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0720*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0730*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x760 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0760*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x800 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0790*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x800 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*07c0*/ BRA 0x800 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07d0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*07e0*/ BRA 0x800 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07f0*/ FADD.FTZ R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe40000010000 */
/*0800*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*0820*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0830*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0840*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff7b004007950 */
/* 0x000fea0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z38NegativeCorrelationForwardDivideKernelPfii
.globl _Z38NegativeCorrelationForwardDivideKernelPfii
.p2align 8
.type _Z38NegativeCorrelationForwardDivideKernelPfii,@function
_Z38NegativeCorrelationForwardDivideKernelPfii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cvt_f32_i32_e32 v3, s0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z38NegativeCorrelationForwardDivideKernelPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z38NegativeCorrelationForwardDivideKernelPfii, .Lfunc_end0-_Z38NegativeCorrelationForwardDivideKernelPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z38NegativeCorrelationForwardDivideKernelPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z38NegativeCorrelationForwardDivideKernelPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00058dcb_00000000-6_NegativeCorrelationForwardDivideKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii
.type _Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii, @function
_Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z38NegativeCorrelationForwardDivideKernelPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii, .-_Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii
.globl _Z38NegativeCorrelationForwardDivideKernelPfii
.type _Z38NegativeCorrelationForwardDivideKernelPfii, @function
_Z38NegativeCorrelationForwardDivideKernelPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z38NegativeCorrelationForwardDivideKernelPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z38NegativeCorrelationForwardDivideKernelPfii, .-_Z38NegativeCorrelationForwardDivideKernelPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z38NegativeCorrelationForwardDivideKernelPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z38NegativeCorrelationForwardDivideKernelPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NegativeCorrelationForwardDivideKernel.hip"
.globl _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii # -- Begin function _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.p2align 4, 0x90
.type _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii,@function
_Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii: # @_Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z38NegativeCorrelationForwardDivideKernelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii, .Lfunc_end0-_Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z38NegativeCorrelationForwardDivideKernelPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z38NegativeCorrelationForwardDivideKernelPfii,@object # @_Z38NegativeCorrelationForwardDivideKernelPfii
.section .rodata,"a",@progbits
.globl _Z38NegativeCorrelationForwardDivideKernelPfii
.p2align 3, 0x0
_Z38NegativeCorrelationForwardDivideKernelPfii:
.quad _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.size _Z38NegativeCorrelationForwardDivideKernelPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z38NegativeCorrelationForwardDivideKernelPfii"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z53__device_stub__NegativeCorrelationForwardDivideKernelPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z38NegativeCorrelationForwardDivideKernelPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reduce_normal_eqs_64_GPU(float *d_C_reduced, float *d_C, int gridDim_x_normal_equations) {
int tid = threadIdx.x;
int bx = blockIdx.x;
// put data in shared memory
int ind = blockIdx.y * gridDim.x * gridDim_x_normal_equations * 64 +
bx * gridDim_x_normal_equations * 64 + tid;
__shared__ float DATA[64];
// load and sum the first 20 elements
float tmp = 0.0f;
for (int i = 0; i < gridDim_x_normal_equations; i++)
tmp += d_C[ind + i * 64];
DATA[tid] = tmp;
__syncthreads(); // ensure reading stage has finished
// reduction
if (tid < 32) { // warp-reduce
DATA[tid] += DATA[tid + 32];
__syncthreads();
DATA[tid] += DATA[tid + 16];
__syncthreads();
DATA[tid] += DATA[tid + 8];
__syncthreads();
DATA[tid] += DATA[tid + 4];
__syncthreads();
DATA[tid] += DATA[tid + 2];
__syncthreads();
DATA[tid] += DATA[tid + 1];
__syncthreads();
}
// write results
if (tid == 0)
d_C_reduced[blockIdx.y * gridDim.x + bx] = DATA[0];
} | code for sm_80
Function : _Z24reduce_normal_eqs_64_GPUPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fd400078e0203 */
/*0090*/ @!P0 BRA 0x320 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R3, R6.reuse, -0x1, RZ ; /* 0xffffffff06037810 */
/* 0x040fe20007ffe0ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe200078ec0ff */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*00f0*/ IMAD R3, R0, c[0x0][0x170], RZ ; /* 0x00005c0000037a24 */
/* 0x000fe200078e02ff */
/*0100*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fd60003f05270 */
/*0110*/ @!P1 BRA 0x270 ; /* 0x0000015000009947 */
/* 0x000fea0003800000 */
/*0120*/ LEA R4, R3, R2, 0x6 ; /* 0x0000000203047211 */
/* 0x002fe200078e30ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R11, R6, -c[0x0][0x170], RZ ; /* 0x80005c00060b7a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0160*/ IADD3 R8, R4, 0xc0, RZ ; /* 0x000000c004087810 */
/* 0x000fc60007ffe0ff */
/*0170*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0180*/ IADD3 R4, R8, -0xc0, RZ ; /* 0xffffff4008047810 */
/* 0x000fd20007ffe0ff */
/*0190*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*01a0*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R9, [R4.64+0x100] ; /* 0x0001000604097981 */
/* 0x000ee8000c1e1900 */
/*01c0*/ LDG.E R12, [R4.64+0x200] ; /* 0x00020006040c7981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R14, [R4.64+0x300] ; /* 0x00030006040e7981 */
/* 0x000f62000c1e1900 */
/*01e0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*01f0*/ IADD3 R8, R8, 0x100, RZ ; /* 0x0000010008087810 */
/* 0x000fe20007ffe0ff */
/*0200*/ FADD R10, R10, R7 ; /* 0x000000070a0a7221 */
/* 0x004fc80000000000 */
/*0210*/ IADD3 R7, R11, UR4, RZ ; /* 0x000000040b077c10 */
/* 0x000fe2000fffe0ff */
/*0220*/ FADD R9, R10, R9 ; /* 0x000000090a097221 */
/* 0x008fc60000000000 */
/*0230*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*0240*/ FADD R9, R9, R12 ; /* 0x0000000c09097221 */
/* 0x010fc80000000000 */
/*0250*/ FADD R7, R9, R14 ; /* 0x0000000e09077221 */
/* 0x020fd00000000000 */
/*0260*/ @P1 BRA 0x170 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*0270*/ @!P0 BRA 0x320 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R3, R3, UR4, RZ ; /* 0x0000000403037c10 */
/* 0x000fca000fffe0ff */
/*0290*/ IMAD R3, R3, 0x40, R2 ; /* 0x0000004003037824 */
/* 0x002fe400078e0202 */
/*02a0*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fca0000000f00 */
/*02b0*/ IMAD.WIDE R4, R3, R4, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fcc00078e0204 */
/*02c0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R3, R3, 0x40, RZ ; /* 0x0000004003037810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0300*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x004fd80000000000 */
/*0310*/ @P0 BRA 0x2a0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0320*/ ISETP.GT.AND P0, PT, R2.reuse, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x042fe20003f04270 */
/*0330*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e80000004800 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0350*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f25270 */
/*0360*/ @P0 BRA 0x560 ; /* 0x000001f000000947 */
/* 0x000fec0003800000 */
/*0370*/ LDS R3, [R2.X4] ; /* 0x0000000002037984 */
/* 0x001fe20000004800 */
/*0380*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0390*/ LDS R4, [R2.X4+0x80] ; /* 0x0000800002047984 */
/* 0x000e240000004800 */
/*03a0*/ FADD R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x001fca0000000000 */
/*03b0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ LDS R4, [R2.X4+0x40] ; /* 0x0000400002047984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS R5, [R2.X4] ; /* 0x0000000002057984 */
/* 0x000e240000004800 */
/*03f0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*0400*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000004800 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0420*/ LDS R4, [R2.X4+0x20] ; /* 0x0000200002047984 */
/* 0x000fe80000004800 */
/*0430*/ LDS R7, [R2.X4] ; /* 0x0000000002077984 */
/* 0x000e240000004800 */
/*0440*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x001fca0000000000 */
/*0450*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000004800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ LDS R3, [R2.X4+0x10] ; /* 0x0000100002037984 */
/* 0x000fe80000004800 */
/*0480*/ LDS R4, [R2.X4] ; /* 0x0000000002047984 */
/* 0x000e240000004800 */
/*0490*/ FADD R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x001fca0000000000 */
/*04a0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04c0*/ LDS R4, [R2.X4+0x8] ; /* 0x0000080002047984 */
/* 0x000fe80000004800 */
/*04d0*/ LDS R5, [R2.X4] ; /* 0x0000000002057984 */
/* 0x000e240000004800 */
/*04e0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*04f0*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000004800 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ LDS R4, [R2.X4+0x4] ; /* 0x0000040002047984 */
/* 0x000fe80000004800 */
/*0520*/ LDS R7, [R2.X4] ; /* 0x0000000002077984 */
/* 0x000e240000004800 */
/*0530*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x001fca0000000000 */
/*0540*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e80000004800 */
/*0550*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0560*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*0570*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0580*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0590*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*05a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*05b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05c0*/ BRA 0x5c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reduce_normal_eqs_64_GPU(float *d_C_reduced, float *d_C, int gridDim_x_normal_equations) {
int tid = threadIdx.x;
int bx = blockIdx.x;
// put data in shared memory
int ind = blockIdx.y * gridDim.x * gridDim_x_normal_equations * 64 +
bx * gridDim_x_normal_equations * 64 + tid;
__shared__ float DATA[64];
// load and sum the first 20 elements
float tmp = 0.0f;
for (int i = 0; i < gridDim_x_normal_equations; i++)
tmp += d_C[ind + i * 64];
DATA[tid] = tmp;
__syncthreads(); // ensure reading stage has finished
// reduction
if (tid < 32) { // warp-reduce
DATA[tid] += DATA[tid + 32];
__syncthreads();
DATA[tid] += DATA[tid + 16];
__syncthreads();
DATA[tid] += DATA[tid + 8];
__syncthreads();
DATA[tid] += DATA[tid + 4];
__syncthreads();
DATA[tid] += DATA[tid + 2];
__syncthreads();
DATA[tid] += DATA[tid + 1];
__syncthreads();
}
// write results
if (tid == 0)
d_C_reduced[blockIdx.y * gridDim.x + bx] = DATA[0];
} | .file "tmpxft_00098e69_00000000-6_reduce_normal_eqs_64_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i
.type _Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i, @function
_Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24reduce_normal_eqs_64_GPUPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i, .-_Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i
.globl _Z24reduce_normal_eqs_64_GPUPfS_i
.type _Z24reduce_normal_eqs_64_GPUPfS_i, @function
_Z24reduce_normal_eqs_64_GPUPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24reduce_normal_eqs_64_GPUPfS_i, .-_Z24reduce_normal_eqs_64_GPUPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24reduce_normal_eqs_64_GPUPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24reduce_normal_eqs_64_GPUPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reduce_normal_eqs_64_GPU(float *d_C_reduced, float *d_C, int gridDim_x_normal_equations) {
int tid = threadIdx.x;
int bx = blockIdx.x;
// put data in shared memory
int ind = blockIdx.y * gridDim.x * gridDim_x_normal_equations * 64 +
bx * gridDim_x_normal_equations * 64 + tid;
__shared__ float DATA[64];
// load and sum the first 20 elements
float tmp = 0.0f;
for (int i = 0; i < gridDim_x_normal_equations; i++)
tmp += d_C[ind + i * 64];
DATA[tid] = tmp;
__syncthreads(); // ensure reading stage has finished
// reduction
if (tid < 32) { // warp-reduce
DATA[tid] += DATA[tid + 32];
__syncthreads();
DATA[tid] += DATA[tid + 16];
__syncthreads();
DATA[tid] += DATA[tid + 8];
__syncthreads();
DATA[tid] += DATA[tid + 4];
__syncthreads();
DATA[tid] += DATA[tid + 2];
__syncthreads();
DATA[tid] += DATA[tid + 1];
__syncthreads();
}
// write results
if (tid == 0)
d_C_reduced[blockIdx.y * gridDim.x + bx] = DATA[0];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce_normal_eqs_64_GPU(float *d_C_reduced, float *d_C, int gridDim_x_normal_equations) {
int tid = threadIdx.x;
int bx = blockIdx.x;
// put data in shared memory
int ind = blockIdx.y * gridDim.x * gridDim_x_normal_equations * 64 +
bx * gridDim_x_normal_equations * 64 + tid;
__shared__ float DATA[64];
// load and sum the first 20 elements
float tmp = 0.0f;
for (int i = 0; i < gridDim_x_normal_equations; i++)
tmp += d_C[ind + i * 64];
DATA[tid] = tmp;
__syncthreads(); // ensure reading stage has finished
// reduction
if (tid < 32) { // warp-reduce
DATA[tid] += DATA[tid + 32];
__syncthreads();
DATA[tid] += DATA[tid + 16];
__syncthreads();
DATA[tid] += DATA[tid + 8];
__syncthreads();
DATA[tid] += DATA[tid + 4];
__syncthreads();
DATA[tid] += DATA[tid + 2];
__syncthreads();
DATA[tid] += DATA[tid + 1];
__syncthreads();
}
// write results
if (tid == 0)
d_C_reduced[blockIdx.y * gridDim.x + bx] = DATA[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce_normal_eqs_64_GPU(float *d_C_reduced, float *d_C, int gridDim_x_normal_equations) {
int tid = threadIdx.x;
int bx = blockIdx.x;
// put data in shared memory
int ind = blockIdx.y * gridDim.x * gridDim_x_normal_equations * 64 +
bx * gridDim_x_normal_equations * 64 + tid;
__shared__ float DATA[64];
// load and sum the first 20 elements
float tmp = 0.0f;
for (int i = 0; i < gridDim_x_normal_equations; i++)
tmp += d_C[ind + i * 64];
DATA[tid] = tmp;
__syncthreads(); // ensure reading stage has finished
// reduction
if (tid < 32) { // warp-reduce
DATA[tid] += DATA[tid + 32];
__syncthreads();
DATA[tid] += DATA[tid + 16];
__syncthreads();
DATA[tid] += DATA[tid + 8];
__syncthreads();
DATA[tid] += DATA[tid + 4];
__syncthreads();
DATA[tid] += DATA[tid + 2];
__syncthreads();
DATA[tid] += DATA[tid + 1];
__syncthreads();
}
// write results
if (tid == 0)
d_C_reduced[blockIdx.y * gridDim.x + bx] = DATA[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24reduce_normal_eqs_64_GPUPfS_i
.globl _Z24reduce_normal_eqs_64_GPUPfS_i
.p2align 8
.type _Z24reduce_normal_eqs_64_GPUPfS_i,@function
_Z24reduce_normal_eqs_64_GPUPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_mul_i32 s6, s3, s2
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v1, s6, 6, v0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, 64, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v2
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v3, 0
.LBB0_4:
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s3, exec_lo
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_6
ds_load_2addr_b32 v[2:3], v1 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24reduce_normal_eqs_64_GPUPfS_i
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24reduce_normal_eqs_64_GPUPfS_i, .Lfunc_end0-_Z24reduce_normal_eqs_64_GPUPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24reduce_normal_eqs_64_GPUPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24reduce_normal_eqs_64_GPUPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce_normal_eqs_64_GPU(float *d_C_reduced, float *d_C, int gridDim_x_normal_equations) {
int tid = threadIdx.x;
int bx = blockIdx.x;
// put data in shared memory
int ind = blockIdx.y * gridDim.x * gridDim_x_normal_equations * 64 +
bx * gridDim_x_normal_equations * 64 + tid;
__shared__ float DATA[64];
// load and sum the first 20 elements
float tmp = 0.0f;
for (int i = 0; i < gridDim_x_normal_equations; i++)
tmp += d_C[ind + i * 64];
DATA[tid] = tmp;
__syncthreads(); // ensure reading stage has finished
// reduction
if (tid < 32) { // warp-reduce
DATA[tid] += DATA[tid + 32];
__syncthreads();
DATA[tid] += DATA[tid + 16];
__syncthreads();
DATA[tid] += DATA[tid + 8];
__syncthreads();
DATA[tid] += DATA[tid + 4];
__syncthreads();
DATA[tid] += DATA[tid + 2];
__syncthreads();
DATA[tid] += DATA[tid + 1];
__syncthreads();
}
// write results
if (tid == 0)
d_C_reduced[blockIdx.y * gridDim.x + bx] = DATA[0];
} | .text
.file "reduce_normal_eqs_64_GPU.hip"
.globl _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i # -- Begin function _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.p2align 4, 0x90
.type _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i,@function
_Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i: # @_Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24reduce_normal_eqs_64_GPUPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i, .Lfunc_end0-_Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24reduce_normal_eqs_64_GPUPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24reduce_normal_eqs_64_GPUPfS_i,@object # @_Z24reduce_normal_eqs_64_GPUPfS_i
.section .rodata,"a",@progbits
.globl _Z24reduce_normal_eqs_64_GPUPfS_i
.p2align 3, 0x0
_Z24reduce_normal_eqs_64_GPUPfS_i:
.quad _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.size _Z24reduce_normal_eqs_64_GPUPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24reduce_normal_eqs_64_GPUPfS_i"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24reduce_normal_eqs_64_GPUPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24reduce_normal_eqs_64_GPUPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fd400078e0203 */
/*0090*/ @!P0 BRA 0x320 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R3, R6.reuse, -0x1, RZ ; /* 0xffffffff06037810 */
/* 0x040fe20007ffe0ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe200078ec0ff */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*00f0*/ IMAD R3, R0, c[0x0][0x170], RZ ; /* 0x00005c0000037a24 */
/* 0x000fe200078e02ff */
/*0100*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fd60003f05270 */
/*0110*/ @!P1 BRA 0x270 ; /* 0x0000015000009947 */
/* 0x000fea0003800000 */
/*0120*/ LEA R4, R3, R2, 0x6 ; /* 0x0000000203047211 */
/* 0x002fe200078e30ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R11, R6, -c[0x0][0x170], RZ ; /* 0x80005c00060b7a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0160*/ IADD3 R8, R4, 0xc0, RZ ; /* 0x000000c004087810 */
/* 0x000fc60007ffe0ff */
/*0170*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0180*/ IADD3 R4, R8, -0xc0, RZ ; /* 0xffffff4008047810 */
/* 0x000fd20007ffe0ff */
/*0190*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*01a0*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R9, [R4.64+0x100] ; /* 0x0001000604097981 */
/* 0x000ee8000c1e1900 */
/*01c0*/ LDG.E R12, [R4.64+0x200] ; /* 0x00020006040c7981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R14, [R4.64+0x300] ; /* 0x00030006040e7981 */
/* 0x000f62000c1e1900 */
/*01e0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*01f0*/ IADD3 R8, R8, 0x100, RZ ; /* 0x0000010008087810 */
/* 0x000fe20007ffe0ff */
/*0200*/ FADD R10, R10, R7 ; /* 0x000000070a0a7221 */
/* 0x004fc80000000000 */
/*0210*/ IADD3 R7, R11, UR4, RZ ; /* 0x000000040b077c10 */
/* 0x000fe2000fffe0ff */
/*0220*/ FADD R9, R10, R9 ; /* 0x000000090a097221 */
/* 0x008fc60000000000 */
/*0230*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*0240*/ FADD R9, R9, R12 ; /* 0x0000000c09097221 */
/* 0x010fc80000000000 */
/*0250*/ FADD R7, R9, R14 ; /* 0x0000000e09077221 */
/* 0x020fd00000000000 */
/*0260*/ @P1 BRA 0x170 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*0270*/ @!P0 BRA 0x320 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R3, R3, UR4, RZ ; /* 0x0000000403037c10 */
/* 0x000fca000fffe0ff */
/*0290*/ IMAD R3, R3, 0x40, R2 ; /* 0x0000004003037824 */
/* 0x002fe400078e0202 */
/*02a0*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fca0000000f00 */
/*02b0*/ IMAD.WIDE R4, R3, R4, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fcc00078e0204 */
/*02c0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R3, R3, 0x40, RZ ; /* 0x0000004003037810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0300*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x004fd80000000000 */
/*0310*/ @P0 BRA 0x2a0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0320*/ ISETP.GT.AND P0, PT, R2.reuse, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x042fe20003f04270 */
/*0330*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e80000004800 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0350*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f25270 */
/*0360*/ @P0 BRA 0x560 ; /* 0x000001f000000947 */
/* 0x000fec0003800000 */
/*0370*/ LDS R3, [R2.X4] ; /* 0x0000000002037984 */
/* 0x001fe20000004800 */
/*0380*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0390*/ LDS R4, [R2.X4+0x80] ; /* 0x0000800002047984 */
/* 0x000e240000004800 */
/*03a0*/ FADD R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x001fca0000000000 */
/*03b0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ LDS R4, [R2.X4+0x40] ; /* 0x0000400002047984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS R5, [R2.X4] ; /* 0x0000000002057984 */
/* 0x000e240000004800 */
/*03f0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*0400*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000004800 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0420*/ LDS R4, [R2.X4+0x20] ; /* 0x0000200002047984 */
/* 0x000fe80000004800 */
/*0430*/ LDS R7, [R2.X4] ; /* 0x0000000002077984 */
/* 0x000e240000004800 */
/*0440*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x001fca0000000000 */
/*0450*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000004800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ LDS R3, [R2.X4+0x10] ; /* 0x0000100002037984 */
/* 0x000fe80000004800 */
/*0480*/ LDS R4, [R2.X4] ; /* 0x0000000002047984 */
/* 0x000e240000004800 */
/*0490*/ FADD R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x001fca0000000000 */
/*04a0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04c0*/ LDS R4, [R2.X4+0x8] ; /* 0x0000080002047984 */
/* 0x000fe80000004800 */
/*04d0*/ LDS R5, [R2.X4] ; /* 0x0000000002057984 */
/* 0x000e240000004800 */
/*04e0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*04f0*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000004800 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ LDS R4, [R2.X4+0x4] ; /* 0x0000040002047984 */
/* 0x000fe80000004800 */
/*0520*/ LDS R7, [R2.X4] ; /* 0x0000000002077984 */
/* 0x000e240000004800 */
/*0530*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x001fca0000000000 */
/*0540*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e80000004800 */
/*0550*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0560*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*0570*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0580*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0590*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*05a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*05b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05c0*/ BRA 0x5c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24reduce_normal_eqs_64_GPUPfS_i
.globl _Z24reduce_normal_eqs_64_GPUPfS_i
.p2align 8
.type _Z24reduce_normal_eqs_64_GPUPfS_i,@function
_Z24reduce_normal_eqs_64_GPUPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_mul_i32 s6, s3, s2
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v1, s6, 6, v0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, 64, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v2
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v3, 0
.LBB0_4:
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s3, exec_lo
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_6
ds_load_2addr_b32 v[2:3], v1 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24reduce_normal_eqs_64_GPUPfS_i
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24reduce_normal_eqs_64_GPUPfS_i, .Lfunc_end0-_Z24reduce_normal_eqs_64_GPUPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24reduce_normal_eqs_64_GPUPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24reduce_normal_eqs_64_GPUPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00098e69_00000000-6_reduce_normal_eqs_64_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i
.type _Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i, @function
_Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24reduce_normal_eqs_64_GPUPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i, .-_Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i
.globl _Z24reduce_normal_eqs_64_GPUPfS_i
.type _Z24reduce_normal_eqs_64_GPUPfS_i, @function
_Z24reduce_normal_eqs_64_GPUPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24reduce_normal_eqs_64_GPUPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24reduce_normal_eqs_64_GPUPfS_i, .-_Z24reduce_normal_eqs_64_GPUPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24reduce_normal_eqs_64_GPUPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24reduce_normal_eqs_64_GPUPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce_normal_eqs_64_GPU.hip"
.globl _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i # -- Begin function _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.p2align 4, 0x90
.type _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i,@function
_Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i: # @_Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24reduce_normal_eqs_64_GPUPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i, .Lfunc_end0-_Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24reduce_normal_eqs_64_GPUPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24reduce_normal_eqs_64_GPUPfS_i,@object # @_Z24reduce_normal_eqs_64_GPUPfS_i
.section .rodata,"a",@progbits
.globl _Z24reduce_normal_eqs_64_GPUPfS_i
.p2align 3, 0x0
_Z24reduce_normal_eqs_64_GPUPfS_i:
.quad _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.size _Z24reduce_normal_eqs_64_GPUPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24reduce_normal_eqs_64_GPUPfS_i"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__reduce_normal_eqs_64_GPUPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24reduce_normal_eqs_64_GPUPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Mask_Sum_Kernel( int* A, int valCount, int* scalarOut)
{
const int localIdx = threadIdx.x;
const int globalIdx = blockDim.x*blockIdx.x + threadIdx.x;
const int blockIdxOut = blockIdx.x / blockDim.x;
while(valCount > 1)
{
int localCount = blockDim.x;
while(localCount > 1)
{
localCount = localCount / 2;
if(localIdx < localCount)
A[globalIdx] += A[globalIdx + localCount];
}
if(localIdx == 0)
A[blockIdxOut] = A[globalIdx];
valCount = valCount / blockDim.x;
}
if(globalIdx==0)
scalarOut[0] = A[0];
} | code for sm_80
Function : _Z15Mask_Sum_KernelPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0050*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD R0, R5, c[0x0][0x0], R6 ; /* 0x0000000005007a24 */
/* 0x001fd800078e0206 */
/*0070*/ @!P0 BRA 0x570 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0080*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e300000209000 */
/*0090*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R8, R3, R7, R2 ; /* 0x0000000703087227 */
/* 0x000fc800078e0002 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.HI.U32 R3, R8, R5, RZ ; /* 0x0000000508037227 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.MOV R10, RZ, RZ, -R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0a03 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff077624 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD R5, R10, c[0x0][0x0], R5 ; /* 0x000000000a057a24 */
/* 0x000fe200078e0205 */
/*0150*/ LOP3.LUT R10, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff0a7a12 */
/* 0x000fc800078e33ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f06070 */
/*0170*/ @P0 IADD3 R5, R5, -c[0x0][0x0], RZ ; /* 0x8000000005050a10 */
/* 0x000fe40007ffe0ff */
/*0180*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fe20003f26070 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fd60003f05070 */
/*01c0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GT.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f24270 */
/*01e0*/ SEL R4, R10, R3, !P0 ; /* 0x000000030a047207 */
/* 0x000fe20004000000 */
/*01f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*0200*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0210*/ @P1 BRA 0x310 ; /* 0x000000f000001947 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f25270 */
/*0230*/ @!P1 LDG.E R9, [R2.64] ; /* 0x0000000402099981 */
/* 0x001ea2000c1e1900 */
/*0240*/ IMAD.HI.U32 R11, R8, R7, RZ ; /* 0x00000007080b7227 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.MOV R6, RZ, RZ, -R11 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a0b */
/*0260*/ IMAD R7, R6, c[0x0][0x0], R7 ; /* 0x0000000006077a24 */
/* 0x000fca00078e0207 */
/*0270*/ ISETP.GE.U32.AND P2, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f46070 */
/*0280*/ @P2 IADD3 R7, R7, -c[0x0][0x0], RZ ; /* 0x8000000007072a10 */
/* 0x000fe40007ffe0ff */
/*0290*/ @P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b2810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P3, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f66070 */
/*02b0*/ @P3 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b3810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ SEL R7, R10, R11, !P0 ; /* 0x0000000b0a077207 */
/* 0x000fc80004000000 */
/*02d0*/ ISETP.GT.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f44270 */
/*02e0*/ @!P1 STG.E [R4.64], R9 ; /* 0x0000000904009986 */
/* 0x0041d8000c101904 */
/*02f0*/ @P2 BRA 0x230 ; /* 0xffffff3000002947 */
/* 0x000fea000383ffff */
/*0300*/ BRA 0x570 ; /* 0x0000026000007947 */
/* 0x000fea0003800000 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x001fca00078e00ff */
/*0320*/ SHF.R.U32.HI R13, RZ, 0x1, R8 ; /* 0x00000001ff0d7819 */
/* 0x000fe20000011608 */
/*0330*/ BSSY B0, 0x3d0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0340*/ ISETP.GT.U32.AND P1, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe40003f24070 */
/*0350*/ ISETP.GE.AND P0, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fda0003f06270 */
/*0360*/ @P0 BRA 0x3c0 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*0370*/ IMAD.WIDE.U32 R8, R13, 0x4, R2 ; /* 0x000000040d087825 */
/* 0x000fe200078e0002 */
/*0380*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000eaa000c1e1900 */
/*0390*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ IADD3 R11, R10, R9, RZ ; /* 0x000000090a0b7210 */
/* 0x004fca0007ffe0ff */
/*03b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101904 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000d */
/*03e0*/ @P1 BRA 0x320 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*03f0*/ ISETP.NE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f45270 */
/*0400*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ea2000c1e1900 */
/*0410*/ I2F.U32.RP R12, c[0x0][0x0] ; /* 0x00000000000c7b06 */
/* 0x000e220000209000 */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0430*/ ISETP.NE.U32.AND P3, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fcc0003f65070 */
/*0440*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*0450*/ IADD3 R9, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c097810 */
/* 0x001fcc0007ffe0ff */
/*0460*/ F2I.FTZ.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e24000021f000 */
/*0470*/ IMAD.MOV R13, RZ, RZ, -R9 ; /* 0x000000ffff0d7224 */
/* 0x001fc800078e0a09 */
/*0480*/ IMAD R13, R13, c[0x0][0x0], RZ ; /* 0x000000000d0d7a24 */
/* 0x000fc800078e02ff */
/*0490*/ IMAD.HI.U32 R8, R9, R13, R8 ; /* 0x0000000d09087227 */
/* 0x000fcc00078e0008 */
/*04a0*/ IMAD.HI.U32 R8, R8, R7, RZ ; /* 0x0000000708087227 */
/* 0x000fc800078e00ff */
/*04b0*/ IMAD.MOV R10, RZ, RZ, -R8 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a08 */
/*04c0*/ IMAD R7, R10, c[0x0][0x0], R7 ; /* 0x000000000a077a24 */
/* 0x000fca00078e0207 */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f06070 */
/*04e0*/ @P0 IADD3 R7, R7, -c[0x0][0x0], RZ ; /* 0x8000000007070a10 */
/* 0x000fe40007ffe0ff */
/*04f0*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fe40007ffe0ff */
/*0500*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f26070 */
/*0510*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fe40007ffe0ff */
/*0520*/ @!P3 LOP3.LUT R8, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff08ba12 */
/* 0x000fc800078e33ff */
/*0530*/ ISETP.GT.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f04270 */
/*0540*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*0550*/ @!P2 STG.E [R4.64], R11 ; /* 0x0000000b0400a986 */
/* 0x0041f6000c101904 */
/*0560*/ @P0 BRA 0x310 ; /* 0xfffffda000000947 */
/* 0x000fea000383ffff */
/*0570*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0580*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*05a0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fca0000000f00 */
/*05b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x001fe400078e00ff */
/*05d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*05e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Mask_Sum_Kernel( int* A, int valCount, int* scalarOut)
{
const int localIdx = threadIdx.x;
const int globalIdx = blockDim.x*blockIdx.x + threadIdx.x;
const int blockIdxOut = blockIdx.x / blockDim.x;
while(valCount > 1)
{
int localCount = blockDim.x;
while(localCount > 1)
{
localCount = localCount / 2;
if(localIdx < localCount)
A[globalIdx] += A[globalIdx + localCount];
}
if(localIdx == 0)
A[blockIdxOut] = A[globalIdx];
valCount = valCount / blockDim.x;
}
if(globalIdx==0)
scalarOut[0] = A[0];
} | .file "tmpxft_00160f42_00000000-6_Mask_Sum_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_
.type _Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_, @function
_Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15Mask_Sum_KernelPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_, .-_Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_
.globl _Z15Mask_Sum_KernelPiiS_
.type _Z15Mask_Sum_KernelPiiS_, @function
_Z15Mask_Sum_KernelPiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15Mask_Sum_KernelPiiS_, .-_Z15Mask_Sum_KernelPiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15Mask_Sum_KernelPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15Mask_Sum_KernelPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Mask_Sum_Kernel( int* A, int valCount, int* scalarOut)
{
const int localIdx = threadIdx.x;
const int globalIdx = blockDim.x*blockIdx.x + threadIdx.x;
const int blockIdxOut = blockIdx.x / blockDim.x;
while(valCount > 1)
{
int localCount = blockDim.x;
while(localCount > 1)
{
localCount = localCount / 2;
if(localIdx < localCount)
A[globalIdx] += A[globalIdx + localCount];
}
if(localIdx == 0)
A[blockIdxOut] = A[globalIdx];
valCount = valCount / blockDim.x;
}
if(globalIdx==0)
scalarOut[0] = A[0];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Mask_Sum_Kernel( int* A, int valCount, int* scalarOut)
{
const int localIdx = threadIdx.x;
const int globalIdx = blockDim.x*blockIdx.x + threadIdx.x;
const int blockIdxOut = blockIdx.x / blockDim.x;
while(valCount > 1)
{
int localCount = blockDim.x;
while(localCount > 1)
{
localCount = localCount / 2;
if(localIdx < localCount)
A[globalIdx] += A[globalIdx + localCount];
}
if(localIdx == 0)
A[blockIdxOut] = A[globalIdx];
valCount = valCount / blockDim.x;
}
if(globalIdx==0)
scalarOut[0] = A[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Mask_Sum_Kernel( int* A, int valCount, int* scalarOut)
{
const int localIdx = threadIdx.x;
const int globalIdx = blockDim.x*blockIdx.x + threadIdx.x;
const int blockIdxOut = blockIdx.x / blockDim.x;
while(valCount > 1)
{
int localCount = blockDim.x;
while(localCount > 1)
{
localCount = localCount / 2;
if(localIdx < localCount)
A[globalIdx] += A[globalIdx + localCount];
}
if(localIdx == 0)
A[blockIdxOut] = A[globalIdx];
valCount = valCount / blockDim.x;
}
if(globalIdx==0)
scalarOut[0] = A[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Mask_Sum_KernelPiiS_
.globl _Z15Mask_Sum_KernelPiiS_
.p2align 8
.type _Z15Mask_Sum_KernelPiiS_,@function
_Z15Mask_Sum_KernelPiiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_cmp_lt_i32 s8, 2
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_cbranch_scc1 .LBB0_9
v_cvt_f32_u32_e32 v2, s3
s_sub_i32 s9, 0, s3
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v4, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s2, v4
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s6, s9, s2
v_add_co_u32 v2, vcc_lo, s4, v2
s_mul_hi_u32 s6, s2, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_add_i32 s2, s2, s6
s_mul_hi_u32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s2, s3
s_add_i32 s7, s2, 1
s_sub_i32 s6, s15, s6
s_sub_i32 s10, s6, s3
s_cmp_ge_u32 s6, s3
s_cselect_b32 s7, s7, s2
s_cselect_b32 s2, s10, s6
s_add_i32 s6, s7, 1
s_cmp_ge_u32 s2, s3
v_cmp_eq_u32_e64 s2, 0, v0
s_cselect_b32 s6, s6, s7
s_cmp_gt_u32 s3, 1
s_cselect_b32 s10, -1, 0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s6, s4, s6
s_addc_u32 s7, s5, s7
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
v_readfirstlane_b32 s11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s9, s11
s_mul_hi_u32 s12, s11, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s11, s12
s_mul_hi_u32 s11, s8, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s11, s3
s_sub_i32 s8, s8, s12
s_add_i32 s12, s11, 1
s_sub_i32 s13, s8, s3
s_cmp_ge_u32 s8, s3
s_cselect_b32 s11, s12, s11
s_cselect_b32 s8, s13, s8
s_add_i32 s12, s11, 1
s_cmp_ge_u32 s8, s3
s_cselect_b32 s8, s12, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_i32 s8, 1
s_cbranch_scc0 .LBB0_9
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s10
s_mov_b32 s11, s3
s_cbranch_vccz .LBB0_7
.LBB0_4:
s_and_saveexec_b32 s11, s2
s_cbranch_execz .LBB0_2
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v5, v6, s[6:7]
s_branch .LBB0_2
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s13
s_cmp_gt_u32 s11, 3
s_mov_b32 s11, s12
s_cbranch_scc0 .LBB0_4
.LBB0_7:
s_lshr_b32 s12, s11, 1
s_mov_b32 s13, exec_lo
v_cmpx_gt_u32_e64 s12, v0
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v6, s12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_clause 0x1
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v7, v6
global_store_b32 v[2:3], v6, off
s_branch .LBB0_6
.LBB0_9:
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Mask_Sum_KernelPiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15Mask_Sum_KernelPiiS_, .Lfunc_end0-_Z15Mask_Sum_KernelPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Mask_Sum_KernelPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15Mask_Sum_KernelPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Mask_Sum_Kernel( int* A, int valCount, int* scalarOut)
{
const int localIdx = threadIdx.x;
const int globalIdx = blockDim.x*blockIdx.x + threadIdx.x;
const int blockIdxOut = blockIdx.x / blockDim.x;
while(valCount > 1)
{
int localCount = blockDim.x;
while(localCount > 1)
{
localCount = localCount / 2;
if(localIdx < localCount)
A[globalIdx] += A[globalIdx + localCount];
}
if(localIdx == 0)
A[blockIdxOut] = A[globalIdx];
valCount = valCount / blockDim.x;
}
if(globalIdx==0)
scalarOut[0] = A[0];
} | .text
.file "Mask_Sum_Kernel.hip"
.globl _Z30__device_stub__Mask_Sum_KernelPiiS_ # -- Begin function _Z30__device_stub__Mask_Sum_KernelPiiS_
.p2align 4, 0x90
.type _Z30__device_stub__Mask_Sum_KernelPiiS_,@function
_Z30__device_stub__Mask_Sum_KernelPiiS_: # @_Z30__device_stub__Mask_Sum_KernelPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15Mask_Sum_KernelPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__Mask_Sum_KernelPiiS_, .Lfunc_end0-_Z30__device_stub__Mask_Sum_KernelPiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15Mask_Sum_KernelPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15Mask_Sum_KernelPiiS_,@object # @_Z15Mask_Sum_KernelPiiS_
.section .rodata,"a",@progbits
.globl _Z15Mask_Sum_KernelPiiS_
.p2align 3, 0x0
_Z15Mask_Sum_KernelPiiS_:
.quad _Z30__device_stub__Mask_Sum_KernelPiiS_
.size _Z15Mask_Sum_KernelPiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15Mask_Sum_KernelPiiS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__Mask_Sum_KernelPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15Mask_Sum_KernelPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15Mask_Sum_KernelPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0050*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD R0, R5, c[0x0][0x0], R6 ; /* 0x0000000005007a24 */
/* 0x001fd800078e0206 */
/*0070*/ @!P0 BRA 0x570 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0080*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e300000209000 */
/*0090*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R8, R3, R7, R2 ; /* 0x0000000703087227 */
/* 0x000fc800078e0002 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.HI.U32 R3, R8, R5, RZ ; /* 0x0000000508037227 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.MOV R10, RZ, RZ, -R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0a03 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff077624 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD R5, R10, c[0x0][0x0], R5 ; /* 0x000000000a057a24 */
/* 0x000fe200078e0205 */
/*0150*/ LOP3.LUT R10, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff0a7a12 */
/* 0x000fc800078e33ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f06070 */
/*0170*/ @P0 IADD3 R5, R5, -c[0x0][0x0], RZ ; /* 0x8000000005050a10 */
/* 0x000fe40007ffe0ff */
/*0180*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fe20003f26070 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fd60003f05070 */
/*01c0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GT.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f24270 */
/*01e0*/ SEL R4, R10, R3, !P0 ; /* 0x000000030a047207 */
/* 0x000fe20004000000 */
/*01f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*0200*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0210*/ @P1 BRA 0x310 ; /* 0x000000f000001947 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f25270 */
/*0230*/ @!P1 LDG.E R9, [R2.64] ; /* 0x0000000402099981 */
/* 0x001ea2000c1e1900 */
/*0240*/ IMAD.HI.U32 R11, R8, R7, RZ ; /* 0x00000007080b7227 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.MOV R6, RZ, RZ, -R11 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a0b */
/*0260*/ IMAD R7, R6, c[0x0][0x0], R7 ; /* 0x0000000006077a24 */
/* 0x000fca00078e0207 */
/*0270*/ ISETP.GE.U32.AND P2, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f46070 */
/*0280*/ @P2 IADD3 R7, R7, -c[0x0][0x0], RZ ; /* 0x8000000007072a10 */
/* 0x000fe40007ffe0ff */
/*0290*/ @P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b2810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P3, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f66070 */
/*02b0*/ @P3 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b3810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ SEL R7, R10, R11, !P0 ; /* 0x0000000b0a077207 */
/* 0x000fc80004000000 */
/*02d0*/ ISETP.GT.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f44270 */
/*02e0*/ @!P1 STG.E [R4.64], R9 ; /* 0x0000000904009986 */
/* 0x0041d8000c101904 */
/*02f0*/ @P2 BRA 0x230 ; /* 0xffffff3000002947 */
/* 0x000fea000383ffff */
/*0300*/ BRA 0x570 ; /* 0x0000026000007947 */
/* 0x000fea0003800000 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x001fca00078e00ff */
/*0320*/ SHF.R.U32.HI R13, RZ, 0x1, R8 ; /* 0x00000001ff0d7819 */
/* 0x000fe20000011608 */
/*0330*/ BSSY B0, 0x3d0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0340*/ ISETP.GT.U32.AND P1, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe40003f24070 */
/*0350*/ ISETP.GE.AND P0, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fda0003f06270 */
/*0360*/ @P0 BRA 0x3c0 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*0370*/ IMAD.WIDE.U32 R8, R13, 0x4, R2 ; /* 0x000000040d087825 */
/* 0x000fe200078e0002 */
/*0380*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000eaa000c1e1900 */
/*0390*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ IADD3 R11, R10, R9, RZ ; /* 0x000000090a0b7210 */
/* 0x004fca0007ffe0ff */
/*03b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101904 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000d */
/*03e0*/ @P1 BRA 0x320 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*03f0*/ ISETP.NE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f45270 */
/*0400*/ @!P2 LDG.E R11, [R2.64] ; /* 0x00000004020ba981 */
/* 0x001ea2000c1e1900 */
/*0410*/ I2F.U32.RP R12, c[0x0][0x0] ; /* 0x00000000000c7b06 */
/* 0x000e220000209000 */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0430*/ ISETP.NE.U32.AND P3, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fcc0003f65070 */
/*0440*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*0450*/ IADD3 R9, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c097810 */
/* 0x001fcc0007ffe0ff */
/*0460*/ F2I.FTZ.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e24000021f000 */
/*0470*/ IMAD.MOV R13, RZ, RZ, -R9 ; /* 0x000000ffff0d7224 */
/* 0x001fc800078e0a09 */
/*0480*/ IMAD R13, R13, c[0x0][0x0], RZ ; /* 0x000000000d0d7a24 */
/* 0x000fc800078e02ff */
/*0490*/ IMAD.HI.U32 R8, R9, R13, R8 ; /* 0x0000000d09087227 */
/* 0x000fcc00078e0008 */
/*04a0*/ IMAD.HI.U32 R8, R8, R7, RZ ; /* 0x0000000708087227 */
/* 0x000fc800078e00ff */
/*04b0*/ IMAD.MOV R10, RZ, RZ, -R8 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a08 */
/*04c0*/ IMAD R7, R10, c[0x0][0x0], R7 ; /* 0x000000000a077a24 */
/* 0x000fca00078e0207 */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f06070 */
/*04e0*/ @P0 IADD3 R7, R7, -c[0x0][0x0], RZ ; /* 0x8000000007070a10 */
/* 0x000fe40007ffe0ff */
/*04f0*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fe40007ffe0ff */
/*0500*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f26070 */
/*0510*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fe40007ffe0ff */
/*0520*/ @!P3 LOP3.LUT R8, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff08ba12 */
/* 0x000fc800078e33ff */
/*0530*/ ISETP.GT.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f04270 */
/*0540*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*0550*/ @!P2 STG.E [R4.64], R11 ; /* 0x0000000b0400a986 */
/* 0x0041f6000c101904 */
/*0560*/ @P0 BRA 0x310 ; /* 0xfffffda000000947 */
/* 0x000fea000383ffff */
/*0570*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0580*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*05a0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fca0000000f00 */
/*05b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x001fe400078e00ff */
/*05d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*05e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Mask_Sum_KernelPiiS_
.globl _Z15Mask_Sum_KernelPiiS_
.p2align 8
.type _Z15Mask_Sum_KernelPiiS_,@function
_Z15Mask_Sum_KernelPiiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_cmp_lt_i32 s8, 2
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_cbranch_scc1 .LBB0_9
v_cvt_f32_u32_e32 v2, s3
s_sub_i32 s9, 0, s3
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v4, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s2, v4
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s6, s9, s2
v_add_co_u32 v2, vcc_lo, s4, v2
s_mul_hi_u32 s6, s2, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_add_i32 s2, s2, s6
s_mul_hi_u32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s2, s3
s_add_i32 s7, s2, 1
s_sub_i32 s6, s15, s6
s_sub_i32 s10, s6, s3
s_cmp_ge_u32 s6, s3
s_cselect_b32 s7, s7, s2
s_cselect_b32 s2, s10, s6
s_add_i32 s6, s7, 1
s_cmp_ge_u32 s2, s3
v_cmp_eq_u32_e64 s2, 0, v0
s_cselect_b32 s6, s6, s7
s_cmp_gt_u32 s3, 1
s_cselect_b32 s10, -1, 0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s6, s4, s6
s_addc_u32 s7, s5, s7
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
v_readfirstlane_b32 s11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s9, s11
s_mul_hi_u32 s12, s11, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s11, s12
s_mul_hi_u32 s11, s8, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s11, s3
s_sub_i32 s8, s8, s12
s_add_i32 s12, s11, 1
s_sub_i32 s13, s8, s3
s_cmp_ge_u32 s8, s3
s_cselect_b32 s11, s12, s11
s_cselect_b32 s8, s13, s8
s_add_i32 s12, s11, 1
s_cmp_ge_u32 s8, s3
s_cselect_b32 s8, s12, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_i32 s8, 1
s_cbranch_scc0 .LBB0_9
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s10
s_mov_b32 s11, s3
s_cbranch_vccz .LBB0_7
.LBB0_4:
s_and_saveexec_b32 s11, s2
s_cbranch_execz .LBB0_2
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v5, v6, s[6:7]
s_branch .LBB0_2
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s13
s_cmp_gt_u32 s11, 3
s_mov_b32 s11, s12
s_cbranch_scc0 .LBB0_4
.LBB0_7:
s_lshr_b32 s12, s11, 1
s_mov_b32 s13, exec_lo
v_cmpx_gt_u32_e64 s12, v0
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v6, s12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_clause 0x1
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v7, v6
global_store_b32 v[2:3], v6, off
s_branch .LBB0_6
.LBB0_9:
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Mask_Sum_KernelPiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15Mask_Sum_KernelPiiS_, .Lfunc_end0-_Z15Mask_Sum_KernelPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Mask_Sum_KernelPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15Mask_Sum_KernelPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00160f42_00000000-6_Mask_Sum_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_
.type _Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_, @function
_Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15Mask_Sum_KernelPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_, .-_Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_
.globl _Z15Mask_Sum_KernelPiiS_
.type _Z15Mask_Sum_KernelPiiS_, @function
_Z15Mask_Sum_KernelPiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15Mask_Sum_KernelPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15Mask_Sum_KernelPiiS_, .-_Z15Mask_Sum_KernelPiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15Mask_Sum_KernelPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15Mask_Sum_KernelPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Mask_Sum_Kernel.hip"
.globl _Z30__device_stub__Mask_Sum_KernelPiiS_ # -- Begin function _Z30__device_stub__Mask_Sum_KernelPiiS_
.p2align 4, 0x90
.type _Z30__device_stub__Mask_Sum_KernelPiiS_,@function
_Z30__device_stub__Mask_Sum_KernelPiiS_: # @_Z30__device_stub__Mask_Sum_KernelPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15Mask_Sum_KernelPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__Mask_Sum_KernelPiiS_, .Lfunc_end0-_Z30__device_stub__Mask_Sum_KernelPiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15Mask_Sum_KernelPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15Mask_Sum_KernelPiiS_,@object # @_Z15Mask_Sum_KernelPiiS_
.section .rodata,"a",@progbits
.globl _Z15Mask_Sum_KernelPiiS_
.p2align 3, 0x0
_Z15Mask_Sum_KernelPiiS_:
.quad _Z30__device_stub__Mask_Sum_KernelPiiS_
.size _Z15Mask_Sum_KernelPiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15Mask_Sum_KernelPiiS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__Mask_Sum_KernelPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15Mask_Sum_KernelPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define LIMIT -999
#define BLOCK_SIZE 16
#define MAX_SEQ_LEN 2100
#define MAX_SEQ_NUM 1024
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <sys/time.h>
inline void cudaCheckError(int line, cudaError_t ce)
{
if (ce != cudaSuccess) {
printf("Error: line %d %s\n", line, cudaGetErrorString(ce));
exit(1);
}
}
// HACK Huan's hack
// this is not the updated validation code
int validation(int *score_matrix_cpu, int *score_matrix, unsigned int length)
{
unsigned int i = 0;
while (i!=length) {
if ( (score_matrix_cpu[i]) == (score_matrix[i] >> 2) ) {
++i;
continue;
}
else {
printf("i = %d, expected %d, got %d.\n",i, score_matrix_cpu[i], score_matrix[i] >> 2);
return 0;
}
}
return 1;
}
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
double gettime() {
struct timeval t;
gettimeofday(&t,NULL);
return t.tv_sec+t.tv_usec*1e-6;
}
__global__ void dummy_function(int * array, unsigned int howlarge)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < 9; i++) {
for (int delta=0; delta<howlarge; delta=delta+blockDim.x*gridDim.x) {
if (tid+delta < howlarge)
array[tid+delta] = array[tid+delta] + tid;
}
}
}
void runTest()
{
double start, end, now;
unsigned int nints = 100 * 1024 * 1024;
unsigned int sz = nints * sizeof(int);
unsigned int nints_small = 1 * 1024 * 1024;
unsigned int sz_small = nints_small * sizeof(int);
#ifdef _LP64
printf ("Running on a 64-bit platform!\n", 0);
#else
#endif
printf("Big Chunk of memory allocated on host & device = %d\n", sz / 1024 /1024);
printf("Small Chunk of memory allocated on host & device = %d\n", sz_small / 1024 /1024);
int * dummy_cpu, * dummy_cpu2, * dummy_small_cpu, * dummy_small_cpu2;
cudaMallocHost( (void**) &dummy_cpu, sz );
cudaMallocHost( (void**) &dummy_cpu2, sz );
cudaMallocHost ( (void**) &dummy_small_cpu, sz_small);
cudaMallocHost ( (void**) &dummy_small_cpu2, sz_small);
int * dummy_gpu, * dummy_gpu2, * dummy_small_gpu, * dummy_small_gpu2;
cudaMalloc( (void**) &dummy_gpu, sz );
cudaMalloc( (void**) &dummy_gpu2, sz );
cudaMalloc( (void**) &dummy_small_gpu, sz_small );
cudaMalloc( (void**) &dummy_small_gpu2, sz_small );
double kernelt = 0, memcpyt = 0, st = 0, ast = 0;
#define TIMES 5
start = gettime();
dummy_function<<<100,512>>>(dummy_gpu, nints);
cudaDeviceSynchronize();
end = gettime();
printf("time for kernel call = %f\n", end-start);
start = gettime();
cudaMemcpy(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost );
cudaDeviceSynchronize();
end = gettime();
printf("time for memcopy D-H = %f\n", end-start);
start = gettime();
cudaMemcpy(dummy_small_gpu, dummy_small_cpu, sz_small, cudaMemcpyHostToDevice);
dummy_function<<<100,512>>>(dummy_gpu, nints);
cudaMemcpy(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost );
cudaDeviceSynchronize();
end = gettime();
printf("time for one iteration = %f\n", end-start);
cudaStream_t stream1;
cudaStreamCreate(&stream1);
cudaStream_t stream2;
cudaStreamCreate(&stream2);
#define DEBUG 1
for (int sync=0; sync<2; sync++){
start = gettime();
for (int i = 0; i< TIMES; i++) {
// small sync copy H->D
cudaMemcpyAsync(dummy_small_gpu, dummy_small_cpu, sz_small, cudaMemcpyHostToDevice, stream1);
//kernel function
dummy_function<<<100,512, 0, stream1>>>(dummy_gpu, nints);
cudaDeviceSynchronize();
//large copy D->H can be sync or async
#ifdef DEBUG
now = gettime();
#endif
if (sync){
cudaMemcpy(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost);
}else{
cudaMemcpyAsync(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost, stream1 );
}
#ifdef DEBUG
printf("(A)sync call took %f\n", gettime() - now);
#endif
// small sync copy H->D
cudaMemcpyAsync(dummy_small_gpu2, dummy_small_cpu2, sz_small, cudaMemcpyHostToDevice, stream2);
//kernel function
dummy_function<<<100,512, 0, stream2>>>(dummy_gpu2, nints);
cudaDeviceSynchronize();
//large copy D->H can be sync or async
if (sync){
cudaMemcpy(dummy_cpu2, dummy_gpu2, sz, cudaMemcpyDeviceToHost);
}else{
cudaMemcpyAsync(dummy_cpu2, dummy_gpu2, sz, cudaMemcpyDeviceToHost , stream2);
}
}
cudaDeviceSynchronize();
end = gettime();
if (!sync)
printf("%d iterations: time for ASYNC calls = %f\n",TIMES,end-start);
else
printf("%d iterations: time for SYNC calls = %f\n",TIMES,end-start);
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
runTest();
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z14dummy_functionPij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003f05270 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fd000078e0203 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ IMAD.IADD R3, R0, 0x1, R5.reuse ; /* 0x0000000100037824 */
/* 0x101fe200078e0205 */
/*00a0*/ BSSY B0, 0x150 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe40003f06070 */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*00e0*/ @P0 BRA 0x140 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*0100*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0110*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0120*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ @!P1 BRA 0x90 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0160*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0180*/ IADD3 R2, R0, R5, RZ ; /* 0x0000000500027210 */
/* 0x001fe20007ffe0ff */
/*0190*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fe200078e0205 */
/*01a0*/ BSSY B0, 0x240 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*01d0*/ @P0 BRA 0x230 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0200*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0210*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*0220*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ @!P1 BRA 0x180 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0260*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc60000000f00 */
/*0270*/ IMAD.IADD R2, R0, 0x1, R5.reuse ; /* 0x0000000100027824 */
/* 0x101fe200078e0205 */
/*0280*/ BSSY B0, 0x330 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*02b0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*02c0*/ @P0 BRA 0x320 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*02d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*02e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*02f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0300*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*0310*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ @!P1 BRA 0x270 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0340*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0360*/ IADD3 R2, R0, R5, RZ ; /* 0x0000000500027210 */
/* 0x001fe20007ffe0ff */
/*0370*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fe200078e0205 */
/*0380*/ BSSY B0, 0x420 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0390*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*03a0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*03b0*/ @P0 BRA 0x410 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*03e0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*0400*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ @!P1 BRA 0x360 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0440*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc60000000f00 */
/*0450*/ IMAD.IADD R2, R0, 0x1, R5.reuse ; /* 0x0000000100027824 */
/* 0x101fe200078e0205 */
/*0460*/ BSSY B0, 0x510 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0470*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*0480*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0490*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*04a0*/ @P0 BRA 0x500 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*04b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*04c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*04d0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*04f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ @!P1 BRA 0x450 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0520*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0540*/ IADD3 R2, R0, R5, RZ ; /* 0x0000000500027210 */
/* 0x001fe20007ffe0ff */
/*0550*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fe200078e0205 */
/*0560*/ BSSY B0, 0x600 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0570*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0580*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*0590*/ @P0 BRA 0x5f0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*05b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*05c0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*05e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*05f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0600*/ @!P1 BRA 0x540 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0610*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0620*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc60000000f00 */
/*0630*/ IMAD.IADD R2, R0, 0x1, R5.reuse ; /* 0x0000000100027824 */
/* 0x101fe200078e0205 */
/*0640*/ BSSY B0, 0x6f0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0650*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*0660*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0670*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*0680*/ @P0 BRA 0x6e0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0690*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*06a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*06b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*06c0*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*06d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ @!P1 BRA 0x630 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0700*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0710*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0720*/ IADD3 R2, R0, R5, RZ ; /* 0x0000000500027210 */
/* 0x001fe20007ffe0ff */
/*0730*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fe200078e0205 */
/*0740*/ BSSY B0, 0x7e0 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0750*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0760*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*0770*/ @P0 BRA 0x7d0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0790*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*07a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*07b0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*07c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*07d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07e0*/ @!P1 BRA 0x720 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0800*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc60000000f00 */
/*0810*/ IMAD.IADD R2, R0, 0x1, R5.reuse ; /* 0x0000000100027824 */
/* 0x101fe200078e0205 */
/*0820*/ BSSY B0, 0x8d0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0830*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*0840*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0850*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*0860*/ @P0 BRA 0x8c0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0870*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0880*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0890*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*08b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ @!P1 BRA 0x810 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define LIMIT -999
#define BLOCK_SIZE 16
#define MAX_SEQ_LEN 2100
#define MAX_SEQ_NUM 1024
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <sys/time.h>
inline void cudaCheckError(int line, cudaError_t ce)
{
if (ce != cudaSuccess) {
printf("Error: line %d %s\n", line, cudaGetErrorString(ce));
exit(1);
}
}
// HACK Huan's hack
// this is not the updated validation code
int validation(int *score_matrix_cpu, int *score_matrix, unsigned int length)
{
unsigned int i = 0;
while (i!=length) {
if ( (score_matrix_cpu[i]) == (score_matrix[i] >> 2) ) {
++i;
continue;
}
else {
printf("i = %d, expected %d, got %d.\n",i, score_matrix_cpu[i], score_matrix[i] >> 2);
return 0;
}
}
return 1;
}
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
double gettime() {
struct timeval t;
gettimeofday(&t,NULL);
return t.tv_sec+t.tv_usec*1e-6;
}
__global__ void dummy_function(int * array, unsigned int howlarge)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < 9; i++) {
for (int delta=0; delta<howlarge; delta=delta+blockDim.x*gridDim.x) {
if (tid+delta < howlarge)
array[tid+delta] = array[tid+delta] + tid;
}
}
}
void runTest()
{
double start, end, now;
unsigned int nints = 100 * 1024 * 1024;
unsigned int sz = nints * sizeof(int);
unsigned int nints_small = 1 * 1024 * 1024;
unsigned int sz_small = nints_small * sizeof(int);
#ifdef _LP64
printf ("Running on a 64-bit platform!\n", 0);
#else
#endif
printf("Big Chunk of memory allocated on host & device = %d\n", sz / 1024 /1024);
printf("Small Chunk of memory allocated on host & device = %d\n", sz_small / 1024 /1024);
int * dummy_cpu, * dummy_cpu2, * dummy_small_cpu, * dummy_small_cpu2;
cudaMallocHost( (void**) &dummy_cpu, sz );
cudaMallocHost( (void**) &dummy_cpu2, sz );
cudaMallocHost ( (void**) &dummy_small_cpu, sz_small);
cudaMallocHost ( (void**) &dummy_small_cpu2, sz_small);
int * dummy_gpu, * dummy_gpu2, * dummy_small_gpu, * dummy_small_gpu2;
cudaMalloc( (void**) &dummy_gpu, sz );
cudaMalloc( (void**) &dummy_gpu2, sz );
cudaMalloc( (void**) &dummy_small_gpu, sz_small );
cudaMalloc( (void**) &dummy_small_gpu2, sz_small );
double kernelt = 0, memcpyt = 0, st = 0, ast = 0;
#define TIMES 5
start = gettime();
dummy_function<<<100,512>>>(dummy_gpu, nints);
cudaDeviceSynchronize();
end = gettime();
printf("time for kernel call = %f\n", end-start);
start = gettime();
cudaMemcpy(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost );
cudaDeviceSynchronize();
end = gettime();
printf("time for memcopy D-H = %f\n", end-start);
start = gettime();
cudaMemcpy(dummy_small_gpu, dummy_small_cpu, sz_small, cudaMemcpyHostToDevice);
dummy_function<<<100,512>>>(dummy_gpu, nints);
cudaMemcpy(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost );
cudaDeviceSynchronize();
end = gettime();
printf("time for one iteration = %f\n", end-start);
cudaStream_t stream1;
cudaStreamCreate(&stream1);
cudaStream_t stream2;
cudaStreamCreate(&stream2);
#define DEBUG 1
for (int sync=0; sync<2; sync++){
start = gettime();
for (int i = 0; i< TIMES; i++) {
// small sync copy H->D
cudaMemcpyAsync(dummy_small_gpu, dummy_small_cpu, sz_small, cudaMemcpyHostToDevice, stream1);
//kernel function
dummy_function<<<100,512, 0, stream1>>>(dummy_gpu, nints);
cudaDeviceSynchronize();
//large copy D->H can be sync or async
#ifdef DEBUG
now = gettime();
#endif
if (sync){
cudaMemcpy(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost);
}else{
cudaMemcpyAsync(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost, stream1 );
}
#ifdef DEBUG
printf("(A)sync call took %f\n", gettime() - now);
#endif
// small sync copy H->D
cudaMemcpyAsync(dummy_small_gpu2, dummy_small_cpu2, sz_small, cudaMemcpyHostToDevice, stream2);
//kernel function
dummy_function<<<100,512, 0, stream2>>>(dummy_gpu2, nints);
cudaDeviceSynchronize();
//large copy D->H can be sync or async
if (sync){
cudaMemcpy(dummy_cpu2, dummy_gpu2, sz, cudaMemcpyDeviceToHost);
}else{
cudaMemcpyAsync(dummy_cpu2, dummy_gpu2, sz, cudaMemcpyDeviceToHost , stream2);
}
}
cudaDeviceSynchronize();
end = gettime();
if (!sync)
printf("%d iterations: time for ASYNC calls = %f\n",TIMES,end-start);
else
printf("%d iterations: time for SYNC calls = %f\n",TIMES,end-start);
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
runTest();
return EXIT_SUCCESS;
} | .file "tmpxft_0009bb7c_00000000-6_dual_buffering.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "i = %d, expected %d, got %d.\n"
.text
.globl _Z10validationPiS_j
.type _Z10validationPiS_j, @function
_Z10validationPiS_j:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
je .L7
movl %edx, %eax
movl $0, %edx
.L6:
movl (%rdi,%rdx,4), %ecx
movl (%rsi,%rdx,4), %r8d
sarl $2, %r8d
cmpl %r8d, %ecx
jne .L5
addq $1, %rdx
cmpq %rax, %rdx
jne .L6
movl $1, %eax
ret
.L5:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L7:
movl $1, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z10validationPiS_j, .-_Z10validationPiS_j
.globl _Z7gettimev
.type _Z7gettimev, @function
_Z7gettimev:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z7gettimev, .-_Z7gettimev
.globl _Z35__device_stub__Z14dummy_functionPijPij
.type _Z35__device_stub__Z14dummy_functionPijPij, @function
_Z35__device_stub__Z14dummy_functionPijPij:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14dummy_functionPij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z14dummy_functionPijPij, .-_Z35__device_stub__Z14dummy_functionPijPij
.globl _Z14dummy_functionPij
.type _Z14dummy_functionPij, @function
_Z14dummy_functionPij:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14dummy_functionPijPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z14dummy_functionPij, .-_Z14dummy_functionPij
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Running on a 64-bit platform!\n"
.align 8
.LC3:
.string "Big Chunk of memory allocated on host & device = %d\n"
.align 8
.LC4:
.string "Small Chunk of memory allocated on host & device = %d\n"
.section .rodata.str1.1
.LC5:
.string "time for kernel call = %f\n"
.LC6:
.string "time for memcopy D-H = %f\n"
.LC7:
.string "time for one iteration = %f\n"
.LC8:
.string "(A)sync call took %f\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "%d iterations: time for ASYNC calls = %f\n"
.align 8
.LC10:
.string "%d iterations: time for SYNC calls = %f\n"
.text
.globl _Z7runTestv
.type _Z7runTestv, @function
_Z7runTestv:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $400, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $419430400, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $419430400, %esi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMallocHost@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMallocHost@PLT
leaq 48(%rsp), %rdi
movl $419430400, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $419430400, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
call _Z7gettimev
movsd %xmm0, (%rsp)
movl $512, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $100, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L25:
call cudaDeviceSynchronize@PLT
call _Z7gettimev
subsd (%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z7gettimev
movsd %xmm0, (%rsp)
movl $2, %ecx
movl $419430400, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call _Z7gettimev
subsd (%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z7gettimev
movsd %xmm0, (%rsp)
movl $1, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $100, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L26:
movl $2, %ecx
movl $419430400, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call _Z7gettimev
subsd (%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 88(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %ebp
leaq .LC8(%rip), %r12
leaq .LC10(%rip), %r13
.L37:
call _Z7gettimev
movsd %xmm0, 8(%rsp)
movl $5, %ebx
jmp .L33
.L41:
movl $104857600, %esi
movq 48(%rsp), %rdi
call _Z35__device_stub__Z14dummy_functionPijPij
jmp .L25
.L42:
movl $104857600, %esi
movq 48(%rsp), %rdi
call _Z35__device_stub__Z14dummy_functionPijPij
jmp .L26
.L44:
movl $104857600, %esi
movq 48(%rsp), %rdi
call _Z35__device_stub__Z14dummy_functionPijPij
jmp .L27
.L28:
movq 80(%rsp), %r8
movl $2, %ecx
movl $419430400, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpyAsync@PLT
jmp .L29
.L45:
movl $104857600, %esi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z14dummy_functionPijPij
jmp .L30
.L46:
movl $2, %ecx
movl $419430400, %edx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
.L32:
subl $1, %ebx
je .L43
.L33:
movq 80(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $512, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $100, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L27:
call cudaDeviceSynchronize@PLT
call _Z7gettimev
movsd %xmm0, (%rsp)
testl %ebp, %ebp
je .L28
movl $2, %ecx
movl $419430400, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
.L29:
call _Z7gettimev
subsd (%rsp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $512, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $100, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movq 88(%rsp), %r9
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L30:
call cudaDeviceSynchronize@PLT
testl %ebp, %ebp
jne .L46
movq 88(%rsp), %r8
movl $2, %ecx
movl $419430400, %edx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpyAsync@PLT
jmp .L32
.L43:
call cudaDeviceSynchronize@PLT
call _Z7gettimev
testl %ebp, %ebp
je .L47
subsd 8(%rsp), %xmm0
movl $5, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl $2, %ebp
jne .L37
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
subsd 8(%rsp), %xmm0
movl $5, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebp
jmp .L37
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z7runTestv, .-_Z7runTestv
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z7runTestv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z14dummy_functionPij"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z14dummy_functionPij(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define LIMIT -999
#define BLOCK_SIZE 16
#define MAX_SEQ_LEN 2100
#define MAX_SEQ_NUM 1024
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <sys/time.h>
inline void cudaCheckError(int line, cudaError_t ce)
{
if (ce != cudaSuccess) {
printf("Error: line %d %s\n", line, cudaGetErrorString(ce));
exit(1);
}
}
// HACK Huan's hack
// this is not the updated validation code
int validation(int *score_matrix_cpu, int *score_matrix, unsigned int length)
{
unsigned int i = 0;
while (i!=length) {
if ( (score_matrix_cpu[i]) == (score_matrix[i] >> 2) ) {
++i;
continue;
}
else {
printf("i = %d, expected %d, got %d.\n",i, score_matrix_cpu[i], score_matrix[i] >> 2);
return 0;
}
}
return 1;
}
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
double gettime() {
struct timeval t;
gettimeofday(&t,NULL);
return t.tv_sec+t.tv_usec*1e-6;
}
__global__ void dummy_function(int * array, unsigned int howlarge)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < 9; i++) {
for (int delta=0; delta<howlarge; delta=delta+blockDim.x*gridDim.x) {
if (tid+delta < howlarge)
array[tid+delta] = array[tid+delta] + tid;
}
}
}
void runTest()
{
double start, end, now;
unsigned int nints = 100 * 1024 * 1024;
unsigned int sz = nints * sizeof(int);
unsigned int nints_small = 1 * 1024 * 1024;
unsigned int sz_small = nints_small * sizeof(int);
#ifdef _LP64
printf ("Running on a 64-bit platform!\n", 0);
#else
#endif
printf("Big Chunk of memory allocated on host & device = %d\n", sz / 1024 /1024);
printf("Small Chunk of memory allocated on host & device = %d\n", sz_small / 1024 /1024);
int * dummy_cpu, * dummy_cpu2, * dummy_small_cpu, * dummy_small_cpu2;
cudaMallocHost( (void**) &dummy_cpu, sz );
cudaMallocHost( (void**) &dummy_cpu2, sz );
cudaMallocHost ( (void**) &dummy_small_cpu, sz_small);
cudaMallocHost ( (void**) &dummy_small_cpu2, sz_small);
int * dummy_gpu, * dummy_gpu2, * dummy_small_gpu, * dummy_small_gpu2;
cudaMalloc( (void**) &dummy_gpu, sz );
cudaMalloc( (void**) &dummy_gpu2, sz );
cudaMalloc( (void**) &dummy_small_gpu, sz_small );
cudaMalloc( (void**) &dummy_small_gpu2, sz_small );
double kernelt = 0, memcpyt = 0, st = 0, ast = 0;
#define TIMES 5
start = gettime();
dummy_function<<<100,512>>>(dummy_gpu, nints);
cudaDeviceSynchronize();
end = gettime();
printf("time for kernel call = %f\n", end-start);
start = gettime();
cudaMemcpy(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost );
cudaDeviceSynchronize();
end = gettime();
printf("time for memcopy D-H = %f\n", end-start);
start = gettime();
cudaMemcpy(dummy_small_gpu, dummy_small_cpu, sz_small, cudaMemcpyHostToDevice);
dummy_function<<<100,512>>>(dummy_gpu, nints);
cudaMemcpy(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost );
cudaDeviceSynchronize();
end = gettime();
printf("time for one iteration = %f\n", end-start);
cudaStream_t stream1;
cudaStreamCreate(&stream1);
cudaStream_t stream2;
cudaStreamCreate(&stream2);
#define DEBUG 1
for (int sync=0; sync<2; sync++){
start = gettime();
for (int i = 0; i< TIMES; i++) {
// small sync copy H->D
cudaMemcpyAsync(dummy_small_gpu, dummy_small_cpu, sz_small, cudaMemcpyHostToDevice, stream1);
//kernel function
dummy_function<<<100,512, 0, stream1>>>(dummy_gpu, nints);
cudaDeviceSynchronize();
//large copy D->H can be sync or async
#ifdef DEBUG
now = gettime();
#endif
if (sync){
cudaMemcpy(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost);
}else{
cudaMemcpyAsync(dummy_cpu, dummy_gpu, sz, cudaMemcpyDeviceToHost, stream1 );
}
#ifdef DEBUG
printf("(A)sync call took %f\n", gettime() - now);
#endif
// small sync copy H->D
cudaMemcpyAsync(dummy_small_gpu2, dummy_small_cpu2, sz_small, cudaMemcpyHostToDevice, stream2);
//kernel function
dummy_function<<<100,512, 0, stream2>>>(dummy_gpu2, nints);
cudaDeviceSynchronize();
//large copy D->H can be sync or async
if (sync){
cudaMemcpy(dummy_cpu2, dummy_gpu2, sz, cudaMemcpyDeviceToHost);
}else{
cudaMemcpyAsync(dummy_cpu2, dummy_gpu2, sz, cudaMemcpyDeviceToHost , stream2);
}
}
cudaDeviceSynchronize();
end = gettime();
if (!sync)
printf("%d iterations: time for ASYNC calls = %f\n",TIMES,end-start);
else
printf("%d iterations: time for SYNC calls = %f\n",TIMES,end-start);
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
runTest();
return EXIT_SUCCESS;
} | #define LIMIT -999
#define BLOCK_SIZE 16
#define MAX_SEQ_LEN 2100
#define MAX_SEQ_NUM 1024
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
inline void cudaCheckError(int line, hipError_t ce)
{
if (ce != hipSuccess) {
printf("Error: line %d %s\n", line, hipGetErrorString(ce));
exit(1);
}
}
// HACK Huan's hack
// this is not the updated validation code
int validation(int *score_matrix_cpu, int *score_matrix, unsigned int length)
{
unsigned int i = 0;
while (i!=length) {
if ( (score_matrix_cpu[i]) == (score_matrix[i] >> 2) ) {
++i;
continue;
}
else {
printf("i = %d, expected %d, got %d.\n",i, score_matrix_cpu[i], score_matrix[i] >> 2);
return 0;
}
}
return 1;
}
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
double gettime() {
struct timeval t;
gettimeofday(&t,NULL);
return t.tv_sec+t.tv_usec*1e-6;
}
__global__ void dummy_function(int * array, unsigned int howlarge)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < 9; i++) {
for (int delta=0; delta<howlarge; delta=delta+blockDim.x*gridDim.x) {
if (tid+delta < howlarge)
array[tid+delta] = array[tid+delta] + tid;
}
}
}
void runTest()
{
double start, end, now;
unsigned int nints = 100 * 1024 * 1024;
unsigned int sz = nints * sizeof(int);
unsigned int nints_small = 1 * 1024 * 1024;
unsigned int sz_small = nints_small * sizeof(int);
#ifdef _LP64
printf ("Running on a 64-bit platform!\n", 0);
#else
#endif
printf("Big Chunk of memory allocated on host & device = %d\n", sz / 1024 /1024);
printf("Small Chunk of memory allocated on host & device = %d\n", sz_small / 1024 /1024);
int * dummy_cpu, * dummy_cpu2, * dummy_small_cpu, * dummy_small_cpu2;
hipHostMalloc( (void**) &dummy_cpu, sz , hipHostMallocDefault);
hipHostMalloc( (void**) &dummy_cpu2, sz , hipHostMallocDefault);
hipHostMalloc ( (void**) &dummy_small_cpu, sz_small, hipHostMallocDefault);
hipHostMalloc ( (void**) &dummy_small_cpu2, sz_small, hipHostMallocDefault);
int * dummy_gpu, * dummy_gpu2, * dummy_small_gpu, * dummy_small_gpu2;
hipMalloc( (void**) &dummy_gpu, sz );
hipMalloc( (void**) &dummy_gpu2, sz );
hipMalloc( (void**) &dummy_small_gpu, sz_small );
hipMalloc( (void**) &dummy_small_gpu2, sz_small );
double kernelt = 0, memcpyt = 0, st = 0, ast = 0;
#define TIMES 5
start = gettime();
dummy_function<<<100,512>>>(dummy_gpu, nints);
hipDeviceSynchronize();
end = gettime();
printf("time for kernel call = %f\n", end-start);
start = gettime();
hipMemcpy(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost );
hipDeviceSynchronize();
end = gettime();
printf("time for memcopy D-H = %f\n", end-start);
start = gettime();
hipMemcpy(dummy_small_gpu, dummy_small_cpu, sz_small, hipMemcpyHostToDevice);
dummy_function<<<100,512>>>(dummy_gpu, nints);
hipMemcpy(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost );
hipDeviceSynchronize();
end = gettime();
printf("time for one iteration = %f\n", end-start);
hipStream_t stream1;
hipStreamCreate(&stream1);
hipStream_t stream2;
hipStreamCreate(&stream2);
#define DEBUG 1
for (int sync=0; sync<2; sync++){
start = gettime();
for (int i = 0; i< TIMES; i++) {
// small sync copy H->D
hipMemcpyAsync(dummy_small_gpu, dummy_small_cpu, sz_small, hipMemcpyHostToDevice, stream1);
//kernel function
dummy_function<<<100,512, 0, stream1>>>(dummy_gpu, nints);
hipDeviceSynchronize();
//large copy D->H can be sync or async
#ifdef DEBUG
now = gettime();
#endif
if (sync){
hipMemcpy(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost);
}else{
hipMemcpyAsync(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost, stream1 );
}
#ifdef DEBUG
printf("(A)sync call took %f\n", gettime() - now);
#endif
// small sync copy H->D
hipMemcpyAsync(dummy_small_gpu2, dummy_small_cpu2, sz_small, hipMemcpyHostToDevice, stream2);
//kernel function
dummy_function<<<100,512, 0, stream2>>>(dummy_gpu2, nints);
hipDeviceSynchronize();
//large copy D->H can be sync or async
if (sync){
hipMemcpy(dummy_cpu2, dummy_gpu2, sz, hipMemcpyDeviceToHost);
}else{
hipMemcpyAsync(dummy_cpu2, dummy_gpu2, sz, hipMemcpyDeviceToHost , stream2);
}
}
hipDeviceSynchronize();
end = gettime();
if (!sync)
printf("%d iterations: time for ASYNC calls = %f\n",TIMES,end-start);
else
printf("%d iterations: time for SYNC calls = %f\n",TIMES,end-start);
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
runTest();
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define LIMIT -999
#define BLOCK_SIZE 16
#define MAX_SEQ_LEN 2100
#define MAX_SEQ_NUM 1024
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
inline void cudaCheckError(int line, hipError_t ce)
{
if (ce != hipSuccess) {
printf("Error: line %d %s\n", line, hipGetErrorString(ce));
exit(1);
}
}
// HACK Huan's hack
// this is not the updated validation code
int validation(int *score_matrix_cpu, int *score_matrix, unsigned int length)
{
unsigned int i = 0;
while (i!=length) {
if ( (score_matrix_cpu[i]) == (score_matrix[i] >> 2) ) {
++i;
continue;
}
else {
printf("i = %d, expected %d, got %d.\n",i, score_matrix_cpu[i], score_matrix[i] >> 2);
return 0;
}
}
return 1;
}
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
double gettime() {
struct timeval t;
gettimeofday(&t,NULL);
return t.tv_sec+t.tv_usec*1e-6;
}
__global__ void dummy_function(int * array, unsigned int howlarge)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < 9; i++) {
for (int delta=0; delta<howlarge; delta=delta+blockDim.x*gridDim.x) {
if (tid+delta < howlarge)
array[tid+delta] = array[tid+delta] + tid;
}
}
}
void runTest()
{
double start, end, now;
unsigned int nints = 100 * 1024 * 1024;
unsigned int sz = nints * sizeof(int);
unsigned int nints_small = 1 * 1024 * 1024;
unsigned int sz_small = nints_small * sizeof(int);
#ifdef _LP64
printf ("Running on a 64-bit platform!\n", 0);
#else
#endif
printf("Big Chunk of memory allocated on host & device = %d\n", sz / 1024 /1024);
printf("Small Chunk of memory allocated on host & device = %d\n", sz_small / 1024 /1024);
int * dummy_cpu, * dummy_cpu2, * dummy_small_cpu, * dummy_small_cpu2;
hipHostMalloc( (void**) &dummy_cpu, sz , hipHostMallocDefault);
hipHostMalloc( (void**) &dummy_cpu2, sz , hipHostMallocDefault);
hipHostMalloc ( (void**) &dummy_small_cpu, sz_small, hipHostMallocDefault);
hipHostMalloc ( (void**) &dummy_small_cpu2, sz_small, hipHostMallocDefault);
int * dummy_gpu, * dummy_gpu2, * dummy_small_gpu, * dummy_small_gpu2;
hipMalloc( (void**) &dummy_gpu, sz );
hipMalloc( (void**) &dummy_gpu2, sz );
hipMalloc( (void**) &dummy_small_gpu, sz_small );
hipMalloc( (void**) &dummy_small_gpu2, sz_small );
double kernelt = 0, memcpyt = 0, st = 0, ast = 0;
#define TIMES 5
start = gettime();
dummy_function<<<100,512>>>(dummy_gpu, nints);
hipDeviceSynchronize();
end = gettime();
printf("time for kernel call = %f\n", end-start);
start = gettime();
hipMemcpy(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost );
hipDeviceSynchronize();
end = gettime();
printf("time for memcopy D-H = %f\n", end-start);
start = gettime();
hipMemcpy(dummy_small_gpu, dummy_small_cpu, sz_small, hipMemcpyHostToDevice);
dummy_function<<<100,512>>>(dummy_gpu, nints);
hipMemcpy(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost );
hipDeviceSynchronize();
end = gettime();
printf("time for one iteration = %f\n", end-start);
hipStream_t stream1;
hipStreamCreate(&stream1);
hipStream_t stream2;
hipStreamCreate(&stream2);
#define DEBUG 1
for (int sync=0; sync<2; sync++){
start = gettime();
for (int i = 0; i< TIMES; i++) {
// small sync copy H->D
hipMemcpyAsync(dummy_small_gpu, dummy_small_cpu, sz_small, hipMemcpyHostToDevice, stream1);
//kernel function
dummy_function<<<100,512, 0, stream1>>>(dummy_gpu, nints);
hipDeviceSynchronize();
//large copy D->H can be sync or async
#ifdef DEBUG
now = gettime();
#endif
if (sync){
hipMemcpy(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost);
}else{
hipMemcpyAsync(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost, stream1 );
}
#ifdef DEBUG
printf("(A)sync call took %f\n", gettime() - now);
#endif
// small sync copy H->D
hipMemcpyAsync(dummy_small_gpu2, dummy_small_cpu2, sz_small, hipMemcpyHostToDevice, stream2);
//kernel function
dummy_function<<<100,512, 0, stream2>>>(dummy_gpu2, nints);
hipDeviceSynchronize();
//large copy D->H can be sync or async
if (sync){
hipMemcpy(dummy_cpu2, dummy_gpu2, sz, hipMemcpyDeviceToHost);
}else{
hipMemcpyAsync(dummy_cpu2, dummy_gpu2, sz, hipMemcpyDeviceToHost , stream2);
}
}
hipDeviceSynchronize();
end = gettime();
if (!sync)
printf("%d iterations: time for ASYNC calls = %f\n",TIMES,end-start);
else
printf("%d iterations: time for SYNC calls = %f\n",TIMES,end-start);
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
runTest();
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14dummy_functionPij
.globl _Z14dummy_functionPij
.p2align 8
.type _Z14dummy_functionPij,@function
_Z14dummy_functionPij:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s3, 0xffff
s_cmp_lg_u32 s2, 0
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_cselect_b32 s3, -1, 0
s_mul_i32 s5, s5, s6
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 9
s_cbranch_scc1 .LBB0_7
.LBB0_2:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_1
s_mov_b32 s6, 0
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
s_add_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s2
s_cbranch_scc1 .LBB0_1
.LBB0_5:
v_add_nc_u32_e32 v2, s6, v1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v1
global_store_b32 v[2:3], v0, off
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14dummy_functionPij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14dummy_functionPij, .Lfunc_end0-_Z14dummy_functionPij
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14dummy_functionPij
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14dummy_functionPij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define LIMIT -999
#define BLOCK_SIZE 16
#define MAX_SEQ_LEN 2100
#define MAX_SEQ_NUM 1024
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
inline void cudaCheckError(int line, hipError_t ce)
{
if (ce != hipSuccess) {
printf("Error: line %d %s\n", line, hipGetErrorString(ce));
exit(1);
}
}
// HACK Huan's hack
// this is not the updated validation code
int validation(int *score_matrix_cpu, int *score_matrix, unsigned int length)
{
unsigned int i = 0;
while (i!=length) {
if ( (score_matrix_cpu[i]) == (score_matrix[i] >> 2) ) {
++i;
continue;
}
else {
printf("i = %d, expected %d, got %d.\n",i, score_matrix_cpu[i], score_matrix[i] >> 2);
return 0;
}
}
return 1;
}
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
void runTest( int argc, char** argv);
double gettime() {
struct timeval t;
gettimeofday(&t,NULL);
return t.tv_sec+t.tv_usec*1e-6;
}
__global__ void dummy_function(int * array, unsigned int howlarge)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < 9; i++) {
for (int delta=0; delta<howlarge; delta=delta+blockDim.x*gridDim.x) {
if (tid+delta < howlarge)
array[tid+delta] = array[tid+delta] + tid;
}
}
}
void runTest()
{
double start, end, now;
unsigned int nints = 100 * 1024 * 1024;
unsigned int sz = nints * sizeof(int);
unsigned int nints_small = 1 * 1024 * 1024;
unsigned int sz_small = nints_small * sizeof(int);
#ifdef _LP64
printf ("Running on a 64-bit platform!\n", 0);
#else
#endif
printf("Big Chunk of memory allocated on host & device = %d\n", sz / 1024 /1024);
printf("Small Chunk of memory allocated on host & device = %d\n", sz_small / 1024 /1024);
int * dummy_cpu, * dummy_cpu2, * dummy_small_cpu, * dummy_small_cpu2;
hipHostMalloc( (void**) &dummy_cpu, sz , hipHostMallocDefault);
hipHostMalloc( (void**) &dummy_cpu2, sz , hipHostMallocDefault);
hipHostMalloc ( (void**) &dummy_small_cpu, sz_small, hipHostMallocDefault);
hipHostMalloc ( (void**) &dummy_small_cpu2, sz_small, hipHostMallocDefault);
int * dummy_gpu, * dummy_gpu2, * dummy_small_gpu, * dummy_small_gpu2;
hipMalloc( (void**) &dummy_gpu, sz );
hipMalloc( (void**) &dummy_gpu2, sz );
hipMalloc( (void**) &dummy_small_gpu, sz_small );
hipMalloc( (void**) &dummy_small_gpu2, sz_small );
double kernelt = 0, memcpyt = 0, st = 0, ast = 0;
#define TIMES 5
start = gettime();
dummy_function<<<100,512>>>(dummy_gpu, nints);
hipDeviceSynchronize();
end = gettime();
printf("time for kernel call = %f\n", end-start);
start = gettime();
hipMemcpy(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost );
hipDeviceSynchronize();
end = gettime();
printf("time for memcopy D-H = %f\n", end-start);
start = gettime();
hipMemcpy(dummy_small_gpu, dummy_small_cpu, sz_small, hipMemcpyHostToDevice);
dummy_function<<<100,512>>>(dummy_gpu, nints);
hipMemcpy(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost );
hipDeviceSynchronize();
end = gettime();
printf("time for one iteration = %f\n", end-start);
hipStream_t stream1;
hipStreamCreate(&stream1);
hipStream_t stream2;
hipStreamCreate(&stream2);
#define DEBUG 1
for (int sync=0; sync<2; sync++){
start = gettime();
for (int i = 0; i< TIMES; i++) {
// small sync copy H->D
hipMemcpyAsync(dummy_small_gpu, dummy_small_cpu, sz_small, hipMemcpyHostToDevice, stream1);
//kernel function
dummy_function<<<100,512, 0, stream1>>>(dummy_gpu, nints);
hipDeviceSynchronize();
//large copy D->H can be sync or async
#ifdef DEBUG
now = gettime();
#endif
if (sync){
hipMemcpy(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost);
}else{
hipMemcpyAsync(dummy_cpu, dummy_gpu, sz, hipMemcpyDeviceToHost, stream1 );
}
#ifdef DEBUG
printf("(A)sync call took %f\n", gettime() - now);
#endif
// small sync copy H->D
hipMemcpyAsync(dummy_small_gpu2, dummy_small_cpu2, sz_small, hipMemcpyHostToDevice, stream2);
//kernel function
dummy_function<<<100,512, 0, stream2>>>(dummy_gpu2, nints);
hipDeviceSynchronize();
//large copy D->H can be sync or async
if (sync){
hipMemcpy(dummy_cpu2, dummy_gpu2, sz, hipMemcpyDeviceToHost);
}else{
hipMemcpyAsync(dummy_cpu2, dummy_gpu2, sz, hipMemcpyDeviceToHost , stream2);
}
}
hipDeviceSynchronize();
end = gettime();
if (!sync)
printf("%d iterations: time for ASYNC calls = %f\n",TIMES,end-start);
else
printf("%d iterations: time for SYNC calls = %f\n",TIMES,end-start);
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
runTest();
return EXIT_SUCCESS;
} | .text
.file "dual_buffering.hip"
.globl _Z10validationPiS_j # -- Begin function _Z10validationPiS_j
.p2align 4, 0x90
.type _Z10validationPiS_j,@function
_Z10validationPiS_j: # @_Z10validationPiS_j
.cfi_startproc
# %bb.0:
movl $1, %eax
testl %edx, %edx
je .LBB0_5
# %bb.1: # %.lr.ph.preheader
movl %edx, %r9d
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%r8,4), %edx
movl (%rsi,%r8,4), %ecx
sarl $2, %ecx
cmpl %ecx, %edx
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
incq %r8
cmpl %r8d, %r9d
jne .LBB0_2
.LBB0_5: # %.loopexit
retq
.LBB0_4:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl %r8d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10validationPiS_j, .Lfunc_end0-_Z10validationPiS_j
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7gettimev
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7gettimev
.p2align 4, 0x90
.type _Z7gettimev,@function
_Z7gettimev: # @_Z7gettimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7gettimev, .Lfunc_end1-_Z7gettimev
.cfi_endproc
# -- End function
.globl _Z29__device_stub__dummy_functionPij # -- Begin function _Z29__device_stub__dummy_functionPij
.p2align 4, 0x90
.type _Z29__device_stub__dummy_functionPij,@function
_Z29__device_stub__dummy_functionPij: # @_Z29__device_stub__dummy_functionPij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14dummy_functionPij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z29__device_stub__dummy_functionPij, .Lfunc_end2-_Z29__device_stub__dummy_functionPij
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7runTestv
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7runTestv
.p2align 4, 0x90
.type _Z7runTestv,@function
_Z7runTestv: # @_Z7runTestv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967396, %rbx # imm = 0x100000064
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movl $400, %esi # imm = 0x190
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
leaq 128(%rsp), %rdi
movl $419430400, %esi # imm = 0x19000000
xorl %edx, %edx
callq hipHostMalloc
leaq 192(%rsp), %rdi
movl $419430400, %esi # imm = 0x19000000
xorl %edx, %edx
callq hipHostMalloc
leaq 152(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
leaq 184(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
leaq 96(%rsp), %rdi
movl $419430400, %esi # imm = 0x19000000
callq hipMalloc
leaq 144(%rsp), %rdi
movl $419430400, %esi # imm = 0x19000000
callq hipMalloc
leaq 136(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 176(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm0
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
leaq 412(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movl $104857600, 32(%rsp) # imm = 0x6400000
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z14dummy_functionPij, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
xorl %r13d, %r13d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movq 128(%rsp), %rdi
movq 96(%rsp), %rsi
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movq 136(%rsp), %rdi
movq 152(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movl $104857600, 32(%rsp) # imm = 0x6400000
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z14dummy_functionPij, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 128(%rsp), %rdi
movq 96(%rsp), %rsi
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq %rsp, %r15
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.6, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
callq hipStreamCreate
leaq 120(%rsp), %rdi
callq hipStreamCreate
leaq 104(%rsp), %r12
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_10: # in Loop: Header=BB3_5 Depth=1
xorps %xmm0, %xmm0
cvtsi2sdq 160(%rsp), %xmm0 # 8-byte Folded Reload
movsd 112(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 112(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm0
addsd %xmm1, %xmm0
subsd 112(%rsp), %xmm0 # 8-byte Folded Reload
testl %r13d, %r13d
movl $.L.str.9, %edi
movl $.L.str.8, %eax
cmoveq %rax, %rdi
movl $5, %esi
movb $1, %al
callq printf
leal 1(%r13), %eax
testl %r13d, %r13d
movl %eax, %r13d
jne .LBB3_11
.LBB3_5: # =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 160(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 112(%rsp) # 8-byte Spill
movl $5, %ebp
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_6 Depth=2
movq 120(%rsp), %r8
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpyAsync
.LBB3_18: # in Loop: Header=BB3_6 Depth=2
decl %ebp
je .LBB3_10
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movq 136(%rsp), %rdi
movq 152(%rsp), %rsi
movq 32(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=2
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movl $104857600, 92(%rsp) # imm = 0x6400000
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 92(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z14dummy_functionPij, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8: # in Loop: Header=BB3_6 Depth=2
callq hipDeviceSynchronize
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
movsd %xmm0, 168(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq 128(%rsp), %rdi
movq 96(%rsp), %rsi
testl %r13d, %r13d
je .LBB3_12
# %bb.9: # in Loop: Header=BB3_6 Depth=2
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpy
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_6 Depth=2
movq 32(%rsp), %r8
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpyAsync
.LBB3_13: # in Loop: Header=BB3_6 Depth=2
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 168(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 176(%rsp), %rdi
movq 184(%rsp), %rsi
movq 120(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 120(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14: # in Loop: Header=BB3_6 Depth=2
movq 144(%rsp), %rax
movq %rax, 80(%rsp)
movl $104857600, 92(%rsp) # imm = 0x6400000
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 92(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z14dummy_functionPij, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15: # in Loop: Header=BB3_6 Depth=2
callq hipDeviceSynchronize
movq 192(%rsp), %rdi
movq 144(%rsp), %rsi
testl %r13d, %r13d
je .LBB3_17
# %bb.16: # in Loop: Header=BB3_6 Depth=2
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpy
jmp .LBB3_18
.LBB3_11:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7runTestv, .Lfunc_end3-_Z7runTestv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z7runTestv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14dummy_functionPij, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i = %d, expected %d, got %d.\n"
.size .L.str, 30
.type _Z14dummy_functionPij,@object # @_Z14dummy_functionPij
.section .rodata,"a",@progbits
.globl _Z14dummy_functionPij
.p2align 3, 0x0
_Z14dummy_functionPij:
.quad _Z29__device_stub__dummy_functionPij
.size _Z14dummy_functionPij, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Big Chunk of memory allocated on host & device = %d\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Small Chunk of memory allocated on host & device = %d\n"
.size .L.str.3, 55
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time for kernel call = %f\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "time for memcopy D-H = %f\n"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "time for one iteration = %f\n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "(A)sync call took %f\n"
.size .L.str.7, 22
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d iterations: time for ASYNC calls = %f\n"
.size .L.str.8, 42
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d iterations: time for SYNC calls = %f\n"
.size .L.str.9, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14dummy_functionPij"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running on a 64-bit platform!"
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__dummy_functionPij
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14dummy_functionPij
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14dummy_functionPij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003f05270 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fd000078e0203 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ IMAD.IADD R3, R0, 0x1, R5.reuse ; /* 0x0000000100037824 */
/* 0x101fe200078e0205 */
/*00a0*/ BSSY B0, 0x150 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe40003f06070 */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*00e0*/ @P0 BRA 0x140 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*0100*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0110*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0120*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ @!P1 BRA 0x90 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0160*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0180*/ IADD3 R2, R0, R5, RZ ; /* 0x0000000500027210 */
/* 0x001fe20007ffe0ff */
/*0190*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fe200078e0205 */
/*01a0*/ BSSY B0, 0x240 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*01d0*/ @P0 BRA 0x230 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0200*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0210*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*0220*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ @!P1 BRA 0x180 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0260*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc60000000f00 */
/*0270*/ IMAD.IADD R2, R0, 0x1, R5.reuse ; /* 0x0000000100027824 */
/* 0x101fe200078e0205 */
/*0280*/ BSSY B0, 0x330 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*02b0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*02c0*/ @P0 BRA 0x320 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*02d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*02e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*02f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0300*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*0310*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ @!P1 BRA 0x270 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0340*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0360*/ IADD3 R2, R0, R5, RZ ; /* 0x0000000500027210 */
/* 0x001fe20007ffe0ff */
/*0370*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fe200078e0205 */
/*0380*/ BSSY B0, 0x420 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0390*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*03a0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*03b0*/ @P0 BRA 0x410 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*03e0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*0400*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ @!P1 BRA 0x360 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0440*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc60000000f00 */
/*0450*/ IMAD.IADD R2, R0, 0x1, R5.reuse ; /* 0x0000000100027824 */
/* 0x101fe200078e0205 */
/*0460*/ BSSY B0, 0x510 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0470*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*0480*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0490*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*04a0*/ @P0 BRA 0x500 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*04b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*04c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*04d0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*04f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ @!P1 BRA 0x450 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0520*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0540*/ IADD3 R2, R0, R5, RZ ; /* 0x0000000500027210 */
/* 0x001fe20007ffe0ff */
/*0550*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fe200078e0205 */
/*0560*/ BSSY B0, 0x600 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0570*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0580*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*0590*/ @P0 BRA 0x5f0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*05b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*05c0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*05e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*05f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0600*/ @!P1 BRA 0x540 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0610*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0620*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc60000000f00 */
/*0630*/ IMAD.IADD R2, R0, 0x1, R5.reuse ; /* 0x0000000100027824 */
/* 0x101fe200078e0205 */
/*0640*/ BSSY B0, 0x6f0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0650*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*0660*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0670*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*0680*/ @P0 BRA 0x6e0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0690*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*06a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*06b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*06c0*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*06d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ @!P1 BRA 0x630 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0700*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0710*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0720*/ IADD3 R2, R0, R5, RZ ; /* 0x0000000500027210 */
/* 0x001fe20007ffe0ff */
/*0730*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fe200078e0205 */
/*0740*/ BSSY B0, 0x7e0 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0750*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0760*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*0770*/ @P0 BRA 0x7d0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0790*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*07a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*07b0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*07c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*07d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07e0*/ @!P1 BRA 0x720 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0800*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc60000000f00 */
/*0810*/ IMAD.IADD R2, R0, 0x1, R5.reuse ; /* 0x0000000100027824 */
/* 0x101fe200078e0205 */
/*0820*/ BSSY B0, 0x8d0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0830*/ IMAD R5, R4, c[0x0][0xc], R5 ; /* 0x0000030004057a24 */
/* 0x000fc600078e0205 */
/*0840*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0850*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fd60003f26070 */
/*0860*/ @P0 BRA 0x8c0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0870*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0880*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0890*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*08b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ @!P1 BRA 0x810 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14dummy_functionPij
.globl _Z14dummy_functionPij
.p2align 8
.type _Z14dummy_functionPij,@function
_Z14dummy_functionPij:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s3, 0xffff
s_cmp_lg_u32 s2, 0
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_cselect_b32 s3, -1, 0
s_mul_i32 s5, s5, s6
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 9
s_cbranch_scc1 .LBB0_7
.LBB0_2:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_1
s_mov_b32 s6, 0
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
s_add_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s2
s_cbranch_scc1 .LBB0_1
.LBB0_5:
v_add_nc_u32_e32 v2, s6, v1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v1
global_store_b32 v[2:3], v0, off
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14dummy_functionPij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14dummy_functionPij, .Lfunc_end0-_Z14dummy_functionPij
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14dummy_functionPij
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14dummy_functionPij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009bb7c_00000000-6_dual_buffering.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "i = %d, expected %d, got %d.\n"
.text
.globl _Z10validationPiS_j
.type _Z10validationPiS_j, @function
_Z10validationPiS_j:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
je .L7
movl %edx, %eax
movl $0, %edx
.L6:
movl (%rdi,%rdx,4), %ecx
movl (%rsi,%rdx,4), %r8d
sarl $2, %r8d
cmpl %r8d, %ecx
jne .L5
addq $1, %rdx
cmpq %rax, %rdx
jne .L6
movl $1, %eax
ret
.L5:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L7:
movl $1, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z10validationPiS_j, .-_Z10validationPiS_j
.globl _Z7gettimev
.type _Z7gettimev, @function
_Z7gettimev:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z7gettimev, .-_Z7gettimev
.globl _Z35__device_stub__Z14dummy_functionPijPij
.type _Z35__device_stub__Z14dummy_functionPijPij, @function
_Z35__device_stub__Z14dummy_functionPijPij:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14dummy_functionPij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z14dummy_functionPijPij, .-_Z35__device_stub__Z14dummy_functionPijPij
.globl _Z14dummy_functionPij
.type _Z14dummy_functionPij, @function
_Z14dummy_functionPij:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14dummy_functionPijPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z14dummy_functionPij, .-_Z14dummy_functionPij
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Running on a 64-bit platform!\n"
.align 8
.LC3:
.string "Big Chunk of memory allocated on host & device = %d\n"
.align 8
.LC4:
.string "Small Chunk of memory allocated on host & device = %d\n"
.section .rodata.str1.1
.LC5:
.string "time for kernel call = %f\n"
.LC6:
.string "time for memcopy D-H = %f\n"
.LC7:
.string "time for one iteration = %f\n"
.LC8:
.string "(A)sync call took %f\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "%d iterations: time for ASYNC calls = %f\n"
.align 8
.LC10:
.string "%d iterations: time for SYNC calls = %f\n"
.text
.globl _Z7runTestv
.type _Z7runTestv, @function
_Z7runTestv:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $400, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $419430400, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $419430400, %esi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMallocHost@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMallocHost@PLT
leaq 48(%rsp), %rdi
movl $419430400, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $419430400, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
call _Z7gettimev
movsd %xmm0, (%rsp)
movl $512, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $100, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L25:
call cudaDeviceSynchronize@PLT
call _Z7gettimev
subsd (%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z7gettimev
movsd %xmm0, (%rsp)
movl $2, %ecx
movl $419430400, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call _Z7gettimev
subsd (%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z7gettimev
movsd %xmm0, (%rsp)
movl $1, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $100, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L26:
movl $2, %ecx
movl $419430400, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call _Z7gettimev
subsd (%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 88(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %ebp
leaq .LC8(%rip), %r12
leaq .LC10(%rip), %r13
.L37:
call _Z7gettimev
movsd %xmm0, 8(%rsp)
movl $5, %ebx
jmp .L33
.L41:
movl $104857600, %esi
movq 48(%rsp), %rdi
call _Z35__device_stub__Z14dummy_functionPijPij
jmp .L25
.L42:
movl $104857600, %esi
movq 48(%rsp), %rdi
call _Z35__device_stub__Z14dummy_functionPijPij
jmp .L26
.L44:
movl $104857600, %esi
movq 48(%rsp), %rdi
call _Z35__device_stub__Z14dummy_functionPijPij
jmp .L27
.L28:
movq 80(%rsp), %r8
movl $2, %ecx
movl $419430400, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpyAsync@PLT
jmp .L29
.L45:
movl $104857600, %esi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z14dummy_functionPijPij
jmp .L30
.L46:
movl $2, %ecx
movl $419430400, %edx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
.L32:
subl $1, %ebx
je .L43
.L33:
movq 80(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $512, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $100, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L27:
call cudaDeviceSynchronize@PLT
call _Z7gettimev
movsd %xmm0, (%rsp)
testl %ebp, %ebp
je .L28
movl $2, %ecx
movl $419430400, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
.L29:
call _Z7gettimev
subsd (%rsp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $512, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $100, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movq 88(%rsp), %r9
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L30:
call cudaDeviceSynchronize@PLT
testl %ebp, %ebp
jne .L46
movq 88(%rsp), %r8
movl $2, %ecx
movl $419430400, %edx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpyAsync@PLT
jmp .L32
.L43:
call cudaDeviceSynchronize@PLT
call _Z7gettimev
testl %ebp, %ebp
je .L47
subsd 8(%rsp), %xmm0
movl $5, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl $2, %ebp
jne .L37
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
subsd 8(%rsp), %xmm0
movl $5, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebp
jmp .L37
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z7runTestv, .-_Z7runTestv
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z7runTestv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z14dummy_functionPij"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z14dummy_functionPij(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dual_buffering.hip"
.globl _Z10validationPiS_j # -- Begin function _Z10validationPiS_j
.p2align 4, 0x90
.type _Z10validationPiS_j,@function
_Z10validationPiS_j: # @_Z10validationPiS_j
.cfi_startproc
# %bb.0:
movl $1, %eax
testl %edx, %edx
je .LBB0_5
# %bb.1: # %.lr.ph.preheader
movl %edx, %r9d
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%r8,4), %edx
movl (%rsi,%r8,4), %ecx
sarl $2, %ecx
cmpl %ecx, %edx
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
incq %r8
cmpl %r8d, %r9d
jne .LBB0_2
.LBB0_5: # %.loopexit
retq
.LBB0_4:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl %r8d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10validationPiS_j, .Lfunc_end0-_Z10validationPiS_j
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7gettimev
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7gettimev
.p2align 4, 0x90
.type _Z7gettimev,@function
_Z7gettimev: # @_Z7gettimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7gettimev, .Lfunc_end1-_Z7gettimev
.cfi_endproc
# -- End function
.globl _Z29__device_stub__dummy_functionPij # -- Begin function _Z29__device_stub__dummy_functionPij
.p2align 4, 0x90
.type _Z29__device_stub__dummy_functionPij,@function
_Z29__device_stub__dummy_functionPij: # @_Z29__device_stub__dummy_functionPij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14dummy_functionPij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z29__device_stub__dummy_functionPij, .Lfunc_end2-_Z29__device_stub__dummy_functionPij
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7runTestv
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7runTestv
.p2align 4, 0x90
.type _Z7runTestv,@function
_Z7runTestv: # @_Z7runTestv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967396, %rbx # imm = 0x100000064
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movl $400, %esi # imm = 0x190
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
leaq 128(%rsp), %rdi
movl $419430400, %esi # imm = 0x19000000
xorl %edx, %edx
callq hipHostMalloc
leaq 192(%rsp), %rdi
movl $419430400, %esi # imm = 0x19000000
xorl %edx, %edx
callq hipHostMalloc
leaq 152(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
leaq 184(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
leaq 96(%rsp), %rdi
movl $419430400, %esi # imm = 0x19000000
callq hipMalloc
leaq 144(%rsp), %rdi
movl $419430400, %esi # imm = 0x19000000
callq hipMalloc
leaq 136(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 176(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm0
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
leaq 412(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movl $104857600, 32(%rsp) # imm = 0x6400000
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z14dummy_functionPij, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
xorl %r13d, %r13d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movq 128(%rsp), %rdi
movq 96(%rsp), %rsi
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movq 136(%rsp), %rdi
movq 152(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movl $104857600, 32(%rsp) # imm = 0x6400000
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z14dummy_functionPij, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 128(%rsp), %rdi
movq 96(%rsp), %rsi
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq %rsp, %r15
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.6, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
callq hipStreamCreate
leaq 120(%rsp), %rdi
callq hipStreamCreate
leaq 104(%rsp), %r12
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_10: # in Loop: Header=BB3_5 Depth=1
xorps %xmm0, %xmm0
cvtsi2sdq 160(%rsp), %xmm0 # 8-byte Folded Reload
movsd 112(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 112(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm0
addsd %xmm1, %xmm0
subsd 112(%rsp), %xmm0 # 8-byte Folded Reload
testl %r13d, %r13d
movl $.L.str.9, %edi
movl $.L.str.8, %eax
cmoveq %rax, %rdi
movl $5, %esi
movb $1, %al
callq printf
leal 1(%r13), %eax
testl %r13d, %r13d
movl %eax, %r13d
jne .LBB3_11
.LBB3_5: # =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 160(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 112(%rsp) # 8-byte Spill
movl $5, %ebp
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_6 Depth=2
movq 120(%rsp), %r8
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpyAsync
.LBB3_18: # in Loop: Header=BB3_6 Depth=2
decl %ebp
je .LBB3_10
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movq 136(%rsp), %rdi
movq 152(%rsp), %rsi
movq 32(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=2
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movl $104857600, 92(%rsp) # imm = 0x6400000
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 92(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z14dummy_functionPij, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8: # in Loop: Header=BB3_6 Depth=2
callq hipDeviceSynchronize
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
movsd %xmm0, 168(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq 128(%rsp), %rdi
movq 96(%rsp), %rsi
testl %r13d, %r13d
je .LBB3_12
# %bb.9: # in Loop: Header=BB3_6 Depth=2
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpy
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_6 Depth=2
movq 32(%rsp), %r8
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpyAsync
.LBB3_13: # in Loop: Header=BB3_6 Depth=2
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 168(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 176(%rsp), %rdi
movq 184(%rsp), %rsi
movq 120(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 120(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14: # in Loop: Header=BB3_6 Depth=2
movq 144(%rsp), %rax
movq %rax, 80(%rsp)
movl $104857600, 92(%rsp) # imm = 0x6400000
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 92(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z14dummy_functionPij, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15: # in Loop: Header=BB3_6 Depth=2
callq hipDeviceSynchronize
movq 192(%rsp), %rdi
movq 144(%rsp), %rsi
testl %r13d, %r13d
je .LBB3_17
# %bb.16: # in Loop: Header=BB3_6 Depth=2
movl $419430400, %edx # imm = 0x19000000
movl $2, %ecx
callq hipMemcpy
jmp .LBB3_18
.LBB3_11:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7runTestv, .Lfunc_end3-_Z7runTestv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z7runTestv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14dummy_functionPij, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i = %d, expected %d, got %d.\n"
.size .L.str, 30
.type _Z14dummy_functionPij,@object # @_Z14dummy_functionPij
.section .rodata,"a",@progbits
.globl _Z14dummy_functionPij
.p2align 3, 0x0
_Z14dummy_functionPij:
.quad _Z29__device_stub__dummy_functionPij
.size _Z14dummy_functionPij, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Big Chunk of memory allocated on host & device = %d\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Small Chunk of memory allocated on host & device = %d\n"
.size .L.str.3, 55
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time for kernel call = %f\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "time for memcopy D-H = %f\n"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "time for one iteration = %f\n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "(A)sync call took %f\n"
.size .L.str.7, 22
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d iterations: time for ASYNC calls = %f\n"
.size .L.str.8, 42
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d iterations: time for SYNC calls = %f\n"
.size .L.str.9, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14dummy_functionPij"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running on a 64-bit platform!"
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__dummy_functionPij
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14dummy_functionPij
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,int var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
for (int i=0; i < var_1; ++i) {
if (comp > (var_2 * (var_3 - (+1.8532E-43f / +1.9626E14f * (+1.7886E-37f * var_4))))) {
if (comp >= (var_5 * (var_6 - var_7))) {
comp += (-0.0f - sinhf((-0.0f / var_9 + floorf(+1.5832E-42f))));
float tmp_1 = -1.1252E-15f;
float tmp_2 = -1.3006E-24f;
comp += tmp_2 - tmp_1 - sinhf((-0.0f - (var_10 / var_11 + (var_12 / +1.1462E34f + var_13))));
if (comp >= atanf(+1.0472E-42f)) {
float tmp_3 = -1.4667E36f;
comp += tmp_3 + (var_14 + (var_15 * var_16 * var_17));
}
for (int i=0; i < var_8; ++i) {
comp = log10f(+1.2622E-35f);
}
if (comp == atan2f(floorf(+1.8171E-8f), (-1.3632E-43f / var_18 - (+0.0f - +1.9495E-41f)))) {
comp = (-1.3993E25f / (+1.0080E-42f * var_19 + var_20));
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
int tmp_9 = atoi(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_001aa209_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff
.type _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff, @function
_Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movl %esi, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 360(%rsp), %rax
movq %rax, 248(%rsp)
leaq 368(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
leaq 384(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 312
pushq 56(%rsp)
.cfi_def_cfa_offset 320
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiffffffiffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff, .-_Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff
.globl _Z7computefiffffffiffffffffffff
.type _Z7computefiffffffiffffffffffff, @function
_Z7computefiffffffiffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss 192(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiffffffiffffffffffff, .-_Z7computefiffffffiffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $192, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 72(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 152(%rsp), %xmm0
subq $96, %rsp
.cfi_def_cfa_offset 320
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 192(%rsp), %xmm7
movl %ebp, %esi
pxor %xmm6, %xmm6
cvtsd2ss 200(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 208(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 216(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 224(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 232(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movl %r12d, %edi
call _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff
addq $96, %rsp
.cfi_def_cfa_offset 224
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiffffffiffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiffffffiffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.