system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernelGetPhi3(const int N, double *T, double *q)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
{
T[i] = q[i] * q[i] * q[i];
}
} | .file "tmpxft_0011b39f_00000000-6_kernelGetPhi3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_
.type _Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_, @function
_Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernelGetPhi3iPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_, .-_Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_
.globl _Z13kernelGetPhi3iPdS_
.type _Z13kernelGetPhi3iPdS_, @function
_Z13kernelGetPhi3iPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernelGetPhi3iPdS_, .-_Z13kernelGetPhi3iPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kernelGetPhi3iPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernelGetPhi3iPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernelGetPhi3(const int N, double *T, double *q)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
{
T[i] = q[i] * q[i] * q[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelGetPhi3(const int N, double *T, double *q)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
{
T[i] = q[i] * q[i] * q[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelGetPhi3(const int N, double *T, double *q)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
{
T[i] = q[i] * q[i] * q[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernelGetPhi3iPdS_
.globl _Z13kernelGetPhi3iPdS_
.p2align 8
.type _Z13kernelGetPhi3iPdS_,@function
_Z13kernelGetPhi3iPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernelGetPhi3iPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernelGetPhi3iPdS_, .Lfunc_end0-_Z13kernelGetPhi3iPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernelGetPhi3iPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernelGetPhi3iPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelGetPhi3(const int N, double *T, double *q)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
{
T[i] = q[i] * q[i] * q[i];
}
} | .text
.file "kernelGetPhi3.hip"
.globl _Z28__device_stub__kernelGetPhi3iPdS_ # -- Begin function _Z28__device_stub__kernelGetPhi3iPdS_
.p2align 4, 0x90
.type _Z28__device_stub__kernelGetPhi3iPdS_,@function
_Z28__device_stub__kernelGetPhi3iPdS_: # @_Z28__device_stub__kernelGetPhi3iPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernelGetPhi3iPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__kernelGetPhi3iPdS_, .Lfunc_end0-_Z28__device_stub__kernelGetPhi3iPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernelGetPhi3iPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernelGetPhi3iPdS_,@object # @_Z13kernelGetPhi3iPdS_
.section .rodata,"a",@progbits
.globl _Z13kernelGetPhi3iPdS_
.p2align 3, 0x0
_Z13kernelGetPhi3iPdS_:
.quad _Z28__device_stub__kernelGetPhi3iPdS_
.size _Z13kernelGetPhi3iPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernelGetPhi3iPdS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernelGetPhi3iPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernelGetPhi3iPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13kernelGetPhi3iPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ DMUL R4, R2, R2 ; /* 0x0000000202047228 */
/* 0x004e0c0000000000 */
/*00c0*/ DMUL R4, R2, R4 ; /* 0x0000000402047228 */
/* 0x001e0e0000000000 */
/*00d0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernelGetPhi3iPdS_
.globl _Z13kernelGetPhi3iPdS_
.p2align 8
.type _Z13kernelGetPhi3iPdS_,@function
_Z13kernelGetPhi3iPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernelGetPhi3iPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernelGetPhi3iPdS_, .Lfunc_end0-_Z13kernelGetPhi3iPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernelGetPhi3iPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernelGetPhi3iPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011b39f_00000000-6_kernelGetPhi3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_
.type _Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_, @function
_Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernelGetPhi3iPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_, .-_Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_
.globl _Z13kernelGetPhi3iPdS_
.type _Z13kernelGetPhi3iPdS_, @function
_Z13kernelGetPhi3iPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13kernelGetPhi3iPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernelGetPhi3iPdS_, .-_Z13kernelGetPhi3iPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kernelGetPhi3iPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernelGetPhi3iPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelGetPhi3.hip"
.globl _Z28__device_stub__kernelGetPhi3iPdS_ # -- Begin function _Z28__device_stub__kernelGetPhi3iPdS_
.p2align 4, 0x90
.type _Z28__device_stub__kernelGetPhi3iPdS_,@function
_Z28__device_stub__kernelGetPhi3iPdS_: # @_Z28__device_stub__kernelGetPhi3iPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernelGetPhi3iPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__kernelGetPhi3iPdS_, .Lfunc_end0-_Z28__device_stub__kernelGetPhi3iPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernelGetPhi3iPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernelGetPhi3iPdS_,@object # @_Z13kernelGetPhi3iPdS_
.section .rodata,"a",@progbits
.globl _Z13kernelGetPhi3iPdS_
.p2align 3, 0x0
_Z13kernelGetPhi3iPdS_:
.quad _Z28__device_stub__kernelGetPhi3iPdS_
.size _Z13kernelGetPhi3iPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernelGetPhi3iPdS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernelGetPhi3iPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernelGetPhi3iPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
// Always remember to add these 3 header files
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
// Create and allocate space for a random vector of size n where each element is in the range of 0-49
int* genRandVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genRandVec(int n) fails.\n");
exit(1);
}
for (int i = 0; i < n; i++) {
vec[i] = rand() % 50;
}
return vec;
}
// Create and allocate space for an empty vector of size n
int* genEmptyVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genEmptyVec(int n) fails.\n");
exit(1);
}
return vec;
}
void printVec(int* vec, int n) {
for (int i = 0; i < n; i++) {
printf("Element %d is : %d\n", i, vec[i]);
}
}
__global__
void vecAddKernel(int* v1, int* v2, int* v3, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
v3[i] = v1[i] + v2[i];
}
}
void vecAdd(int* v1, int* v2, int* v3, int n) {
int size = n * sizeof(int);
int* d_v1, *d_v2, *d_v3;
cudaMalloc((void**) &d_v1, size);
cudaMemcpy(d_v1, v1, size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_v2, size);
cudaMemcpy(d_v2, v2, size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_v3, size);
cudaMemcpy(d_v3, v3, size, cudaMemcpyHostToDevice);
// Lauch kernel here
vecAddKernel <<<ceil(n / 256.0), 256>>>(d_v1, d_v2, d_v3, n);
cudaMemcpy(v3, d_v3, size, cudaMemcpyDeviceToHost);
cudaFree(d_v1);
cudaFree(d_v2);
cudaFree(d_v3);
}
int main() {
int length = 5;
int* v1 = genRandVec(length);
int* v2 = genRandVec(length);
int* v3 = genEmptyVec(length);
vecAdd(v1, v2, v3, length);
// Print out content of v1
printf("Elements of v1 are: \n");
printVec(v1, length);
printf("\n");
// Print out content of v2
printf("Elements of v2 are: \n");
printVec(v2, length);
printf("\n");
// Print out content of v3
printf("Elements of v3 are: \n");
printVec(v3, length);
printf("\n");
free(v1);
free(v2);
free(v3);
return 0;
} | code for sm_80
Function : _Z12vecAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
// Always remember to add these 3 header files
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
// Create and allocate space for a random vector of size n where each element is in the range of 0-49
int* genRandVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genRandVec(int n) fails.\n");
exit(1);
}
for (int i = 0; i < n; i++) {
vec[i] = rand() % 50;
}
return vec;
}
// Create and allocate space for an empty vector of size n
int* genEmptyVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genEmptyVec(int n) fails.\n");
exit(1);
}
return vec;
}
void printVec(int* vec, int n) {
for (int i = 0; i < n; i++) {
printf("Element %d is : %d\n", i, vec[i]);
}
}
__global__
void vecAddKernel(int* v1, int* v2, int* v3, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
v3[i] = v1[i] + v2[i];
}
}
void vecAdd(int* v1, int* v2, int* v3, int n) {
int size = n * sizeof(int);
int* d_v1, *d_v2, *d_v3;
cudaMalloc((void**) &d_v1, size);
cudaMemcpy(d_v1, v1, size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_v2, size);
cudaMemcpy(d_v2, v2, size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_v3, size);
cudaMemcpy(d_v3, v3, size, cudaMemcpyHostToDevice);
// Lauch kernel here
vecAddKernel <<<ceil(n / 256.0), 256>>>(d_v1, d_v2, d_v3, n);
cudaMemcpy(v3, d_v3, size, cudaMemcpyDeviceToHost);
cudaFree(d_v1);
cudaFree(d_v2);
cudaFree(d_v3);
}
int main() {
int length = 5;
int* v1 = genRandVec(length);
int* v2 = genRandVec(length);
int* v3 = genEmptyVec(length);
vecAdd(v1, v2, v3, length);
// Print out content of v1
printf("Elements of v1 are: \n");
printVec(v1, length);
printf("\n");
// Print out content of v2
printf("Elements of v2 are: \n");
printVec(v2, length);
printf("\n");
// Print out content of v3
printf("Elements of v3 are: \n");
printVec(v3, length);
printf("\n");
free(v1);
free(v2);
free(v3);
return 0;
} | .file "tmpxft_00066704_00000000-6_vectorAddition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Malloc for vector in genRandVec(int n) fails.\n"
.text
.globl _Z10genRandVeci
.type _Z10genRandVeci, @function
_Z10genRandVeci:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r13d
movslq %edi, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
testq %rax, %rax
je .L4
movq %rax, %r12
movq %rax, %rbx
addq %rax, %rbp
testl %r13d, %r13d
jle .L3
.L7:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $50, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L7
.L3:
movq %r12, %rax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10genRandVeci, .-_Z10genRandVeci
.section .rodata.str1.8
.align 8
.LC1:
.string "Malloc for vector in genEmptyVec(int n) fails.\n"
.text
.globl _Z11genEmptyVeci
.type _Z11genEmptyVeci, @function
_Z11genEmptyVeci:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
testq %rax, %rax
je .L14
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z11genEmptyVeci, .-_Z11genEmptyVeci
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Element %d is : %d\n"
.text
.globl _Z8printVecPii
.type _Z8printVecPii, @function
_Z8printVecPii:
.LFB3671:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L20
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movslq %esi, %rbp
movl $0, %ebx
leaq .LC2(%rip), %r13
.L17:
movl (%r12,%rbx,4), %ecx
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L17
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3671:
.size _Z8printVecPii, .-_Z8printVecPii
.globl _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
.type _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i:
.LFB3698:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i, .-_Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
.globl _Z12vecAddKernelPiS_S_i
.type _Z12vecAddKernelPiS_S_i, @function
_Z12vecAddKernelPiS_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z12vecAddKernelPiS_S_i, .-_Z12vecAddKernelPiS_S_i
.globl _Z6vecAddPiS_S_i
.type _Z6vecAddPiS_S_i, @function
_Z6vecAddPiS_S_i:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC3(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L32
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L32:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L33:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
jmp .L33
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z6vecAddPiS_S_i, .-_Z6vecAddPiS_S_i
.section .rodata.str1.1
.LC8:
.string "Elements of v1 are: \n"
.LC9:
.string "\n"
.LC10:
.string "Elements of v2 are: \n"
.LC11:
.string "Elements of v3 are: \n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $5, %edi
call _Z10genRandVeci
movq %rax, %r12
movl $5, %edi
call _Z10genRandVeci
movq %rax, %rbp
movl $5, %edi
call _Z11genEmptyVeci
movq %rax, %rbx
movl $5, %ecx
movq %rax, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z6vecAddPiS_S_i
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %esi
movq %r12, %rdi
call _Z8printVecPii
leaq .LC9(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %esi
movq %rbp, %rdi
call _Z8printVecPii
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %esi
movq %rbx, %rdi
call _Z8printVecPii
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12vecAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1064304640
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
// Always remember to add these 3 header files
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
// Create and allocate space for a random vector of size n where each element is in the range of 0-49
int* genRandVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genRandVec(int n) fails.\n");
exit(1);
}
for (int i = 0; i < n; i++) {
vec[i] = rand() % 50;
}
return vec;
}
// Create and allocate space for an empty vector of size n
int* genEmptyVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genEmptyVec(int n) fails.\n");
exit(1);
}
return vec;
}
void printVec(int* vec, int n) {
for (int i = 0; i < n; i++) {
printf("Element %d is : %d\n", i, vec[i]);
}
}
__global__
void vecAddKernel(int* v1, int* v2, int* v3, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
v3[i] = v1[i] + v2[i];
}
}
void vecAdd(int* v1, int* v2, int* v3, int n) {
int size = n * sizeof(int);
int* d_v1, *d_v2, *d_v3;
cudaMalloc((void**) &d_v1, size);
cudaMemcpy(d_v1, v1, size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_v2, size);
cudaMemcpy(d_v2, v2, size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_v3, size);
cudaMemcpy(d_v3, v3, size, cudaMemcpyHostToDevice);
// Lauch kernel here
vecAddKernel <<<ceil(n / 256.0), 256>>>(d_v1, d_v2, d_v3, n);
cudaMemcpy(v3, d_v3, size, cudaMemcpyDeviceToHost);
cudaFree(d_v1);
cudaFree(d_v2);
cudaFree(d_v3);
}
int main() {
int length = 5;
int* v1 = genRandVec(length);
int* v2 = genRandVec(length);
int* v3 = genEmptyVec(length);
vecAdd(v1, v2, v3, length);
// Print out content of v1
printf("Elements of v1 are: \n");
printVec(v1, length);
printf("\n");
// Print out content of v2
printf("Elements of v2 are: \n");
printVec(v2, length);
printf("\n");
// Print out content of v3
printf("Elements of v3 are: \n");
printVec(v3, length);
printf("\n");
free(v1);
free(v2);
free(v3);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
// Always remember to add these 3 header files
#include <hip/hip_runtime.h>
// Create and allocate space for a random vector of size n where each element is in the range of 0-49
int* genRandVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genRandVec(int n) fails.\n");
exit(1);
}
for (int i = 0; i < n; i++) {
vec[i] = rand() % 50;
}
return vec;
}
// Create and allocate space for an empty vector of size n
int* genEmptyVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genEmptyVec(int n) fails.\n");
exit(1);
}
return vec;
}
void printVec(int* vec, int n) {
for (int i = 0; i < n; i++) {
printf("Element %d is : %d\n", i, vec[i]);
}
}
__global__
void vecAddKernel(int* v1, int* v2, int* v3, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
v3[i] = v1[i] + v2[i];
}
}
void vecAdd(int* v1, int* v2, int* v3, int n) {
int size = n * sizeof(int);
int* d_v1, *d_v2, *d_v3;
hipMalloc((void**) &d_v1, size);
hipMemcpy(d_v1, v1, size, hipMemcpyHostToDevice);
hipMalloc((void**) &d_v2, size);
hipMemcpy(d_v2, v2, size, hipMemcpyHostToDevice);
hipMalloc((void**) &d_v3, size);
hipMemcpy(d_v3, v3, size, hipMemcpyHostToDevice);
// Lauch kernel here
vecAddKernel <<<ceil(n / 256.0), 256>>>(d_v1, d_v2, d_v3, n);
hipMemcpy(v3, d_v3, size, hipMemcpyDeviceToHost);
hipFree(d_v1);
hipFree(d_v2);
hipFree(d_v3);
}
int main() {
int length = 5;
int* v1 = genRandVec(length);
int* v2 = genRandVec(length);
int* v3 = genEmptyVec(length);
vecAdd(v1, v2, v3, length);
// Print out content of v1
printf("Elements of v1 are: \n");
printVec(v1, length);
printf("\n");
// Print out content of v2
printf("Elements of v2 are: \n");
printVec(v2, length);
printf("\n");
// Print out content of v3
printf("Elements of v3 are: \n");
printVec(v3, length);
printf("\n");
free(v1);
free(v2);
free(v3);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
// Always remember to add these 3 header files
#include <hip/hip_runtime.h>
// Create and allocate space for a random vector of size n where each element is in the range of 0-49
int* genRandVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genRandVec(int n) fails.\n");
exit(1);
}
for (int i = 0; i < n; i++) {
vec[i] = rand() % 50;
}
return vec;
}
// Create and allocate space for an empty vector of size n
int* genEmptyVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genEmptyVec(int n) fails.\n");
exit(1);
}
return vec;
}
void printVec(int* vec, int n) {
for (int i = 0; i < n; i++) {
printf("Element %d is : %d\n", i, vec[i]);
}
}
__global__
void vecAddKernel(int* v1, int* v2, int* v3, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
v3[i] = v1[i] + v2[i];
}
}
void vecAdd(int* v1, int* v2, int* v3, int n) {
int size = n * sizeof(int);
int* d_v1, *d_v2, *d_v3;
hipMalloc((void**) &d_v1, size);
hipMemcpy(d_v1, v1, size, hipMemcpyHostToDevice);
hipMalloc((void**) &d_v2, size);
hipMemcpy(d_v2, v2, size, hipMemcpyHostToDevice);
hipMalloc((void**) &d_v3, size);
hipMemcpy(d_v3, v3, size, hipMemcpyHostToDevice);
// Lauch kernel here
vecAddKernel <<<ceil(n / 256.0), 256>>>(d_v1, d_v2, d_v3, n);
hipMemcpy(v3, d_v3, size, hipMemcpyDeviceToHost);
hipFree(d_v1);
hipFree(d_v2);
hipFree(d_v3);
}
int main() {
int length = 5;
int* v1 = genRandVec(length);
int* v2 = genRandVec(length);
int* v3 = genEmptyVec(length);
vecAdd(v1, v2, v3, length);
// Print out content of v1
printf("Elements of v1 are: \n");
printVec(v1, length);
printf("\n");
// Print out content of v2
printf("Elements of v2 are: \n");
printVec(v2, length);
printf("\n");
// Print out content of v3
printf("Elements of v3 are: \n");
printVec(v3, length);
printf("\n");
free(v1);
free(v2);
free(v3);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPiS_S_i
.globl _Z12vecAddKernelPiS_S_i
.p2align 8
.type _Z12vecAddKernelPiS_S_i,@function
_Z12vecAddKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPiS_S_i, .Lfunc_end0-_Z12vecAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
// Always remember to add these 3 header files
#include <hip/hip_runtime.h>
// Create and allocate space for a random vector of size n where each element is in the range of 0-49
int* genRandVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genRandVec(int n) fails.\n");
exit(1);
}
for (int i = 0; i < n; i++) {
vec[i] = rand() % 50;
}
return vec;
}
// Create and allocate space for an empty vector of size n
int* genEmptyVec(int n) {
int* vec = (int*) malloc(n * sizeof(int));
if (vec == NULL) {
printf("Malloc for vector in genEmptyVec(int n) fails.\n");
exit(1);
}
return vec;
}
void printVec(int* vec, int n) {
for (int i = 0; i < n; i++) {
printf("Element %d is : %d\n", i, vec[i]);
}
}
__global__
void vecAddKernel(int* v1, int* v2, int* v3, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
v3[i] = v1[i] + v2[i];
}
}
void vecAdd(int* v1, int* v2, int* v3, int n) {
int size = n * sizeof(int);
int* d_v1, *d_v2, *d_v3;
hipMalloc((void**) &d_v1, size);
hipMemcpy(d_v1, v1, size, hipMemcpyHostToDevice);
hipMalloc((void**) &d_v2, size);
hipMemcpy(d_v2, v2, size, hipMemcpyHostToDevice);
hipMalloc((void**) &d_v3, size);
hipMemcpy(d_v3, v3, size, hipMemcpyHostToDevice);
// Lauch kernel here
vecAddKernel <<<ceil(n / 256.0), 256>>>(d_v1, d_v2, d_v3, n);
hipMemcpy(v3, d_v3, size, hipMemcpyDeviceToHost);
hipFree(d_v1);
hipFree(d_v2);
hipFree(d_v3);
}
int main() {
int length = 5;
int* v1 = genRandVec(length);
int* v2 = genRandVec(length);
int* v3 = genEmptyVec(length);
vecAdd(v1, v2, v3, length);
// Print out content of v1
printf("Elements of v1 are: \n");
printVec(v1, length);
printf("\n");
// Print out content of v2
printf("Elements of v2 are: \n");
printVec(v2, length);
printf("\n");
// Print out content of v3
printf("Elements of v3 are: \n");
printVec(v3, length);
printf("\n");
free(v1);
free(v2);
free(v3);
return 0;
} | .text
.file "vectorAddition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10genRandVeci # -- Begin function _Z10genRandVeci
.p2align 4, 0x90
.type _Z10genRandVeci,@function
_Z10genRandVeci: # @_Z10genRandVeci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movslq %edi, %rdi
shlq $2, %rdi
callq malloc
testq %rax, %rax
je .LBB0_5
# %bb.1: # %.preheader
movq %rax, %rbx
testl %ebp, %ebp
jle .LBB0_4
# %bb.2: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_3
.LBB0_4: # %._crit_edge
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 48
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10genRandVeci, .Lfunc_end0-_Z10genRandVeci
.cfi_endproc
# -- End function
.globl _Z11genEmptyVeci # -- Begin function _Z11genEmptyVeci
.p2align 4, 0x90
.type _Z11genEmptyVeci,@function
_Z11genEmptyVeci: # @_Z11genEmptyVeci
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movslq %edi, %rdi
shlq $2, %rdi
callq malloc
testq %rax, %rax
je .LBB1_2
# %bb.1:
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 16
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z11genEmptyVeci, .Lfunc_end1-_Z11genEmptyVeci
.cfi_endproc
# -- End function
.globl _Z8printVecPii # -- Begin function _Z8printVecPii
.p2align 4, 0x90
.type _Z8printVecPii,@function
_Z8printVecPii: # @_Z8printVecPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z8printVecPii, .Lfunc_end2-_Z8printVecPii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vecAddKernelPiS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPiS_S_i,@function
_Z27__device_stub__vecAddKernelPiS_S_i: # @_Z27__device_stub__vecAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z27__device_stub__vecAddKernelPiS_S_i, .Lfunc_end3-_Z27__device_stub__vecAddKernelPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6vecAddPiS_S_i
.LCPI4_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z6vecAddPiS_S_i
.p2align 4, 0x90
.type _Z6vecAddPiS_S_i,@function
_Z6vecAddPiS_S_i: # @_Z6vecAddPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2sd %r15d, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z6vecAddPiS_S_i, .Lfunc_end4-_Z6vecAddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $20, %edi
callq malloc
testq %rax, %rax
je .LBB5_8
# %bb.1: # %.lr.ph.i.preheader
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $5, %r14
jne .LBB5_2
# %bb.3: # %_Z10genRandVeci.exit
movl $20, %edi
callq malloc
testq %rax, %rax
je .LBB5_8
# %bb.4: # %.lr.ph.i20.preheader
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_5: # %.lr.ph.i20
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $5, %r15
jne .LBB5_5
# %bb.6: # %_Z10genRandVeci.exit25
movl $20, %edi
callq malloc
testq %rax, %rax
je .LBB5_7
# %bb.10: # %_Z11genEmptyVeci.exit
movq %rax, %r15
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
movl $5, %ecx
callq _Z6vecAddPiS_S_i
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_11: # %.lr.ph.i27
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $5, %r12
jne .LBB5_11
# %bb.12: # %_Z8printVecPii.exit
movl $10, %edi
callq putchar@PLT
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_13: # %.lr.ph.i31
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $5, %r12
jne .LBB5_13
# %bb.14: # %_Z8printVecPii.exit35
movl $10, %edi
callq putchar@PLT
movl $.Lstr.4, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_15: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $5, %r12
jne .LBB5_15
# %bb.16: # %_Z8printVecPii.exit40
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_8:
.cfi_def_cfa_offset 48
movl $.Lstr, %edi
jmp .LBB5_9
.LBB5_7:
movl $.Lstr.1, %edi
.LBB5_9:
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Element %d is : %d\n"
.size .L.str.2, 20
.type _Z12vecAddKernelPiS_S_i,@object # @_Z12vecAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPiS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPiS_S_i:
.quad _Z27__device_stub__vecAddKernelPiS_S_i
.size _Z12vecAddKernelPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12vecAddKernelPiS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Malloc for vector in genRandVec(int n) fails."
.size .Lstr, 46
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Malloc for vector in genEmptyVec(int n) fails."
.size .Lstr.1, 47
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Elements of v1 are: "
.size .Lstr.2, 21
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Elements of v2 are: "
.size .Lstr.3, 21
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Elements of v3 are: "
.size .Lstr.4, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12vecAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPiS_S_i
.globl _Z12vecAddKernelPiS_S_i
.p2align 8
.type _Z12vecAddKernelPiS_S_i,@function
_Z12vecAddKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPiS_S_i, .Lfunc_end0-_Z12vecAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00066704_00000000-6_vectorAddition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Malloc for vector in genRandVec(int n) fails.\n"
.text
.globl _Z10genRandVeci
.type _Z10genRandVeci, @function
_Z10genRandVeci:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r13d
movslq %edi, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
testq %rax, %rax
je .L4
movq %rax, %r12
movq %rax, %rbx
addq %rax, %rbp
testl %r13d, %r13d
jle .L3
.L7:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $50, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L7
.L3:
movq %r12, %rax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10genRandVeci, .-_Z10genRandVeci
.section .rodata.str1.8
.align 8
.LC1:
.string "Malloc for vector in genEmptyVec(int n) fails.\n"
.text
.globl _Z11genEmptyVeci
.type _Z11genEmptyVeci, @function
_Z11genEmptyVeci:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
testq %rax, %rax
je .L14
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z11genEmptyVeci, .-_Z11genEmptyVeci
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Element %d is : %d\n"
.text
.globl _Z8printVecPii
.type _Z8printVecPii, @function
_Z8printVecPii:
.LFB3671:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L20
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movslq %esi, %rbp
movl $0, %ebx
leaq .LC2(%rip), %r13
.L17:
movl (%r12,%rbx,4), %ecx
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L17
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3671:
.size _Z8printVecPii, .-_Z8printVecPii
.globl _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
.type _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i:
.LFB3698:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i, .-_Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
.globl _Z12vecAddKernelPiS_S_i
.type _Z12vecAddKernelPiS_S_i, @function
_Z12vecAddKernelPiS_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z12vecAddKernelPiS_S_i, .-_Z12vecAddKernelPiS_S_i
.globl _Z6vecAddPiS_S_i
.type _Z6vecAddPiS_S_i, @function
_Z6vecAddPiS_S_i:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC3(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L32
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L32:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L33:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
jmp .L33
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z6vecAddPiS_S_i, .-_Z6vecAddPiS_S_i
.section .rodata.str1.1
.LC8:
.string "Elements of v1 are: \n"
.LC9:
.string "\n"
.LC10:
.string "Elements of v2 are: \n"
.LC11:
.string "Elements of v3 are: \n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $5, %edi
call _Z10genRandVeci
movq %rax, %r12
movl $5, %edi
call _Z10genRandVeci
movq %rax, %rbp
movl $5, %edi
call _Z11genEmptyVeci
movq %rax, %rbx
movl $5, %ecx
movq %rax, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z6vecAddPiS_S_i
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %esi
movq %r12, %rdi
call _Z8printVecPii
leaq .LC9(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %esi
movq %rbp, %rdi
call _Z8printVecPii
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %esi
movq %rbx, %rdi
call _Z8printVecPii
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12vecAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1064304640
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAddition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10genRandVeci # -- Begin function _Z10genRandVeci
.p2align 4, 0x90
.type _Z10genRandVeci,@function
_Z10genRandVeci: # @_Z10genRandVeci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movslq %edi, %rdi
shlq $2, %rdi
callq malloc
testq %rax, %rax
je .LBB0_5
# %bb.1: # %.preheader
movq %rax, %rbx
testl %ebp, %ebp
jle .LBB0_4
# %bb.2: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_3
.LBB0_4: # %._crit_edge
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 48
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10genRandVeci, .Lfunc_end0-_Z10genRandVeci
.cfi_endproc
# -- End function
.globl _Z11genEmptyVeci # -- Begin function _Z11genEmptyVeci
.p2align 4, 0x90
.type _Z11genEmptyVeci,@function
_Z11genEmptyVeci: # @_Z11genEmptyVeci
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movslq %edi, %rdi
shlq $2, %rdi
callq malloc
testq %rax, %rax
je .LBB1_2
# %bb.1:
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 16
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z11genEmptyVeci, .Lfunc_end1-_Z11genEmptyVeci
.cfi_endproc
# -- End function
.globl _Z8printVecPii # -- Begin function _Z8printVecPii
.p2align 4, 0x90
.type _Z8printVecPii,@function
_Z8printVecPii: # @_Z8printVecPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z8printVecPii, .Lfunc_end2-_Z8printVecPii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vecAddKernelPiS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPiS_S_i,@function
_Z27__device_stub__vecAddKernelPiS_S_i: # @_Z27__device_stub__vecAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z27__device_stub__vecAddKernelPiS_S_i, .Lfunc_end3-_Z27__device_stub__vecAddKernelPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6vecAddPiS_S_i
.LCPI4_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z6vecAddPiS_S_i
.p2align 4, 0x90
.type _Z6vecAddPiS_S_i,@function
_Z6vecAddPiS_S_i: # @_Z6vecAddPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2sd %r15d, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z6vecAddPiS_S_i, .Lfunc_end4-_Z6vecAddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $20, %edi
callq malloc
testq %rax, %rax
je .LBB5_8
# %bb.1: # %.lr.ph.i.preheader
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $5, %r14
jne .LBB5_2
# %bb.3: # %_Z10genRandVeci.exit
movl $20, %edi
callq malloc
testq %rax, %rax
je .LBB5_8
# %bb.4: # %.lr.ph.i20.preheader
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_5: # %.lr.ph.i20
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $5, %r15
jne .LBB5_5
# %bb.6: # %_Z10genRandVeci.exit25
movl $20, %edi
callq malloc
testq %rax, %rax
je .LBB5_7
# %bb.10: # %_Z11genEmptyVeci.exit
movq %rax, %r15
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
movl $5, %ecx
callq _Z6vecAddPiS_S_i
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_11: # %.lr.ph.i27
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $5, %r12
jne .LBB5_11
# %bb.12: # %_Z8printVecPii.exit
movl $10, %edi
callq putchar@PLT
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_13: # %.lr.ph.i31
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $5, %r12
jne .LBB5_13
# %bb.14: # %_Z8printVecPii.exit35
movl $10, %edi
callq putchar@PLT
movl $.Lstr.4, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_15: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $5, %r12
jne .LBB5_15
# %bb.16: # %_Z8printVecPii.exit40
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_8:
.cfi_def_cfa_offset 48
movl $.Lstr, %edi
jmp .LBB5_9
.LBB5_7:
movl $.Lstr.1, %edi
.LBB5_9:
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Element %d is : %d\n"
.size .L.str.2, 20
.type _Z12vecAddKernelPiS_S_i,@object # @_Z12vecAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPiS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPiS_S_i:
.quad _Z27__device_stub__vecAddKernelPiS_S_i
.size _Z12vecAddKernelPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12vecAddKernelPiS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Malloc for vector in genRandVec(int n) fails."
.size .Lstr, 46
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Malloc for vector in genEmptyVec(int n) fails."
.size .Lstr.1, 47
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Elements of v1 are: "
.size .Lstr.2, 21
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Elements of v2 are: "
.size .Lstr.3, 21
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Elements of v3 are: "
.size .Lstr.4, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdio>
#include <cassert>
__global__ void array_manipulation_kernel(int* a, int n) {
unsigned int index;
index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
a[index] *= 2;
}
class ArrayManipulation {
public:
int *array;
int arrayLength; // Number of elements in the array
size_t arraySize; // Size of the array in bytes
explicit ArrayManipulation(int length);
void run(size_t numGrids, size_t numThreads);
void DisplayArray() const;
private:
void assertResult() const;
};
ArrayManipulation::ArrayManipulation(int length) {
this->arrayLength = length;
this->arraySize = length * sizeof(int);
cudaMallocManaged(&array, arraySize);
for(int i = 0; i < length; i++)
this->array[i] = i;
}
void ArrayManipulation::DisplayArray() const {
for(int i = 0; i < this->arrayLength; i++)
printf("Index %d: %d\n", i, this->array[i]);
}
void ArrayManipulation::run(size_t numGrids, size_t numThreads) {
int deviceId = cudaGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", cudaCpuDeviceId);
array_manipulation_kernel<<<numGrids, numThreads>>>(array, arraySize);
cudaDeviceSynchronize();
this->assertResult();
}
void ArrayManipulation::assertResult() const {
for(int i = 0; i < arrayLength; i++)
assert (array[i] == i * 2);
}
int main() {
int arrayLength = 10;
ArrayManipulation program(arrayLength);
size_t numThreads = 256;
size_t numGrids = (arrayLength + numThreads - 1) / numThreads;
program.run(numGrids, numThreads);
program.DisplayArray();
} | code for sm_80
Function : _Z25array_manipulation_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdio>
#include <cassert>
__global__ void array_manipulation_kernel(int* a, int n) {
unsigned int index;
index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
a[index] *= 2;
}
class ArrayManipulation {
public:
int *array;
int arrayLength; // Number of elements in the array
size_t arraySize; // Size of the array in bytes
explicit ArrayManipulation(int length);
void run(size_t numGrids, size_t numThreads);
void DisplayArray() const;
private:
void assertResult() const;
};
ArrayManipulation::ArrayManipulation(int length) {
this->arrayLength = length;
this->arraySize = length * sizeof(int);
cudaMallocManaged(&array, arraySize);
for(int i = 0; i < length; i++)
this->array[i] = i;
}
void ArrayManipulation::DisplayArray() const {
for(int i = 0; i < this->arrayLength; i++)
printf("Index %d: %d\n", i, this->array[i]);
}
void ArrayManipulation::run(size_t numGrids, size_t numThreads) {
int deviceId = cudaGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", cudaCpuDeviceId);
array_manipulation_kernel<<<numGrids, numThreads>>>(array, arraySize);
cudaDeviceSynchronize();
this->assertResult();
}
void ArrayManipulation::assertResult() const {
for(int i = 0; i < arrayLength; i++)
assert (array[i] == i * 2);
}
int main() {
int arrayLength = 10;
ArrayManipulation program(arrayLength);
size_t numThreads = 256;
size_t numGrids = (arrayLength + numThreads - 1) / numThreads;
program.run(numGrids, numThreads);
program.DisplayArray();
} | .file "tmpxft_00197538_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN17ArrayManipulationC2Ei
.type _ZN17ArrayManipulationC2Ei, @function
_ZN17ArrayManipulationC2Ei:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %r12d
movl %esi, 8(%rdi)
movslq %esi, %rbp
leaq 0(,%rbp,4), %rsi
movq %rsi, 16(%rdi)
movl $1, %edx
call cudaMallocManaged@PLT
testl %r12d, %r12d
jle .L3
movl $0, %eax
.L5:
movq (%rbx), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq %rax, %rbp
jne .L5
.L3:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZN17ArrayManipulationC2Ei, .-_ZN17ArrayManipulationC2Ei
.globl _ZN17ArrayManipulationC1Ei
.set _ZN17ArrayManipulationC1Ei,_ZN17ArrayManipulationC2Ei
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Index %d: %d\n"
.text
.align 2
.globl _ZNK17ArrayManipulation12DisplayArrayEv
.type _ZNK17ArrayManipulation12DisplayArrayEv, @function
_ZNK17ArrayManipulation12DisplayArrayEv:
.LFB2060:
.cfi_startproc
endbr64
cmpl $0, 8(%rdi)
jle .L13
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl $0, %ebx
leaq .LC0(%rip), %r12
.L10:
movq 0(%rbp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 8(%rbp)
jg .L10
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2060:
.size _ZNK17ArrayManipulation12DisplayArrayEv, .-_ZNK17ArrayManipulation12DisplayArrayEv
.align 2
.globl _ZNK17ArrayManipulation12assertResultEv
.type _ZNK17ArrayManipulation12assertResultEv, @function
_ZNK17ArrayManipulation12assertResultEv:
.LFB2062:
.cfi_startproc
endbr64
movl 8(%rdi), %edx
testl %edx, %edx
jle .L16
movl $0, %eax
.L18:
addl $1, %eax
cmpl %edx, %eax
jne .L18
.L16:
ret
.cfi_endproc
.LFE2062:
.size _ZNK17ArrayManipulation12assertResultEv, .-_ZNK17ArrayManipulation12assertResultEv
.globl _Z46__device_stub__Z25array_manipulation_kernelPiiPii
.type _Z46__device_stub__Z25array_manipulation_kernelPiiPii, @function
_Z46__device_stub__Z25array_manipulation_kernelPiiPii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25array_manipulation_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z46__device_stub__Z25array_manipulation_kernelPiiPii, .-_Z46__device_stub__Z25array_manipulation_kernelPiiPii
.globl _Z25array_manipulation_kernelPii
.type _Z25array_manipulation_kernelPii, @function
_Z25array_manipulation_kernelPii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z25array_manipulation_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z25array_manipulation_kernelPii, .-_Z25array_manipulation_kernelPii
.section .rodata.str1.1
.LC1:
.string "GPU Device ID: %d\n"
.LC2:
.string "CPU Device ID: %d\n\n"
.text
.align 2
.globl _ZN17ArrayManipulation3runEmm
.type _ZN17ArrayManipulation3runEmm, @function
_ZN17ArrayManipulation3runEmm:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %rbx
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
movl %eax, %edx
movl %eax, 12(%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, 28(%rsp)
movl $1, 32(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L29:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq (%r12), %rdi
movl 16(%r12), %esi
call _Z46__device_stub__Z25array_manipulation_kernelPiiPii
jmp .L29
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _ZN17ArrayManipulation3runEmm, .-_ZN17ArrayManipulation3runEmm
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $10, %esi
movq %rbx, %rdi
call _ZN17ArrayManipulationC1Ei
movl $256, %edx
movl $1, %esi
movq %rbx, %rdi
call _ZN17ArrayManipulation3runEmm
movq %rbx, %rdi
call _ZNK17ArrayManipulation12DisplayArrayEv
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z25array_manipulation_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z25array_manipulation_kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdio>
#include <cassert>
__global__ void array_manipulation_kernel(int* a, int n) {
unsigned int index;
index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
a[index] *= 2;
}
class ArrayManipulation {
public:
int *array;
int arrayLength; // Number of elements in the array
size_t arraySize; // Size of the array in bytes
explicit ArrayManipulation(int length);
void run(size_t numGrids, size_t numThreads);
void DisplayArray() const;
private:
void assertResult() const;
};
ArrayManipulation::ArrayManipulation(int length) {
this->arrayLength = length;
this->arraySize = length * sizeof(int);
cudaMallocManaged(&array, arraySize);
for(int i = 0; i < length; i++)
this->array[i] = i;
}
void ArrayManipulation::DisplayArray() const {
for(int i = 0; i < this->arrayLength; i++)
printf("Index %d: %d\n", i, this->array[i]);
}
void ArrayManipulation::run(size_t numGrids, size_t numThreads) {
int deviceId = cudaGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", cudaCpuDeviceId);
array_manipulation_kernel<<<numGrids, numThreads>>>(array, arraySize);
cudaDeviceSynchronize();
this->assertResult();
}
void ArrayManipulation::assertResult() const {
for(int i = 0; i < arrayLength; i++)
assert (array[i] == i * 2);
}
int main() {
int arrayLength = 10;
ArrayManipulation program(arrayLength);
size_t numThreads = 256;
size_t numGrids = (arrayLength + numThreads - 1) / numThreads;
program.run(numGrids, numThreads);
program.DisplayArray();
} | #include "hip/hip_runtime.h"
#include <cstdio>
#include <cassert>
__global__ void array_manipulation_kernel(int* a, int n) {
unsigned int index;
index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
a[index] *= 2;
}
class ArrayManipulation {
public:
int *array;
int arrayLength; // Number of elements in the array
size_t arraySize; // Size of the array in bytes
explicit ArrayManipulation(int length);
void run(size_t numGrids, size_t numThreads);
void DisplayArray() const;
private:
void assertResult() const;
};
ArrayManipulation::ArrayManipulation(int length) {
this->arrayLength = length;
this->arraySize = length * sizeof(int);
hipMallocManaged(&array, arraySize);
for(int i = 0; i < length; i++)
this->array[i] = i;
}
void ArrayManipulation::DisplayArray() const {
for(int i = 0; i < this->arrayLength; i++)
printf("Index %d: %d\n", i, this->array[i]);
}
void ArrayManipulation::run(size_t numGrids, size_t numThreads) {
int deviceId = hipGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", hipCpuDeviceId);
array_manipulation_kernel<<<numGrids, numThreads>>>(array, arraySize);
hipDeviceSynchronize();
this->assertResult();
}
void ArrayManipulation::assertResult() const {
for(int i = 0; i < arrayLength; i++)
assert (array[i] == i * 2);
}
int main() {
int arrayLength = 10;
ArrayManipulation program(arrayLength);
size_t numThreads = 256;
size_t numGrids = (arrayLength + numThreads - 1) / numThreads;
program.run(numGrids, numThreads);
program.DisplayArray();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <cstdio>
#include <cassert>
__global__ void array_manipulation_kernel(int* a, int n) {
unsigned int index;
index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
a[index] *= 2;
}
class ArrayManipulation {
public:
int *array;
int arrayLength; // Number of elements in the array
size_t arraySize; // Size of the array in bytes
explicit ArrayManipulation(int length);
void run(size_t numGrids, size_t numThreads);
void DisplayArray() const;
private:
void assertResult() const;
};
ArrayManipulation::ArrayManipulation(int length) {
this->arrayLength = length;
this->arraySize = length * sizeof(int);
hipMallocManaged(&array, arraySize);
for(int i = 0; i < length; i++)
this->array[i] = i;
}
void ArrayManipulation::DisplayArray() const {
for(int i = 0; i < this->arrayLength; i++)
printf("Index %d: %d\n", i, this->array[i]);
}
void ArrayManipulation::run(size_t numGrids, size_t numThreads) {
int deviceId = hipGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", hipCpuDeviceId);
array_manipulation_kernel<<<numGrids, numThreads>>>(array, arraySize);
hipDeviceSynchronize();
this->assertResult();
}
void ArrayManipulation::assertResult() const {
for(int i = 0; i < arrayLength; i++)
assert (array[i] == i * 2);
}
int main() {
int arrayLength = 10;
ArrayManipulation program(arrayLength);
size_t numThreads = 256;
size_t numGrids = (arrayLength + numThreads - 1) / numThreads;
program.run(numGrids, numThreads);
program.DisplayArray();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25array_manipulation_kernelPii
.globl _Z25array_manipulation_kernelPii
.p2align 8
.type _Z25array_manipulation_kernelPii,@function
_Z25array_manipulation_kernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25array_manipulation_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25array_manipulation_kernelPii, .Lfunc_end0-_Z25array_manipulation_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25array_manipulation_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25array_manipulation_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <cstdio>
#include <cassert>
__global__ void array_manipulation_kernel(int* a, int n) {
unsigned int index;
index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
a[index] *= 2;
}
class ArrayManipulation {
public:
int *array;
int arrayLength; // Number of elements in the array
size_t arraySize; // Size of the array in bytes
explicit ArrayManipulation(int length);
void run(size_t numGrids, size_t numThreads);
void DisplayArray() const;
private:
void assertResult() const;
};
ArrayManipulation::ArrayManipulation(int length) {
this->arrayLength = length;
this->arraySize = length * sizeof(int);
hipMallocManaged(&array, arraySize);
for(int i = 0; i < length; i++)
this->array[i] = i;
}
void ArrayManipulation::DisplayArray() const {
for(int i = 0; i < this->arrayLength; i++)
printf("Index %d: %d\n", i, this->array[i]);
}
void ArrayManipulation::run(size_t numGrids, size_t numThreads) {
int deviceId = hipGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", hipCpuDeviceId);
array_manipulation_kernel<<<numGrids, numThreads>>>(array, arraySize);
hipDeviceSynchronize();
this->assertResult();
}
void ArrayManipulation::assertResult() const {
for(int i = 0; i < arrayLength; i++)
assert (array[i] == i * 2);
}
int main() {
int arrayLength = 10;
ArrayManipulation program(arrayLength);
size_t numThreads = 256;
size_t numGrids = (arrayLength + numThreads - 1) / numThreads;
program.run(numGrids, numThreads);
program.DisplayArray();
} | .text
.file "main.hip"
.globl _Z40__device_stub__array_manipulation_kernelPii # -- Begin function _Z40__device_stub__array_manipulation_kernelPii
.p2align 4, 0x90
.type _Z40__device_stub__array_manipulation_kernelPii,@function
_Z40__device_stub__array_manipulation_kernelPii: # @_Z40__device_stub__array_manipulation_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25array_manipulation_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z40__device_stub__array_manipulation_kernelPii, .Lfunc_end0-_Z40__device_stub__array_manipulation_kernelPii
.cfi_endproc
# -- End function
.globl _ZN17ArrayManipulationC2Ei # -- Begin function _ZN17ArrayManipulationC2Ei
.p2align 4, 0x90
.type _ZN17ArrayManipulationC2Ei,@function
_ZN17ArrayManipulationC2Ei: # @_ZN17ArrayManipulationC2Ei
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, 8(%rdi)
movslq %esi, %r15
leaq (,%r15,4), %rsi
movq %rsi, 16(%rdi)
movl $1, %edx
callq hipMallocManaged
testl %r15d, %r15d
jle .LBB1_3
# %bb.1: # %.lr.ph
movq (%r14), %rax
movl %ebx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl %edx, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _ZN17ArrayManipulationC2Ei, .Lfunc_end1-_ZN17ArrayManipulationC2Ei
.cfi_endproc
# -- End function
.globl _ZNK17ArrayManipulation12DisplayArrayEv # -- Begin function _ZNK17ArrayManipulation12DisplayArrayEv
.p2align 4, 0x90
.type _ZNK17ArrayManipulation12DisplayArrayEv,@function
_ZNK17ArrayManipulation12DisplayArrayEv: # @_ZNK17ArrayManipulation12DisplayArrayEv
.cfi_startproc
# %bb.0:
cmpl $0, 8(%rdi)
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx), %rax
movl (%rax,%r14,4), %edx
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
movslq 8(%rbx), %rax
cmpq %rax, %r14
jl .LBB2_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _ZNK17ArrayManipulation12DisplayArrayEv, .Lfunc_end2-_ZNK17ArrayManipulation12DisplayArrayEv
.cfi_endproc
# -- End function
.globl _ZN17ArrayManipulation3runEmm # -- Begin function _ZN17ArrayManipulation3runEmm
.p2align 4, 0x90
.type _ZN17ArrayManipulation3runEmm,@function
_ZN17ArrayManipulation3runEmm: # @_ZN17ArrayManipulation3runEmm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq %rsp, %rdi
callq hipGetDevice
movl %eax, (%rsp)
movl $.L.str.1, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $-1, %esi
xorl %eax, %eax
callq printf
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r14d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rbx), %rax
movl 16(%rbx), %ecx
movq %rax, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25array_manipulation_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN17ArrayManipulation3runEmm, .Lfunc_end3-_ZN17ArrayManipulation3runEmm
.cfi_endproc
# -- End function
.globl _ZNK17ArrayManipulation12assertResultEv # -- Begin function _ZNK17ArrayManipulation12assertResultEv
.p2align 4, 0x90
.type _ZNK17ArrayManipulation12assertResultEv,@function
_ZNK17ArrayManipulation12assertResultEv: # @_ZNK17ArrayManipulation12assertResultEv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end4:
.size _ZNK17ArrayManipulation12assertResultEv, .Lfunc_end4-_ZNK17ArrayManipulation12assertResultEv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movl $10, 16(%rsp)
movq $40, 24(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 8(%rsp), %rcx
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB5_1
# %bb.2: # %_ZN17ArrayManipulationC2Ei.exit
leaq 8(%rsp), %rdi
movl $1, %esi
movl $256, %edx # imm = 0x100
callq _ZN17ArrayManipulation3runEmm
cmpl $0, 16(%rsp)
jle .LBB5_5
# %bb.3: # %.lr.ph.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
movslq 16(%rsp), %rax
cmpq %rax, %rbx
jl .LBB5_4
.LBB5_5: # %_ZNK17ArrayManipulation12DisplayArrayEv.exit
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25array_manipulation_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25array_manipulation_kernelPii,@object # @_Z25array_manipulation_kernelPii
.section .rodata,"a",@progbits
.globl _Z25array_manipulation_kernelPii
.p2align 3, 0x0
_Z25array_manipulation_kernelPii:
.quad _Z40__device_stub__array_manipulation_kernelPii
.size _Z25array_manipulation_kernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Index %d: %d\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Device ID: %d\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU Device ID: %d\n\n"
.size .L.str.2, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25array_manipulation_kernelPii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN17ArrayManipulationC1Ei
.type _ZN17ArrayManipulationC1Ei,@function
.set _ZN17ArrayManipulationC1Ei, _ZN17ArrayManipulationC2Ei
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__array_manipulation_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25array_manipulation_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25array_manipulation_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25array_manipulation_kernelPii
.globl _Z25array_manipulation_kernelPii
.p2align 8
.type _Z25array_manipulation_kernelPii,@function
_Z25array_manipulation_kernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25array_manipulation_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25array_manipulation_kernelPii, .Lfunc_end0-_Z25array_manipulation_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25array_manipulation_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25array_manipulation_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00197538_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN17ArrayManipulationC2Ei
.type _ZN17ArrayManipulationC2Ei, @function
_ZN17ArrayManipulationC2Ei:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %r12d
movl %esi, 8(%rdi)
movslq %esi, %rbp
leaq 0(,%rbp,4), %rsi
movq %rsi, 16(%rdi)
movl $1, %edx
call cudaMallocManaged@PLT
testl %r12d, %r12d
jle .L3
movl $0, %eax
.L5:
movq (%rbx), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq %rax, %rbp
jne .L5
.L3:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZN17ArrayManipulationC2Ei, .-_ZN17ArrayManipulationC2Ei
.globl _ZN17ArrayManipulationC1Ei
.set _ZN17ArrayManipulationC1Ei,_ZN17ArrayManipulationC2Ei
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Index %d: %d\n"
.text
.align 2
.globl _ZNK17ArrayManipulation12DisplayArrayEv
.type _ZNK17ArrayManipulation12DisplayArrayEv, @function
_ZNK17ArrayManipulation12DisplayArrayEv:
.LFB2060:
.cfi_startproc
endbr64
cmpl $0, 8(%rdi)
jle .L13
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl $0, %ebx
leaq .LC0(%rip), %r12
.L10:
movq 0(%rbp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 8(%rbp)
jg .L10
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2060:
.size _ZNK17ArrayManipulation12DisplayArrayEv, .-_ZNK17ArrayManipulation12DisplayArrayEv
.align 2
.globl _ZNK17ArrayManipulation12assertResultEv
.type _ZNK17ArrayManipulation12assertResultEv, @function
_ZNK17ArrayManipulation12assertResultEv:
.LFB2062:
.cfi_startproc
endbr64
movl 8(%rdi), %edx
testl %edx, %edx
jle .L16
movl $0, %eax
.L18:
addl $1, %eax
cmpl %edx, %eax
jne .L18
.L16:
ret
.cfi_endproc
.LFE2062:
.size _ZNK17ArrayManipulation12assertResultEv, .-_ZNK17ArrayManipulation12assertResultEv
.globl _Z46__device_stub__Z25array_manipulation_kernelPiiPii
.type _Z46__device_stub__Z25array_manipulation_kernelPiiPii, @function
_Z46__device_stub__Z25array_manipulation_kernelPiiPii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25array_manipulation_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z46__device_stub__Z25array_manipulation_kernelPiiPii, .-_Z46__device_stub__Z25array_manipulation_kernelPiiPii
.globl _Z25array_manipulation_kernelPii
.type _Z25array_manipulation_kernelPii, @function
_Z25array_manipulation_kernelPii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z25array_manipulation_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z25array_manipulation_kernelPii, .-_Z25array_manipulation_kernelPii
.section .rodata.str1.1
.LC1:
.string "GPU Device ID: %d\n"
.LC2:
.string "CPU Device ID: %d\n\n"
.text
.align 2
.globl _ZN17ArrayManipulation3runEmm
.type _ZN17ArrayManipulation3runEmm, @function
_ZN17ArrayManipulation3runEmm:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %rbx
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
movl %eax, %edx
movl %eax, 12(%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, 28(%rsp)
movl $1, 32(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L29:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq (%r12), %rdi
movl 16(%r12), %esi
call _Z46__device_stub__Z25array_manipulation_kernelPiiPii
jmp .L29
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _ZN17ArrayManipulation3runEmm, .-_ZN17ArrayManipulation3runEmm
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $10, %esi
movq %rbx, %rdi
call _ZN17ArrayManipulationC1Ei
movl $256, %edx
movl $1, %esi
movq %rbx, %rdi
call _ZN17ArrayManipulation3runEmm
movq %rbx, %rdi
call _ZNK17ArrayManipulation12DisplayArrayEv
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z25array_manipulation_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z25array_manipulation_kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z40__device_stub__array_manipulation_kernelPii # -- Begin function _Z40__device_stub__array_manipulation_kernelPii
.p2align 4, 0x90
.type _Z40__device_stub__array_manipulation_kernelPii,@function
_Z40__device_stub__array_manipulation_kernelPii: # @_Z40__device_stub__array_manipulation_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25array_manipulation_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z40__device_stub__array_manipulation_kernelPii, .Lfunc_end0-_Z40__device_stub__array_manipulation_kernelPii
.cfi_endproc
# -- End function
.globl _ZN17ArrayManipulationC2Ei # -- Begin function _ZN17ArrayManipulationC2Ei
.p2align 4, 0x90
.type _ZN17ArrayManipulationC2Ei,@function
_ZN17ArrayManipulationC2Ei: # @_ZN17ArrayManipulationC2Ei
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, 8(%rdi)
movslq %esi, %r15
leaq (,%r15,4), %rsi
movq %rsi, 16(%rdi)
movl $1, %edx
callq hipMallocManaged
testl %r15d, %r15d
jle .LBB1_3
# %bb.1: # %.lr.ph
movq (%r14), %rax
movl %ebx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl %edx, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _ZN17ArrayManipulationC2Ei, .Lfunc_end1-_ZN17ArrayManipulationC2Ei
.cfi_endproc
# -- End function
.globl _ZNK17ArrayManipulation12DisplayArrayEv # -- Begin function _ZNK17ArrayManipulation12DisplayArrayEv
.p2align 4, 0x90
.type _ZNK17ArrayManipulation12DisplayArrayEv,@function
_ZNK17ArrayManipulation12DisplayArrayEv: # @_ZNK17ArrayManipulation12DisplayArrayEv
.cfi_startproc
# %bb.0:
cmpl $0, 8(%rdi)
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx), %rax
movl (%rax,%r14,4), %edx
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
movslq 8(%rbx), %rax
cmpq %rax, %r14
jl .LBB2_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _ZNK17ArrayManipulation12DisplayArrayEv, .Lfunc_end2-_ZNK17ArrayManipulation12DisplayArrayEv
.cfi_endproc
# -- End function
.globl _ZN17ArrayManipulation3runEmm # -- Begin function _ZN17ArrayManipulation3runEmm
.p2align 4, 0x90
.type _ZN17ArrayManipulation3runEmm,@function
_ZN17ArrayManipulation3runEmm: # @_ZN17ArrayManipulation3runEmm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq %rsp, %rdi
callq hipGetDevice
movl %eax, (%rsp)
movl $.L.str.1, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $-1, %esi
xorl %eax, %eax
callq printf
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r14d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rbx), %rax
movl 16(%rbx), %ecx
movq %rax, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25array_manipulation_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN17ArrayManipulation3runEmm, .Lfunc_end3-_ZN17ArrayManipulation3runEmm
.cfi_endproc
# -- End function
.globl _ZNK17ArrayManipulation12assertResultEv # -- Begin function _ZNK17ArrayManipulation12assertResultEv
.p2align 4, 0x90
.type _ZNK17ArrayManipulation12assertResultEv,@function
_ZNK17ArrayManipulation12assertResultEv: # @_ZNK17ArrayManipulation12assertResultEv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end4:
.size _ZNK17ArrayManipulation12assertResultEv, .Lfunc_end4-_ZNK17ArrayManipulation12assertResultEv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movl $10, 16(%rsp)
movq $40, 24(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 8(%rsp), %rcx
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB5_1
# %bb.2: # %_ZN17ArrayManipulationC2Ei.exit
leaq 8(%rsp), %rdi
movl $1, %esi
movl $256, %edx # imm = 0x100
callq _ZN17ArrayManipulation3runEmm
cmpl $0, 16(%rsp)
jle .LBB5_5
# %bb.3: # %.lr.ph.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
movslq 16(%rsp), %rax
cmpq %rax, %rbx
jl .LBB5_4
.LBB5_5: # %_ZNK17ArrayManipulation12DisplayArrayEv.exit
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25array_manipulation_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25array_manipulation_kernelPii,@object # @_Z25array_manipulation_kernelPii
.section .rodata,"a",@progbits
.globl _Z25array_manipulation_kernelPii
.p2align 3, 0x0
_Z25array_manipulation_kernelPii:
.quad _Z40__device_stub__array_manipulation_kernelPii
.size _Z25array_manipulation_kernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Index %d: %d\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Device ID: %d\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU Device ID: %d\n\n"
.size .L.str.2, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25array_manipulation_kernelPii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN17ArrayManipulationC1Ei
.type _ZN17ArrayManipulationC1Ei,@function
.set _ZN17ArrayManipulationC1Ei, _ZN17ArrayManipulationC2Ei
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__array_manipulation_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25array_manipulation_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <ctime>
#include <cstdlib>
#include <iostream>
#include <string>
#include <cmath>
#include <vector>
class Pt
{
public:
float x = 0;
float y = 0;
int group = 1;
};
__global__ void setFalse(bool*& Changed, int dsize);
__device__ float dist(const Pt& p1, const Pt& p2);
__global__ void Group_find(Pt*& data, int dsize, Pt* dev_ctrs, bool*& moved);
__global__ void Moved_find(bool* moved, int dsize, bool* dev_isMoved);
__global__ void Group_update(Pt*& data, int dsize, float* sums, int* cnts);
int main()
{
unsigned seed = time(0);
srand(seed);
int dsize=10;
printf("enter data size ");
scanf("%d", &dsize);
const int gsize = dsize/2;
const int m1 = 0, n1 = gsize;
const int m2 = n1+1, n2 = dsize;
Pt expected1, expected2;
float xsum = 0, ysum = 0;
Pt* data;
cudaMallocManaged( &data, dsize * sizeof(Pt) );
bool* moved;
cudaMallocManaged( &moved, dsize * sizeof(bool) );
int blockSize = 1024;
int blockNum = (dsize + blockSize - 1) / blockSize;
Pt* dataTemp = new Pt[dsize];
for(int i = 0; i < gsize; ++i)
{
Pt p;
p.x = m1 + rand() % (n1 - m1);
xsum += p.x;
p.y = m1 + rand() % (n1 - m1);
ysum += p.y;
dataTemp[i]=p;
}
expected1.x = xsum/gsize;
expected1.y = ysum/gsize;
xsum = 0, ysum = 0;
for(int i = 0; i < gsize; ++i)
{
Pt p;
p.x = m2 + rand() % (n2 - m2);
xsum += p.x;
p.y = m2 + rand() % (n2 - m2);
ysum += p.y;
dataTemp[i + gsize]=p;
}
expected2.x = xsum/gsize;
expected2.y = ysum/gsize;
cudaMemcpy(data,dataTemp, dsize * sizeof( Pt ), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
Pt* ctrs = new Pt[2];
ctrs[0].x = m1 + rand() % (n2-m1);
ctrs[0].y = m1 + rand() % (n2-m1);
ctrs[1].x = m1 + rand() % (n2-m1);
ctrs[1].y = m1 + rand() % (n2-m1);
Pt* dev_ctrs;
cudaMallocManaged(&dev_ctrs, 2 * sizeof(Pt));
cudaMemcpy(dev_ctrs, ctrs, 2 * sizeof( Pt ), cudaMemcpyHostToDevice);
float* sums = new float[4];
for(int s = 0; s < 4; ++s) sums[s] = 0;
float* dev_sums;
cudaMallocManaged(&dev_sums, 4 * sizeof(float));
int* cnts = new int[2];
cnts[0] = 1; cnts[1] = 1;
int* dev_cnts;
cudaMallocManaged(&dev_cnts, 2 * sizeof(int));
bool* isMoved = new bool[1];
isMoved[0] = true;
bool* dev_isMoved;
cudaMallocManaged(&dev_isMoved, sizeof(bool));
while( isMoved[0] )
{
printf("Center1 = ( %.2f, %.2f )\n", ctrs[0].x ,ctrs[0].y);
printf("Center2 = ( %.2f, %.2f )\n", ctrs[1].x, ctrs[1].y);
isMoved[0] = false;
clock_t st = clock();
setFalse<<<blockNum, blockSize>>>(moved, dsize);
cudaDeviceSynchronize();
Group_find<<<blockNum, blockSize>>>(data, dsize, dev_ctrs, moved);
cudaDeviceSynchronize();
cudaMemcpy(dev_isMoved, isMoved, sizeof( bool ), cudaMemcpyHostToDevice);
Moved_find<<<1, 1>>>(moved, dsize, dev_isMoved);
cudaDeviceSynchronize();
cudaMemcpy(isMoved, dev_isMoved, sizeof( bool ), cudaMemcpyDeviceToHost);
clock_t st2 = clock();
clock_t st3 = 0;
clock_t st4 = 0;
if( isMoved[0] )
{
st3 = clock();
cudaMemcpy(dev_sums, sums, 4 * sizeof( float ), cudaMemcpyHostToDevice);
cudaMemcpy(dev_cnts, cnts, 2 * sizeof( int ), cudaMemcpyHostToDevice);
Group_update<<<blockNum, blockSize>>>(data, dsize, dev_sums, dev_cnts);
cudaDeviceSynchronize();
cudaMemcpy(sums, dev_sums, 4 * sizeof( float ), cudaMemcpyDeviceToHost);
cudaMemcpy(cnts, dev_cnts, 2 * sizeof( int ), cudaMemcpyDeviceToHost);
st4 = clock();
ctrs[0].x = sums[0] / cnts[0];
ctrs[0].y = sums[1] / cnts[0];
ctrs[1].x = sums[2] / cnts[1];
ctrs[1].y = sums[3] / cnts[1];
}
clock_t st5 = clock();
cudaMemcpy(ctrs,dev_ctrs, 2 * sizeof( Pt ), cudaMemcpyDeviceToHost);
printf("\n Elapsed Time : %u ms \n", clock() - st5 + (st4 - st3) + (st2 - st));
}
printf("---Result---:\n");
printf("Expected1 = ( %.2f, %.2f )\n",expected1.x, expected1.y);
printf("Expected2 = ( %.2f, %.2f )\n", expected2.x, expected2.y);
printf("random initial Center1 = ( %.2f, %.2f )" ,ctrs[0].x ,ctrs[0].y);
printf("random initial Center2 = ( %.2f, %.2f )", ctrs[1].x, ctrs[1].y);
cudaFree(&data);
cudaFree(&moved);
delete [] dataTemp;
delete [] isMoved;
cudaFree( &dev_isMoved);
delete [] sums;
cudaFree( &dev_sums);
delete [] cnts;
cudaFree( &dev_cnts);
}
__device__ float dist(const Pt& p1, const Pt& p2)
{
float s = sqrt(pow((p1.x - p2.x), 2) + pow((p1.y - p2.y), 2));
return s;
}
__global__ void setFalse(bool*& Changed, int dsize)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < dsize)
{
Changed[index] = false;
}
}
__global__ void Group_find(Pt*& data, int dsize, Pt* dev_ctrs, bool*& moved)
{
int p = blockIdx.x * blockDim.x + threadIdx.x;
if (p < dsize)
{
float d1 = dist(dev_ctrs[0], data[p]);
float d2 = dist(dev_ctrs[1], data[p]);
int oldGroup = data[p].group;
if (d1 < d2)
data[p].group = 1;
else
data[p].group = 2;
if (data[p].group != oldGroup)
{
moved[p] = true;
}
}
}
__global__ void Moved_find(bool* moved, int dsize, bool* dev_isMoved)
{
int index = 0;
while (index < dsize && !dev_isMoved[0])
{
if (moved[index] == true) {
dev_isMoved[0] = true;
}
index++;
}
}
__global__ void Group_update(Pt*& data, int dsize, float* sums, int* cnts)
{
int p = blockIdx.x * blockDim.x + threadIdx.x;
if (p < dsize)
{
if (data[p].group == 1)
{
sums[0] += data[p].x; sums[1] += data[p].y;
cnts[0]++;
}
else
{
sums[2] += data[p].x; sums[3] += data[p].y;
cnts[1]++;
}
}
} | .file "tmpxft_00101907_00000000-6_Kmeans.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4039:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4039:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4distRK2PtS1_
.type _Z4distRK2PtS1_, @function
_Z4distRK2PtS1_:
.LFB4036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4036:
.size _Z4distRK2PtS1_, .-_Z4distRK2PtS1_
.globl _Z29__device_stub__Z8setFalseRPbiPPbi
.type _Z29__device_stub__Z8setFalseRPbiPPbi, @function
_Z29__device_stub__Z8setFalseRPbiPPbi:
.LFB4061:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8setFalseRPbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4061:
.size _Z29__device_stub__Z8setFalseRPbiPPbi, .-_Z29__device_stub__Z8setFalseRPbiPPbi
.globl _Z8setFalseRPbi
.type _Z8setFalseRPbi, @function
_Z8setFalseRPbi:
.LFB4062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8setFalseRPbiPPbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4062:
.size _Z8setFalseRPbi, .-_Z8setFalseRPbi
.globl _Z40__device_stub__Z10Group_findRP2PtiS0_RPbPP2PtiS0_PPb
.type _Z40__device_stub__Z10Group_findRP2PtiS0_RPbPP2PtiS0_PPb, @function
_Z40__device_stub__Z10Group_findRP2PtiS0_RPbPP2PtiS0_PPb:
.LFB4063:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10Group_findRP2PtiS0_RPb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4063:
.size _Z40__device_stub__Z10Group_findRP2PtiS0_RPbPP2PtiS0_PPb, .-_Z40__device_stub__Z10Group_findRP2PtiS0_RPbPP2PtiS0_PPb
.globl _Z10Group_findRP2PtiS0_RPb
.type _Z10Group_findRP2PtiS0_RPb, @function
_Z10Group_findRP2PtiS0_RPb:
.LFB4064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z10Group_findRP2PtiS0_RPbPP2PtiS0_PPb
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4064:
.size _Z10Group_findRP2PtiS0_RPb, .-_Z10Group_findRP2PtiS0_RPb
.globl _Z33__device_stub__Z10Moved_findPbiS_PbiS_
.type _Z33__device_stub__Z10Moved_findPbiS_PbiS_, @function
_Z33__device_stub__Z10Moved_findPbiS_PbiS_:
.LFB4065:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10Moved_findPbiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4065:
.size _Z33__device_stub__Z10Moved_findPbiS_PbiS_, .-_Z33__device_stub__Z10Moved_findPbiS_PbiS_
.globl _Z10Moved_findPbiS_
.type _Z10Moved_findPbiS_, @function
_Z10Moved_findPbiS_:
.LFB4066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10Moved_findPbiS_PbiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4066:
.size _Z10Moved_findPbiS_, .-_Z10Moved_findPbiS_
.globl _Z40__device_stub__Z12Group_updateRP2PtiPfPiPP2PtiPfPi
.type _Z40__device_stub__Z12Group_updateRP2PtiPfPiPP2PtiPfPi, @function
_Z40__device_stub__Z12Group_updateRP2PtiPfPiPP2PtiPfPi:
.LFB4067:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12Group_updateRP2PtiPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z40__device_stub__Z12Group_updateRP2PtiPfPiPP2PtiPfPi, .-_Z40__device_stub__Z12Group_updateRP2PtiPfPiPP2PtiPfPi
.globl _Z12Group_updateRP2PtiPfPi
.type _Z12Group_updateRP2PtiPfPi, @function
_Z12Group_updateRP2PtiPfPi:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z12Group_updateRP2PtiPfPiPP2PtiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z12Group_updateRP2PtiPfPi, .-_Z12Group_updateRP2PtiPfPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "enter data size "
.LC2:
.string "%d"
.LC3:
.string "Center1 = ( %.2f, %.2f )\n"
.LC4:
.string "Center2 = ( %.2f, %.2f )\n"
.LC5:
.string "\n Elapsed Time : %u ms \n"
.LC6:
.string "---Result---:\n"
.LC7:
.string "Expected1 = ( %.2f, %.2f )\n"
.LC8:
.string "Expected2 = ( %.2f, %.2f )\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "random initial Center1 = ( %.2f, %.2f )"
.align 8
.LC10:
.string "random initial Center2 = ( %.2f, %.2f )"
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $10, 76(%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 76(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 76(%rsp), %r15d
movl %r15d, %r12d
shrl $31, %r12d
addl %r15d, %r12d
sarl %r12d
movslq %r15d, %rax
leaq (%rax,%rax,2), %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movslq 76(%rsp), %rsi
leaq 88(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movl 76(%rsp), %ebx
leal 2046(%rbx), %eax
movl %ebx, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 16(%rsp)
movslq %ebx, %rbx
movabsq $768614336404564650, %rax
cmpq %rbx, %rax
jb .L38
movl %r12d, %ebp
leal 1(%r12), %r13d
leaq (%rbx,%rbx,2), %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, 40(%rsp)
subq $1, %rbx
js .L40
.L42:
movl $0x00000000, (%rax)
movl $0x00000000, 4(%rax)
movl $1, 8(%rax)
addq $12, %rax
subq $1, %rbx
jns .L42
.L40:
cmpl $1, %r15d
jle .L43
movq 40(%rsp), %rbx
movl $0, %r14d
movl $0x00000000, 8(%rsp)
movl $0x00000000, (%rsp)
movl %r15d, 24(%rsp)
.L44:
call rand@PLT
cltd
idivl %ebp
pxor %xmm6, %xmm6
cvtsi2ssl %edx, %xmm6
movd %xmm6, %r15d
movaps %xmm6, %xmm2
addss (%rsp), %xmm2
movss %xmm2, (%rsp)
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss 8(%rsp), %xmm3
addss %xmm0, %xmm3
movss %xmm3, 8(%rsp)
movl %r15d, (%rbx)
movss %xmm0, 4(%rbx)
movl $1, 8(%rbx)
addl $1, %r14d
addq $12, %rbx
cmpl %r14d, %r12d
jg .L44
movl 24(%rsp), %r15d
pxor %xmm1, %xmm1
cvtsi2ssl %r12d, %xmm1
movss (%rsp), %xmm4
divss %xmm1, %xmm4
movss %xmm4, 56(%rsp)
movaps %xmm3, %xmm5
divss %xmm1, %xmm5
movss %xmm5, 60(%rsp)
movslq %r12d, %rax
leaq (%rax,%rax,2), %rax
movq 40(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movl $0, %r14d
movl $0x00000000, 8(%rsp)
movl $0x00000000, (%rsp)
movl %r15d, %ebp
subl %r13d, %ebp
movss %xmm1, 32(%rsp)
.L45:
call rand@PLT
cltd
idivl %ebp
addl %r13d, %edx
pxor %xmm6, %xmm6
cvtsi2ssl %edx, %xmm6
movd %xmm6, %r15d
movaps %xmm6, %xmm4
addss (%rsp), %xmm4
movss %xmm4, (%rsp)
call rand@PLT
cltd
idivl %ebp
addl %r13d, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss 8(%rsp), %xmm5
addss %xmm0, %xmm5
movss %xmm5, 8(%rsp)
movl %r15d, (%rbx)
movss %xmm0, 4(%rbx)
movl $1, 8(%rbx)
addl $1, %r14d
addq $12, %rbx
cmpl %r14d, %r12d
jg .L45
movl 24(%rsp), %r15d
movss 32(%rsp), %xmm1
.L53:
movss (%rsp), %xmm2
divss %xmm1, %xmm2
movss %xmm2, 48(%rsp)
movss 8(%rsp), %xmm3
divss %xmm1, %xmm3
movss %xmm3, 52(%rsp)
movslq 76(%rsp), %rax
leaq (%rax,%rax,2), %rdx
salq $2, %rdx
movl $1, %ecx
movq 40(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $24, %edi
call _Znam@PLT
movq %rax, %rbx
movl $0x00000000, (%rax)
movl $0x00000000, 4(%rax)
movl $1, 8(%rax)
movl $0x00000000, 12(%rax)
movl $0x00000000, 16(%rax)
movl $1, 20(%rax)
call rand@PLT
cltd
idivl %r15d
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx)
call rand@PLT
cltd
idivl %r15d
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 4(%rbx)
call rand@PLT
cltd
idivl %r15d
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 12(%rbx)
call rand@PLT
cltd
idivl %r15d
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 16(%rbx)
leaq 96(%rsp), %rdi
movl $1, %edx
movl $24, %esi
call cudaMallocManaged@PLT
movl $1, %ecx
movl $24, %edx
movq %rbx, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, %edi
call _Znam@PLT
movq %rax, %r14
movl $0x00000000, (%rax)
movl $0x00000000, 4(%rax)
movl $0x00000000, 8(%rax)
movl $0x00000000, 12(%rax)
leaq 104(%rsp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movl $8, %edi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $1, (%rax)
movl $1, 4(%rax)
leaq 112(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
movl $1, %edi
call _Znam@PLT
movq %rax, %r13
movb $1, (%rax)
leaq 120(%rsp), %rdi
movl $1, %edx
movl $1, %esi
call cudaMallocManaged@PLT
cmpb $0, 0(%r13)
je .L46
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
movl 16(%rsp), %r15d
jmp .L52
.L38:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L41
call __stack_chk_fail@PLT
.L41:
call __cxa_throw_bad_array_new_length@PLT
.L64:
movl 76(%rsp), %esi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z8setFalseRPbiPPbi
jmp .L47
.L65:
leaq 80(%rsp), %rdi
movq 32(%rsp), %rcx
movq 96(%rsp), %rdx
movl 76(%rsp), %esi
call _Z40__device_stub__Z10Group_findRP2PtiS0_RPbPP2PtiS0_PPb
jmp .L48
.L66:
movq 120(%rsp), %rdx
movl 76(%rsp), %esi
movq 88(%rsp), %rdi
call _Z33__device_stub__Z10Moved_findPbiS_PbiS_
jmp .L49
.L51:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $16, %edx
movq 104(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $8, %edx
movq 112(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %rbp
movq 24(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2ssl (%rax), %xmm1
movss (%r14), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbx)
movss 4(%r14), %xmm0
divss %xmm1, %xmm0
movss %xmm0, 4(%rbx)
pxor %xmm1, %xmm1
cvtsi2ssl 4(%rax), %xmm1
movss 8(%r14), %xmm0
divss %xmm1, %xmm0
movss %xmm0, 12(%rbx)
movss 12(%r14), %xmm0
divss %xmm1, %xmm0
movss %xmm0, 16(%rbx)
.L50:
call clock@PLT
movq %rax, 16(%rsp)
movl $2, %ecx
movl $24, %edx
movq 96(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %rdx
movq 16(%rsp), %rax
subq %rax, %rdx
subq %r12, %rbp
addq %rbp, %rdx
movq 8(%rsp), %rax
movq (%rsp), %rcx
subq %rcx, %rax
addq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpb $0, 0(%r13)
je .L46
.L52:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rbx), %xmm1
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 16(%rbx), %xmm1
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movb $0, 0(%r13)
call clock@PLT
movq %rax, (%rsp)
movl $1024, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl %r15d, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L47:
call cudaDeviceSynchronize@PLT
movl $1024, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl %r15d, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L48:
call cudaDeviceSynchronize@PLT
movl $1, %ecx
movl $1, %edx
movq %r13, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L49:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $1, %edx
movq 120(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, 8(%rsp)
movl $0, %ebp
movl $0, %r12d
cmpb $0, 0(%r13)
je .L50
call clock@PLT
movq %rax, %r12
movl $1, %ecx
movl $16, %edx
movq %r14, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl %r15d, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L51
leaq 80(%rsp), %rdi
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movl 76(%rsp), %esi
call _Z40__device_stub__Z12Group_updateRP2PtiPfPiPP2PtiPfPi
jmp .L51
.L46:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 56(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 60(%rsp), %xmm1
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 52(%rsp), %xmm1
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rbx), %xmm1
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 16(%rbx), %xmm1
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
call cudaFree@PLT
leaq 88(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
leaq 120(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call _ZdaPv@PLT
leaq 104(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call _ZdaPv@PLT
leaq 112(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pxor %xmm1, %xmm1
cvtsi2ssl %r12d, %xmm1
pxor %xmm0, %xmm0
divss %xmm1, %xmm0
movss %xmm0, 56(%rsp)
movss %xmm0, 60(%rsp)
movl $0x00000000, 8(%rsp)
movl $0x00000000, (%rsp)
jmp .L53
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z12Group_updateRP2PtiPfPi"
.LC12:
.string "_Z10Moved_findPbiS_"
.LC13:
.string "_Z10Group_findRP2PtiS0_RPb"
.LC14:
.string "_Z8setFalseRPbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Group_updateRP2PtiPfPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10Moved_findPbiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z10Group_findRP2PtiS0_RPb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z8setFalseRPbi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <ctime>
#include <cstdlib>
#include <iostream>
#include <string>
#include <cmath>
#include <vector>
class Pt
{
public:
float x = 0;
float y = 0;
int group = 1;
};
__global__ void setFalse(bool*& Changed, int dsize);
__device__ float dist(const Pt& p1, const Pt& p2);
__global__ void Group_find(Pt*& data, int dsize, Pt* dev_ctrs, bool*& moved);
__global__ void Moved_find(bool* moved, int dsize, bool* dev_isMoved);
__global__ void Group_update(Pt*& data, int dsize, float* sums, int* cnts);
int main()
{
unsigned seed = time(0);
srand(seed);
int dsize=10;
printf("enter data size ");
scanf("%d", &dsize);
const int gsize = dsize/2;
const int m1 = 0, n1 = gsize;
const int m2 = n1+1, n2 = dsize;
Pt expected1, expected2;
float xsum = 0, ysum = 0;
Pt* data;
cudaMallocManaged( &data, dsize * sizeof(Pt) );
bool* moved;
cudaMallocManaged( &moved, dsize * sizeof(bool) );
int blockSize = 1024;
int blockNum = (dsize + blockSize - 1) / blockSize;
Pt* dataTemp = new Pt[dsize];
for(int i = 0; i < gsize; ++i)
{
Pt p;
p.x = m1 + rand() % (n1 - m1);
xsum += p.x;
p.y = m1 + rand() % (n1 - m1);
ysum += p.y;
dataTemp[i]=p;
}
expected1.x = xsum/gsize;
expected1.y = ysum/gsize;
xsum = 0, ysum = 0;
for(int i = 0; i < gsize; ++i)
{
Pt p;
p.x = m2 + rand() % (n2 - m2);
xsum += p.x;
p.y = m2 + rand() % (n2 - m2);
ysum += p.y;
dataTemp[i + gsize]=p;
}
expected2.x = xsum/gsize;
expected2.y = ysum/gsize;
cudaMemcpy(data,dataTemp, dsize * sizeof( Pt ), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
Pt* ctrs = new Pt[2];
ctrs[0].x = m1 + rand() % (n2-m1);
ctrs[0].y = m1 + rand() % (n2-m1);
ctrs[1].x = m1 + rand() % (n2-m1);
ctrs[1].y = m1 + rand() % (n2-m1);
Pt* dev_ctrs;
cudaMallocManaged(&dev_ctrs, 2 * sizeof(Pt));
cudaMemcpy(dev_ctrs, ctrs, 2 * sizeof( Pt ), cudaMemcpyHostToDevice);
float* sums = new float[4];
for(int s = 0; s < 4; ++s) sums[s] = 0;
float* dev_sums;
cudaMallocManaged(&dev_sums, 4 * sizeof(float));
int* cnts = new int[2];
cnts[0] = 1; cnts[1] = 1;
int* dev_cnts;
cudaMallocManaged(&dev_cnts, 2 * sizeof(int));
bool* isMoved = new bool[1];
isMoved[0] = true;
bool* dev_isMoved;
cudaMallocManaged(&dev_isMoved, sizeof(bool));
while( isMoved[0] )
{
printf("Center1 = ( %.2f, %.2f )\n", ctrs[0].x ,ctrs[0].y);
printf("Center2 = ( %.2f, %.2f )\n", ctrs[1].x, ctrs[1].y);
isMoved[0] = false;
clock_t st = clock();
setFalse<<<blockNum, blockSize>>>(moved, dsize);
cudaDeviceSynchronize();
Group_find<<<blockNum, blockSize>>>(data, dsize, dev_ctrs, moved);
cudaDeviceSynchronize();
cudaMemcpy(dev_isMoved, isMoved, sizeof( bool ), cudaMemcpyHostToDevice);
Moved_find<<<1, 1>>>(moved, dsize, dev_isMoved);
cudaDeviceSynchronize();
cudaMemcpy(isMoved, dev_isMoved, sizeof( bool ), cudaMemcpyDeviceToHost);
clock_t st2 = clock();
clock_t st3 = 0;
clock_t st4 = 0;
if( isMoved[0] )
{
st3 = clock();
cudaMemcpy(dev_sums, sums, 4 * sizeof( float ), cudaMemcpyHostToDevice);
cudaMemcpy(dev_cnts, cnts, 2 * sizeof( int ), cudaMemcpyHostToDevice);
Group_update<<<blockNum, blockSize>>>(data, dsize, dev_sums, dev_cnts);
cudaDeviceSynchronize();
cudaMemcpy(sums, dev_sums, 4 * sizeof( float ), cudaMemcpyDeviceToHost);
cudaMemcpy(cnts, dev_cnts, 2 * sizeof( int ), cudaMemcpyDeviceToHost);
st4 = clock();
ctrs[0].x = sums[0] / cnts[0];
ctrs[0].y = sums[1] / cnts[0];
ctrs[1].x = sums[2] / cnts[1];
ctrs[1].y = sums[3] / cnts[1];
}
clock_t st5 = clock();
cudaMemcpy(ctrs,dev_ctrs, 2 * sizeof( Pt ), cudaMemcpyDeviceToHost);
printf("\n Elapsed Time : %u ms \n", clock() - st5 + (st4 - st3) + (st2 - st));
}
printf("---Result---:\n");
printf("Expected1 = ( %.2f, %.2f )\n",expected1.x, expected1.y);
printf("Expected2 = ( %.2f, %.2f )\n", expected2.x, expected2.y);
printf("random initial Center1 = ( %.2f, %.2f )" ,ctrs[0].x ,ctrs[0].y);
printf("random initial Center2 = ( %.2f, %.2f )", ctrs[1].x, ctrs[1].y);
cudaFree(&data);
cudaFree(&moved);
delete [] dataTemp;
delete [] isMoved;
cudaFree( &dev_isMoved);
delete [] sums;
cudaFree( &dev_sums);
delete [] cnts;
cudaFree( &dev_cnts);
}
__device__ float dist(const Pt& p1, const Pt& p2)
{
float s = sqrt(pow((p1.x - p2.x), 2) + pow((p1.y - p2.y), 2));
return s;
}
__global__ void setFalse(bool*& Changed, int dsize)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < dsize)
{
Changed[index] = false;
}
}
__global__ void Group_find(Pt*& data, int dsize, Pt* dev_ctrs, bool*& moved)
{
int p = blockIdx.x * blockDim.x + threadIdx.x;
if (p < dsize)
{
float d1 = dist(dev_ctrs[0], data[p]);
float d2 = dist(dev_ctrs[1], data[p]);
int oldGroup = data[p].group;
if (d1 < d2)
data[p].group = 1;
else
data[p].group = 2;
if (data[p].group != oldGroup)
{
moved[p] = true;
}
}
}
__global__ void Moved_find(bool* moved, int dsize, bool* dev_isMoved)
{
int index = 0;
while (index < dsize && !dev_isMoved[0])
{
if (moved[index] == true) {
dev_isMoved[0] = true;
}
index++;
}
}
__global__ void Group_update(Pt*& data, int dsize, float* sums, int* cnts)
{
int p = blockIdx.x * blockDim.x + threadIdx.x;
if (p < dsize)
{
if (data[p].group == 1)
{
sums[0] += data[p].x; sums[1] += data[p].y;
cnts[0]++;
}
else
{
sums[2] += data[p].x; sums[3] += data[p].y;
cnts[1]++;
}
}
} | #include <hip/hip_runtime.h>
#include <ctime>
#include <cstdlib>
#include <iostream>
#include <string>
#include <cmath>
#include <vector>
class Pt
{
public:
float x = 0;
float y = 0;
int group = 1;
};
__global__ void setFalse(bool*& Changed, int dsize);
__device__ float dist(const Pt& p1, const Pt& p2);
__global__ void Group_find(Pt*& data, int dsize, Pt* dev_ctrs, bool*& moved);
__global__ void Moved_find(bool* moved, int dsize, bool* dev_isMoved);
__global__ void Group_update(Pt*& data, int dsize, float* sums, int* cnts);
int main()
{
unsigned seed = time(0);
srand(seed);
int dsize=10;
printf("enter data size ");
scanf("%d", &dsize);
const int gsize = dsize/2;
const int m1 = 0, n1 = gsize;
const int m2 = n1+1, n2 = dsize;
Pt expected1, expected2;
float xsum = 0, ysum = 0;
Pt* data;
hipMallocManaged( &data, dsize * sizeof(Pt) );
bool* moved;
hipMallocManaged( &moved, dsize * sizeof(bool) );
int blockSize = 1024;
int blockNum = (dsize + blockSize - 1) / blockSize;
Pt* dataTemp = new Pt[dsize];
for(int i = 0; i < gsize; ++i)
{
Pt p;
p.x = m1 + rand() % (n1 - m1);
xsum += p.x;
p.y = m1 + rand() % (n1 - m1);
ysum += p.y;
dataTemp[i]=p;
}
expected1.x = xsum/gsize;
expected1.y = ysum/gsize;
xsum = 0, ysum = 0;
for(int i = 0; i < gsize; ++i)
{
Pt p;
p.x = m2 + rand() % (n2 - m2);
xsum += p.x;
p.y = m2 + rand() % (n2 - m2);
ysum += p.y;
dataTemp[i + gsize]=p;
}
expected2.x = xsum/gsize;
expected2.y = ysum/gsize;
hipMemcpy(data,dataTemp, dsize * sizeof( Pt ), hipMemcpyHostToDevice);
hipDeviceSynchronize();
Pt* ctrs = new Pt[2];
ctrs[0].x = m1 + rand() % (n2-m1);
ctrs[0].y = m1 + rand() % (n2-m1);
ctrs[1].x = m1 + rand() % (n2-m1);
ctrs[1].y = m1 + rand() % (n2-m1);
Pt* dev_ctrs;
hipMallocManaged(&dev_ctrs, 2 * sizeof(Pt));
hipMemcpy(dev_ctrs, ctrs, 2 * sizeof( Pt ), hipMemcpyHostToDevice);
float* sums = new float[4];
for(int s = 0; s < 4; ++s) sums[s] = 0;
float* dev_sums;
hipMallocManaged(&dev_sums, 4 * sizeof(float));
int* cnts = new int[2];
cnts[0] = 1; cnts[1] = 1;
int* dev_cnts;
hipMallocManaged(&dev_cnts, 2 * sizeof(int));
bool* isMoved = new bool[1];
isMoved[0] = true;
bool* dev_isMoved;
hipMallocManaged(&dev_isMoved, sizeof(bool));
while( isMoved[0] )
{
printf("Center1 = ( %.2f, %.2f )\n", ctrs[0].x ,ctrs[0].y);
printf("Center2 = ( %.2f, %.2f )\n", ctrs[1].x, ctrs[1].y);
isMoved[0] = false;
clock_t st = clock();
setFalse<<<blockNum, blockSize>>>(moved, dsize);
hipDeviceSynchronize();
Group_find<<<blockNum, blockSize>>>(data, dsize, dev_ctrs, moved);
hipDeviceSynchronize();
hipMemcpy(dev_isMoved, isMoved, sizeof( bool ), hipMemcpyHostToDevice);
Moved_find<<<1, 1>>>(moved, dsize, dev_isMoved);
hipDeviceSynchronize();
hipMemcpy(isMoved, dev_isMoved, sizeof( bool ), hipMemcpyDeviceToHost);
clock_t st2 = clock();
clock_t st3 = 0;
clock_t st4 = 0;
if( isMoved[0] )
{
st3 = clock();
hipMemcpy(dev_sums, sums, 4 * sizeof( float ), hipMemcpyHostToDevice);
hipMemcpy(dev_cnts, cnts, 2 * sizeof( int ), hipMemcpyHostToDevice);
Group_update<<<blockNum, blockSize>>>(data, dsize, dev_sums, dev_cnts);
hipDeviceSynchronize();
hipMemcpy(sums, dev_sums, 4 * sizeof( float ), hipMemcpyDeviceToHost);
hipMemcpy(cnts, dev_cnts, 2 * sizeof( int ), hipMemcpyDeviceToHost);
st4 = clock();
ctrs[0].x = sums[0] / cnts[0];
ctrs[0].y = sums[1] / cnts[0];
ctrs[1].x = sums[2] / cnts[1];
ctrs[1].y = sums[3] / cnts[1];
}
clock_t st5 = clock();
hipMemcpy(ctrs,dev_ctrs, 2 * sizeof( Pt ), hipMemcpyDeviceToHost);
printf("\n Elapsed Time : %u ms \n", clock() - st5 + (st4 - st3) + (st2 - st));
}
printf("---Result---:\n");
printf("Expected1 = ( %.2f, %.2f )\n",expected1.x, expected1.y);
printf("Expected2 = ( %.2f, %.2f )\n", expected2.x, expected2.y);
printf("random initial Center1 = ( %.2f, %.2f )" ,ctrs[0].x ,ctrs[0].y);
printf("random initial Center2 = ( %.2f, %.2f )", ctrs[1].x, ctrs[1].y);
hipFree(&data);
hipFree(&moved);
delete [] dataTemp;
delete [] isMoved;
hipFree( &dev_isMoved);
delete [] sums;
hipFree( &dev_sums);
delete [] cnts;
hipFree( &dev_cnts);
}
__device__ float dist(const Pt& p1, const Pt& p2)
{
float s = sqrt(pow((p1.x - p2.x), 2) + pow((p1.y - p2.y), 2));
return s;
}
__global__ void setFalse(bool*& Changed, int dsize)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < dsize)
{
Changed[index] = false;
}
}
__global__ void Group_find(Pt*& data, int dsize, Pt* dev_ctrs, bool*& moved)
{
int p = blockIdx.x * blockDim.x + threadIdx.x;
if (p < dsize)
{
float d1 = dist(dev_ctrs[0], data[p]);
float d2 = dist(dev_ctrs[1], data[p]);
int oldGroup = data[p].group;
if (d1 < d2)
data[p].group = 1;
else
data[p].group = 2;
if (data[p].group != oldGroup)
{
moved[p] = true;
}
}
}
__global__ void Moved_find(bool* moved, int dsize, bool* dev_isMoved)
{
int index = 0;
while (index < dsize && !dev_isMoved[0])
{
if (moved[index] == true) {
dev_isMoved[0] = true;
}
index++;
}
}
__global__ void Group_update(Pt*& data, int dsize, float* sums, int* cnts)
{
int p = blockIdx.x * blockDim.x + threadIdx.x;
if (p < dsize)
{
if (data[p].group == 1)
{
sums[0] += data[p].x; sums[1] += data[p].y;
cnts[0]++;
}
else
{
sums[2] += data[p].x; sums[3] += data[p].y;
cnts[1]++;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <ctime>
#include <cstdlib>
#include <iostream>
#include <string>
#include <cmath>
#include <vector>
class Pt
{
public:
float x = 0;
float y = 0;
int group = 1;
};
__global__ void setFalse(bool*& Changed, int dsize);
__device__ float dist(const Pt& p1, const Pt& p2);
__global__ void Group_find(Pt*& data, int dsize, Pt* dev_ctrs, bool*& moved);
__global__ void Moved_find(bool* moved, int dsize, bool* dev_isMoved);
__global__ void Group_update(Pt*& data, int dsize, float* sums, int* cnts);
int main()
{
unsigned seed = time(0);
srand(seed);
int dsize=10;
printf("enter data size ");
scanf("%d", &dsize);
const int gsize = dsize/2;
const int m1 = 0, n1 = gsize;
const int m2 = n1+1, n2 = dsize;
Pt expected1, expected2;
float xsum = 0, ysum = 0;
Pt* data;
hipMallocManaged( &data, dsize * sizeof(Pt) );
bool* moved;
hipMallocManaged( &moved, dsize * sizeof(bool) );
int blockSize = 1024;
int blockNum = (dsize + blockSize - 1) / blockSize;
Pt* dataTemp = new Pt[dsize];
for(int i = 0; i < gsize; ++i)
{
Pt p;
p.x = m1 + rand() % (n1 - m1);
xsum += p.x;
p.y = m1 + rand() % (n1 - m1);
ysum += p.y;
dataTemp[i]=p;
}
expected1.x = xsum/gsize;
expected1.y = ysum/gsize;
xsum = 0, ysum = 0;
for(int i = 0; i < gsize; ++i)
{
Pt p;
p.x = m2 + rand() % (n2 - m2);
xsum += p.x;
p.y = m2 + rand() % (n2 - m2);
ysum += p.y;
dataTemp[i + gsize]=p;
}
expected2.x = xsum/gsize;
expected2.y = ysum/gsize;
hipMemcpy(data,dataTemp, dsize * sizeof( Pt ), hipMemcpyHostToDevice);
hipDeviceSynchronize();
Pt* ctrs = new Pt[2];
ctrs[0].x = m1 + rand() % (n2-m1);
ctrs[0].y = m1 + rand() % (n2-m1);
ctrs[1].x = m1 + rand() % (n2-m1);
ctrs[1].y = m1 + rand() % (n2-m1);
Pt* dev_ctrs;
hipMallocManaged(&dev_ctrs, 2 * sizeof(Pt));
hipMemcpy(dev_ctrs, ctrs, 2 * sizeof( Pt ), hipMemcpyHostToDevice);
float* sums = new float[4];
for(int s = 0; s < 4; ++s) sums[s] = 0;
float* dev_sums;
hipMallocManaged(&dev_sums, 4 * sizeof(float));
int* cnts = new int[2];
cnts[0] = 1; cnts[1] = 1;
int* dev_cnts;
hipMallocManaged(&dev_cnts, 2 * sizeof(int));
bool* isMoved = new bool[1];
isMoved[0] = true;
bool* dev_isMoved;
hipMallocManaged(&dev_isMoved, sizeof(bool));
while( isMoved[0] )
{
printf("Center1 = ( %.2f, %.2f )\n", ctrs[0].x ,ctrs[0].y);
printf("Center2 = ( %.2f, %.2f )\n", ctrs[1].x, ctrs[1].y);
isMoved[0] = false;
clock_t st = clock();
setFalse<<<blockNum, blockSize>>>(moved, dsize);
hipDeviceSynchronize();
Group_find<<<blockNum, blockSize>>>(data, dsize, dev_ctrs, moved);
hipDeviceSynchronize();
hipMemcpy(dev_isMoved, isMoved, sizeof( bool ), hipMemcpyHostToDevice);
Moved_find<<<1, 1>>>(moved, dsize, dev_isMoved);
hipDeviceSynchronize();
hipMemcpy(isMoved, dev_isMoved, sizeof( bool ), hipMemcpyDeviceToHost);
clock_t st2 = clock();
clock_t st3 = 0;
clock_t st4 = 0;
if( isMoved[0] )
{
st3 = clock();
hipMemcpy(dev_sums, sums, 4 * sizeof( float ), hipMemcpyHostToDevice);
hipMemcpy(dev_cnts, cnts, 2 * sizeof( int ), hipMemcpyHostToDevice);
Group_update<<<blockNum, blockSize>>>(data, dsize, dev_sums, dev_cnts);
hipDeviceSynchronize();
hipMemcpy(sums, dev_sums, 4 * sizeof( float ), hipMemcpyDeviceToHost);
hipMemcpy(cnts, dev_cnts, 2 * sizeof( int ), hipMemcpyDeviceToHost);
st4 = clock();
ctrs[0].x = sums[0] / cnts[0];
ctrs[0].y = sums[1] / cnts[0];
ctrs[1].x = sums[2] / cnts[1];
ctrs[1].y = sums[3] / cnts[1];
}
clock_t st5 = clock();
hipMemcpy(ctrs,dev_ctrs, 2 * sizeof( Pt ), hipMemcpyDeviceToHost);
printf("\n Elapsed Time : %u ms \n", clock() - st5 + (st4 - st3) + (st2 - st));
}
printf("---Result---:\n");
printf("Expected1 = ( %.2f, %.2f )\n",expected1.x, expected1.y);
printf("Expected2 = ( %.2f, %.2f )\n", expected2.x, expected2.y);
printf("random initial Center1 = ( %.2f, %.2f )" ,ctrs[0].x ,ctrs[0].y);
printf("random initial Center2 = ( %.2f, %.2f )", ctrs[1].x, ctrs[1].y);
hipFree(&data);
hipFree(&moved);
delete [] dataTemp;
delete [] isMoved;
hipFree( &dev_isMoved);
delete [] sums;
hipFree( &dev_sums);
delete [] cnts;
hipFree( &dev_cnts);
}
__device__ float dist(const Pt& p1, const Pt& p2)
{
float s = sqrt(pow((p1.x - p2.x), 2) + pow((p1.y - p2.y), 2));
return s;
}
__global__ void setFalse(bool*& Changed, int dsize)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < dsize)
{
Changed[index] = false;
}
}
__global__ void Group_find(Pt*& data, int dsize, Pt* dev_ctrs, bool*& moved)
{
int p = blockIdx.x * blockDim.x + threadIdx.x;
if (p < dsize)
{
float d1 = dist(dev_ctrs[0], data[p]);
float d2 = dist(dev_ctrs[1], data[p]);
int oldGroup = data[p].group;
if (d1 < d2)
data[p].group = 1;
else
data[p].group = 2;
if (data[p].group != oldGroup)
{
moved[p] = true;
}
}
}
__global__ void Moved_find(bool* moved, int dsize, bool* dev_isMoved)
{
int index = 0;
while (index < dsize && !dev_isMoved[0])
{
if (moved[index] == true) {
dev_isMoved[0] = true;
}
index++;
}
}
__global__ void Group_update(Pt*& data, int dsize, float* sums, int* cnts)
{
int p = blockIdx.x * blockDim.x + threadIdx.x;
if (p < dsize)
{
if (data[p].group == 1)
{
sums[0] += data[p].x; sums[1] += data[p].y;
cnts[0]++;
}
else
{
sums[2] += data[p].x; sums[3] += data[p].y;
cnts[1]++;
}
}
} | .text
.file "Kmeans.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $10, 4(%rsp)
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r14
movl %r14d, %r15d
shrl $31, %r15d
addl %r14d, %r15d
sarl %r15d
movq %r14, %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rsi
leaq 152(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movslq 4(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movslq 4(%rsp), %rbx
leal 1023(%rbx), %eax
leal 2046(%rbx), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
movl $12, %ecx
movq %rbx, %rax
mulq %rcx
movq $-1, %rdi
cmovnoq %rax, %rdi
callq _Znam
movq %rax, 104(%rsp) # 8-byte Spill
testq %rbx, %rbx
je .LBB0_3
# %bb.1:
leaq (%rbx,%rbx,2), %rax
movq 104(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rax
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq $0, (%rcx)
movl $1, 8(%rcx)
addq $12, %rcx
cmpq %rax, %rcx
jne .LBB0_2
.LBB0_3: # %.loopexit
movl %r15d, %ebx
xorps %xmm1, %xmm1
xorps %xmm0, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
cmpl $2, %r14d
movq %r15, %r13
jl .LBB0_6
# %bb.4: # %.lr.ph.preheader
movq 104(%rsp), %rax # 8-byte Reload
leaq 8(%rax), %r15
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %rbx, %r12
.p2align 4, 0x90
.LBB0_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm1, 16(%rsp) # 4-byte Spill
callq rand
cltd
idivl %r13d
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
movss %xmm1, 96(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq rand
movss 16(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cltd
idivl %r13d
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
addss %xmm0, %xmm1
movss 96(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, -8(%r15)
movss %xmm0, -4(%r15)
movl $1, (%r15)
addq $12, %r15
decq %r12
jne .LBB0_5
.LBB0_6: # %.preheader
movss %xmm1, 16(%rsp) # 4-byte Spill
movq %r13, 200(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
movss %xmm0, 8(%rsp) # 4-byte Spill
cmpl $2, %r14d
xorps %xmm1, %xmm1
jl .LBB0_9
# %bb.7: # %.lr.ph184
movq 200(%rsp), %rax # 8-byte Reload
leal 1(%rax), %r15d
movl %r14d, %r12d
subl %r15d, %r12d
leaq (%rbx,%rbx,2), %rax
movq 104(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
addq $8, %r13
movss %xmm0, 8(%rsp) # 4-byte Spill
.p2align 4, 0x90
.LBB0_8: # =>This Inner Loop Header: Depth=1
movss %xmm1, 20(%rsp) # 4-byte Spill
callq rand
cltd
idivl %r12d
addl %r15d, %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
movss %xmm1, 96(%rsp) # 4-byte Spill
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, 8(%rsp) # 4-byte Spill
callq rand
movss 20(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cltd
idivl %r12d
addl %r15d, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
addss %xmm0, %xmm1
movss 96(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, -8(%r13)
movss %xmm0, -4(%r13)
movl $1, (%r13)
addq $12, %r13
decq %rbx
jne .LBB0_8
.LBB0_9: # %._crit_edge
movss %xmm1, 20(%rsp) # 4-byte Spill
sarl $10, %ebp
movq 152(%rsp), %rdi
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rdx
movq 104(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movl $24, %edi
callq _Znam
movq %rax, %r12
movl $8, %eax
.p2align 4, 0x90
.LBB0_10: # =>This Inner Loop Header: Depth=1
movq $0, -8(%r12,%rax)
movl $1, (%r12,%rax)
addq $12, %rax
cmpq $32, %rax
jne .LBB0_10
# %bb.11:
callq rand
cltd
idivl %r14d
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r12)
callq rand
cltd
idivl %r14d
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, 4(%r12)
callq rand
cltd
idivl %r14d
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, 12(%r12)
callq rand
cltd
idivl %r14d
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, 16(%r12)
leaq 192(%rsp), %rdi
movl $24, %esi
movl $1, %edx
callq hipMallocManaged
movq 192(%rsp), %rdi
movl $24, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl $16, %edi
callq _Znam
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
leaq 136(%rsp), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movl $8, %edi
callq _Znam
movq %rax, %r14
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, (%r14)
leaq 128(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
movl $1, %edi
callq _Znam
movq %rax, %r15
movb $1, (%rax)
leaq 120(%rsp), %rdi
movl $1, %esi
movl $1, %edx
callq hipMallocManaged
cmpb $0, (%r15)
je .LBB0_25
# %bb.12: # %.lr.ph190
movabsq $4294968320, %rcx # imm = 0x100000400
movl %ebp, %eax
movq %rcx, %rbp
addq %rcx, %rax
addq $-1024, %rax # imm = 0xFC00
movq %rax, 208(%rsp) # 8-byte Spill
movq %rbx, 224(%rsp) # 8-byte Spill
movq %r14, 96(%rsp) # 8-byte Spill
movq %r15, 216(%rsp) # 8-byte Spill
jmp .LBB0_13
.p2align 4, 0x90
.LBB0_23: # in Loop: Header=BB0_13 Depth=1
callq hipDeviceSynchronize
movq 136(%rsp), %rsi
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 128(%rsp), %rsi
movl $8, %edx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
cvtsi2ssl (%r13), %xmm0
movq %r13, %rcx
movq %rax, %r13
movss (%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%r12)
movss 4(%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 4(%r12)
movss 8(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtsi2ssl 4(%rcx), %xmm1
divss %xmm1, %xmm0
movss %xmm0, 12(%r12)
movss 12(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
movss %xmm0, 16(%r12)
.LBB0_24: # in Loop: Header=BB0_13 Depth=1
callq clock
movq %rax, %rbx
movq 192(%rsp), %rsi
movl $24, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
addq %r15, %r14
addq %r13, %rbp
addq %rbx, %r14
subq %r14, %rbp
addq %rax, %rbp
movl $.L.str.4, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq printf
movq 216(%rsp), %r15 # 8-byte Reload
cmpb $0, (%r15)
movq 224(%rsp), %rbx # 8-byte Reload
movq 96(%rsp), %r14 # 8-byte Reload
movabsq $4294968320, %rbp # imm = 0x100000400
je .LBB0_25
.LBB0_13: # =>This Inner Loop Header: Depth=1
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.2, %edi
movb $2, %al
callq printf
movss 12(%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 16(%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.3, %edi
movb $2, %al
callq printf
movb $0, (%r15)
callq clock
movq %rax, %r14
movq 208(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14: # in Loop: Header=BB0_13 Depth=1
movl 4(%rsp), %eax
leaq 144(%rsp), %rcx
movq %rcx, 80(%rsp)
movl %eax, 24(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z8setFalseRPbi, %edi
leaq 160(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15: # in Loop: Header=BB0_13 Depth=1
callq hipDeviceSynchronize
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_17
# %bb.16: # in Loop: Header=BB0_13 Depth=1
movl 4(%rsp), %eax
movq 192(%rsp), %rcx
leaq 152(%rsp), %rdx
movq %rdx, 80(%rsp)
movl %eax, 92(%rsp)
movq %rcx, 72(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 92(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10Group_findRP2PtiS0_RPb, %edi
leaq 160(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_17: # in Loop: Header=BB0_13 Depth=1
callq hipDeviceSynchronize
movq 120(%rsp), %rdi
movl $1, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq -1023(%rbp), %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 96(%rsp), %r13 # 8-byte Reload
jne .LBB0_19
# %bb.18: # in Loop: Header=BB0_13 Depth=1
movq 144(%rsp), %rax
movl 4(%rsp), %ecx
movq 120(%rsp), %rdx
movq %rax, 80(%rsp)
movl %ecx, 112(%rsp)
movq %rdx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10Moved_findPbiS_, %edi
leaq 160(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_19: # in Loop: Header=BB0_13 Depth=1
callq hipDeviceSynchronize
movq 120(%rsp), %rsi
movl $1, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
movq %rax, %rbp
cmpb $0, (%r15)
je .LBB0_20
# %bb.21: # in Loop: Header=BB0_13 Depth=1
callq clock
movq %rax, %r15
movq 136(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 128(%rsp), %rdi
movl $8, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 208(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_23
# %bb.22: # in Loop: Header=BB0_13 Depth=1
movl 4(%rsp), %eax
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
leaq 152(%rsp), %rsi
movq %rsi, 80(%rsp)
movl %eax, 92(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 92(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z12Group_updateRP2PtiPfPi, %edi
leaq 160(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_20: # in Loop: Header=BB0_13 Depth=1
xorl %r15d, %r15d
xorl %r13d, %r13d
jmp .LBB0_24
.LBB0_25: # %._crit_edge191
xorps %xmm0, %xmm0
cvtsi2ssl 200(%rsp), %xmm0 # 4-byte Folded Reload
movss 20(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 20(%rsp) # 4-byte Spill
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 8(%rsp) # 4-byte Spill
movss 16(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 16(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
movl $.Lstr, %edi
callq puts@PLT
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 16(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.6, %edi
movb $2, %al
callq printf
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 20(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.7, %edi
movb $2, %al
callq printf
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.8, %edi
movb $2, %al
callq printf
movss 12(%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 16(%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.9, %edi
movb $2, %al
callq printf
leaq 152(%rsp), %rdi
callq hipFree
leaq 144(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
leaq 120(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
leaq 136(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq _ZdaPv
leaq 128(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z23__device_stub__setFalseRPbi # -- Begin function _Z23__device_stub__setFalseRPbi
.p2align 4, 0x90
.type _Z23__device_stub__setFalseRPbi,@function
_Z23__device_stub__setFalseRPbi: # @_Z23__device_stub__setFalseRPbi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8setFalseRPbi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__setFalseRPbi, .Lfunc_end1-_Z23__device_stub__setFalseRPbi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__Group_findRP2PtiS0_RPb # -- Begin function _Z25__device_stub__Group_findRP2PtiS0_RPb
.p2align 4, 0x90
.type _Z25__device_stub__Group_findRP2PtiS0_RPb,@function
_Z25__device_stub__Group_findRP2PtiS0_RPb: # @_Z25__device_stub__Group_findRP2PtiS0_RPb
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10Group_findRP2PtiS0_RPb, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__Group_findRP2PtiS0_RPb, .Lfunc_end2-_Z25__device_stub__Group_findRP2PtiS0_RPb
.cfi_endproc
# -- End function
.globl _Z25__device_stub__Moved_findPbiS_ # -- Begin function _Z25__device_stub__Moved_findPbiS_
.p2align 4, 0x90
.type _Z25__device_stub__Moved_findPbiS_,@function
_Z25__device_stub__Moved_findPbiS_: # @_Z25__device_stub__Moved_findPbiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10Moved_findPbiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z25__device_stub__Moved_findPbiS_, .Lfunc_end3-_Z25__device_stub__Moved_findPbiS_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__Group_updateRP2PtiPfPi # -- Begin function _Z27__device_stub__Group_updateRP2PtiPfPi
.p2align 4, 0x90
.type _Z27__device_stub__Group_updateRP2PtiPfPi,@function
_Z27__device_stub__Group_updateRP2PtiPfPi: # @_Z27__device_stub__Group_updateRP2PtiPfPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12Group_updateRP2PtiPfPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z27__device_stub__Group_updateRP2PtiPfPi, .Lfunc_end4-_Z27__device_stub__Group_updateRP2PtiPfPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8setFalseRPbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10Group_findRP2PtiS0_RPb, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10Moved_findPbiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12Group_updateRP2PtiPfPi, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "enter data size "
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Center1 = ( %.2f, %.2f )\n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Center2 = ( %.2f, %.2f )\n"
.size .L.str.3, 26
.type _Z8setFalseRPbi,@object # @_Z8setFalseRPbi
.section .rodata,"a",@progbits
.globl _Z8setFalseRPbi
.p2align 3, 0x0
_Z8setFalseRPbi:
.quad _Z23__device_stub__setFalseRPbi
.size _Z8setFalseRPbi, 8
.type _Z10Group_findRP2PtiS0_RPb,@object # @_Z10Group_findRP2PtiS0_RPb
.globl _Z10Group_findRP2PtiS0_RPb
.p2align 3, 0x0
_Z10Group_findRP2PtiS0_RPb:
.quad _Z25__device_stub__Group_findRP2PtiS0_RPb
.size _Z10Group_findRP2PtiS0_RPb, 8
.type _Z10Moved_findPbiS_,@object # @_Z10Moved_findPbiS_
.globl _Z10Moved_findPbiS_
.p2align 3, 0x0
_Z10Moved_findPbiS_:
.quad _Z25__device_stub__Moved_findPbiS_
.size _Z10Moved_findPbiS_, 8
.type _Z12Group_updateRP2PtiPfPi,@object # @_Z12Group_updateRP2PtiPfPi
.globl _Z12Group_updateRP2PtiPfPi
.p2align 3, 0x0
_Z12Group_updateRP2PtiPfPi:
.quad _Z27__device_stub__Group_updateRP2PtiPfPi
.size _Z12Group_updateRP2PtiPfPi, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "\n Elapsed Time : %u ms \n"
.size .L.str.4, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Expected1 = ( %.2f, %.2f )\n"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Expected2 = ( %.2f, %.2f )\n"
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "random initial Center1 = ( %.2f, %.2f )"
.size .L.str.8, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "random initial Center2 = ( %.2f, %.2f )"
.size .L.str.9, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8setFalseRPbi"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10Group_findRP2PtiS0_RPb"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10Moved_findPbiS_"
.size .L__unnamed_3, 20
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z12Group_updateRP2PtiPfPi"
.size .L__unnamed_4, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "---Result---:"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__setFalseRPbi
.addrsig_sym _Z25__device_stub__Group_findRP2PtiS0_RPb
.addrsig_sym _Z25__device_stub__Moved_findPbiS_
.addrsig_sym _Z27__device_stub__Group_updateRP2PtiPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8setFalseRPbi
.addrsig_sym _Z10Group_findRP2PtiS0_RPb
.addrsig_sym _Z10Moved_findPbiS_
.addrsig_sym _Z12Group_updateRP2PtiPfPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "reduce.cuh"
#include "real.h"
#include "assert.h"
#include <iostream>
void sumTest(){
real summands[1024];
for (int i=0; i!=1024; ++i)
summands[i]=1;
assert(reducev1(summands,1024) == 1024);
assert(reducev2(summands,1024) == 1024);
}
int main(){
sumTest();
std::cout << "Success!!!\n" << std::flush;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "reduce.cuh"
#include "real.h"
#include "assert.h"
#include <iostream>
void sumTest(){
real summands[1024];
for (int i=0; i!=1024; ++i)
summands[i]=1;
assert(reducev1(summands,1024) == 1024);
assert(reducev2(summands,1024) == 1024);
}
int main(){
sumTest();
std::cout << "Success!!!\n" << std::flush;
} | .file "tmpxft_0008a0ce_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sumTestv
.type _Z7sumTestv, @function
_Z7sumTestv:
.LFB3669:
.cfi_startproc
endbr64
movl $1024, %eax
.L4:
subl $1, %eax
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z7sumTestv, .-_Z7sumTestv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Success!!!\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "reduce.cuh"
#include "real.h"
#include "assert.h"
#include <iostream>
void sumTest(){
real summands[1024];
for (int i=0; i!=1024; ++i)
summands[i]=1;
assert(reducev1(summands,1024) == 1024);
assert(reducev2(summands,1024) == 1024);
}
int main(){
sumTest();
std::cout << "Success!!!\n" << std::flush;
} | #include <hip/hip_runtime.h>
#include "reduce.cuh"
#include "real.h"
#include "assert.h"
#include <iostream>
void sumTest(){
real summands[1024];
for (int i=0; i!=1024; ++i)
summands[i]=1;
assert(reducev1(summands,1024) == 1024);
assert(reducev2(summands,1024) == 1024);
}
int main(){
sumTest();
std::cout << "Success!!!\n" << std::flush;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "reduce.cuh"
#include "real.h"
#include "assert.h"
#include <iostream>
void sumTest(){
real summands[1024];
for (int i=0; i!=1024; ++i)
summands[i]=1;
assert(reducev1(summands,1024) == 1024);
assert(reducev2(summands,1024) == 1024);
}
int main(){
sumTest();
std::cout << "Success!!!\n" << std::flush;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "reduce.cuh"
#include "real.h"
#include "assert.h"
#include <iostream>
void sumTest(){
real summands[1024];
for (int i=0; i!=1024; ++i)
summands[i]=1;
assert(reducev1(summands,1024) == 1024);
assert(reducev2(summands,1024) == 1024);
}
int main(){
sumTest();
std::cout << "Success!!!\n" << std::flush;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7sumTestv # -- Begin function _Z7sumTestv
.p2align 4, 0x90
.type _Z7sumTestv,@function
_Z7sumTestv: # @_Z7sumTestv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z7sumTestv, .Lfunc_end0-_Z7sumTestv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Success!!!\n"
.size .L.str, 12
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008a0ce_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sumTestv
.type _Z7sumTestv, @function
_Z7sumTestv:
.LFB3669:
.cfi_startproc
endbr64
movl $1024, %eax
.L4:
subl $1, %eax
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z7sumTestv, .-_Z7sumTestv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Success!!!\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7sumTestv # -- Begin function _Z7sumTestv
.p2align 4, 0x90
.type _Z7sumTestv,@function
_Z7sumTestv: # @_Z7sumTestv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z7sumTestv, .Lfunc_end0-_Z7sumTestv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Success!!!\n"
.size .L.str, 12
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <algorithm>
#include <cmath>
#include <iostream>
#include <fstream>
#include <ctime>
#include <string>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <thrust/host_vector.h>
#include <thrust/device_ptr.h>
#include <thrust/scan.h>
#include <thrust/reduce.h>
#include <thrust/sort.h>
#define MAX 10
#define MIN 0
#define THREADS_PER_BLOCK 256
#define BITS_IN_BYTE 8
#define FILE_NAME "input1000.txt"
#define K 2
// Different versions for the parallel algorithm
#define RADIX_SORT 0
#define THRUST_SORT 1
#define SORT THRUST_SORT
#define DISTANCE_GATHER 0
#define DISTANCE_MAPREDUCE 1
#define DISTANCE DISTANCE_GATHER
using namespace std;
__global__ void normalize(float * d_input, float *d_max, float *d_min, unsigned int numAttributes,
unsigned int numElems) {
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int attributeIdx = tid % numAttributes;
if(tid < numElems*numAttributes) {
d_input[tid] = (d_input[tid] - d_min[attributeIdx]) / (d_max[attributeIdx] - d_min[attributeIdx]);
}
}
__global__ void findDistanceMap(float *d_inputAttributes, float *d_inputSample, float *d_output, unsigned int numAttributes,
unsigned int numSamples) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < numAttributes * numSamples) {
d_output[tid] = pow(d_inputAttributes[tid] - d_inputSample[tid % numAttributes], 2);
}
}
__global__ void findDistance(float *d_inputAttributes, float *d_inputSample, float *d_output, unsigned int numAttributes,
unsigned int numElems) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
float distance = 0;
if (tid < numElems) {
for (int i = 0; i < numAttributes; i++) {
distance += pow(d_inputAttributes[numAttributes*tid + i] - d_inputSample[i], 2);
}
// OPTIMIZATION: We don't have to square root, because if
// there's no point in wasting all of the distance values are squares
d_output[tid] = distance;
}
}
void distances(float *d_knowns, float* d_unknownSample, float *d_distance,
int numAttributes, int numKnownSamples)
{
if (DISTANCE == DISTANCE_GATHER) {
int threadsPerBlock = THREADS_PER_BLOCK;
int numBlocks = numKnownSamples / threadsPerBlock + 1;
findDistance<<<numBlocks, threadsPerBlock>>>(d_knowns, d_unknownSample, d_distance,
numAttributes, numKnownSamples);
} else if (DISTANCE == DISTANCE_MAPREDUCE) {
// Find the distances between the
float *d_distanceMap;
cudaMalloc(&d_distanceMap, sizeof(float) * numKnownSamples * numAttributes);
float *h_distance = (float*) malloc(sizeof(float) * numKnownSamples);
int threadsPerBlock = THREADS_PER_BLOCK;
int numBlocks = numAttributes * numKnownSamples / threadsPerBlock + 1;
findDistanceMap<<<numBlocks, threadsPerBlock>>>(d_knowns, d_unknownSample, d_distanceMap,
numAttributes, numKnownSamples);
thrust::device_ptr<float> t_distanceMap = thrust::device_pointer_cast(d_distanceMap);
for (int i = 0; i < numKnownSamples; i++) {
h_distance[i] = thrust::reduce(t_distanceMap+(i*numAttributes), t_distanceMap+(i+1)*numAttributes, 0.0);
}
cudaMemcpy(d_distance, h_distance, sizeof(float) * numKnownSamples, cudaMemcpyHostToDevice);
cudaFree(d_distanceMap);
free(h_distance);
}
}
// RADIX Sort helper function
// Map Ones and Zeros
__global__
void mapOnesZeros(unsigned int* const d_ones, unsigned int* const d_zeros, const unsigned int* const d_inputVals,
const unsigned int mask, const size_t numElems) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
// Check if we're outside the bounds of the array
if (myId < numElems) {
if ((d_inputVals[myId] & mask) == 0) {
d_zeros[myId] = 1;
d_ones[myId] = 0;
} else {
d_zeros[myId] = 0;
d_ones[myId] = 1;
}
}
}
// Reorder elements based on their generated positions
__global__
void reorderElements(unsigned int* const d_outputVals, unsigned int* const d_outputClassification,
const unsigned int* const d_inputVals, const unsigned int* const d_inputClassification, const unsigned int* const d_positions_zeros,
const unsigned int* const d_positions_ones, const unsigned int mask, const size_t numElems) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
// Check if we're outside the bounds of the array
if (myId < numElems) {
// Based on if the digit is zero or one depends on which position values
if ((d_inputVals[myId] & mask) == 0) {
d_outputVals[d_positions_zeros[myId]] = d_inputVals[myId];
d_outputClassification[d_positions_zeros[myId]] = d_inputClassification[myId];
} else {
d_outputVals[d_positions_ones[myId]] = d_inputVals[myId];
d_outputClassification[d_positions_ones[myId]] = d_inputClassification[myId];
}
}
}
void radixSort(unsigned int* const d_inputVals,
unsigned int* const d_inputClassification,
unsigned int* const d_outputVals,
unsigned int* const d_outputClassification,
const size_t numElems)
{
// Set the proper grid size and block size for this problem.
int blockSize = THREADS_PER_BLOCK;
int gridSize = numElems / blockSize + 1;
// Iterate over the number of bits in the unsigned int.
for (unsigned int i = 0; i < (sizeof(unsigned int) * BITS_IN_BYTE); i++) {
unsigned int *d_zeros;
unsigned int *d_ones;
cudaMalloc(&d_zeros, sizeof(unsigned int) * numElems);
cudaMalloc(&d_ones, sizeof(unsigned int) * numElems);
// Choose which digit to check currently for our radix
unsigned int mask = 1U << i;
// Find out which digits end in 0, and which digits end in 1
mapOnesZeros<<<gridSize, blockSize>>>(d_ones, d_zeros, d_inputVals, mask, numElems);
// Thrust requires us to copy the memory from Cuda to the host for
// processing.
unsigned int *h_zeros = (unsigned int *) malloc(sizeof(unsigned int) * numElems);
unsigned int *h_ones = (unsigned int *) malloc(sizeof(unsigned int) * numElems);
unsigned int *h_positions_zeros = (unsigned int *) malloc(sizeof(unsigned int) * numElems);
unsigned int *h_positions_ones = (unsigned int *) malloc(sizeof(unsigned int) * numElems);
cudaMemcpy(h_zeros, d_zeros, sizeof(unsigned int) * numElems,
cudaMemcpyDeviceToHost);
cudaMemcpy(h_ones, d_ones, sizeof(unsigned int) * numElems,
cudaMemcpyDeviceToHost);
// Perform an exclusive scan on zeros to determine the position of elements with zero
thrust::exclusive_scan(h_zeros, h_zeros + numElems, h_positions_zeros, 0);
// Determine the position offset to shift the ones positions by
// If the last element's digit is a zero, then it's the last element of d_positions_zeros
// Otherwise, it's just the (last element of the d_positions_zeros array + 1)
unsigned int offset;
if (h_zeros[numElems - 1] == 1) {
offset = h_positions_zeros[numElems - 1] + 1;
} else {
offset = h_positions_zeros[numElems - 1];
}
// Perform an exclusive scan on the ones (with offset) to position elements with one
thrust::exclusive_scan(h_ones, h_ones + numElems, h_positions_ones, offset);
// Copy position elements to the device memory
unsigned int *d_positions_ones;
unsigned int *d_positions_zeros;
cudaMalloc(&d_positions_ones, sizeof(unsigned int) * numElems);
cudaMalloc(&d_positions_zeros, sizeof(unsigned int) * numElems);
cudaMemcpy(d_positions_zeros, h_positions_zeros, sizeof(unsigned int) * numElems,
cudaMemcpyHostToDevice);
cudaMemcpy(d_positions_ones, h_positions_ones, sizeof(unsigned int) * numElems,
cudaMemcpyHostToDevice);
// Now reorder the elements in cuda, based on our position items
reorderElements<<<gridSize, blockSize>>>(d_outputVals, d_outputClassification, d_inputVals, d_inputClassification,
d_positions_zeros, d_positions_ones, mask, numElems);
cudaMemcpy(d_inputVals, d_outputVals, sizeof(unsigned int) * numElems,
cudaMemcpyDeviceToDevice);
cudaMemcpy(d_inputClassification, d_outputClassification, sizeof(unsigned int) * numElems,
cudaMemcpyDeviceToDevice);
// Clear all of our allocated memory
cudaFree(d_positions_ones);
cudaFree(d_positions_zeros);
cudaFree(d_ones);
cudaFree(d_zeros);
free(h_zeros);
free(h_ones);
free(h_positions_ones);
free(h_positions_zeros);
}
}
void sort(unsigned int* const d_inputVals,
unsigned int* const d_inputClassification,
unsigned int* const d_outputVals,
unsigned int* const d_outputClassification,
const size_t numElems)
{
if (SORT == RADIX_SORT) {
radixSort(d_inputVals, d_inputClassification,
d_outputVals,d_outputClassification,
numElems);
} else if (SORT == THRUST_SORT) {
thrust::device_ptr<unsigned int> t_outputClassification = thrust::device_pointer_cast(d_inputClassification);
thrust::device_ptr<unsigned int> t_outputVals = thrust::device_pointer_cast(d_inputVals);
thrust::sort_by_key(t_outputVals, t_outputVals + numElems, t_outputClassification);
cudaMemcpy(d_outputClassification, d_inputClassification, sizeof(float) * numElems, cudaMemcpyDeviceToDevice);
cudaMemcpy(d_outputVals, d_inputVals, sizeof(float) * numElems, cudaMemcpyDeviceToDevice);
}
}
int chooseMajority(int* d_outputClassification, unsigned int length, int numClass) {
int *histogram = new int[numClass];
// Initialize the histogram
for (int i = 0; i < numClass; i++) {
histogram[i] = 0;
}
// Count the values.
for (int i = 0; i < K; i++) {
// Make sure we're not above array bounds
if (i < length) {
histogram[d_outputClassification[i]]++;
}
}
// Find the element of the majority
int maxClass = distance(histogram, max_element(histogram, histogram + numClass));
return maxClass;
}
/*__global__ void block_sum(float *input, float *results, size_t n)
{
extern __shared__ float sdata[];
int i = threadIdx.x + blockDim.x*blockIdx.x;
int tx = threadIdx.x;
// load input into __shared__ memory
float x = 0;
if(i < n) {
x = input[i];
}
sdata[tx] = x;
for(int offset = blockDim.x / 2; offset > 0; offset >>= 1)
{
if(tx < offset)
{
// add a partial sum upstream to our own
sdata[tx] += sdata[tx + offset];
}
__syncthreads();
}
if(tx == 0) {
results[blockIdx.x] =
}
}*/
void parse(int* numAttributes, int* numKnownSamples, int* numClass, int *numUnknowns,
float ** min, float ** max, float ** knowns, int ** classifications,
float ** unknowns, string** unknownNames)
{
ifstream myfile(FILE_NAME, ios::in); // declare and open
int numAttrib, numKnownSamp, numCla, numUn;
myfile >> numKnownSamp >> numAttrib >> numCla >> numUn;
*numAttributes = numAttrib;
*numKnownSamples = numKnownSamp;
*numClass = numCla;
*numUnknowns = numUn;
// Populate all of the mins and maxes
*min = (float*) malloc(sizeof(float) * numAttrib);
*max = (float*) malloc(sizeof(float) * numAttrib);
for (int i = 0; i < numAttrib; i++) {
float currentMax, currentMin;
myfile >> currentMin >> currentMax;
(*min)[i] = currentMin;
(*max)[i] = currentMax;
}
// Populate the known object types
*classifications =(int*) malloc(sizeof(int) * numKnownSamp);
*knowns = (float*) malloc(sizeof(float) * numKnownSamp * numAttrib);
for (int i = 0; i < numKnownSamp; i++) {
int currentClass;
myfile >> currentClass;
(*classifications)[i] = currentClass;
for (int j = 0; j < numAttrib; j++) {
float currentAttrib;
myfile >> currentAttrib;
(*knowns)[i*numAttrib + j] = currentAttrib;
}
}
// Populate the unknown object types
*unknownNames = new string[numUn];
*unknowns = (float*) malloc(sizeof(float) * numUn * numAttrib);
for (int i = 0; i < numUn; i++) {
string currentName;
myfile >> currentName;
(*unknownNames)[i] = currentName;
for (int j = 0; j < numAttrib; j++) {
float currentAttrib;
myfile >> currentAttrib;
(*unknowns)[i*numAttrib + j] = currentAttrib;
}
}
myfile.close();
}
int main() {
unsigned int threadsPerBlock = THREADS_PER_BLOCK;
int numBlocks;
// Metadata about our learning algorithm data
int numAttributes, numKnownSamples, numClass, numUnknowns;
// Data that needs to be sent to the device.
float *h_min, *h_max;
float *h_knowns;
int *h_classifications;
float *h_unknowns;
// Device data
float *d_min, *d_max;
float *d_knowns;
int *d_classifications;
float *d_unknowns;
string *unknownNames;
// Needed for the profiling
std::clock_t start;
std::clock_t kStart;
float totalDuration;
float normalDuration = 0;
float distanceDuration = 0;
float sortDuration = 0;
float majorityDuration = 0;
parse(&numAttributes, &numKnownSamples, &numClass, &numUnknowns,
&h_min, &h_max, &h_knowns, &h_classifications, &h_unknowns, &unknownNames);
start = std::clock();
// Start mallocing the data to the kernel
cudaMalloc(&d_min, sizeof(float) * numAttributes);
cudaMalloc(&d_max, sizeof(float) * numAttributes);
cudaMalloc(&d_knowns, sizeof(float) * numKnownSamples * numAttributes);
cudaMalloc(&d_unknowns, sizeof(float) * numUnknowns * numAttributes);
cudaMalloc(&d_classifications, sizeof(int) * numKnownSamples);
// Copy the data from the host to the kernel
cudaMemcpy(d_min, h_min, sizeof(float) * numAttributes, cudaMemcpyHostToDevice);
cudaMemcpy(d_max, h_max, sizeof(float) * numAttributes, cudaMemcpyHostToDevice);
cudaMemcpy(d_knowns, h_knowns, sizeof(float) * numKnownSamples * numAttributes, cudaMemcpyHostToDevice);
cudaMemcpy(d_unknowns, h_unknowns, sizeof(float) * numUnknowns * numAttributes, cudaMemcpyHostToDevice);
cudaMemcpy(d_classifications, h_classifications, sizeof(int) * numKnownSamples, cudaMemcpyHostToDevice);
kStart = std::clock();
// Normalize the known values
threadsPerBlock = 256;
numBlocks = numAttributes * numKnownSamples / threadsPerBlock + 1;
normalize<<<numBlocks, threadsPerBlock>>>(d_knowns, d_max, d_min,
numAttributes, numKnownSamples);
// Normalize the unknown values
threadsPerBlock = 256;
numBlocks = numAttributes * numKnownSamples / threadsPerBlock + 1;
normalize<<<numBlocks, threadsPerBlock>>>(d_unknowns, d_max, d_min,
numAttributes, numUnknowns);
normalDuration = ( std::clock() - kStart ) / (float) CLOCKS_PER_SEC;
for (int cUn = 0; cUn < numUnknowns; cUn++) {
// Find the distances between the
kStart = std::clock();
float *d_distance;
cudaMalloc(&d_distance, sizeof(float) * numKnownSamples);
distances(d_knowns, d_unknowns+cUn*numAttributes, d_distance, numAttributes, numKnownSamples);
distanceDuration += ( std::clock() - kStart ) / (float) CLOCKS_PER_SEC;
/*float *h_distance = (float*) malloc(sizeof(float) * numKnownSamples);
cudaMemcpy(h_distance, d_distance, sizeof(float) * numKnownSamples, cudaMemcpyDeviceToHost);
for (int i = 0; i < numKnownSamples; i++) {
printf("%f ", h_distance[i]);
}
printf("\n");*/
kStart = std::clock();
int *d_outputClassification;
float *d_outputDistances;
// Perform the sort
cudaMalloc(&d_outputClassification, sizeof(int) * numKnownSamples);
cudaMalloc(&d_outputDistances, sizeof(float) * numKnownSamples);
sort((unsigned int*) d_distance,
(unsigned int*) d_classifications,
(unsigned int*) d_outputDistances,
(unsigned int*) d_outputClassification,
numKnownSamples);
sortDuration += ( std::clock() - kStart ) / (float) CLOCKS_PER_SEC;
kStart = std::clock();
int *h_outputClassifications = (int*) malloc(sizeof(int) * numKnownSamples);
cudaMemcpy(h_outputClassifications, d_outputClassification, sizeof(int) * numKnownSamples, cudaMemcpyDeviceToHost);
/*
float *h_outputDistances = (float*) malloc(sizeof(float) * numKnownSamples);
cudaMemcpy(h_outputDistances, d_outputDistances, sizeof(float) * numKnownSamples, cudaMemcpyDeviceToHost);
for (int i = 0; i < numKnownSamples; i++) {
cout << h_outputClassifications[i] << " " << h_outputDistances[i] << endl;
}*/
//int *h_outputClassifications = (int*) malloc(sizeof(int) * numKnownSamples);
int majority = chooseMajority(h_outputClassifications, numKnownSamples, numClass);
majorityDuration += ( std::clock() - kStart ) / (float) CLOCKS_PER_SEC;
cudaMemcpy(h_outputClassifications, d_outputClassification, sizeof(int) * numKnownSamples, cudaMemcpyDeviceToHost);
//cout << unknownNames[0] << " " << majority << endl;
cudaFree(d_distance);
cudaFree(d_outputClassification);
cudaFree(d_outputDistances);
free(h_outputClassifications);
}
totalDuration = ( std::clock() - start ) / (float) CLOCKS_PER_SEC;
std::cout<<"total Duration: "<< totalDuration <<'\n';
cout << "normal duraton: " << normalDuration << endl;
cout << "distance duration: " << distanceDuration << endl;
cout << "sort duration: " << sortDuration << endl;
cout << "majority duration: " << majorityDuration << endl ;
} | #include <stdio.h>
#include <algorithm>
#include <cmath>
#include <iostream>
#include <fstream>
#include <ctime>
#include <string>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <thrust/host_vector.h>
#include <thrust/device_ptr.h>
#include <thrust/scan.h>
#include <thrust/reduce.h>
#include <thrust/sort.h>
#define MAX 10
#define MIN 0
#define THREADS_PER_BLOCK 256
#define BITS_IN_BYTE 8
#define FILE_NAME "input1000.txt"
#define K 2
// Different versions for the parallel algorithm
#define RADIX_SORT 0
#define THRUST_SORT 1
#define SORT THRUST_SORT
#define DISTANCE_GATHER 0
#define DISTANCE_MAPREDUCE 1
#define DISTANCE DISTANCE_GATHER
using namespace std;
__global__ void normalize(float * d_input, float *d_max, float *d_min, unsigned int numAttributes,
unsigned int numElems) {
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int attributeIdx = tid % numAttributes;
if(tid < numElems*numAttributes) {
d_input[tid] = (d_input[tid] - d_min[attributeIdx]) / (d_max[attributeIdx] - d_min[attributeIdx]);
}
}
__global__ void findDistanceMap(float *d_inputAttributes, float *d_inputSample, float *d_output, unsigned int numAttributes,
unsigned int numSamples) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < numAttributes * numSamples) {
d_output[tid] = pow(d_inputAttributes[tid] - d_inputSample[tid % numAttributes], 2);
}
}
__global__ void findDistance(float *d_inputAttributes, float *d_inputSample, float *d_output, unsigned int numAttributes,
unsigned int numElems) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
float distance = 0;
if (tid < numElems) {
for (int i = 0; i < numAttributes; i++) {
distance += pow(d_inputAttributes[numAttributes*tid + i] - d_inputSample[i], 2);
}
// OPTIMIZATION: We don't have to square root, because if
// there's no point in wasting all of the distance values are squares
d_output[tid] = distance;
}
}
void distances(float *d_knowns, float* d_unknownSample, float *d_distance,
int numAttributes, int numKnownSamples)
{
if (DISTANCE == DISTANCE_GATHER) {
int threadsPerBlock = THREADS_PER_BLOCK;
int numBlocks = numKnownSamples / threadsPerBlock + 1;
findDistance<<<numBlocks, threadsPerBlock>>>(d_knowns, d_unknownSample, d_distance,
numAttributes, numKnownSamples);
} else if (DISTANCE == DISTANCE_MAPREDUCE) {
// Find the distances between the
float *d_distanceMap;
hipMalloc(&d_distanceMap, sizeof(float) * numKnownSamples * numAttributes);
float *h_distance = (float*) malloc(sizeof(float) * numKnownSamples);
int threadsPerBlock = THREADS_PER_BLOCK;
int numBlocks = numAttributes * numKnownSamples / threadsPerBlock + 1;
findDistanceMap<<<numBlocks, threadsPerBlock>>>(d_knowns, d_unknownSample, d_distanceMap,
numAttributes, numKnownSamples);
thrust::device_ptr<float> t_distanceMap = thrust::device_pointer_cast(d_distanceMap);
for (int i = 0; i < numKnownSamples; i++) {
h_distance[i] = thrust::reduce(t_distanceMap+(i*numAttributes), t_distanceMap+(i+1)*numAttributes, 0.0);
}
hipMemcpy(d_distance, h_distance, sizeof(float) * numKnownSamples, hipMemcpyHostToDevice);
hipFree(d_distanceMap);
free(h_distance);
}
}
// RADIX Sort helper function
// Map Ones and Zeros
__global__
void mapOnesZeros(unsigned int* const d_ones, unsigned int* const d_zeros, const unsigned int* const d_inputVals,
const unsigned int mask, const size_t numElems) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
// Check if we're outside the bounds of the array
if (myId < numElems) {
if ((d_inputVals[myId] & mask) == 0) {
d_zeros[myId] = 1;
d_ones[myId] = 0;
} else {
d_zeros[myId] = 0;
d_ones[myId] = 1;
}
}
}
// Reorder elements based on their generated positions
__global__
void reorderElements(unsigned int* const d_outputVals, unsigned int* const d_outputClassification,
const unsigned int* const d_inputVals, const unsigned int* const d_inputClassification, const unsigned int* const d_positions_zeros,
const unsigned int* const d_positions_ones, const unsigned int mask, const size_t numElems) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
// Check if we're outside the bounds of the array
if (myId < numElems) {
// Based on if the digit is zero or one depends on which position values
if ((d_inputVals[myId] & mask) == 0) {
d_outputVals[d_positions_zeros[myId]] = d_inputVals[myId];
d_outputClassification[d_positions_zeros[myId]] = d_inputClassification[myId];
} else {
d_outputVals[d_positions_ones[myId]] = d_inputVals[myId];
d_outputClassification[d_positions_ones[myId]] = d_inputClassification[myId];
}
}
}
void radixSort(unsigned int* const d_inputVals,
unsigned int* const d_inputClassification,
unsigned int* const d_outputVals,
unsigned int* const d_outputClassification,
const size_t numElems)
{
// Set the proper grid size and block size for this problem.
int blockSize = THREADS_PER_BLOCK;
int gridSize = numElems / blockSize + 1;
// Iterate over the number of bits in the unsigned int.
for (unsigned int i = 0; i < (sizeof(unsigned int) * BITS_IN_BYTE); i++) {
unsigned int *d_zeros;
unsigned int *d_ones;
hipMalloc(&d_zeros, sizeof(unsigned int) * numElems);
hipMalloc(&d_ones, sizeof(unsigned int) * numElems);
// Choose which digit to check currently for our radix
unsigned int mask = 1U << i;
// Find out which digits end in 0, and which digits end in 1
mapOnesZeros<<<gridSize, blockSize>>>(d_ones, d_zeros, d_inputVals, mask, numElems);
// Thrust requires us to copy the memory from Cuda to the host for
// processing.
unsigned int *h_zeros = (unsigned int *) malloc(sizeof(unsigned int) * numElems);
unsigned int *h_ones = (unsigned int *) malloc(sizeof(unsigned int) * numElems);
unsigned int *h_positions_zeros = (unsigned int *) malloc(sizeof(unsigned int) * numElems);
unsigned int *h_positions_ones = (unsigned int *) malloc(sizeof(unsigned int) * numElems);
hipMemcpy(h_zeros, d_zeros, sizeof(unsigned int) * numElems,
hipMemcpyDeviceToHost);
hipMemcpy(h_ones, d_ones, sizeof(unsigned int) * numElems,
hipMemcpyDeviceToHost);
// Perform an exclusive scan on zeros to determine the position of elements with zero
thrust::exclusive_scan(h_zeros, h_zeros + numElems, h_positions_zeros, 0);
// Determine the position offset to shift the ones positions by
// If the last element's digit is a zero, then it's the last element of d_positions_zeros
// Otherwise, it's just the (last element of the d_positions_zeros array + 1)
unsigned int offset;
if (h_zeros[numElems - 1] == 1) {
offset = h_positions_zeros[numElems - 1] + 1;
} else {
offset = h_positions_zeros[numElems - 1];
}
// Perform an exclusive scan on the ones (with offset) to position elements with one
thrust::exclusive_scan(h_ones, h_ones + numElems, h_positions_ones, offset);
// Copy position elements to the device memory
unsigned int *d_positions_ones;
unsigned int *d_positions_zeros;
hipMalloc(&d_positions_ones, sizeof(unsigned int) * numElems);
hipMalloc(&d_positions_zeros, sizeof(unsigned int) * numElems);
hipMemcpy(d_positions_zeros, h_positions_zeros, sizeof(unsigned int) * numElems,
hipMemcpyHostToDevice);
hipMemcpy(d_positions_ones, h_positions_ones, sizeof(unsigned int) * numElems,
hipMemcpyHostToDevice);
// Now reorder the elements in cuda, based on our position items
reorderElements<<<gridSize, blockSize>>>(d_outputVals, d_outputClassification, d_inputVals, d_inputClassification,
d_positions_zeros, d_positions_ones, mask, numElems);
hipMemcpy(d_inputVals, d_outputVals, sizeof(unsigned int) * numElems,
hipMemcpyDeviceToDevice);
hipMemcpy(d_inputClassification, d_outputClassification, sizeof(unsigned int) * numElems,
hipMemcpyDeviceToDevice);
// Clear all of our allocated memory
hipFree(d_positions_ones);
hipFree(d_positions_zeros);
hipFree(d_ones);
hipFree(d_zeros);
free(h_zeros);
free(h_ones);
free(h_positions_ones);
free(h_positions_zeros);
}
}
void sort(unsigned int* const d_inputVals,
unsigned int* const d_inputClassification,
unsigned int* const d_outputVals,
unsigned int* const d_outputClassification,
const size_t numElems)
{
if (SORT == RADIX_SORT) {
radixSort(d_inputVals, d_inputClassification,
d_outputVals,d_outputClassification,
numElems);
} else if (SORT == THRUST_SORT) {
thrust::device_ptr<unsigned int> t_outputClassification = thrust::device_pointer_cast(d_inputClassification);
thrust::device_ptr<unsigned int> t_outputVals = thrust::device_pointer_cast(d_inputVals);
thrust::sort_by_key(t_outputVals, t_outputVals + numElems, t_outputClassification);
hipMemcpy(d_outputClassification, d_inputClassification, sizeof(float) * numElems, hipMemcpyDeviceToDevice);
hipMemcpy(d_outputVals, d_inputVals, sizeof(float) * numElems, hipMemcpyDeviceToDevice);
}
}
int chooseMajority(int* d_outputClassification, unsigned int length, int numClass) {
int *histogram = new int[numClass];
// Initialize the histogram
for (int i = 0; i < numClass; i++) {
histogram[i] = 0;
}
// Count the values.
for (int i = 0; i < K; i++) {
// Make sure we're not above array bounds
if (i < length) {
histogram[d_outputClassification[i]]++;
}
}
// Find the element of the majority
int maxClass = distance(histogram, max_element(histogram, histogram + numClass));
return maxClass;
}
/*__global__ void block_sum(float *input, float *results, size_t n)
{
extern __shared__ float sdata[];
int i = threadIdx.x + blockDim.x*blockIdx.x;
int tx = threadIdx.x;
// load input into __shared__ memory
float x = 0;
if(i < n) {
x = input[i];
}
sdata[tx] = x;
for(int offset = blockDim.x / 2; offset > 0; offset >>= 1)
{
if(tx < offset)
{
// add a partial sum upstream to our own
sdata[tx] += sdata[tx + offset];
}
__syncthreads();
}
if(tx == 0) {
results[blockIdx.x] =
}
}*/
void parse(int* numAttributes, int* numKnownSamples, int* numClass, int *numUnknowns,
float ** min, float ** max, float ** knowns, int ** classifications,
float ** unknowns, string** unknownNames)
{
ifstream myfile(FILE_NAME, ios::in); // declare and open
int numAttrib, numKnownSamp, numCla, numUn;
myfile >> numKnownSamp >> numAttrib >> numCla >> numUn;
*numAttributes = numAttrib;
*numKnownSamples = numKnownSamp;
*numClass = numCla;
*numUnknowns = numUn;
// Populate all of the mins and maxes
*min = (float*) malloc(sizeof(float) * numAttrib);
*max = (float*) malloc(sizeof(float) * numAttrib);
for (int i = 0; i < numAttrib; i++) {
float currentMax, currentMin;
myfile >> currentMin >> currentMax;
(*min)[i] = currentMin;
(*max)[i] = currentMax;
}
// Populate the known object types
*classifications =(int*) malloc(sizeof(int) * numKnownSamp);
*knowns = (float*) malloc(sizeof(float) * numKnownSamp * numAttrib);
for (int i = 0; i < numKnownSamp; i++) {
int currentClass;
myfile >> currentClass;
(*classifications)[i] = currentClass;
for (int j = 0; j < numAttrib; j++) {
float currentAttrib;
myfile >> currentAttrib;
(*knowns)[i*numAttrib + j] = currentAttrib;
}
}
// Populate the unknown object types
*unknownNames = new string[numUn];
*unknowns = (float*) malloc(sizeof(float) * numUn * numAttrib);
for (int i = 0; i < numUn; i++) {
string currentName;
myfile >> currentName;
(*unknownNames)[i] = currentName;
for (int j = 0; j < numAttrib; j++) {
float currentAttrib;
myfile >> currentAttrib;
(*unknowns)[i*numAttrib + j] = currentAttrib;
}
}
myfile.close();
}
int main() {
unsigned int threadsPerBlock = THREADS_PER_BLOCK;
int numBlocks;
// Metadata about our learning algorithm data
int numAttributes, numKnownSamples, numClass, numUnknowns;
// Data that needs to be sent to the device.
float *h_min, *h_max;
float *h_knowns;
int *h_classifications;
float *h_unknowns;
// Device data
float *d_min, *d_max;
float *d_knowns;
int *d_classifications;
float *d_unknowns;
string *unknownNames;
// Needed for the profiling
std::clock_t start;
std::clock_t kStart;
float totalDuration;
float normalDuration = 0;
float distanceDuration = 0;
float sortDuration = 0;
float majorityDuration = 0;
parse(&numAttributes, &numKnownSamples, &numClass, &numUnknowns,
&h_min, &h_max, &h_knowns, &h_classifications, &h_unknowns, &unknownNames);
start = std::clock();
// Start mallocing the data to the kernel
hipMalloc(&d_min, sizeof(float) * numAttributes);
hipMalloc(&d_max, sizeof(float) * numAttributes);
hipMalloc(&d_knowns, sizeof(float) * numKnownSamples * numAttributes);
hipMalloc(&d_unknowns, sizeof(float) * numUnknowns * numAttributes);
hipMalloc(&d_classifications, sizeof(int) * numKnownSamples);
// Copy the data from the host to the kernel
hipMemcpy(d_min, h_min, sizeof(float) * numAttributes, hipMemcpyHostToDevice);
hipMemcpy(d_max, h_max, sizeof(float) * numAttributes, hipMemcpyHostToDevice);
hipMemcpy(d_knowns, h_knowns, sizeof(float) * numKnownSamples * numAttributes, hipMemcpyHostToDevice);
hipMemcpy(d_unknowns, h_unknowns, sizeof(float) * numUnknowns * numAttributes, hipMemcpyHostToDevice);
hipMemcpy(d_classifications, h_classifications, sizeof(int) * numKnownSamples, hipMemcpyHostToDevice);
kStart = std::clock();
// Normalize the known values
threadsPerBlock = 256;
numBlocks = numAttributes * numKnownSamples / threadsPerBlock + 1;
normalize<<<numBlocks, threadsPerBlock>>>(d_knowns, d_max, d_min,
numAttributes, numKnownSamples);
// Normalize the unknown values
threadsPerBlock = 256;
numBlocks = numAttributes * numKnownSamples / threadsPerBlock + 1;
normalize<<<numBlocks, threadsPerBlock>>>(d_unknowns, d_max, d_min,
numAttributes, numUnknowns);
normalDuration = ( std::clock() - kStart ) / (float) CLOCKS_PER_SEC;
for (int cUn = 0; cUn < numUnknowns; cUn++) {
// Find the distances between the
kStart = std::clock();
float *d_distance;
hipMalloc(&d_distance, sizeof(float) * numKnownSamples);
distances(d_knowns, d_unknowns+cUn*numAttributes, d_distance, numAttributes, numKnownSamples);
distanceDuration += ( std::clock() - kStart ) / (float) CLOCKS_PER_SEC;
/*float *h_distance = (float*) malloc(sizeof(float) * numKnownSamples);
cudaMemcpy(h_distance, d_distance, sizeof(float) * numKnownSamples, cudaMemcpyDeviceToHost);
for (int i = 0; i < numKnownSamples; i++) {
printf("%f ", h_distance[i]);
}
printf("\n");*/
kStart = std::clock();
int *d_outputClassification;
float *d_outputDistances;
// Perform the sort
hipMalloc(&d_outputClassification, sizeof(int) * numKnownSamples);
hipMalloc(&d_outputDistances, sizeof(float) * numKnownSamples);
sort((unsigned int*) d_distance,
(unsigned int*) d_classifications,
(unsigned int*) d_outputDistances,
(unsigned int*) d_outputClassification,
numKnownSamples);
sortDuration += ( std::clock() - kStart ) / (float) CLOCKS_PER_SEC;
kStart = std::clock();
int *h_outputClassifications = (int*) malloc(sizeof(int) * numKnownSamples);
hipMemcpy(h_outputClassifications, d_outputClassification, sizeof(int) * numKnownSamples, hipMemcpyDeviceToHost);
/*
float *h_outputDistances = (float*) malloc(sizeof(float) * numKnownSamples);
cudaMemcpy(h_outputDistances, d_outputDistances, sizeof(float) * numKnownSamples, cudaMemcpyDeviceToHost);
for (int i = 0; i < numKnownSamples; i++) {
cout << h_outputClassifications[i] << " " << h_outputDistances[i] << endl;
}*/
//int *h_outputClassifications = (int*) malloc(sizeof(int) * numKnownSamples);
int majority = chooseMajority(h_outputClassifications, numKnownSamples, numClass);
majorityDuration += ( std::clock() - kStart ) / (float) CLOCKS_PER_SEC;
hipMemcpy(h_outputClassifications, d_outputClassification, sizeof(int) * numKnownSamples, hipMemcpyDeviceToHost);
//cout << unknownNames[0] << " " << majority << endl;
hipFree(d_distance);
hipFree(d_outputClassification);
hipFree(d_outputDistances);
free(h_outputClassifications);
}
totalDuration = ( std::clock() - start ) / (float) CLOCKS_PER_SEC;
std::cout<<"total Duration: "<< totalDuration <<'\n';
cout << "normal duraton: " << normalDuration << endl;
cout << "distance duration: " << distanceDuration << endl;
cout << "sort duration: " << sortDuration << endl;
cout << "majority duration: " << majorityDuration << endl ;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "basic_conv.cuh"
#include "assert.h"
#include "real.h"
#include <iostream>
void trial(){
constexpr int asize=10^5;
constexpr int bsize=1000;
real A[asize];
for(int i=0; i< asize; i++){
A[i]=1;
}
real M[bsize];
for (int i=0; i<bsize; ++i){
M[i]=i;
}
real P[asize];
basic_conv(A,M,P,bsize,asize);
}
int main(){
trial();
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "basic_conv.cuh"
#include "assert.h"
#include "real.h"
#include <iostream>
void trial(){
constexpr int asize=10^5;
constexpr int bsize=1000;
real A[asize];
for(int i=0; i< asize; i++){
A[i]=1;
}
real M[bsize];
for (int i=0; i<bsize; ++i){
M[i]=i;
}
real P[asize];
basic_conv(A,M,P,bsize,asize);
}
int main(){
trial();
} | .file "tmpxft_000c303d_00000000-6_bconvtrial.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5trialv
.type _Z5trialv, @function
_Z5trialv:
.LFB3669:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $56, %rsp
.cfi_def_cfa_offset 4160
movq %fs:40, %rax
movq %rax, 4136(%rsp)
xorl %eax, %eax
movq %rsp, %rax
leaq 60(%rsp), %rdx
movss .LC0(%rip), %xmm0
.L4:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L4
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 128(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L5
leaq 64(%rsp), %rdx
leaq 128(%rsp), %rsi
movq %rsp, %rdi
movl $15, %r8d
movl $1000, %ecx
call _Z10basic_convPfS_S_ii@PLT
movq 4136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $4152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z5trialv, .-_Z5trialv
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z5trialv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "basic_conv.cuh"
#include "assert.h"
#include "real.h"
#include <iostream>
void trial(){
constexpr int asize=10^5;
constexpr int bsize=1000;
real A[asize];
for(int i=0; i< asize; i++){
A[i]=1;
}
real M[bsize];
for (int i=0; i<bsize; ++i){
M[i]=i;
}
real P[asize];
basic_conv(A,M,P,bsize,asize);
}
int main(){
trial();
} | #include <hip/hip_runtime.h>
#include "basic_conv.cuh"
#include "assert.h"
#include "real.h"
#include <iostream>
void trial(){
constexpr int asize=10^5;
constexpr int bsize=1000;
real A[asize];
for(int i=0; i< asize; i++){
A[i]=1;
}
real M[bsize];
for (int i=0; i<bsize; ++i){
M[i]=i;
}
real P[asize];
basic_conv(A,M,P,bsize,asize);
}
int main(){
trial();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "basic_conv.cuh"
#include "assert.h"
#include "real.h"
#include <iostream>
void trial(){
constexpr int asize=10^5;
constexpr int bsize=1000;
real A[asize];
for(int i=0; i< asize; i++){
A[i]=1;
}
real M[bsize];
for (int i=0; i<bsize; ++i){
M[i]=i;
}
real P[asize];
basic_conv(A,M,P,bsize,asize);
}
int main(){
trial();
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "basic_conv.cuh"
#include "assert.h"
#include "real.h"
#include <iostream>
void trial(){
constexpr int asize=10^5;
constexpr int bsize=1000;
real A[asize];
for(int i=0; i< asize; i++){
A[i]=1;
}
real M[bsize];
for (int i=0; i<bsize; ++i){
M[i]=i;
}
real P[asize];
basic_conv(A,M,P,bsize,asize);
}
int main(){
trial();
} | .text
.file "bconvtrial.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5trialv # -- Begin function _Z5trialv
.p2align 4, 0x90
.type _Z5trialv,@function
_Z5trialv: # @_Z5trialv
.cfi_startproc
# %bb.0:
subq $4136, %rsp # imm = 0x1028
.cfi_def_cfa_offset 4144
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $15, %rax
jne .LBB0_1
# %bb.2:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 128(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_3
# %bb.4:
movq %rsp, %rdi
leaq 128(%rsp), %rsi
leaq 64(%rsp), %rdx
movl $1000, %ecx # imm = 0x3E8
movl $15, %r8d
callq _Z10basic_convPfS_S_ii
addq $4136, %rsp # imm = 0x1028
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5trialv, .Lfunc_end0-_Z5trialv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $4136, %rsp # imm = 0x1028
.cfi_def_cfa_offset 4144
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $15, %rax
jne .LBB1_1
# %bb.2:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 128(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_3
# %bb.4: # %_Z5trialv.exit
movq %rsp, %rdi
leaq 128(%rsp), %rsi
leaq 64(%rsp), %rdx
movl $1000, %ecx # imm = 0x3E8
movl $15, %r8d
callq _Z10basic_convPfS_S_ii
xorl %eax, %eax
addq $4136, %rsp # imm = 0x1028
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c303d_00000000-6_bconvtrial.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5trialv
.type _Z5trialv, @function
_Z5trialv:
.LFB3669:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $56, %rsp
.cfi_def_cfa_offset 4160
movq %fs:40, %rax
movq %rax, 4136(%rsp)
xorl %eax, %eax
movq %rsp, %rax
leaq 60(%rsp), %rdx
movss .LC0(%rip), %xmm0
.L4:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L4
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 128(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L5
leaq 64(%rsp), %rdx
leaq 128(%rsp), %rsi
movq %rsp, %rdi
movl $15, %r8d
movl $1000, %ecx
call _Z10basic_convPfS_S_ii@PLT
movq 4136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $4152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z5trialv, .-_Z5trialv
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z5trialv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bconvtrial.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5trialv # -- Begin function _Z5trialv
.p2align 4, 0x90
.type _Z5trialv,@function
_Z5trialv: # @_Z5trialv
.cfi_startproc
# %bb.0:
subq $4136, %rsp # imm = 0x1028
.cfi_def_cfa_offset 4144
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $15, %rax
jne .LBB0_1
# %bb.2:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 128(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_3
# %bb.4:
movq %rsp, %rdi
leaq 128(%rsp), %rsi
leaq 64(%rsp), %rdx
movl $1000, %ecx # imm = 0x3E8
movl $15, %r8d
callq _Z10basic_convPfS_S_ii
addq $4136, %rsp # imm = 0x1028
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5trialv, .Lfunc_end0-_Z5trialv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $4136, %rsp # imm = 0x1028
.cfi_def_cfa_offset 4144
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $15, %rax
jne .LBB1_1
# %bb.2:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 128(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_3
# %bb.4: # %_Z5trialv.exit
movq %rsp, %rdi
leaq 128(%rsp), %rsi
leaq 64(%rsp), %rdx
movl $1000, %ecx # imm = 0x3E8
movl $15, %r8d
callq _Z10basic_convPfS_S_ii
xorl %eax, %eax
addq $4136, %rsp # imm = 0x1028
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // codigo incrementa e depois decrementa valores de um vetor.
//
// este codigo exemplifica o uso de __syncthreads() e
// o uso de memoria compartilhada criada estaticamente
// e dinamicamente.
//
// a primeira grade incrementa as posicoes de um vetor
// N vezes por thread. Usa memoria compartilhada criada estaticamente
//
// a segunda grade decrementa da mesma forma.
// o vetor comeca com vlrs 0 (zero) e termina com 0 (zero).
// Usa memória compartilhada criada dinâmicamente.
//
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
// no maximo 1024, pois determina o nr de threads no bloco
#define N 1024
__global__ void staticShdMem(int *vetD_glb)
{
// criacao estatica na memoria compartilhada
__shared__ int vetD_shd[N];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread incrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux++;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
__global__ void dynamicShdMem(int *vetD_glb)
{
// criacao dinamica na memoria compartilhada
extern __shared__ int vetD_shd[];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread decrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux--;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
int main(void)
{
int vetA_h[N], vetD_h[N];
int *vetD_d;
int i;
for (i = 0; i < N; i++) {
vetA_h[i] = 0;
}
cudaMalloc(&vetD_d, N * sizeof(int));
cudaMemcpy(vetD_d, vetA_h, N*sizeof(int), cudaMemcpyHostToDevice);
// algoritmo so funciona se as threads estiverem no mesmo bloco
// devido a limitacao do __syncthreads()
// invoca a versao com memoria compartilhada criada estaticamente
staticShdMem<<<1,N>>>(vetD_d);
cudaMemcpy(vetD_h, vetD_d, N*sizeof(int), cudaMemcpyDeviceToHost);
printf("Static Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
// nao eh necessario copiar o vetor d do host para o device.
// a grade anterior fez essa copia e o conteudo dele ainda esta no device
// cudaMemcpy(vetD_d, vetD_h, N*sizeof(int), cudaMemcpyHostToDevice);
// invoca a versao com memoria compartilhada criada dinamicamente
dynamicShdMem<<<1,N,(N*sizeof(int))>>>(vetD_d);
cudaMemcpy(vetD_h, vetD_d, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("Dynamic Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
//Desaloca vetor no device
cudaFree(vetD_d);
exit(0);
} | .file "tmpxft_000e3939_00000000-6_06-soma-sync.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z12staticShdMemPiPi
.type _Z32__device_stub__Z12staticShdMemPiPi, @function
_Z32__device_stub__Z12staticShdMemPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12staticShdMemPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z12staticShdMemPiPi, .-_Z32__device_stub__Z12staticShdMemPiPi
.globl _Z12staticShdMemPi
.type _Z12staticShdMemPi, @function
_Z12staticShdMemPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12staticShdMemPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12staticShdMemPi, .-_Z12staticShdMemPi
.globl _Z33__device_stub__Z13dynamicShdMemPiPi
.type _Z33__device_stub__Z13dynamicShdMemPiPi, @function
_Z33__device_stub__Z13dynamicShdMemPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13dynamicShdMemPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z13dynamicShdMemPiPi, .-_Z33__device_stub__Z13dynamicShdMemPiPi
.globl _Z13dynamicShdMemPi
.type _Z13dynamicShdMemPi, @function
_Z13dynamicShdMemPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13dynamicShdMemPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13dynamicShdMemPi, .-_Z13dynamicShdMemPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Static Results(%d): "
.LC1:
.string "%d "
.LC2:
.string "\n\n"
.LC3:
.string "Dynamic Results(%d): "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $4096, %rsp
.cfi_def_cfa_offset 4136
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8232
orq $0, (%rsp)
subq $56, %rsp
.cfi_def_cfa_offset 8288
movq %fs:40, %rax
movq %rax, 8232(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rax
leaq 4128(%rsp), %rdx
.L20:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L21:
leaq 4128(%rsp), %rbx
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1024, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rbp
leaq 8224(%rsp), %r12
leaq .LC1(%rip), %r13
.L22:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L22
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L23:
leaq 4128(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $1024, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rbx
.L24:
movl 0(%rbp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L24
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %edi
call exit@PLT
.L30:
movq (%rsp), %rdi
call _Z32__device_stub__Z12staticShdMemPiPi
jmp .L21
.L31:
movq (%rsp), %rdi
call _Z33__device_stub__Z13dynamicShdMemPiPi
jmp .L23
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13dynamicShdMemPi"
.LC5:
.string "_Z12staticShdMemPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13dynamicShdMemPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12staticShdMemPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // codigo incrementa e depois decrementa valores de um vetor.
//
// este codigo exemplifica o uso de __syncthreads() e
// o uso de memoria compartilhada criada estaticamente
// e dinamicamente.
//
// a primeira grade incrementa as posicoes de um vetor
// N vezes por thread. Usa memoria compartilhada criada estaticamente
//
// a segunda grade decrementa da mesma forma.
// o vetor comeca com vlrs 0 (zero) e termina com 0 (zero).
// Usa memória compartilhada criada dinâmicamente.
//
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
// no maximo 1024, pois determina o nr de threads no bloco
#define N 1024
__global__ void staticShdMem(int *vetD_glb)
{
// criacao estatica na memoria compartilhada
__shared__ int vetD_shd[N];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread incrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux++;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
__global__ void dynamicShdMem(int *vetD_glb)
{
// criacao dinamica na memoria compartilhada
extern __shared__ int vetD_shd[];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread decrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux--;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
int main(void)
{
int vetA_h[N], vetD_h[N];
int *vetD_d;
int i;
for (i = 0; i < N; i++) {
vetA_h[i] = 0;
}
cudaMalloc(&vetD_d, N * sizeof(int));
cudaMemcpy(vetD_d, vetA_h, N*sizeof(int), cudaMemcpyHostToDevice);
// algoritmo so funciona se as threads estiverem no mesmo bloco
// devido a limitacao do __syncthreads()
// invoca a versao com memoria compartilhada criada estaticamente
staticShdMem<<<1,N>>>(vetD_d);
cudaMemcpy(vetD_h, vetD_d, N*sizeof(int), cudaMemcpyDeviceToHost);
printf("Static Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
// nao eh necessario copiar o vetor d do host para o device.
// a grade anterior fez essa copia e o conteudo dele ainda esta no device
// cudaMemcpy(vetD_d, vetD_h, N*sizeof(int), cudaMemcpyHostToDevice);
// invoca a versao com memoria compartilhada criada dinamicamente
dynamicShdMem<<<1,N,(N*sizeof(int))>>>(vetD_d);
cudaMemcpy(vetD_h, vetD_d, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("Dynamic Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
//Desaloca vetor no device
cudaFree(vetD_d);
exit(0);
} | // codigo incrementa e depois decrementa valores de um vetor.
//
// este codigo exemplifica o uso de __syncthreads() e
// o uso de memoria compartilhada criada estaticamente
// e dinamicamente.
//
// a primeira grade incrementa as posicoes de um vetor
// N vezes por thread. Usa memoria compartilhada criada estaticamente
//
// a segunda grade decrementa da mesma forma.
// o vetor comeca com vlrs 0 (zero) e termina com 0 (zero).
// Usa memória compartilhada criada dinâmicamente.
//
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
// no maximo 1024, pois determina o nr de threads no bloco
#define N 1024
__global__ void staticShdMem(int *vetD_glb)
{
// criacao estatica na memoria compartilhada
__shared__ int vetD_shd[N];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread incrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux++;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
__global__ void dynamicShdMem(int *vetD_glb)
{
// criacao dinamica na memoria compartilhada
extern __shared__ int vetD_shd[];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread decrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux--;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
int main(void)
{
int vetA_h[N], vetD_h[N];
int *vetD_d;
int i;
for (i = 0; i < N; i++) {
vetA_h[i] = 0;
}
hipMalloc(&vetD_d, N * sizeof(int));
hipMemcpy(vetD_d, vetA_h, N*sizeof(int), hipMemcpyHostToDevice);
// algoritmo so funciona se as threads estiverem no mesmo bloco
// devido a limitacao do __syncthreads()
// invoca a versao com memoria compartilhada criada estaticamente
staticShdMem<<<1,N>>>(vetD_d);
hipMemcpy(vetD_h, vetD_d, N*sizeof(int), hipMemcpyDeviceToHost);
printf("Static Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
// nao eh necessario copiar o vetor d do host para o device.
// a grade anterior fez essa copia e o conteudo dele ainda esta no device
// cudaMemcpy(vetD_d, vetD_h, N*sizeof(int), cudaMemcpyHostToDevice);
// invoca a versao com memoria compartilhada criada dinamicamente
dynamicShdMem<<<1,N,(N*sizeof(int))>>>(vetD_d);
hipMemcpy(vetD_h, vetD_d, N * sizeof(int), hipMemcpyDeviceToHost);
printf("Dynamic Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
//Desaloca vetor no device
hipFree(vetD_d);
exit(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // codigo incrementa e depois decrementa valores de um vetor.
//
// este codigo exemplifica o uso de __syncthreads() e
// o uso de memoria compartilhada criada estaticamente
// e dinamicamente.
//
// a primeira grade incrementa as posicoes de um vetor
// N vezes por thread. Usa memoria compartilhada criada estaticamente
//
// a segunda grade decrementa da mesma forma.
// o vetor comeca com vlrs 0 (zero) e termina com 0 (zero).
// Usa memória compartilhada criada dinâmicamente.
//
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
// no maximo 1024, pois determina o nr de threads no bloco
#define N 1024
__global__ void staticShdMem(int *vetD_glb)
{
// criacao estatica na memoria compartilhada
__shared__ int vetD_shd[N];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread incrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux++;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
__global__ void dynamicShdMem(int *vetD_glb)
{
// criacao dinamica na memoria compartilhada
extern __shared__ int vetD_shd[];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread decrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux--;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
int main(void)
{
int vetA_h[N], vetD_h[N];
int *vetD_d;
int i;
for (i = 0; i < N; i++) {
vetA_h[i] = 0;
}
hipMalloc(&vetD_d, N * sizeof(int));
hipMemcpy(vetD_d, vetA_h, N*sizeof(int), hipMemcpyHostToDevice);
// algoritmo so funciona se as threads estiverem no mesmo bloco
// devido a limitacao do __syncthreads()
// invoca a versao com memoria compartilhada criada estaticamente
staticShdMem<<<1,N>>>(vetD_d);
hipMemcpy(vetD_h, vetD_d, N*sizeof(int), hipMemcpyDeviceToHost);
printf("Static Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
// nao eh necessario copiar o vetor d do host para o device.
// a grade anterior fez essa copia e o conteudo dele ainda esta no device
// cudaMemcpy(vetD_d, vetD_h, N*sizeof(int), cudaMemcpyHostToDevice);
// invoca a versao com memoria compartilhada criada dinamicamente
dynamicShdMem<<<1,N,(N*sizeof(int))>>>(vetD_d);
hipMemcpy(vetD_h, vetD_d, N * sizeof(int), hipMemcpyDeviceToHost);
printf("Dynamic Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
//Desaloca vetor no device
hipFree(vetD_d);
exit(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12staticShdMemPi
.globl _Z12staticShdMemPi
.p2align 8
.type _Z12staticShdMemPi,@function
_Z12staticShdMemPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
v_xor_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v2, s[0:1]
v_add_co_u32 v0, s0, s0, v2
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
s_movk_i32 s0, 0x400
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v3
s_add_i32 s0, s0, -1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s0, 0
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v4, 1, v4
ds_store_b32 v2, v4
s_cbranch_scc1 .LBB0_1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12staticShdMemPi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12staticShdMemPi, .Lfunc_end0-_Z12staticShdMemPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13dynamicShdMemPi
.globl _Z13dynamicShdMemPi
.p2align 8
.type _Z13dynamicShdMemPi,@function
_Z13dynamicShdMemPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
v_xor_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 2, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v2, s[0:1]
v_add_co_u32 v0, s0, s0, v2
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_add_nc_u32_e32 v2, 0, v2
s_movk_i32 s0, 0x400
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
.LBB1_1:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v3
s_add_i32 s0, s0, -1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s0, 0
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v4, -1, v4
ds_store_b32 v2, v4
s_cbranch_scc1 .LBB1_1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13dynamicShdMemPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13dynamicShdMemPi, .Lfunc_end1-_Z13dynamicShdMemPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12staticShdMemPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z12staticShdMemPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13dynamicShdMemPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z13dynamicShdMemPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // codigo incrementa e depois decrementa valores de um vetor.
//
// este codigo exemplifica o uso de __syncthreads() e
// o uso de memoria compartilhada criada estaticamente
// e dinamicamente.
//
// a primeira grade incrementa as posicoes de um vetor
// N vezes por thread. Usa memoria compartilhada criada estaticamente
//
// a segunda grade decrementa da mesma forma.
// o vetor comeca com vlrs 0 (zero) e termina com 0 (zero).
// Usa memória compartilhada criada dinâmicamente.
//
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
// no maximo 1024, pois determina o nr de threads no bloco
#define N 1024
__global__ void staticShdMem(int *vetD_glb)
{
// criacao estatica na memoria compartilhada
__shared__ int vetD_shd[N];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread incrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux++;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
__global__ void dynamicShdMem(int *vetD_glb)
{
// criacao dinamica na memoria compartilhada
extern __shared__ int vetD_shd[];
int t = threadIdx.x;
int i, aux;
// transfere dado da memoria global para a mem shd
// as N threads fazem isso
vetD_shd[t] = vetD_glb[t];
// cada thread decrementa N vezes cada posicao t
for (i = 0; i < N; i++)
{
__syncthreads(); // sync necessaria
aux = vetD_shd[N-t-1];
aux--;
__syncthreads(); // apenas esta sync produz resultados errados
vetD_shd[t] = aux;
}
// Retorna resultado para memoria global.
// Executado por todas as N threads.
vetD_glb[t] = vetD_shd[t];
}
int main(void)
{
int vetA_h[N], vetD_h[N];
int *vetD_d;
int i;
for (i = 0; i < N; i++) {
vetA_h[i] = 0;
}
hipMalloc(&vetD_d, N * sizeof(int));
hipMemcpy(vetD_d, vetA_h, N*sizeof(int), hipMemcpyHostToDevice);
// algoritmo so funciona se as threads estiverem no mesmo bloco
// devido a limitacao do __syncthreads()
// invoca a versao com memoria compartilhada criada estaticamente
staticShdMem<<<1,N>>>(vetD_d);
hipMemcpy(vetD_h, vetD_d, N*sizeof(int), hipMemcpyDeviceToHost);
printf("Static Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
// nao eh necessario copiar o vetor d do host para o device.
// a grade anterior fez essa copia e o conteudo dele ainda esta no device
// cudaMemcpy(vetD_d, vetD_h, N*sizeof(int), cudaMemcpyHostToDevice);
// invoca a versao com memoria compartilhada criada dinamicamente
dynamicShdMem<<<1,N,(N*sizeof(int))>>>(vetD_d);
hipMemcpy(vetD_h, vetD_d, N * sizeof(int), hipMemcpyDeviceToHost);
printf("Dynamic Results(%d): ", N);
for (i = 0; i < N; i++)
printf("%d ", vetD_h[i]);
printf("\n\n");
//Desaloca vetor no device
hipFree(vetD_d);
exit(0);
} | .text
.file "06-soma-sync.hip"
.globl _Z27__device_stub__staticShdMemPi # -- Begin function _Z27__device_stub__staticShdMemPi
.p2align 4, 0x90
.type _Z27__device_stub__staticShdMemPi,@function
_Z27__device_stub__staticShdMemPi: # @_Z27__device_stub__staticShdMemPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12staticShdMemPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z27__device_stub__staticShdMemPi, .Lfunc_end0-_Z27__device_stub__staticShdMemPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__dynamicShdMemPi # -- Begin function _Z28__device_stub__dynamicShdMemPi
.p2align 4, 0x90
.type _Z28__device_stub__dynamicShdMemPi,@function
_Z28__device_stub__dynamicShdMemPi: # @_Z28__device_stub__dynamicShdMemPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13dynamicShdMemPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z28__device_stub__dynamicShdMemPi, .Lfunc_end1-_Z28__device_stub__dynamicShdMemPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $8288, %rsp # imm = 0x2060
.cfi_def_cfa_offset 8320
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 4192(%rsp), %r14
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 1023(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 64(%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, 64(%rsp)
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12staticShdMemPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_3
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
movl $4096, %r8d # imm = 0x1000
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13dynamicShdMemPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movl $.L.str.3, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB2_7
# %bb.8:
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12staticShdMemPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13dynamicShdMemPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12staticShdMemPi,@object # @_Z12staticShdMemPi
.section .rodata,"a",@progbits
.globl _Z12staticShdMemPi
.p2align 3, 0x0
_Z12staticShdMemPi:
.quad _Z27__device_stub__staticShdMemPi
.size _Z12staticShdMemPi, 8
.type _Z13dynamicShdMemPi,@object # @_Z13dynamicShdMemPi
.globl _Z13dynamicShdMemPi
.p2align 3, 0x0
_Z13dynamicShdMemPi:
.quad _Z28__device_stub__dynamicShdMemPi
.size _Z13dynamicShdMemPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Static Results(%d): "
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Dynamic Results(%d): "
.size .L.str.3, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12staticShdMemPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13dynamicShdMemPi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__staticShdMemPi
.addrsig_sym _Z28__device_stub__dynamicShdMemPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12staticShdMemPi
.addrsig_sym _Z13dynamicShdMemPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e3939_00000000-6_06-soma-sync.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z12staticShdMemPiPi
.type _Z32__device_stub__Z12staticShdMemPiPi, @function
_Z32__device_stub__Z12staticShdMemPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12staticShdMemPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z12staticShdMemPiPi, .-_Z32__device_stub__Z12staticShdMemPiPi
.globl _Z12staticShdMemPi
.type _Z12staticShdMemPi, @function
_Z12staticShdMemPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12staticShdMemPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12staticShdMemPi, .-_Z12staticShdMemPi
.globl _Z33__device_stub__Z13dynamicShdMemPiPi
.type _Z33__device_stub__Z13dynamicShdMemPiPi, @function
_Z33__device_stub__Z13dynamicShdMemPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13dynamicShdMemPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z13dynamicShdMemPiPi, .-_Z33__device_stub__Z13dynamicShdMemPiPi
.globl _Z13dynamicShdMemPi
.type _Z13dynamicShdMemPi, @function
_Z13dynamicShdMemPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13dynamicShdMemPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13dynamicShdMemPi, .-_Z13dynamicShdMemPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Static Results(%d): "
.LC1:
.string "%d "
.LC2:
.string "\n\n"
.LC3:
.string "Dynamic Results(%d): "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $4096, %rsp
.cfi_def_cfa_offset 4136
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8232
orq $0, (%rsp)
subq $56, %rsp
.cfi_def_cfa_offset 8288
movq %fs:40, %rax
movq %rax, 8232(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rax
leaq 4128(%rsp), %rdx
.L20:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L21:
leaq 4128(%rsp), %rbx
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1024, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rbp
leaq 8224(%rsp), %r12
leaq .LC1(%rip), %r13
.L22:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L22
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L23:
leaq 4128(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $1024, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rbx
.L24:
movl 0(%rbp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L24
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %edi
call exit@PLT
.L30:
movq (%rsp), %rdi
call _Z32__device_stub__Z12staticShdMemPiPi
jmp .L21
.L31:
movq (%rsp), %rdi
call _Z33__device_stub__Z13dynamicShdMemPiPi
jmp .L23
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13dynamicShdMemPi"
.LC5:
.string "_Z12staticShdMemPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13dynamicShdMemPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12staticShdMemPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "06-soma-sync.hip"
.globl _Z27__device_stub__staticShdMemPi # -- Begin function _Z27__device_stub__staticShdMemPi
.p2align 4, 0x90
.type _Z27__device_stub__staticShdMemPi,@function
_Z27__device_stub__staticShdMemPi: # @_Z27__device_stub__staticShdMemPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12staticShdMemPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z27__device_stub__staticShdMemPi, .Lfunc_end0-_Z27__device_stub__staticShdMemPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__dynamicShdMemPi # -- Begin function _Z28__device_stub__dynamicShdMemPi
.p2align 4, 0x90
.type _Z28__device_stub__dynamicShdMemPi,@function
_Z28__device_stub__dynamicShdMemPi: # @_Z28__device_stub__dynamicShdMemPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13dynamicShdMemPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z28__device_stub__dynamicShdMemPi, .Lfunc_end1-_Z28__device_stub__dynamicShdMemPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $8288, %rsp # imm = 0x2060
.cfi_def_cfa_offset 8320
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 4192(%rsp), %r14
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 1023(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 64(%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, 64(%rsp)
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12staticShdMemPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_3
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
movl $4096, %r8d # imm = 0x1000
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13dynamicShdMemPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movl $.L.str.3, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB2_7
# %bb.8:
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12staticShdMemPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13dynamicShdMemPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12staticShdMemPi,@object # @_Z12staticShdMemPi
.section .rodata,"a",@progbits
.globl _Z12staticShdMemPi
.p2align 3, 0x0
_Z12staticShdMemPi:
.quad _Z27__device_stub__staticShdMemPi
.size _Z12staticShdMemPi, 8
.type _Z13dynamicShdMemPi,@object # @_Z13dynamicShdMemPi
.globl _Z13dynamicShdMemPi
.p2align 3, 0x0
_Z13dynamicShdMemPi:
.quad _Z28__device_stub__dynamicShdMemPi
.size _Z13dynamicShdMemPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Static Results(%d): "
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Dynamic Results(%d): "
.size .L.str.3, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12staticShdMemPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13dynamicShdMemPi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__staticShdMemPi
.addrsig_sym _Z28__device_stub__dynamicShdMemPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12staticShdMemPi
.addrsig_sym _Z13dynamicShdMemPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include <malloc.h>
#include <stdlib.h>
#define N 1000
void MatrixMul(int *A, int *B, int *C, int Width) {
int i, j, k;
for(i=0; i<Width; i++)
for(j=0; j<Width; j++){
int s=0;
for(k=0; k<Width; k++)
s+=A[i*Width+k]*B[k*Width+j];
C[i*Width+j]=s;
}
}
#define TILE_WIDTH 16
__global__ void KernelMatrixMul(int* Md, int* Nd, int* Pd, int Width)
{
int x = threadIdx.x+blockIdx.x*blockDim.x;
int y = threadIdx.y+blockIdx.y*blockDim.y;
int Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue+=Md[y * Width + k]*Nd[k * Width + x];
Pd[y*Width + x] = Pvalue;
}
int main(){
int *A=(int*)malloc(N*N*sizeof(int));
int *B=(int*)malloc(N*N*sizeof(int));
int *C=(int*)malloc(N*N*sizeof(int));
int i;
for(i=0;i<N*N;i++){
A[i] = 1;
B[i] = 2;
}
//MatrixMul(A,B,C,N);
int *dev_A,*dev_B,*dev_C;
dim3 dimGrid(N/TILE_WIDTH,N/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH,TILE_WIDTH);
cudaMalloc((void**)&dev_A,N*N*sizeof(int));
cudaMalloc((void**)&dev_B,N*N*sizeof(int));
cudaMalloc((void**)&dev_C,N*N*sizeof(int));
cudaMemcpy(dev_A,A,N*N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_B,B,N*N*sizeof(int),cudaMemcpyHostToDevice);
KernelMatrixMul<<<dimGrid,dimBlock>>>(dev_A,dev_B,dev_C,N);
cudaThreadSynchronize();
cudaMemcpy(C,dev_C,N*N*sizeof(int),cudaMemcpyDeviceToHost);
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
int m,n;
for(m=0;m<N;m++){
for(n=0;n<N;n++)
printf("C[%d][%d] = %d\n",m,n,C[m*N+n]);
}
return 0;
} | code for sm_80
Function : _Z15KernelMatrixMulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include <malloc.h>
#include <stdlib.h>
#define N 1000
void MatrixMul(int *A, int *B, int *C, int Width) {
int i, j, k;
for(i=0; i<Width; i++)
for(j=0; j<Width; j++){
int s=0;
for(k=0; k<Width; k++)
s+=A[i*Width+k]*B[k*Width+j];
C[i*Width+j]=s;
}
}
#define TILE_WIDTH 16
__global__ void KernelMatrixMul(int* Md, int* Nd, int* Pd, int Width)
{
int x = threadIdx.x+blockIdx.x*blockDim.x;
int y = threadIdx.y+blockIdx.y*blockDim.y;
int Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue+=Md[y * Width + k]*Nd[k * Width + x];
Pd[y*Width + x] = Pvalue;
}
int main(){
int *A=(int*)malloc(N*N*sizeof(int));
int *B=(int*)malloc(N*N*sizeof(int));
int *C=(int*)malloc(N*N*sizeof(int));
int i;
for(i=0;i<N*N;i++){
A[i] = 1;
B[i] = 2;
}
//MatrixMul(A,B,C,N);
int *dev_A,*dev_B,*dev_C;
dim3 dimGrid(N/TILE_WIDTH,N/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH,TILE_WIDTH);
cudaMalloc((void**)&dev_A,N*N*sizeof(int));
cudaMalloc((void**)&dev_B,N*N*sizeof(int));
cudaMalloc((void**)&dev_C,N*N*sizeof(int));
cudaMemcpy(dev_A,A,N*N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_B,B,N*N*sizeof(int),cudaMemcpyHostToDevice);
KernelMatrixMul<<<dimGrid,dimBlock>>>(dev_A,dev_B,dev_C,N);
cudaThreadSynchronize();
cudaMemcpy(C,dev_C,N*N*sizeof(int),cudaMemcpyDeviceToHost);
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
int m,n;
for(m=0;m<N;m++){
for(n=0;n<N;n++)
printf("C[%d][%d] = %d\n",m,n,C[m*N+n]);
}
return 0;
} | .file "tmpxft_001293f1_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9MatrixMulPiS_S_i
.type _Z9MatrixMulPiS_S_i, @function
_Z9MatrixMulPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r8
movq %rsi, %rbp
movq %rdx, %r11
movl %ecx, %r13d
movslq %ecx, %r12
leaq 0(,%r12,4), %rdi
movq %r8, %rbx
addq %rdi, %r8
movl $0, %r14d
.L5:
movq %rbp, %r10
movl $0, %r9d
.L8:
movq %r10, %rcx
movq %rbx, %rax
movl $0, %esi
.L6:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, %esi
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L6
movl %esi, (%r11,%r9,4)
addq $1, %r9
addq $4, %r10
cmpq %r12, %r9
jne .L8
addl $1, %r14d
addq %rdi, %r11
addq %rdi, %rbx
addq %rdi, %r8
cmpl %r14d, %r13d
jne .L5
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2057:
.size _Z9MatrixMulPiS_S_i, .-_Z9MatrixMulPiS_S_i
.globl _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15KernelMatrixMulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i
.globl _Z15KernelMatrixMulPiS_S_i
.type _Z15KernelMatrixMulPiS_S_i, @function
_Z15KernelMatrixMulPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15KernelMatrixMulPiS_S_i, .-_Z15KernelMatrixMulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "C[%d][%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L23:
movl $1, 0(%rbp,%rax)
movl $2, (%rbx,%rax)
addq $4, %rax
cmpq $4000000, %rax
jne .L23
movl $62, 32(%rsp)
movl $62, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L24:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $4000000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebp
leaq .LC0(%rip), %r13
.L25:
movl $0, %ebx
.L26:
movl (%r12,%rbx,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1000, %rbx
jne .L26
addl $1, %ebp
addq $4000, %r12
cmpl $1000, %ebp
jne .L25
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl $1000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i
jmp .L24
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15KernelMatrixMulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15KernelMatrixMulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include <malloc.h>
#include <stdlib.h>
#define N 1000
void MatrixMul(int *A, int *B, int *C, int Width) {
int i, j, k;
for(i=0; i<Width; i++)
for(j=0; j<Width; j++){
int s=0;
for(k=0; k<Width; k++)
s+=A[i*Width+k]*B[k*Width+j];
C[i*Width+j]=s;
}
}
#define TILE_WIDTH 16
__global__ void KernelMatrixMul(int* Md, int* Nd, int* Pd, int Width)
{
int x = threadIdx.x+blockIdx.x*blockDim.x;
int y = threadIdx.y+blockIdx.y*blockDim.y;
int Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue+=Md[y * Width + k]*Nd[k * Width + x];
Pd[y*Width + x] = Pvalue;
}
int main(){
int *A=(int*)malloc(N*N*sizeof(int));
int *B=(int*)malloc(N*N*sizeof(int));
int *C=(int*)malloc(N*N*sizeof(int));
int i;
for(i=0;i<N*N;i++){
A[i] = 1;
B[i] = 2;
}
//MatrixMul(A,B,C,N);
int *dev_A,*dev_B,*dev_C;
dim3 dimGrid(N/TILE_WIDTH,N/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH,TILE_WIDTH);
cudaMalloc((void**)&dev_A,N*N*sizeof(int));
cudaMalloc((void**)&dev_B,N*N*sizeof(int));
cudaMalloc((void**)&dev_C,N*N*sizeof(int));
cudaMemcpy(dev_A,A,N*N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_B,B,N*N*sizeof(int),cudaMemcpyHostToDevice);
KernelMatrixMul<<<dimGrid,dimBlock>>>(dev_A,dev_B,dev_C,N);
cudaThreadSynchronize();
cudaMemcpy(C,dev_C,N*N*sizeof(int),cudaMemcpyDeviceToHost);
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
int m,n;
for(m=0;m<N;m++){
for(n=0;n<N;n++)
printf("C[%d][%d] = %d\n",m,n,C[m*N+n]);
}
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include <malloc.h>
#include <stdlib.h>
#define N 1000
void MatrixMul(int *A, int *B, int *C, int Width) {
int i, j, k;
for(i=0; i<Width; i++)
for(j=0; j<Width; j++){
int s=0;
for(k=0; k<Width; k++)
s+=A[i*Width+k]*B[k*Width+j];
C[i*Width+j]=s;
}
}
#define TILE_WIDTH 16
__global__ void KernelMatrixMul(int* Md, int* Nd, int* Pd, int Width)
{
int x = threadIdx.x+blockIdx.x*blockDim.x;
int y = threadIdx.y+blockIdx.y*blockDim.y;
int Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue+=Md[y * Width + k]*Nd[k * Width + x];
Pd[y*Width + x] = Pvalue;
}
int main(){
int *A=(int*)malloc(N*N*sizeof(int));
int *B=(int*)malloc(N*N*sizeof(int));
int *C=(int*)malloc(N*N*sizeof(int));
int i;
for(i=0;i<N*N;i++){
A[i] = 1;
B[i] = 2;
}
//MatrixMul(A,B,C,N);
int *dev_A,*dev_B,*dev_C;
dim3 dimGrid(N/TILE_WIDTH,N/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH,TILE_WIDTH);
hipMalloc((void**)&dev_A,N*N*sizeof(int));
hipMalloc((void**)&dev_B,N*N*sizeof(int));
hipMalloc((void**)&dev_C,N*N*sizeof(int));
hipMemcpy(dev_A,A,N*N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_B,B,N*N*sizeof(int),hipMemcpyHostToDevice);
KernelMatrixMul<<<dimGrid,dimBlock>>>(dev_A,dev_B,dev_C,N);
hipDeviceSynchronize();
hipMemcpy(C,dev_C,N*N*sizeof(int),hipMemcpyDeviceToHost);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
int m,n;
for(m=0;m<N;m++){
for(n=0;n<N;n++)
printf("C[%d][%d] = %d\n",m,n,C[m*N+n]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include <malloc.h>
#include <stdlib.h>
#define N 1000
void MatrixMul(int *A, int *B, int *C, int Width) {
int i, j, k;
for(i=0; i<Width; i++)
for(j=0; j<Width; j++){
int s=0;
for(k=0; k<Width; k++)
s+=A[i*Width+k]*B[k*Width+j];
C[i*Width+j]=s;
}
}
#define TILE_WIDTH 16
__global__ void KernelMatrixMul(int* Md, int* Nd, int* Pd, int Width)
{
int x = threadIdx.x+blockIdx.x*blockDim.x;
int y = threadIdx.y+blockIdx.y*blockDim.y;
int Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue+=Md[y * Width + k]*Nd[k * Width + x];
Pd[y*Width + x] = Pvalue;
}
int main(){
int *A=(int*)malloc(N*N*sizeof(int));
int *B=(int*)malloc(N*N*sizeof(int));
int *C=(int*)malloc(N*N*sizeof(int));
int i;
for(i=0;i<N*N;i++){
A[i] = 1;
B[i] = 2;
}
//MatrixMul(A,B,C,N);
int *dev_A,*dev_B,*dev_C;
dim3 dimGrid(N/TILE_WIDTH,N/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH,TILE_WIDTH);
hipMalloc((void**)&dev_A,N*N*sizeof(int));
hipMalloc((void**)&dev_B,N*N*sizeof(int));
hipMalloc((void**)&dev_C,N*N*sizeof(int));
hipMemcpy(dev_A,A,N*N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_B,B,N*N*sizeof(int),hipMemcpyHostToDevice);
KernelMatrixMul<<<dimGrid,dimBlock>>>(dev_A,dev_B,dev_C,N);
hipDeviceSynchronize();
hipMemcpy(C,dev_C,N*N*sizeof(int),hipMemcpyDeviceToHost);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
int m,n;
for(m=0;m<N;m++){
for(n=0;n<N;n++)
printf("C[%d][%d] = %d\n",m,n,C[m*N+n]);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15KernelMatrixMulPiS_S_i
.globl _Z15KernelMatrixMulPiS_S_i
.p2align 8
.type _Z15KernelMatrixMulPiS_S_i,@function
_Z15KernelMatrixMulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15KernelMatrixMulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15KernelMatrixMulPiS_S_i, .Lfunc_end0-_Z15KernelMatrixMulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15KernelMatrixMulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15KernelMatrixMulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include <malloc.h>
#include <stdlib.h>
#define N 1000
void MatrixMul(int *A, int *B, int *C, int Width) {
int i, j, k;
for(i=0; i<Width; i++)
for(j=0; j<Width; j++){
int s=0;
for(k=0; k<Width; k++)
s+=A[i*Width+k]*B[k*Width+j];
C[i*Width+j]=s;
}
}
#define TILE_WIDTH 16
__global__ void KernelMatrixMul(int* Md, int* Nd, int* Pd, int Width)
{
int x = threadIdx.x+blockIdx.x*blockDim.x;
int y = threadIdx.y+blockIdx.y*blockDim.y;
int Pvalue = 0;
for (int k = 0; k < Width; ++k)
Pvalue+=Md[y * Width + k]*Nd[k * Width + x];
Pd[y*Width + x] = Pvalue;
}
int main(){
int *A=(int*)malloc(N*N*sizeof(int));
int *B=(int*)malloc(N*N*sizeof(int));
int *C=(int*)malloc(N*N*sizeof(int));
int i;
for(i=0;i<N*N;i++){
A[i] = 1;
B[i] = 2;
}
//MatrixMul(A,B,C,N);
int *dev_A,*dev_B,*dev_C;
dim3 dimGrid(N/TILE_WIDTH,N/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH,TILE_WIDTH);
hipMalloc((void**)&dev_A,N*N*sizeof(int));
hipMalloc((void**)&dev_B,N*N*sizeof(int));
hipMalloc((void**)&dev_C,N*N*sizeof(int));
hipMemcpy(dev_A,A,N*N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_B,B,N*N*sizeof(int),hipMemcpyHostToDevice);
KernelMatrixMul<<<dimGrid,dimBlock>>>(dev_A,dev_B,dev_C,N);
hipDeviceSynchronize();
hipMemcpy(C,dev_C,N*N*sizeof(int),hipMemcpyDeviceToHost);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
int m,n;
for(m=0;m<N;m++){
for(n=0;n<N;n++)
printf("C[%d][%d] = %d\n",m,n,C[m*N+n]);
}
return 0;
} | .text
.file "test.hip"
.globl _Z9MatrixMulPiS_S_i # -- Begin function _Z9MatrixMulPiS_S_i
.p2align 4, 0x90
.type _Z9MatrixMulPiS_S_i,@function
_Z9MatrixMulPiS_S_i: # @_Z9MatrixMulPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB0_7
# %bb.1: # %.preheader26.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %edx, %edx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movl %edx, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
xorl %r12d, %r12d
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r13), %r9d
imull (%r11,%r12,4), %r9d
addl %r9d, %ebp
incq %r12
addq %r8, %r13
cmpq %r12, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
movl %ebp, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB0_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %ecx, %edx
cmpq %rax, %r10
jne .LBB0_2
.LBB0_7: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9MatrixMulPiS_S_i, .Lfunc_end0-_Z9MatrixMulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__KernelMatrixMulPiS_S_i # -- Begin function _Z30__device_stub__KernelMatrixMulPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__KernelMatrixMulPiS_S_i,@function
_Z30__device_stub__KernelMatrixMulPiS_S_i: # @_Z30__device_stub__KernelMatrixMulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15KernelMatrixMulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__KernelMatrixMulPiS_S_i, .Lfunc_end1-_Z30__device_stub__KernelMatrixMulPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r15
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r15,%rax,4)
movl $2, (%r14,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB2_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 24(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $266287972414, %rdi # imm = 0x3E0000003E
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15KernelMatrixMulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %ecx
movl $.L.str, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
incq %r14
addq $4000, %rbx # imm = 0xFA0
cmpq $1000, %r14 # imm = 0x3E8
jne .LBB2_5
# %bb.8:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15KernelMatrixMulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15KernelMatrixMulPiS_S_i,@object # @_Z15KernelMatrixMulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15KernelMatrixMulPiS_S_i
.p2align 3, 0x0
_Z15KernelMatrixMulPiS_S_i:
.quad _Z30__device_stub__KernelMatrixMulPiS_S_i
.size _Z15KernelMatrixMulPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "C[%d][%d] = %d\n"
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15KernelMatrixMulPiS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__KernelMatrixMulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15KernelMatrixMulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15KernelMatrixMulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15KernelMatrixMulPiS_S_i
.globl _Z15KernelMatrixMulPiS_S_i
.p2align 8
.type _Z15KernelMatrixMulPiS_S_i,@function
_Z15KernelMatrixMulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15KernelMatrixMulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15KernelMatrixMulPiS_S_i, .Lfunc_end0-_Z15KernelMatrixMulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15KernelMatrixMulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15KernelMatrixMulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001293f1_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9MatrixMulPiS_S_i
.type _Z9MatrixMulPiS_S_i, @function
_Z9MatrixMulPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r8
movq %rsi, %rbp
movq %rdx, %r11
movl %ecx, %r13d
movslq %ecx, %r12
leaq 0(,%r12,4), %rdi
movq %r8, %rbx
addq %rdi, %r8
movl $0, %r14d
.L5:
movq %rbp, %r10
movl $0, %r9d
.L8:
movq %r10, %rcx
movq %rbx, %rax
movl $0, %esi
.L6:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, %esi
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L6
movl %esi, (%r11,%r9,4)
addq $1, %r9
addq $4, %r10
cmpq %r12, %r9
jne .L8
addl $1, %r14d
addq %rdi, %r11
addq %rdi, %rbx
addq %rdi, %r8
cmpl %r14d, %r13d
jne .L5
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2057:
.size _Z9MatrixMulPiS_S_i, .-_Z9MatrixMulPiS_S_i
.globl _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15KernelMatrixMulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i
.globl _Z15KernelMatrixMulPiS_S_i
.type _Z15KernelMatrixMulPiS_S_i, @function
_Z15KernelMatrixMulPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15KernelMatrixMulPiS_S_i, .-_Z15KernelMatrixMulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "C[%d][%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L23:
movl $1, 0(%rbp,%rax)
movl $2, (%rbx,%rax)
addq $4, %rax
cmpq $4000000, %rax
jne .L23
movl $62, 32(%rsp)
movl $62, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L24:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $4000000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebp
leaq .LC0(%rip), %r13
.L25:
movl $0, %ebx
.L26:
movl (%r12,%rbx,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1000, %rbx
jne .L26
addl $1, %ebp
addq $4000, %r12
cmpl $1000, %ebp
jne .L25
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl $1000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15KernelMatrixMulPiS_S_iPiS_S_i
jmp .L24
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15KernelMatrixMulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15KernelMatrixMulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z9MatrixMulPiS_S_i # -- Begin function _Z9MatrixMulPiS_S_i
.p2align 4, 0x90
.type _Z9MatrixMulPiS_S_i,@function
_Z9MatrixMulPiS_S_i: # @_Z9MatrixMulPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB0_7
# %bb.1: # %.preheader26.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %edx, %edx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movl %edx, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
xorl %r12d, %r12d
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r13), %r9d
imull (%r11,%r12,4), %r9d
addl %r9d, %ebp
incq %r12
addq %r8, %r13
cmpq %r12, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
movl %ebp, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB0_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %ecx, %edx
cmpq %rax, %r10
jne .LBB0_2
.LBB0_7: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9MatrixMulPiS_S_i, .Lfunc_end0-_Z9MatrixMulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__KernelMatrixMulPiS_S_i # -- Begin function _Z30__device_stub__KernelMatrixMulPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__KernelMatrixMulPiS_S_i,@function
_Z30__device_stub__KernelMatrixMulPiS_S_i: # @_Z30__device_stub__KernelMatrixMulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15KernelMatrixMulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__KernelMatrixMulPiS_S_i, .Lfunc_end1-_Z30__device_stub__KernelMatrixMulPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r15
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r15,%rax,4)
movl $2, (%r14,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB2_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 24(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $266287972414, %rdi # imm = 0x3E0000003E
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15KernelMatrixMulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %ecx
movl $.L.str, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
incq %r14
addq $4000, %rbx # imm = 0xFA0
cmpq $1000, %r14 # imm = 0x3E8
jne .LBB2_5
# %bb.8:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15KernelMatrixMulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15KernelMatrixMulPiS_S_i,@object # @_Z15KernelMatrixMulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15KernelMatrixMulPiS_S_i
.p2align 3, 0x0
_Z15KernelMatrixMulPiS_S_i:
.quad _Z30__device_stub__KernelMatrixMulPiS_S_i
.size _Z15KernelMatrixMulPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "C[%d][%d] = %d\n"
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15KernelMatrixMulPiS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__KernelMatrixMulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15KernelMatrixMulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "ppm.h"
#include <math.h>
#include <iostream>
#include <stdio.h>
__global__
void colorToGreyScaleConversion(int* imdata,int* outimdata,int size){
int dex= 3*(threadIdx.x+blockIdx.x*blockDim.x);
if (dex>= size) return;
int r=imdata[dex];
int g=imdata[dex+1];
int b=imdata[dex+2];
int grey= round(255*( 0.21*(r/255.0)+0.71*(g/255.0)+0.07*(b/255.0)));
// printf("Grey value is : ")
outimdata[dex]=grey;
outimdata[dex+1]=grey;
outimdata[dex+2]=grey;
}
int main(){
ppm football("football.ppm");
int size=3*football.height*football.width;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_gfootball_data;
cudaMalloc((void**)&d_football_data,arsize);
cudaMalloc((void**)&d_gfootball_data,arsize );
cudaMemcpy(d_football_data,football.data,arsize,cudaMemcpyHostToDevice);
cudaMemcpy(d_gfootball_data,football.data,arsize,cudaMemcpyHostToDevice);
colorToGreyScaleConversion<<< 1<<20 ,256>>>(d_football_data,d_gfootball_data,size);
ppm gfootball(football);
cudaMemcpy(gfootball.data,d_gfootball_data,arsize,cudaMemcpyDeviceToHost);
gfootball.write("gfootball.ppm");
cudaFree(d_gfootball_data);
cudaFree(d_football_data);
} | code for sm_80
Function : _Z26colorToGreyScaleConversionPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R21, SR_CTAID.X ; /* 0x0000000000157919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R21, R21, c[0x0][0x0], R0 ; /* 0x0000000015157a24 */
/* 0x001fc800078e0200 */
/*0040*/ IMAD R21, R21, 0x3, RZ ; /* 0x0000000315157824 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x170], PT ; /* 0x00005c0015007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R16, R21, R16, c[0x0][0x160] ; /* 0x0000580015107625 */
/* 0x000fca00078e0210 */
/*00a0*/ LDG.E R0, [R16.64] ; /* 0x0000000410007981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ MUFU.RCP64H R3, 255 ; /* 0x406fe00000037908 */
/* 0x000e220000001800 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x240 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff077424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*0100*/ DFMA R4, R2, -R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000806 */
/*0110*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0120*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*0130*/ DFMA R6, R4, -R6, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000806 */
/*0140*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e220000000004 */
/*0150*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x004e2a0000201c00 */
/*0160*/ DMUL R18, R2, R6 ; /* 0x0000000602127228 */
/* 0x001e220000000000 */
/*0170*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fca0003f2e200 */
/*0180*/ DFMA R4, R18, -255, R2 ; /* 0xc06fe0001204782b */
/* 0x001e0c0000000002 */
/*0190*/ DFMA R18, R6, R4, R18 ; /* 0x000000040612722b */
/* 0x001e140000000012 */
/*01a0*/ FFMA R4, RZ, 3.748046875, R19 ; /* 0x406fe000ff047823 */
/* 0x001fca0000000013 */
/*01b0*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f04200 */
/*01c0*/ @P0 BRA P1, 0x230 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01e0*/ MOV R22, 0x210 ; /* 0x0000021000167802 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff057424 */
/* 0x000fe400078e00ff */
/*0200*/ CALL.REL.NOINC 0x690 ; /* 0x0000048000007944 */
/* 0x000fea0003c00000 */
/*0210*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0006 */
/*0220*/ IMAD.MOV.U32 R19, RZ, RZ, R7 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0007 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ LDG.E R0, [R16.64+0x4] ; /* 0x0000040410007981 */
/* 0x000ea2000c1e1900 */
/*0250*/ MUFU.RCP64H R3, 255 ; /* 0x406fe00000037908 */
/* 0x000e220000001800 */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*0270*/ BSSY B0, 0x400 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0280*/ IMAD.MOV.U32 R7, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff077424 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*02a0*/ DFMA R4, R2, -R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000806 */
/*02b0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*02c0*/ DFMA R2, R2, R4, R2 ; /* 0x000000040202722b */
/* 0x001e0c0000000002 */
/*02d0*/ DFMA R6, R2, -R6, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000806 */
/*02e0*/ DFMA R8, R2, R6, R2 ; /* 0x000000060208722b */
/* 0x001e220000000002 */
/*02f0*/ I2F.F64 R4, R0 ; /* 0x0000000000047312 */
/* 0x004e2a0000201c00 */
/*0300*/ DMUL R2, R8, R4 ; /* 0x0000000408027228 */
/* 0x001e220000000000 */
/*0310*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*0320*/ DFMA R6, R2, -255, R4 ; /* 0xc06fe0000206782b */
/* 0x001e0c0000000004 */
/*0330*/ DFMA R2, R8, R6, R2 ; /* 0x000000060802722b */
/* 0x001e140000000002 */
/*0340*/ FFMA R6, RZ, 3.748046875, R3 ; /* 0x406fe000ff067823 */
/* 0x001fca0000000003 */
/*0350*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*0360*/ @P0 BRA P1, 0x3f0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0370*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0380*/ MOV R22, 0x3d0 ; /* 0x000003d000167802 */
/* 0x000fe20000000f00 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*03a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*03b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff057424 */
/* 0x000fe400078e00ff */
/*03c0*/ CALL.REL.NOINC 0x690 ; /* 0x000002c000007944 */
/* 0x002fea0003c00000 */
/*03d0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fe20000000f00 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R16, [R16.64+0x8] ; /* 0x0000080410107981 */
/* 0x000ea2000c1e1900 */
/*0410*/ MUFU.RCP64H R5, 255 ; /* 0x406fe00000057908 */
/* 0x000e220000001800 */
/*0420*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*0430*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x000ee20000000000 */
/*0440*/ IMAD.MOV.U32 R7, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff077424 */
/* 0x000fe200078e00ff */
/*0450*/ BSSY B0, 0x5c0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0460*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fc600078e00ff */
/*0470*/ DFMA R18, R18, c[0x2][0x8], R2 ; /* 0x0080020012127a2b */
/* 0x008fc80000000002 */
/*0480*/ DFMA R8, R4, -R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000806 */
/*0490*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*04a0*/ DFMA R8, R4, R8, R4 ; /* 0x000000080408722b */
/* 0x001e0c0000000004 */
/*04b0*/ DFMA R6, R8, -R6, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c0000000806 */
/*04c0*/ DFMA R10, R8, R6, R8 ; /* 0x00000006080a722b */
/* 0x001e220000000008 */
/*04d0*/ I2F.F64 R4, R16 ; /* 0x0000001000047312 */
/* 0x004e2a0000201c00 */
/*04e0*/ DMUL R6, R10, R4 ; /* 0x000000040a067228 */
/* 0x001e220000000000 */
/*04f0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*0500*/ DFMA R8, R6, -255, R4 ; /* 0xc06fe0000608782b */
/* 0x001e0c0000000004 */
/*0510*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x001e140000000006 */
/*0520*/ FFMA R0, RZ, 3.748046875, R7 ; /* 0x406fe000ff007823 */
/* 0x001fca0000000007 */
/*0530*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0540*/ @P0 BRA P1, 0x5b0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0550*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0560*/ MOV R22, 0x5b0 ; /* 0x000005b000167802 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*0580*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.MOV.U32 R5, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff057424 */
/* 0x000fe400078e00ff */
/*05a0*/ CALL.REL.NOINC 0x690 ; /* 0x000000e000007944 */
/* 0x002fea0003c00000 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ DFMA R18, R6, c[0x2][0x10], R18 ; /* 0x0080040006127a2b */
/* 0x000e220000000012 */
/*05d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*05e0*/ IMAD.WIDE R4, R21, R4, c[0x0][0x168] ; /* 0x00005a0015047625 */
/* 0x000fe200078e0204 */
/*05f0*/ DMUL R18, R18, 255 ; /* 0x406fe00012127828 */
/* 0x001e140000000000 */
/*0600*/ LOP3.LUT R2, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013027812 */
/* 0x001fc800078ec0ff */
/*0610*/ LOP3.LUT R3, R2, 0x3fe00000, RZ, 0xfc, !PT ; /* 0x3fe0000002037812 */
/* 0x000fe200078efcff */
/*0620*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0630*/ DADD.RZ R2, R18, R2 ; /* 0x0000000012027229 */
/* 0x000e14000000c002 */
/*0640*/ F2I.F64.TRUNC R3, R2 ; /* 0x0000000200037311 */
/* 0x001e24000030d100 */
/*0650*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe8000c101904 */
/*0660*/ STG.E [R4.64+0x4], R3 ; /* 0x0000040304007986 */
/* 0x000fe8000c101904 */
/*0670*/ STG.E [R4.64+0x8], R3 ; /* 0x0000080304007986 */
/* 0x000fe2000c101904 */
/*0680*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0690*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*06a0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x1 ; /* 0x00000001ff187424 */
/* 0x000fe200078e00ff */
/*06b0*/ LOP3.LUT R6, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05067812 */
/* 0x000fe200078ec0ff */
/*06c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*06d0*/ FSETP.GEU.AND P2, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f4e200 */
/*06e0*/ BSSY B1, 0xc30 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*06f0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0710*/ LOP3.LUT R23, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003177812 */
/* 0x000fc400078ec0ff */
/*0720*/ LOP3.LUT R14, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050e7812 */
/* 0x000fe400078ec0ff */
/*0730*/ MOV R20, 0x1ca00000 ; /* 0x1ca0000000147802 */
/* 0x000fe20000000f00 */
/*0740*/ @!P0 DMUL R6, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004068828 */
/* 0x000e220000000000 */
/*0750*/ ISETP.GE.U32.AND P1, PT, R23, R14, PT ; /* 0x0000000e1700720c */
/* 0x000fc60003f26070 */
/*0760*/ @!P2 LOP3.LUT R0, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000500a812 */
/* 0x000fe200078ec0ff */
/*0770*/ @!P2 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0ca224 */
/* 0x000fe200078e00ff */
/*0780*/ MUFU.RCP64H R25, R7 ; /* 0x0000000700197308 */
/* 0x001e220000001800 */
/*0790*/ SEL R9, R20.reuse, 0x63400000, !P1 ; /* 0x6340000014097807 */
/* 0x040fe40004800000 */
/*07a0*/ @!P2 ISETP.GE.U32.AND P3, PT, R23, R0, PT ; /* 0x000000001700a20c */
/* 0x000fe20003f66070 */
/*07b0*/ IMAD.MOV.U32 R0, RZ, RZ, R23 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0017 */
/*07c0*/ LOP3.LUT R9, R9, 0x800fffff, R3, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fe400078ef803 */
/*07d0*/ @!P2 SEL R13, R20, 0x63400000, !P3 ; /* 0x63400000140da807 */
/* 0x000fc80005800000 */
/*07e0*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R3, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fc800078ef803 */
/*07f0*/ @!P2 LOP3.LUT R13, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d0da812 */
/* 0x000fe200078efcff */
/*0800*/ DFMA R10, R24, -R6, 1 ; /* 0x3ff00000180a742b */
/* 0x001e0a0000000806 */
/*0810*/ @!P2 DFMA R8, R8, 2, -R12 ; /* 0x400000000808a82b */
/* 0x000fc8000000080c */
/*0820*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0830*/ DFMA R10, R24, R10, R24 ; /* 0x0000000a180a722b */
/* 0x0010620000000018 */
/*0840*/ @!P2 LOP3.LUT R0, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000900a812 */
/* 0x000fe200078ec0ff */
/*0850*/ IMAD.MOV.U32 R25, RZ, RZ, R14 ; /* 0x000000ffff197224 */
/* 0x001fe200078e000e */
/*0860*/ @!P0 LOP3.LUT R25, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007198812 */
/* 0x000fe400078ec0ff */
/*0870*/ IADD3 R14, R0, -0x1, RZ ; /* 0xffffffff000e7810 */
/* 0x000fe20007ffe0ff */
/*0880*/ DFMA R12, R10, -R6, 1 ; /* 0x3ff000000a0c742b */
/* 0x002e220000000806 */
/*0890*/ IADD3 R24, R25, -0x1, RZ ; /* 0xffffffff19187810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ; /* 0x7feffffe0e00780c */
/* 0x000fc60003f04070 */
/*08b0*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e22000000000a */
/*08c0*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fca0000704470 */
/*08d0*/ DMUL R12, R10, R8 ; /* 0x000000080a0c7228 */
/* 0x001e0c0000000000 */
/*08e0*/ DFMA R14, R12, -R6, R8 ; /* 0x800000060c0e722b */
/* 0x001e0c0000000008 */
/*08f0*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x001062000000000c */
/*0900*/ @P0 BRA 0xad0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0910*/ LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005027812 */
/* 0x000fc800078ec0ff */
/*0920*/ ISETP.GE.U32.AND P0, PT, R23.reuse, R2, PT ; /* 0x000000021700720c */
/* 0x040fe20003f06070 */
/*0930*/ IMAD.IADD R0, R23, 0x1, -R2 ; /* 0x0000000117007824 */
/* 0x000fe400078e0a02 */
/*0940*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0950*/ SEL R3, R20, 0x63400000, !P0 ; /* 0x6340000014037807 */
/* 0x000fe40004000000 */
/*0960*/ IMNMX R0, R0, -0x46a00000, !PT ; /* 0xb960000000007817 */
/* 0x000fc80007800200 */
/*0970*/ IMNMX R0, R0, 0x46a00000, PT ; /* 0x46a0000000007817 */
/* 0x000fca0003800200 */
/*0980*/ IMAD.IADD R0, R0, 0x1, -R3 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a03 */
/*0990*/ IADD3 R3, R0, 0x7fe00000, RZ ; /* 0x7fe0000000037810 */
/* 0x000fcc0007ffe0ff */
/*09a0*/ DMUL R10, R14, R2 ; /* 0x000000020e0a7228 */
/* 0x003e140000000000 */
/*09b0*/ FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x001fda0003f0c200 */
/*09c0*/ @P0 BRA 0xc20 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*09d0*/ DFMA R6, R14, -R6, R8 ; /* 0x800000060e06722b */
/* 0x000e220000000008 */
/*09e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd200078e00ff */
/*09f0*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0a00*/ LOP3.LUT R9, R7, 0x80000000, R5, 0x48, !PT ; /* 0x8000000007097812 */
/* 0x000fc800078e4805 */
/*0a10*/ LOP3.LUT R3, R9, R3, RZ, 0xfc, !PT ; /* 0x0000000309037212 */
/* 0x000fce00078efcff */
/*0a20*/ @!P0 BRA 0xc20 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0a30*/ IMAD.MOV R5, RZ, RZ, -R0 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a00 */
/*0a40*/ DMUL.RP R2, R14, R2 ; /* 0x000000020e027228 */
/* 0x000e220000008000 */
/*0a50*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0a60*/ DFMA R4, R10, -R4, R14 ; /* 0x800000040a04722b */
/* 0x000e46000000000e */
/*0a70*/ LOP3.LUT R9, R3, R9, RZ, 0x3c, !PT ; /* 0x0000000903097212 */
/* 0x001fc600078e3cff */
/*0a80*/ IADD3 R4, -R0, -0x43300000, RZ ; /* 0xbcd0000000047810 */
/* 0x002fc80007ffe1ff */
/*0a90*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0aa0*/ FSEL R10, R2, R10, !P0 ; /* 0x0000000a020a7208 */
/* 0x000fe40004000000 */
/*0ab0*/ FSEL R11, R9, R11, !P0 ; /* 0x0000000b090b7208 */
/* 0x000fe20004000000 */
/*0ac0*/ BRA 0xc20 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0ad0*/ DSETP.NAN.AND P0, PT, R2, R2, PT ; /* 0x000000020200722a */
/* 0x000e9c0003f08000 */
/*0ae0*/ @P0 BRA 0xc00 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0af0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0b00*/ @P0 BRA 0xbd0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0b10*/ ISETP.NE.AND P0, PT, R0, R25, PT ; /* 0x000000190000720c */
/* 0x000fe20003f05270 */
/*0b20*/ IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b7424 */
/* 0x001fe200078e00ff */
/*0b30*/ MOV R10, 0x0 ; /* 0x00000000000a7802 */
/* 0x000fd60000000f00 */
/*0b40*/ @!P0 BRA 0xc20 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b50*/ ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fe40003f05270 */
/*0b60*/ LOP3.LUT R11, R3, 0x80000000, R5, 0x48, !PT ; /* 0x80000000030b7812 */
/* 0x000fe400078e4805 */
/*0b70*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*0b80*/ @P0 LOP3.LUT R0, R11, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000b000812 */
/* 0x000fe200078efcff */
/*0b90*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e00ff */
/*0ba0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0bb0*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e0000 */
/*0bc0*/ BRA 0xc20 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ LOP3.LUT R11, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050b7812 */
/* 0x001fe200078efcff */
/*0be0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*0bf0*/ BRA 0xc20 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c00*/ LOP3.LUT R11, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000030b7812 */
/* 0x001fe200078efcff */
/*0c10*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0c20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c30*/ IMAD.MOV.U32 R23, RZ, RZ, 0x0 ; /* 0x00000000ff177424 */
/* 0x000fe400078e00ff */
/*0c40*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fc400078e000a */
/*0c50*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*0c60*/ RET.REL.NODEC R22 0x0 ; /* 0xfffff39016007950 */
/* 0x000fec0003c3ffff */
/*0c70*/ BRA 0xc70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "ppm.h"
#include <math.h>
#include <iostream>
#include <stdio.h>
__global__
void colorToGreyScaleConversion(int* imdata,int* outimdata,int size){
int dex= 3*(threadIdx.x+blockIdx.x*blockDim.x);
if (dex>= size) return;
int r=imdata[dex];
int g=imdata[dex+1];
int b=imdata[dex+2];
int grey= round(255*( 0.21*(r/255.0)+0.71*(g/255.0)+0.07*(b/255.0)));
// printf("Grey value is : ")
outimdata[dex]=grey;
outimdata[dex+1]=grey;
outimdata[dex+2]=grey;
}
int main(){
ppm football("football.ppm");
int size=3*football.height*football.width;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_gfootball_data;
cudaMalloc((void**)&d_football_data,arsize);
cudaMalloc((void**)&d_gfootball_data,arsize );
cudaMemcpy(d_football_data,football.data,arsize,cudaMemcpyHostToDevice);
cudaMemcpy(d_gfootball_data,football.data,arsize,cudaMemcpyHostToDevice);
colorToGreyScaleConversion<<< 1<<20 ,256>>>(d_football_data,d_gfootball_data,size);
ppm gfootball(football);
cudaMemcpy(gfootball.data,d_gfootball_data,arsize,cudaMemcpyDeviceToHost);
gfootball.write("gfootball.ppm");
cudaFree(d_gfootball_data);
cudaFree(d_football_data);
} | .file "tmpxft_000d072e_00000000-6_ctg.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4710:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z26colorToGreyScaleConversionPiS_iPiS_i
.type _Z49__device_stub__Z26colorToGreyScaleConversionPiS_iPiS_i, @function
_Z49__device_stub__Z26colorToGreyScaleConversionPiS_iPiS_i:
.LFB4732:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26colorToGreyScaleConversionPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4732:
.size _Z49__device_stub__Z26colorToGreyScaleConversionPiS_iPiS_i, .-_Z49__device_stub__Z26colorToGreyScaleConversionPiS_iPiS_i
.globl _Z26colorToGreyScaleConversionPiS_i
.type _Z26colorToGreyScaleConversionPiS_i, @function
_Z26colorToGreyScaleConversionPiS_i:
.LFB4733:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z26colorToGreyScaleConversionPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4733:
.size _Z26colorToGreyScaleConversionPiS_i, .-_Z26colorToGreyScaleConversionPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26colorToGreyScaleConversionPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4735:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26colorToGreyScaleConversionPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4735:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB5080:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L22
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L23
cmpq $1, %rax
jne .L18
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L19:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L25
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L25:
call __stack_chk_fail@PLT
.L23:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L17:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L19
.L18:
testq %rax, %rax
je .L19
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5080:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE.str1.1,"aMS",@progbits,1
.LC2:
.string "P3"
.LC3:
.string "Wrong image type!!"
.LC4:
.string "255"
.LC5:
.string "Wrong image color depth!!"
.section .text._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppmC5ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.align 2
.weak _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB4703:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4703
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $568, %rsp
.cfi_def_cfa_offset 624
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %r12
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
movq $0, 504(%rsp)
movb $0, 512(%rsp)
movb $0, 513(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq $0, 536(%rsp)
movq $0, 544(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r15
movq %r15, 32(%rsp)
movq -24(%r15), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
movq $0, 40(%rsp)
movq 32(%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 48(%rsp), %rsi
leaq 288(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
jmp .L73
.L65:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L29:
movq %r15, 32(%rsp)
movq -24(%r15), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
movq $0, 40(%rsp)
.L30:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L31
call __stack_chk_fail@PLT
.L64:
endbr64
movq %rax, %rbx
jmp .L29
.L63:
endbr64
movq %rax, %rbx
jmp .L30
.L31:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L73:
movq 0(%rbp), %rsi
leaq 48(%rsp), %rdi
movl $8, %edx
.LEHB4:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L74
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L33
.L74:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE4:
.L33:
movq %rsp, %rsi
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
leaq 32(%rsp), %rdi
.LEHB5:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE5:
cmpq $2, 8(%rsp)
je .L75
.L34:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rbp
leaq .LC3(%rip), %rsi
movq %rax, %rdi
.LEHB6:
call _ZNSt12out_of_rangeC1EPKc@PLT
.LEHE6:
jmp .L76
.L75:
movl $2, %edx
leaq .LC2(%rip), %rsi
movq (%rsp), %rdi
call memcmp@PLT
testl %eax, %eax
jne .L34
leaq 32(%rsp), %rdi
movq %rbx, %rsi
.LEHB7:
call _ZNSirsERi@PLT
jmp .L77
.L76:
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L36:
movq _ZNSt12out_of_rangeD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt12out_of_range(%rip), %rsi
movq %rbp, %rdi
call __cxa_throw@PLT
.L60:
endbr64
movq %rax, %rbx
jmp .L52
.L77:
leaq 4(%rbx), %rsi
leaq 32(%rsp), %rdi
call _ZNSirsERi@PLT
movq %rsp, %rsi
leaq 32(%rsp), %rdi
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE7:
cmpq $3, 8(%rsp)
je .L78
.L37:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rbp
leaq .LC5(%rip), %rsi
movq %rax, %rdi
.LEHB8:
call _ZNSt12out_of_rangeC1EPKc@PLT
.LEHE8:
jmp .L79
.L78:
movl $3, %edx
leaq .LC4(%rip), %rsi
movq (%rsp), %rdi
call memcmp@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L37
movl 4(%rbx), %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L40
leaq 0(,%rax,4), %rdi
.LEHB9:
call _Znam@PLT
jmp .L80
.L79:
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L39:
movq _ZNSt12out_of_rangeD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt12out_of_range(%rip), %rsi
movq %rbp, %rdi
call __cxa_throw@PLT
.L80:
movq %rax, 8(%rbx)
movl %r14d, %r12d
leaq 32(%rsp), %r13
cmpl $0, 4(%rbx)
jg .L43
.L44:
leaq 48(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
jmp .L81
.L40:
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
call __cxa_throw_bad_array_new_length@PLT
.L82:
movl %r12d, %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
leaq 4(%rdx,%rax,4), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
movl %r12d, %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
leaq 8(%rdx,%rax,4), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
addl $3, %ebp
movl (%rbx), %eax
leal (%rax,%rax,2), %edx
cmpl %ebp, %edx
jle .L46
.L45:
imull %r12d, %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
leaq (%rdx,%rax,4), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
.LEHE9:
jmp .L82
.L46:
addl $1, %r12d
cmpl %r12d, 4(%rbx)
jle .L44
.L43:
movl (%rbx), %eax
movl %r14d, %ebp
testl %eax, %eax
jg .L45
jmp .L46
.L81:
testq %rax, %rax
je .L83
.L47:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L48
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L48:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rdi
.LEHB10:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE10:
jmp .L50
.L83:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB11:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE11:
jmp .L47
.L66:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L50:
leaq 152(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r15, 32(%rsp)
movq -24(%r15), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
movq $0, 40(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L84
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rbp, %rdi
call __cxa_free_exception@PLT
.L52:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L54:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L55
call __stack_chk_fail@PLT
.L62:
endbr64
movq %rax, %rbx
movq %rbp, %rdi
call __cxa_free_exception@PLT
jmp .L52
.L59:
endbr64
movq %rax, %rbx
jmp .L54
.L55:
movq %rbx, %rdi
.LEHB12:
call _Unwind_Resume@PLT
.LEHE12:
.L84:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4703:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN3ppmC5ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.align 4
.LLSDA4703:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4703-.LLSDATTD4703
.LLSDATTD4703:
.byte 0x1
.uleb128 .LLSDACSE4703-.LLSDACSB4703
.LLSDACSB4703:
.uleb128 .LEHB0-.LFB4703
.uleb128 .LEHE0-.LEHB0
.uleb128 .L63-.LFB4703
.uleb128 0
.uleb128 .LEHB1-.LFB4703
.uleb128 .LEHE1-.LEHB1
.uleb128 .L64-.LFB4703
.uleb128 0
.uleb128 .LEHB2-.LFB4703
.uleb128 .LEHE2-.LEHB2
.uleb128 .L65-.LFB4703
.uleb128 0
.uleb128 .LEHB3-.LFB4703
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4703
.uleb128 .LEHE4-.LEHB4
.uleb128 .L59-.LFB4703
.uleb128 0
.uleb128 .LEHB5-.LFB4703
.uleb128 .LEHE5-.LEHB5
.uleb128 .L60-.LFB4703
.uleb128 0
.uleb128 .LEHB6-.LFB4703
.uleb128 .LEHE6-.LEHB6
.uleb128 .L61-.LFB4703
.uleb128 0
.uleb128 .LEHB7-.LFB4703
.uleb128 .LEHE7-.LEHB7
.uleb128 .L60-.LFB4703
.uleb128 0
.uleb128 .LEHB8-.LFB4703
.uleb128 .LEHE8-.LEHB8
.uleb128 .L62-.LFB4703
.uleb128 0
.uleb128 .LEHB9-.LFB4703
.uleb128 .LEHE9-.LEHB9
.uleb128 .L60-.LFB4703
.uleb128 0
.uleb128 .LEHB10-.LFB4703
.uleb128 .LEHE10-.LEHB10
.uleb128 .L66-.LFB4703
.uleb128 0x1
.uleb128 .LEHB11-.LFB4703
.uleb128 .LEHE11-.LEHB11
.uleb128 .L60-.LFB4703
.uleb128 0
.uleb128 .LEHB12-.LFB4703
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.LLSDACSE4703:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4703:
.section .text._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppmC5ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.size _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.weak _ZN3ppmC1ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.set _ZN3ppmC1ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .rodata._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE.str1.1,"aMS",@progbits,1
.LC6:
.string "P3\n"
.LC7:
.string " "
.LC8:
.string "\n"
.LC9:
.string "255\n"
.section .text._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.align 2
.weak _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB4705:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4705
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $536, %rsp
.cfi_def_cfa_offset 592
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 520(%rsp)
xorl %eax, %eax
movq %rsp, %r12
leaq 248(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 248(%rsp)
movq $0, 464(%rsp)
movb $0, 472(%rsp)
movb $0, 473(%rsp)
movq $0, 480(%rsp)
movq $0, 488(%rsp)
movq $0, 496(%rsp)
movq $0, 504(%rsp)
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r14
movq %r14, (%rsp)
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r15
movq -24(%r14), %rax
movq %r15, (%rsp,%rax)
movq (%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB13:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE13:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 248(%rsp)
leaq 8(%rsp), %rdi
.LEHB14:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE14:
leaq 8(%rsp), %rsi
leaq 248(%rsp), %rdi
.LEHB15:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
movq 0(%rbp), %rsi
leaq 8(%rsp), %rdi
movl $16, %edx
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L116
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L87
.L116:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE15:
.L87:
movq %rsp, %rdi
movl $3, %edx
leaq .LC6(%rip), %rsi
.LEHB16:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.LEHE16:
jmp .L117
.L108:
endbr64
movq %rax, %rbx
leaq 8(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L90:
movq %r14, (%rsp)
movq -24(%r14), %rax
movq %r15, (%rsp,%rax)
.L91:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 248(%rsp)
leaq 248(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
je .L92
call __stack_chk_fail@PLT
.L107:
endbr64
movq %rax, %rbx
jmp .L90
.L106:
endbr64
movq %rax, %rbx
jmp .L91
.L92:
movq %rbx, %rdi
.LEHB17:
call _Unwind_Resume@PLT
.LEHE17:
.L117:
movl (%rbx), %esi
movq %rsp, %rdi
.LEHB18:
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC8(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rsp, %rdi
movl $4, %edx
leaq .LC9(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $0, %r12d
leaq .LC8(%rip), %r13
cmpl $0, 4(%rbx)
jg .L93
.L94:
leaq 8(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
jmp .L118
.L119:
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
movl 4(%rdx,%rax,4), %esi
movq %rsp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
movl 8(%rdx,%rax,4), %esi
movq %rsp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $3, %ebp
movl (%rbx), %eax
leal (%rax,%rax,2), %edx
cmpl %ebp, %edx
jle .L96
.L95:
imull %r12d, %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
movl (%rdx,%rax,4), %esi
movq %rsp, %rdi
call _ZNSolsEi@PLT
.LEHE18:
jmp .L119
.L96:
addl $1, %r12d
cmpl %r12d, 4(%rbx)
jle .L94
.L93:
movl (%rbx), %eax
movl $0, %ebp
testl %eax, %eax
jg .L95
jmp .L96
.L118:
testq %rax, %rax
je .L120
.L97:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 248(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
.LEHB19:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE19:
jmp .L99
.L120:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB20:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE20:
jmp .L97
.L109:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L99:
leaq 112(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r14, (%rsp)
movq -24(%r14), %rax
movq %r15, (%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 248(%rsp)
leaq 248(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
jne .L121
addq $536, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L105:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
je .L101
call __stack_chk_fail@PLT
.L101:
movq %rbx, %rdi
.LEHB21:
call _Unwind_Resume@PLT
.LEHE21:
.L121:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4705:
.section .gcc_except_table._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.align 4
.LLSDA4705:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4705-.LLSDATTD4705
.LLSDATTD4705:
.byte 0x1
.uleb128 .LLSDACSE4705-.LLSDACSB4705
.LLSDACSB4705:
.uleb128 .LEHB13-.LFB4705
.uleb128 .LEHE13-.LEHB13
.uleb128 .L106-.LFB4705
.uleb128 0
.uleb128 .LEHB14-.LFB4705
.uleb128 .LEHE14-.LEHB14
.uleb128 .L107-.LFB4705
.uleb128 0
.uleb128 .LEHB15-.LFB4705
.uleb128 .LEHE15-.LEHB15
.uleb128 .L108-.LFB4705
.uleb128 0
.uleb128 .LEHB16-.LFB4705
.uleb128 .LEHE16-.LEHB16
.uleb128 .L105-.LFB4705
.uleb128 0
.uleb128 .LEHB17-.LFB4705
.uleb128 .LEHE17-.LEHB17
.uleb128 0
.uleb128 0
.uleb128 .LEHB18-.LFB4705
.uleb128 .LEHE18-.LEHB18
.uleb128 .L105-.LFB4705
.uleb128 0
.uleb128 .LEHB19-.LFB4705
.uleb128 .LEHE19-.LEHB19
.uleb128 .L109-.LFB4705
.uleb128 0x1
.uleb128 .LEHB20-.LFB4705
.uleb128 .LEHE20-.LEHB20
.uleb128 .L105-.LFB4705
.uleb128 0
.uleb128 .LEHB21-.LFB4705
.uleb128 .LEHE21-.LEHB21
.uleb128 0
.uleb128 0
.LLSDACSE4705:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4705:
.section .text._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.size _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "football.ppm"
.LC11:
.string "Size is: "
.LC12:
.string "gfootball.ppm"
.text
.globl main
.type main, @function
main:
.LFB4707:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4707
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdx
leaq 96(%rsp), %rbx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
.LEHB22:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE22:
leaq 32(%rsp), %rdi
movq %rbx, %rsi
.LEHB23:
call _ZN3ppmC1ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE23:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl 36(%rsp), %eax
imull 32(%rsp), %eax
leal (%rax,%rax,2), %ebp
leal 0(,%rbp,4), %ebx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB24:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movslq %ebx, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1048576, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L123
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z49__device_stub__Z26colorToGreyScaleConversionPiS_iPiS_i
.L123:
movl 32(%rsp), %eax
movl %eax, 64(%rsp)
movl 36(%rsp), %edx
movl %edx, 68(%rsp)
imull %edx, %eax
leal (%rax,%rax,2), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L124
salq $2, %rdi
call _Znam@PLT
.LEHE24:
movq %rax, %rbp
movq %rax, 72(%rsp)
movq 40(%rsp), %rsi
movl 32(%rsp), %eax
imull 36(%rsp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
cmpq $4, %rdx
jle .L125
movq %rbp, %rdi
call memmove@PLT
.L126:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
.LEHB25:
call cudaMemcpy@PLT
.LEHE25:
jmp .L145
.L125:
jne .L126
movl (%rsi), %eax
movl %eax, 0(%rbp)
jmp .L126
.L124:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L128
call __stack_chk_fail@PLT
.L128:
.LEHB26:
call __cxa_throw_bad_array_new_length@PLT
.LEHE26:
.L139:
endbr64
movq %rax, %rbx
jmp .L134
.L145:
leaq 20(%rsp), %rdx
leaq 96(%rsp), %rdi
leaq .LC12(%rip), %rsi
.LEHB27:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE27:
leaq 96(%rsp), %rsi
leaq 64(%rsp), %rdi
.LEHB28:
call _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE28:
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 8(%rsp), %rdi
.LEHB29:
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
.LEHE29:
movq %rbp, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .L129
call _ZdaPv@PLT
.L129:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L146
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L138:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L131
call __stack_chk_fail@PLT
.L131:
movq %rbx, %rdi
.LEHB30:
call _Unwind_Resume@PLT
.L141:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L133:
movq %rbp, %rdi
call _ZdaPv@PLT
.L134:
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .L135
call _ZdaPv@PLT
.L135:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L136
call __stack_chk_fail@PLT
.L140:
endbr64
movq %rax, %rbx
jmp .L133
.L136:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE30:
.L146:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4707:
.section .gcc_except_table,"a",@progbits
.LLSDA4707:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4707-.LLSDACSB4707
.LLSDACSB4707:
.uleb128 .LEHB22-.LFB4707
.uleb128 .LEHE22-.LEHB22
.uleb128 0
.uleb128 0
.uleb128 .LEHB23-.LFB4707
.uleb128 .LEHE23-.LEHB23
.uleb128 .L138-.LFB4707
.uleb128 0
.uleb128 .LEHB24-.LFB4707
.uleb128 .LEHE24-.LEHB24
.uleb128 .L139-.LFB4707
.uleb128 0
.uleb128 .LEHB25-.LFB4707
.uleb128 .LEHE25-.LEHB25
.uleb128 .L140-.LFB4707
.uleb128 0
.uleb128 .LEHB26-.LFB4707
.uleb128 .LEHE26-.LEHB26
.uleb128 .L139-.LFB4707
.uleb128 0
.uleb128 .LEHB27-.LFB4707
.uleb128 .LEHE27-.LEHB27
.uleb128 .L140-.LFB4707
.uleb128 0
.uleb128 .LEHB28-.LFB4707
.uleb128 .LEHE28-.LEHB28
.uleb128 .L141-.LFB4707
.uleb128 0
.uleb128 .LEHB29-.LFB4707
.uleb128 .LEHE29-.LEHB29
.uleb128 .L140-.LFB4707
.uleb128 0
.uleb128 .LEHB30-.LFB4707
.uleb128 .LEHE30-.LEHB30
.uleb128 0
.uleb128 0
.LLSDACSE4707:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "ppm.h"
#include <math.h>
#include <iostream>
#include <stdio.h>
__global__
void colorToGreyScaleConversion(int* imdata,int* outimdata,int size){
int dex= 3*(threadIdx.x+blockIdx.x*blockDim.x);
if (dex>= size) return;
int r=imdata[dex];
int g=imdata[dex+1];
int b=imdata[dex+2];
int grey= round(255*( 0.21*(r/255.0)+0.71*(g/255.0)+0.07*(b/255.0)));
// printf("Grey value is : ")
outimdata[dex]=grey;
outimdata[dex+1]=grey;
outimdata[dex+2]=grey;
}
int main(){
ppm football("football.ppm");
int size=3*football.height*football.width;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_gfootball_data;
cudaMalloc((void**)&d_football_data,arsize);
cudaMalloc((void**)&d_gfootball_data,arsize );
cudaMemcpy(d_football_data,football.data,arsize,cudaMemcpyHostToDevice);
cudaMemcpy(d_gfootball_data,football.data,arsize,cudaMemcpyHostToDevice);
colorToGreyScaleConversion<<< 1<<20 ,256>>>(d_football_data,d_gfootball_data,size);
ppm gfootball(football);
cudaMemcpy(gfootball.data,d_gfootball_data,arsize,cudaMemcpyDeviceToHost);
gfootball.write("gfootball.ppm");
cudaFree(d_gfootball_data);
cudaFree(d_football_data);
} | #include <hip/hip_runtime.h>
#include "ppm.h"
#include <math.h>
#include <iostream>
#include <stdio.h>
__global__
void colorToGreyScaleConversion(int* imdata,int* outimdata,int size){
int dex= 3*(threadIdx.x+blockIdx.x*blockDim.x);
if (dex>= size) return;
int r=imdata[dex];
int g=imdata[dex+1];
int b=imdata[dex+2];
int grey= round(255*( 0.21*(r/255.0)+0.71*(g/255.0)+0.07*(b/255.0)));
// printf("Grey value is : ")
outimdata[dex]=grey;
outimdata[dex+1]=grey;
outimdata[dex+2]=grey;
}
int main(){
ppm football("football.ppm");
int size=3*football.height*football.width;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_gfootball_data;
hipMalloc((void**)&d_football_data,arsize);
hipMalloc((void**)&d_gfootball_data,arsize );
hipMemcpy(d_football_data,football.data,arsize,hipMemcpyHostToDevice);
hipMemcpy(d_gfootball_data,football.data,arsize,hipMemcpyHostToDevice);
colorToGreyScaleConversion<<< 1<<20 ,256>>>(d_football_data,d_gfootball_data,size);
ppm gfootball(football);
hipMemcpy(gfootball.data,d_gfootball_data,arsize,hipMemcpyDeviceToHost);
gfootball.write("gfootball.ppm");
hipFree(d_gfootball_data);
hipFree(d_football_data);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "ppm.h"
#include <math.h>
#include <iostream>
#include <stdio.h>
__global__
void colorToGreyScaleConversion(int* imdata,int* outimdata,int size){
int dex= 3*(threadIdx.x+blockIdx.x*blockDim.x);
if (dex>= size) return;
int r=imdata[dex];
int g=imdata[dex+1];
int b=imdata[dex+2];
int grey= round(255*( 0.21*(r/255.0)+0.71*(g/255.0)+0.07*(b/255.0)));
// printf("Grey value is : ")
outimdata[dex]=grey;
outimdata[dex+1]=grey;
outimdata[dex+2]=grey;
}
int main(){
ppm football("football.ppm");
int size=3*football.height*football.width;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_gfootball_data;
hipMalloc((void**)&d_football_data,arsize);
hipMalloc((void**)&d_gfootball_data,arsize );
hipMemcpy(d_football_data,football.data,arsize,hipMemcpyHostToDevice);
hipMemcpy(d_gfootball_data,football.data,arsize,hipMemcpyHostToDevice);
colorToGreyScaleConversion<<< 1<<20 ,256>>>(d_football_data,d_gfootball_data,size);
ppm gfootball(football);
hipMemcpy(gfootball.data,d_gfootball_data,arsize,hipMemcpyDeviceToHost);
gfootball.write("gfootball.ppm");
hipFree(d_gfootball_data);
hipFree(d_football_data);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26colorToGreyScaleConversionPiS_i
.globl _Z26colorToGreyScaleConversionPiS_i
.p2align 8
.type _Z26colorToGreyScaleConversionPiS_i,@function
_Z26colorToGreyScaleConversionPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v0, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s5, 0x3fe6b851
s_mov_b32 s4, 0xeb851eb8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v32, vcc_lo, v0, 4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v33, vcc_lo, 0, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v32
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v33, vcc_lo
v_add_co_u32 v34, vcc_lo, v0, 8
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v35, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v34
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v35, vcc_lo
global_load_b32 v10, v[2:3], off
s_waitcnt vmcnt(2)
v_cvt_f64_i32_e32 v[2:3], v6
s_waitcnt vmcnt(1)
v_cvt_f64_i32_e32 v[4:5], v4
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f64 v[6:7], null, 0x406fe000, 0x406fe000, v[2:3]
v_div_scale_f64 v[8:9], null, 0x406fe000, 0x406fe000, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_scale_f64 v[16:17], null, 0x406fe000, 0x406fe000, v[10:11]
v_div_scale_f64 v[30:31], s1, v[10:11], 0x406fe000, v[10:11]
v_rcp_f64_e32 v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[8:9]
v_rcp_f64_e32 v[22:23], v[16:17]
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], -v[6:7], v[12:13], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[8:9], v[14:15], 1.0
v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
v_fma_f64 v[18:19], -v[16:17], v[22:23], 1.0
v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[20:21], -v[6:7], v[12:13], 1.0
v_fma_f64 v[18:19], v[22:23], v[18:19], v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[24:25], -v[8:9], v[14:15], 1.0
v_div_scale_f64 v[22:23], vcc_lo, v[2:3], 0x406fe000, v[2:3]
v_fma_f64 v[12:13], v[12:13], v[20:21], v[12:13]
v_div_scale_f64 v[20:21], s0, v[4:5], 0x406fe000, v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[14:15], v[14:15], v[24:25], v[14:15]
v_fma_f64 v[24:25], -v[16:17], v[18:19], 1.0
v_mul_f64 v[26:27], v[22:23], v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[28:29], v[20:21], v[14:15]
v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], -v[6:7], v[26:27], v[22:23]
v_fma_f64 v[8:9], -v[8:9], v[28:29], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[20:21], v[30:31], v[18:19]
v_div_fmas_f64 v[6:7], v[6:7], v[12:13], v[26:27]
s_mov_b32 vcc_lo, s0
s_mov_b32 s0, 0xae147ae1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[28:29]
v_fma_f64 v[12:13], -v[16:17], v[20:21], v[30:31]
s_mov_b32 vcc_lo, s1
s_mov_b32 s1, 0x3fcae147
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[2:3], v[6:7], 0x406fe000, v[2:3]
v_div_fixup_f64 v[4:5], v[8:9], 0x406fe000, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[8:9], v[12:13], v[18:19], v[20:21]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mul_f64 v[4:5], v[4:5], s[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[6:7], v[8:9], 0x406fe000, v[10:11]
v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5]
s_mov_b32 s1, 0x3fb1eb85
s_mov_b32 s0, 0x1eb851ec
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[6:7], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], 0x406fe000
v_trunc_f64_e32 v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[2:3], -v[4:5]
v_mov_b32_e32 v2, 0
v_cmp_ge_f64_e64 s0, |v[6:7]|, 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, 0, 0x3ff00000, s0
v_bfi_b32 v3, 0x7fffffff, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[4:5], v[2:3]
v_cvt_i32_f64_e32 v6, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v32
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v33, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v34
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v35, vcc_lo
s_clause 0x2
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v6, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26colorToGreyScaleConversionPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 36
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26colorToGreyScaleConversionPiS_i, .Lfunc_end0-_Z26colorToGreyScaleConversionPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26colorToGreyScaleConversionPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26colorToGreyScaleConversionPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 36
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "ppm.h"
#include <math.h>
#include <iostream>
#include <stdio.h>
__global__
void colorToGreyScaleConversion(int* imdata,int* outimdata,int size){
int dex= 3*(threadIdx.x+blockIdx.x*blockDim.x);
if (dex>= size) return;
int r=imdata[dex];
int g=imdata[dex+1];
int b=imdata[dex+2];
int grey= round(255*( 0.21*(r/255.0)+0.71*(g/255.0)+0.07*(b/255.0)));
// printf("Grey value is : ")
outimdata[dex]=grey;
outimdata[dex+1]=grey;
outimdata[dex+2]=grey;
}
int main(){
ppm football("football.ppm");
int size=3*football.height*football.width;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_gfootball_data;
hipMalloc((void**)&d_football_data,arsize);
hipMalloc((void**)&d_gfootball_data,arsize );
hipMemcpy(d_football_data,football.data,arsize,hipMemcpyHostToDevice);
hipMemcpy(d_gfootball_data,football.data,arsize,hipMemcpyHostToDevice);
colorToGreyScaleConversion<<< 1<<20 ,256>>>(d_football_data,d_gfootball_data,size);
ppm gfootball(football);
hipMemcpy(gfootball.data,d_gfootball_data,arsize,hipMemcpyDeviceToHost);
gfootball.write("gfootball.ppm");
hipFree(d_gfootball_data);
hipFree(d_football_data);
} | .text
.file "ctg.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z41__device_stub__colorToGreyScaleConversionPiS_i # -- Begin function _Z41__device_stub__colorToGreyScaleConversionPiS_i
.p2align 4, 0x90
.type _Z41__device_stub__colorToGreyScaleConversionPiS_i,@function
_Z41__device_stub__colorToGreyScaleConversionPiS_i: # @_Z41__device_stub__colorToGreyScaleConversionPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26colorToGreyScaleConversionPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z41__device_stub__colorToGreyScaleConversionPiS_i, .Lfunc_end0-_Z41__device_stub__colorToGreyScaleConversionPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $216, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 136(%rsp), %r14
movq %r14, 120(%rsp)
movabsq $7812726529069117286, %rax # imm = 0x6C6C6162746F6F66
movq %rax, 136(%rsp)
movl $1836085294, 144(%rsp) # imm = 0x6D70702E
movq $12, 128(%rsp)
movb $0, 148(%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
leaq 120(%rsp), %rsi
callq _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_3
# %bb.2: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movl 68(%rsp), %ebx
imull 64(%rsp), %ebx
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp4:
# %bb.4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp5:
leal (%rbx,%rbx,2), %r14d
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
.Ltmp6:
# %bb.5:
leal (,%r14,4), %eax
movslq %eax, %rbx
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp9:
# %bb.6:
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp11:
# %bb.7:
movq 16(%rsp), %rdi
movq 72(%rsp), %rsi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.8:
movq 8(%rsp), %rdi
movq 72(%rsp), %rsi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp15:
# %bb.9:
.Ltmp16:
.cfi_escape 0x2e, 0x00
movabsq $4296015872, %rdi # imm = 0x100100000
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp17:
# %bb.10:
testl %eax, %eax
jne .LBB1_13
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 208(%rsp)
movq %rcx, 200(%rsp)
movl %r14d, 28(%rsp)
leaq 208(%rsp), %rax
movq %rax, 32(%rsp)
leaq 200(%rsp), %rax
movq %rax, 40(%rsp)
leaq 28(%rsp), %rax
movq %rax, 48(%rsp)
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp19:
# %bb.12: # %.noexc31
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
.Ltmp20:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z26colorToGreyScaleConversionPiS_i, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp21:
.LBB1_13:
movl 64(%rsp), %eax
movl 68(%rsp), %r15d
movl %eax, 32(%rsp)
movl %r15d, 36(%rsp)
imull %eax, %r15d
leal (%r15,%r15,2), %ebp
movslq %ebp, %rax
shlq $2, %rax
testl %r15d, %r15d
movq $-1, %rdi
cmovnsq %rax, %rdi
.Ltmp23:
.cfi_escape 0x2e, 0x00
callq _Znam
.Ltmp24:
# %bb.14: # %.noexc36
movq %rax, %r14
movq %rax, 40(%rsp)
testl %r15d, %r15d
jle .LBB1_16
# %bb.15:
movq 72(%rsp), %rsi
movl %ebp, %edx
shlq $2, %rdx
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq memmove@PLT
.LBB1_16: # %_ZN3ppmC2ERS_.exit
movq 8(%rsp), %rsi
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp27:
# %bb.17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit43
leaq 104(%rsp), %r14
movq %r14, 88(%rsp)
movabsq $7809631481062450791, %rax # imm = 0x6C6162746F6F6667
movq %rax, 104(%rsp)
movabsq $7885926292215587170, %rax # imm = 0x6D70702E6C6C6162
movq %rax, 109(%rsp)
movq $13, 96(%rsp)
movb $0, 117(%rsp)
.Ltmp28:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
leaq 88(%rsp), %rsi
callq _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp29:
# %bb.18:
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_20
# %bb.19: # %.critedge.i.i44
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit46
movq 8(%rsp), %rdi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp32:
# %bb.21:
movq 16(%rsp), %rdi
.Ltmp33:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp34:
# %bb.22:
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_24
# %bb.23:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
.LBB1_24: # %_ZN3ppmD2Ev.exit
movq 72(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_26
# %bb.25:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
.LBB1_26: # %_ZN3ppmD2Ev.exit47
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 256
.Ltmp30:
movq %rax, %rbx
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_34
# %bb.28: # %.critedge.i.i48
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB1_34
.LBB1_29:
.Ltmp25:
jmp .LBB1_37
.LBB1_30:
.Ltmp2:
movq %rax, %rbx
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_40
# %bb.31: # %.critedge.i.i33
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_32:
.Ltmp7:
jmp .LBB1_37
.LBB1_33:
.Ltmp35:
movq %rax, %rbx
.LBB1_34: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit50
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_38
# %bb.35:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
jmp .LBB1_38
.LBB1_36:
.Ltmp22:
.LBB1_37:
movq %rax, %rbx
.LBB1_38:
movq 72(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_40
# %bb.39:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
.LBB1_40: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit35
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp21-.Ltmp8 # Call between .Ltmp8 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp26-.Ltmp24 # Call between .Ltmp24 and .Ltmp26
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp34-.Ltmp31 # Call between .Ltmp31 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp34 # Call between .Ltmp34 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.weak _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $552, %rsp # imm = 0x228
.cfi_def_cfa_offset 608
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq %rdi, %rbx
leaq 32(%rsp), %r15
movq %r15, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
leaq 48(%rsp), %rdi
movq (%r12), %rsi
.Ltmp36:
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp37:
# %bb.1: # %.noexc
movq 32(%rsp), %rcx
addq -24(%rcx), %r15
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_3
# %bb.2:
movl 32(%r15), %esi
orl $4, %esi
.LBB2_3: # %.invoke
.Ltmp38:
movq %r15, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp39:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode.exit
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
.Ltmp41:
leaq 32(%rsp), %rdi
movq %rsp, %rsi
callq _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE
.Ltmp42:
# %bb.5:
movq 8(%rsp), %rdx
cmpq $2, %rdx
jne .LBB2_7
# %bb.6: # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit
movq (%rsp), %rdi
movl $.L.str.5, %esi
callq bcmp@PLT
testl %eax, %eax
jne .LBB2_7
# %bb.11: # %.critedge29
.Ltmp46:
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq _ZNSirsERi
.Ltmp47:
# %bb.12:
leaq 4(%rbx), %r15
.Ltmp48:
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq _ZNSirsERi
.Ltmp49:
# %bb.13:
.Ltmp50:
leaq 32(%rsp), %rdi
movq %rsp, %rsi
callq _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE
.Ltmp51:
# %bb.14:
movq 8(%rsp), %rdx
cmpq $3, %rdx
jne .LBB2_16
# %bb.15: # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit22
movq (%rsp), %rdi
movl $.L.str.7, %esi
callq bcmp@PLT
testl %eax, %eax
jne .LBB2_16
# %bb.20: # %.critedge31
movslq 4(%rbx), %rax
movslq (%rbx), %rcx
imulq %rax, %rcx
movq %rcx, %rax
shlq $2, %rax
testl %ecx, %ecx
leaq (%rax,%rax,2), %rax
movq $-1, %rdi
cmovnsq %rax, %rdi
.Ltmp57:
callq _Znam
.Ltmp58:
# %bb.21:
movq %rax, 8(%rbx)
cmpl $0, 4(%rbx)
jle .LBB2_30
# %bb.22: # %.preheader.preheader
xorl %ebp, %ebp
leaq 32(%rsp), %r12
xorl %r13d, %r13d
jmp .LBB2_23
.p2align 4, 0x90
.LBB2_29: # %._crit_edge
# in Loop: Header=BB2_23 Depth=1
incl %r13d
addl $3, %ebp
cmpl (%r15), %r13d
jge .LBB2_30
.LBB2_23: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_25 Depth 2
movl (%rbx), %eax
testl %eax, %eax
jle .LBB2_29
# %bb.24: # %.lr.ph
# in Loop: Header=BB2_23 Depth=1
leal (%rax,%rax,2), %eax
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_25: # Parent Loop BB2_23 Depth=1
# => This Inner Loop Header: Depth=2
imull %r13d, %eax
movslq %eax, %rsi
addq %r14, %rsi
shlq $2, %rsi
addq 8(%rbx), %rsi
.Ltmp59:
movq %r12, %rdi
callq _ZNSirsERi
.Ltmp60:
# %bb.26: # in Loop: Header=BB2_25 Depth=2
movq 8(%rbx), %rax
movl (%rbx), %ecx
imull %ebp, %ecx
movslq %ecx, %rcx
addq %r14, %rcx
leaq (%rax,%rcx,4), %rsi
addq $4, %rsi
.Ltmp61:
movq %r12, %rdi
callq _ZNSirsERi
.Ltmp62:
# %bb.27: # in Loop: Header=BB2_25 Depth=2
movq 8(%rbx), %rax
movl (%rbx), %ecx
imull %ebp, %ecx
movslq %ecx, %rcx
addq %r14, %rcx
leaq (%rax,%rcx,4), %rsi
addq $8, %rsi
.Ltmp63:
movq %r12, %rdi
callq _ZNSirsERi
.Ltmp64:
# %bb.28: # in Loop: Header=BB2_25 Depth=2
movl (%rbx), %eax
leal (%rax,%rax,2), %eax
addq $3, %r14
cmpl %eax, %r14d
jl .LBB2_25
jmp .LBB2_29
.LBB2_30: # %._crit_edge34
.Ltmp66:
leaq 48(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp67:
# %bb.31: # %.noexc24
testq %rax, %rax
jne .LBB2_33
# %bb.32:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $32, %rdi
movl 64(%rsp,%rax), %esi
orl $4, %esi
.Ltmp68:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp69:
.LBB2_33: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_35
# %bb.34: # %.critedge.i.i
callq _ZdlPv
.LBB2_35: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
leaq 32(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
addq $552, %rsp # imm = 0x228
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7: # %.critedge
.cfi_def_cfa_offset 608
movl $16, %edi
callq __cxa_allocate_exception
movq %rax, %r14
.Ltmp43:
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZNSt12out_of_rangeC1EPKc
.Ltmp44:
jmp .LBB2_17
.LBB2_16: # %.critedge30
movl $16, %edi
callq __cxa_allocate_exception
movq %rax, %r14
.Ltmp52:
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZNSt12out_of_rangeC1EPKc
.Ltmp53:
.LBB2_17: # %.invoke35
.Ltmp55:
movl $_ZTISt12out_of_range, %esi
movl $_ZNSt12out_of_rangeD1Ev, %edx
movq %r14, %rdi
callq __cxa_throw
.Ltmp56:
# %bb.18: # %.cont
.LBB2_19:
.Ltmp54:
jmp .LBB2_10
.LBB2_9:
.Ltmp45:
.LBB2_10:
movq %rax, %rbx
movq %r14, %rdi
callq __cxa_free_exception
jmp .LBB2_38
.LBB2_8:
.Ltmp40:
movq %rax, %rbx
jmp .LBB2_40
.LBB2_36:
.Ltmp70:
jmp .LBB2_37
.LBB2_41:
.Ltmp65:
.LBB2_37:
movq %rax, %rbx
.LBB2_38:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_40
# %bb.39: # %.critedge.i.i26
callq _ZdlPv
.LBB2_40:
leaq 32(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end2-_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
.section .gcc_except_table._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.p2align 2, 0x0
GCC_except_table2:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp36-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp36
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp39-.Ltmp36 # Call between .Ltmp36 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin1 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp58-.Ltmp41 # Call between .Ltmp41 and .Ltmp58
.uleb128 .Ltmp70-.Lfunc_begin1 # jumps to .Ltmp70
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp64-.Ltmp59 # Call between .Ltmp59 and .Ltmp64
.uleb128 .Ltmp65-.Lfunc_begin1 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp69-.Ltmp66 # Call between .Ltmp66 and .Ltmp69
.uleb128 .Ltmp70-.Lfunc_begin1 # jumps to .Ltmp70
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp43-.Ltmp69 # Call between .Ltmp69 and .Ltmp43
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44
.uleb128 .Ltmp45-.Lfunc_begin1 # jumps to .Ltmp45
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp52-.Ltmp44 # Call between .Ltmp44 and .Ltmp52
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53
.uleb128 .Ltmp54-.Lfunc_begin1 # jumps to .Ltmp54
.byte 0 # On action: cleanup
.uleb128 .Ltmp55-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp56-.Ltmp55 # Call between .Ltmp55 and .Ltmp56
.uleb128 .Ltmp70-.Lfunc_begin1 # jumps to .Ltmp70
.byte 0 # On action: cleanup
.uleb128 .Ltmp56-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Lfunc_end2-.Ltmp56 # Call between .Ltmp56 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.weak _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $512, %rsp # imm = 0x200
.cfi_def_cfa_offset 560
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode
.Ltmp71:
movl $.L.str.9, %esi
movl $3, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp72:
# %bb.1: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl (%rbx), %esi
.Ltmp73:
movq %rsp, %rdi
callq _ZNSolsEi
.Ltmp74:
# %bb.2:
.Ltmp75:
movq %rax, %r14
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp76:
# %bb.3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit17
movl 4(%rbx), %esi
.Ltmp77:
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp78:
# %bb.4:
.Ltmp79:
movl $.L.str.11, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp80:
# %bb.5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit18
.Ltmp81:
movq %rsp, %rdi
movl $.L.str.12, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp82:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19.preheader
cmpl $0, 4(%rbx)
jle .LBB3_18
# %bb.7: # %.preheader.lr.ph
xorl %r15d, %r15d
movq %rsp, %r14
xorl %ebp, %ebp
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19
# in Loop: Header=BB3_8 Depth=1
incl %ebp
addl $3, %r15d
cmpl 4(%rbx), %ebp
jge .LBB3_18
.LBB3_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
movl (%rbx), %eax
testl %eax, %eax
jle .LBB3_17
# %bb.9: # %.lr.ph
# in Loop: Header=BB3_8 Depth=1
leal (%rax,%rax,2), %eax
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
movq 8(%rbx), %rcx
imull %ebp, %eax
cltq
addq %r12, %rax
movl (%rcx,%rax,4), %esi
.Ltmp83:
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp84:
# %bb.11: # in Loop: Header=BB3_10 Depth=2
.Ltmp85:
movl $.L.str.11, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp86:
# %bb.12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit22
# in Loop: Header=BB3_10 Depth=2
movq 8(%rbx), %rax
movl (%rbx), %ecx
imull %r15d, %ecx
movslq %ecx, %rcx
addq %r12, %rcx
movl 4(%rax,%rcx,4), %esi
.Ltmp87:
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp88:
# %bb.13: # in Loop: Header=BB3_10 Depth=2
.Ltmp89:
movl $.L.str.11, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp90:
# %bb.14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit24
# in Loop: Header=BB3_10 Depth=2
movq 8(%rbx), %rax
movl (%rbx), %ecx
imull %r15d, %ecx
movslq %ecx, %rcx
addq %r12, %rcx
movl 8(%rax,%rcx,4), %esi
.Ltmp91:
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp92:
# %bb.15: # in Loop: Header=BB3_10 Depth=2
.Ltmp93:
movl $.L.str.11, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp94:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit26
# in Loop: Header=BB3_10 Depth=2
movl (%rbx), %eax
leal (%rax,%rax,2), %eax
addq $3, %r12
cmpl %eax, %r12d
jl .LBB3_10
jmp .LBB3_17
.LBB3_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19._crit_edge
leaq 8(%rsp), %rdi
.Ltmp96:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp97:
# %bb.19: # %.noexc
testq %rax, %rax
jne .LBB3_21
# %bb.20:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rsp,%rax), %esi
orl $4, %esi
.Ltmp98:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp99:
.LBB3_21: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq %rsp, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
addq $512, %rsp # imm = 0x200
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_22:
.cfi_def_cfa_offset 560
.Ltmp100:
jmp .LBB3_23
.LBB3_24:
.Ltmp95:
.LBB3_23:
movq %rax, %rbx
movq %rsp, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end3-_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
.section .gcc_except_table._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Lfunc_begin2-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp71-.Lfunc_begin2 # Call between .Lfunc_begin2 and .Ltmp71
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp71-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp82-.Ltmp71 # Call between .Ltmp71 and .Ltmp82
.uleb128 .Ltmp100-.Lfunc_begin2 # jumps to .Ltmp100
.byte 0 # On action: cleanup
.uleb128 .Ltmp83-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp94-.Ltmp83 # Call between .Ltmp83 and .Ltmp94
.uleb128 .Ltmp95-.Lfunc_begin2 # jumps to .Ltmp95
.byte 0 # On action: cleanup
.uleb128 .Ltmp96-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp99-.Ltmp96 # Call between .Ltmp96 and .Ltmp99
.uleb128 .Ltmp100-.Lfunc_begin2 # jumps to .Ltmp100
.byte 0 # On action: cleanup
.uleb128 .Ltmp99-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Lfunc_end3-.Ltmp99 # Call between .Ltmp99 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26colorToGreyScaleConversionPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26colorToGreyScaleConversionPiS_i,@object # @_Z26colorToGreyScaleConversionPiS_i
.section .rodata,"a",@progbits
.globl _Z26colorToGreyScaleConversionPiS_i
.p2align 3, 0x0
_Z26colorToGreyScaleConversionPiS_i:
.quad _Z41__device_stub__colorToGreyScaleConversionPiS_i
.size _Z26colorToGreyScaleConversionPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "football.ppm"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Size is: "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "gfootball.ppm"
.size .L.str.2, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "P3"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Wrong image type!!"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "255"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Wrong image color depth!!"
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "P3\n"
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " "
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\n"
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "255\n"
.size .L.str.12, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26colorToGreyScaleConversionPiS_i"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__colorToGreyScaleConversionPiS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z26colorToGreyScaleConversionPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZTISt12out_of_range
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26colorToGreyScaleConversionPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R21, SR_CTAID.X ; /* 0x0000000000157919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R21, R21, c[0x0][0x0], R0 ; /* 0x0000000015157a24 */
/* 0x001fc800078e0200 */
/*0040*/ IMAD R21, R21, 0x3, RZ ; /* 0x0000000315157824 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x170], PT ; /* 0x00005c0015007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R16, R21, R16, c[0x0][0x160] ; /* 0x0000580015107625 */
/* 0x000fca00078e0210 */
/*00a0*/ LDG.E R0, [R16.64] ; /* 0x0000000410007981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ MUFU.RCP64H R3, 255 ; /* 0x406fe00000037908 */
/* 0x000e220000001800 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x240 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff077424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*0100*/ DFMA R4, R2, -R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000806 */
/*0110*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0120*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*0130*/ DFMA R6, R4, -R6, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000806 */
/*0140*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e220000000004 */
/*0150*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x004e2a0000201c00 */
/*0160*/ DMUL R18, R2, R6 ; /* 0x0000000602127228 */
/* 0x001e220000000000 */
/*0170*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fca0003f2e200 */
/*0180*/ DFMA R4, R18, -255, R2 ; /* 0xc06fe0001204782b */
/* 0x001e0c0000000002 */
/*0190*/ DFMA R18, R6, R4, R18 ; /* 0x000000040612722b */
/* 0x001e140000000012 */
/*01a0*/ FFMA R4, RZ, 3.748046875, R19 ; /* 0x406fe000ff047823 */
/* 0x001fca0000000013 */
/*01b0*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f04200 */
/*01c0*/ @P0 BRA P1, 0x230 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01e0*/ MOV R22, 0x210 ; /* 0x0000021000167802 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff057424 */
/* 0x000fe400078e00ff */
/*0200*/ CALL.REL.NOINC 0x690 ; /* 0x0000048000007944 */
/* 0x000fea0003c00000 */
/*0210*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0006 */
/*0220*/ IMAD.MOV.U32 R19, RZ, RZ, R7 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0007 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ LDG.E R0, [R16.64+0x4] ; /* 0x0000040410007981 */
/* 0x000ea2000c1e1900 */
/*0250*/ MUFU.RCP64H R3, 255 ; /* 0x406fe00000037908 */
/* 0x000e220000001800 */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*0270*/ BSSY B0, 0x400 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0280*/ IMAD.MOV.U32 R7, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff077424 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*02a0*/ DFMA R4, R2, -R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000806 */
/*02b0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*02c0*/ DFMA R2, R2, R4, R2 ; /* 0x000000040202722b */
/* 0x001e0c0000000002 */
/*02d0*/ DFMA R6, R2, -R6, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000806 */
/*02e0*/ DFMA R8, R2, R6, R2 ; /* 0x000000060208722b */
/* 0x001e220000000002 */
/*02f0*/ I2F.F64 R4, R0 ; /* 0x0000000000047312 */
/* 0x004e2a0000201c00 */
/*0300*/ DMUL R2, R8, R4 ; /* 0x0000000408027228 */
/* 0x001e220000000000 */
/*0310*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*0320*/ DFMA R6, R2, -255, R4 ; /* 0xc06fe0000206782b */
/* 0x001e0c0000000004 */
/*0330*/ DFMA R2, R8, R6, R2 ; /* 0x000000060802722b */
/* 0x001e140000000002 */
/*0340*/ FFMA R6, RZ, 3.748046875, R3 ; /* 0x406fe000ff067823 */
/* 0x001fca0000000003 */
/*0350*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*0360*/ @P0 BRA P1, 0x3f0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0370*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0380*/ MOV R22, 0x3d0 ; /* 0x000003d000167802 */
/* 0x000fe20000000f00 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*03a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*03b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff057424 */
/* 0x000fe400078e00ff */
/*03c0*/ CALL.REL.NOINC 0x690 ; /* 0x000002c000007944 */
/* 0x002fea0003c00000 */
/*03d0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fe20000000f00 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R16, [R16.64+0x8] ; /* 0x0000080410107981 */
/* 0x000ea2000c1e1900 */
/*0410*/ MUFU.RCP64H R5, 255 ; /* 0x406fe00000057908 */
/* 0x000e220000001800 */
/*0420*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*0430*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x000ee20000000000 */
/*0440*/ IMAD.MOV.U32 R7, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff077424 */
/* 0x000fe200078e00ff */
/*0450*/ BSSY B0, 0x5c0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0460*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fc600078e00ff */
/*0470*/ DFMA R18, R18, c[0x2][0x8], R2 ; /* 0x0080020012127a2b */
/* 0x008fc80000000002 */
/*0480*/ DFMA R8, R4, -R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000806 */
/*0490*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*04a0*/ DFMA R8, R4, R8, R4 ; /* 0x000000080408722b */
/* 0x001e0c0000000004 */
/*04b0*/ DFMA R6, R8, -R6, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c0000000806 */
/*04c0*/ DFMA R10, R8, R6, R8 ; /* 0x00000006080a722b */
/* 0x001e220000000008 */
/*04d0*/ I2F.F64 R4, R16 ; /* 0x0000001000047312 */
/* 0x004e2a0000201c00 */
/*04e0*/ DMUL R6, R10, R4 ; /* 0x000000040a067228 */
/* 0x001e220000000000 */
/*04f0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*0500*/ DFMA R8, R6, -255, R4 ; /* 0xc06fe0000608782b */
/* 0x001e0c0000000004 */
/*0510*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x001e140000000006 */
/*0520*/ FFMA R0, RZ, 3.748046875, R7 ; /* 0x406fe000ff007823 */
/* 0x001fca0000000007 */
/*0530*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0540*/ @P0 BRA P1, 0x5b0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0550*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0560*/ MOV R22, 0x5b0 ; /* 0x000005b000167802 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*0580*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.MOV.U32 R5, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff057424 */
/* 0x000fe400078e00ff */
/*05a0*/ CALL.REL.NOINC 0x690 ; /* 0x000000e000007944 */
/* 0x002fea0003c00000 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ DFMA R18, R6, c[0x2][0x10], R18 ; /* 0x0080040006127a2b */
/* 0x000e220000000012 */
/*05d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*05e0*/ IMAD.WIDE R4, R21, R4, c[0x0][0x168] ; /* 0x00005a0015047625 */
/* 0x000fe200078e0204 */
/*05f0*/ DMUL R18, R18, 255 ; /* 0x406fe00012127828 */
/* 0x001e140000000000 */
/*0600*/ LOP3.LUT R2, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013027812 */
/* 0x001fc800078ec0ff */
/*0610*/ LOP3.LUT R3, R2, 0x3fe00000, RZ, 0xfc, !PT ; /* 0x3fe0000002037812 */
/* 0x000fe200078efcff */
/*0620*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0630*/ DADD.RZ R2, R18, R2 ; /* 0x0000000012027229 */
/* 0x000e14000000c002 */
/*0640*/ F2I.F64.TRUNC R3, R2 ; /* 0x0000000200037311 */
/* 0x001e24000030d100 */
/*0650*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe8000c101904 */
/*0660*/ STG.E [R4.64+0x4], R3 ; /* 0x0000040304007986 */
/* 0x000fe8000c101904 */
/*0670*/ STG.E [R4.64+0x8], R3 ; /* 0x0000080304007986 */
/* 0x000fe2000c101904 */
/*0680*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0690*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*06a0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x1 ; /* 0x00000001ff187424 */
/* 0x000fe200078e00ff */
/*06b0*/ LOP3.LUT R6, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05067812 */
/* 0x000fe200078ec0ff */
/*06c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*06d0*/ FSETP.GEU.AND P2, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f4e200 */
/*06e0*/ BSSY B1, 0xc30 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*06f0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0710*/ LOP3.LUT R23, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003177812 */
/* 0x000fc400078ec0ff */
/*0720*/ LOP3.LUT R14, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050e7812 */
/* 0x000fe400078ec0ff */
/*0730*/ MOV R20, 0x1ca00000 ; /* 0x1ca0000000147802 */
/* 0x000fe20000000f00 */
/*0740*/ @!P0 DMUL R6, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004068828 */
/* 0x000e220000000000 */
/*0750*/ ISETP.GE.U32.AND P1, PT, R23, R14, PT ; /* 0x0000000e1700720c */
/* 0x000fc60003f26070 */
/*0760*/ @!P2 LOP3.LUT R0, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000500a812 */
/* 0x000fe200078ec0ff */
/*0770*/ @!P2 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0ca224 */
/* 0x000fe200078e00ff */
/*0780*/ MUFU.RCP64H R25, R7 ; /* 0x0000000700197308 */
/* 0x001e220000001800 */
/*0790*/ SEL R9, R20.reuse, 0x63400000, !P1 ; /* 0x6340000014097807 */
/* 0x040fe40004800000 */
/*07a0*/ @!P2 ISETP.GE.U32.AND P3, PT, R23, R0, PT ; /* 0x000000001700a20c */
/* 0x000fe20003f66070 */
/*07b0*/ IMAD.MOV.U32 R0, RZ, RZ, R23 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0017 */
/*07c0*/ LOP3.LUT R9, R9, 0x800fffff, R3, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fe400078ef803 */
/*07d0*/ @!P2 SEL R13, R20, 0x63400000, !P3 ; /* 0x63400000140da807 */
/* 0x000fc80005800000 */
/*07e0*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R3, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fc800078ef803 */
/*07f0*/ @!P2 LOP3.LUT R13, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d0da812 */
/* 0x000fe200078efcff */
/*0800*/ DFMA R10, R24, -R6, 1 ; /* 0x3ff00000180a742b */
/* 0x001e0a0000000806 */
/*0810*/ @!P2 DFMA R8, R8, 2, -R12 ; /* 0x400000000808a82b */
/* 0x000fc8000000080c */
/*0820*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0830*/ DFMA R10, R24, R10, R24 ; /* 0x0000000a180a722b */
/* 0x0010620000000018 */
/*0840*/ @!P2 LOP3.LUT R0, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000900a812 */
/* 0x000fe200078ec0ff */
/*0850*/ IMAD.MOV.U32 R25, RZ, RZ, R14 ; /* 0x000000ffff197224 */
/* 0x001fe200078e000e */
/*0860*/ @!P0 LOP3.LUT R25, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007198812 */
/* 0x000fe400078ec0ff */
/*0870*/ IADD3 R14, R0, -0x1, RZ ; /* 0xffffffff000e7810 */
/* 0x000fe20007ffe0ff */
/*0880*/ DFMA R12, R10, -R6, 1 ; /* 0x3ff000000a0c742b */
/* 0x002e220000000806 */
/*0890*/ IADD3 R24, R25, -0x1, RZ ; /* 0xffffffff19187810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ; /* 0x7feffffe0e00780c */
/* 0x000fc60003f04070 */
/*08b0*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e22000000000a */
/*08c0*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fca0000704470 */
/*08d0*/ DMUL R12, R10, R8 ; /* 0x000000080a0c7228 */
/* 0x001e0c0000000000 */
/*08e0*/ DFMA R14, R12, -R6, R8 ; /* 0x800000060c0e722b */
/* 0x001e0c0000000008 */
/*08f0*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x001062000000000c */
/*0900*/ @P0 BRA 0xad0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0910*/ LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005027812 */
/* 0x000fc800078ec0ff */
/*0920*/ ISETP.GE.U32.AND P0, PT, R23.reuse, R2, PT ; /* 0x000000021700720c */
/* 0x040fe20003f06070 */
/*0930*/ IMAD.IADD R0, R23, 0x1, -R2 ; /* 0x0000000117007824 */
/* 0x000fe400078e0a02 */
/*0940*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0950*/ SEL R3, R20, 0x63400000, !P0 ; /* 0x6340000014037807 */
/* 0x000fe40004000000 */
/*0960*/ IMNMX R0, R0, -0x46a00000, !PT ; /* 0xb960000000007817 */
/* 0x000fc80007800200 */
/*0970*/ IMNMX R0, R0, 0x46a00000, PT ; /* 0x46a0000000007817 */
/* 0x000fca0003800200 */
/*0980*/ IMAD.IADD R0, R0, 0x1, -R3 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a03 */
/*0990*/ IADD3 R3, R0, 0x7fe00000, RZ ; /* 0x7fe0000000037810 */
/* 0x000fcc0007ffe0ff */
/*09a0*/ DMUL R10, R14, R2 ; /* 0x000000020e0a7228 */
/* 0x003e140000000000 */
/*09b0*/ FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x001fda0003f0c200 */
/*09c0*/ @P0 BRA 0xc20 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*09d0*/ DFMA R6, R14, -R6, R8 ; /* 0x800000060e06722b */
/* 0x000e220000000008 */
/*09e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd200078e00ff */
/*09f0*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0a00*/ LOP3.LUT R9, R7, 0x80000000, R5, 0x48, !PT ; /* 0x8000000007097812 */
/* 0x000fc800078e4805 */
/*0a10*/ LOP3.LUT R3, R9, R3, RZ, 0xfc, !PT ; /* 0x0000000309037212 */
/* 0x000fce00078efcff */
/*0a20*/ @!P0 BRA 0xc20 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0a30*/ IMAD.MOV R5, RZ, RZ, -R0 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a00 */
/*0a40*/ DMUL.RP R2, R14, R2 ; /* 0x000000020e027228 */
/* 0x000e220000008000 */
/*0a50*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0a60*/ DFMA R4, R10, -R4, R14 ; /* 0x800000040a04722b */
/* 0x000e46000000000e */
/*0a70*/ LOP3.LUT R9, R3, R9, RZ, 0x3c, !PT ; /* 0x0000000903097212 */
/* 0x001fc600078e3cff */
/*0a80*/ IADD3 R4, -R0, -0x43300000, RZ ; /* 0xbcd0000000047810 */
/* 0x002fc80007ffe1ff */
/*0a90*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0aa0*/ FSEL R10, R2, R10, !P0 ; /* 0x0000000a020a7208 */
/* 0x000fe40004000000 */
/*0ab0*/ FSEL R11, R9, R11, !P0 ; /* 0x0000000b090b7208 */
/* 0x000fe20004000000 */
/*0ac0*/ BRA 0xc20 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0ad0*/ DSETP.NAN.AND P0, PT, R2, R2, PT ; /* 0x000000020200722a */
/* 0x000e9c0003f08000 */
/*0ae0*/ @P0 BRA 0xc00 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0af0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0b00*/ @P0 BRA 0xbd0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0b10*/ ISETP.NE.AND P0, PT, R0, R25, PT ; /* 0x000000190000720c */
/* 0x000fe20003f05270 */
/*0b20*/ IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b7424 */
/* 0x001fe200078e00ff */
/*0b30*/ MOV R10, 0x0 ; /* 0x00000000000a7802 */
/* 0x000fd60000000f00 */
/*0b40*/ @!P0 BRA 0xc20 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b50*/ ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fe40003f05270 */
/*0b60*/ LOP3.LUT R11, R3, 0x80000000, R5, 0x48, !PT ; /* 0x80000000030b7812 */
/* 0x000fe400078e4805 */
/*0b70*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*0b80*/ @P0 LOP3.LUT R0, R11, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000b000812 */
/* 0x000fe200078efcff */
/*0b90*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e00ff */
/*0ba0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0bb0*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e0000 */
/*0bc0*/ BRA 0xc20 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ LOP3.LUT R11, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050b7812 */
/* 0x001fe200078efcff */
/*0be0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*0bf0*/ BRA 0xc20 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c00*/ LOP3.LUT R11, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000030b7812 */
/* 0x001fe200078efcff */
/*0c10*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0c20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c30*/ IMAD.MOV.U32 R23, RZ, RZ, 0x0 ; /* 0x00000000ff177424 */
/* 0x000fe400078e00ff */
/*0c40*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fc400078e000a */
/*0c50*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*0c60*/ RET.REL.NODEC R22 0x0 ; /* 0xfffff39016007950 */
/* 0x000fec0003c3ffff */
/*0c70*/ BRA 0xc70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26colorToGreyScaleConversionPiS_i
.globl _Z26colorToGreyScaleConversionPiS_i
.p2align 8
.type _Z26colorToGreyScaleConversionPiS_i,@function
_Z26colorToGreyScaleConversionPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v0, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s5, 0x3fe6b851
s_mov_b32 s4, 0xeb851eb8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v32, vcc_lo, v0, 4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v33, vcc_lo, 0, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v32
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v33, vcc_lo
v_add_co_u32 v34, vcc_lo, v0, 8
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v35, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v34
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v35, vcc_lo
global_load_b32 v10, v[2:3], off
s_waitcnt vmcnt(2)
v_cvt_f64_i32_e32 v[2:3], v6
s_waitcnt vmcnt(1)
v_cvt_f64_i32_e32 v[4:5], v4
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f64 v[6:7], null, 0x406fe000, 0x406fe000, v[2:3]
v_div_scale_f64 v[8:9], null, 0x406fe000, 0x406fe000, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_scale_f64 v[16:17], null, 0x406fe000, 0x406fe000, v[10:11]
v_div_scale_f64 v[30:31], s1, v[10:11], 0x406fe000, v[10:11]
v_rcp_f64_e32 v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[8:9]
v_rcp_f64_e32 v[22:23], v[16:17]
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], -v[6:7], v[12:13], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[8:9], v[14:15], 1.0
v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
v_fma_f64 v[18:19], -v[16:17], v[22:23], 1.0
v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[20:21], -v[6:7], v[12:13], 1.0
v_fma_f64 v[18:19], v[22:23], v[18:19], v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[24:25], -v[8:9], v[14:15], 1.0
v_div_scale_f64 v[22:23], vcc_lo, v[2:3], 0x406fe000, v[2:3]
v_fma_f64 v[12:13], v[12:13], v[20:21], v[12:13]
v_div_scale_f64 v[20:21], s0, v[4:5], 0x406fe000, v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[14:15], v[14:15], v[24:25], v[14:15]
v_fma_f64 v[24:25], -v[16:17], v[18:19], 1.0
v_mul_f64 v[26:27], v[22:23], v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[28:29], v[20:21], v[14:15]
v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], -v[6:7], v[26:27], v[22:23]
v_fma_f64 v[8:9], -v[8:9], v[28:29], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[20:21], v[30:31], v[18:19]
v_div_fmas_f64 v[6:7], v[6:7], v[12:13], v[26:27]
s_mov_b32 vcc_lo, s0
s_mov_b32 s0, 0xae147ae1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[28:29]
v_fma_f64 v[12:13], -v[16:17], v[20:21], v[30:31]
s_mov_b32 vcc_lo, s1
s_mov_b32 s1, 0x3fcae147
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[2:3], v[6:7], 0x406fe000, v[2:3]
v_div_fixup_f64 v[4:5], v[8:9], 0x406fe000, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[8:9], v[12:13], v[18:19], v[20:21]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mul_f64 v[4:5], v[4:5], s[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[6:7], v[8:9], 0x406fe000, v[10:11]
v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5]
s_mov_b32 s1, 0x3fb1eb85
s_mov_b32 s0, 0x1eb851ec
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[6:7], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], 0x406fe000
v_trunc_f64_e32 v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[2:3], -v[4:5]
v_mov_b32_e32 v2, 0
v_cmp_ge_f64_e64 s0, |v[6:7]|, 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, 0, 0x3ff00000, s0
v_bfi_b32 v3, 0x7fffffff, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[4:5], v[2:3]
v_cvt_i32_f64_e32 v6, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v32
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v33, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v34
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v35, vcc_lo
s_clause 0x2
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v6, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26colorToGreyScaleConversionPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 36
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26colorToGreyScaleConversionPiS_i, .Lfunc_end0-_Z26colorToGreyScaleConversionPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26colorToGreyScaleConversionPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26colorToGreyScaleConversionPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 36
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reg_addArrays_kernel_float4(float4 *array1_d, float4 *array2_d)
{
const int tid= (blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
if(tid < c_VoxelNumber){
float4 a = array1_d[tid];
float4 b = array1_d[tid];
array1_d[tid] = make_float4(a.x+b.x,a.y+b.y,a.z+b.z,a.w+b.w);
}
} | code for sm_80
Function : _Z27reg_addArrays_kernel_float4P6float4S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x3][0x0], PT ; /* 0x00c0000000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff037435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E.128 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1d00 */
/*00c0*/ FADD R7, R7, R7 ; /* 0x0000000707077221 */
/* 0x004fe40000000000 */
/*00d0*/ FADD R6, R6, R6 ; /* 0x0000000606067221 */
/* 0x000fe40000000000 */
/*00e0*/ FADD R5, R5, R5 ; /* 0x0000000505057221 */
/* 0x000fe40000000000 */
/*00f0*/ FADD R4, R4, R4 ; /* 0x0000000404047221 */
/* 0x000fca0000000000 */
/*0100*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101d04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reg_addArrays_kernel_float4(float4 *array1_d, float4 *array2_d)
{
const int tid= (blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
if(tid < c_VoxelNumber){
float4 a = array1_d[tid];
float4 b = array1_d[tid];
array1_d[tid] = make_float4(a.x+b.x,a.y+b.y,a.z+b.z,a.w+b.w);
}
} | .file "tmpxft_00042352_00000000-6_reg_addArrays_kernel_float4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_
.type _Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_, @function
_Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z27reg_addArrays_kernel_float4P6float4S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_, .-_Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_
.globl _Z27reg_addArrays_kernel_float4P6float4S0_
.type _Z27reg_addArrays_kernel_float4P6float4S0_, @function
_Z27reg_addArrays_kernel_float4P6float4S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27reg_addArrays_kernel_float4P6float4S0_, .-_Z27reg_addArrays_kernel_float4P6float4S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27reg_addArrays_kernel_float4P6float4S0_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c_VoxelNumber"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27reg_addArrays_kernel_float4P6float4S0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13c_VoxelNumber(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL13c_VoxelNumber
.comm _ZL13c_VoxelNumber,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reg_addArrays_kernel_float4(float4 *array1_d, float4 *array2_d)
{
const int tid= (blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
if(tid < c_VoxelNumber){
float4 a = array1_d[tid];
float4 b = array1_d[tid];
array1_d[tid] = make_float4(a.x+b.x,a.y+b.y,a.z+b.z,a.w+b.w);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reg_addArrays_kernel_float4(float4 *array1_d, float4 *array2_d)
{
const int tid= (blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
if(tid < c_VoxelNumber){
float4 a = array1_d[tid];
float4 b = array1_d[tid];
array1_d[tid] = make_float4(a.x+b.x,a.y+b.y,a.z+b.z,a.w+b.w);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reg_addArrays_kernel_float4(float4 *array1_d, float4 *array2_d)
{
const int tid= (blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
if(tid < c_VoxelNumber){
float4 a = array1_d[tid];
float4 b = array1_d[tid];
array1_d[tid] = make_float4(a.x+b.x,a.y+b.y,a.z+b.z,a.w+b.w);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.globl _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.p2align 8
.type _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_,@function
_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, c_VoxelNumber@rel32@lo+4
s_addc_u32 s3, s3, c_VoxelNumber@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s15
s_and_b32 s4, s5, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b128 v[0:3], v[4:5], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v0 :: v_dual_add_f32 v1, v1, v1
v_dual_add_f32 v2, v2, v2 :: v_dual_add_f32 v3, v3, v3
global_store_b128 v[4:5], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_VoxelNumber
.type c_VoxelNumber,@object
.section .bss,"aw",@nobits
.globl c_VoxelNumber
.p2align 2, 0x0
c_VoxelNumber:
.long 0
.size c_VoxelNumber, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_VoxelNumber
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reg_addArrays_kernel_float4(float4 *array1_d, float4 *array2_d)
{
const int tid= (blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
if(tid < c_VoxelNumber){
float4 a = array1_d[tid];
float4 b = array1_d[tid];
array1_d[tid] = make_float4(a.x+b.x,a.y+b.y,a.z+b.z,a.w+b.w);
}
} | .text
.file "reg_addArrays_kernel_float4.hip"
.globl _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_ # -- Begin function _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.p2align 4, 0x90
.type _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_,@function
_Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_: # @_Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_VoxelNumber, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_VoxelNumber,@object # @c_VoxelNumber
.local c_VoxelNumber
.comm c_VoxelNumber,4,4
.type _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_,@object # @_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.section .rodata,"a",@progbits
.globl _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.p2align 3, 0x0
_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_:
.quad _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.size _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_"
.size .L__unnamed_1, 60
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_VoxelNumber"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_VoxelNumber
.addrsig_sym _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27reg_addArrays_kernel_float4P6float4S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x3][0x0], PT ; /* 0x00c0000000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff037435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E.128 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1d00 */
/*00c0*/ FADD R7, R7, R7 ; /* 0x0000000707077221 */
/* 0x004fe40000000000 */
/*00d0*/ FADD R6, R6, R6 ; /* 0x0000000606067221 */
/* 0x000fe40000000000 */
/*00e0*/ FADD R5, R5, R5 ; /* 0x0000000505057221 */
/* 0x000fe40000000000 */
/*00f0*/ FADD R4, R4, R4 ; /* 0x0000000404047221 */
/* 0x000fca0000000000 */
/*0100*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101d04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.globl _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.p2align 8
.type _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_,@function
_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, c_VoxelNumber@rel32@lo+4
s_addc_u32 s3, s3, c_VoxelNumber@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s15
s_and_b32 s4, s5, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b128 v[0:3], v[4:5], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v0 :: v_dual_add_f32 v1, v1, v1
v_dual_add_f32 v2, v2, v2 :: v_dual_add_f32 v3, v3, v3
global_store_b128 v[4:5], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_VoxelNumber
.type c_VoxelNumber,@object
.section .bss,"aw",@nobits
.globl c_VoxelNumber
.p2align 2, 0x0
c_VoxelNumber:
.long 0
.size c_VoxelNumber, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_VoxelNumber
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00042352_00000000-6_reg_addArrays_kernel_float4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_
.type _Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_, @function
_Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z27reg_addArrays_kernel_float4P6float4S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_, .-_Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_
.globl _Z27reg_addArrays_kernel_float4P6float4S0_
.type _Z27reg_addArrays_kernel_float4P6float4S0_, @function
_Z27reg_addArrays_kernel_float4P6float4S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z27reg_addArrays_kernel_float4P6float4S0_P6float4S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27reg_addArrays_kernel_float4P6float4S0_, .-_Z27reg_addArrays_kernel_float4P6float4S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27reg_addArrays_kernel_float4P6float4S0_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c_VoxelNumber"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27reg_addArrays_kernel_float4P6float4S0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13c_VoxelNumber(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL13c_VoxelNumber
.comm _ZL13c_VoxelNumber,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reg_addArrays_kernel_float4.hip"
.globl _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_ # -- Begin function _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.p2align 4, 0x90
.type _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_,@function
_Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_: # @_Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_VoxelNumber, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_VoxelNumber,@object # @c_VoxelNumber
.local c_VoxelNumber
.comm c_VoxelNumber,4,4
.type _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_,@object # @_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.section .rodata,"a",@progbits
.globl _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.p2align 3, 0x0
_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_:
.quad _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.size _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_"
.size .L__unnamed_1, 60
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_VoxelNumber"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_VoxelNumber
.addrsig_sym _Z27reg_addArrays_kernel_float4P15HIP_vector_typeIfLj4EES1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
*
* Programa de Introducción a los conceptos de CUDA
* Mariana Hernández
* Alan Córdova
*
*
*/
#include <stdio.h>
#include <stdlib.h>
/* Declaración de métodos/
/* Utilidad para checar errores de CUDA */
void checkCUDAError(const char*);
/* Kernel para sumar dos vectores en un sólo bloque de hilos */
__global__ void vect_add(int *d_a, int *d_b, int *d_c)
{
/* Part 2B: Implementación del kernel para realizar la suma de los vectores en el GPU */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Versión de múltiples bloques de la suma de vectores */
__global__ void vect_add_multiblock(int *d_a, int *d_b, int *d_c)
{
/* Part 2C: Implementación del kernel pero esta vez permitiendo múltiples bloques de hilos. */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Numero de elementos en el vector */
#define ARRAY_SIZE 256
/*
* Número de bloques e hilos
* Su producto siempre debe ser el tamaño del vector (arreglo).
*/
#define NUM_BLOCKS 1
#define THREADS_PER_BLOCK 256
/* Main routine */
int main(int argc, char *argv[])
{
int *a, *b, *c, *d; /* Arreglos del CPU */
int *d_a, *d_b, *d_c, *d_d;/* Arreglos del GPU */
int i;
size_t sz = ARRAY_SIZE * sizeof(int);
/*
* Reservar memoria en el cpu
*/
a = (int *) malloc(sz);
b = (int *) malloc(sz);
c = (int *) malloc(sz);
d = (int *) malloc(sz);
/*
* Parte 1A:Reservar memoria en el GPU
*/
cudaMalloc(&d_a, sz);
cudaMalloc(&d_b, sz);
cudaMalloc(&d_c, sz);
cudaMalloc(&d_d, sz);
/* inicialización */
for (i = 0; i < ARRAY_SIZE; i++) {
a[i] = i;
b[i] = ARRAY_SIZE - i;
c[i] = 0;
d[i] = 0;
}
/* Parte 1B: Copiar los vectores del CPU al GPU */
cudaMemcpy(d_a, a, sz, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sz, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, sz, cudaMemcpyHostToDevice);
cudaMemcpy(d_d, d, sz, cudaMemcpyHostToDevice);
/* run the kernel on the GPU */
/* Parte 2A: Configurar y llamar los kernels */
/* dim3 dimGrid( ); */
/* dim3 dimBlock( ); */
/* vect_add<<< , >>>( ); */
//invocamos kernel
int threadsPerBlock = 64; // ARRAY_SIZE/NUM_BLOCKS
int blocksPerGrid = 4; // nuevo NUM_BLOCKS
// Para obtener tiempos de ejecucion del kernel
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
vect_add<<< NUM_BLOCKS , THREADS_PER_BLOCK >>> (d_a, d_b, d_c);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add: \t %f \n", milliseconds);
cudaEventRecord(start);
vect_add_multiblock<<< blocksPerGrid , threadsPerBlock >>> (d_a, d_b, d_d);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add_multiblock (4 bloques): \t %f \n", milliseconds);
/* Esperar a que todos los threads acaben y checar por errores */
cudaThreadSynchronize();
checkCUDAError("kernel invocation");
/* Part 1C: copiar el resultado de nuevo al CPU */
cudaMemcpy(a, d_a, sz, cudaMemcpyDeviceToHost);
cudaMemcpy(b, d_b, sz, cudaMemcpyDeviceToHost);
cudaMemcpy(c, d_c, sz, cudaMemcpyDeviceToHost);
cudaMemcpy(d, d_d, sz, cudaMemcpyDeviceToHost);
checkCUDAError("memcpy");
/* print out the result */
printf("Results: ");
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", c[i]);
}
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", d[i] );
}
printf("\n\n");
/* Parte 1D: Liberar los arreglos */
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFree(d_d);
free(a);
free(b);
free(c);
free(d);
return 0;
}
/* Utility function to check for and report CUDA errors */
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | code for sm_80
Function : _Z19vect_add_multiblockPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8vect_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
*
* Programa de Introducción a los conceptos de CUDA
* Mariana Hernández
* Alan Córdova
*
*
*/
#include <stdio.h>
#include <stdlib.h>
/* Declaración de métodos/
/* Utilidad para checar errores de CUDA */
void checkCUDAError(const char*);
/* Kernel para sumar dos vectores en un sólo bloque de hilos */
__global__ void vect_add(int *d_a, int *d_b, int *d_c)
{
/* Part 2B: Implementación del kernel para realizar la suma de los vectores en el GPU */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Versión de múltiples bloques de la suma de vectores */
__global__ void vect_add_multiblock(int *d_a, int *d_b, int *d_c)
{
/* Part 2C: Implementación del kernel pero esta vez permitiendo múltiples bloques de hilos. */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Numero de elementos en el vector */
#define ARRAY_SIZE 256
/*
* Número de bloques e hilos
* Su producto siempre debe ser el tamaño del vector (arreglo).
*/
#define NUM_BLOCKS 1
#define THREADS_PER_BLOCK 256
/* Main routine */
int main(int argc, char *argv[])
{
int *a, *b, *c, *d; /* Arreglos del CPU */
int *d_a, *d_b, *d_c, *d_d;/* Arreglos del GPU */
int i;
size_t sz = ARRAY_SIZE * sizeof(int);
/*
* Reservar memoria en el cpu
*/
a = (int *) malloc(sz);
b = (int *) malloc(sz);
c = (int *) malloc(sz);
d = (int *) malloc(sz);
/*
* Parte 1A:Reservar memoria en el GPU
*/
cudaMalloc(&d_a, sz);
cudaMalloc(&d_b, sz);
cudaMalloc(&d_c, sz);
cudaMalloc(&d_d, sz);
/* inicialización */
for (i = 0; i < ARRAY_SIZE; i++) {
a[i] = i;
b[i] = ARRAY_SIZE - i;
c[i] = 0;
d[i] = 0;
}
/* Parte 1B: Copiar los vectores del CPU al GPU */
cudaMemcpy(d_a, a, sz, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sz, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, sz, cudaMemcpyHostToDevice);
cudaMemcpy(d_d, d, sz, cudaMemcpyHostToDevice);
/* run the kernel on the GPU */
/* Parte 2A: Configurar y llamar los kernels */
/* dim3 dimGrid( ); */
/* dim3 dimBlock( ); */
/* vect_add<<< , >>>( ); */
//invocamos kernel
int threadsPerBlock = 64; // ARRAY_SIZE/NUM_BLOCKS
int blocksPerGrid = 4; // nuevo NUM_BLOCKS
// Para obtener tiempos de ejecucion del kernel
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
vect_add<<< NUM_BLOCKS , THREADS_PER_BLOCK >>> (d_a, d_b, d_c);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add: \t %f \n", milliseconds);
cudaEventRecord(start);
vect_add_multiblock<<< blocksPerGrid , threadsPerBlock >>> (d_a, d_b, d_d);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add_multiblock (4 bloques): \t %f \n", milliseconds);
/* Esperar a que todos los threads acaben y checar por errores */
cudaThreadSynchronize();
checkCUDAError("kernel invocation");
/* Part 1C: copiar el resultado de nuevo al CPU */
cudaMemcpy(a, d_a, sz, cudaMemcpyDeviceToHost);
cudaMemcpy(b, d_b, sz, cudaMemcpyDeviceToHost);
cudaMemcpy(c, d_c, sz, cudaMemcpyDeviceToHost);
cudaMemcpy(d, d_d, sz, cudaMemcpyDeviceToHost);
checkCUDAError("memcpy");
/* print out the result */
printf("Results: ");
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", c[i]);
}
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", d[i] );
}
printf("\n\n");
/* Parte 1D: Liberar los arreglos */
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFree(d_d);
free(a);
free(b);
free(c);
free(d);
return 0;
}
/* Utility function to check for and report CUDA errors */
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .file "tmpxft_00003ac1_00000000-6_intro.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
.type _Z31__device_stub__Z8vect_addPiS_S_PiS_S_, @function
_Z31__device_stub__Z8vect_addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8vect_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z8vect_addPiS_S_PiS_S_, .-_Z31__device_stub__Z8vect_addPiS_S_PiS_S_
.globl _Z8vect_addPiS_S_
.type _Z8vect_addPiS_S_, @function
_Z8vect_addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8vect_addPiS_S_, .-_Z8vect_addPiS_S_
.globl _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_
.type _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_, @function
_Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19vect_add_multiblockPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_, .-_Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_
.globl _Z19vect_add_multiblockPiS_S_
.type _Z19vect_add_multiblockPiS_S_, @function
_Z19vect_add_multiblockPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19vect_add_multiblockPiS_S_, .-_Z19vect_add_multiblockPiS_S_
.section .rodata.str1.1
.LC2:
.string "Tiempo de vect_add: \t %f \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Tiempo de vect_add_multiblock (4 bloques): \t %f \n"
.section .rodata.str1.1
.LC4:
.string "kernel invocation"
.LC5:
.string "memcpy"
.LC6:
.string "Results: "
.LC7:
.string "%d, "
.LC8:
.string "\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1024, %edi
call malloc@PLT
movq %rax, %r14
movl $1024, %edi
call malloc@PLT
movq %rax, %r13
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $1024, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $0, %eax
movl $256, %ecx
.L24:
movl %eax, (%r14,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, 0(%r13,%rax,4)
movl $0, 0(%rbp,%rax,4)
movl $0, (%r12,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L24
movl $1, %ecx
movl $1024, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L25:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $64, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L26:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaThreadSynchronize@PLT
leaq .LC4(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rdi
call _Z14checkCUDAErrorPKc
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 1024(%rbp), %r15
.L27:
movl (%rbx), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L27
movq %r12, %rbx
leaq 1024(%r12), %r15
.L28:
movl (%rbx), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L28
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
jmp .L25
.L35:
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_
jmp .L26
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z19vect_add_multiblockPiS_S_"
.LC10:
.string "_Z8vect_addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z19vect_add_multiblockPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vect_addPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
*
* Programa de Introducción a los conceptos de CUDA
* Mariana Hernández
* Alan Córdova
*
*
*/
#include <stdio.h>
#include <stdlib.h>
/* Declaración de métodos/
/* Utilidad para checar errores de CUDA */
void checkCUDAError(const char*);
/* Kernel para sumar dos vectores en un sólo bloque de hilos */
__global__ void vect_add(int *d_a, int *d_b, int *d_c)
{
/* Part 2B: Implementación del kernel para realizar la suma de los vectores en el GPU */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Versión de múltiples bloques de la suma de vectores */
__global__ void vect_add_multiblock(int *d_a, int *d_b, int *d_c)
{
/* Part 2C: Implementación del kernel pero esta vez permitiendo múltiples bloques de hilos. */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Numero de elementos en el vector */
#define ARRAY_SIZE 256
/*
* Número de bloques e hilos
* Su producto siempre debe ser el tamaño del vector (arreglo).
*/
#define NUM_BLOCKS 1
#define THREADS_PER_BLOCK 256
/* Main routine */
int main(int argc, char *argv[])
{
int *a, *b, *c, *d; /* Arreglos del CPU */
int *d_a, *d_b, *d_c, *d_d;/* Arreglos del GPU */
int i;
size_t sz = ARRAY_SIZE * sizeof(int);
/*
* Reservar memoria en el cpu
*/
a = (int *) malloc(sz);
b = (int *) malloc(sz);
c = (int *) malloc(sz);
d = (int *) malloc(sz);
/*
* Parte 1A:Reservar memoria en el GPU
*/
cudaMalloc(&d_a, sz);
cudaMalloc(&d_b, sz);
cudaMalloc(&d_c, sz);
cudaMalloc(&d_d, sz);
/* inicialización */
for (i = 0; i < ARRAY_SIZE; i++) {
a[i] = i;
b[i] = ARRAY_SIZE - i;
c[i] = 0;
d[i] = 0;
}
/* Parte 1B: Copiar los vectores del CPU al GPU */
cudaMemcpy(d_a, a, sz, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sz, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, sz, cudaMemcpyHostToDevice);
cudaMemcpy(d_d, d, sz, cudaMemcpyHostToDevice);
/* run the kernel on the GPU */
/* Parte 2A: Configurar y llamar los kernels */
/* dim3 dimGrid( ); */
/* dim3 dimBlock( ); */
/* vect_add<<< , >>>( ); */
//invocamos kernel
int threadsPerBlock = 64; // ARRAY_SIZE/NUM_BLOCKS
int blocksPerGrid = 4; // nuevo NUM_BLOCKS
// Para obtener tiempos de ejecucion del kernel
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
vect_add<<< NUM_BLOCKS , THREADS_PER_BLOCK >>> (d_a, d_b, d_c);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add: \t %f \n", milliseconds);
cudaEventRecord(start);
vect_add_multiblock<<< blocksPerGrid , threadsPerBlock >>> (d_a, d_b, d_d);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add_multiblock (4 bloques): \t %f \n", milliseconds);
/* Esperar a que todos los threads acaben y checar por errores */
cudaThreadSynchronize();
checkCUDAError("kernel invocation");
/* Part 1C: copiar el resultado de nuevo al CPU */
cudaMemcpy(a, d_a, sz, cudaMemcpyDeviceToHost);
cudaMemcpy(b, d_b, sz, cudaMemcpyDeviceToHost);
cudaMemcpy(c, d_c, sz, cudaMemcpyDeviceToHost);
cudaMemcpy(d, d_d, sz, cudaMemcpyDeviceToHost);
checkCUDAError("memcpy");
/* print out the result */
printf("Results: ");
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", c[i]);
}
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", d[i] );
}
printf("\n\n");
/* Parte 1D: Liberar los arreglos */
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFree(d_d);
free(a);
free(b);
free(c);
free(d);
return 0;
}
/* Utility function to check for and report CUDA errors */
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | /*
*
* Programa de Introducción a los conceptos de CUDA
* Mariana Hernández
* Alan Córdova
*
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/* Declaración de métodos/
/* Utilidad para checar errores de CUDA */
void checkCUDAError(const char*);
/* Kernel para sumar dos vectores en un sólo bloque de hilos */
__global__ void vect_add(int *d_a, int *d_b, int *d_c)
{
/* Part 2B: Implementación del kernel para realizar la suma de los vectores en el GPU */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Versión de múltiples bloques de la suma de vectores */
__global__ void vect_add_multiblock(int *d_a, int *d_b, int *d_c)
{
/* Part 2C: Implementación del kernel pero esta vez permitiendo múltiples bloques de hilos. */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Numero de elementos en el vector */
#define ARRAY_SIZE 256
/*
* Número de bloques e hilos
* Su producto siempre debe ser el tamaño del vector (arreglo).
*/
#define NUM_BLOCKS 1
#define THREADS_PER_BLOCK 256
/* Main routine */
int main(int argc, char *argv[])
{
int *a, *b, *c, *d; /* Arreglos del CPU */
int *d_a, *d_b, *d_c, *d_d;/* Arreglos del GPU */
int i;
size_t sz = ARRAY_SIZE * sizeof(int);
/*
* Reservar memoria en el cpu
*/
a = (int *) malloc(sz);
b = (int *) malloc(sz);
c = (int *) malloc(sz);
d = (int *) malloc(sz);
/*
* Parte 1A:Reservar memoria en el GPU
*/
hipMalloc(&d_a, sz);
hipMalloc(&d_b, sz);
hipMalloc(&d_c, sz);
hipMalloc(&d_d, sz);
/* inicialización */
for (i = 0; i < ARRAY_SIZE; i++) {
a[i] = i;
b[i] = ARRAY_SIZE - i;
c[i] = 0;
d[i] = 0;
}
/* Parte 1B: Copiar los vectores del CPU al GPU */
hipMemcpy(d_a, a, sz, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sz, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, sz, hipMemcpyHostToDevice);
hipMemcpy(d_d, d, sz, hipMemcpyHostToDevice);
/* run the kernel on the GPU */
/* Parte 2A: Configurar y llamar los kernels */
/* dim3 dimGrid( ); */
/* dim3 dimBlock( ); */
/* vect_add<<< , >>>( ); */
//invocamos kernel
int threadsPerBlock = 64; // ARRAY_SIZE/NUM_BLOCKS
int blocksPerGrid = 4; // nuevo NUM_BLOCKS
// Para obtener tiempos de ejecucion del kernel
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
vect_add<<< NUM_BLOCKS , THREADS_PER_BLOCK >>> (d_a, d_b, d_c);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add: \t %f \n", milliseconds);
hipEventRecord(start);
vect_add_multiblock<<< blocksPerGrid , threadsPerBlock >>> (d_a, d_b, d_d);
hipEventRecord(stop);
hipEventSynchronize(stop);
milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add_multiblock (4 bloques): \t %f \n", milliseconds);
/* Esperar a que todos los threads acaben y checar por errores */
hipDeviceSynchronize();
checkCUDAError("kernel invocation");
/* Part 1C: copiar el resultado de nuevo al CPU */
hipMemcpy(a, d_a, sz, hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, sz, hipMemcpyDeviceToHost);
hipMemcpy(c, d_c, sz, hipMemcpyDeviceToHost);
hipMemcpy(d, d_d, sz, hipMemcpyDeviceToHost);
checkCUDAError("memcpy");
/* print out the result */
printf("Results: ");
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", c[i]);
}
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", d[i] );
}
printf("\n\n");
/* Parte 1D: Liberar los arreglos */
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipFree(d_d);
free(a);
free(b);
free(c);
free(d);
return 0;
}
/* Utility function to check for and report CUDA errors */
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
*
* Programa de Introducción a los conceptos de CUDA
* Mariana Hernández
* Alan Córdova
*
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/* Declaración de métodos/
/* Utilidad para checar errores de CUDA */
void checkCUDAError(const char*);
/* Kernel para sumar dos vectores en un sólo bloque de hilos */
__global__ void vect_add(int *d_a, int *d_b, int *d_c)
{
/* Part 2B: Implementación del kernel para realizar la suma de los vectores en el GPU */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Versión de múltiples bloques de la suma de vectores */
__global__ void vect_add_multiblock(int *d_a, int *d_b, int *d_c)
{
/* Part 2C: Implementación del kernel pero esta vez permitiendo múltiples bloques de hilos. */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Numero de elementos en el vector */
#define ARRAY_SIZE 256
/*
* Número de bloques e hilos
* Su producto siempre debe ser el tamaño del vector (arreglo).
*/
#define NUM_BLOCKS 1
#define THREADS_PER_BLOCK 256
/* Main routine */
int main(int argc, char *argv[])
{
int *a, *b, *c, *d; /* Arreglos del CPU */
int *d_a, *d_b, *d_c, *d_d;/* Arreglos del GPU */
int i;
size_t sz = ARRAY_SIZE * sizeof(int);
/*
* Reservar memoria en el cpu
*/
a = (int *) malloc(sz);
b = (int *) malloc(sz);
c = (int *) malloc(sz);
d = (int *) malloc(sz);
/*
* Parte 1A:Reservar memoria en el GPU
*/
hipMalloc(&d_a, sz);
hipMalloc(&d_b, sz);
hipMalloc(&d_c, sz);
hipMalloc(&d_d, sz);
/* inicialización */
for (i = 0; i < ARRAY_SIZE; i++) {
a[i] = i;
b[i] = ARRAY_SIZE - i;
c[i] = 0;
d[i] = 0;
}
/* Parte 1B: Copiar los vectores del CPU al GPU */
hipMemcpy(d_a, a, sz, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sz, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, sz, hipMemcpyHostToDevice);
hipMemcpy(d_d, d, sz, hipMemcpyHostToDevice);
/* run the kernel on the GPU */
/* Parte 2A: Configurar y llamar los kernels */
/* dim3 dimGrid( ); */
/* dim3 dimBlock( ); */
/* vect_add<<< , >>>( ); */
//invocamos kernel
int threadsPerBlock = 64; // ARRAY_SIZE/NUM_BLOCKS
int blocksPerGrid = 4; // nuevo NUM_BLOCKS
// Para obtener tiempos de ejecucion del kernel
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
vect_add<<< NUM_BLOCKS , THREADS_PER_BLOCK >>> (d_a, d_b, d_c);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add: \t %f \n", milliseconds);
hipEventRecord(start);
vect_add_multiblock<<< blocksPerGrid , threadsPerBlock >>> (d_a, d_b, d_d);
hipEventRecord(stop);
hipEventSynchronize(stop);
milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add_multiblock (4 bloques): \t %f \n", milliseconds);
/* Esperar a que todos los threads acaben y checar por errores */
hipDeviceSynchronize();
checkCUDAError("kernel invocation");
/* Part 1C: copiar el resultado de nuevo al CPU */
hipMemcpy(a, d_a, sz, hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, sz, hipMemcpyDeviceToHost);
hipMemcpy(c, d_c, sz, hipMemcpyDeviceToHost);
hipMemcpy(d, d_d, sz, hipMemcpyDeviceToHost);
checkCUDAError("memcpy");
/* print out the result */
printf("Results: ");
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", c[i]);
}
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", d[i] );
}
printf("\n\n");
/* Parte 1D: Liberar los arreglos */
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipFree(d_d);
free(a);
free(b);
free(c);
free(d);
return 0;
}
/* Utility function to check for and report CUDA errors */
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8vect_addPiS_S_
.globl _Z8vect_addPiS_S_
.p2align 8
.type _Z8vect_addPiS_S_,@function
_Z8vect_addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8vect_addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8vect_addPiS_S_, .Lfunc_end0-_Z8vect_addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19vect_add_multiblockPiS_S_
.globl _Z19vect_add_multiblockPiS_S_
.p2align 8
.type _Z19vect_add_multiblockPiS_S_,@function
_Z19vect_add_multiblockPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19vect_add_multiblockPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19vect_add_multiblockPiS_S_, .Lfunc_end1-_Z19vect_add_multiblockPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8vect_addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8vect_addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19vect_add_multiblockPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19vect_add_multiblockPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
*
* Programa de Introducción a los conceptos de CUDA
* Mariana Hernández
* Alan Córdova
*
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/* Declaración de métodos/
/* Utilidad para checar errores de CUDA */
void checkCUDAError(const char*);
/* Kernel para sumar dos vectores en un sólo bloque de hilos */
__global__ void vect_add(int *d_a, int *d_b, int *d_c)
{
/* Part 2B: Implementación del kernel para realizar la suma de los vectores en el GPU */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Versión de múltiples bloques de la suma de vectores */
__global__ void vect_add_multiblock(int *d_a, int *d_b, int *d_c)
{
/* Part 2C: Implementación del kernel pero esta vez permitiendo múltiples bloques de hilos. */
int i = blockDim.x * blockIdx.x + threadIdx.x;
// if (i < N)
d_c[i] = d_a[i] + d_b[i];
}
/* Numero de elementos en el vector */
#define ARRAY_SIZE 256
/*
* Número de bloques e hilos
* Su producto siempre debe ser el tamaño del vector (arreglo).
*/
#define NUM_BLOCKS 1
#define THREADS_PER_BLOCK 256
/* Main routine */
int main(int argc, char *argv[])
{
int *a, *b, *c, *d; /* Arreglos del CPU */
int *d_a, *d_b, *d_c, *d_d;/* Arreglos del GPU */
int i;
size_t sz = ARRAY_SIZE * sizeof(int);
/*
* Reservar memoria en el cpu
*/
a = (int *) malloc(sz);
b = (int *) malloc(sz);
c = (int *) malloc(sz);
d = (int *) malloc(sz);
/*
* Parte 1A:Reservar memoria en el GPU
*/
hipMalloc(&d_a, sz);
hipMalloc(&d_b, sz);
hipMalloc(&d_c, sz);
hipMalloc(&d_d, sz);
/* inicialización */
for (i = 0; i < ARRAY_SIZE; i++) {
a[i] = i;
b[i] = ARRAY_SIZE - i;
c[i] = 0;
d[i] = 0;
}
/* Parte 1B: Copiar los vectores del CPU al GPU */
hipMemcpy(d_a, a, sz, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sz, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, sz, hipMemcpyHostToDevice);
hipMemcpy(d_d, d, sz, hipMemcpyHostToDevice);
/* run the kernel on the GPU */
/* Parte 2A: Configurar y llamar los kernels */
/* dim3 dimGrid( ); */
/* dim3 dimBlock( ); */
/* vect_add<<< , >>>( ); */
//invocamos kernel
int threadsPerBlock = 64; // ARRAY_SIZE/NUM_BLOCKS
int blocksPerGrid = 4; // nuevo NUM_BLOCKS
// Para obtener tiempos de ejecucion del kernel
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
vect_add<<< NUM_BLOCKS , THREADS_PER_BLOCK >>> (d_a, d_b, d_c);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add: \t %f \n", milliseconds);
hipEventRecord(start);
vect_add_multiblock<<< blocksPerGrid , threadsPerBlock >>> (d_a, d_b, d_d);
hipEventRecord(stop);
hipEventSynchronize(stop);
milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Tiempo de vect_add_multiblock (4 bloques): \t %f \n", milliseconds);
/* Esperar a que todos los threads acaben y checar por errores */
hipDeviceSynchronize();
checkCUDAError("kernel invocation");
/* Part 1C: copiar el resultado de nuevo al CPU */
hipMemcpy(a, d_a, sz, hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, sz, hipMemcpyDeviceToHost);
hipMemcpy(c, d_c, sz, hipMemcpyDeviceToHost);
hipMemcpy(d, d_d, sz, hipMemcpyDeviceToHost);
checkCUDAError("memcpy");
/* print out the result */
printf("Results: ");
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", c[i]);
}
for (i = 0; i < ARRAY_SIZE; i++) {
printf("%d, ", d[i] );
}
printf("\n\n");
/* Parte 1D: Liberar los arreglos */
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipFree(d_d);
free(a);
free(b);
free(c);
free(d);
return 0;
}
/* Utility function to check for and report CUDA errors */
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.file "intro.hip"
.globl _Z23__device_stub__vect_addPiS_S_ # -- Begin function _Z23__device_stub__vect_addPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__vect_addPiS_S_,@function
_Z23__device_stub__vect_addPiS_S_: # @_Z23__device_stub__vect_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8vect_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__vect_addPiS_S_, .Lfunc_end0-_Z23__device_stub__vect_addPiS_S_
.cfi_endproc
# -- End function
.globl _Z34__device_stub__vect_add_multiblockPiS_S_ # -- Begin function _Z34__device_stub__vect_add_multiblockPiS_S_
.p2align 4, 0x90
.type _Z34__device_stub__vect_add_multiblockPiS_S_,@function
_Z34__device_stub__vect_add_multiblockPiS_S_: # @_Z34__device_stub__vect_add_multiblockPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19vect_add_multiblockPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__vect_add_multiblockPiS_S_, .Lfunc_end1-_Z34__device_stub__vect_add_multiblockPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r15
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 48(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 40(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
xorl %r13d, %r13d
movl $1024, %edx # imm = 0x400
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1024, %edx # imm = 0x400
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
movl $256, %eax # imm = 0x100
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %r13d, (%rbx,%r13,4)
movl %eax, (%r14,%r13,4)
incq %r13
decq %rax
jne .LBB2_1
# %bb.2:
movabsq $4294967297, %r13 # imm = 0x100000001
movq 24(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 255(%r13), %rdx
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8vect_addPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 3(%r13), %rdi
addq $63, %r13
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z19vect_add_multiblockPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_7
# %bb.9: # %_Z14checkCUDAErrorPKc.exit
movq 24(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z14checkCUDAErrorPKc.exit63
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_12: # =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $256, %r13 # imm = 0x100
jne .LBB2_12
# %bb.13: # %.preheader.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $256, %r13 # imm = 0x100
jne .LBB2_14
# %bb.15:
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
jmp .LBB2_8
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %edx
.LBB2_8:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB3_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z14checkCUDAErrorPKc, .Lfunc_end3-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8vect_addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19vect_add_multiblockPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8vect_addPiS_S_,@object # @_Z8vect_addPiS_S_
.section .rodata,"a",@progbits
.globl _Z8vect_addPiS_S_
.p2align 3, 0x0
_Z8vect_addPiS_S_:
.quad _Z23__device_stub__vect_addPiS_S_
.size _Z8vect_addPiS_S_, 8
.type _Z19vect_add_multiblockPiS_S_,@object # @_Z19vect_add_multiblockPiS_S_
.globl _Z19vect_add_multiblockPiS_S_
.p2align 3, 0x0
_Z19vect_add_multiblockPiS_S_:
.quad _Z34__device_stub__vect_add_multiblockPiS_S_
.size _Z19vect_add_multiblockPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tiempo de vect_add: \t %f \n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Tiempo de vect_add_multiblock (4 bloques): \t %f \n"
.size .L.str.1, 50
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel invocation"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "memcpy"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Results: "
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d, "
.size .L.str.5, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.7, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8vect_addPiS_S_"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19vect_add_multiblockPiS_S_"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__vect_addPiS_S_
.addrsig_sym _Z34__device_stub__vect_add_multiblockPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8vect_addPiS_S_
.addrsig_sym _Z19vect_add_multiblockPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19vect_add_multiblockPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8vect_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8vect_addPiS_S_
.globl _Z8vect_addPiS_S_
.p2align 8
.type _Z8vect_addPiS_S_,@function
_Z8vect_addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8vect_addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8vect_addPiS_S_, .Lfunc_end0-_Z8vect_addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19vect_add_multiblockPiS_S_
.globl _Z19vect_add_multiblockPiS_S_
.p2align 8
.type _Z19vect_add_multiblockPiS_S_,@function
_Z19vect_add_multiblockPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19vect_add_multiblockPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19vect_add_multiblockPiS_S_, .Lfunc_end1-_Z19vect_add_multiblockPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8vect_addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8vect_addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19vect_add_multiblockPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19vect_add_multiblockPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00003ac1_00000000-6_intro.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
.type _Z31__device_stub__Z8vect_addPiS_S_PiS_S_, @function
_Z31__device_stub__Z8vect_addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8vect_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z8vect_addPiS_S_PiS_S_, .-_Z31__device_stub__Z8vect_addPiS_S_PiS_S_
.globl _Z8vect_addPiS_S_
.type _Z8vect_addPiS_S_, @function
_Z8vect_addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8vect_addPiS_S_, .-_Z8vect_addPiS_S_
.globl _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_
.type _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_, @function
_Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19vect_add_multiblockPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_, .-_Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_
.globl _Z19vect_add_multiblockPiS_S_
.type _Z19vect_add_multiblockPiS_S_, @function
_Z19vect_add_multiblockPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19vect_add_multiblockPiS_S_, .-_Z19vect_add_multiblockPiS_S_
.section .rodata.str1.1
.LC2:
.string "Tiempo de vect_add: \t %f \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Tiempo de vect_add_multiblock (4 bloques): \t %f \n"
.section .rodata.str1.1
.LC4:
.string "kernel invocation"
.LC5:
.string "memcpy"
.LC6:
.string "Results: "
.LC7:
.string "%d, "
.LC8:
.string "\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1024, %edi
call malloc@PLT
movq %rax, %r14
movl $1024, %edi
call malloc@PLT
movq %rax, %r13
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $1024, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $0, %eax
movl $256, %ecx
.L24:
movl %eax, (%r14,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, 0(%r13,%rax,4)
movl $0, 0(%rbp,%rax,4)
movl $0, (%r12,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L24
movl $1, %ecx
movl $1024, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L25:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $64, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L26:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaThreadSynchronize@PLT
leaq .LC4(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rdi
call _Z14checkCUDAErrorPKc
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 1024(%rbp), %r15
.L27:
movl (%rbx), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L27
movq %r12, %rbx
leaq 1024(%r12), %r15
.L28:
movl (%rbx), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L28
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
jmp .L25
.L35:
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z19vect_add_multiblockPiS_S_PiS_S_
jmp .L26
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z19vect_add_multiblockPiS_S_"
.LC10:
.string "_Z8vect_addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z19vect_add_multiblockPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vect_addPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "intro.hip"
.globl _Z23__device_stub__vect_addPiS_S_ # -- Begin function _Z23__device_stub__vect_addPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__vect_addPiS_S_,@function
_Z23__device_stub__vect_addPiS_S_: # @_Z23__device_stub__vect_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8vect_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__vect_addPiS_S_, .Lfunc_end0-_Z23__device_stub__vect_addPiS_S_
.cfi_endproc
# -- End function
.globl _Z34__device_stub__vect_add_multiblockPiS_S_ # -- Begin function _Z34__device_stub__vect_add_multiblockPiS_S_
.p2align 4, 0x90
.type _Z34__device_stub__vect_add_multiblockPiS_S_,@function
_Z34__device_stub__vect_add_multiblockPiS_S_: # @_Z34__device_stub__vect_add_multiblockPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19vect_add_multiblockPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__vect_add_multiblockPiS_S_, .Lfunc_end1-_Z34__device_stub__vect_add_multiblockPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r15
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 48(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 40(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
xorl %r13d, %r13d
movl $1024, %edx # imm = 0x400
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1024, %edx # imm = 0x400
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
movl $256, %eax # imm = 0x100
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %r13d, (%rbx,%r13,4)
movl %eax, (%r14,%r13,4)
incq %r13
decq %rax
jne .LBB2_1
# %bb.2:
movabsq $4294967297, %r13 # imm = 0x100000001
movq 24(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 255(%r13), %rdx
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8vect_addPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 3(%r13), %rdi
addq $63, %r13
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z19vect_add_multiblockPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_7
# %bb.9: # %_Z14checkCUDAErrorPKc.exit
movq 24(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z14checkCUDAErrorPKc.exit63
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_12: # =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $256, %r13 # imm = 0x100
jne .LBB2_12
# %bb.13: # %.preheader.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $256, %r13 # imm = 0x100
jne .LBB2_14
# %bb.15:
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %edx
jmp .LBB2_8
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.3, %edx
.LBB2_8:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB3_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z14checkCUDAErrorPKc, .Lfunc_end3-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8vect_addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19vect_add_multiblockPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8vect_addPiS_S_,@object # @_Z8vect_addPiS_S_
.section .rodata,"a",@progbits
.globl _Z8vect_addPiS_S_
.p2align 3, 0x0
_Z8vect_addPiS_S_:
.quad _Z23__device_stub__vect_addPiS_S_
.size _Z8vect_addPiS_S_, 8
.type _Z19vect_add_multiblockPiS_S_,@object # @_Z19vect_add_multiblockPiS_S_
.globl _Z19vect_add_multiblockPiS_S_
.p2align 3, 0x0
_Z19vect_add_multiblockPiS_S_:
.quad _Z34__device_stub__vect_add_multiblockPiS_S_
.size _Z19vect_add_multiblockPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tiempo de vect_add: \t %f \n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Tiempo de vect_add_multiblock (4 bloques): \t %f \n"
.size .L.str.1, 50
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel invocation"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "memcpy"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Results: "
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d, "
.size .L.str.5, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.7, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8vect_addPiS_S_"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19vect_add_multiblockPiS_S_"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__vect_addPiS_S_
.addrsig_sym _Z34__device_stub__vect_add_multiblockPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8vect_addPiS_S_
.addrsig_sym _Z19vect_add_multiblockPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*********************************************************
* Name : kernelInteractions.cu
* Author : Kevin Mooney
* Created : 12/08/16
* Updated :
*
* Description:
*
* Notes:
*********************************************************/
#include "cudaErrors.cuh"
void transfer2Host (float * begin, float * end, float * begin2 ) {
size_t sizeOfTransfer = sizeof(float)*std::distance(begin,end);
gpuErrchk ( cudaMemcpy ( begin2, begin, sizeOfTransfer, cudaMemcpyDeviceToHost ) );
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*********************************************************
* Name : kernelInteractions.cu
* Author : Kevin Mooney
* Created : 12/08/16
* Updated :
*
* Description:
*
* Notes:
*********************************************************/
#include "cudaErrors.cuh"
void transfer2Host (float * begin, float * end, float * begin2 ) {
size_t sizeOfTransfer = sizeof(float)*std::distance(begin,end);
gpuErrchk ( cudaMemcpy ( begin2, begin, sizeOfTransfer, cudaMemcpyDeviceToHost ) );
} | .file "tmpxft_000e3616_00000000-6_kernelInteractions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3731:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3731:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3754:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3754:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z9gpuAssert9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.section .text._Z9gpuAssert9cudaErrorPKci,"axG",@progbits,_Z9gpuAssert9cudaErrorPKci,comdat
.weak _Z9gpuAssert9cudaErrorPKci
.type _Z9gpuAssert9cudaErrorPKci, @function
_Z9gpuAssert9cudaErrorPKci:
.LFB3727:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3727
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $424, %rsp
.cfi_def_cfa_offset 480
movq %fs:40, %rax
movq %rax, 408(%rsp)
xorl %eax, %eax
testl %edi, %edi
jne .L29
movq 408(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $424, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %r12
movl %edx, %ebp
leaq 32(%rsp), %r13
leaq 144(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 144(%rsp)
movq $0, 360(%rsp)
movb $0, 368(%rsp)
movb $0, 369(%rsp)
movq $0, 376(%rsp)
movq $0, 384(%rsp)
movq $0, 392(%rsp)
movq $0, 400(%rsp)
movq 8+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r14
movq %r14, 32(%rsp)
movq 16+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r15
movq -24(%r14), %rax
movq %r15, 32(%rsp,%rax)
movq 32(%rsp), %rax
movq %r13, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 144(%rsp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 40(%rsp)
movl $16, 104(%rsp)
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
movq $0, 120(%rsp)
movb $0, 128(%rsp)
leaq 40(%rsp), %rsi
leaq 144(%rsp), %rdi
.LEHB1:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE1:
jmp .L31
.L26:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 40(%rsp)
movq 112(%rsp), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
je .L9
movq 128(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L9:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r14, 32(%rsp)
movq -24(%r14), %rax
movq %r15, 32(%rsp,%rax)
.L10:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 144(%rsp)
leaq 144(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 408(%rsp), %rax
subq %fs:40, %rax
je .L11
call __stack_chk_fail@PLT
.L25:
endbr64
movq %rax, %rbx
jmp .L10
.L11:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L31:
movl %ebx, %edi
.LEHB3:
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L32
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L13
.L32:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.L13:
leaq 32(%rsp), %rdi
movl $1, %edx
leaq .LC0(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testq %r12, %r12
je .L33
movq %r12, %rdi
call strlen@PLT
movq %rax, %rdx
leaq 32(%rsp), %rdi
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L15
.L33:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.L15:
leaq 32(%rsp), %rdi
movl $1, %edx
leaq .LC0(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 32(%rsp), %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
.LEHE3:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rbp
movq %rsp, %rdi
leaq 40(%rsp), %rsi
.LEHB4:
call _ZNKSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@PLT
.LEHE4:
movq %rsp, %rsi
movq %rbp, %rdi
.LEHB5:
call _ZNSt11logic_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE5:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 408(%rsp), %rax
subq %fs:40, %rax
je .L16
call __stack_chk_fail@PLT
.L16:
movq _ZNSt11logic_errorD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt11logic_error(%rip), %rsi
movq %rbp, %rdi
.LEHB6:
call __cxa_throw@PLT
.LEHE6:
.L22:
endbr64
movq %rax, %rbx
jmp .L19
.L24:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L18:
movq %rbp, %rdi
call __cxa_free_exception@PLT
.L19:
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
movq 408(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L23:
endbr64
movq %rax, %rbx
jmp .L18
.L20:
movq %rbx, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.globl __gxx_personality_v0
.section .gcc_except_table._Z9gpuAssert9cudaErrorPKci,"aG",@progbits,_Z9gpuAssert9cudaErrorPKci,comdat
.LLSDA3727:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3727-.LLSDACSB3727
.LLSDACSB3727:
.uleb128 .LEHB0-.LFB3727
.uleb128 .LEHE0-.LEHB0
.uleb128 .L25-.LFB3727
.uleb128 0
.uleb128 .LEHB1-.LFB3727
.uleb128 .LEHE1-.LEHB1
.uleb128 .L26-.LFB3727
.uleb128 0
.uleb128 .LEHB2-.LFB3727
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3727
.uleb128 .LEHE3-.LEHB3
.uleb128 .L22-.LFB3727
.uleb128 0
.uleb128 .LEHB4-.LFB3727
.uleb128 .LEHE4-.LEHB4
.uleb128 .L23-.LFB3727
.uleb128 0
.uleb128 .LEHB5-.LFB3727
.uleb128 .LEHE5-.LEHB5
.uleb128 .L24-.LFB3727
.uleb128 0
.uleb128 .LEHB6-.LFB3727
.uleb128 .LEHE6-.LEHB6
.uleb128 .L22-.LFB3727
.uleb128 0
.uleb128 .LEHB7-.LFB3727
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE3727:
.section .text._Z9gpuAssert9cudaErrorPKci,"axG",@progbits,_Z9gpuAssert9cudaErrorPKci,comdat
.size _Z9gpuAssert9cudaErrorPKci, .-_Z9gpuAssert9cudaErrorPKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/knjmooney/cylRad/master/src/kernelInteractions.cu"
.text
.globl _Z13transfer2HostPfS_S_
.type _Z13transfer2HostPfS_S_, @function
_Z13transfer2HostPfS_S_:
.LFB3728:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rdx, %rdi
movq %rsi, %rdx
subq %rax, %rdx
movl $2, %ecx
movq %rax, %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $16, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3728:
.size _Z13transfer2HostPfS_S_, .-_Z13transfer2HostPfS_S_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*********************************************************
* Name : kernelInteractions.cu
* Author : Kevin Mooney
* Created : 12/08/16
* Updated :
*
* Description:
*
* Notes:
*********************************************************/
#include "cudaErrors.cuh"
void transfer2Host (float * begin, float * end, float * begin2 ) {
size_t sizeOfTransfer = sizeof(float)*std::distance(begin,end);
gpuErrchk ( cudaMemcpy ( begin2, begin, sizeOfTransfer, cudaMemcpyDeviceToHost ) );
} | #include <hip/hip_runtime.h>
/*********************************************************
* Name : kernelInteractions.cuh
* Author : Kevin Mooney
* Created : 22/03/16
* Updated : 11/08/16
*
* Description:
*
* Notes:
*********************************************************/
void transfer2Host (float * begin, float * end, float * begin2 ); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*********************************************************
* Name : kernelInteractions.cuh
* Author : Kevin Mooney
* Created : 22/03/16
* Updated : 11/08/16
*
* Description:
*
* Notes:
*********************************************************/
void transfer2Host (float * begin, float * end, float * begin2 ); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*********************************************************
* Name : kernelInteractions.cuh
* Author : Kevin Mooney
* Created : 22/03/16
* Updated : 11/08/16
*
* Description:
*
* Notes:
*********************************************************/
void transfer2Host (float * begin, float * end, float * begin2 ); | .text
.file "kernelInteractions.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e3616_00000000-6_kernelInteractions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3731:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3731:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3754:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3754:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z9gpuAssert9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.section .text._Z9gpuAssert9cudaErrorPKci,"axG",@progbits,_Z9gpuAssert9cudaErrorPKci,comdat
.weak _Z9gpuAssert9cudaErrorPKci
.type _Z9gpuAssert9cudaErrorPKci, @function
_Z9gpuAssert9cudaErrorPKci:
.LFB3727:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3727
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $424, %rsp
.cfi_def_cfa_offset 480
movq %fs:40, %rax
movq %rax, 408(%rsp)
xorl %eax, %eax
testl %edi, %edi
jne .L29
movq 408(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $424, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %r12
movl %edx, %ebp
leaq 32(%rsp), %r13
leaq 144(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 144(%rsp)
movq $0, 360(%rsp)
movb $0, 368(%rsp)
movb $0, 369(%rsp)
movq $0, 376(%rsp)
movq $0, 384(%rsp)
movq $0, 392(%rsp)
movq $0, 400(%rsp)
movq 8+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r14
movq %r14, 32(%rsp)
movq 16+_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r15
movq -24(%r14), %rax
movq %r15, 32(%rsp,%rax)
movq 32(%rsp), %rax
movq %r13, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 144(%rsp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 40(%rsp)
movl $16, 104(%rsp)
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
movq $0, 120(%rsp)
movb $0, 128(%rsp)
leaq 40(%rsp), %rsi
leaq 144(%rsp), %rdi
.LEHB1:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE1:
jmp .L31
.L26:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 40(%rsp)
movq 112(%rsp), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
je .L9
movq 128(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L9:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r14, 32(%rsp)
movq -24(%r14), %rax
movq %r15, 32(%rsp,%rax)
.L10:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 144(%rsp)
leaq 144(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 408(%rsp), %rax
subq %fs:40, %rax
je .L11
call __stack_chk_fail@PLT
.L25:
endbr64
movq %rax, %rbx
jmp .L10
.L11:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L31:
movl %ebx, %edi
.LEHB3:
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L32
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L13
.L32:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.L13:
leaq 32(%rsp), %rdi
movl $1, %edx
leaq .LC0(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testq %r12, %r12
je .L33
movq %r12, %rdi
call strlen@PLT
movq %rax, %rdx
leaq 32(%rsp), %rdi
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L15
.L33:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.L15:
leaq 32(%rsp), %rdi
movl $1, %edx
leaq .LC0(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 32(%rsp), %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
.LEHE3:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rbp
movq %rsp, %rdi
leaq 40(%rsp), %rsi
.LEHB4:
call _ZNKSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@PLT
.LEHE4:
movq %rsp, %rsi
movq %rbp, %rdi
.LEHB5:
call _ZNSt11logic_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE5:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 408(%rsp), %rax
subq %fs:40, %rax
je .L16
call __stack_chk_fail@PLT
.L16:
movq _ZNSt11logic_errorD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt11logic_error(%rip), %rsi
movq %rbp, %rdi
.LEHB6:
call __cxa_throw@PLT
.LEHE6:
.L22:
endbr64
movq %rax, %rbx
jmp .L19
.L24:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L18:
movq %rbp, %rdi
call __cxa_free_exception@PLT
.L19:
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
movq 408(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L23:
endbr64
movq %rax, %rbx
jmp .L18
.L20:
movq %rbx, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.globl __gxx_personality_v0
.section .gcc_except_table._Z9gpuAssert9cudaErrorPKci,"aG",@progbits,_Z9gpuAssert9cudaErrorPKci,comdat
.LLSDA3727:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3727-.LLSDACSB3727
.LLSDACSB3727:
.uleb128 .LEHB0-.LFB3727
.uleb128 .LEHE0-.LEHB0
.uleb128 .L25-.LFB3727
.uleb128 0
.uleb128 .LEHB1-.LFB3727
.uleb128 .LEHE1-.LEHB1
.uleb128 .L26-.LFB3727
.uleb128 0
.uleb128 .LEHB2-.LFB3727
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3727
.uleb128 .LEHE3-.LEHB3
.uleb128 .L22-.LFB3727
.uleb128 0
.uleb128 .LEHB4-.LFB3727
.uleb128 .LEHE4-.LEHB4
.uleb128 .L23-.LFB3727
.uleb128 0
.uleb128 .LEHB5-.LFB3727
.uleb128 .LEHE5-.LEHB5
.uleb128 .L24-.LFB3727
.uleb128 0
.uleb128 .LEHB6-.LFB3727
.uleb128 .LEHE6-.LEHB6
.uleb128 .L22-.LFB3727
.uleb128 0
.uleb128 .LEHB7-.LFB3727
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE3727:
.section .text._Z9gpuAssert9cudaErrorPKci,"axG",@progbits,_Z9gpuAssert9cudaErrorPKci,comdat
.size _Z9gpuAssert9cudaErrorPKci, .-_Z9gpuAssert9cudaErrorPKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/knjmooney/cylRad/master/src/kernelInteractions.cu"
.text
.globl _Z13transfer2HostPfS_S_
.type _Z13transfer2HostPfS_S_, @function
_Z13transfer2HostPfS_S_:
.LFB3728:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rdx, %rdi
movq %rsi, %rdx
subq %rax, %rdx
movl $2, %ecx
movq %rax, %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $16, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3728:
.size _Z13transfer2HostPfS_S_, .-_Z13transfer2HostPfS_S_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelInteractions.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <cuda_runtime.h>
#include <iostream>
#include <chrono> // measure times
using namespace std;
using namespace std::chrono;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {
return a*a;
}
__global__ void square_global(float *d_a, int n) {
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) d_a[ind] = square(d_a[ind]);
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// timing
high_resolution_clock::time_point t1 = high_resolution_clock::now();
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
//timing
high_resolution_clock::time_point t2 = high_resolution_clock::now();
auto duration = duration_cast<microseconds>( t2 - t1 ).count();
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "CPU time: "<< duration << "ms" << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
// timing START
high_resolution_clock::time_point t3 = high_resolution_clock::now();
// allocate the GPU memory
size_t nbytes = n*sizeof(float);
float *d_a = NULL;
cudaMalloc(&d_a, nbytes);
cudaMemset(d_a, 0, nbytes);
//copy host memory to device
cudaMemcpy( d_a, a, nbytes, cudaMemcpyHostToDevice );
// launch kernel
dim3 block = dim3(32,1,1);
dim3 grid = dim3(1,1,1);
square_global <<<grid,block>>> (d_a, n);
CUDA_CHECK;
// copy device memory to host
cudaMemcpy( a, d_a, nbytes, cudaMemcpyDeviceToHost );
//timing END
high_resolution_clock::time_point t4 = high_resolution_clock::now();
auto duration2 = duration_cast<microseconds>( t4 - t3 ).count();
// free memory
cudaFree(d_a);
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "GPU time: "<< duration2 << "ms" << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | code for sm_80
Function : _Z13square_globalPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <cuda_runtime.h>
#include <iostream>
#include <chrono> // measure times
using namespace std;
using namespace std::chrono;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {
return a*a;
}
__global__ void square_global(float *d_a, int n) {
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) d_a[ind] = square(d_a[ind]);
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// timing
high_resolution_clock::time_point t1 = high_resolution_clock::now();
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
//timing
high_resolution_clock::time_point t2 = high_resolution_clock::now();
auto duration = duration_cast<microseconds>( t2 - t1 ).count();
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "CPU time: "<< duration << "ms" << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
// timing START
high_resolution_clock::time_point t3 = high_resolution_clock::now();
// allocate the GPU memory
size_t nbytes = n*sizeof(float);
float *d_a = NULL;
cudaMalloc(&d_a, nbytes);
cudaMemset(d_a, 0, nbytes);
//copy host memory to device
cudaMemcpy( d_a, a, nbytes, cudaMemcpyHostToDevice );
// launch kernel
dim3 block = dim3(32,1,1);
dim3 grid = dim3(1,1,1);
square_global <<<grid,block>>> (d_a, n);
CUDA_CHECK;
// copy device memory to host
cudaMemcpy( a, d_a, nbytes, cudaMemcpyDeviceToHost );
//timing END
high_resolution_clock::time_point t4 = high_resolution_clock::now();
auto duration2 = duration_cast<microseconds>( t4 - t3 ).count();
// free memory
cudaFree(d_a);
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "GPU time: "<< duration2 << "ms" << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | .file "tmpxft_00169273_00000000-6_squareArray.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line "
.LC1:
.string ": "
.LC2:
.string " ("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3768:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3768:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z6squaref
.type _Z6squaref, @function
_Z6squaref:
.LFB3769:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3769:
.size _Z6squaref, .-_Z6squaref
.globl _Z34__device_stub__Z13square_globalPfiPfi
.type _Z34__device_stub__Z13square_globalPfiPfi, @function
_Z34__device_stub__Z13square_globalPfiPfi:
.LFB3797:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13square_globalPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z34__device_stub__Z13square_globalPfiPfi, .-_Z34__device_stub__Z13square_globalPfiPfi
.globl _Z13square_globalPfi
.type _Z13square_globalPfi, @function
_Z13square_globalPfi:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13square_globalPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z13square_globalPfi, .-_Z13square_globalPfi
.section .rodata.str1.1
.LC4:
.string "CPU:"
.LC5:
.string "CPU time: "
.LC6:
.string "ms"
.LC7:
.string "GPU:"
.LC8:
.string "GPU time: "
.text
.globl main
.type main, @function
main:
.LFB3770:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3770
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $40, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %r13
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L18
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movq %r13, %rax
leaq 40(%r13), %rdx
.L19:
movss (%rax), %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, 8(%rsp)
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L24
.L45:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L43:
call __stack_chk_fail@PLT
.L22:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L23:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $10, %rbp
je .L44
.L24:
movl %ebp, %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbp,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L45
cmpb $0, 56(%r12)
je .L22
movzbl 67(%r12), %esi
jmp .L23
.L44:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
.L25:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L25
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $40, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movl $40, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L26:
leaq 64(%rsp), %rbp
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movq $94, 32(%rsp)
leaq 32(%rsp), %rsi
movl $0, %edx
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE0:
movq %rax, 64(%rsp)
movq 32(%rsp), %rdx
movq %rdx, 80(%rsp)
movabsq $7094628900666304559, %rsi
movabsq $8386058951765290613, %rdi
movq %rsi, (%rax)
movq %rdi, 8(%rax)
movabsq $8391102703641916257, %rsi
movabsq $8247268711403840353, %rdi
movq %rsi, 16(%rax)
movq %rdi, 24(%rax)
movabsq $8462954687814855009, %rsi
movabsq $7435271896686752867, %rdi
movq %rsi, 32(%rax)
movq %rdi, 40(%rax)
movabsq $7017296931985125985, %rsi
movabsq $8320223708492161839, %rdi
movq %rsi, 48(%rax)
movq %rdi, 56(%rax)
movabsq $7310594957409989937, %rsi
movabsq $3414688886752948082, %rdi
movq %rsi, 64(%rax)
movq %rdi, 72(%rax)
movabsq $7310012302218178403, %rsi
movabsq $8458655623992734273, %rdi
movq %rsi, 78(%rax)
movq %rdi, 86(%rax)
movq %rdx, 72(%rsp)
movq 64(%rsp), %rax
movb $0, (%rax,%rdx)
movl $100, %esi
movq %rbp, %rdi
.LEHB1:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE1:
jmp .L47
.L46:
movl $10, %esi
movq 24(%rsp), %rdi
.LEHB2:
call _Z34__device_stub__Z13square_globalPfiPfi
jmp .L26
.L47:
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, 8(%rsp)
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L31
.L50:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L29:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $10, %rbp
je .L49
.L31:
movl %ebp, %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbp,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L50
cmpb $0, 56(%r12)
je .L29
movzbl 67(%r12), %esi
jmp .L30
.L49:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L33
call __stack_chk_fail@PLT
.L33:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE2:
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3770:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3770-.LLSDACSB3770
.LLSDACSB3770:
.uleb128 .LEHB0-.LFB3770
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3770
.uleb128 .LEHE1-.LEHB1
.uleb128 .L35-.LFB3770
.uleb128 0
.uleb128 .LEHB2-.LFB3770
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3770:
.text
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z13square_globalPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13square_globalPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <cuda_runtime.h>
#include <iostream>
#include <chrono> // measure times
using namespace std;
using namespace std::chrono;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {
return a*a;
}
__global__ void square_global(float *d_a, int n) {
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) d_a[ind] = square(d_a[ind]);
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// timing
high_resolution_clock::time_point t1 = high_resolution_clock::now();
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
//timing
high_resolution_clock::time_point t2 = high_resolution_clock::now();
auto duration = duration_cast<microseconds>( t2 - t1 ).count();
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "CPU time: "<< duration << "ms" << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
// timing START
high_resolution_clock::time_point t3 = high_resolution_clock::now();
// allocate the GPU memory
size_t nbytes = n*sizeof(float);
float *d_a = NULL;
cudaMalloc(&d_a, nbytes);
cudaMemset(d_a, 0, nbytes);
//copy host memory to device
cudaMemcpy( d_a, a, nbytes, cudaMemcpyHostToDevice );
// launch kernel
dim3 block = dim3(32,1,1);
dim3 grid = dim3(1,1,1);
square_global <<<grid,block>>> (d_a, n);
CUDA_CHECK;
// copy device memory to host
cudaMemcpy( a, d_a, nbytes, cudaMemcpyDeviceToHost );
//timing END
high_resolution_clock::time_point t4 = high_resolution_clock::now();
auto duration2 = duration_cast<microseconds>( t4 - t3 ).count();
// free memory
cudaFree(d_a);
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "GPU time: "<< duration2 << "ms" << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <hip/hip_runtime.h>
#include <iostream>
#include <chrono> // measure times
using namespace std;
using namespace std::chrono;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {
return a*a;
}
__global__ void square_global(float *d_a, int n) {
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) d_a[ind] = square(d_a[ind]);
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// timing
high_resolution_clock::time_point t1 = high_resolution_clock::now();
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
//timing
high_resolution_clock::time_point t2 = high_resolution_clock::now();
auto duration = duration_cast<microseconds>( t2 - t1 ).count();
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "CPU time: "<< duration << "ms" << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
// timing START
high_resolution_clock::time_point t3 = high_resolution_clock::now();
// allocate the GPU memory
size_t nbytes = n*sizeof(float);
float *d_a = NULL;
hipMalloc(&d_a, nbytes);
hipMemset(d_a, 0, nbytes);
//copy host memory to device
hipMemcpy( d_a, a, nbytes, hipMemcpyHostToDevice );
// launch kernel
dim3 block = dim3(32,1,1);
dim3 grid = dim3(1,1,1);
square_global <<<grid,block>>> (d_a, n);
CUDA_CHECK;
// copy device memory to host
hipMemcpy( a, d_a, nbytes, hipMemcpyDeviceToHost );
//timing END
high_resolution_clock::time_point t4 = high_resolution_clock::now();
auto duration2 = duration_cast<microseconds>( t4 - t3 ).count();
// free memory
hipFree(d_a);
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "GPU time: "<< duration2 << "ms" << endl;
cout << endl;
// free CPU arrays
delete[] a;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <hip/hip_runtime.h>
#include <iostream>
#include <chrono> // measure times
using namespace std;
using namespace std::chrono;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {
return a*a;
}
__global__ void square_global(float *d_a, int n) {
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) d_a[ind] = square(d_a[ind]);
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// timing
high_resolution_clock::time_point t1 = high_resolution_clock::now();
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
//timing
high_resolution_clock::time_point t2 = high_resolution_clock::now();
auto duration = duration_cast<microseconds>( t2 - t1 ).count();
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "CPU time: "<< duration << "ms" << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
// timing START
high_resolution_clock::time_point t3 = high_resolution_clock::now();
// allocate the GPU memory
size_t nbytes = n*sizeof(float);
float *d_a = NULL;
hipMalloc(&d_a, nbytes);
hipMemset(d_a, 0, nbytes);
//copy host memory to device
hipMemcpy( d_a, a, nbytes, hipMemcpyHostToDevice );
// launch kernel
dim3 block = dim3(32,1,1);
dim3 grid = dim3(1,1,1);
square_global <<<grid,block>>> (d_a, n);
CUDA_CHECK;
// copy device memory to host
hipMemcpy( a, d_a, nbytes, hipMemcpyDeviceToHost );
//timing END
high_resolution_clock::time_point t4 = high_resolution_clock::now();
auto duration2 = duration_cast<microseconds>( t4 - t3 ).count();
// free memory
hipFree(d_a);
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "GPU time: "<< duration2 << "ms" << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13square_globalPfi
.globl _Z13square_globalPfi
.p2align 8
.type _Z13square_globalPfi,@function
_Z13square_globalPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13square_globalPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13square_globalPfi, .Lfunc_end0-_Z13square_globalPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13square_globalPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13square_globalPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <hip/hip_runtime.h>
#include <iostream>
#include <chrono> // measure times
using namespace std;
using namespace std::chrono;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {
return a*a;
}
__global__ void square_global(float *d_a, int n) {
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) d_a[ind] = square(d_a[ind]);
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// timing
high_resolution_clock::time_point t1 = high_resolution_clock::now();
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
//timing
high_resolution_clock::time_point t2 = high_resolution_clock::now();
auto duration = duration_cast<microseconds>( t2 - t1 ).count();
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "CPU time: "<< duration << "ms" << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
// timing START
high_resolution_clock::time_point t3 = high_resolution_clock::now();
// allocate the GPU memory
size_t nbytes = n*sizeof(float);
float *d_a = NULL;
hipMalloc(&d_a, nbytes);
hipMemset(d_a, 0, nbytes);
//copy host memory to device
hipMemcpy( d_a, a, nbytes, hipMemcpyHostToDevice );
// launch kernel
dim3 block = dim3(32,1,1);
dim3 grid = dim3(1,1,1);
square_global <<<grid,block>>> (d_a, n);
CUDA_CHECK;
// copy device memory to host
hipMemcpy( a, d_a, nbytes, hipMemcpyDeviceToHost );
//timing END
high_resolution_clock::time_point t4 = high_resolution_clock::now();
auto duration2 = duration_cast<microseconds>( t4 - t3 ).count();
// free memory
hipFree(d_a);
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
// print timing
cout << "GPU time: "<< duration2 << "ms" << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | .text
.file "squareArray.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__square_globalPfi # -- Begin function _Z28__device_stub__square_globalPfi
.p2align 4, 0x90
.type _Z28__device_stub__square_globalPfi,@function
_Z28__device_stub__square_globalPfi: # @_Z28__device_stub__square_globalPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13square_globalPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z28__device_stub__square_globalPfi, .Lfunc_end1-_Z28__device_stub__square_globalPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $40, %edi
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_1
# %bb.2:
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $10, %r15
jne .LBB2_3
# %bb.4:
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %r13 # imm = 0x20C49BA5E353F7CF
imulq %r13
movq %rdx, %r14
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_53
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
movq %r14, %r12
shrq $63, %r12
sarq $7, %r14
cmpb $0, 56(%r15)
je .LBB2_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB2_8
.LBB2_7:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
addq %r12, %r14
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_31: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit82
# in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $10, %r15
je .LBB2_11
.LBB2_9: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_10
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i79
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r12)
je .LBB2_31
# %bb.30: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_32
.LBB2_11:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_54
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i69
cmpb $0, 56(%r15)
je .LBB2_14
# %bb.13:
movzbl 67(%r15), %eax
jmp .LBB2_15
.LBB2_14:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit72
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_55
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i74
cmpb $0, 56(%r14)
je .LBB2_18
# %bb.17:
movzbl 67(%r14), %eax
jmp .LBB2_19
.LBB2_18:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit77
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_20: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_20
# %bb.21:
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq $0, 8(%rsp)
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $40, %edx
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movl $10, 20(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z13square_globalPfi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
leaq 40(%rsp), %r15
movq %r15, 24(%rsp)
.cfi_escape 0x2e, 0x00
movl $106, %edi
callq _Znwm
movq %rax, 24(%rsp)
movq $105, 40(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+89(%rip), %xmm0
movups %xmm0, 89(%rax)
movq $105, 32(%rsp)
movb $0, 105(%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $100, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp1:
# %bb.24:
movq 24(%rsp), %rdi
cmpq %r15, %rdi
je .LBB2_26
# %bb.25: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
imulq %r13
movq %rdx, %r14
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_56
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
movq %r14, %r12
shrq $63, %r12
sarq $7, %r14
cmpb $0, 56(%r15)
je .LBB2_33
# %bb.28:
movzbl 67(%r15), %eax
jmp .LBB2_34
.LBB2_33:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit87
addq %r12, %r14
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
jmp .LBB2_35
.p2align 4, 0x90
.LBB2_51: # in Loop: Header=BB2_35 Depth=1
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_52: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit102
# in Loop: Header=BB2_35 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $10, %r15
je .LBB2_37
.LBB2_35: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_36
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i99
# in Loop: Header=BB2_35 Depth=1
cmpb $0, 56(%r12)
je .LBB2_51
# %bb.50: # in Loop: Header=BB2_35 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_52
.LBB2_37:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_57
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%r15)
je .LBB2_40
# %bb.39:
movzbl 67(%r15), %eax
jmp .LBB2_41
.LBB2_40:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_41: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit92
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_58
# %bb.42: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%r14)
je .LBB2_44
# %bb.43:
movzbl 67(%r14), %eax
jmp .LBB2_45
.LBB2_44:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_45: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit97
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 192
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_36:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_53:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_54:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_55:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_56:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_57:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_58:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_46:
.Ltmp2:
movq %rax, %rbx
movq 24(%rsp), %rdi
cmpq %r15, %rdi
je .LBB2_48
# %bb.47: # %.critedge.i.i65
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_48: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit67
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end2-.Ltmp1 # Call between .Ltmp1 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13square_globalPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z13square_globalPfi,@object # @_Z13square_globalPfi
.section .rodata,"a",@progbits
.globl _Z13square_globalPfi
.p2align 3, 0x0
_Z13square_globalPfi:
.quad _Z28__device_stub__square_globalPfi
.size _Z13square_globalPfi, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "CPU:"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU time: "
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "ms"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/garibarba/cuda_ws15/master/basic/squareArray.hip"
.size .L.str.7, 106
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU:"
.size .L.str.8, 5
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPU time: "
.size .L.str.9, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13square_globalPfi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__square_globalPfi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z13square_globalPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13square_globalPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13square_globalPfi
.globl _Z13square_globalPfi
.p2align 8
.type _Z13square_globalPfi,@function
_Z13square_globalPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13square_globalPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13square_globalPfi, .Lfunc_end0-_Z13square_globalPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13square_globalPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13square_globalPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00169273_00000000-6_squareArray.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line "
.LC1:
.string ": "
.LC2:
.string " ("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3768:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3768:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z6squaref
.type _Z6squaref, @function
_Z6squaref:
.LFB3769:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3769:
.size _Z6squaref, .-_Z6squaref
.globl _Z34__device_stub__Z13square_globalPfiPfi
.type _Z34__device_stub__Z13square_globalPfiPfi, @function
_Z34__device_stub__Z13square_globalPfiPfi:
.LFB3797:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13square_globalPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z34__device_stub__Z13square_globalPfiPfi, .-_Z34__device_stub__Z13square_globalPfiPfi
.globl _Z13square_globalPfi
.type _Z13square_globalPfi, @function
_Z13square_globalPfi:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13square_globalPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z13square_globalPfi, .-_Z13square_globalPfi
.section .rodata.str1.1
.LC4:
.string "CPU:"
.LC5:
.string "CPU time: "
.LC6:
.string "ms"
.LC7:
.string "GPU:"
.LC8:
.string "GPU time: "
.text
.globl main
.type main, @function
main:
.LFB3770:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3770
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $40, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %r13
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L18
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movq %r13, %rax
leaq 40(%r13), %rdx
.L19:
movss (%rax), %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, 8(%rsp)
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L24
.L45:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L43:
call __stack_chk_fail@PLT
.L22:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L23:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $10, %rbp
je .L44
.L24:
movl %ebp, %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbp,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L45
cmpb $0, 56(%r12)
je .L22
movzbl 67(%r12), %esi
jmp .L23
.L44:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
.L25:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L25
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $40, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movl $40, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L26:
leaq 64(%rsp), %rbp
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movq $94, 32(%rsp)
leaq 32(%rsp), %rsi
movl $0, %edx
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE0:
movq %rax, 64(%rsp)
movq 32(%rsp), %rdx
movq %rdx, 80(%rsp)
movabsq $7094628900666304559, %rsi
movabsq $8386058951765290613, %rdi
movq %rsi, (%rax)
movq %rdi, 8(%rax)
movabsq $8391102703641916257, %rsi
movabsq $8247268711403840353, %rdi
movq %rsi, 16(%rax)
movq %rdi, 24(%rax)
movabsq $8462954687814855009, %rsi
movabsq $7435271896686752867, %rdi
movq %rsi, 32(%rax)
movq %rdi, 40(%rax)
movabsq $7017296931985125985, %rsi
movabsq $8320223708492161839, %rdi
movq %rsi, 48(%rax)
movq %rdi, 56(%rax)
movabsq $7310594957409989937, %rsi
movabsq $3414688886752948082, %rdi
movq %rsi, 64(%rax)
movq %rdi, 72(%rax)
movabsq $7310012302218178403, %rsi
movabsq $8458655623992734273, %rdi
movq %rsi, 78(%rax)
movq %rdi, 86(%rax)
movq %rdx, 72(%rsp)
movq 64(%rsp), %rax
movb $0, (%rax,%rdx)
movl $100, %esi
movq %rbp, %rdi
.LEHB1:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE1:
jmp .L47
.L46:
movl $10, %esi
movq 24(%rsp), %rdi
.LEHB2:
call _Z34__device_stub__Z13square_globalPfiPfi
jmp .L26
.L47:
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, 8(%rsp)
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L31
.L50:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L29:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $10, %rbp
je .L49
.L31:
movl %ebp, %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbp,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L50
cmpb $0, 56(%r12)
je .L29
movzbl 67(%r12), %esi
jmp .L30
.L49:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L33
call __stack_chk_fail@PLT
.L33:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE2:
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3770:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3770-.LLSDACSB3770
.LLSDACSB3770:
.uleb128 .LEHB0-.LFB3770
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3770
.uleb128 .LEHE1-.LEHB1
.uleb128 .L35-.LFB3770
.uleb128 0
.uleb128 .LEHB2-.LFB3770
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3770:
.text
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z13square_globalPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13square_globalPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "squareArray.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__square_globalPfi # -- Begin function _Z28__device_stub__square_globalPfi
.p2align 4, 0x90
.type _Z28__device_stub__square_globalPfi,@function
_Z28__device_stub__square_globalPfi: # @_Z28__device_stub__square_globalPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13square_globalPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z28__device_stub__square_globalPfi, .Lfunc_end1-_Z28__device_stub__square_globalPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $40, %edi
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_1
# %bb.2:
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $10, %r15
jne .LBB2_3
# %bb.4:
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %r13 # imm = 0x20C49BA5E353F7CF
imulq %r13
movq %rdx, %r14
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_53
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
movq %r14, %r12
shrq $63, %r12
sarq $7, %r14
cmpb $0, 56(%r15)
je .LBB2_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB2_8
.LBB2_7:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
addq %r12, %r14
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_31: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit82
# in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $10, %r15
je .LBB2_11
.LBB2_9: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_10
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i79
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r12)
je .LBB2_31
# %bb.30: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_32
.LBB2_11:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_54
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i69
cmpb $0, 56(%r15)
je .LBB2_14
# %bb.13:
movzbl 67(%r15), %eax
jmp .LBB2_15
.LBB2_14:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit72
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_55
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i74
cmpb $0, 56(%r14)
je .LBB2_18
# %bb.17:
movzbl 67(%r14), %eax
jmp .LBB2_19
.LBB2_18:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit77
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_20: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_20
# %bb.21:
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq $0, 8(%rsp)
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $40, %edx
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movl $10, 20(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z13square_globalPfi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
leaq 40(%rsp), %r15
movq %r15, 24(%rsp)
.cfi_escape 0x2e, 0x00
movl $106, %edi
callq _Znwm
movq %rax, 24(%rsp)
movq $105, 40(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.7+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.7+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.7+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.7+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.7+89(%rip), %xmm0
movups %xmm0, 89(%rax)
movq $105, 32(%rsp)
movb $0, 105(%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $100, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp1:
# %bb.24:
movq 24(%rsp), %rdi
cmpq %r15, %rdi
je .LBB2_26
# %bb.25: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
imulq %r13
movq %rdx, %r14
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_56
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
movq %r14, %r12
shrq $63, %r12
sarq $7, %r14
cmpb $0, 56(%r15)
je .LBB2_33
# %bb.28:
movzbl 67(%r15), %eax
jmp .LBB2_34
.LBB2_33:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit87
addq %r12, %r14
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
jmp .LBB2_35
.p2align 4, 0x90
.LBB2_51: # in Loop: Header=BB2_35 Depth=1
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_52: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit102
# in Loop: Header=BB2_35 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $10, %r15
je .LBB2_37
.LBB2_35: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_36
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i99
# in Loop: Header=BB2_35 Depth=1
cmpb $0, 56(%r12)
je .LBB2_51
# %bb.50: # in Loop: Header=BB2_35 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_52
.LBB2_37:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_57
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%r15)
je .LBB2_40
# %bb.39:
movzbl 67(%r15), %eax
jmp .LBB2_41
.LBB2_40:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_41: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit92
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_58
# %bb.42: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%r14)
je .LBB2_44
# %bb.43:
movzbl 67(%r14), %eax
jmp .LBB2_45
.LBB2_44:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_45: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit97
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 192
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_36:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_53:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_54:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_55:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_56:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_57:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_58:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_46:
.Ltmp2:
movq %rax, %rbx
movq 24(%rsp), %rdi
cmpq %r15, %rdi
je .LBB2_48
# %bb.47: # %.critedge.i.i65
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_48: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit67
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end2-.Ltmp1 # Call between .Ltmp1 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13square_globalPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z13square_globalPfi,@object # @_Z13square_globalPfi
.section .rodata,"a",@progbits
.globl _Z13square_globalPfi
.p2align 3, 0x0
_Z13square_globalPfi:
.quad _Z28__device_stub__square_globalPfi
.size _Z13square_globalPfi, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "CPU:"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU time: "
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "ms"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/garibarba/cuda_ws15/master/basic/squareArray.hip"
.size .L.str.7, 106
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU:"
.size .L.str.8, 5
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPU time: "
.size .L.str.9, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13square_globalPfi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__square_globalPfi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z13square_globalPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void scatterKernel( const unsigned int *d_In, const unsigned int *d_FalseKeyAddresses, unsigned int *d_Out, const unsigned int totalFalses, size_t size, unsigned int bitPos)
{
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + (blockIdx.y * gridDim.x);
int threadId = threadIdx.x + (threadIdx.y * blockDim.x);
int myId = (blockId * threadsPerBlock) + threadId;
if (myId < size)
{
unsigned int _myFalseKeyAddress =
d_FalseKeyAddresses[myId];
// Calculate true sort key address
int _trueSortKeyAddress =
myId - _myFalseKeyAddress + totalFalses;
// True sort key?
unsigned int _trueSortKey =
(d_In[myId] >> bitPos) & 0x1;
int _destinationAddress =
_trueSortKey ?
_trueSortKeyAddress :
_myFalseKeyAddress;
d_Out[_destinationAddress] =
d_In[myId];
}
} | code for sm_80
Function : _Z13scatterKernelPKjS0_Pjjmj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*00a0*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x184], PT, P0 ; /* 0x0000610003007a0c */
/* 0x000fda0003f06100 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*00d0*/ SHF.L.U64.HI R3, R0, 0x2, R3 ; /* 0x0000000200037819 */
/* 0x000fe20000010203 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f1e0ff */
/*0100*/ IADD3 R6, P1, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe40007f3e0ff */
/*0110*/ IADD3.X R5, R3.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003057a10 */
/* 0x040fe400007fe4ff */
/*0120*/ IADD3.X R7, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003077a10 */
/* 0x000fc80000ffe4ff */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ee2000c1e1900 */
/*0150*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0170*/ ULDC UR5, c[0x0][0x188] ; /* 0x0000620000057ab9 */
/* 0x000fe40000000800 */
/*0180*/ USHF.L.U32 UR4, UR4, UR5, URZ ; /* 0x0000000504047299 */
/* 0x000fe2000800063f */
/*0190*/ IADD3 R0, -R5, c[0x0][0x178], R0 ; /* 0x00005e0005007a10 */
/* 0x004fca0007ffe100 */
/*01a0*/ LOP3.LUT P0, RZ, R7, UR4, RZ, 0xc0, !PT ; /* 0x0000000407ff7c12 */
/* 0x008fc8000f80c0ff */
/*01b0*/ SEL R0, R5, R0, !P0 ; /* 0x0000000005007207 */
/* 0x000fca0004000000 */
/*01c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*01d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void scatterKernel( const unsigned int *d_In, const unsigned int *d_FalseKeyAddresses, unsigned int *d_Out, const unsigned int totalFalses, size_t size, unsigned int bitPos)
{
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + (blockIdx.y * gridDim.x);
int threadId = threadIdx.x + (threadIdx.y * blockDim.x);
int myId = (blockId * threadsPerBlock) + threadId;
if (myId < size)
{
unsigned int _myFalseKeyAddress =
d_FalseKeyAddresses[myId];
// Calculate true sort key address
int _trueSortKeyAddress =
myId - _myFalseKeyAddress + totalFalses;
// True sort key?
unsigned int _trueSortKey =
(d_In[myId] >> bitPos) & 0x1;
int _destinationAddress =
_trueSortKey ?
_trueSortKeyAddress :
_myFalseKeyAddress;
d_Out[_destinationAddress] =
d_In[myId];
}
} | .file "tmpxft_001144b9_00000000-6_scatterKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj
.type _Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj, @function
_Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 16(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13scatterKernelPKjS0_Pjjmj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj, .-_Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj
.globl _Z13scatterKernelPKjS0_Pjjmj
.type _Z13scatterKernelPKjS0_Pjjmj, @function
_Z13scatterKernelPKjS0_Pjjmj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13scatterKernelPKjS0_Pjjmj, .-_Z13scatterKernelPKjS0_Pjjmj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13scatterKernelPKjS0_Pjjmj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13scatterKernelPKjS0_Pjjmj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void scatterKernel( const unsigned int *d_In, const unsigned int *d_FalseKeyAddresses, unsigned int *d_Out, const unsigned int totalFalses, size_t size, unsigned int bitPos)
{
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + (blockIdx.y * gridDim.x);
int threadId = threadIdx.x + (threadIdx.y * blockDim.x);
int myId = (blockId * threadsPerBlock) + threadId;
if (myId < size)
{
unsigned int _myFalseKeyAddress =
d_FalseKeyAddresses[myId];
// Calculate true sort key address
int _trueSortKeyAddress =
myId - _myFalseKeyAddress + totalFalses;
// True sort key?
unsigned int _trueSortKey =
(d_In[myId] >> bitPos) & 0x1;
int _destinationAddress =
_trueSortKey ?
_trueSortKeyAddress :
_myFalseKeyAddress;
d_Out[_destinationAddress] =
d_In[myId];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scatterKernel( const unsigned int *d_In, const unsigned int *d_FalseKeyAddresses, unsigned int *d_Out, const unsigned int totalFalses, size_t size, unsigned int bitPos)
{
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + (blockIdx.y * gridDim.x);
int threadId = threadIdx.x + (threadIdx.y * blockDim.x);
int myId = (blockId * threadsPerBlock) + threadId;
if (myId < size)
{
unsigned int _myFalseKeyAddress =
d_FalseKeyAddresses[myId];
// Calculate true sort key address
int _trueSortKeyAddress =
myId - _myFalseKeyAddress + totalFalses;
// True sort key?
unsigned int _trueSortKey =
(d_In[myId] >> bitPos) & 0x1;
int _destinationAddress =
_trueSortKey ?
_trueSortKeyAddress :
_myFalseKeyAddress;
d_Out[_destinationAddress] =
d_In[myId];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scatterKernel( const unsigned int *d_In, const unsigned int *d_FalseKeyAddresses, unsigned int *d_Out, const unsigned int totalFalses, size_t size, unsigned int bitPos)
{
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + (blockIdx.y * gridDim.x);
int threadId = threadIdx.x + (threadIdx.y * blockDim.x);
int myId = (blockId * threadsPerBlock) + threadId;
if (myId < size)
{
unsigned int _myFalseKeyAddress =
d_FalseKeyAddresses[myId];
// Calculate true sort key address
int _trueSortKeyAddress =
myId - _myFalseKeyAddress + totalFalses;
// True sort key?
unsigned int _trueSortKey =
(d_In[myId] >> bitPos) & 0x1;
int _destinationAddress =
_trueSortKey ?
_trueSortKeyAddress :
_myFalseKeyAddress;
d_Out[_destinationAddress] =
d_In[myId];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13scatterKernelPKjS0_Pjjmj
.globl _Z13scatterKernelPKjS0_Pjjmj
.p2align 8
.type _Z13scatterKernelPKjS0_Pjjmj,@function
_Z13scatterKernelPKjS0_Pjjmj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s4, s[0:1], 0x3c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_lshr_b32 s3, s4, 16
s_add_i32 s2, s2, s14
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x20
v_and_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_clause 0x1
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, s4, v0
s_waitcnt vmcnt(1)
v_bfe_u32 v2, v3, s0, 1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v1
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13scatterKernelPKjS0_Pjjmj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13scatterKernelPKjS0_Pjjmj, .Lfunc_end0-_Z13scatterKernelPKjS0_Pjjmj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13scatterKernelPKjS0_Pjjmj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13scatterKernelPKjS0_Pjjmj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scatterKernel( const unsigned int *d_In, const unsigned int *d_FalseKeyAddresses, unsigned int *d_Out, const unsigned int totalFalses, size_t size, unsigned int bitPos)
{
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + (blockIdx.y * gridDim.x);
int threadId = threadIdx.x + (threadIdx.y * blockDim.x);
int myId = (blockId * threadsPerBlock) + threadId;
if (myId < size)
{
unsigned int _myFalseKeyAddress =
d_FalseKeyAddresses[myId];
// Calculate true sort key address
int _trueSortKeyAddress =
myId - _myFalseKeyAddress + totalFalses;
// True sort key?
unsigned int _trueSortKey =
(d_In[myId] >> bitPos) & 0x1;
int _destinationAddress =
_trueSortKey ?
_trueSortKeyAddress :
_myFalseKeyAddress;
d_Out[_destinationAddress] =
d_In[myId];
}
} | .text
.file "scatterKernel.hip"
.globl _Z28__device_stub__scatterKernelPKjS0_Pjjmj # -- Begin function _Z28__device_stub__scatterKernelPKjS0_Pjjmj
.p2align 4, 0x90
.type _Z28__device_stub__scatterKernelPKjS0_Pjjmj,@function
_Z28__device_stub__scatterKernelPKjS0_Pjjmj: # @_Z28__device_stub__scatterKernelPKjS0_Pjjmj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13scatterKernelPKjS0_Pjjmj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__scatterKernelPKjS0_Pjjmj, .Lfunc_end0-_Z28__device_stub__scatterKernelPKjS0_Pjjmj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13scatterKernelPKjS0_Pjjmj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13scatterKernelPKjS0_Pjjmj,@object # @_Z13scatterKernelPKjS0_Pjjmj
.section .rodata,"a",@progbits
.globl _Z13scatterKernelPKjS0_Pjjmj
.p2align 3, 0x0
_Z13scatterKernelPKjS0_Pjjmj:
.quad _Z28__device_stub__scatterKernelPKjS0_Pjjmj
.size _Z13scatterKernelPKjS0_Pjjmj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13scatterKernelPKjS0_Pjjmj"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__scatterKernelPKjS0_Pjjmj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13scatterKernelPKjS0_Pjjmj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13scatterKernelPKjS0_Pjjmj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*00a0*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x184], PT, P0 ; /* 0x0000610003007a0c */
/* 0x000fda0003f06100 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*00d0*/ SHF.L.U64.HI R3, R0, 0x2, R3 ; /* 0x0000000200037819 */
/* 0x000fe20000010203 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f1e0ff */
/*0100*/ IADD3 R6, P1, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe40007f3e0ff */
/*0110*/ IADD3.X R5, R3.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003057a10 */
/* 0x040fe400007fe4ff */
/*0120*/ IADD3.X R7, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003077a10 */
/* 0x000fc80000ffe4ff */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ee2000c1e1900 */
/*0150*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0170*/ ULDC UR5, c[0x0][0x188] ; /* 0x0000620000057ab9 */
/* 0x000fe40000000800 */
/*0180*/ USHF.L.U32 UR4, UR4, UR5, URZ ; /* 0x0000000504047299 */
/* 0x000fe2000800063f */
/*0190*/ IADD3 R0, -R5, c[0x0][0x178], R0 ; /* 0x00005e0005007a10 */
/* 0x004fca0007ffe100 */
/*01a0*/ LOP3.LUT P0, RZ, R7, UR4, RZ, 0xc0, !PT ; /* 0x0000000407ff7c12 */
/* 0x008fc8000f80c0ff */
/*01b0*/ SEL R0, R5, R0, !P0 ; /* 0x0000000005007207 */
/* 0x000fca0004000000 */
/*01c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*01d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13scatterKernelPKjS0_Pjjmj
.globl _Z13scatterKernelPKjS0_Pjjmj
.p2align 8
.type _Z13scatterKernelPKjS0_Pjjmj,@function
_Z13scatterKernelPKjS0_Pjjmj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s4, s[0:1], 0x3c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_lshr_b32 s3, s4, 16
s_add_i32 s2, s2, s14
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x20
v_and_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_clause 0x1
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, s4, v0
s_waitcnt vmcnt(1)
v_bfe_u32 v2, v3, s0, 1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v1
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13scatterKernelPKjS0_Pjjmj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13scatterKernelPKjS0_Pjjmj, .Lfunc_end0-_Z13scatterKernelPKjS0_Pjjmj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13scatterKernelPKjS0_Pjjmj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13scatterKernelPKjS0_Pjjmj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001144b9_00000000-6_scatterKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj
.type _Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj, @function
_Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 16(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13scatterKernelPKjS0_Pjjmj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj, .-_Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj
.globl _Z13scatterKernelPKjS0_Pjjmj
.type _Z13scatterKernelPKjS0_Pjjmj, @function
_Z13scatterKernelPKjS0_Pjjmj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z13scatterKernelPKjS0_PjjmjPKjS0_Pjjmj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13scatterKernelPKjS0_Pjjmj, .-_Z13scatterKernelPKjS0_Pjjmj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13scatterKernelPKjS0_Pjjmj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13scatterKernelPKjS0_Pjjmj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scatterKernel.hip"
.globl _Z28__device_stub__scatterKernelPKjS0_Pjjmj # -- Begin function _Z28__device_stub__scatterKernelPKjS0_Pjjmj
.p2align 4, 0x90
.type _Z28__device_stub__scatterKernelPKjS0_Pjjmj,@function
_Z28__device_stub__scatterKernelPKjS0_Pjjmj: # @_Z28__device_stub__scatterKernelPKjS0_Pjjmj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13scatterKernelPKjS0_Pjjmj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__scatterKernelPKjS0_Pjjmj, .Lfunc_end0-_Z28__device_stub__scatterKernelPKjS0_Pjjmj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13scatterKernelPKjS0_Pjjmj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13scatterKernelPKjS0_Pjjmj,@object # @_Z13scatterKernelPKjS0_Pjjmj
.section .rodata,"a",@progbits
.globl _Z13scatterKernelPKjS0_Pjjmj
.p2align 3, 0x0
_Z13scatterKernelPKjS0_Pjjmj:
.quad _Z28__device_stub__scatterKernelPKjS0_Pjjmj
.size _Z13scatterKernelPKjS0_Pjjmj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13scatterKernelPKjS0_Pjjmj"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__scatterKernelPKjS0_Pjjmj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13scatterKernelPKjS0_Pjjmj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add_reference_points_norm(float * array, int width, int pitch, int height, float * norm){
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int xIndex = blockIdx.x * blockDim.x + tx;
unsigned int yIndex = blockIdx.y * blockDim.y + ty;
__shared__ float shared_vec[16];
if (tx==0 && yIndex<height)
shared_vec[ty] = norm[yIndex];
__syncthreads();
if (xIndex<width && yIndex<height)
array[yIndex*pitch+xIndex] += shared_vec[ty];
} | code for sm_80
Function : _Z25add_reference_points_normPfiiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x120 ; /* 0x000000e000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002200 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R4 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0204 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003f06070 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0203 */
/*00a0*/ ISETP.NE.OR P1, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40000725670 */
/*00b0*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fd60000706470 */
/*00c0*/ @P1 BRA 0x110 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*00e0*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x178] ; /* 0x00005e0005027625 */
/* 0x000fcc00078e0002 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0100*/ STS [R4.X4], R2 ; /* 0x0000000204007388 */
/* 0x0041e40000004800 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD R2, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005027a24 */
/* 0x001fc400078e0200 */
/*0160*/ LDS R0, [R4.X4] ; /* 0x0000000004007984 */
/* 0x000e240000004800 */
/*0170*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0180*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000e24000c1e1900 */
/*0190*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x001fca0000000000 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add_reference_points_norm(float * array, int width, int pitch, int height, float * norm){
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int xIndex = blockIdx.x * blockDim.x + tx;
unsigned int yIndex = blockIdx.y * blockDim.y + ty;
__shared__ float shared_vec[16];
if (tx==0 && yIndex<height)
shared_vec[ty] = norm[yIndex];
__syncthreads();
if (xIndex<width && yIndex<height)
array[yIndex*pitch+xIndex] += shared_vec[ty];
} | .file "tmpxft_0013e136_00000000-6_add_reference_points_norm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_
.type _Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_, @function
_Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25add_reference_points_normPfiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_, .-_Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_
.globl _Z25add_reference_points_normPfiiiS_
.type _Z25add_reference_points_normPfiiiS_, @function
_Z25add_reference_points_normPfiiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25add_reference_points_normPfiiiS_, .-_Z25add_reference_points_normPfiiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25add_reference_points_normPfiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25add_reference_points_normPfiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add_reference_points_norm(float * array, int width, int pitch, int height, float * norm){
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int xIndex = blockIdx.x * blockDim.x + tx;
unsigned int yIndex = blockIdx.y * blockDim.y + ty;
__shared__ float shared_vec[16];
if (tx==0 && yIndex<height)
shared_vec[ty] = norm[yIndex];
__syncthreads();
if (xIndex<width && yIndex<height)
array[yIndex*pitch+xIndex] += shared_vec[ty];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add_reference_points_norm(float * array, int width, int pitch, int height, float * norm){
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int xIndex = blockIdx.x * blockDim.x + tx;
unsigned int yIndex = blockIdx.y * blockDim.y + ty;
__shared__ float shared_vec[16];
if (tx==0 && yIndex<height)
shared_vec[ty] = norm[yIndex];
__syncthreads();
if (xIndex<width && yIndex<height)
array[yIndex*pitch+xIndex] += shared_vec[ty];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add_reference_points_norm(float * array, int width, int pitch, int height, float * norm){
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int xIndex = blockIdx.x * blockDim.x + tx;
unsigned int yIndex = blockIdx.y * blockDim.y + ty;
__shared__ float shared_vec[16];
if (tx==0 && yIndex<height)
shared_vec[ty] = norm[yIndex];
__syncthreads();
if (xIndex<width && yIndex<height)
array[yIndex*pitch+xIndex] += shared_vec[ty];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25add_reference_points_normPfiiiS_
.globl _Z25add_reference_points_normPfiiiS_
.p2align 8
.type _Z25add_reference_points_normPfiiiS_,@function
_Z25add_reference_points_normPfiiiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s3, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s2, 0, v0
v_cmp_gt_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x18
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_load_b32 s2, s[0:1], 0x8
s_and_b32 s3, 0xffff, s3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s14, s3, v[0:1]
s_barrier
buffer_gl0_inv
v_cmp_gt_u32_e64 s2, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v1
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v2, s2, v[3:4]
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25add_reference_points_normPfiiiS_
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25add_reference_points_normPfiiiS_, .Lfunc_end0-_Z25add_reference_points_normPfiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25add_reference_points_normPfiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25add_reference_points_normPfiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add_reference_points_norm(float * array, int width, int pitch, int height, float * norm){
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int xIndex = blockIdx.x * blockDim.x + tx;
unsigned int yIndex = blockIdx.y * blockDim.y + ty;
__shared__ float shared_vec[16];
if (tx==0 && yIndex<height)
shared_vec[ty] = norm[yIndex];
__syncthreads();
if (xIndex<width && yIndex<height)
array[yIndex*pitch+xIndex] += shared_vec[ty];
} | .text
.file "add_reference_points_norm.hip"
.globl _Z40__device_stub__add_reference_points_normPfiiiS_ # -- Begin function _Z40__device_stub__add_reference_points_normPfiiiS_
.p2align 4, 0x90
.type _Z40__device_stub__add_reference_points_normPfiiiS_,@function
_Z40__device_stub__add_reference_points_normPfiiiS_: # @_Z40__device_stub__add_reference_points_normPfiiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25add_reference_points_normPfiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__add_reference_points_normPfiiiS_, .Lfunc_end0-_Z40__device_stub__add_reference_points_normPfiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25add_reference_points_normPfiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25add_reference_points_normPfiiiS_,@object # @_Z25add_reference_points_normPfiiiS_
.section .rodata,"a",@progbits
.globl _Z25add_reference_points_normPfiiiS_
.p2align 3, 0x0
_Z25add_reference_points_normPfiiiS_:
.quad _Z40__device_stub__add_reference_points_normPfiiiS_
.size _Z25add_reference_points_normPfiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25add_reference_points_normPfiiiS_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__add_reference_points_normPfiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25add_reference_points_normPfiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25add_reference_points_normPfiiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x120 ; /* 0x000000e000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002200 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R4 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0204 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003f06070 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0203 */
/*00a0*/ ISETP.NE.OR P1, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40000725670 */
/*00b0*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fd60000706470 */
/*00c0*/ @P1 BRA 0x110 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*00e0*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x178] ; /* 0x00005e0005027625 */
/* 0x000fcc00078e0002 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0100*/ STS [R4.X4], R2 ; /* 0x0000000204007388 */
/* 0x0041e40000004800 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD R2, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005027a24 */
/* 0x001fc400078e0200 */
/*0160*/ LDS R0, [R4.X4] ; /* 0x0000000004007984 */
/* 0x000e240000004800 */
/*0170*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0180*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000e24000c1e1900 */
/*0190*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x001fca0000000000 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25add_reference_points_normPfiiiS_
.globl _Z25add_reference_points_normPfiiiS_
.p2align 8
.type _Z25add_reference_points_normPfiiiS_,@function
_Z25add_reference_points_normPfiiiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s3, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s2, 0, v0
v_cmp_gt_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x18
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_load_b32 s2, s[0:1], 0x8
s_and_b32 s3, 0xffff, s3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s14, s3, v[0:1]
s_barrier
buffer_gl0_inv
v_cmp_gt_u32_e64 s2, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v1
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v2, s2, v[3:4]
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25add_reference_points_normPfiiiS_
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25add_reference_points_normPfiiiS_, .Lfunc_end0-_Z25add_reference_points_normPfiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25add_reference_points_normPfiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25add_reference_points_normPfiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013e136_00000000-6_add_reference_points_norm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_
.type _Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_, @function
_Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25add_reference_points_normPfiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_, .-_Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_
.globl _Z25add_reference_points_normPfiiiS_
.type _Z25add_reference_points_normPfiiiS_, @function
_Z25add_reference_points_normPfiiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25add_reference_points_normPfiiiS_PfiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25add_reference_points_normPfiiiS_, .-_Z25add_reference_points_normPfiiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25add_reference_points_normPfiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25add_reference_points_normPfiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_reference_points_norm.hip"
.globl _Z40__device_stub__add_reference_points_normPfiiiS_ # -- Begin function _Z40__device_stub__add_reference_points_normPfiiiS_
.p2align 4, 0x90
.type _Z40__device_stub__add_reference_points_normPfiiiS_,@function
_Z40__device_stub__add_reference_points_normPfiiiS_: # @_Z40__device_stub__add_reference_points_normPfiiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25add_reference_points_normPfiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__add_reference_points_normPfiiiS_, .Lfunc_end0-_Z40__device_stub__add_reference_points_normPfiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25add_reference_points_normPfiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25add_reference_points_normPfiiiS_,@object # @_Z25add_reference_points_normPfiiiS_
.section .rodata,"a",@progbits
.globl _Z25add_reference_points_normPfiiiS_
.p2align 3, 0x0
_Z25add_reference_points_normPfiiiS_:
.quad _Z40__device_stub__add_reference_points_normPfiiiS_
.size _Z25add_reference_points_normPfiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25add_reference_points_normPfiiiS_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__add_reference_points_normPfiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25add_reference_points_normPfiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void spaceFilterUpdate(const double *Params, const float *data, const float *U, const bool *UtU, const int *iC, const int *iW, float *dprod, const int *st, const int *id, const int *counter){
volatile __shared__ float sU[32*NrankMax];
volatile __shared__ int iU[32];
float x;
int tid, bid, ind, nt0, i, t, k, Nrank, NT, Nfilt, NchanU, Nchan;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
// just need to do this for all filters that have overlap with id[bid] and st[id]
// tidx still represents time, from -nt0 to nt0
// tidy loops through all filters that have overlap
if (tid<NchanU)
iU[tid] = iC[tid + NchanU * iW[bid]];
__syncthreads();
if (tid<NchanU)
for (k=0;k<Nrank;k++)
sU[tid + k * NchanU] = U[iU[tid] + Nchan * bid + Nchan * Nfilt * k];
__syncthreads();
for(ind=counter[1];ind<counter[0];ind++)
if (UtU[id[ind] + Nfilt *bid]){
t = st[ind] + tid - nt0;
// if this is a hit, threads compute all time offsets
if (t>=0 & t<NT){
for (k=0;k<Nrank;k++){
x = 0.0f;
for(i=0;i<NchanU;i++)
x += sU[i + NchanU*k] * data[t + NT * iU[i]];
dprod[t + NT*bid + k*NT*Nfilt] = x;
}
}
}
} | .file "tmpxft_000bb227_00000000-6_spaceFilterUpdate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.type _Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_, @function
_Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq 280(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movq %rsp, %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_, .-_Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.globl _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.type _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, @function
_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_PKdPKfS2_PKbPKiS6_PfS6_S6_S6_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_, .-_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17spaceFilterUpdatePKdPKfS2_PKbPKiS6_PfS6_S6_S6_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void spaceFilterUpdate(const double *Params, const float *data, const float *U, const bool *UtU, const int *iC, const int *iW, float *dprod, const int *st, const int *id, const int *counter){
volatile __shared__ float sU[32*NrankMax];
volatile __shared__ int iU[32];
float x;
int tid, bid, ind, nt0, i, t, k, Nrank, NT, Nfilt, NchanU, Nchan;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
// just need to do this for all filters that have overlap with id[bid] and st[id]
// tidx still represents time, from -nt0 to nt0
// tidy loops through all filters that have overlap
if (tid<NchanU)
iU[tid] = iC[tid + NchanU * iW[bid]];
__syncthreads();
if (tid<NchanU)
for (k=0;k<Nrank;k++)
sU[tid + k * NchanU] = U[iU[tid] + Nchan * bid + Nchan * Nfilt * k];
__syncthreads();
for(ind=counter[1];ind<counter[0];ind++)
if (UtU[id[ind] + Nfilt *bid]){
t = st[ind] + tid - nt0;
// if this is a hit, threads compute all time offsets
if (t>=0 & t<NT){
for (k=0;k<Nrank;k++){
x = 0.0f;
for(i=0;i<NchanU;i++)
x += sU[i + NchanU*k] * data[t + NT * iU[i]];
dprod[t + NT*bid + k*NT*Nfilt] = x;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void spaceFilterUpdate(const double *Params, const float *data, const float *U, const bool *UtU, const int *iC, const int *iW, float *dprod, const int *st, const int *id, const int *counter){
volatile __shared__ float sU[32*NrankMax];
volatile __shared__ int iU[32];
float x;
int tid, bid, ind, nt0, i, t, k, Nrank, NT, Nfilt, NchanU, Nchan;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
NchanU = (int) Params[10];
nt0 = (int) Params[4];
Nchan = (int) Params[9];
// just need to do this for all filters that have overlap with id[bid] and st[id]
// tidx still represents time, from -nt0 to nt0
// tidy loops through all filters that have overlap
if (tid<NchanU)
iU[tid] = iC[tid + NchanU * iW[bid]];
__syncthreads();
if (tid<NchanU)
for (k=0;k<Nrank;k++)
sU[tid + k * NchanU] = U[iU[tid] + Nchan * bid + Nchan * Nfilt * k];
__syncthreads();
for(ind=counter[1];ind<counter[0];ind++)
if (UtU[id[ind] + Nfilt *bid]){
t = st[ind] + tid - nt0;
// if this is a hit, threads compute all time offsets
if (t>=0 & t<NT){
for (k=0;k<Nrank;k++){
x = 0.0f;
for(i=0;i<NchanU;i++)
x += sU[i + NchanU*k] * data[t + NT * iU[i]];
dprod[t + NT*bid + k*NT*Nfilt] = x;
}
}
}
} |
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